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2  spfd_pilo - Perform SPFD-based placement independent logic optimization.
3     _________________________________________________________________
4
5   spfd_pilo  [-a  <[0,1]>] [-D <depth>] [-f <file>] [-h] [-i <freq>] [-p
6   <percent>] [-r] [-S <n>] [-t <sec>] [-v <n>] [-w <file>]
7
8   This   command   performs   SPFD-based  wire  removal/replacement  and
9   reprogramming  of  combinational circuits mapped to LUT-based FPGAs to
10   reduce the number of wires and nodes in the circuit. The flexibilities
11   in  the  circuit  are  represented  by SPFDs. The following references
12   explain in detail the theory behind SPFDs.
13
14   S.  Yamashita,  H.  Sawada,  and  A.  Nagoya.  A new method to express
15   functional  permissibilities for LUT based FPGAs and its applications.
16   In  International  Conference on Computer Aided Design, pages 254-261,
17   1996.
18
19   Subarnarekha  Sinha  and  Robert K. Brayton. Implementation and use of
20   SPFDs  in optimizaing Boolean networks. In International Conference on
21   Computer Aided Design, 1998.
22
23   Instead  of  computing the flexibilities for every node in the network
24   at once, the algorithm computes the flexibilities for one cluster at a
25   time.  Working  with  clusters  allows  us  to avoid the BDD explosion
26   problem  and  hence, handle large circuits. The SPFDs are computed for
27   the  cluster  and  the  cluster  nodes  are  reprogrammed based on the
28   flexibility derived. Switching activity is used to drive the choice of
29   alternate  function  to  be implemented at the node. In the absence of
30   switching  activity  information, the function that can reduce support
31   of  the  node can be chosen (not implemented). Currently, an arbitrary
32   choice  is made from the flexibilities provided by SPFDs. (-S 0, -S 2,
33   and -S 4)
34
35   Before calling this command a network should be created for the design
36   (use  flatten_hierarchy)  and  MDD  ids  for every node in the network
37   should  be  created  (static_order  -o  all  -n  append, for example).
38   Dynamic  variable  ordering (dvo -e sift) can be enabled to reduce BDD
39   sizes.
40
41   Command options:
42
43   -a <alpha>
44          A   convex   combination  of  switched  capacitance  (switching
45          activity  * fanout count, SWC) and topological depth is used to
46          sort  the fanin nodes during SPFD computation. alpha is between
47          0    and    1.0.    The    cost   function   is   alpha*SWC   +
48          (1.0-alpha)*topDepth. The default value is 0.5.
49
50   -D <depth>
51          A cluster is computed which includes nodes within the specified
52          'depth'. The default value is 1.
53
54   -f <file>
55          File  with simulation vectors. The file format is as below. The
56          format is simple but strict and hence, few checks are made.
57
58          .i c n d o e p f q g r h s i t j u k a l b m
59          .s
60          0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 ;
61          0 1 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 1 ;
62          0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 ;
63          0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 ;
64          The  .i  statement specifies the primary inputs of the network.
65          The  patterns  start  after .s key word. Each vector is a space
66          separated  list of bits and ends in a semi-colon. The length of
67          any  vector  should be equal to the number of signals specified
68          in the .i statement. A line starting with # is a comment.
69
70   -h
71          Print usage.
72
73   -i <freq>
74          Number  of  iterations  after  which  to  update node switching
75          activity. This is valid only if patterns are provided in a file
76          using -f option. The default value is every 5 iterations.
77
78   -m <n>
79          Heuristics to optimize a selected node.
80          0: Reduce the selected node's support.
81          1: Reprogram the selected node.
82          2: Reprogram the selected node's fanin nodes. (default)
83          3: Reduce the selected node's fanout wires.
84
85   -p <percent>
86          The  percentage  of  vectors,  specified via -f option, used to
87          perform  simulation (to update switching activity) during logic
88          optimization. The default value is 10%.
89
90   -r
91          Do  not  reprogram  LUTs  if  no  structural  changes have been
92          performed  with in the cluster, i.e., if no nodes or wires have
93          been  removed  do  not  change the local implementation of LUTs
94          even  if  alternate  implementations  are  availabe  from  SPFD
95          information. The default is to reprogram.
96
97   -S <n>
98          Method used to sort nodes. The nodes are then optimized in that
99          order.
100          0: Random node is chosen. (default)
101          1: If switching activity is available, node with maximum SWC is
102          chosen.
103          2: Node with maximum fanout is chosen.
104          3: If switching activity is available, node with minimum SWC is
105          chosen.
106          4: Node with minimum fanout is chosen.
107
108   -t <sec>
109          Time  in  seconds  allowed  to  complete  the  command.  If the
110          computation time goes above that limit, the process is aborted.
111          The default is no limit.
112
113   -v <n>
114          Verbosity level. Default value is 0.
115
116   -w <file>
117          File to output final optimized circuit.
118            __________________________________________________________
119
120          Last updated on 20050519 10h16
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