source: vis_dev/vis-2.3/models/arbiter/arbiter.v @ 43

Last change on this file since 43 was 28, checked in by cecile, 13 years ago

exemples de test

File size: 2.2 KB
Line 
1typedef enum {A, B, C, X} selection;
2typedef enum {IDLE, READY, BUSY} controller_state;
3typedef enum {NO_REQ, REQ, HAVE_TOKEN} client_state;
4
5module main(clk);
6input clk;
7output ackA, ackB, ackC;
8
9selection wire sel;
10wire active;
11
12assign active = pass_tokenA || pass_tokenB || pass_tokenC;
13
14controller controllerA(clk, reqA, ackA, sel, pass_tokenA, A);
15controller controllerB(clk, reqB, ackB, sel, pass_tokenB, B);
16controller controllerC(clk, reqC, ackC, sel, pass_tokenC, C);
17arbiter arbiter(clk, sel, active);
18
19client clientA(clk, reqA, ackA);
20client clientB(clk, reqB, ackB);
21client clientC(clk, reqC, ackC);
22
23endmodule
24
25module controller(clk, req, ack, sel, pass_token, id);
26input clk, req, sel, id;
27output ack, pass_token;
28
29selection wire sel, id;
30reg ack, pass_token;
31controller_state reg state;
32
33initial state = IDLE;
34initial ack = 0;
35initial pass_token = 1;
36
37wire is_selected;
38assign is_selected = (sel == id);
39
40always @(posedge clk) begin
41  case(state)
42    IDLE:
43      if (is_selected)
44        if (req)
45          begin
46          state = READY;
47          pass_token = 0; /* dropping off this line causes a safety bug */
48          end
49        else
50          pass_token = 1;
51      else
52        pass_token = 0;
53    READY:
54      begin
55      state = BUSY;
56      ack = 1;
57      end
58    BUSY:
59      if (!req)
60        begin
61        state = IDLE;
62        ack = 0;
63        pass_token = 1;
64        end
65  endcase
66end
67endmodule
68
69module arbiter(clk, sel, active);
70input clk, active;
71output sel;
72
73selection wire sel;
74selection reg state;
75
76initial state = A;
77
78assign sel = active ? state: X;
79
80always @(posedge clk) begin
81  if (active)
82    case(state) 
83      A:
84        state = B;
85      B:
86        state = C;
87      C:
88        state = A;
89    endcase
90end
91endmodule
92
93module client(clk, req, ack);
94input clk, ack;
95output req;
96
97reg req;
98client_state reg state;
99
100wire rand_choice;
101
102initial req = 0;
103initial state = NO_REQ;
104
105assign rand_choice = $ND(0,1);
106
107always @(posedge clk) begin
108  case(state)
109    NO_REQ:
110      if (rand_choice)
111        begin
112        req = 1;
113        state = REQ;
114        end
115    REQ:
116      if (ack)
117        state = HAVE_TOKEN;
118    HAVE_TOKEN:
119      if (rand_choice)
120        begin
121        req = 0;
122        state = NO_REQ;
123        end
124  endcase
125end
126endmodule
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