source: vis_dev/vis-2.3/models/counter/counter.v @ 71

Last change on this file since 71 was 28, checked in by cecile, 13 years ago

exemples de test

File size: 620 bytes
Line 
1/* translation of counter.smv to verilog
2
3   Sriram Krishnan 7/93.
4   
5
6
7*/ 
8
9
10
11module counter(clk);
12input clk;
13
14wire out0, out1, out2; 
15
16counter_cell bit0 (clk, 1, out0);
17counter_cell bit1 (clk, out0, out1);
18counter_cell bit2 (clk, out1, out2); 
19endmodule
20
21module counter_cell(clk, carry_in, carry_out); 
22input clk; 
23input carry_in; 
24output carry_out; 
25reg value; 
26
27assign carry_out = value & carry_in;
28
29initial value = 0;
30
31always @(posedge clk) begin
32// value = (value + carry_in) % 2; 
33        case(value)         
34                0: value = carry_in; 
35                1: if (carry_in ==0) 
36                        value = 1;
37                else value = 0;
38        endcase 
39end 
40endmodule
41
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