source:
vis_dev/vis-2.3/models/debug/and2.v
@
33
Last change on this file since 33 was 33, checked in by , 13 years ago | |
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File size: 192 bytes |
Rev | Line | |
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[33] | 1 | module andgate(clk,a,b); |
2 | input clk; | |
3 | input a; | |
4 | input b; | |
5 | ||
6 | reg c; | |
7 | wire x; | |
8 | wire y; | |
9 | ||
10 | initial c = 0; | |
11 | ||
12 | assign x = a & b; | |
13 | assign y = (a)?b:x; | |
14 | ||
15 | always @(posedge clk) | |
16 | begin | |
17 | c = ~x + c; | |
18 | end | |
19 | endmodule | |
20 | ||
21 |
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