module andgate(clk,a,b);
input clk;
input [1:0]a;
input [1:0]b;

reg [1:0]c;
reg [1:0]d;

initial c = 0;
initial d = 0;


always @(posedge clk)
begin
	c = a | b ;
	d = a & b ;
end
endmodule