source: vis_dev/vis-2.3/models/debug/and2.v @ 34

module andgate(clk,a,b);
input clk;
input a;
input b;

reg c;
wire x;
wire y;

initial c = 0;

assign x = a & b;
assign y = (a)?b:x;

always @(posedge clk)
begin
        c = ~x + c;
end
endmodule