source: vis_dev/vis-2.3/models/debug/and2.v @ 43

module andgate(clk,a,b);
input clk;
input a;
input b;

reg c;
reg d;

initial c = 0;
initial d = 0;


always @(posedge clk)
begin
        c = a | b ;
        d = a & b ;
end
endmodule