Rev | Line | |
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[99] | 1 | module cex(ck,j); |
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| 2 | input ck; |
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| 3 | input j; |
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| 4 | wire nd_1; |
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| 5 | wire nd_2; |
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| 6 | wire nd_3; |
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| 7 | |
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| 8 | |
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| 9 | reg [2:0]state; |
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| 10 | reg s2; |
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| 11 | reg s3; |
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| 12 | reg s4; |
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| 13 | |
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| 14 | initial |
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| 15 | begin |
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| 16 | state[0] = 1; |
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| 17 | state[1] = 1; |
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| 18 | state[2] = $ND(0,1); |
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| 19 | if(state == 3) |
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| 20 | s2 = 0; |
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| 21 | else |
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| 22 | s2 = 1; |
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| 23 | s3 = $ND(0,1); |
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| 24 | s4 = $ND(0,1); |
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| 25 | end |
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| 26 | |
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| 27 | assign nd_1 = $ND(0,1); |
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| 28 | assign nd_2 = $ND(0,1); |
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| 29 | assign nd_3 = $ND(0,1); |
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| 30 | always @(posedge ck) |
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| 31 | begin |
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| 32 | case (state) |
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| 33 | 7 : |
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| 34 | if(j == 1) |
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| 35 | begin |
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| 36 | s2 = 1; |
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| 37 | s3 = 0; |
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| 38 | s4 = 0; |
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| 39 | state = 1; |
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| 40 | end |
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| 41 | else |
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| 42 | begin |
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| 43 | s2 = 0; |
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| 44 | s3 = nd_1; |
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| 45 | s4 = nd_2; |
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| 46 | state = 2; |
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| 47 | end |
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| 48 | |
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| 49 | 3: |
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| 50 | begin |
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| 51 | s2 = nd_3; |
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| 52 | s3 = nd_1; |
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| 53 | s4 = nd_2; |
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| 54 | state = 0; |
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| 55 | end |
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| 56 | 1: |
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| 57 | begin |
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| 58 | s2 = nd_3; |
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| 59 | s3 = 0; |
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| 60 | s4 = nd_2; |
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| 61 | state = 4; |
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| 62 | end |
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| 63 | 2: |
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| 64 | begin |
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| 65 | s2 = nd_3; |
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| 66 | s3 = nd_1; |
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| 67 | s4 = nd_2; |
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| 68 | state = 0; |
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| 69 | end |
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| 70 | 4: |
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| 71 | begin |
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| 72 | s2 = nd_3; |
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| 73 | s3 = nd_1; |
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| 74 | s4 = nd_2; |
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| 75 | state = 0; |
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| 76 | end |
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| 77 | 0: |
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| 78 | begin |
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| 79 | s2 = nd_3; |
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| 80 | s3 = nd_1; |
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| 81 | s4 = nd_2; |
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| 82 | state = 0; |
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| 83 | end |
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| 84 | |
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| 85 | |
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| 86 | endcase |
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| 87 | end |
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| 88 | |
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| 89 | endmodule |
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| 90 | |
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| 91 | |
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