module cex(ck,j);
input ck;
input j;
wire nd_1;
wire nd_2;
wire nd_3;


reg [2:0]state;
reg s2;
reg s3;
reg s4;

initial 
  begin
    state[0] = 1;
    state[1] = 1;
    state[2] = $ND(0,1);
    if(state == 3)
      s2 = 0;
    else
      s2 = 1;
  s3 = $ND(0,1);
  s4 = $ND(0,1);
  end

assign nd_1 = $ND(0,1);
assign nd_2 = $ND(0,1);
assign nd_3 = $ND(0,1);
always @(posedge ck)
begin
case (state)
  7 :
    if(j == 1)
    begin
      s2 = 1;
      s3 = 0;
      s4 = 0;
      state = 1;
    end
    else
    begin
      s2 = 0;
      s3 = nd_1;
      s4 = nd_2;
      state = 2;
    end

  3:
    begin
      s2 = nd_3;
      s3 = nd_1;
      s4 = nd_2;
      state = 0;
    end
  1:
    begin
      s2 = nd_3;
      s3 = 0;
      s4 = nd_2;
      state = 4;
    end
  2:
    begin
      s2 = nd_3;
      s3 = nd_1;
      s4 = nd_2;
      state = 0;
    end
  4:
    begin
      s2 = nd_3;
      s3 = nd_1;
      s4 = nd_2;
      state = 0;
    end
  0:
    begin
      s2 = nd_3;
      s3 = nd_1;
      s4 = nd_2;
      state = 0;
    end


endcase
end

endmodule