module simple(ck,i,t);
input ck;
input i;
output t;

wire nd_t;

assign nd_t = $ND(0,1);

reg [1:0]state;
reg t;

initial state = 0;
initial t = $ND(0,1);

always @(posedge ck)
begin
case (state)
  0 :
    begin
      t = (i == 0)?nd_t:1;
      state = (i == 0)?0:1;
    end
  1:
    begin
      t =nd_t;
      state = 2;
    end
   2: begin
      t = nd_t;
      state = 2;
    end
endcase
end

endmodule