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| 2 | ltl_model_check - perform LTL model checking on a flattened network |
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| 3 | _________________________________________________________________ |
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| 4 | |
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| 5 | ltl_model_check [-a <ltl2aut_algorithm>] [-b] [-d <dbg_level>] [-f |
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| 6 | <dbg_file>] [-h] [-i] [-m] [-s] [-t <time_out_period>][-v <verbosity_level>] |
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| 7 | [-A <le_method>] [-D <dc_level>] [-L <lockstep_mode>] [-S <schedule>] [-F] |
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| 8 | [-X] [-Y] [-M] <ltl_file> |
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| 9 | |
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| 10 | Performs LTL model checking on a flattened network. Before calling this |
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| 11 | command, the user should have initialized the design by calling the command |
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| 12 | [1]init_verify. Regardless of the options, no 'false positives' or 'false |
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| 13 | negatives' will occur: the result is correct for the given circuit. |
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| 14 | |
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| 15 | Properties to be verified should be provided as LTL formulae in the file |
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| 16 | ltl_file. Note that the support of any wire referred to in a formula should |
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| 17 | consist only of latches. For the precise syntax of LTL formulas, see the |
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| 18 | [2]VIS CTL and LTL syntax manual. |
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| 19 | |
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| 20 | A formula passes iff it is true for all initial states of the system. |
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| 21 | Therefore, in the presence of multiple initial states, if a formula fails, |
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| 22 | the negation of the formula may also fail. |
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| 23 | |
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| 24 | If a formula does not pass, a (potentially partial) proof of failure |
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| 25 | (referred to as a debug trace) is demonstrated. Fair paths are represented |
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| 26 | by a finite sequence of states (the stem) leading to a fair cycle, i.e. a |
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| 27 | cycle on which there is a state from each fairness condition. Whether |
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| 28 | demostrate the proof or not can be specified (see option -d). |
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| 29 | |
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| 30 | Command options: |
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| 31 | |
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| 32 | -a <ltl2aut_algorithm> |
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| 33 | Specify the algorithm used in LTL formula -> Buechi automaton |
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| 34 | translation. |
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| 35 | |
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| 36 | ltl2aut_algorithm must be one of the following: |
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| 37 | |
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| 38 | 0: GPVW. |
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| 39 | |
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| 40 | 1: GPVW+. |
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| 41 | |
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| 42 | 2: LTL2AUT. |
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| 43 | |
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| 44 | 3: WRING (default). |
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| 45 | |
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| 46 | -b |
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| 47 | Use boolean minimization during the LTL to Automaton translation. |
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| 48 | |
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| 49 | -d <dbg_level> |
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| 50 | Specify whether to demonstrate a counter-example when the system |
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| 51 | fails a formula being checked. |
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| 52 | |
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| 53 | dbg_level must be one of the following: |
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| 54 | |
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| 55 | 0: No debugging performed. dbg_level=0 is the default. |
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| 56 | |
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| 57 | 1: Generate a counter-example (a path to a fair cycle). |
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| 58 | |
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| 59 | -f <dbg_file> |
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| 60 | Write the debugger output to dbg_file. |
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| 61 | |
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| 62 | -h |
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| 63 | Print the command usage. |
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| 64 | |
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| 65 | -i |
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| 66 | Print input values causing transitions between states during |
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| 67 | debugging. Both primary and pseudo inputs are printed. |
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| 68 | |
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| 69 | -m |
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| 70 | Pipe debugger output through the UNIX utility more. |
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| 71 | |
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| 72 | -t <timeOutPeriod> |
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| 73 | Specify the time out period (in seconds) after which the command |
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| 74 | aborts. By default this option is set to infinity. |
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| 75 | |
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| 76 | -s |
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| 77 | Print debug output in the format accepted by the [3]simulate command. |
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| 78 | |
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| 79 | -v <verbosity_level> |
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| 80 | Specify verbosity level. This sets the amount of feedback on CPU |
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| 81 | usage and code status. |
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| 82 | verbosity_level must be one of the following: |
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| 83 | |
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| 84 | 0: No feedback provided. This is the default. |
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| 85 | |
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| 86 | 1: Feedback on code location. |
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| 87 | |
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| 88 | 2: Feedback on code location and CPU usage. |
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| 89 | |
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| 90 | -A <le_method> |
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| 91 | Specify whether the compositional SCC analysis algorithm, Divide and |
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| 92 | Compose (DnC), is enabled for language emptiness checking. The DnC |
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| 93 | algorithm first enumerates fair SCCs in an over-approximated abstract |
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| 94 | model, and then successively refines them in the more concrete |
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| 95 | models. Since non-fair SCCs can be ignored in the more concrete |
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| 96 | models, a potentially large part of the state space are pruned away |
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| 97 | early on when the computations are cheap. |
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| 98 | |
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| 99 | le_method must be one of the following: |
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| 100 | |
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| 101 | 0 : no use of Divide and Compose (Default). |
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| 102 | |
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| 103 | 1 : use Divide and Compose. |
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| 104 | |
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| 105 | -D <dc_level> |
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| 106 | Specify extent to which don't cares are used to simplify MDDs in |
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| 107 | model checking. Don't cares are minterms on which the value taken by |
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| 108 | functions does not affect the computation; potentially, these |
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| 109 | minterms can be used to simplify MDDs and reduce the time taken to |
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| 110 | perform model checking. |
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| 111 | dc_level must be one of the following: |
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| 112 | |
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| 113 | 0 : No don't cares are used. |
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| 114 | |
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| 115 | 1 : Use unreachable states as don't cares. This is the default. |
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| 116 | |
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| 117 | 2 : Use unreachable states as don't cares and in the EU computation, |
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| 118 | use 'frontiers' for image computation. |
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| 119 | |
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| 120 | 3 : First compute an overapproximation of the reachable states |
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| 121 | (ARDC), and use that as the cares set. Use `frontiers' for image |
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| 122 | computation. For help on controlling options for ARDC, look up help |
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| 123 | on the command: [4]print_ardc_options. Refer to Moon, Jang, Somenzi, |
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| 124 | Pixley, Yuan, "Approximate Reachability Don't Cares for {CTL} Model |
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| 125 | Checking", ICCAD98, and to two papers by Cho et al, IEEE TCAD |
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| 126 | December 1996: one is for State Space Decomposition and the other is |
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| 127 | for Approximate FSM Traversal. |
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| 128 | |
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| 129 | -S <schedule> |
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| 130 | Specify schedule for GSH algorithm, which generalizes the Emerson-Lei |
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| 131 | algorithm and is used to compute greatest fixpoints. The choice of |
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| 132 | schedule affects the sequence in which EX and EU operators are |
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| 133 | applied. It makes a difference only when fairness constraints are |
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| 134 | specified. |
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| 135 | <schedule> must be one of the following: |
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| 136 | |
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| 137 | EL : EU and EX operators strictly alternate. This is the default. |
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| 138 | |
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| 139 | EL1 : EX is applied once for every application of all EUs. |
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| 140 | |
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| 141 | EL2 : EX is applied repeatedly after each application of all EUs. |
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| 142 | |
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| 143 | budget : a hybrid of EL and EL2 |
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| 144 | |
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| 145 | random : enabled operators are applied in (pseudo-)random order. |
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| 146 | |
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| 147 | off : GSH is disabled, and the old algorithm is used instead. The old |
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| 148 | algorithm uses the EL , but the termination checks are less |
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| 149 | sophisticated than in GSH. |
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| 150 | |
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| 151 | -F |
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| 152 | Use forward analysis in the computation of the greatest fixpoint. |
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| 153 | This option is incompatible with -d 1 or higher and can only be used |
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| 154 | with -D 1. |
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| 155 | |
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| 156 | -L <lockstep_mode> |
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| 157 | Use the lockstep algorithm, which is based on fair SCC enumeration. |
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| 158 | <lockstep_mode> must be one of the following: |
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| 159 | |
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| 160 | off : Lockstep is disabled. This is the default. Language emptiness |
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| 161 | is checked by computing a hull of the fair SCCs. |
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| 162 | |
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| 163 | on : Lockstep is enabled. |
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| 164 | |
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| 165 | all : Lockstep is enabled; all fair SCCs are enumerated instead of |
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| 166 | terminating as soon as one is found. This can be used to study the |
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| 167 | SCCs of a graph, but it is slower than the default option. |
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| 168 | |
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| 169 | n : (n is a positive integer). Lockstep is enabled and up to n fair |
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| 170 | SCCs are enumerated. This is less expensive than all , but still less |
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| 171 | efficient than on , even when n = 1 . |
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| 172 | |
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| 173 | -X |
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| 174 | Disable strength reduction (use different decision procedures for |
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| 175 | strong, weak, and terminal automaton). Strength reduction is the |
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| 176 | default. Refer to Bloem, Ravi, Somenzi, "Efficient Decision |
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| 177 | Procedures for LTL Model Checking," CAV99. |
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| 178 | |
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| 179 | -Y |
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| 180 | Disable incremental construction of the partition for (MxA). Instead, |
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| 181 | build a new partition from the scratch. Incremental construction of |
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| 182 | the partition is the default. |
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| 183 | |
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| 184 | -Z |
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| 185 | Add arcs into the Buechi automaton by direct simulation relation, to |
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| 186 | heuristically reduce the length of shortest counter-example in model |
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| 187 | checking. Refer to Awedh and Somenze, "Proving More Properties with |
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| 188 | Bounded Model Checking," CAV04. |
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| 189 | |
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| 190 | -M |
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| 191 | Maximize (adding arcs to) Buechi automaton using Direct Simulation. |
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| 192 | |
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| 193 | <ltl_file> |
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| 194 | File containing LTL formulas to be model checked. |
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| 195 | |
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| 196 | Related "set" options: |
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| 197 | |
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| 198 | ltl_change_bracket <yes/no> |
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| 199 | Vl2mv automatically converts "[]" to "<>" in node names, therefore |
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| 200 | CTL* parser does the same thing. However, in some cases a user does |
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| 201 | not want to change node names in CTL* parsing. Then, use this set |
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| 202 | option by giving "no". Default is "yes". |
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| 203 | |
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| 204 | See also commands : model_check, approximate_model_check, |
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| 205 | incremental_ctl_verification |
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| 206 | __________________________________________________________ |
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| 207 | |
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| 208 | Last updated on 20100410 00h02 |
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| 209 | |
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| 210 | References |
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| 211 | |
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| 212 | 1. file://localhost/projects/development/hsv/vis/common/doc/html/init_verifyCmd.html |
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| 213 | 2. file://localhost/projects/development/hsv/vis/common/doc/ctl/ctl/ctl.html |
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| 214 | 3. file://localhost/projects/development/hsv/vis/common/doc/html/simulateCmd.html |
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| 215 | 4. file://localhost/projects/development/hsv/vis/common/doc/html/print_ardc_optionsCmd.html |
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