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| 2 | spfd_pdlo - Perform SPFD-based simultaneous placement and logic optimization. |
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| 3 | _________________________________________________________________ |
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| 4 | |
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| 5 | spfd_pdlo [-D <depth>] [-h] [-n <file>] [-r] [-t <sec>] [-v <n>] [-w <file>] |
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| 6 | net_file arch_file place_file route_file |
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| 7 | |
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| 8 | This command performs SPFD-based combined logic and placement optimization |
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| 9 | of combinational circuits mapped to LUT-based FPGAs to improve circuit area |
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| 10 | and speed. The flexibilities in the circuit are represented by SPFDs. The |
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| 11 | following references explain in detail the theory behind SPFDs. |
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| 12 | |
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| 13 | S. Yamashita, H. Sawada, and A. Nagoya. A new method to express functional |
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| 14 | permissibilities for LUT based FPGAs and its applications. In International |
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| 15 | Conference on Computer Aided Design, pages 254-261, 1996. |
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| 16 | |
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| 17 | Subarnarekha Sinha and Robert K. Brayton. Implementation and use of SPFDs in |
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| 18 | optimizaing Boolean networks. In International Conference on Computer Aided |
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| 19 | Design, 1998. |
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| 20 | |
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| 21 | The command implements a technique that tightly links the logic and |
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| 22 | placement optimization steps. The algorithm is based on simulated annealing. |
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| 23 | Two types of moves, directed towards global reduction in the cost function |
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| 24 | (total wire length), are accepted by the simulated annealing algorithm: (1) |
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| 25 | wire removal/replacement, and (2) swapping of a pair of blocks in the FPGA. |
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| 26 | Feedback from placement is valuable in making an informed choice of a target |
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| 27 | wire during logic optimization moves. The logic optimization steps performed |
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| 28 | are similar to those of spfd_pilo, except that the placement information is |
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| 29 | now used instead of the fanout count. More information on this technique can |
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| 30 | be found in : |
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| 31 | |
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| 32 | Balakrishna Kumthekar and Fabio Somenzi. Power and delay reduction via |
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| 33 | simultaneous logic and placement optimization in FPGAs. In Design, |
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| 34 | Automation and Test in Europe, 2000. |
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| 35 | |
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| 36 | The command produces a placement file which is used by VPR for routing. |
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| 37 | |
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| 38 | This command can be used only if VIS is linked with VPR 4.22 (Versatile |
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| 39 | Place and Route), the FPGA place and route tool [1]VPR, from the University |
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| 40 | of Toronto. Please follow the instructions provided in the release notes to |
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| 41 | use VPR with VIS. You can also contact kumtheka@avanticorp.com if you need |
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| 42 | more help. |
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| 43 | |
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| 44 | Before calling this command a network should be created for the design (use |
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| 45 | flatten_hierarchy) and MDD ids for every node in the network should be |
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| 46 | created (static_order -o all -n append). Dynamic variable ordering (dvo -e |
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| 47 | sift) can be enabled to reduce BDD sizes. |
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| 48 | |
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| 49 | Command options: |
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| 50 | |
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| 51 | -D <depth> |
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| 52 | A cluster is computed which includes nodes within the specified |
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| 53 | 'depth'. The default value is 1. |
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| 54 | |
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| 55 | -n <file> |
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| 56 | File to output the optimized circuit in VPR's .net format. |
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| 57 | |
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| 58 | -r |
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| 59 | Do not reprogram LUTs if no structural changes have been performed |
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| 60 | with in the cluster, i.e., if no nodes or wires have been removed do |
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| 61 | not change the local implementation of LUTs even if alternate |
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| 62 | implementations are availabe from SPFD information. The default is to |
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| 63 | reprogram. |
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| 64 | |
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| 65 | -t <sec> |
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| 66 | Time in seconds allowed to complete the command. If the computation |
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| 67 | time goes above that limit, the process is is aborted. The default is |
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| 68 | no limit. |
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| 69 | |
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| 70 | -v <n> |
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| 71 | Verbosity level. |
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| 72 | |
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| 73 | -w <file> |
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| 74 | File to output final optimized circuit. |
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| 75 | |
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| 76 | The following is needed by VPR: |
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| 77 | |
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| 78 | net_file |
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| 79 | The description of the circuit in the .net format. Logic optimization |
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| 80 | uses the circuit described in .BLIF format whereas VPR needs the same |
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| 81 | circuit described in .net format. VPack (which comes with VPR) |
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| 82 | converts a .BLIF format into a .net format. |
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| 83 | |
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| 84 | arch_file |
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| 85 | Architecture description file for FPGAs. More information can be |
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| 86 | found in VPR's manual. |
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| 87 | |
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| 88 | place_file |
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| 89 | File to dump placement information. |
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| 90 | |
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| 91 | route_file |
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| 92 | File to dump routing information. |
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| 93 | |
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| 94 | Relevant flags to be set by the set command: |
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| 95 | |
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| 96 | spfd_pdlo_logic_move_freq "r1 m1 r2 m2 ..." |
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| 97 | Perform m1 logic moves whenever the rate of acceptance during |
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| 98 | simulated annealing is greater than or equal to r1, and so on. |
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| 99 | r1, r2, r3 ... should be monotonically decreasing, else the |
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| 100 | results would be unpredictable. 0 <= ri <= 1.0. For example: |
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| 101 | |
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| 102 | set spfd_pdlo_logic_move_freq "0.8 0 0.5 5 0.2 10" |
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| 103 | |
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| 104 | In the above logic schedule, zero logic moves per temperature |
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| 105 | will be performed when the rate of acceptance is above 0.8, 5 |
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| 106 | logic moves between 0.8 and 0.5, 10 moves between 0.5 and 0.2. |
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| 107 | As no value is specified for acceptance rate close to 0.0, by |
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| 108 | default, 1 logic move per temperature will be performed. In |
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| 109 | this example it will be 1 logic move between 0.2 and 0.0. The |
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| 110 | quotes around the schedule are necessary. |
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| 111 | |
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| 112 | spfd_repl_rem |
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| 113 | If no, the logic optimization performs only wire removal. If |
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| 114 | yes, both wire replacement and removal are performed. |
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| 115 | |
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| 116 | spfd_pdlo_timing |
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| 117 | If set, use timing driven method to remove or replace wires on |
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| 118 | the critical path. If not set, use bounding box of the wires as |
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| 119 | the cost function. |
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| 120 | |
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| 121 | spfd_pdlo_timing_nodeorwire |
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| 122 | Remove/replace all the wires belonging to the most critical |
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| 123 | net. If not set, attempt to remove/replace only the most |
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| 124 | critical wire. |
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| 125 | |
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| 126 | spfd_pdlo_out_crit_nets_first |
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| 127 | Output the circuit in VPR's .net format with the nets appearing |
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| 128 | in the increasing order of their slack. If not set, the initial |
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| 129 | net order specified in the original circuit's .net file is |
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| 130 | used. The file is specified with -n option. This variable is |
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| 131 | valid only if spfd_pdlo_timing is set. |
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| 132 | |
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| 133 | spfd_pdlo_remap_clb_array |
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| 134 | During logic optimization, due to the removal of nodes in the |
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| 135 | network, the current size of FPGA might be bigger than it is |
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| 136 | necessary. In such cases, if this variable is set, the size of |
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| 137 | the FPGA is reduced to fit the current logic network. |
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| 138 | |
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| 139 | Relevant flags that are options to VPR: |
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| 140 | |
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| 141 | For detailed information on the following options please refer to the |
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| 142 | manual that accompanies VPR source distribution. |
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| 143 | |
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| 144 | vpr_nodisp |
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| 145 | vpr_fix_pins |
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| 146 | vpr_nx |
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| 147 | vpr_ny |
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| 148 | vpr_fast |
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| 149 | vpr_init_t |
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| 150 | vpr_alpha_t |
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| 151 | vpr_exit_t |
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| 152 | vpr_inner_num |
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| 153 | vpr_seet |
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| 154 | vpr_place_cost_exp |
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| 155 | vpr_place_chan_width |
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| 156 | __________________________________________________________ |
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| 157 | |
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| 158 | Last updated on 20100410 00h02 |
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| 159 | |
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| 160 | References |
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| 161 | |
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| 162 | 1. http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html |
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