source: vis_dev/vis-2.3/share/help/spfd_pdloCmd.txt @ 94

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2  spfd_pdlo - Perform SPFD-based simultaneous placement and logic optimization.
3     _________________________________________________________________
4
5   spfd_pdlo [-D <depth>] [-h] [-n <file>] [-r] [-t <sec>] [-v <n>] [-w <file>]
6   net_file arch_file place_file route_file
7
8   This command performs SPFD-based combined logic and placement optimization
9   of combinational circuits mapped to LUT-based FPGAs to improve circuit area
10   and speed. The flexibilities in the circuit are represented by SPFDs. The
11   following references explain in detail the theory behind SPFDs.
12
13   S. Yamashita, H. Sawada, and A. Nagoya. A new method to express functional
14   permissibilities for LUT based FPGAs and its applications. In International
15   Conference on Computer Aided Design, pages 254-261, 1996.
16
17   Subarnarekha Sinha and Robert K. Brayton. Implementation and use of SPFDs in
18   optimizaing Boolean networks. In International Conference on Computer Aided
19   Design, 1998.
20
21   The  command  implements  a technique that tightly links the logic and
22   placement optimization steps. The algorithm is based on simulated annealing.
23   Two types of moves, directed towards global reduction in the cost function
24   (total wire length), are accepted by the simulated annealing algorithm: (1)
25   wire removal/replacement, and (2) swapping of a pair of blocks in the FPGA.
26   Feedback from placement is valuable in making an informed choice of a target
27   wire during logic optimization moves. The logic optimization steps performed
28   are similar to those of spfd_pilo, except that the placement information is
29   now used instead of the fanout count. More information on this technique can
30   be found in :
31
32   Balakrishna Kumthekar and Fabio Somenzi. Power and delay reduction via
33   simultaneous  logic  and  placement  optimization in FPGAs. In Design,
34   Automation and Test in Europe, 2000.
35
36   The command produces a placement file which is used by VPR for routing.
37
38   This command can be used only if VIS is linked with VPR 4.22 (Versatile
39   Place and Route), the FPGA place and route tool [1]VPR, from the University
40   of Toronto. Please follow the instructions provided in the release notes to
41   use VPR with VIS. You can also contact kumtheka@avanticorp.com if you need
42   more help.
43
44   Before calling this command a network should be created for the design (use
45   flatten_hierarchy) and MDD ids for every node in the network should be
46   created (static_order -o all -n append). Dynamic variable ordering (dvo -e
47   sift) can be enabled to reduce BDD sizes.
48
49   Command options:
50
51   -D <depth>
52          A cluster is computed which includes nodes within the specified
53          'depth'. The default value is 1.
54
55   -n <file>
56          File to output the optimized circuit in VPR's .net format.
57
58   -r
59          Do not reprogram LUTs if no structural changes have been performed
60          with in the cluster, i.e., if no nodes or wires have been removed do
61          not  change  the local implementation of LUTs even if alternate
62          implementations are availabe from SPFD information. The default is to
63          reprogram.
64
65   -t <sec>
66          Time in seconds allowed to complete the command. If the computation
67          time goes above that limit, the process is is aborted. The default is
68          no limit.
69
70   -v <n>
71          Verbosity level.
72
73   -w <file>
74          File to output final optimized circuit.
75
76   The following is needed by VPR:
77
78   net_file
79          The description of the circuit in the .net format. Logic optimization
80          uses the circuit described in .BLIF format whereas VPR needs the same
81          circuit  described in .net format. VPack (which comes with VPR)
82          converts a .BLIF format into a .net format.
83
84   arch_file
85          Architecture description file for FPGAs. More information can be
86          found in VPR's manual.
87
88   place_file
89          File to dump placement information.
90
91   route_file
92          File to dump routing information.
93
94          Relevant flags to be set by the set command:
95
96        spfd_pdlo_logic_move_freq "r1 m1 r2 m2 ..."
97                Perform m1 logic moves whenever the rate of acceptance during
98                simulated annealing is greater than or equal to r1, and so on.
99                r1, r2, r3 ... should be monotonically decreasing, else the
100                results would be unpredictable. 0 <= ri <= 1.0. For example:
101
102                set spfd_pdlo_logic_move_freq "0.8 0 0.5 5 0.2 10"
103
104                In the above logic schedule, zero logic moves per temperature
105                will be performed when the rate of acceptance is above 0.8, 5
106                logic moves between 0.8 and 0.5, 10 moves between 0.5 and 0.2.
107                As no value is specified for acceptance rate close to 0.0, by
108                default, 1 logic move per temperature will be performed. In
109                this example it will be 1 logic move between 0.2 and 0.0. The
110                quotes around the schedule are necessary.
111
112        spfd_repl_rem
113                If no, the logic optimization performs only wire removal. If
114                yes, both wire replacement and removal are performed.
115
116        spfd_pdlo_timing
117                If set, use timing driven method to remove or replace wires on
118                the critical path. If not set, use bounding box of the wires as
119                the cost function.
120
121        spfd_pdlo_timing_nodeorwire
122                Remove/replace all the wires belonging to the most critical
123                net.  If not set, attempt to remove/replace only the most
124                critical wire.
125
126        spfd_pdlo_out_crit_nets_first
127                Output the circuit in VPR's .net format with the nets appearing
128                in the increasing order of their slack. If not set, the initial
129                net order specified in the original circuit's .net file is
130                used. The file is specified with -n option. This variable is
131                valid only if spfd_pdlo_timing is set.
132
133        spfd_pdlo_remap_clb_array
134                During logic optimization, due to the removal of nodes in the
135                network, the current size of FPGA might be bigger than it is
136                necessary. In such cases, if this variable is set, the size of
137                the FPGA is reduced to fit the current logic network.
138
139          Relevant flags that are options to VPR:
140
141          For detailed information on the following options please refer to the
142          manual that accompanies VPR source distribution.
143
144        vpr_nodisp
145        vpr_fix_pins
146        vpr_nx
147        vpr_ny
148        vpr_fast
149        vpr_init_t
150        vpr_alpha_t
151        vpr_exit_t
152        vpr_inner_num
153        vpr_seet
154        vpr_place_cost_exp
155        vpr_place_chan_width
156            __________________________________________________________
157
158          Last updated on 20100410 00h02
159
160References
161
162   1. http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html
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