source: vis_dev/vis-2.3/share/help/spfd_piloCmd.txt @ 64

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2  spfd_pilo - Perform SPFD-based placement independent logic optimization.
3     _________________________________________________________________
4
5   spfd_pilo  [-a  <[0,1]>] [-D <depth>] [-f <file>] [-h] [-i <freq>] [-p
6   <percent>] [-r] [-S <n>] [-t <sec>] [-v <n>] [-w <file>]
7
8   This command performs SPFD-based wire removal/replacement and reprogramming
9   of combinational circuits mapped to LUT-based FPGAs to reduce the number of
10   wires  and  nodes in the circuit. The flexibilities in the circuit are
11   represented by SPFDs. The following references explain in detail the theory
12   behind SPFDs.
13
14   S. Yamashita, H. Sawada, and A. Nagoya. A new method to express functional
15   permissibilities for LUT based FPGAs and its applications. In International
16   Conference on Computer Aided Design, pages 254-261, 1996.
17
18   Subarnarekha Sinha and Robert K. Brayton. Implementation and use of SPFDs in
19   optimizaing Boolean networks. In International Conference on Computer Aided
20   Design, 1998.
21
22   Instead of computing the flexibilities for every node in the network at
23   once, the algorithm computes the flexibilities for one cluster at a time.
24   Working with clusters allows us to avoid the BDD explosion problem and
25   hence, handle large circuits. The SPFDs are computed for the cluster and the
26   cluster nodes are reprogrammed based on the flexibility derived. Switching
27   activity is used to drive the choice of alternate function to be implemented
28   at the node. In the absence of switching activity information, the function
29   that  can  reduce support of the node can be chosen (not implemented).
30   Currently, an arbitrary choice is made from the flexibilities provided by
31   SPFDs. (-S 0, -S 2, and -S 4)
32
33   Before calling this command a network should be created for the design (use
34   flatten_hierarchy) and MDD ids for every node in the network should be
35   created (static_order -o all -n append, for example). Dynamic variable
36   ordering (dvo -e sift) can be enabled to reduce BDD sizes.
37
38   Command options:
39
40   -a <alpha>
41          A convex combination of switched capacitance (switching activity *
42          fanout count, SWC) and topological depth is used to sort the fanin
43          nodes during SPFD computation. alpha is between 0 and 1.0. The cost
44          function is alpha*SWC + (1.0-alpha)*topDepth. The default value is
45          0.5.
46
47   -D <depth>
48          A cluster is computed which includes nodes within the specified
49          'depth'. The default value is 1.
50
51   -f <file>
52          File with simulation vectors. The file format is as below. The format
53          is simple but strict and hence, few checks are made.
54
55          .i c n d o e p f q g r h s i t j u k a l b m
56          .s
57          0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 ;
58          0 1 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 1 ;
59          0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 ;
60          0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 ;
61          The .i statement specifies the primary inputs of the network. The
62          patterns start after .s key word. Each vector is a space separated
63          list of bits and ends in a semi-colon. The length of any vector
64          should  be  equal  to the number of signals specified in the .i
65          statement. A line starting with # is a comment.
66
67   -h
68          Print usage.
69
70   -i <freq>
71          Number of iterations after which to update node switching activity.
72          This  is valid only if patterns are provided in a file using -f
73          option. The default value is every 5 iterations.
74
75   -m <n>
76          Heuristics to optimize a selected node.
77          0: Reduce the selected node's support.
78          1: Reprogram the selected node.
79          2: Reprogram the selected node's fanin nodes. (default)
80          3: Reduce the selected node's fanout wires.
81
82   -p <percent>
83          The percentage of vectors, specified via -f option, used to perform
84          simulation (to update switching activity) during logic optimization.
85          The default value is 10%.
86
87   -r
88          Do not reprogram LUTs if no structural changes have been performed
89          with in the cluster, i.e., if no nodes or wires have been removed do
90          not  change  the local implementation of LUTs even if alternate
91          implementations are availabe from SPFD information. The default is to
92          reprogram.
93
94   -S <n>
95          Method used to sort nodes. The nodes are then optimized in that
96          order.
97          0: Random node is chosen. (default)
98          1: If switching activity is available, node with maximum SWC is
99          chosen.
100          2: Node with maximum fanout is chosen.
101          3: If switching activity is available, node with minimum SWC is
102          chosen.
103          4: Node with minimum fanout is chosen.
104
105   -t <sec>
106          Time in seconds allowed to complete the command. If the computation
107          time goes above that limit, the process is aborted. The default is no
108          limit.
109
110   -v <n>
111          Verbosity level. Default value is 0.
112
113   -w <file>
114          File to output final optimized circuit.
115            __________________________________________________________
116
117          Last updated on 20100410 00h02
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