1 | .\" SCCSID: @(#)verilog.1 8.1 9/11/90 |
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2 | .TH vl2mv 1 |
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3 | .SH Name |
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4 | vl2mv \- Compile the synthesizable subset of Verilog Programs into BLIF-MV |
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5 | .SH Syntax |
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6 | .B vl2mv [\fIoptions\fR] filename |
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7 | .SH Description |
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8 | The |
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9 | .B vl2mv |
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10 | command compiles programs in the synthesizable subset of Verilog into |
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11 | BLIF-MV. It is not able to handle full set Verilog language now due to |
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12 | its dynamic nature. The output file, if not specified, is inferred by |
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13 | removing everything after the last . and appending mv. |
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14 | .SH Options |
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15 | .IP \fB\-a\fR 0.3i |
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16 | Use .subcircuits/.macros to abstract all behavioral operators. All integers |
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17 | and bit vectors are abstracted as symbolic variables and expanded in |
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18 | subcircuits using \fI.bundle\fR construct. |
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19 | .IP \fB\-A\fR 0.3i |
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20 | Send output to \fBstdout\fR. |
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21 | .IP \fB\-c\fR 0.3i |
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22 | Explicit clocking scheme, clocking wires and auxiliary circuits are |
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23 | generated in resulting BLIF-MV file in order to emulate edge triggerred |
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24 | latches and level sensitive latches. |
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25 | .IP \fB\-g\fR 0.3i |
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26 | Put source debugging information in the BLIF-MV target. All debugging |
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27 | information begins with '##'. |
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28 | .IP \fB\-h\fR 0.3i |
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29 | Generate HSIS system calls instead of real subcircuits/flattened tables for |
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30 | \fIand\fR, \fInand\fR, \fIor\fR, \fInor\fR, \fIxor\fR, \fIxnor\fR, |
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31 | \fIadd\fR, and \fIminus\fR. |
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32 | .IP \fB\-m\fR 0.3i |
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33 | Use .macro in place of abstracted behavioral operators. This option is |
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34 | effective only when \fB\-a\fR is provided. |
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35 | .IP \fB\-o\ \fIfile\fR 0.3i |
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36 | Send output to \fIfile.\fR |
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37 | .IP \fB\-p\fR 0.3i |
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38 | Dump out the internal representations for input programs. |
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39 | .IP \fB\-S\fR 0.3i |
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40 | Do not use set notation in BLIF-MV. |
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41 | In general, set abbreviation notation (=, .default, []) in BLIF-MV can result |
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42 | in a more compact target file. |
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43 | .IP \fB\-T\ \fIwidth\fR 0.3i |
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44 | Decompose tables for nonblocking assignments when number of control |
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45 | variables plus that of temporary variables for assignments is greater than |
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46 | \fIwidth\fR. |
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47 | |
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48 | .SH Authors |
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49 | Szu-Tsung Cheng, Gary York |
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50 | .SH See Also |
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51 | For the synthesizable subset of Verilog and how it is compiled into BLIF-MV, |
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52 | please refer to the related documentations and examples. |
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