source: vis_dev/vl2mv-2.3/vl2mv.1 @ 106

Last change on this file since 106 was 18, checked in by cecile, 13 years ago

vl2mv added

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1.\" SCCSID: @(#)verilog.1     8.1     9/11/90
2.TH vl2mv 1
3.SH Name
4vl2mv \- Compile the synthesizable subset of Verilog Programs into BLIF-MV
5.SH Syntax
6.B vl2mv [\fIoptions\fR] filename
7.SH Description
8The
9.B vl2mv
10command compiles programs in the synthesizable subset of Verilog into
11BLIF-MV. It is not able to handle full set Verilog language now due to
12its dynamic nature. The output file, if not specified, is inferred by
13removing everything after the last . and appending mv.
14.SH Options
15.IP \fB\-a\fR 0.3i
16Use .subcircuits/.macros to abstract all behavioral operators. All integers
17and bit vectors are abstracted as symbolic variables and expanded in
18subcircuits using \fI.bundle\fR construct.
19.IP \fB\-A\fR 0.3i
20Send output to \fBstdout\fR.
21.IP \fB\-c\fR 0.3i
22Explicit clocking scheme, clocking wires and auxiliary circuits are
23generated in resulting BLIF-MV file in order to emulate edge triggerred
24latches and level sensitive latches.
25.IP \fB\-g\fR 0.3i
26Put source debugging information in the BLIF-MV target. All debugging
27information begins with '##'.
28.IP \fB\-h\fR 0.3i
29Generate HSIS system calls instead of real subcircuits/flattened tables for
30\fIand\fR, \fInand\fR, \fIor\fR, \fInor\fR, \fIxor\fR, \fIxnor\fR,
31\fIadd\fR, and \fIminus\fR.
32.IP \fB\-m\fR 0.3i
33Use .macro in place of abstracted behavioral operators. This option is
34effective only when \fB\-a\fR is provided.
35.IP \fB\-o\ \fIfile\fR 0.3i
36Send output to \fIfile.\fR
37.IP \fB\-p\fR 0.3i
38Dump out the internal representations for input programs.
39.IP \fB\-S\fR 0.3i
40Do not use set notation in BLIF-MV.
41In general, set abbreviation notation (=, .default, []) in BLIF-MV can result
42in a more compact target file.
43.IP \fB\-T\ \fIwidth\fR 0.3i
44Decompose tables for nonblocking assignments when number of control
45variables plus that of temporary variables for assignments is greater than
46\fIwidth\fR.
47
48.SH Authors
49Szu-Tsung Cheng, Gary York
50.SH See Also
51For the synthesizable subset of Verilog and how it is compiled into BLIF-MV,
52please refer to the related documentations and examples.
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