Index: vis_dev/vis-2.1/INSTALL =================================================================== --- vis_dev/vis-2.1/INSTALL (revision 11) +++ vis_dev/vis-2.1/INSTALL (revision 11) @@ -0,0 +1,176 @@ +Basic Installation +================== + + These are generic installation instructions. + + The `configure' shell script attempts to guess correct values for +various system-dependent variables used during compilation. It uses +those values to create a `Makefile' in each directory of the package. +It may also create one or more `.h' files containing system-dependent +definitions. Finally, it creates a shell script `config.status' that +you can run in the future to recreate the current configuration, a file +`config.cache' that saves the results of its tests to speed up +reconfiguring, and a file `config.log' containing compiler output +(useful mainly for debugging `configure'). + + If you need to do unusual things to compile the package, please try +to figure out how `configure' could check whether to do them, and mail +diffs or instructions to the address given in the `README' so they can +be considered for the next release. If at some point `config.cache' +contains results you don't want to keep, you may remove or edit it. + + The file `configure.in' is used to create `configure' by a program +called `autoconf'. You only need `configure.in' if you want to change +it or regenerate `configure' using a newer version of `autoconf'. + +The simplest way to compile this package is: + + 1. `cd' to the directory containing the package's source code and type + `./configure' to configure the package for your system. If you're + using `csh' on an old version of System V, you might need to type + `sh ./configure' instead to prevent `csh' from trying to execute + `configure' itself. + + Running `configure' takes awhile. While running, it prints some + messages telling which features it is checking for. + + 2. Type `make' to compile the package. + + 3. Optionally, type `make check' to run any self-tests that come with + the package. + + 4. Type `make install' to install the programs and any data files and + documentation. + + 5. You can remove the program binaries and object files from the + source code directory by typing `make clean'. To also remove the + files that `configure' created (so you can compile the package for + a different kind of computer), type `make distclean'. There is + also a `make maintainer-clean' target, but that is intended mainly + for the package's developers. If you use it, you may have to get + all sorts of other programs in order to regenerate files that came + with the distribution. + +Compilers and Options +===================== + + Some systems require unusual options for compilation or linking that +the `configure' script does not know about. You can give `configure' +initial values for variables by setting them in the environment. Using +a Bourne-compatible shell, you can do that on the command line like +this: + CC=c89 CFLAGS=-O2 LIBS=-lposix ./configure + +Or on systems that have the `env' program, you can do it like this: + env CPPFLAGS=-I/usr/local/include LDFLAGS=-s ./configure + +Compiling For Multiple Architectures +==================================== + + You can compile the package for more than one kind of computer at the +same time, by placing the object files for each architecture in their +own directory. To do this, you must use a version of `make' that +supports the `VPATH' variable, such as GNU `make'. `cd' to the +directory where you want the object files and executables to go and run +the `configure' script. `configure' automatically checks for the +source code in the directory that `configure' is in and in `..'. + + If you have to use a `make' that does not supports the `VPATH' +variable, you have to compile the package for one architecture at a time +in the source code directory. After you have installed the package for +one architecture, use `make distclean' before reconfiguring for another +architecture. + +Installation Names +================== + + By default, `make install' will install the package's files in +`/usr/local/bin', `/usr/local/man', etc. You can specify an +installation prefix other than `/usr/local' by giving `configure' the +option `--prefix=PATH'. + + You can specify separate installation prefixes for +architecture-specific files and architecture-independent files. If you +give `configure' the option `--exec-prefix=PATH', the package will use +PATH as the prefix for installing programs and libraries. +Documentation and other data files will still use the regular prefix. + + If the package supports it, you can cause programs to be installed +with an extra prefix or suffix on their names by giving `configure' the +option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'. + +Optional Features +================= + + Some packages pay attention to `--enable-FEATURE' options to +`configure', where FEATURE indicates an optional part of the package. +They may also pay attention to `--with-PACKAGE' options, where PACKAGE +is something like `gnu-as' or `x' (for the X Window System). The +`README' should mention any `--enable-' and `--with-' options that the +package recognizes. + + For packages that use the X Window System, `configure' can usually +find the X include and library files automatically, but if it doesn't, +you can use the `configure' options `--x-includes=DIR' and +`--x-libraries=DIR' to specify their locations. + +Specifying the System Type +========================== + + There may be some features `configure' can not figure out +automatically, but needs to determine by the type of host the package +will run on. Usually `configure' can figure that out, but if it prints +a message saying it can not guess the host type, give it the +`--host=TYPE' option. TYPE can either be a short name for the system +type, such as `sun4', or a canonical name with three fields: + CPU-COMPANY-SYSTEM + +See the file `config.sub' for the possible values of each field. If +`config.sub' isn't included in this package, then this package doesn't +need to know the host type. + + If you are building compiler tools for cross-compiling, you can also +use the `--target=TYPE' option to select the type of system they will +produce code for and the `--build=TYPE' option to select the type of +system on which you are compiling the package. + +Sharing Defaults +================ + + If you want to set default values for `configure' scripts to share, +you can create a site shell script called `config.site' that gives +default values for variables like `CC', `cache_file', and `prefix'. +`configure' looks for `PREFIX/share/config.site' if it exists, then +`PREFIX/etc/config.site' if it exists. Or, you can set the +`CONFIG_SITE' environment variable to the location of the site script. +A warning: not all `configure' scripts look for a site script. + +Operation Controls +================== + + `configure' recognizes the following options to control how it +operates. + +`--cache-file=FILE' + Use and save the results of the tests in FILE instead of + `./config.cache'. Set FILE to `/dev/null' to disable caching, for + debugging `configure'. + +`--help' + Print a summary of the options to `configure', and exit. + +`--quiet' +`--silent' +`-q' + Do not print messages saying which checks are being made. + +`--srcdir=DIR' + Look for the package's source code in directory DIR. Usually + `configure' can determine that directory automatically. + +`--version' + Print the version of Autoconf used to generate the `configure' + script, and exit. + +`configure' also accepts some other, not widely useful, options. + Index: vis_dev/vis-2.1/Makefile.in =================================================================== --- vis_dev/vis-2.1/Makefile.in (revision 11) +++ vis_dev/vis-2.1/Makefile.in (revision 11) @@ -0,0 +1,1166 @@ +# FileName [ Makefile.in ] +# +# PackageName [ vis ] +# +# Synopsis [ Package-wide Makefile ] +# +# Description [ This file requires GNU's make program. +# Run "configure" to generate the Makefile, or use +# "config.status" (created by configure) to regenerate the +# Makefile after modifying this file. +# +# Type "gmake help" for help about valid targets. +# ] +# +# SeeAlso [ configure.in ] +# +# Author [ Stephen Edwards +# Tom Shiple ] +# +# Copyright [ +# Copyright (c) 1994-1996 The Regents of the Univ. of California. +# All rights reserved. +# +# Permission is hereby granted, without written agreement and without license +# or royalty fees, to use, copy, modify, and distribute this software and its +# documentation for any purpose, provided that the above copyright notice and +# the following two paragraphs appear in all copies of this software. +# +# IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR +# DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT +# OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF +# CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND +# FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN +# "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO PROVIDE +# MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. +# ] +# +# Revision [$Id: Makefile.in,v 1.124 2005/05/18 20:59:38 fabio Exp $] + +# Default target: + +.PHONY : default + +default : all + +#---------------------------------------------------------------------- +# The list of packages to compile. Change this if you are only compiling +# part of VIS +#---------------------------------------------------------------------- + +#PKGS = tst +PKGS = $(ALL_PKGS) + +# The name of the BDD package to use + +BDDPKG = @BDDLIB@ + +#---------------------------------------------------------------------- +# This Makefile is designed for three different situations: +# +# 1. Single platform build (the default) +# +# All packages listed in the PKGS variable +# local_srcdir = master_srcdir = . +# +# 2. Multi-platform build +# +# All packages listed in the PKGS variable +# local_srcdir = master_srcdir = /where/source/files/reside +# +# 3. Multi-platform development (used at Berkeley) +# +# Packages under development listed in the PKGS variable +# local_srcdir = ../common +# master_srcdir = /projects/vis/vis-devel/common +# +# User has a directory structure that looks like +# +# vis/common/src/ Subdirectory with package source files +# under development. +# +# vis/$PLATFORM/ Subdirectory with this Makefile. +# Compilation is invoked here. +# +# $PLATFORM is something like "alpha-g" (DEC Alpha, debug version) +# +#---------------------------------------------------------------------- + +#---------------------------------------------------------------------- +# Information about all the packages +#---------------------------------------------------------------------- + +ALL_PKGS = abs amc baig bmc cmd ctlp ctlsp eqv fsm rob grab hrc imc img io ltl \ + maig mark mc mvf mvfaig ntk ntm ntmaig ord part puresat rst res restr \ + rt sat sim spfd synth tbl truesim tst var vm +# Generate the list of all packages NOT in the PKGS list + +MISSING_PKGS = $(filter-out $(PKGS), $(ALL_PKGS)) + +# All the BDD packages +BDDPKGS = cu cmu cal + +#---------------------------------------------------------------------- +# For safety +#---------------------------------------------------------------------- + +SHELL = /bin/sh +.SUFFIXES: + +#---------------------------------------------------------------------- +# The name of the product and its version +#---------------------------------------------------------------------- + +PRODUCT = vis +VERSION = 2.1 + +# Compile and version information +# +# CUR_DATE and CUR_VER are strings surrounded by double quotes that contain +# spaces, e.g., "vis release 2.0" + +VERDATE := -DCUR_DATE="\"$(shell date)\"" -DCUR_VER="\"$(PRODUCT) release $(VERSION)\"" + +#---------------------------------------------------------------------- +# Source directories +#---------------------------------------------------------------------- + +# Directory containing master source files. This directory is searched +# for packages NOT listed in the PKGS variable. Defaults to "." +# Override with ./configure --srcdir= +master_srcdir = @srcdir@ + +# Directory containing local source files. This directory is searched +# for packages listed in the PKGS variable. Defaults to the master source +# directory (see above). +# Override with ./configure --with-local-srcdir= +local_srcdir = @local_srcdir@ + +#---------------------------------------------------------------------- +# Directories used while building +#---------------------------------------------------------------------- + +# Directories to search for glu .h files (space-separated) +gluincdir1 = @gluincdir@ + +# Directories to search for libglu.a (space-separated) +glulibdir1 = @glulibdir@ + +# Directory where object files will be placed during the build +objectdir = obj + +# Directory where links to header files will be placed during the build +headerdir = $(local_srcdir)/include + +# Directories where documentation will be placed during the build +docdir = $(master_srcdir)/doc +htmldocdir = $(docdir)/html +txtdocdir = $(docdir)/txt +helpdir = $(master_srcdir)/share/help + +# Directories to search for VIS library files +# Set by ./configure --with-vis-libdir= +vislibdir = @vislibdir@ + +# Full path of platform-independent library files during the build. +# Using this variable as an environment variable allows VIS to work +# before it is installed. +# +# Note: This is NOT where they will be installed + +VIS_LIBRARY_PATH = $(shell cd $(master_srcdir)/share ; pwd) + +#---------------------------------------------------------------------- +# Defaults for GLU library and header files +#---------------------------------------------------------------------- + +ifndef gluincdir1 + gluincdir = ../glu-$(VERSION)/include ../../glu-$(VERSION)/include +else + gluincdir = $(gluincdir1) $(gluincdir1)/../src/cudd +endif + +ifndef glulibdir1 + glulibdir = ../glu-$(VERSION) ../../glu-$(VERSION) +else + glulibdir = $(glulibdir1) +endif + +#---------------------------------------------------------------------- +# Installation names and directories +#---------------------------------------------------------------------- + +# Name of the library to create +LIBRARY = lib$(PRODUCT).a + +# Name of the man page +MANPAGE = vis.1 + +# Directory in which to install architecture-independent files +# Set by ./configure --prefix=... +prefix = @prefix@ + +# Directory in which to install architecture-dependent files +# Set by ./configure --exec-prefix=... +exec_prefix = @exec_prefix@ + +# Directory in which to install binaries +bindir = $(exec_prefix)/bin + +# Directory in which to install libraries +libdir = $(exec_prefix)/lib + +# Directory in which to install headers +includedir = $(prefix)/include + +# Directory in which to install architecture-independent library files +datadir = $(prefix)/share/vis + +# Directory for the man page +mandir = $(prefix)/man/man1 + +#---------------------------------------------------------------------- +# The following are set by the configure script +#---------------------------------------------------------------------- + +AC_FLAGS = @DEFS@ +LIBDIRS = @LIBDIRS@ +RANLIB = @RANLIB@ +CC = @CC@ +LINKER = @LINKER@ +LDFLAGS = @LDFLAGS@ +CPPFLAGS = @CPPFLAGS@ +# +# Define the linker for the executable with "memory_profile" activated +# +PLINKER = @PLINKER@ +CFLAGS = @CFLAGS@ +OTHERLIBS = -lm @LIBS@ @LEXLIB@ +YACC = @YACC@ +LEX = @LEX@ +NAWK = @AWK@ +INSTALL = @INSTALL@ +INSTALL_PROGRAM = @INSTALL_PROGRAM@ +INSTALL_DATA = @INSTALL_DATA@ +AR = @AR@ +ZCHAFF= @ZCHAFF@ +#---------------------------------------------------------------------- +# Examples included in the distribution +#---------------------------------------------------------------------- + +# Each example is declared only once. If some checking through is done +# make check, then it is declared in one of CHECK_COMMON_EXAMPLES, +# CHECK_EXAMPLES_cu, CHECK_EXAMPLES_cmu or CHECK_EXAMPLES_cu. If the example +# is just being added to the examples directory in VIS, then add it here. + +EXAMPLES = $(CHECK_COMMON_EXAMPLES) $(CHECK_EXAMPLES_cu) \ + $(CHECK_EXAMPLES_cmu) $(CHECK_EXAMPLES_cal) \ + bpb eight_queens minmax ping_pong_new rcnum + +# The "interesting" example files are anything in the examples subdirectories +# except the RCS subdirectories +# +# This is a rather messy way to look for filenames in the local_srcdir, +# then remove the local_srcdir prefix + +EXAMPLEFILES = $(patsubst $(local_srcdir)/%, %, \ + $(filter-out %RCS, $(foreach example, $(EXAMPLES), \ + $(wildcard $(local_srcdir)/examples/$(example)/*)))) + +# $(pathsubst $(local_srcdir)/%, %, \ +# $(filter-out %/RCS, $(foreach example, $(EXAMPLES), \ + + +#---------------------------------------------------------------------- +# Distributed files in the doc directory +#---------------------------------------------------------------------- + +DOCUMENTATION = blifmv.ps ctl.ps vis_user.ps two_phase.ps + +#---------------------------------------------------------------------- +# Files in the share directory +#---------------------------------------------------------------------- + +SHAREFILES = master.visrc ioBlifToMv.nawk ioBlifToMvForIncremental.nawk\ + script_compute_reach.simple script_compute_reach.robust\ + script_model_check.simple script_model_check.robust\ + script_fair_model_check.simple script_fair_model_check.robust\ + script_lang_empty_check.simple script_lang_empty_check.robust\ + script_generic.simple script_generic.robust\ + sislib.mv createfunctionmap memoryaccount visdbgpp + +HELPFILES = $(notdir $(wildcard $(helpdir)/*.txt)) + +#---------------------------------------------------------------------- +# Include the make templates from all the packages +# +# Each of these templates (e.g., array/array.make) should contains lines +# of the form +# +# CSRC += source1.c source2.c +# HEADERS += header1.h header2.h +# LEXSRC += file1.l +# YACCSRC += file2.y +# GENERATEDCSRC += ctlpLex.c ctlpRead.c +#---------------------------------------------------------------------- + +MAKEINCLUDES = $(foreach package, $(PKGS), \ + $(local_srcdir)/src/$(package)/$(package).make) + +include $(MAKEINCLUDES) + +OBJECTS = $(addprefix $(objectdir)/,$(GENERATEDCSRC:.c=.o) $(CSRC:.c=.o)) + +#---------------------------------------------------------------------- +# Include the dependency files from each package directory. +# A missing dependency file does not produce an error. +#---------------------------------------------------------------------- + +DEPENDENCIES = $(foreach package, $(PKGS), \ + $(local_srcdir)/src/$(package)/$(package).d) + +-include $(DEPENDENCIES) + +#---------------------------------------------------------------------- +# Header files and library search paths and names +# +# INCLUDEDIRS looks like "-I/projects/glu/ -I/projects/vis/ ..." +# LIBRARYDIRS looks like "-L/projects/glu/ -L/projects/vis/ ..." +# LIBS looks like "-lm -lglu -lvis" +#---------------------------------------------------------------------- + +INCLUDEDIRS = $(addprefix -I,$(gluincdir)) \ + $(foreach package, $(PKGS), -I$(local_srcdir)/src/$(package)) \ + $(foreach package, $(MISSING_PKGS), \ + -I$(master_srcdir)/src/$(package)) \ + -I$(objectdir) \ + $(CPPFLAGS) + +LIBRARYDIRS = $(addprefix -L,$(vislibdir)) $(addprefix -L,$(glulibdir)) \ + $(LIBDIRS) + +# Link against the VIS library only if some packages are missing +# (i.e., we are compiling only a few packages locally) + +ifneq ($(strip $(MISSING_PKGS)),) + VISLIBS = -l$(PRODUCT) +else + VISLIBS = +endif + +GLULIBS = -l$(BDDPKG) -lglu + +# g++ on Linux RH requires -lstdc++ +ifeq ($(CC),g++) +OTHERLIBS += -lstdc++ +endif + +LIBS = $(VISLIBS) $(GLULIBS) $(OTHERLIBS) + +#---------------------------------------------------------------------- +# Form the the list of directories to search for header files. +# +# VPATH looks like /projects/vis:/projects/glu/: ... +#---------------------------------------------------------------------- + +VPATH = $(local_srcdir): \ + $(master_srcdir): \ + $(addprefix :$(local_srcdir)/src/,$(PKGS)): \ + $(addprefix :$(master_srcdir)/src/,$(MISSING_PKGS)): \ + $(objectdir): \ + $(local_srcdir)/share + +#---------------------------------------------------------------------- +# Definitions for the distribution file +#---------------------------------------------------------------------- + +DISTRIBUTION = $(PRODUCT)-$(VERSION) + +# Directories to include in the distribution file + +DISTDIRS = src helpers share share/help obj doc examples \ + $(addprefix examples/,$(EXAMPLES)) $(addprefix src/,$(PKGS)) + +# Build/install helper files + +HELPERS = $(addprefix helpers/, \ + install-sh mkinstalldirs config.guess config.sub dependency.make) + +# Files to include in the distribution file + +DISTFILES = \ + README INSTALL NEWS \ + configure configure.in Makefile.in $(HELPERS) \ + vis.1 \ + xsimv \ + $(CSRC) $(HEADERS) $(LEXSRC) $(YACCSRC) $(MAKEINCLUDES) \ + $(EXAMPLEFILES) \ + $(addprefix doc/,$(DOCUMENTATION)) \ + $(addprefix share/,$(SHAREFILES)) \ + $(addprefix share/help/,$(HELPFILES)) + +#---------------------------------------------------------------------- +# Variables used by for Revision Control +#---------------------------------------------------------------------- + +# The root RCS directory +rcs_rootdir = /projects/vis/rcsRoot/common + +RCSFILES = $(CSRC) $(HEADERS) $(LEXSRC) $(YACCSRC) $(MAKEINCLUDES) + +RCSMISCFILES = Makefile.in configure.in localconfigure \ + masterconfigure README INSTALL NEWS xsimv $(addprefix helpers/, mkinstalldirs install-sh \ + config.guess config.sub dependency.make ) + +RCSSHAREFILES = $(SHAREFILES) + +#---------------------------------------------------------------------- +# Implicit rules +#---------------------------------------------------------------------- + +ALLCFLAGS = $(CFLAGS) $(AC_FLAGS) $(VERDATE) \ + -DNAWK=\"$(NAWK)\" -DLIBRARY=\"$(datadir)\" + +# For compiling a source file into the object directory + +$(objectdir)/%.o : %.c + umask 2 ; $(CC) -c $(ALLCFLAGS) $(INCLUDEDIRS) -o $@ $< + +# Place object files into an archive + +%.a : + rm -f $@ + umask 2; $(AR) cq $@ $^ + $(RANLIB) $@ + +###################################################################### +# RULES # +###################################################################### + +#: +#: Useful targets: +#: + +#---------------------------------------------------------------------- +# Rule for getting help +#---------------------------------------------------------------------- + +.PHONY : help + +#: help -- Print a list of targets + +# This prints all lines in this Makefile that begin with #: + +help : + @sed -n "s/^#://p" Makefile + +#---------------------------------------------------------------------- +# Always executed once when the Makefile is run +#---------------------------------------------------------------------- + +# Make sure the directory in which to place the objects exists + +ignored := $(shell umask 2; test -d $(objectdir) || mkdir $(objectdir)) + +#---------------------------------------------------------------------- +# Rules to compile and build libraries and executables +#---------------------------------------------------------------------- + +.PHONY : all allprods library allprods-mp exe-mp compile-version delete-version + +#: +#: all (the default) -- Compile the main executable +# (force the version to be recompiled) + +all : ALLCFLAGS += -DBDD$(BDDPKG) + +all : compile-version $(PRODUCT) + +# Create the main executable +$(PRODUCT) : $(OBJECTS) $(glulibdir)/libglu.a $(glulibdir)/lib$(BDDPKG).a + umask 2 ; $(LINKER) -o $(PRODUCT) $(LDFLAGS) \ + $(OBJECTS) $(LIBRARYDIRS) $(LIBS) + +#: allprods -- Compile an executable linked with each BDD package + +allprods : $(OBJECTS) $(glulibdir)/libglu.a $(foreach bddpkg, $(BDDPKGS), \ + $(glulibdir)/lib$(bddpkg).a) + @for bddpkg in $(BDDPKGS) ; \ + do \ + rm -f $(objectdir)/satBDD.o; \ + umask 2 ; $(CC) -c $(ALLCFLAGS) -DBDD$$bddpkg $(INCLUDEDIRS) -o $(objectdir)/satBDD.o $(master_srcdir)/src/sat/satBDD.c; \ + echo "Creating vis-$$bddpkg";\ + umask 2 ; $(LINKER) -o $(PRODUCT)-$$bddpkg $(LDFLAGS) $(OBJECTS) \ + $(LIBRARYDIRS) $(VISLIBS) -l$$bddpkg -lglu $(OTHERLIBS); \ + done + +# Force the "version" information to be recompiled + +compile-version : delete-version $(objectdir)/vmVers.o $(objectdir)/satBDD.o + +# Delete the object file related to the version + +delete-version : + rm -f $(objectdir)/vmVers.o $(objectdir)/satBDD.o + +# Build a library containing all the objects + +#: library -- Create a library of all the objects (useful in a central area) + +library : $(LIBRARY) + +$(LIBRARY) : $(OBJECTS) + +ifdef PLINKER +$(PRODUCT)-mp : $(LIBRARY) $(glulibdir)/libglu.a \ + $(foreach bddpkg, $(BDDPKGS), \ + $(glulibdir)/lib$(bddpkg).a) + umask 2 ; $(PLINKER) -o $(PRODUCT)-mp $(OBJECTS) \ + `purify -printhomedir`/libpurify_stubs.a \ + $(LIBRARYDIRS) $(LIBS) + +allprods-mp : $(LIBRARY) $(glulibdir)/libglu.a \ + $(foreach bddpkg, $(BDDPKGS), \ + $(glulibdir)/lib$(bddpkg).a) + @for bddpkg in $(BDDPKGS) ; \ + do \ + echo "Creating vis-$$bddpkg";\ + umask 2 ; $(PLINKER) -o $(PRODUCT)-$$bddpkg-mp $(OBJECTS) \ + `purify -printhomedir`/libpurify_stubs.a \ + $(LIBRARYDIRS) $(VISLIBS) -l$$bddpkg -lglu $(OTHERLIBS) ; \ + done + +exe-mp : $(OBJECTS) + $(PLINKER) -o $(PRODUCT)-mp $(OBJECTS) \ + `purify -printhomedir`/libpurify_stubs.a \ + $(LIBRARYDIRS) $(LIBS) +endif + +#---------------------------------------------------------------------- +# Rule to produce the function map for the memory_profile command +#---------------------------------------------------------------------- + +.PHONY : functionmap + +FMAPFILE = .fmap +functionmap: $(CSRC) + $(VIS)/common/share/createfunctionmap $^ >$(FMAPFILE) + +#---------------------------------------------------------------------- +# Rules for installation +#---------------------------------------------------------------------- + +.PHONY : install uninstall installdirs + +#: +#: install -- Install the product and libraries in bindir, libdir, +#: datadir, etc. + +install : $(PRODUCT) $(LIBRARY) installdirs + @echo "Installing $(bindir)/$(PRODUCT)" + @$(INSTALL_PROGRAM) $(PRODUCT) $(bindir)/$(PRODUCT) + @echo "Installing $(libdir)/$(LIBRARY)" + @$(INSTALL_DATA) $(LIBRARY) $(libdir)/$(LIBRARY) + @for file in $(SHAREFILES) ; do \ + echo "Installing $(datadir)/$$file"; \ + $(INSTALL_DATA) $(master_srcdir)/share/$$file \ + $(datadir)/$$file; \ + done + @for file in $(HELPFILES) ; do \ + echo "Installing $(datadir)/help/$$file"; \ + $(INSTALL_DATA) $(master_srcdir)/share/help/$$file \ + $(datadir)/help/$$file; \ + done + @echo "Installing $(mandir)/vis.1" + @$(INSTALL_DATA) vis.1 $(mandir)/vis.1 + @for header in $(HEADERS); do \ + echo "Installing $(includedir)/$$header"; \ + $(INSTALL_DATA) $(master_srcdir)/src/*/$$header \ + $(includedir)/$$header; \ + done + +#: uninstall -- Reverse the effects of "install" + +uninstall : + rm -f $(bindir)/$(PRODUCT) + rm -f $(libdir)/$(LIBRARY) + @for file in $(SHAREFILES) ; \ + do \ + echo "Removing $(datadir)/$$file"; \ + rm -f $(datadir)/$$file; \ + done + @for file in $(HELPFILES) ; \ + do \ + echo "Removing $(datadir)/help/$$file"; \ + rm -f $(datadir)/help/$$file; \ + done + @for header in $(HEADERS); \ + do \ + echo "Removing $(includedir)/$$header"; \ + rm -f $(includedir)/$$header; \ + done + +installdirs : + $(master_srcdir)/helpers/mkinstalldirs \ + $(bindir) $(libdir) $(includedir) $(datadir) $(datadir)/help \ + $(mandir) + +#---------------------------------------------------------------------- +# Rules for checking the build +#---------------------------------------------------------------------- + +.PHONY : check check-examples + +# This is a lengthy sed command used to filter out the irrelevant VIS +# output that appears when the examples are running. +# +# Sed does not permit space between the trailing p ("print matching +# lines") and the semicolon (end of command). Hashes are escaped -- +# otherwise they are Makefile comments. This was once a long egrep +# expression, but the string was too long for Ultrix's egrep. + +SED_CMD = \ + /^FSM depth/p; \ + /^computation depth/p; \ + /^reachable states =/p; \ + /^\# MC: formula passed/p; \ + /^\# MC: formula failed/p; \ + /^\# MC: the number of non-trivial forced segments/p; \ + /^\# MC: Vacuous/p; \ + /^\# MC: No vacuous/p; \ + /[sS]tates covered/p; \ + /covered states/p; \ + /Percentage of coverage/p; \ + /^\# LTL_MC: formula passed/p; \ + /^\# LTL_MC: formula failed/p; \ + /^\# INV: formula passed/p; \ + /^\# INV: formula failed/p; \ + /^\# LE: language is not empty/p; \ + /^\# LE: language emptiness check passes/p; \ + /^\# ABS: formula passed/p; \ + /^\# ABS: formula failed/p; \ + /^\# BMC: formula failed/p;\ + /^\# BMC: no counterexample found/p; \ + /Residue/p; \ + /^\# AMC: Verified formula TRUE/p; \ + /^\# AMC: Verified formula FALSE/p; \ + /Equivalence Classes/p; \ + /Total number of literals/p; \ + /Networks are combinationally equivalent\./p; \ + /Networks are sequentially equivalent\./p; \ + /;.*;/p; + +CHECK_EXAMPLES_cu = daio_receiver mult6x6 s1269 fpmpy restruct synthesis \ + production_cell +CHECK_EXAMPLES_cmu = +CHECK_EXAMPLES_cal = + +# List of all examples to check (A subset of EXAMPLES) + +CHECK_COMMON_EXAMPLES = abp amp arbiter bakery coherence counter crd ctlp3 \ + dcnew eisenberg elevator ethernet exampleS gcd gigamax ping_pong \ + scheduler short slider tbl_one_bug tcp tlc treearbiter + +CHECK_EXAMPLES = $(CHECK_COMMON_EXAMPLES) $(CHECK_EXAMPLES_$(BDDPKG)) + +# Determine the absolute executable path +# +# Starting from the current directory, change directory to the directory +# part of the product name, then tack on the filename part of EXECUTABLE + +EXECUTABLE = $(PRODUCT) + +EXECUTABLEPATH := \ + $(shell cd $(dir $(EXECUTABLE)) ; pwd)/$(notdir $(EXECUTABLE)) + +# Determine the rootname of the examples +# + +EXAMPLEPATH = $(master_srcdir)/examples + +FULLEXAMPLEPATH := $(shell cd $(EXAMPLEPATH) ; pwd) + +#: +#: check -- Test the locally-built executable (runs check-examples) + +check : check-examples + +# Run check on each of the bdd versions (named e.g., vis-cmu) + +#: check-allprods -- Test each of the BDD executables (see allprods) + +check-allprods : + @for bddpkg in $(BDDPKGS) ; \ + do \ + echo "Checking $(PRODUCT)-$$bddpkg";\ + $(MAKE) PRODUCT=$(PRODUCT)-$$bddpkg BDDPKG=$$bddpkg check ; \ + done + +#: check-examples -- Test each of the examples listed in CHECK_EXAMPLES +#: You may want to invoke this with +#: gmake "CHECK_EXAMPLES=abp bakery" check-examples +#: gmake EXECUTABLE=vis-cmu check-examples +#: gmake EXECUTABLE=/projects/vis/vis-devel/alpha-g/vis \ +#: check-examples +#: gmake EXAMPLEPATH=/projects/vis/vis-devel/common/examples \ +#: check-examples +#: gmake EXAMPLEPATH=../common/examples check-examples +#: gmake VIS_LIBRARY_PATH=/projects/vis/vis-devel/share + +# For each example, +# +# 1) create the directory checkresults/ +# 2) enter that directory +# 3) create "check_script" by prepending a "set open_path" command +# to the example's check_script in the master source directory. This +# makes VIS look in the master source directory for example files +# 4) run VIS on that script, producing "result.raw" +# 5) filter out relevant lines in the result, producing "result.filtered" +# and compare this with the "check_result" file in the master source +# directory. Differences are written to "result.differences" + +check-examples : + @test -d checkresults || mkdir checkresults + @echo "Checking examples. Results will be in checkresults//result.raw" + @echo "Running executable $(EXECUTABLEPATH)" + @echo " (change with EXECUTABLE=...)" + @echo "Taking examples from $(FULLEXAMPLEPATH)" + @echo " (change with EXAMPLEPATH=...)" + @cwd=`pwd` ; \ + VIS_LIBRARY_PATH=$(VIS_LIBRARY_PATH) ; \ + export VIS_LIBRARY_PATH ; \ + for example in $(CHECK_EXAMPLES) ; \ + do \ + echo -n "Checking $$example ... " ; \ + cd $$cwd ; \ + test -d checkresults/$$example || \ + mkdir checkresults/$$example ; \ + cd checkresults/$$example ; \ + rm -f check_script ; \ + echo "set open_path $(FULLEXAMPLEPATH)/$$example" > check_script ; \ + cat $(FULLEXAMPLEPATH)/$$example/check_script >> check_script ; \ + $(EXECUTABLEPATH) -f check_script -x > result.raw 2> result.stderr ; \ + sed -n '$(SED_CMD)' result.raw > result.filtered ; \ + if diff result.filtered \ + $(FULLEXAMPLEPATH)/$$example/check_result > result.differences ; \ + then \ + echo "passed" ; \ + rm result.differences ; \ + else \ + echo "failed (more checkresults/$$example/result.differences)" ; \ + fi ; \ + done + +# egrep '$(KEY_WORDS)' result.raw > result.filtered ; \ + +#---------------------------------------------------------------------- +# Rules that produce/delete the dependency file for every package +#---------------------------------------------------------------------- + +.PHONY : dependencies cleandependencies + +#: +#: dependencies -- Create a list of dependency files. +#: Useful when modifying header files. + +# Invoke the "dependency.make" Makefile on each package subdirectory, +# passing the path, etc. to it. +# +# There's a strange feature in autoconf where lines of the form " VPATH=" +# are removed from the Makefile. Thus, a flag is placed before the +# VPATH= argument below. + +dependencies: +ifneq ($(findstring <$(CC)>, ),) + for pkg in $(PKGS) ; \ + do \ + $(MAKE) --no-print-directory \ + -f $(master_srcdir)/helpers/dependency.make \ + CC="$(CC)" \ + CFLAGS="$(CFLAGS)" VPATH="$(local_srcdir)/src/$$pkg" \ + AC_FLAGS="$(AC_FLAGS)" \ + INCLUDEDIRS="$(INCLUDEDIRS)" objectdir=$(objectdir) \ + PKGNAME=$(local_srcdir)/src/$$pkg/$$pkg \ + $(local_srcdir)/src/$$pkg/$$pkg.d ; \ + done +else + @echo "dependency requires gcc or g++" + @echo "Reconfigure with gcc or g++" +endif + +cleandependencies: + rm -f $(local_srcdir)/src/*/*.d + +#---------------------------------------------------------------------- +# Rules for making a distribution file +#---------------------------------------------------------------------- + +.PHONY : dist + +#: +#: dist -- Create a tarred, gzipped distribution file + +# Warning: "tar" under Digital Unix (on DEC Alphas) writes directories +# that don't work under SunOS tar + +dist : $(DISTRIBUTION).tar.gz + +$(DISTRIBUTION).tar.gz : $(DISTFILES) +ifeq ($(strip $(FULL_MISSING_PKGS)),) + rm -rf $(DISTRIBUTION) + umask 022; mkdir $(DISTRIBUTION) + for dir in $(DISTDIRS); \ + do \ + umask 022; mkdir $(DISTRIBUTION)/$$dir; \ + done + @echo "Copying distribution files" + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + echo " $$file"; \ + cp -p $(local_srcdir)/$$file $(DISTRIBUTION)/$$file; \ + done + - chmod -R a+r $(DISTRIBUTION) + - chmod -R u+w $(DISTRIBUTION) + tar cf - $(DISTRIBUTION) | gzip -9 > $(DISTRIBUTION).tar.gz + rm -rf $(DISTRIBUTION) +else + @echo "Missing packages: $(FULL_MISSING_PKGS)" + @echo "Make sure PKGS lists all the packages" + @exit 1 +endif + +#---------------------------------------------------------------------- +# Rules for rebuilding the configure file and Makefile +#---------------------------------------------------------------------- + +${master_srcdir}/configure : configure.in + cd ${master_srcdir} && autoconf + chmod 0775 ${master_srcdir}/config* + +config.status : configure + ./config.status --recheck + +Makefile : Makefile.in config.status + @echo "The master Makefile.in has been changed:" + @echo "run config.status" + @echo "Warning: This will overwrite any local Makefile modifications" + @exit 1 + +#---------------------------------------------------------------------- +# Rules for cleaning +#---------------------------------------------------------------------- + +.PHONY : clean mostlyclean distclean + +#: +#: clean -- Remove every file created by building + +clean mostlyclean : + rm -rf $(objectdir)/* $(LIBRARY) $(PRODUCT) \ + $(foreach bddpkg, $(BDDPKGS), $(PRODUCT)-$(bddpkg)) \ + checkresults include + +#: distclean -- Remove every file created by building or configuring + +distclean : clean cleandependencies + rm -f Makefile config.status config.cache config.log + +#---------------------------------------------------------------------- +# Rule for performing a lint-like check on the source code +# +# Note: This requires gcc or g++ +#---------------------------------------------------------------------- + +.PHONY : check-code + +#: +#: check-code -- Run a lint-like check on the source code. +#: (useful for development) + +CHECK_FLAGS := -Wall -pedantic -DBDD$(BDDPKG) +ifeq ($(CC),gcc) + CHECK_FLAGS += -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations +endif + +check-code : $(CSRC) $(BDD_CSRC) $(MDD_CSRC) +ifneq ($(findstring <$(CC)>, ),) + @rm -f *.o_checkcode + @for file in $^; \ + do \ + echo "------------------------ Checking $$file"; \ + $(CC) -c $(CFLAGS) $(AC_FLAGS) $(CHECK_FLAGS) \ + $(VERDATE) $(INCLUDEDIRS) \ + -o $(objectdir)/checkcode_output.o $$file; \ + rm -f $(objectdir)/checkcode_output.o; \ + done + @rm -f *.o_checkcode +else + @echo "check-code requires gcc or g++" + @echo "Reconfigure with gcc or g++" +endif + +#---------------------------------------------------------------------- +# Rule for generating function prototypes for all the +# source and header files in all the PKGS +# +# Note: This requires "extproto," part of the ext package available from +# ftp://ic.eecs.berkeley.edu/pub/Ext +#---------------------------------------------------------------------- + +.PHONY : proto + +#: +#: proto -- Regenerate all the function prototypes in the packages +#: Useful during development. You may want to invoke it with +#: gmake "PKGS=tst tbl" proto + +proto : + @cd $(local_srcdir)/src ; \ + for pkg in $(PKGS); \ + do \ + cd $$pkg ; \ + extproto *.h *.c ; \ + cd .. ; \ + done + +#---------------------------------------------------------------------- +# Rules for generating the documentation and command help files +# for all the packages +# +# Note: This requires "extdoc," part of the ext package, and +# lynx, a textual WWW browser +#---------------------------------------------------------------------- + +.PHONY : allDoc doc indices helpfiles cleandoc + +#: +#: allDoc -- Extract all the documentation (runs doc, indices, and helpfiles) + +allDoc : cleandoc doc indices helpfiles + +#: doc -- Extract HTML and text documentation on all the functions + +doc : $(htmldocdir) $(txtdocdir) + for pkg in $(PKGS); \ + do \ + umask 2 ; extdoc --html=$(htmldocdir) --text=$(txtdocdir) \ + $(local_srcdir)/src/$$pkg/$$pkg; \ + done + +#: indices -- Generate function and command indices for the HTML documentation + +indices : $(htmldocdir) + umask 2 ; extindex $(htmldocdir) + +#: helpfiles -- Generate the help files from the HTML documentation + +helpfiles : $(helpdir) + for file in $(htmldocdir)/*Cmd.html ; \ + do \ + echo Converting $$file ; \ + umask 2 ; lynx -dump $$file > $(helpdir)/`basename $$file .html`.txt ; \ + done + +#: cleandoc -- Remove all the documentation generated by "allDoc" + +cleandoc : + -rm -f $(htmldocdir)/*.html + -rm -f $(txtdocdir)/*.txt + -rm -f $(helpdir)/*Cmd.txt + +$(htmldocdir) : + - umask 2 ; mkdir $(htmldocdir) + +$(txtdocdir) : + - umask 2 ; mkdir $(txtdocdir) + +$(helpdir) : + - umask 2 ; mkdir $(helpdir) + + +#---------------------------------------------------------------------- +# Revision control rules +# +# May be invoked with command-line overrides, e.g., +# gmake RCSFILES=foo.c rcs_co +# gmake PKGS=array rcs_ci +#---------------------------------------------------------------------- + +.PHONY: rcs_ci rcs_co rcs_diff rcs_ident rcs_status + +#: +#: You may want to invoke the RCS rules with +#: gmake "PKGS=tst tbl" rcs_ci +#: gmake "RCSFILES=tstMain.c" rcs_co +#: +#: rcs_ci -- check in user-modified files and put an updated copy +#: in the central area + +rcs_ci: $(RCSFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + ci -u $(RCSFLAGS) $(local_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + co -u $(RCSFLAGS) $(master_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + done + +#: rcs_co -- check out files for modification + +rcs_co: $(RCSFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + co -l $(RCSFLAGS) $(local_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + done + +#: rcs_diff -- Report differences between local files and checked-in versions + +rcs_diff: $(RCSFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + rcsdiff $(RCSFLAGS) $(local_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + done + +#: rcs_ident -- Print the RCS identifier in each file + +rcs_ident: $(RCSFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + ident $(RCSFLAGS) $(local_srcdir)/$$file; \ + done + +#: rcs_status -- Report who has checked out files + +rcs_status: $(RCSFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + rlog -L -h $(RCSFLAGS) $(rcs_rootdir)/$$file,v; \ + done + +#---------------------------------------------------------------------- +# RCS rules for common/{Makefile.in, configure.in, localconfigure, +# masterconfigure, mkinstalldirs, install-sh} +#---------------------------------------------------------------------- + +.PHONY : rcs_ci_misc rcs_co_misc rcs_diff_misc + +#: rcs_ci_misc -- Check in miscellaneous files, updating central area + +rcs_ci_misc: $(RCSMISCFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + ci -u $(RCSFLAGS) $(local_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + co -u $(RCSFLAGS) $(master_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + done + +#: rcs_co_misc -- Check out miscellaneous files + +rcs_co_misc: $(RCSMISCFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + co -l $(RCSFLAGS) $(local_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + done + +#: rcs_diff_misc -- Report differences in miscellaneous files + +rcs_diff_misc: $(RCSMISCFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + rcsdiff $(RCSFLAGS) $(local_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + done + +#: rcs_ident_misc -- Report RCS identifiers + +rcs_ident_misc: $(RCSMISCFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + ident $(RCSFLAGS) $(local_srcdir)/$$file; \ + done + +#: rcs_status_misc -- Report checked in/out status, ownership + +rcs_status_misc: $(RCSMISCFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + rlog -L -h $(RCSFLAGS) $(rcs_rootdir)/$$file,v; \ + done + +#---------------------------------------------------------------------- +# RCS rules for files in common/share +#---------------------------------------------------------------------- + +.PHONY : rcs_ci_share rcs_co_share rcs_diff_share + +#: rcs_ci_share -- Check in files in the share/ directory + +rcs_ci_share: $(RCSSHAREFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + ci -u $(RCSFLAGS) $(local_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + co -u $(RCSFLAGS) $(master_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + done + +#: rcs_co_share -- Check out share files + +rcs_co_share: $(RCSSHAREFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + co -l $(RCSFLAGS) $(local_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + done + +#: rcs_diff_share -- Report differences in share files + +rcs_diff_share: $(RCSSHAREFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + rcsdiff $(RCSFLAGS) $(local_srcdir)/$$file $(rcs_rootdir)/$$file,v; \ + done + +#: rcs_ident_share -- Report RCS identifiers + +rcs_ident_share: $(RCSSHAREFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + ident $(RCSFLAGS) $(local_srcdir)/$$file; \ + done + +#: rcs_status_share -- Report checked in/out status, ownership + +rcs_status_share: $(RCSSHAREFILES) + @for file in $(patsubst $(local_srcdir)/%, %, $^); \ + do \ + rlog -L -h $(RCSFLAGS) $(rcs_rootdir)/$$file,v; \ + done + +#---------------------------------------------------------------------- +# Rules for debugging the Makefile +#---------------------------------------------------------------------- + +.PHONY : debug-make + +DEBUG_VARS = ALL_PKGS \ + PKGS \ + MISSING_PKGS \ + VPATH \ + INCLUDEDIRS \ + CSRC \ + OBJECTS \ + HEADERS \ + MAKEINCLUDES \ + CFLAGS \ + AC_FLAGS \ + master_srcdir \ + local_srcdir \ + RCSFILES \ + RCSDIR \ + LIBS \ + VISLIBS \ + DISTFILES \ + EXAMPLEFILES + +#: +#: debug-make -- Print a list of Makefile variables + +debug-make: + @$(foreach var, $(DEBUG_VARS), echo $(var)=$($(var)) ; ) Index: vis_dev/vis-2.1/NEWS =================================================================== --- vis_dev/vis-2.1/NEWS (revision 11) +++ vis_dev/vis-2.1/NEWS (revision 11) @@ -0,0 +1,1642 @@ +VIS NEWS -*-indented-text-*- + History of user-visible changes. + +Please sent bug reports to vis-users@colorado.edu. Please let us know what +version of VIS you are running and what architecture you are running it on. + +====================================================================== + +Version 2.1 + +Release 2.1 of VIS improves VIS 2.0 in the following areas: + +1. Revamped Bounded Model Checker with efficient termination criteria +2. Grab and Puresat algorithms for invariant checking based on + abstraction refinement +3. DnC algorithm for language emptiness check based on abstraction + refinement +4. CirCUs SAT solver. +5. Fate and Free Will algorithm for the analysis of counterexamples +6. Vacuity detection for CTL +7. Coverage estimation for CTL +8. Far Side algorithm for image computation +9. CUDD 2.4.1 +10. Miscellaneous + + +Bounded Model Checking +---------------------- + +BMC in VIS 2.1 is much faster than it was in VIS 2.0. The +construction of the circuit data structure, the encoding of the +property, the use of a faster SAT solver all have contributed to this +improvement. + +BMC in VIS 2.1 can prove properties rather than just falsifying them. +The following sequence of commands is used to perform bounded model +checking with termination check: + + read_blif_mv model.mv + flatten_hierarchy + build_partition_maigs + bounded_model_check -k 10 -r 2 model.ltl + +The termination check will be performed every other step. The +construction of the MDDs is not needed if termination check is needed +for invariant properties only. For details on the stopping criteria, +see + +M. Awedh and F. Somenzi, "Proving More Properties with Bounded Model +Checking," CAV 2004, pp. 96-108, LNCS 3114. + +Other new options to the bounded_model_check command allow one to +control the formula encoding, the solver to be applied (CirCUs or +zChaff) and, for the former, the incremental solving algorithm. + +A new command ltl2snf allows one to translate an LTL formula to +separation normal form. + + +Abstraction Refinement for Invariants +------------------------------------- + +The check_invariant command allows the user the choice of one of two +abstraction refinement algorithms for invariants. The Grab algorithm +uses BDD-based model checking on the abstract model and SAT for +counterexample concretization check. Its refinement strategy is +game-theoretic. It is run as follows: + + read_blif_mv model.mv + flatten_hierarchy + build_partition_maigs + check_invariant -A3 model.inv + +By default, grab enables dynamic variable reordering for the abstract +model. One can override this behavior by explicitly building +partition MDDs. For details of the algorithm, see + +C. Wang, B. Li, H. Jin, G. D. Hachtel, and F. Somenzi, "Improving +Ariadne's Bundle by Following Multiple Threads in Abstraction +Refinement," ICCAD 2003, pp. 408-415. + +The puresat algorithm uses SAT as the only decision procedure for both +abstract and concrete model. It analyzes the proofs of +unsatisfiability to produce refinements. It is invoked as follows: + + read_blif_mv model.mv + flatten_hierarchy + build_partition_maigs + check_invariant -A4 model.inv + +The algorithm is described in + +B. Li, C. Wang, and F. Somenzi, "Abstraction Refinement in Symbolic +Model Checking Using Satisfiability as the Only Decision Procedure," +STTT, vol.7, n. 2, pp. 143-155. + + +Abstraction Refinement for Language Emptiness +-------------------------------------------- + +The lang_empty command has a new option that runs the "Divide and +Compose" (DnC) algorithm described in + +C. Wang, R. Bloem, G. D. Hachtel, K. Ravi, and F. Somenzi, "Divide and +Compose: SCC Refinement for Language Emptiness", CONCUR 2001, +pp. 456-471, LNCS 2154. + +The algorithm, which is based on refinement of the strongly connected +components of the model, is invoked as follows: + + read_blif_mv model.mv + init_verify + lang_empty -A 1 + + +CirCUs SAT solver +----------------- + +VIS 2.1 includes the SAT solver CirCUs, a short description of which +can be found in + +H. Jin, M. Awedh, and F. Somenzi, "CirCUs: A Satisfiability Solver +Geared Towards Bounded Model Checking," CAV 2004, pp. 519-522, LNCS +3114. + +CirCUs is an incremental SAT solver that accepts input in either +circuit or CNF form. It is the default solver for bounded model +checking and abstraction refinement algorithms. It can also be +invoked from the VIS prompt as a stand-alone CNF SAT solver on a set +of clauses described in DIMACS format: + + cnf_sat input.cnf + + +Fate and Free Will Algorithm +---------------------------- + +The counterexamples produced by model_check and check_invariant can be +optionally generated with the Fate and Free Will algorithm of + +H. Jin, K. Ravi, and F. Somenzi, "Fate and Free Will in Error Traces," +STTT, vol. 6, n. 2, pp. 102-116. + +This algorithm is only available when vis is linked with the cu BDD +package. It assumes a partition of the inputs into variables +controlled by the environment and variables controlled by the system, +and divides a counterexample into fated and free segments. In a fated +segment, the values of the variables controlled by the environment +suffice to impose progress toward violation of the property. In a +free segment, the other variables are also required. + +To run the Fate and Free Will algorithm, one prepares a file with the +inputs that the system controls. For a failing invariant, the +invocation is like this: + + read_blif_mv model.mv + init_verify + check_invariant -d1 -i -w system_inputs + +The last command is replaced by + + model_check -d2 -i -w system_inputs + +for a CTL property. The -W option can be used to assign all inputs to +the system, while the -G option invokes a variant of the algorithm. + + +Vacuity Detection for CTL +------------------------- + +VIS 2.1 implements two algorithms for the detection of vacuity in CTL +model checking. A formula passes vacuously if it can be strengthened +by replacement of one of its subformulae with "bottom" and still pass. +Likewise, a formula fails vacuously if it can be weakened by +replacement of one of its subformulae with "top" and still fail. + +The algorithm of Beer et al. (CAV 97) is invoked with the -B option as +follows: + + read_blif_mv model.mv + init_verify + model_check -B model.ctl + +This algorithm applies to a subset of ACTL and considers only passing +properties. If an error trace is requested with -d, in case of +vacuous pass, an interesting witness is produced. + +The second algorithm for vacuity detection is an extension of the one +describe in + +M. Purandare and F. Somenzi, "Vacuum Cleaning CTL Formulae," CAV 2002, +pp. 485-499, LNCS 2404. + +This algorithm applies a thorough vacuity detection to all of CTL and +to both passing and failing properties. With -d, it produces +interesting witnesses for passing properties and interesting +counterexamples for failing ones. + +The current implementation is limited in its treatment of the +operators <-> (equivalence) and ^ (exclusive or). + + +Coverage Estimation for CTL +--------------------------- + +VIS 2.1 provides two algorithms for coverage estimation in CTL model +checking. Both are invoked with options passed to the model_check +command. + +The first algorithm is the one of Hoskote et al. (DAC 1999). It +applies to a subset of ACTL. The option is -C. The second algorithm +is an improved version of the same described in + +N. Jayakumar, M. Purandare, and F. Somenzi, "Dos and Don'ts of CTL +State Coverage Estimation," DAC 2003, pp. 292-295. + +To invoke the improved coverage estimation algorithm one writes: + + read_blif_mv model.mv + init_verify + model_check -I model.ctl + + +Far Side Algorithm for Image Computation +---------------------------------------- + +By setting image_farside_method to 1, a user of VIS 2.1 can invoke the +Far Side approach to image computation which applies a compositional +method based on don't cares to speed up reachability analysis. The +algorithm is described in + +C. Wang, G. D. Hachtel, and F. Somenzi, "The Compositional Far Side of +Image Computation," ICCAD 2003, pp. 334-340. + +See the documentation of the "set" command for the details. + + +CUDD 2.4.1 +---------- + +VIS-2.0 includes CUDD 2.4.1. Compared to the version that was +included in VIS-2.0, the new version has faster grabage collection, +provides improved support for C++ compilation, contains a number of +bug fixes and several new functions, including functions for the +manipulation of prime implicants of a function. + + +Miscellaneous +------------- + +* Glu and vis can be built using g++ as compiler by configuring as + follows: + + ./configure --enable-gcc=g++ + +* The code in glu has gone through another round of rejuvenation. + This process allows vis to be built with recent versions of gcc (3.3 + and later) without producing any type-punning warning. + +* Two bugs have been fixed in early termination detection in CTL model + checking. + +* A bug has been fixed in the treatment of multi-valued inputs. + +* Vis no longer crashes when compute_reach is invoked with the -i + option. + +* Timeout values for model_check, check_invariant, and lang_empty are + now in CPU time instead of elapsed time. This is beneficial when + running regression tests in the presence of other processes. + +* The ctime command is no longer supported. + + +====================================================================== + +Version 2.0 + +Release 2.0 of VIS improves VIS 1.4 in the following areas: + +1. LTL model checking +2. SAT-based Bounded Model Checking (BMC) +3. Minimum Lifetime Permutation (MLP) algorithm for conjuction scheduling +4. Generalized SCC Hull (GSH) algorithm for greatest fixpoint + computation +5. Lockstep algorithm for language emptiness +6. Built-in regression test facility +7. CUDD 2.3.2 +8. Miscellaneous + + +LTL model checking +------------------ + +VIS-2.0 has a new command ltl_model_check that model checks LTL +formulae. The syntax for LTL is quite similar to that used for CTL. +Another new command, ltl_to_aut, translates LTL formulae into Buechi +automata. + + +SAT-Based Bounded Model Checking +-------------------------------- + +VIS-2.0 has a new command bounded_model_check for bounded LTL model +checking. The SAT solver zchaff (http://www.ee.princeton.edu/~chaff/) +must be in the executable path for this command to work. The following +sequence of commands is used to perform bounded model checking: + + read_blif_mv model.mv + flatten_hierarchy + build_partition_maigs + bounded_model_check -k 10 model.ltl + +where "-k 10" specifies the bound on the length of the counterexample. + + +Minimum Lifetime Permutation (MLP) Algorithm for Conjuction Scheduling +---------------------------------------------------------------------- + +The MLP algorithm can considerably speed up image computations. It is +selected by typing + + set image_method mlp + +For details on the algorithm, see + +I-H. Moon, G. D. Hachtel, and F. Somenzi, "Border-Block Triangular +Form and Conjunction Schedule in Image Computation," FMCAD 2000, +pp. 73-90, LNCS 1954. + + +Generalized SCC Hull (GSH) Algorithm for Greatest Fixpoint Computation +---------------------------------------------------------------------- + +The commands model_check, ltl_model_check, and lang_empty use a new +algorithm for greatest fixpoint computations. This algorithm has +different "schedules" that can be controlled with the -S option. For +details on the algorithm, see + +K. Ravi, R. Bloem, and F. Somenzi, "A Comparative Study of Symbolic +Algorithms for the Computation of Fair Cycles," FMCAD 2000, +pp. 143-160, LNCS 1954. + +F. Somenzi, K. Ravi, and R. Bloem, "Analysis of Symbolic {SCC} Hull +Algorithms," FMCAD 2002, To appear. + + +Lockstep Algorithm for Language Emptiness +----------------------------------------- + +In VIS-2.0, the commands ltl_model_check and lang_empty can use the +lockstep algorithm to perform the language emptiness check. The use +of the lockstep algorithm as an alternative to the GSH algorithm is +controlled by the -L option. For details of Lockstep, see + +R. Bloem, H. N. Gabow, and F. Somenzi, "An Algorithm for Strongly +Connected Component Analysis in n log n Symbolic Steps," FMCAD 2000, +pp. 37-54, LNCS 1954. + + +Built-in Regression Test Facility +--------------------------------- + +VIS-2.0 has a new command regression_test which allows users to +compare runs of two different versions of vis, or runs with different +options. + + +CUDD 2.3.2 +---------- + +VIS-2.0 includes CUDD 2.3.2. Compared to the version that was +included in VIS-1.4, the new version contains a number of bug fixes +and several new functions. + +In particular, there is a new function that will compute the AND of +two BDDs only if the result does not require the creation of too many +nodes. This function is used by VIS-2.0 to make clustering of the +transition relation more robust. + + +Miscellaneous +------------- + +* Improved counterexample generation in model_check with -d3 and -d4. + +* Changes in verbosity level (-v option) of model_check. The new + verbosity levels are: + -v0: unchanged (minimum verbosity) + -v1: essential statistics (new) + -v2: equivalent to the old -v1 + -v3: equivalent to the old -v2 + +* Fixed bug and extended early termination detection in CTL model + checking. + +* Fixed bug in guided search for CTL model checking which affected + counterexample generation with global hints. + +* Vis no longer crashes when a directory name is specified in a + command line instead of a regular file name. + +* Fixed several bugs in approximate_model_check, + incremental_ctl_verification, and iterative_model_check. + +* The code in glu has been substantially rejuvenated. + +====================================================================== + +Version 1.4 + +Release 1.4 of VIS improves VIS 1.3 in the following areas: + + 1. Hybrid Image Computation + 2. Guided Search for Reachability Analysis and Invariant Checking + 3. Guided Search for CTL Model Checking + 4. Least Fix-point Machine-By-Machine Approximate FSM Traversal (LMBM) + 5. Iterative Abstraction-based Model Checking (IMC) + 6. Lazy Sifting + 7. SPFD-based Placement and Logic Optimization + 8. Truesim + 9. Arithmetic Functions with Extended Double Precision (EPD) +10. CUDD 2.3.1 +11. Miscellaneous + + +1. Hybrid Image Computation +--------------------------- +Image computation is the key step in fix-point computation. +Traditionally two techniques have been used: The transition relation +method is based on conjunction of a partitioned transition relation, +whereas the transition function method is based on splitting on an +input or output variable recursively. + +The hybrid method chooses either splitting or conjunction at each +recursion dynamically using the dependence matrix. This hybrid +approach combines, in a unified framework, conjunction, input and +output splitting, and a host of auxiliary techniques that can +significantly speed up the computation. See: I.-H. Moon, J.H. Kukula, +K. Ravi, F. Somenzi, "To Split or to Conjoin: The Question in Image +Computation", Proceedings of the Design Automation Conference (DAC), +pages 73-90, 2000. + +Also, the transition function method is implemented as a part of the +hybrid computation. The transition function method itself can be used +as an independent image method. However, we do not recommend to use +this method in general cases, even though it may work well for +approximate reachability analysis. The implementation of the +transition function method is basically for experimental purposes. + +** Usage: + set image_method hybrid + set image_method tfm + +Also refer to: print_hybrid_options and print_tfm_options + + +2. Guided Search for Reachability Analysis +------------------------------------------ +VIS-1.4 introduces the use of hints to guide the exploration of the +state space. This may result in orders-of-magnitude reductions in +time and space requirements. Good hints can often be found with the +help of simple heuristics by someone who understands the circuit well +enough to devise simulation stimuli or verification properties for it. +Hints are applied by constraining the transition relation of the +system to be verified. They specify possible values for (subsets of) +the primary inputs and state variables. The constrained traversal of +the state space may proceed much faster than the standard +breadth-first search, because the traversal with hints is designed to +produce smaller BDDs. Once all states reachable following the hints +have been visited, the system is unconstrained and reachability +analysis proceeds on the original system. Given enough resources, the +algorithm will therefore search all reachable states, unless a state +that violates the invariant is found. See: K. Ravi, F. Somenzi, +"Hints to accelerate Symbolic Traversal", Correct Hardware Design and +Verification Methods (CHARME), pages 250-264, 1999. + +** Usage: + compute_reach -g : guided symbolic state space + traverse + check_invariant -g : guided search for invariant + checking + +The file HintsFileName contains a series of hints. A hint is a +formula that does not contain any temporal operators, so hints_file +has the same syntax as a file of invariants used for check_invariant. + +Also refer to: model_check -g + + +3. Guided Search for CTL Model Checking +--------------------------------------- +Guided Search for CTL is an extension of Guided Search for +reachability. It works much along the same lines, and has the same +benefits. There are a few differences. First, for greatest fixpoints +(EG, AU, and AF), it uses overapproximations of the transition +relation, instead of underapproximations. Second, there is a +distinction between local and global hints. Local hints are the +default. They can be used for any kind of CTL formula, and will apply +all hints to a subformula before moving up in the parse tree. Global +hints are only applicable to ACTL and ECTL formulae, and evaluate the +entire formula once for every hint. See: R. Bloem, K. Ravi, and +F. Somenzi, "Symbolic Guided Search for CTL Model Checking", +Proceedings of the Design Automation Conference (DAC), pages 29-34, +2000. + +** usage: + model_check -g HintsFileName : perform model check guided by the + hints specified in HintsFileName + +Also refer to: compute_reach -g + check_invariant -g + + +4. Least Fix-point Machine-By-Machine Approximate FSM Traversal (LMBM) +---------------------------------------------------------------------- +The knowledge of the reachable states of a sequential circuit can +dramatically speed up optimization and model checking. Since exact +reachability may be intractable, approximate techniques are often +preferable. Least Fix-point MBM (LMBM) method is such a technique. +It is as efficient as MBM, but provably more accurate. LMBM can +compute RFBF-quality approximations for all the large ISCAS-89 +benchmark circuit in a total of less than 9000 seconds. For more +information, see: I.-H. Moon, J. Kukula, T. Shiple, F. Somenzi, "Least +Fixpoint Approximation for Reachability Analysis," International +Conference on Computer-Aided Design (ICCAD), pages 41-44, 1999. + +** Usage: + set ardc_traversal_method 4: LMBM(least fix-point MBM, default) + is selected for ARDC + set ardc_traversal_method 5: TLMBM(combination of LMBM and TFBF) + is selected for ARDC + model_check -D 3 : model checking with ARDCs + compute_reach -A 2 : compute over-approximate reachable + states + compute_reach -D : compute exact reachable states with + the help of ARDCs + check_invariant -D : check invariants with the help of + ARDCs + synthesize_network -r 3 : synthesize sequential network + with ARDCs + +Also refer to: print_ardc_options + + +5. Iterative Abstraction-Based Model Checking (IMC) +--------------------------------------------------- +VIS-1.4 introduces an automatic abstraction/refinement algorithm for +symbolic CTL model checking. This algorithm supports full CTL +language without fairness constraints. The algorithm begins with +initial upper- and/or lower-bound approximations that include some +exact sub-transition relations of a determined set of latches for a +given CTL formula. As long as a conclusive verification decision +can't be reached due to potentially false positives and negatives, the +system is refined. Two refinement methods are implemented: Latch Name +Sorting and Latch Affinity Scheduling. For more information, See: +J.-Y. Jang, I.-H. Moon, G.D. Hachtel, "Iterative Abstraction-based CTL +Model Checking," Design Automation and Test in Europe (DATE), pages +502-507, 2000. IMC supersedes the AMC package, which may disappear in +future releases. + +** Usage: + iterative_model_check -i 8 : iterative model checking with + incremental refinement step set + to 8 latches + iterative_model_check -r 0 : iterative model checking using + Latch Name Sorting refinement + scheduling + iterative_model_check -g 1 : iterative model checking using + Positive Operational Graph only + +Also refer to: model_check, approximate_model_check, +incremental_ctl_verification + + +6. Lazy Sifting +--------------- +Lazy sifting is a new variable reordering option that is specifically +designed for sequential verification with the transition relation +method (i.e., IWLS95 in VIS). Lazy sifting groups together +corresponding present state and next state variables only when it +expects the grouping to be beneficial. See: H. Higuchi and +F. Somenzi, "Lazy Group Sifting for Efficient Symbolic State Traversal +of FSMs," Proceedings of the International Conference on +Computer-Aided Design (ICCAD), pages 45-49, 1999. + +** Usage: + dynamic_var_ordering -e lazy_sift + + +7. SPFD-based placement and logic optimization +---------------------------------------------- +This is an algorithm based on Sets of Pairs of Functions to be +Distinguished (SPFDs) that combines logic and placement optimization +of combinational circuits mapped to LUT-based Field-Programmable Gate +Arrays to improve circuit area and speed. The flexibilities in the +circuit are represented by SPFDs. The package contains two commands: +spfd_pilo - perform SPFD-based placement-independent logic optimization; +and spfd_pdlo - simultaneous placement and logic optimization. + +spfd_pilo performs SPFD-based wire and node removal/replacement and +reprogramming of combinational circuits mapped to LUT-based FPGAs to +reduce the number of wires and nodes in the circuit. Instead of +computing the flexibilities for every node in the network at once, the +algorithm computes the flexibilities for one `cluster' at a time. +Working with clusters allows us to avoid the BDD explosion problem and +hence handle large circuits. The SPFDs are computed for the cluster +and the cluster nodes are reprogrammed based on the flexibility +derived. Switching activity (computed via simulation of user specified bit +vectors or randomly generated bit vectors) is used to drive the choice +of alternate function to be implemented at the node, in such a way that +the total switching activity in the circuit is minimized. In the absence +of bit vectors, an arbitrary implementation for a node is chosen from +the bounds represented by SPFDs. + +The command spfd_pdlo implements a technique that tightly links the +logic and placement optimization steps. The algorithm is based on +simulated annealing. Two types of moves (directed towards global +reduction in the cost function of total wire length), are performed: +(1) wire removal/replacement, and (2) swapping of a pair of blocks in +the FPGA. Feedback from placement is valuable in making informed +choice of a target wire during logic optimization moves. This command +produces a placement file which is used by VPR for routing. spfd_pdlo +can be used only if VIS is linked with VPR 4.22, an +FPGA place and route tool from the University of Toronto +(http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html). VPack, a tool to +convert circuits (mapped to FPGA blocks) in .BLIF format to the .net +format (used by VPR), is also needed. + +Please contact Balakrishna Kumthekar (kumtheka@avanticorp.com) for details +on integrating VPR with VIS. + +See: B. Kumthekar and F. Somenzi, "Power and Delay Reduction via +Simultaneous Logic and Placement Optimization in FPGAs," Design +Automation and Test in Europe (DATE), pages 202-207, 2000. + +** usage: + spfd_pilo -D : sets the cluster depth for SPFD + computation. + spfd_pilo -f : use simulation vectors from specified + file. These vectors are used to compute + switching activity of nodes in the circuit. + spfd_pilo -S : selects one of several methods to + choose the node to be optimized. + spfd_pilo -m : selects the heuristic to use in + optimizing a selected node. + + See 'help spfd_pilo' and 'help spfd_pdlo' for various options. + +8. Truesim +---------- +Simulates a network with a set of input vectors. Before calling this +command, the user should create a partition (using the command +build_partition_mdds). The simulation vectors can be provided by the +user (using -f vectors_file), or generated randomly. When -d option is +used, it performs event-driven true delay simulation. The fanout count +of the nodes is used as an estimate for the node delay. Primary inputs +are assumed to have arrival times of zero. + +9. Arithmetic Functions with extended double precision (EPD) +------------------------------------------------------------ +This is an arithmetic function package for extended double precision +format floating-point numbers. It supports the IEEE-754 double +(64-bit) precision floating-point number format: both the big_endian +and the little_endian. The range is from 2.2631E-4932 to +1.1897E+4932. This package is used internally to provide fast and +accurate counting of the states in large FSMs like those encountered +in approximate reachability analysis. + +10. New version of the CUDD package. +----------------------------------- +VIS-1.4 includes CUDD 2.3.1. Compared to the version that was +included in VIS-1.3, the new version contains a number of bug fixes +and several new functions. + +* Miscellaneous +--------------- + +** One bug in the CAL package has been fixed. It affected platforms without +the valloc function. + +** Changes in supported platforms. Support for SunOS 5.8 (Solaris +2.8) on the Intel x86 platform has been added. Ultrix and SunOs 4 are +no longer supported. + +** Change of Verbosity level for debugging in model_check +Debugging refers to the printing of an error-trace when a formula +fails. The new debug levels are: +-d0: no debugging (the old -d0) +-d1: minimal debugging, with less verbosity than the old -d1 had +-d2: minimal debugging with more verbosity (the old -d1) +-d3: recursive debugging (the old -d2) +-d4: interactive debugging (the old -d3) + +** Early termination in Model Checking. In limited cases, VIS will +terminate a model checking run before reaching a fixpoint. This may +lead to a speedup. + +** The set of fair states is not computed of there are no fairness +constraints. This may lead to a speedup of the model_check command. + +** Perl Script for pretty printing counter-examples. The Perl script +visdbgpp, contributed by Toshi Isogai, can be run on counterexamples +produced by vis to improve their readability. In particular, the +script collects the bits of vectors and displays them on a single +line. + +** Counterexample generation. The states on an error trace now lie +closer together, which means that, on average, fewer signal +transitions will occur. + +** Variable reordering. In flatten_hierarchy In VIS-1.4, variable +reordering is invoked automatically during flatten_hierarchy. + +** Changes of passing BDD cube arguments in VIS to CUDD. Some +arguments in the CUDD functions are BDD cubes that are generated by +the conjunctions of BDD variables on demand. VIS-1.4 pre-builds some +BDD cubes that do not change, such as for present state variables, +next state variables, and primary input variables. This speeds up +significantly large runs, especially for approximate reachability +analysis. + + +============================================================ + +Version 1.3 + +* Introduction + +Release 1.3 of VIS improves VIS 1.2 in the following areas: + +** Approximate Reachability Don't Cares (ARDCs) +** High Density Reachability Analysis. +** On-the-Fly Invariant Checking. +** Seeding Reachability Analysis via Simulation +** Forward Model Checking +** Abstraction-refinement based Incremental CTL Verification +** Synthesis +** State Transition Graph Restructuring for Low Power +** Miscellaneous + +* Approximate Reachability Don't Cares (ARDCs) + +VIS-1.3 includes the use of ARDCs in model checking and reachability +analysis. The power of using reachable states as a care set (RDCs) is +well known; however, computing reachable states exactly is intractable +in many large designs. ARDCs are an overapproximation of the +reachable states, which are then used as the care set. Computing +ARDCs is much cheaper than computing RDCs while their effectiveness in +speeding up model checking is comparable to that of RDCs. Therefore, +ARDCs are good for large designs, especially those in which exact +reachability analysis is intractable. See: I.-H. Moon, J.-Y. Jang, +G. D. Hachtel, F. Somenzi, "Approximate reachability don't cares for +CTL model checking", ICCAD'98. + +** Usage: + model_check -D 3 : model checking with ARDCs + compute_reach -A 2 : compute over-approximate reachable + states + compute_reach -D : compute exact reachable states with + the help of ARDCs + check_invariant -D : check invariants with the help of + ARDCs + synthesize_network -r 3 : synthesize sequential network + with ARDCs + +Also refer to: print_ardc_options + + +* High Density Reachability Analysis (HD) + +HD is an alternate approach to performing exact reachability +analysis. Using BDD subsetting techniques, the HD method tries to keep +the sizes of the BDDs small during the traversal. This is intended to +keep the memory occupation under control as well as make the traversal +more efficient by manipulating smaller BDDs. + +On large circuits, for which the default (breadth-first search) method +does not complete, HD is likely to find many more reachable states. +This is useful in invariant checking. +For mid-size circuits, HD is sometimes faster in completing +reachability analysis, but for smaller circuits, HD may result in too +much overhead. It is recommended to use this option when the default +method for reachability analysis fails (runs out of memory or takes +very long). Refer to Ravi and Somenzi, "High-density reachability +analysis", ICCAD'95. + +HD analysis only works with the CUDD package. + +** Usage: + compute_reach -A 1: reachability analysis with HD approach. + +Also refer to: print_hd_options + + +* On-the-Fly Invariant Checking + +Checking invariants is done by performing reachability analysis and +checking if all invariants hold in the reachable states. VIS-1.3 +does invariant checking during reachability computation (on-the-fly +verification). Invariants that fail are reported early, along with the +counter examples if requested. + +Since reachability analysis can be expensive, one may use HD in +invariant checking. For circuits on which the default reachability +analysis runs out of resources, HD will typically explore more +reachable states, and more invariants may prove false. However, the +counter examples provided by using HD may not be of shortest length. + +HD invariant checking only works with the CUDD package. + +** Usage: + check_invariant -A 1 : check_invariant where HD is used for + reachability analysis + +One may also start with an overapproximation of the reachable +states. In this case, if all invariants hold on the overapproximation, +verification is successfully completed. If not, the algorithm will +compute the exact reachable states as before, and check the +invariants that failed with the overapproximation. + +** Usage: + check_invariant -A 2 : check_invariant where over + approximation is used for reachability + analysis. + +* Seeding Reachability Analysis via Simulation + +A new option rch_simulate can be used to use simulation to augment the +set of initial states for reachability analysis. The value of the +variable is the number of random input vectors that are simulated. The +states reached in this way are considered as initial +states. Augmenting the set of initial states may sometimes lead to +faster reachability analysis, or may sometimes lead to better +underapproximations, when reachability analysis is not carried out to +completion. The commands affected by this option are compute_reach and +check_invariant. + +** Usage: + set rch_simulate n : simulate n vectors prior to + reachability analysis + + +* Forward Model Checking + +VIS-1.3 includes the capability of forward model checking based on +H. Iwashita, T. Nakata, F. Hirose, "CTL model checking based on +forward state traversal", ICCAD'96. Standard "backward" CTL model +checking uses only preimage computations. Forward model checking tries +to use image computations in place of preimage computations as much as +possible, because they are typically faster. +According to our experiments, forward model checking gives drastic +performance improvement in many designs, but we have also seen many +cases in which forward model checking does much worse. Performance +depends on the design. + +** Usage: + model_check -F : model checking based on forward traversal + + +* Incremental CTL Verification + +The command "incremental_ctl_verification" (aliased to "icv") +performs verification of CTL formulas following the incremental +paradigm described in A. Pardo, G. Hachtel, "Incremental CTL model +checking using BDD subsetting", DAC'98. The algorithm starts with an +initial simple approximation of the verification and then proceeds at +refining the different evaluations until the formula can be proved +conclusively. The approximation technique currently adopted makes use +of BDD approximation techniques. As implemented in release 1.3, +incremental_ctl_verification supports fairness constraints, but tends +to be less efficient than model_check when they are specified. + +Incremental verification works only with the CUDD package. + +** Usage: + incremental_ctl_verification [options] ctl_file + + +* Synthesis + +VIS 1.3 includes a new command "synthesize_network" (aliased to +"synth") to transform both combinational and sequential circuits into +multi-level boolean networks using symbolic factorization based on +Zero-suppressed BDDs (ZDDs). In the case of sequential circuits, only +the combinational part of the circuit is synthesized: state encoding +is not altered. The emphasis of this algorithm is on the reduction of +the number of literals in the factored form of the network. The final +multi-level circuit can be obtained in either the BLIF format or the +equation format. Designs described in BLIF or BLIF-MV format can be +used as an input to this command. However, multiple valued variables +are not supported. Hence, signals in the designs described in BLIF-MV +need to be restricted to binary values. + +Synthesis can be used only when VIS is linked with the CUDD package. + +** Usage: + synthesize_network [options] + +* STG Restructuring for Low Power + +VIS-1.3 includes a new command "restruct_fsm". This command +implements a State Transition Graph (STG) restructuring algorithm +that exploits the existence of equivalent states to decrease power +dissipation, not necessarily by collapsing the equivalence states, but +by redirecting transitions in the graph. This algorithm is based on +the monolithic transition relation. The complexity of the algorithm +in general increases with an increase in the size of the state +transition graph, which depends on the number of state variables and +primary inputs. The algorithm can handle circuits described in both +BLIF and BLIF-MV formats. However, multi-valued variables are not +supported. Also, the final synthesized circuit (network implementation +of the restructured STG) is available only in BLIF format. The +sequential circuit should have a single initial state. For more +details see, B. Kumthekar, I.-H. Moon, F. Somenzi, "A Symbolic +Algorithm for Low-Power Sequential Synthesis", ISLPED 97. + +STG restructuring works only with the CUDD package. + +** Usage: + restruct_fsm [options] + +* Miscellaneous + +** New versions of CUDD and CAL packages. +VIS-1.3 includes CUDD 2.3.0 and CAL 2.0.1. Compared to the versions +that were included in VIS-1.2, the new packages have better +performance and improved statistics reporting. + +** Changes in configure +Configure now defaults to using 32-bit pointers on DEC Alpha machines. +To use 64-bit pointers, invoke "configure" with "--enable-64." + +** gmake check +"gmake check" now consistently runs the local executable using the +examples in the master source directory. Previously, there were +different versions for local-area and central-area checks. + +** Native Compiler. +The configuration scripts now try to use the native C compiler (cc) by +default. The use of gcc can be forced by running configure with the +option --enable-gcc. On AIX and SunOS, however, only gcc is +supported. + +As a result, the following configuration options have been removed + + --with-comp-mode=solaris + --with-comp-mode=mips + --with-comp-mode=alpha32 + --with-comp-mode=alpha64 + +Configure now defaults to using 32-bit pointers on DEC Alpha machines. +To use 64-bit pointers, invoke "configure" with "--enable-64." + +** Changes in supported platforms. +VIS-1.3 has been tested under IRIX 5.3 with both cc and gcc. +VIS-1.3 has been tested under HP-UX with cc. (Previously only gcc was +supported.) +VIS-1.3 linked with the CAL BDD package currently does not work under +CYGWIN32. When the problems are fixed, we shall issue a patch. + +** Uniformity across platforms. +VIS-1.3 provides enhanced architecture independence. For the commands +model_check, approximate_model_check, compute_reach, +incremental_ctl_verification, check_invariant, and lang_empty, the runs +will be exactly the same on every platform with the same memory limits. +Previously, invocations of reordering, and hence BDD sizes could differ +from platform to platform. + +** Changes to static_order. +The static_order command has changed substantially. For combinational +circuits, VIS-1.2 and earlier releases effectively generated random +orders regardless of the method specified by the user. (Sequential +circuits did not have this problem.) The randomness of the orders was +due to a bug that has been fixed in VIS-1.3. For all +circuits---combinational and sequential---the default ordering method +is a new algorithm called "interleave." The new default method is +substantially more memory efficient than the previous default method +(merge_left). The quality of the resulting orders is comparable. + +** New -v option for dynamic_var_ordering. +The option -v 1 can be specified to cause VIS to write a one-line +message whenever dynamic reordering is executed. The message reports +the reduction in BDD or ZDD size, and on the time taken by reordering. +This option is only effective with CUDD. + +** New -i option for comb_verify and seq_verify. +It is now possible to print statistics on BDD usage and performance +when running combinational or sequential verification. This is done +by specifying the -i option for comb_verify and seq_verify. It is +important to notice that these two commands use a local BDD manager, +which is destroyed before control is returned to the user. It is not +therefore possible to use print_bdd_stats to inspect the statistics of +the BDD package when invoking either of the two commands. + +** Default method for build_partition_mdds changed to inout. +The default method has been changed to inout, because this has been +found to produce better results than frontier in many cases. The +frontier method can build the partition MDDs in more cases than the +inout method; the latter, however, tends to give better performance +during model checking. + +** set ctl_change_bracket [yes/no] +VIS-1.3 includes this set command option for the CTL parser. VL2MV +automatically converts "[]" to "<>" in node names, therefore the CTL +parser does the same thing. However, in some cases a user does not +want to change bracket type in the CTL formulas. This can be +accomplished by setting this set command option to "no." The default +is "yes". The commands affected are check_invariant, model_check, +approximate_model_check, and incremental_ctl_verification. + +** Printing time for model checking +VIS-1.3 includes printing time for model checking. If verbosity is set on, +then the model checking time for both each formula and total will be printed +out. + +** Incremental reachability analysis and invariant checking. +In VIS-1.3 it is possible to perform reachability analysis +incrementally. The -d option of compute_reach specifies how many +steps (image computations) should be performed at most before +returning control to the user. If compute_reach is invoked more than +once with the -d option, each time reachability analysis starts from +the previous result. If check_invariant is invoked after +compute_reach has been invoked with the -d option, the partial +reachability results are used to speed up verification. + +** Completeness and determinism check in flatten_hierarchy +The check for completeness and determinism performed by +flatten_hierarchy that was previously optional is now always +performed. The -b option to flatten_hierarchy and init_verify has no +effect in VIS-1.3 and is retained for compatibility with existing +scripts. It may disappear in future releases. Users of VIS-1.3 will +observe modest increases in the time taken to flatten the +hierarchy. + + + +Version 1.2 + +* Introduction + +** Improvements + +*** Over 10x performance improvement in model checking for many examples +*** extended CTL syntax +*** better access to the BDD parameters and statistics +*** enhanced user interface +*** improved portability and flexibility of configuration + +** New verification algorithms + +*** approximate_model_check: model checking of ACTL formulae for systems + that are too large for model_check +*** res_verify: residue based verification of arithmetic circuits + +* Performance improvement in model checking + +** We have changed image computation (the underlying operation of + model checking) to make the best use of don't care sets. The don't + cares arise from unreachable states, and using them appropriately + reduces the BDD sizes significantly, leading to improved + performance of model checking. In addition, we have fixed a + performance bug that caused repeated computation of simplified + transition relations. We performed a performance comparison with + VIS 1.1 on a set of examples, and on some cases we observed more + than 30x performance improvement. In fact, on some examples VIS 1.2 + could finish model checking in about 26 secs whereas VIS 1.1 took + about 2400 secs. + +** The model checking runs that use don't cares (-D option different + from 0) are those that benefit the most from the changes in VIS + 1.2. In general it is not trivial to tell whether -D 1 or -D 0 will + produce the faster CPU time. An empirical approach consists of + running "compute_reach -t 300" (reachability for 5 + minutes). Depending upon the progress in reachable state + computation, one can then invoke model checking with -D 0 or -D 1. + +* Approximate Model Checking + +** VIS 1.2 includes a new command approximate_model_check, a model + checker that performs ACTL model checking on an abstracted and + flattened network. The command is designed to tackle the state + explosion problem we encounter when dealing with large and complex + circuits. Based on the initial size of the group (of latches), the + command constructs an over- or under-approximation of the + transition relation of the system. These approximations may not + contain every detail of the exact system. However they may contain + enough information to determine whether the formula is positive or + negative. Starting from an initial coarse approximation, the + command makes its effort to prove whether the given ACTL formula is + true or false. When the procedure fails to prove correctness of the + formula with initial approximations, it automatically refines the + approximations. It repeats the process until the algorithm produces + a reliable result or the available resources are exhausted. For + detailed description, refer to the relevant manual page ("help + approximate_model_check from" the VIS shell). + +** approximate_model_check is faster than model_check for some of the + VIS 1.2 distribution examples. However, significant improvements + over the exact computation can be seen for even larger examples + such as s15850. The current version of the code does not perform + any refinements. The refinement techniques similar to the "machine + by machine" and "frame by frame" may be implemented in future + version. Furthermore, more aggressive reduction of the initial + states can be performed while proving whether the ACTL formula is + positive. The reduction of the initial states are made for each + level of the lattice of approximations in this version. + +** The current version includes two distinct "grouping method". More + experiments are required to determine better grouping method(s). + +** The current version only supports ACTL formulae. + +* Residue Based Verification + +** VIS 1.2 includes a new command "res_verify" for combinational + verification based on residue arithmetic. Residue-based + verification is especially suited to multipliers and other + arithmetic circuits. See below, however, for a discussion of the + application of "res_verify" to other circuits. This command is only + available if VIS has been linked with the cu library (default). + +** The command res_verify takes two circuits (specification and + implementation) whose equivalence is to be established, and an + order for the outputs. The order for the outputs allows res_verify + to interpret the output vectors as integers. Based on this + interpretation, res_verify applies the Chinese remainder theorem to + the equivalence verification: the specification and the + implementation are equivalent if, for a suitable set of relatively + prime numbers, the residues of their outputs are equivalent. The + residues are computed by composing the two circuits into a function + representing the residue computation. + +** res_verify allows the user to specify what pairs of outputs of the + circuits should be compared directly by building their BDDs, + instead of computing residues for them. The -d option controls + this feature; n pairs of outputs, starting from the least + significant bits of the output vectors, are verified directly if -d + n is specified. + +** As a special case, the user can specify -d all. This causes + res_verify to directly verify all the output pairs, effectively + foregoing residue verification. This can be useful for + non-arithmetic circuits that are not suited to residue + verification. In this case res_verify works similarly to + comb_verify, with a significant exception: res_verify verifies one + output at the time. This often translates into reduced memory + requirements and CPU times. + +** res_verify can be applied to pairs of sequential circuits with the + same state encoding. Several options and VIS variables control the + detailed behavior of the command. Refer to the on-line + documentation for the details (help res_verify). + + +* Extended CTL Syntax + +** Users can now write CTL fomulae using vector notation. Vector + variables have the form of var[i:j] and each bit can be written as + either var or var[i]. For instance, the following formulae are + valid. + + counter[3:0] = 10 + counter[3:0] = b1010 + counter[3:0] = {1,2,10} + + The formula in the last line is true if counter has one of the listed + values. + +** Macros can be defined and used in CTL formulae to stand for subformulae. + For instance: + + \define VALID_INPUT (a[3:0]=0 -> b=1) + + defines the macro VALID_INPUT, which can be later used in a formula + like this: + + AG(start=1 * \VALID_INPUT -> AF(res[7:0]=b10101010)); + +** The CTL parser allows users to write the following formulae: + + var1 == var2 + var1[i:j] == var2[k:l] + + The first formula is equivalent to (var1=1) * (var2=1) + (var1=0) * + (var2=0) and currently is allowed only in the boolean domain. (It + cannot be used for variables of enumerated types.) The second formula + can be used if the lengths of two vectors match. + +** AX:n(f) is allowed as a shorthand for AX(AX(...AX(f)...)), where n + is the number of invocations of AX. EX:n(f) is defined similarly. + + +* BDD manipulation + +** VIS 1.2 incorporates Release 2.1.1 of CUDD and an improved version of + CAL. Improvements specific to CUDD and relevant to VIS are: + +** All reordering methods preserve variable groups. Variable groups are + created by VIS to keep corresponding present and next state variables + adjacent. In VIS 1.1 only method "sift" retained the variable groups. + +** CUDD determines the maximum size of the computed table based on the + amount of main memory available. On systems where getrlimit is + available, the datasize limit is used to determine how much memory + is available. CUDD allows the computed table to grow up to one + fourth of that amount. This feature allows VIS to self-calibrate + for optimum performance. The computed table will not necessarily + grow to its maximum value, and VIS is not guaranteed to stay within + the memory bound returned by getrlimit. If the datasize limit is + not set, if getrlimit is not available, or if it is available but + does not know about datasize, then a suitable default value is used + instead. The default value is normally 16MB. This value can be + changed at configuration time. Even a value as low as 16MB gives a + reasonably sized computed table for small-medium runs. However, for + large runs--hundreds of MB--the ability to set the memory limit may + produce much faster execution. The maximum computed table size can + be set also from within VIS with set_bdd_parameters. + +** CUDD now provides access to the package parameters and statistics + via the commands bdd_print_stats and set_bdd_parameters. The + parameters that can be set control the sizing of CUDD's main data + structures (unique table and computed table) and many aspects of + the variable reordering algorithms. The parameters reported refer + to memory occupation, computed table (cache) performance, and + variable reordering. + +** It is now possible to impose a limit on the number of variable + swaps performed during reordering. + + +* User Interface + +** New VIS command "set_bdd_parameters". + + The command "print_bdd_stats" prints two sets of data from the + underlying BDD package, parameters and statistics. The parameters + can be modified as follows. By using the "set" command, set the + value of a variable whose prefix is "BDD." and whose suffix is + exactly the name seen in the output of the command + "print_bdd_stats", for example: + + vis> set "BDD.Garbage collection enabled" no + + Then, the command "set_bdd_parameters" reprograms the underlying BDD + core based on the values of the variables of this type. + +** Readline Library. + + The Readline library is a GNU package that provides command line + editing, command history, and file name completion capabilities. If + the system where VIS is built has this library and it is installed + so that the linker can use it, the configure script will detect + this situation and the executable will be linked with + libreadline.a. + +** Variable Interpolation. + + The VIS shell now allows variable interpolation. For instance, typing + + vis> echo $open_path + + causes vis to echo the current value of open_path. Typing + + vis> set open_path $open_path:/some/path + + will append /some/path to open_path. Variable interpolation can be + used also to exchange parameters with scripts. This allows reliable + parameter passing even when "source" is called with options. + +** PAGER + + If the PAGER environment variable is set, VIS uses it to choose the + program used to display the help pages. If PAGER is not set, VIS + uses 'more.' + +** File Buffering. + + The output of VIS when run in batch mode is now line buffered on + systems that provide setvbuf. This makes it more convenient to + observe the evolution of long-running jobs. + +* Portability and Configuration + +** VIS 1.2 runs on two new platforms: IBM RS6000 running AIX and Intel + Pentium running Windows95 with Gnu-Win32. The Gnu-Win32 environment + (http://www.cygnus.com/misc/gnu-win32/) is a freely available GNU + environment for Windows 95 and Windows NT. + +** This release of VIS has been tested with some native compilers + (Ultrix, Solaris, Digital Unix). In particular, when building with + the native compiler on a DEC Alpha running Digital Unix, the option + is provided to compile with 32 bit pointers. Please see the README + file for specific instructions on how to compile with the different + native compilers. + +** The GLU library now provides portable functions for random number + generation and sorting that help make results reproducible across + different platforms. + +** The GLU library now provides a function to read the available + memory (based on getrlimit). This function is currently used by the + CUDD package to choose the optimal size of data structures. For + systems without getrlimit a suitable default is provided and can be + changed at configuration time. + + + +Version 1.1 + +* Introduction + +** Improvements over 1.0 + +*** multiple BDD packages +*** more synthesis capability +*** hierarchy restructuring +*** new methods for partitioning +*** automatic reduction during model checking +*** support for multi-phase clocking and transparent latches +*** support for invoking standard scripts +*** support for graphically viewing simulation output + + These significantly improve VIS's performance in terms of computer + time, memory usage, and ability to complete on larger designs. + Further, additional capability for synthesis is provided. + + One particular example of the improved performance of VIS 1.1 is the + first (to our knowledge) reported exact state space traversal of + benchmark s5378. It was run with the cu BDD package on an Alpha + 300MHz (using 32 bit pointers). The datasize limit was set at + 1GB. The process grew to about 440MB. Dynamic reordering was enabled + all the time and occurred more than 50 times. The orginal ISCAS89 + circuit was used, which has 179 latches. + +*** Multiple BDD packages + + We have added the capability to run VIS with three different BDD + packages, cu - from University of Colorado, cal - from UC Berkeley + and cmu - from Carnegie Mellon University. Further details are in + the section "BDD Packages" below. + +*** Synthesis + + VIS synthesis is represented by a number of commands, write_blif, + read_blif, collapse_child, and decompose_child. These allow the + user to manipulate the hierarchy and to write blif files to SIS + and then later read in an optimized file. Each of these commands + can be executed on sub-nodes or sub-trees of the + hierarchy. Details about these commands are in the section + "Collapsing and decomposing a hierarchy" and "Reading and writing + blif files" below. + +*** Partitioning + + Partitioning in VIS is used in a number of places: simulation, + model checking, computing the set of reached states, etc. Recall + that the VIS data structure is simply a set of tables with outputs + (signals) which can be inputs to other tables. There are also + primary input signals and inputs from latches. Some signals are + primary outputs and/or inputs to latches. A partition is simply a + subset of nodes (signals) which are to be preserved, the remaining + are to be eliminated. Of course, primary outputs and inputs to + latches cannot be eliminated. We provide some new partitioning + methods as described below (in the section "Creating partitions of + the network"). + + In many cases, a formula to be model checked does not depend on + all of the signals in the design. In such cases, the design can be + reduced to include only signals in the transitive fan-in of the + latches mentioned in the CTL formula plus the fairness + constraints. This reduction can result in vastly more efficient + model checking. + +*** Multi-phase clocking + + One question that is asked frequently is how does VIS support + multi-phase clocking and transparent latches in Verilog. We + provide this capability in our Verilog compiler "vl2mv" and detail + this in a document that describes exactly the steps to be + taken. This document is in the vis-1.1/doc directory and is called + two_phase.ps. + +*** Standard scripts + + Standard scripts have been provided which should help the new user + select certain options that we have determined to be good choices + on a variety of examples. The scripts are divided into two + categories: simple - which are recommended for small/medium + examples, and robust - recommended for large examples where + completion rather than compute time is the most important + concern. The 10 scripts provided are summarized below in the + section "Standard scripts". + +*** xsimv + + Finally, we have included "xsimv", which provides a graphical + method for viewing simulation output. This is detailed in the + section "Using Xsimv". + +* Multiple BDD packages + + We have added the capability to run VIS with three different BDD + packages, cu - from University of Colorado, cal - from UC Berkeley + and cmu - from Carnegie Mellon University. The commands for these + respectively are vis-cu, vis-cal, and vis-cmu. The cmu package is + the same as in VIS 1.0. The cu package is very strong in having a + fast dynamic variable reordering capability. In addition, cu has + been upgraded for the DEC alpha machines so that it uses 32 bit + pointers, instead of 64 bit pointers; hence it realizes a factor of + 2 in memory savings on such machines. The other two packages remain + to be upgraded for 32 bit pointers on the DEC alphas. The cal + package uses the BFS BDD technique and is particularly good at + avoiding paging on large designs. For most problems, we recommend + the cu package. + +* Reading and writing BLIF files + + The "write_blif" command in vis-1.0 only wrote out the combinational + part of an hnode (a node of the hierarchy). Now this functionality + is performed by the "write_blif -c" command. Other options have been + added as well. The options are: + + (1) write_blif -l + + writes out the latches of the hnode as well. Additionally, all + latch IOs are made into POs in the blif file that is + created. This ensures that the these nodes do not get optimized + away by SIS, so that mv-latches can be re-inserted by the + read_blif command in VIS. + + (2) write_blif -c + + same as "write_blif" of vis-1.0 + + (3) write_blif + + writes out latches of the hnode, but does not make latch IOs + into POs in the blif file. The .blif and .enc files that are + generated by this command currently cannot be guaranteed to read + back into VIS correctly using the read_blif command. + + (4) write_blif -R + + recursively writes out the entire hnode hierarchy rooted at the + current hnode, to a blif file. This command opens up a direct + path from Verilog to pure blif files and hence to synthesis in + the SIS framework. For this command to work, 1) all variables + in the hnode hierarchy rooted at the current hnode must be + binary, 2) all tables should be deterministic, and 3) there must + be a unique initial state. + +* Collapsing and decomposing a hierarchy + + If the user travels (via "cd" commands) to a particular node in the + hierarchy and does a "write_blif", only the logic in the *current* + node gets written out. The user might want to collapse some of the + child nodes together and do synthesis in the "collapsed" node. The + "collapse_child" command does just that. The usage is: + + collapse_child + + and the effect is that the child node is absorbed by the parent. By + successive invocations of this command, multiple nodes can be + collapsed into a single node. + + "decompose_child" is a command that effects the inverse operation of + collapse_child. The user can specify components of the current node + to be grouped as a separate newly created child node. The user must + also specify the name of the new child. Successive invocations of + "decompose_child" can be used to effect multiple + decompositions. "decompose_child" provides the infra-structure for + implementing and testing FSM decomposition algorithms (to appear + later). + + Together, collapse_child and decompose_child provide powerful + primitives that can be used to restructure the design hierarchy. + +* Creating a flattened network for verification + + The important change to note is the "-b" option in the + "flatten_hierarchy" command. By default this option is off, + implying that the system is not checked for complete and + deterministic specification. However, if the given design does not + meet this criteria, model checking may produce wrong results. (Note: + In VIS nondeterminism is handled by providing pseudo-inputs. + Internally all the tables are deterministic and completely + specified.) Invoking this "-b" option forces the necessary + checking. However this can be computationally expensive. The best + strategy is to invoke "flatten_hierarchy" with "-b" option the first + time and if the check passes, use it without "-b" option in + subsequent runs. + +* Creating partitions of the network + + Three new methods for creating partitions for the "build_partition_mdds" + command have been added. + + - partial + + This can be used to perform partitioning while forcing a + user-specified set of signals (nodes) in the partition. The + set of nodes to be included can either be supplied in a file, + or on the command line. + + - boundary + + In this method, all nodes that are sub-circuit IOs are + included in the partition. + + - frontier + + In this method (the default method), the user specifies a + parameter "partition_threshold" which is used to include an + intermediate variable whenever the BDD size for a node in the + network increases beyond the threshold value. This method is + very useful when it is not possible to create the next state + functions in terms of primary inputs because of large BDD + sizes. This method encompasses both "in_out" and "total" + partitioning methods (corresponds to very large and 0 value of + "partition_threshold", respectively). The parameter can be set + by invoking the following from the VIS commandline: "set + partition_threshold ". + +* Reachability computation + + A few new options to reachability computation have been added + (command: compute_reach). + + + -d depthValue + + Used to perform reachability up to a certain number of + steps. + + -r threshold_value + + Invokes dynamic reordering of variables ONCE, after the + size of the reached state set crosses the threshold_value. + +* CTL Syntax + + For Verilog compatibility, && and || are supported in addition to * + (Boolean AND) and + (Boolean OR) respectively. + +* Model checking + + The mc command, by default, now reduces the model FSM with respect + to the union of all the formulas in the CTL file and uses the + reachability don't cares (thus reachablilty is done first before any + model checking). Also, -d 0 is the default now, i.e. no error trace + is computed. The -r option has been modified and a new capability + for sharing sub-formulas has been added. + + -r + + (This option has been modified). If this option is used, each + formula is model checked individually on an FSM reduced with + respect to the formula. + + -c + + This disables the default that sub-formulas of the formulas given + in the CTL file are shared. The sharing of sub-formulas makes sure + that a sub-formula in the set of all sub-formulas of the formulas + in the CTL file is evaluated only once. If both -r (formula + dependent FSM reduction) or "-D 1" (use reachability don't cares) + are enabled, this facility is automatically disabled. (Note that + currently if the same sub-formula occurs more than once within a + single formula, it may be checked twice.) + +* Standard scripts + + There are 10 standard scripts provided (in the "share" directory), + divided into two categories, simple and robust. The simple scripts + work best on small/medium size examples. The robust scripts are + recommended for large problems where the objective is to complete + the computation without too much concern for computation time. Below + are the scripts with their required arguments. All scripts assume + that a BLIV-MV file has already been read in. + + script_generic.simple + script_compute_reach.simple + script_model_check.simple foo.ctl + script_fair_model_check.simple foo.fair foo.ctl + script_lang_empty_check.simple foo.fair + + script_generic.robust + script_compute_reach.robust + script_model_check.robust foo.ctl + script_fair_model_check.robust foo.fair foo.ctl + script_lang_empty_check.robust foo.fair + + In all cases, "script_generic" is a preample to the other scripts. + Generally, we recommend trying a "simple" script first, since it + should be the fastest. + +* Using "xsimv" + + Before invoking xsimv, please modify the first line of the file + "xsimv" and put the complete path name for "expectk". + + xsimv is invoked by the command + + xsimv + + where is a file produced by the vis command + + simulate -n -o + + When xsimv executes, it comes up with a window with 4 buttons in it, + GO, ReDraw, Save and Quit. At the same time it produces a file, + "strk.simv", with the signal names in it. For example + + sensor.rand_choice + timer.rand_choice + car_present + farm_light + hwy_light + timer.state + + If only a subset of these names are required the user can edit this + file and comment out a line using "#". For example, + + #sensor.rand_choice + #timer.rand_choice + car_present + farm_light + hwy_light + timer.state + + will cause the first two signals' simulation to be not displayed. + + Pushing GO or ReDraw then produces a new window with the simulation + results shown where time increases from left to right. The signal + value names not commented out are shown vertically, one for each + row. The "edit strk.simv" and REDRAW sequence can be iterated. + + +Version 1.0 + +* Initial release Index: vis_dev/vis-2.1/README =================================================================== --- vis_dev/vis-2.1/README (revision 11) +++ vis_dev/vis-2.1/README (revision 11) @@ -0,0 +1,454 @@ +This is release 2.1 of VIS, a system for verifying and synthesizing +finite-state systems. VIS builds on GLU, a collection of BDD packages +and low-level utilities. + +To build VIS and GLU, you will need + + * An ANSI C compiler (gcc will do, as will several versions of cc) + * GNU Flex version 2.5 or greater + * GNU Bison version 1.22 or greater + * GNU's make utility + * GNU's gzip utility + * Approximately 90 MB of free disk space for the build of both + vis and glu + * Approximately 60 MB of free disk space for the installation + +--------------------------------------------------------------------------- +* Useful Addresses + +The most recent version of vl2mv, the Verilog compiler designed to work +with VIS: + + ftp://vlsi.colorado.edu/pub/vis/vl2mv-2.01.tar.gz + +The most recent versions of VIS and GLU: + + ftp://vlsi.colorado.edu/pub/vis/{glu-2.1.tar.gz,vis-2.1.tar.gz} + +The VIS home page, which includes additional documentation: + + http://vlsi.colorado.edu/~vis + +The most recent version of the GNU tools: + + http://www.gnu.org + +The most recent version of perl, which is required to run 'visdbgpp': + + http://www.cpan.org + +The most recent version of expectk, which is required to run 'xsimv': + + http://expect.nist.gov + +The most recent version of Tcl/Tk, which is required to run 'expectk': + + http://www.scriptics.com/ + +Optionally, the most recent version of zchaff, the SAT solver which can +be used to CirCUs (included in VIS) to execute the bounded_model_check command: + + http://www.ee.princeton.edu/~chaff/ + +--------------------------------------------------------------------------- +* Platforms + +This is the list of architecture/operating system/compiler +combinations we have tested. (For installation with compilers marked +with (*) please refer to the Platform Specific Instructions.) + + * IBM RISC System/6000 / AIX Version 4.3.3 / gcc(*) + * Intel ix86 / Linux / gcc, g++, icc + * Intel ix86 / Windows XP with Cygwin 1.5.16-1 / gcc, g++(*) + * Intel ia64 / Linux / gcc + * Sun Sparc/ Solaris 2.8 / gcc, g++, cc(*) + +The following instructions are for the generic build process. Before +building the tool please refer to the section "Platform Specific +Instructions". + +--------------------------------------------------------------------------- +* Building VIS + +To build a VIS executable for a single operating system: + +1. Download the most recent versions of VIS and GLU from the address + above into a convenient directory, (e.g., /tmp). + +2. Move to where you would like to build VIS and GLU and unpack the + distributions: + + % cd /home/vis # for example + % gzip -dc /tmp/glu-2.1.tar.gz | tar xf - + % gzip -dc /tmp/vis-2.1.tar.gz | tar xf - + +3. Move into the glu-2.1 directory and run configure, which will + determine some system-specific parameters and create the Makefile: + + % cd glu-2.1 + % ./configure + + By default, this will use your system's native compiler. To use gcc, + + % ./configure --enable-gcc + + (You may want to do this because you don't have the native compiler + installed or because it is not ANSI.) + + Note: For platforms where VIS is not supported for the native compiler, + the default compiler is set to gcc. + + Note: Not all checks in ./configure will return "yes." This is + normal and should not affect compilation. However, do be concerned + with any warnings "configure" produces. + + Note: Occasionally, configure will make a bad guess or will choose + a default you do not want. In this case, simply edit the Makefile + after configure finishes. + + Note: You may want to specify parameters to configure -- see the + "Installing" sections below. + + Note: To parallelize the installation procedure, you can begin steps + 5 and 6 at this point, as long as step 4 completes before step 6 + (since VIS must link against the GLU library). + + Note: The Makefile by default uses the "-g" option for + compilation. The resultant "vis" executable may be much larger than + the executable generated without using the "-g" option. Using the + "-g" option however, provides debugging capabilities. + + Note: The following is of interest only to people developing code + within vis. For full debugging support, specify + --with-comp-mode=debug. This will turn off optimization, and turn + on the assertions (sanity checks) in the code. Similarly, + --with-comp-mode=purify and --with-comp-mode=quantify will link vis + with IBM Rational's Purify or Quantify tool, if it is installed. + +4. Build the GLU system by running GNU's gmake utility: + + % gmake + + You may not have GNU make installed on your system under the name + 'gmake' -- try make. If this fails, you probably need the latest + version of GNU's make program -- download it from the address + above. + +5. Move into the vis-2.1 directory and run configure: + + % cd ../vis-2.1 + % ./configure + + By default, this will use your system's native compiler. To use gcc, + + % ./configure --enable-gcc + + (You may wish to do this because you don't have the native compiler + installed or because it is not ANSI.) + + Note: For platforms where VIS is not supported for the native compiler, + the default compiler is set to gcc. + + Note: If you supplied compilation-option flags (e.g., --enable-64) + to the GLU configure, provide the same to the VIS configure. + + Note: Not all checks in ./configure will return "yes." This is + normal and should not affect compilation. However, do be concerned + with any warnings "configure" produces. + + Note: Occasionally, configure will make a bad guess or will choose + a default you do not want. In this case, simply edit the Makefile + after configure finishes. + + Note: You may want to specify parameters to configure -- see the + "Installing" sections below. + + Note: You may want to remove the "-g" flag from the make file. See + under 3. + +6. Build the VIS system by running GNU's gmake utility: + + % gmake + + This builds an executable "vis" in the current directory. + + WARNING: If you are not successful in building a VIS executable, + double check that you are using Flex version 2.5 or greater (check + using "flex -V") and GNU Bison version 1.22 or greater (check with + "bison -V"). Having out-of-date versions of these programs can + lead to obscure compilation and linking errors. You can download + the new versions from the GNU FTP address above. + + VIS expects to find master.visrc, two .nawk files, and a directory + of help files in the directory given by the environment variable + VIS_LIBRARY_PATH. Set this to the "share" directory in the source + tree: + + % setenv VIS_LIBRARY_PATH $cwd/share + +7. OPTIONAL: Verify VIS works by running it on some of the examples + included in the distribution: + + % gmake check + + This step finishes in less than five minutes on most machines + and requires approximately 32MB of RAM. + +--------------------------------------------------------------------------- +* Installing GLU: + +Developers will want to install the GLU library and its associated header +files in a central area: + +To install the GLU library and its header files, type, while in the +glu-2.1 directory, + + % gmake install + +By default, this will put libraries and headers in /usr/local/lib +and /usr/local/include respectively. To choose a different +location, provide a default prefix when you invoke configure, e.g., +to install in /projects/glu/bin, etc., use + + % ./configure --prefix=/projects/glu + +when configuring GLU. Note that "tilde expansion" doesn't work for the +prefix (i.e., don't specify --prefix=~smith/glu). + +--------------------------------------------------------------------------- +* Installing VIS: + +Administrators and people who want to discard the source files after +building VIS may install VIS in a central area: + +To install the VIS executable, library, headers, and help files, type, +while in the vis-2.1 directory, + + % gmake install + +By default, this will put binaries, libraries, headers, and help files +in /usr/local/bin, /usr/local/lib, /usr/local/include, and +/usr/local/share respectively. To choose a different location, +provide a default prefix when you invoke configure, e.g., to install +in /projects/vis/bin, etc., use + + % ./configure --prefix=/projects/vis + +when configuring VIS. + +"gmake clean" removes all the files generated during "gmake." This is +useful when you want to rebuild VIS with a different prefix, +different compiler options, etc. + +During configure if --prefix option is used, files found in the +"share" directory will be installed in $prefix/share/vis; otherwise +they will be installed in /usr/local/share/vis by default. Set the +environment variable "VIS_LIBRARY_PATH" to the appropriate directory so +that VIS can find master.visrc, the two .nawk files and the "help" +directory. The above mentioned files can also be present in a +different directory, but "VIS_LIBRARY_PATH" should be set to that +directory. For example, + + % setenv VIS_LIBRARY_PATH /projects/vis/common + +--------------------------------------------------------------------------- +* Installation for multiple platforms + +To install VIS on multiple operating systems depending on the same +source tree, see the file "INSTALL" included in the distribution. + +In this case, when the build directory is different from the source +directory, it's necessary to configure VIS to look elsewhere for the +GLU libraries and headers, e.g., + + % ./configure --with-glu-libdir=/tmp/glu-2.1/alpha \ + --with-glu-incdir=/tmp/glu-2.1/include + +Also, make sure that there is an obj/ directory in the directory in +which you are compiling. See ./configure --help for more information. + +--------------------------------------------------------------------------- +* Selecting a different BDD package + +To create VIS with a different BDD library (say cal) than the default +one (cu), use the following command: + + %./configure --with-bdd=cal + +The same can be achieved by changing the "BDDPKG" definition in the +Makefile from "cu" to "cal". + +VIS can work with three different BDD packages (cmu, cal, cu), all of +which are supplied with glu-2.1. However, some commands in VIS are +available only with the cu BDD package. Please refer to the NEWS file +for more details. + +--------------------------------------------------------------------------- +To create three versions of VIS, each with different BDD libraries, +run 'gmake allprods'. This will create vis-cal, vis-cu, and +vis-cmu. To verify whether all these executables are compiled +correctly, use 'gmake check-allprods' at the end. +--------------------------------------------------------------------------- + +* Files in the VIS distribution: + +README This file. + +INSTALL Generic installation instructions for use with configure, + including instructions for simultaneous multi-platform + builds. These are not specific to VIS nor GLU, so don't + follow them word for word. + +NEWS Changes since the last version/release. + +configure An executable shell script that creates "Makefile" from + Makefile.in after determining system-specific parameters. + +configure.in Autoconf source for generating the configure file. + Only needed if you want to modify the configure script. + +Makefile.in The template Makefile. + +vis.1 Unix-style man page documenting vis invocation + parameters. + +xsimv An expectk script to visualize VIS simulation traces. + +helpers/ Programs useful during configuration and building + install-sh Shell scripts used by "gmake install." + mkinstalldirs + config.guess + config.sub + dependency.make + +doc/vis_user.ps + A user's manual for the VIS system, describing our approach + to formal verification and how to use the tool. + +doc/blifmv.ps Documentation on the BLIF-MV file format, a low-level + language for specifying designs. + +doc/ctl.ps Documentation on the CTL file format, a language + for specifying properties. + +examples/*/ A collection of small systems and properties to be + verified. Used by "gmake check." + +share/master.visrc + A VIS script designed to be run automatically at + start-up: contains aliases for commonly used commands + and some default parameter settings. + +share/*.nawk nawk scripts for converting BLIF files to BLIF-MV, + used by the "read_blif" command. + +share/script* Sample scripts. + +share/sislib.mv Library of gates used by models translated by vl2mv + from gate-level Verilog descriptions. + +share/visdbgpp A perl script to pretty-print counterexamples produced + by the model_check and check_invariant commands. + +share/help/ ASCII documentation for each VIS command, accessible + through the "help" command within VIS. + +src/*/ Source code and headers for the VIS system. + +obj/ Directory where .o files and generated .c files are + placed during a build. + +checkresults/ Directory where tests (i.e., gmake check) are run. + Results of the tests are placed here. The directory + is only created when 'gmake check' is run. + +--------------------------------------------------------------------------- +* Platform Specific Instructions + +Note: some instructions apply to platforms we no longer support. + +** Little-endian machines: + + vis-cal will occasionally fail when compiled with + --with-comp-mode=debug on little-endian machines like the Alphas and + the Intel ix86 CPUs. + +** DEC Alpha: + + Warnings about MIN and MAX are harmless. + Warnings about Olimit are harmless. They can be gotten rid of by + increasing the number following Olimit under CFLAGS. + + By default, configure uses 32-bit pointers when using DEC's OSF/1 C + compiler for the Alpha, which is more efficient if your processes + use less than 2GB. To use 64-bit pointers, invoke configure as follows: + + % ./configure --enable-64 + + The gcc compiler always compiles with 64-bit pointers. + + Note that you must also specify this flag when configuring GLU. + + Some machines do not have the program 'om'. In this case, simply + removing the om flag from LDFLAGS is sufficient to complete + compilation. + +** Intel A64: + + vis-cal compiled with gcc 3.2.3 crashes when sifting is invoked. + +** Solaris (Sparc and ix86): + + If Sun's C compiler is not installed on your system, use gcc + (./configure --enable-gcc). + + Warnings about redefined symbol are harmless, so are the warnings + that say "end-of-loop code not reached". + + The sun cc compiler (Workshop 6 update 1) on ix86 appears to have a + bug in the optimization routines. The -xO4 an -xO5 compiler options + will make vis crash in some runs. As a safety precaution, we have + changed the optimization flag to be -xO3 for all Sun platforms that + use the cc compiler. You can try higher optimization flags on your + machine. In general, it is hard to determine cc options that will + give optimal results on every platform, so it may pay off to play + atound with the optimization options. + +** HP-UX: + + Some operating systems on HP machines have a built-in command called + "vis" under /usr/ucb. In light of this, be careful about the + definition of your path. + +** MS Windows with Cygwin: + + You need Red Hat's Cygwin environment (freely available from + http://www.cygwin.com) to build GLU and VIS. + + With Cygwin the configuration script automatically selects gcc. + +** AIX: + + The configuration script automatically selects gcc. vis-cal + occasionally produces incorrect results when optimization is turned + on. If you plan to use vis-cal with AIX, you should configure glu + and vis with --with-comp-mode=debug. + +** IRIX + + When compiling VIS with gcc, you may get the error message + + gcc.x: cannot specify -o with -c or -S and multiple compilations + + If this happens, edit Makefile, and replace the definition of + VERDATE with the following: + + VERDATE := -DCUR_DATE="\"N/A\"" -DCUR_VER="\"$(PRODUCT)-$(VERSION)\"" + +--------------------------------------------------------------------------- +* Verilog front-end + +vl2mv, written by Szu-Tsung Cheng, allows one to translate a subset of +Verilog into blif-MV, the input format of VIS. The most recent +version of vl2mv can be found in ftp://vlsi.colorado.edu/pub/vl2mv-2.1.tar.gz. +This version requires glu-2.1 to compile and link. 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"./$cache_file";; + esac + fi +else + { $as_echo "$as_me:$LINENO: creating cache $cache_file" >&5 +$as_echo "$as_me: creating cache $cache_file" >&6;} + >$cache_file +fi + +# Check that the precious variables saved in the cache have kept the same +# value. +ac_cache_corrupted=false +for ac_var in $ac_precious_vars; do + eval ac_old_set=\$ac_cv_env_${ac_var}_set + eval ac_new_set=\$ac_env_${ac_var}_set + eval ac_old_val=\$ac_cv_env_${ac_var}_value + eval ac_new_val=\$ac_env_${ac_var}_value + case $ac_old_set,$ac_new_set in + set,) + { $as_echo "$as_me:$LINENO: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5 +$as_echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;} + ac_cache_corrupted=: ;; + ,set) + { $as_echo "$as_me:$LINENO: error: \`$ac_var' was not set in the previous run" >&5 +$as_echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;} + ac_cache_corrupted=: ;; + ,);; + *) + if test "x$ac_old_val" != "x$ac_new_val"; then + # differences in whitespace do not lead to failure. + ac_old_val_w=`echo x $ac_old_val` + ac_new_val_w=`echo x $ac_new_val` + if test "$ac_old_val_w" != "$ac_new_val_w"; then + { $as_echo "$as_me:$LINENO: error: \`$ac_var' has changed since the previous run:" >&5 +$as_echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;} + ac_cache_corrupted=: + else + { $as_echo "$as_me:$LINENO: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5 +$as_echo "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;} + eval $ac_var=\$ac_old_val + fi + { $as_echo "$as_me:$LINENO: former value: \`$ac_old_val'" >&5 +$as_echo "$as_me: former value: \`$ac_old_val'" >&2;} + { $as_echo "$as_me:$LINENO: current value: \`$ac_new_val'" >&5 +$as_echo "$as_me: current value: \`$ac_new_val'" >&2;} + fi;; + esac + # Pass precious variables to config.status. + if test "$ac_new_set" = set; then + case $ac_new_val in + *\'*) ac_arg=$ac_var=`$as_echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;; + *) ac_arg=$ac_var=$ac_new_val ;; + esac + case " $ac_configure_args " in + *" '$ac_arg' "*) ;; # Avoid dups. Use of quotes ensures accuracy. + *) ac_configure_args="$ac_configure_args '$ac_arg'" ;; + esac + fi +done +if $ac_cache_corrupted; then + { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + { $as_echo "$as_me:$LINENO: error: changes in the environment can compromise the build" >&5 +$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;} + { { $as_echo "$as_me:$LINENO: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&5 +$as_echo "$as_me: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&2;} + { (exit 1); exit 1; }; } +fi + + + + + + + + + + + + + + + + + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + +# Look for install.sh, config.guess, and config.sub in the "helpers" dir +ac_aux_dir= +for ac_dir in helpers "$srcdir"/helpers; do + if test -f "$ac_dir/install-sh"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install-sh -c" + break + elif test -f "$ac_dir/install.sh"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install.sh -c" + break + elif test -f "$ac_dir/shtool"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/shtool install -c" + break + fi +done +if test -z "$ac_aux_dir"; then + { { $as_echo "$as_me:$LINENO: error: cannot find install-sh or install.sh in helpers \"$srcdir\"/helpers" >&5 +$as_echo "$as_me: error: cannot find install-sh or install.sh in helpers \"$srcdir\"/helpers" >&2;} + { (exit 1); exit 1; }; } +fi + +# These three variables are undocumented and unsupported, +# and are intended to be withdrawn in a future Autoconf release. +# They can cause serious problems if a builder's source tree is in a directory +# whose full name contains unusual characters. +ac_config_guess="$SHELL $ac_aux_dir/config.guess" # Please don't use this var. +ac_config_sub="$SHELL $ac_aux_dir/config.sub" # Please don't use this var. +ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var. + + + +#---------------------------------------------------------------------- + +# Configuration options +#---------------------------------------------------------------------- + +# Give the configurer a chance to set the location of the GLU tree + + + +@%:@ Check whether --with-glu-libdir was given. +if test "${with_glu_libdir+set}" = set; then + withval=$with_glu_libdir; glulibdir=$withval +else + glulibdir="" +fi + + + + +@%:@ Check whether --with-glu-incdir was given. +if test "${with_glu_incdir+set}" = set; then + withval=$with_glu_incdir; gluincdir=$withval +else + gluincdir="" +fi + + +# Give the configurer a chance to set a different location for the VIS +# headers and library + + + +@%:@ Check whether --with-vis-libdir was given. +if test "${with_vis_libdir+set}" = set; then + withval=$with_vis_libdir; vislibdir=$withval +else + vislibdir="." +fi + + +# Give the configurer a chance to set a different location for the VIS +# source. When specified, "srcdir" points to "master" source, and +# "local_srcdir" points to the source under local development. + + + +@%:@ Check whether --with-local-srcdir was given. +if test "${with_local_srcdir+set}" = set; then + withval=$with_local_srcdir; local_srcdir=$withval +else + local_srcdir=$srcdir +fi + + +# Give the configurer a chance to set the BDD library + + + +@%:@ Check whether --with-bdd was given. +if test "${with_bdd+set}" = set; then + withval=$with_bdd; BDDLIB=$withval +else + BDDLIB=cu +fi + + +#---------------------------------------------------------------------- +# Checks for programs we need +#---------------------------------------------------------------------- +# Extract the first word of "zchaff", so it can be a program name with args. +set dummy zchaff; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_ZCHAFF+set}" = set; then + $as_echo_n "(cached) " >&6 +else + case $ZCHAFF in + [\\/]* | ?:[\\/]*) + ac_cv_path_ZCHAFF="$ZCHAFF" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_path_ZCHAFF="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + + ;; +esac +fi +ZCHAFF=$ac_cv_path_ZCHAFF +if test -n "$ZCHAFF"; then + { $as_echo "$as_me:$LINENO: result: $ZCHAFF" >&5 +$as_echo "$ZCHAFF" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +# Extract the first word of "sharpSAT", so it can be a program name with args. +set dummy sharpSAT; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_SHARPSAT+set}" = set; then + $as_echo_n "(cached) " >&6 +else + case $SHARPSAT in + [\\/]* | ?:[\\/]*) + ac_cv_path_SHARPSAT="$SHARPSAT" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_path_SHARPSAT="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + + ;; +esac +fi +SHARPSAT=$ac_cv_path_SHARPSAT +if test -n "$SHARPSAT"; then + { $as_echo "$as_me:$LINENO: result: $SHARPSAT" >&5 +$as_echo "$SHARPSAT" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +# Extract the first word of "ar", so it can be a program name with args. +set dummy ar; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_AR+set}" = set; then + $as_echo_n "(cached) " >&6 +else + case $AR in + [\\/]* | ?:[\\/]*) + ac_cv_path_AR="$AR" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_path_AR="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + + test -z "$ac_cv_path_AR" && ac_cv_path_AR="ar" + ;; +esac +fi +AR=$ac_cv_path_AR +if test -n "$AR"; then + { $as_echo "$as_me:$LINENO: result: $AR" >&5 +$as_echo "$AR" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:$LINENO: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:$LINENO: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + + +# Make sure we can run config.sub. +$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 || + { { $as_echo "$as_me:$LINENO: error: cannot run $SHELL $ac_aux_dir/config.sub" >&5 +$as_echo "$as_me: error: cannot run $SHELL $ac_aux_dir/config.sub" >&2;} + { (exit 1); exit 1; }; } + +{ $as_echo "$as_me:$LINENO: checking build system type" >&5 +$as_echo_n "checking build system type... " >&6; } +if test "${ac_cv_build+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_build_alias=$build_alias +test "x$ac_build_alias" = x && + ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"` +test "x$ac_build_alias" = x && + { { $as_echo "$as_me:$LINENO: error: cannot guess build type; you must specify one" >&5 +$as_echo "$as_me: error: cannot guess build type; you must specify one" >&2;} + { (exit 1); exit 1; }; } +ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` || + { { $as_echo "$as_me:$LINENO: error: $SHELL $ac_aux_dir/config.sub $ac_build_alias failed" >&5 +$as_echo "$as_me: error: $SHELL $ac_aux_dir/config.sub $ac_build_alias failed" >&2;} + { (exit 1); exit 1; }; } + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_build" >&5 +$as_echo "$ac_cv_build" >&6; } +case $ac_cv_build in +*-*-*) ;; +*) { { $as_echo "$as_me:$LINENO: error: invalid value of canonical build" >&5 +$as_echo "$as_me: error: invalid value of canonical build" >&2;} + { (exit 1); exit 1; }; };; +esac +build=$ac_cv_build +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_build +shift +build_cpu=$1 +build_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +build_os=$* +IFS=$ac_save_IFS +case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:$LINENO: checking host system type" >&5 +$as_echo_n "checking host system type... " >&6; } +if test "${ac_cv_host+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test "x$host_alias" = x; then + ac_cv_host=$ac_cv_build +else + ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || + { { $as_echo "$as_me:$LINENO: error: $SHELL $ac_aux_dir/config.sub $host_alias failed" >&5 +$as_echo "$as_me: error: $SHELL $ac_aux_dir/config.sub $host_alias failed" >&2;} + { (exit 1); exit 1; }; } +fi + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_host" >&5 +$as_echo "$ac_cv_host" >&6; } +case $ac_cv_host in +*-*-*) ;; +*) { { $as_echo "$as_me:$LINENO: error: invalid value of canonical host" >&5 +$as_echo "$as_me: error: invalid value of canonical host" >&2;} + { (exit 1); exit 1; }; };; +esac +host=$ac_cv_host +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_host +shift +host_cpu=$1 +host_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +host_os=$* +IFS=$ac_save_IFS +case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:$LINENO: checking target system type" >&5 +$as_echo_n "checking target system type... " >&6; } +if test "${ac_cv_target+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test "x$target_alias" = x; then + ac_cv_target=$ac_cv_host +else + ac_cv_target=`$SHELL "$ac_aux_dir/config.sub" $target_alias` || + { { $as_echo "$as_me:$LINENO: error: $SHELL $ac_aux_dir/config.sub $target_alias failed" >&5 +$as_echo "$as_me: error: $SHELL $ac_aux_dir/config.sub $target_alias failed" >&2;} + { (exit 1); exit 1; }; } +fi + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_target" >&5 +$as_echo "$ac_cv_target" >&6; } +case $ac_cv_target in +*-*-*) ;; +*) { { $as_echo "$as_me:$LINENO: error: invalid value of canonical target" >&5 +$as_echo "$as_me: error: invalid value of canonical target" >&2;} + { (exit 1); exit 1; }; };; +esac +target=$ac_cv_target +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_target +shift +target_cpu=$1 +target_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +target_os=$* +IFS=$ac_save_IFS +case $target_os in *\ *) target_os=`echo "$target_os" | sed 's/ /-/g'`;; esac + + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +test -n "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + + +# Determine the name of the C compiler we're going to use + +@%:@ Check whether --enable-gcc was given. +if test "${enable_gcc+set}" = set; then + enableval=$enable_gcc; gcc_ok=$enableval +else + gcc_ok=no +fi + + +# We cannot set CC=g++ directly because many configuration test programs +# do not compile with g++. Hence, when the user specifies --enable-gcc=g++, +# we set CC=gcc during configuration, and then CC=g++ at the end. +# The same applies to icpc and icc. +if test "$gcc_ok" != no; then + case "$gcc_ok" in + yes | g++) + CC=gcc ;; + icpc) + CC=icc ;; + *) + CC=$gcc_ok + esac +else + if test -z "$CC" ; then + # Balakrishna Kumthekar + # As we do not support cc on RS6000, Cygwin and SunOS. + case "$target" in + rs6000-ibm-aix* | *-pc-cygwin32 | sparc-sun-sunos*) + CC=gcc ;; + *) + CC=cc ;; + esac + fi +fi +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:$LINENO: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:$LINENO: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:$LINENO: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $@%:@ != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:$LINENO: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:$LINENO: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:$LINENO: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { $as_echo "$as_me:$LINENO: error: no acceptable C compiler found in \$PATH +See \`config.log' for more details." >&5 +$as_echo "$as_me: error: no acceptable C compiler found in \$PATH +See \`config.log' for more details." >&2;} + { (exit 1); exit 1; }; }; } + +# Provide some information about the compiler. +$as_echo "$as_me:$LINENO: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +{ (ac_try="$ac_compiler --version >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compiler --version >&5") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } +{ (ac_try="$ac_compiler -v >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compiler -v >&5") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } +{ (ac_try="$ac_compiler -V >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compiler -V >&5") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } + +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:$LINENO: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... 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We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi + +{ $as_echo "$as_me:$LINENO: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +if test -z "$ac_file"; then + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { $as_echo "$as_me:$LINENO: error: C compiler cannot create executables +See \`config.log' for more details." >&5 +$as_echo "$as_me: error: C compiler cannot create executables +See \`config.log' for more details." >&2;} + { (exit 77); exit 77; }; }; } +fi + +ac_exeext=$ac_cv_exeext + +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:$LINENO: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... 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For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { $as_echo "$as_me:$LINENO: error: cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." >&5 +$as_echo "$as_me: error: cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." >&2;} + { (exit 1); exit 1; }; }; } +fi + +rm -f conftest$ac_cv_exeext +{ $as_echo "$as_me:$LINENO: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +{ $as_echo "$as_me:$LINENO: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... 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" >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_prog_cc_g=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + CFLAGS="" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + : +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_prog_cc_g=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:$LINENO: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_prog_cc_c89=$ac_arg +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:$LINENO: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:$LINENO: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:$LINENO: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac + + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +@%:@ Check whether --enable-64 was given. +if test "${enable_64+set}" = set; then + enableval=$enable_64; use_sixty_four=$enableval +else + use_sixty_four=no +fi + + +# Gcc does not support 32-bit pointers on the Alphas. +if test "$gcc_ok" != no; then + use_sixty_four=yes +fi + + +# Roderick Bloem (rbloem@colorado.edu): making a special case for +# ultrix install, since it's annoying about setting groupids. +case "$target" in + mips-dec-ultrix*) + INSTALL="helpers/install-sh -c" + INSTALL_PROGRAM="\${INSTALL}" + INSTALL_DATA="\${INSTALL} -m 644";; + + *) + # Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:$LINENO: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if test "${ac_cv_path_install+set}" = set; then + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in + ./ | .// | /cC/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:\\/os2\\/install\\/* | ?:\\/OS2\\/INSTALL\\/* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + +done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:$LINENO: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + ;; +esac + +# Determine the compiler flags to use + +DEBUG_CFLAGS="-g" +DEBUG_LDFLAGS="" + +case "$target" in + + i686-pc-linux-gnu) + # Linux with Intel compiler + # -ansi: ANSI C conformance + # -ip: inter-procedural optimization + OPTIMIZE_CFLAGS="-g -O3 -ansi -ip" + ;; + + sparc-sun-solaris* | i386-pc-solaris*) + # Sparc and X86 Solaris: + # -xO3: Highest safe level of optimization + # -native: Optimize for the native processor (if supported) + # -dalign: Generate double-word load/store for performance + # (only for SPARC) + # and other arcane compilation flags. + if test "$GCC" = yes; then + OPTIMIZE_CFLAGS="-O" + else + case "$target" in + sparc-sun-solaris*) + ALIGN=" -dalign" ;; + *) + ALIGN="" ;; + esac + { $as_echo "$as_me:$LINENO: checking for -native" >&5 +$as_echo_n "checking for -native... " >&6; } + CFLAGS="-xO3 -native$ALIGN" + +if test "${ac_cv_have_native+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then + ac_cv_have_native=no +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + + main(){exit(0);} + +_ACEOF +rm -f conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { ac_try='./conftest$ac_exeext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + ac_cv_have_native=yes +else + $as_echo "$as_me: program exited with status $ac_status" >&5 +$as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +( exit $ac_status ) +ac_cv_have_native=no +fi +rm -rf conftest.dSYM +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +fi + + +fi + + if test $ac_cv_have_native = yes ; then + { $as_echo "$as_me:$LINENO: result: working" >&5 +$as_echo "working" >&6; } + OPTIMIZE_CFLAGS="-xO3 -native$ALIGN" + else + { $as_echo "$as_me:$LINENO: result: broken" >&5 +$as_echo "broken" >&6; } + { $as_echo "$as_me:$LINENO: checking for fallback optimization flags" >&5 +$as_echo_n "checking for fallback optimization flags... " >&6; } + CFLAGS="-xO3 -fns -fsimple=2$ALIGN -ftrap=%none -xlibmil" + if test "${ac_cv_have_fallback+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then + ac_cv_have_fallback=no +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + + main(){exit(0);} + +_ACEOF +rm -f conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { ac_try='./conftest$ac_exeext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + ac_cv_have_fallback=yes +else + $as_echo "$as_me: program exited with status $ac_status" >&5 +$as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +( exit $ac_status ) +ac_cv_have_fallback=no +fi +rm -rf conftest.dSYM +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +fi + + +fi + + if test $ac_cv_have_fallback = yes ; then + { $as_echo "$as_me:$LINENO: result: working" >&5 +$as_echo "working" >&6; } + OPTIMIZE_CFLAGS="-xO3 -fns -fsimple=2$ALIGN -ftrap=%none -xlibmil" + else + { $as_echo "$as_me:$LINENO: result: broken" >&5 +$as_echo "broken" >&6; } + OPTIMIZE_CFLAGS="-O" + fi + fi + fi + ;; + + mips-dec-ultrix*) + # MIPS-based DECstations running Ultrix: + # -std1: Produce non-ANSI code warnings, and define __STDC__ + # -O: Use the global "ucode" optimizer + # -Olimit 5000: Don't optimize routines bigger than 5000 basic blocks + OPTIMIZE_CFLAGS="-std1 -O -Olimit 5000" ;; + + alpha-dec-osf*) + # DEC Alpha running OSF: + + # 64-bit mode: + # -g3: Produce symbol table information for optimized code + # -O4: Enable every optimization + # -std: Enforce the ANSI standard with extensions, define __STDC__ + # -ieee_with_no_inexact: Disable (potentially slow) signaling + # for inexact floating-point results + # -tune host: Tune instructions for the compilation host machine + OPTIMIZE_CFLAGS="-g3 -O4 -std -ieee_with_no_inexact -tune host" + DEBUG_CFLAGS="-g -std -ieee_with_no_inexact" + + # -non_shared: Do not use shared libraries + # -om: Generate an OMAGIC file for the om optimizer + OPTIMIZE_LDFLAGS="-non_shared" + + if test "$use_sixty_four" = "no"; then + # 32-bit mode: + # -xtaso: Make the compiler respond to #pragma pointer_size directives + OPTIMIZE_CFLAGS="$OPTIMIZE_CFLAGS -xtaso" + DEBUG_CFLAGS="$DEBUG_CFLAGS -xtaso" + + # -taso: Load the executable into the lower 31-bit address space + OPTIMIZE_LDFLAGS="$OPTIMIZE_LDFLAGS -om -taso" + DEBUG_LDFLAGS="$DEBUG_LDFLAGS -taso" + + cat >>confdefs.h <<\_ACEOF +@%:@define SIZEOF_VOID_P 4 +_ACEOF + + ac_sizeof_voidp=4 + fi + ;; + + hppa*-*-hpux*) + # HP running HPUX + # -Aa: Behave as an ANSI compiler + # -D_HPUX_SOURCE: Include "HP-specific" symbols in the header + # files (e.g., this means sys/resource.h has struct rusage) + # +Onolimit: removes resource restrictions for optimization + OPTIMIZE_CFLAGS="-O -Aa +Onolimit -D_HPUX_SOURCE" + DEBUG_CFLAGS="-g -Aa -D_HPUX_SOURCE" ;; + + *) + # Other systems: + OPTIMIZE_CFLAGS="-O" ;; + +esac + +if test "$GCC" = yes; then + case "$target" in + i686-pc-linux-gnu | i386-pc-solaris* | i386-pc-cygwin32 | i386-*-freebsd*) + { $as_echo "$as_me:$LINENO: checking for -mcpu and -malign compiler options" >&5 +$as_echo_n "checking for -mcpu and -malign compiler options... " >&6; } + CFLAGS="-g -O3 -mcpu=pentiumpro -malign-double" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_have_mcpu=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_have_mcpu=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "$ac_have_mcpu" = yes; then + { $as_echo "$as_me:$LINENO: result: working" >&5 +$as_echo "working" >&6; } + OPTIMIZE_CFLAGS="-g -O3 -mcpu=pentiumpro -malign-double" + else + { $as_echo "$as_me:$LINENO: result: broken" >&5 +$as_echo "broken" >&6; } + OPTIMIZE_CFLAGS="-g -O3" + fi + ;; + sparc-sun-solaris*) + { $as_echo "$as_me:$LINENO: checking for -mtune compiler option" >&5 +$as_echo_n "checking for -mtune compiler option... " >&6; } + CFLAGS="-g -O3 -mtune=ultrasparc" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_have_mtune=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_have_mtune=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "$ac_have_mtune" = yes; then + { $as_echo "$as_me:$LINENO: result: working" >&5 +$as_echo "working" >&6; } + OPTIMIZE_CFLAGS="-g -O3 -mtune=ultrasparc" + else + { $as_echo "$as_me:$LINENO: result: not working" >&5 +$as_echo "not working" >&6; } + OPTIMIZE_CFLAGS="-g -O3" + fi + ;; + *) + OPTIMIZE_CFLAGS="-g -O3" + ;; + esac + OPTIMIZE_LDFLAGS="" + DEBUG_CFLAGS="-g" + DEBUG_LDFLAGS="" +fi + + +@%:@ Check whether --with-comp-mode was given. +if test "${with_comp_mode+set}" = set; then + withval=$with_comp_mode; comp_mode=$withval +else + comp_mode=optimize +fi + + + + +LINKER="$CC" + +case "$comp_mode" in + debug) + CFLAGS="$DEBUG_CFLAGS" + LDFLAGS="$DEBUG_LDFLAGS" ;; + purify) + CFLAGS="$DEBUG_CFLAGS" + LDFLAGS="$DEBUG_LDFLAGS" + cat >>confdefs.h <<\_ACEOF +@%:@define PURIFY 1 +_ACEOF + + LINKER="purify -cache-dir=/tmp $CC" + PLINKER="purify -log-file=./purify.log -cachedir=/tmp $CC" ;; + quantify) + CFLAGS="$OPTIMIZE_CFLAGS" + LDFLAGS="$OPTIMIZE_LDFLAGS" + cat >>confdefs.h <<\_ACEOF +@%:@define QUANTIFY 1 +_ACEOF + + cat >>confdefs.h <<\_ACEOF +@%:@define NDEBUG 1 +_ACEOF + + LINKER="quantify $CC" ;; + optimize | *) + CFLAGS="$OPTIMIZE_CFLAGS" + LDFLAGS="$OPTIMIZE_LDFLAGS" + cat >>confdefs.h <<\_ACEOF +@%:@define NDEBUG 1 +_ACEOF + ;; +esac + +for ac_prog in flex lex +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_LEX+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$LEX"; then + ac_cv_prog_LEX="$LEX" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_LEX="$ac_prog" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +LEX=$ac_cv_prog_LEX +if test -n "$LEX"; then + { $as_echo "$as_me:$LINENO: result: $LEX" >&5 +$as_echo "$LEX" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$LEX" && break +done +test -n "$LEX" || LEX=":" + +if test "x$LEX" != "x:"; then + cat >conftest.l <<_ACEOF +%% +a { ECHO; } +b { REJECT; } +c { yymore (); } +d { yyless (1); } +e { yyless (input () != 0); } +f { unput (yytext[0]); } +. { BEGIN INITIAL; } +%% +#ifdef YYTEXT_POINTER +extern char *yytext; +#endif +int +main (void) +{ + return ! yylex () + ! yywrap (); +} +_ACEOF +{ (ac_try="$LEX conftest.l" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$LEX conftest.l") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } +{ $as_echo "$as_me:$LINENO: checking lex output file root" >&5 +$as_echo_n "checking lex output file root... " >&6; } +if test "${ac_cv_prog_lex_root+set}" = set; then + $as_echo_n "(cached) " >&6 +else + +if test -f lex.yy.c; then + ac_cv_prog_lex_root=lex.yy +elif test -f lexyy.c; then + ac_cv_prog_lex_root=lexyy +else + { { $as_echo "$as_me:$LINENO: error: cannot find output from $LEX; giving up" >&5 +$as_echo "$as_me: error: cannot find output from $LEX; giving up" >&2;} + { (exit 1); exit 1; }; } +fi +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_prog_lex_root" >&5 +$as_echo "$ac_cv_prog_lex_root" >&6; } +LEX_OUTPUT_ROOT=$ac_cv_prog_lex_root + +if test -z "${LEXLIB+set}"; then + { $as_echo "$as_me:$LINENO: checking lex library" >&5 +$as_echo_n "checking lex library... " >&6; } +if test "${ac_cv_lib_lex+set}" = set; then + $as_echo_n "(cached) " >&6 +else + + ac_save_LIBS=$LIBS + ac_cv_lib_lex='none needed' + for ac_lib in '' -lfl -ll; do + LIBS="$ac_lib $ac_save_LIBS" + cat >conftest.$ac_ext <<_ACEOF +`cat $LEX_OUTPUT_ROOT.c` +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_lex=$ac_lib +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext + test "$ac_cv_lib_lex" != 'none needed' && break + done + LIBS=$ac_save_LIBS + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_lex" >&5 +$as_echo "$ac_cv_lib_lex" >&6; } + test "$ac_cv_lib_lex" != 'none needed' && LEXLIB=$ac_cv_lib_lex +fi + + +{ $as_echo "$as_me:$LINENO: checking whether yytext is a pointer" >&5 +$as_echo_n "checking whether yytext is a pointer... " >&6; } +if test "${ac_cv_prog_lex_yytext_pointer+set}" = set; then + $as_echo_n "(cached) " >&6 +else + # POSIX says lex can declare yytext either as a pointer or an array; the +# default is implementation-dependent. Figure out which it is, since +# not all implementations provide the %pointer and %array declarations. +ac_cv_prog_lex_yytext_pointer=no +ac_save_LIBS=$LIBS +LIBS="$LEXLIB $ac_save_LIBS" +cat >conftest.$ac_ext <<_ACEOF +#define YYTEXT_POINTER 1 +`cat $LEX_OUTPUT_ROOT.c` +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_prog_lex_yytext_pointer=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_save_LIBS + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_prog_lex_yytext_pointer" >&5 +$as_echo "$ac_cv_prog_lex_yytext_pointer" >&6; } +if test $ac_cv_prog_lex_yytext_pointer = yes; then + +cat >>confdefs.h <<\_ACEOF +@%:@define YYTEXT_POINTER 1 +_ACEOF + +fi +rm -f conftest.l $LEX_OUTPUT_ROOT.c + +fi +{ $as_echo "$as_me:$LINENO: checking if $LEX accepts the -o and -P options" >&5 +$as_echo_n "checking if $LEX accepts the -o and -P options... " >&6; } + +if test "${ac_cv_flex_accepts_op+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_cv_flex_accepts_op=yes ; +echo "%%\ +%%" | $LEX -Ptest -o/dev/null >/dev/null 2>&1 || ac_cv_flex_accepts_op=no +fi + +if test $ac_cv_flex_accepts_op = yes ; then + { $as_echo "$as_me:$LINENO: result: yes" >&5 +$as_echo "yes" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } + { $as_echo "$as_me:$LINENO: WARNING: You either need a newer version of flex, or need to modify +the defintion of LEX in the Makefile to point to a version that does +accept -p -t and -o." >&5 +$as_echo "$as_me: WARNING: You either need a newer version of flex, or need to modify +the defintion of LEX in the Makefile to point to a version that does +accept -p -t and -o." >&2;} +fi + +for ac_prog in 'bison -y' byacc +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_YACC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$YACC"; then + ac_cv_prog_YACC="$YACC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_YACC="$ac_prog" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +YACC=$ac_cv_prog_YACC +if test -n "$YACC"; then + { $as_echo "$as_me:$LINENO: result: $YACC" >&5 +$as_echo "$YACC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$YACC" && break +done +test -n "$YACC" || YACC="yacc" + +{ $as_echo "$as_me:$LINENO: checking if $YACC accepts the -p, -t, and -o options" >&5 +$as_echo_n "checking if $YACC accepts the -p, -t, and -o options... " >&6; } +if test "${ac_cv_yacc_accepts_pto+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_cv_yacc_accepts_pto=yes ; +echo "%token terminal\ +%%\ +nonterminal: terminal\ +%%" > config.in +$YACC -ptest -o /dev/null config.in >/dev/null 2>&1 || ac_cv_yacc_accepts_pto=no +rm -f config.in +fi + +if test $ac_cv_yacc_accepts_pto = yes ; then + { $as_echo "$as_me:$LINENO: result: yes" >&5 +$as_echo "yes" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } + { $as_echo "$as_me:$LINENO: WARNING: You either need a newer version of bison, or need to modify +the defintion of YACC in the Makefile to point to a version that does +accept -p -t and -o." >&5 +$as_echo "$as_me: WARNING: You either need a newer version of bison, or need to modify +the defintion of YACC in the Makefile to point to a version that does +accept -p -t and -o." >&2;} +fi + +#---------------------------------------------------------------------- +# Checks for headers and libraries +#---------------------------------------------------------------------- +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5 +$as_echo_n "checking how to run the C preprocessor... " >&6; } +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then + if test "${ac_cv_prog_CPP+set}" = set; then + $as_echo_n "(cached) " >&6 +else + # Double quotes because CPP needs to be expanded + for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" + do + ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +@%:@ifdef __STDC__ +@%:@ include +@%:@else +@%:@ include +@%:@endif + Syntax error +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + : +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + # Broken: fails on valid input. +continue +fi + +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +@%:@include +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + # Broken: success on invalid input. +continue +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + # Passes both tests. +ac_preproc_ok=: +break +fi + +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then + break +fi + + done + ac_cv_prog_CPP=$CPP + +fi + CPP=$ac_cv_prog_CPP +else + ac_cv_prog_CPP=$CPP +fi +{ $as_echo "$as_me:$LINENO: result: $CPP" >&5 +$as_echo "$CPP" >&6; } +ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +@%:@ifdef __STDC__ +@%:@ include +@%:@else +@%:@ include +@%:@endif + Syntax error +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + : +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + # Broken: fails on valid input. +continue +fi + +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +@%:@include +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + # Broken: success on invalid input. +continue +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + # Passes both tests. +ac_preproc_ok=: +break +fi + +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then + : +else + { { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { $as_echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." >&5 +$as_echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." >&2;} + { (exit 1); exit 1; }; }; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +{ $as_echo "$as_me:$LINENO: checking for grep that handles long lines and -e" >&5 +$as_echo_n "checking for grep that handles long lines and -e... " >&6; } +if test "${ac_cv_path_GREP+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + ac_count=`expr $ac_count + 1` + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done +done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + { { $as_echo "$as_me:$LINENO: error: no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 +$as_echo "$as_me: error: no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} + { (exit 1); exit 1; }; } + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:$LINENO: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if test "${ac_cv_path_EGREP+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + ac_count=`expr $ac_count + 1` + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done +done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + { { $as_echo "$as_me:$LINENO: error: no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 +$as_echo "$as_me: error: no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} + { (exit 1); exit 1; }; } + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +{ $as_echo "$as_me:$LINENO: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if test "${ac_cv_header_stdc+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include +#include +#include + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_header_stdc=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_header_stdc=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then + : +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then + : +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then + : +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +rm -f conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { ac_try='./conftest$ac_exeext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + : +else + $as_echo "$as_me: program exited with status $ac_status" >&5 +$as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +( exit $ac_status ) +ac_cv_header_stdc=no +fi +rm -rf conftest.dSYM +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +fi + + +fi +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +cat >>confdefs.h <<\_ACEOF +@%:@define STDC_HEADERS 1 +_ACEOF + +fi + + + + +# add -lucb to LIBS and -L/usr/ucblib to LIBDIRS +# if there's a libucb.a available +# (Solaris needs this for signals) + +ac_save_ldflags="$LDFLAGS" +LDFLAGS=-L/usr/ucblib +{ $as_echo "$as_me:$LINENO: checking for main in -lucb" >&5 +$as_echo_n "checking for main in -lucb... " >&6; } +if test "${ac_cv_lib_ucb_main+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lucb $LIBS" +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + + +int +main () +{ +return main (); + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_ucb_main=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_lib_ucb_main=no +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_ucb_main" >&5 +$as_echo "$ac_cv_lib_ucb_main" >&6; } +if test "x$ac_cv_lib_ucb_main" = x""yes; then + LIBDIRS="$LIBDIRS -L/usr/ucblib" +fi + +LDFLAGS="$ac_save_ldflags" + +# add -lbsd if there's a libbsd.a available +# (e.g., Linux needs this for bsd_ioctl) + +{ $as_echo "$as_me:$LINENO: checking for main in -lbsd" >&5 +$as_echo_n "checking for main in -lbsd... " >&6; } +if test "${ac_cv_lib_bsd_main+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lbsd $LIBS" +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + + +int +main () +{ +return main (); + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_bsd_main=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_lib_bsd_main=no +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_bsd_main" >&5 +$as_echo "$ac_cv_lib_bsd_main" >&6; } +if test "x$ac_cv_lib_bsd_main" = x""yes; then + cat >>confdefs.h <<_ACEOF +@%:@define HAVE_LIBBSD 1 +_ACEOF + + LIBS="-lbsd $LIBS" + +fi + + +# Check if libreadline exists and the function readline can be used. +# This implies checking for the availability of libtermcap or of a +# suitable replacement. (We only look for libncurses.) +if test "${vis_cv_termcap_lib+set}" = set; then + $as_echo_n "(cached) " >&6 +else + { $as_echo "$as_me:$LINENO: checking for tgetent in -ltermcap" >&5 +$as_echo_n "checking for tgetent in -ltermcap... " >&6; } +if test "${ac_cv_lib_termcap_tgetent+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ltermcap $LIBS" +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char tgetent (); +int +main () +{ +return tgetent (); + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_termcap_tgetent=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_lib_termcap_tgetent=no +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_termcap_tgetent" >&5 +$as_echo "$ac_cv_lib_termcap_tgetent" >&6; } +if test "x$ac_cv_lib_termcap_tgetent" = x""yes; then + vis_cv_termcap_lib=-ltermcap +else + { $as_echo "$as_me:$LINENO: checking for tgetent in -lncurses" >&5 +$as_echo_n "checking for tgetent in -lncurses... " >&6; } +if test "${ac_cv_lib_ncurses_tgetent+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lncurses $LIBS" +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char tgetent (); +int +main () +{ +return tgetent (); + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_ncurses_tgetent=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_lib_ncurses_tgetent=no +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_ncurses_tgetent" >&5 +$as_echo "$ac_cv_lib_ncurses_tgetent" >&6; } +if test "x$ac_cv_lib_ncurses_tgetent" = x""yes; then + vis_cv_termcap_lib=-lncurses +else + bash_cv_termcap_lib=none +fi + +fi + +fi + +if test "$vis_cv_termcap_lib" != none; then + { $as_echo "$as_me:$LINENO: checking for readline in -lreadline" >&5 +$as_echo_n "checking for readline in -lreadline... " >&6; } +if test "${ac_cv_lib_readline_readline+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lreadline $vis_cv_termcap_lib $LIBS" +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char readline (); +int +main () +{ +return readline (); + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_readline_readline=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_lib_readline_readline=no +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_readline_readline" >&5 +$as_echo "$ac_cv_lib_readline_readline" >&6; } +if test "x$ac_cv_lib_readline_readline" = x""yes; then + ac_readline_flag=1 +else + ac_readline_flag=0 +fi + + if test $ac_readline_flag = 1 ; then + LIBS="$LIBS -lreadline $vis_cv_termcap_lib" ; cat >>confdefs.h <<\_ACEOF +@%:@define HAVE_LIBREADLINE 1 +_ACEOF + + fi +fi + +# Check for the dirent header file, which is quite a mess + + + + + +ac_header_dirent=no +for ac_hdr in dirent.h sys/ndir.h sys/dir.h ndir.h; do + as_ac_Header=`$as_echo "ac_cv_header_dirent_$ac_hdr" | $as_tr_sh` +{ $as_echo "$as_me:$LINENO: checking for $ac_hdr that defines DIR" >&5 +$as_echo_n "checking for $ac_hdr that defines DIR... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include <$ac_hdr> + +int +main () +{ +if ((DIR *) 0) +return 0; + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + eval "$as_ac_Header=yes" +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + eval "$as_ac_Header=no" +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +as_val=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + if test "x$as_val" = x""yes; then + cat >>confdefs.h <<_ACEOF +@%:@define `$as_echo "HAVE_$ac_hdr" | $as_tr_cpp` 1 +_ACEOF + +ac_header_dirent=$ac_hdr; break +fi + +done +# Two versions of opendir et al. are in -ldir and -lx on SCO Xenix. +if test $ac_header_dirent = dirent.h; then + { $as_echo "$as_me:$LINENO: checking for library containing opendir" >&5 +$as_echo_n "checking for library containing opendir... " >&6; } +if test "${ac_cv_search_opendir+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char opendir (); +int +main () +{ +return opendir (); + ; + return 0; +} +_ACEOF +for ac_lib in '' dir; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_search_opendir=$ac_res +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext + if test "${ac_cv_search_opendir+set}" = set; then + break +fi +done +if test "${ac_cv_search_opendir+set}" = set; then + : +else + ac_cv_search_opendir=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_search_opendir" >&5 +$as_echo "$ac_cv_search_opendir" >&6; } +ac_res=$ac_cv_search_opendir +if test "$ac_res" != no; then + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + +fi + +else + { $as_echo "$as_me:$LINENO: checking for library containing opendir" >&5 +$as_echo_n "checking for library containing opendir... " >&6; } +if test "${ac_cv_search_opendir+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char opendir (); +int +main () +{ +return opendir (); + ; + return 0; +} +_ACEOF +for ac_lib in '' x; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_search_opendir=$ac_res +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext + if test "${ac_cv_search_opendir+set}" = set; then + break +fi +done +if test "${ac_cv_search_opendir+set}" = set; then + : +else + ac_cv_search_opendir=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_search_opendir" >&5 +$as_echo "$ac_cv_search_opendir" >&6; } +ac_res=$ac_cv_search_opendir +if test "$ac_res" != no; then + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + +fi + +fi + + +# Check for these system header files +# On IRIX 5.3, sys/types and inttypes.h are conflicting. + + + + + + + + + +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do +as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 +$as_echo_n "checking for $ac_header... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +$ac_includes_default + +@%:@include <$ac_header> +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + eval "$as_ac_Header=yes" +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + eval "$as_ac_Header=no" +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +as_val=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + if test "x$as_val" = x""yes; then + cat >>confdefs.h <<_ACEOF +@%:@define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + + + + + + + + +for ac_header in sys/termios.h sys/ioctl.h sys/time.h signal.h sys/signal.h readline/readline.h readline/history.h +do +as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + { $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 +$as_echo_n "checking for $ac_header... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +else + # Is the header compilable? +{ $as_echo "$as_me:$LINENO: checking $ac_header usability" >&5 +$as_echo_n "checking $ac_header usability... " >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +$ac_includes_default +@%:@include <$ac_header> +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_header_compiler=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_compiler=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +{ $as_echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 +$as_echo "$ac_header_compiler" >&6; } + +# Is the header present? +{ $as_echo "$as_me:$LINENO: checking $ac_header presence" >&5 +$as_echo_n "checking $ac_header presence... " >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +@%:@include <$ac_header> +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + ac_header_preproc=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_preproc=no +fi + +rm -f conftest.err conftest.$ac_ext +{ $as_echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 +$as_echo "$ac_header_preproc" >&6; } + +# So? What about this header? +case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in + yes:no: ) + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 +$as_echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 +$as_echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} + ac_header_preproc=yes + ;; + no:yes:* ) + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 +$as_echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 +$as_echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 +$as_echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 +$as_echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 +$as_echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 +$as_echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} + + ;; +esac +{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 +$as_echo_n "checking for $ac_header... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +else + eval "$as_ac_Header=\$ac_header_preproc" +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + +fi +as_val=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + if test "x$as_val" = x""yes; then + cat >>confdefs.h <<_ACEOF +@%:@define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +# This is for Linux + +for ac_header in bsd/sgtty.h +do +as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + { $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 +$as_echo_n "checking for $ac_header... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +else + # Is the header compilable? +{ $as_echo "$as_me:$LINENO: checking $ac_header usability" >&5 +$as_echo_n "checking $ac_header usability... " >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +$ac_includes_default +@%:@include <$ac_header> +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_header_compiler=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_compiler=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +{ $as_echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 +$as_echo "$ac_header_compiler" >&6; } + +# Is the header present? +{ $as_echo "$as_me:$LINENO: checking $ac_header presence" >&5 +$as_echo_n "checking $ac_header presence... " >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +@%:@include <$ac_header> +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + ac_header_preproc=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_preproc=no +fi + +rm -f conftest.err conftest.$ac_ext +{ $as_echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 +$as_echo "$ac_header_preproc" >&6; } + +# So? What about this header? +case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in + yes:no: ) + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 +$as_echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 +$as_echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} + ac_header_preproc=yes + ;; + no:yes:* ) + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 +$as_echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 +$as_echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 +$as_echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 +$as_echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 +$as_echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 +$as_echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} + + ;; +esac +{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 +$as_echo_n "checking for $ac_header... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +else + eval "$as_ac_Header=\$ac_header_preproc" +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + +fi +as_val=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + if test "x$as_val" = x""yes; then + cat >>confdefs.h <<_ACEOF +@%:@define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +# Some systems want both sys/ioctl.h and sys/termios.h, but others can +# only have one -- check for that + +{ $as_echo "$as_me:$LINENO: checking whether sys/termios.h and sys/ioctl.h should both be included" >&5 +$as_echo_n "checking whether sys/termios.h and sys/ioctl.h should both be included... " >&6; } + +if test "${ac_cv_ioctl_with_termios+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +#include +#include + +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + ac_cv_ioctl_with_termios=1 +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_ioctl_with_termios=0 +fi + +rm -f conftest.err conftest.$ac_ext +fi + +if test $ac_cv_ioctl_with_termios = 1 ; then + { $as_echo "$as_me:$LINENO: result: yes" >&5 +$as_echo "yes" >&6; } ; cat >>confdefs.h <<\_ACEOF +@%:@define IOCTL_WITH_TERMIOS 1 +_ACEOF + +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + +# cmdFile.c wants to be able to use TIOCGETC to do file completion, +# but some systems (e.g., HPUX) don't have this +# + +{ $as_echo "$as_me:$LINENO: checking for TIOCGETC" >&5 +$as_echo_n "checking for TIOCGETC... " >&6; } + +if test "${ac_cv_have_ioctl_with_tiocgetc+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test $ac_cv_ioctl_with_termios = 1 ; then + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include +#ifdef TIOCGETC + yes +#endif +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "yes" >/dev/null 2>&1; then + ac_cv_have_ioctl_with_tiocgetc=yes +else + ac_cv_have_ioctl_with_tiocgetc=no +fi +rm -f conftest* + +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#ifdef TIOCGETC + yes +#endif +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "yes" >/dev/null 2>&1; then + ac_cv_have_ioctl_with_tiocgetc=yes +else + ac_cv_have_ioctl_with_tiocgetc=no +fi +rm -f conftest* + +fi +fi + +if test $ac_cv_have_ioctl_with_tiocgetc = "yes" ; then + { $as_echo "$as_me:$LINENO: result: yes" >&5 +$as_echo "yes" >&6; } ; cat >>confdefs.h <<\_ACEOF +@%:@define HAVE_IOCTL_WITH_TIOCGETC 1 +_ACEOF + +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + +# # cmdFile.c wants to turn off interrupts, but some systems don't +# # seem to know how to do that using TIOCLBIS +# # +# # This is probably fairly fragile, and it's probably cmdFile.c that should +# # be fixed +# # +# # This has been very unreliable (e.g., on Solaris), so the facility has +# # been turned off +# +# if test $ac_cv_have_ioctl_with_tiocgetc = "yes" ; then +# +# AC_MSG_CHECKING(for TIOCLBIS) +# +# AC_CACHE_VAL(ac_cv_have_term_interrupts, +# [AC_EGREP_CPP(yes, +# [#include +# #include +# #ifdef TIOCLBIS +# yes +# #endif +# ], ac_cv_have_term_interrupts=1, +# ac_cv_have_term_interrupts=0 )]) +# +# if test $ac_cv_have_term_interrupts = 1 ; then +# AC_MSG_RESULT(yes) ; AC_DEFINE(HAVE_TERM_INTERRUPTS) +# else +# AC_MSG_RESULT(no) +# fi +# +# fi # ac_cv_have_ioctl_with_tiocgetc + +#---------------------------------------------------------------------- +# Checks for typedefs, structures, and compiler characteristics. +#---------------------------------------------------------------------- + +# Check to see if the compiler understands "const" +# #define it empty otherwise +{ $as_echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5 +$as_echo_n "checking for an ANSI C-conforming const... " >&6; } +if test "${ac_cv_c_const+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ +/* FIXME: Include the comments suggested by Paul. */ +#ifndef __cplusplus + /* Ultrix mips cc rejects this. */ + typedef int charset[2]; + const charset cs; + /* SunOS 4.1.1 cc rejects this. */ + char const *const *pcpcc; + char **ppc; + /* NEC SVR4.0.2 mips cc rejects this. */ + struct point {int x, y;}; + static struct point const zero = {0,0}; + /* AIX XL C 1.02.0.0 rejects this. + It does not let you subtract one const X* pointer from another in + an arm of an if-expression whose if-part is not a constant + expression */ + const char *g = "string"; + pcpcc = &g + (g ? g-g : 0); + /* HPUX 7.0 cc rejects these. */ + ++pcpcc; + ppc = (char**) pcpcc; + pcpcc = (char const *const *) ppc; + { /* SCO 3.2v4 cc rejects this. */ + char *t; + char const *s = 0 ? (char *) 0 : (char const *) 0; + + *t++ = 0; + if (s) return 0; + } + { /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */ + int x[] = {25, 17}; + const int *foo = &x[0]; + ++foo; + } + { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */ + typedef const int *iptr; + iptr p = 0; + ++p; + } + { /* AIX XL C 1.02.0.0 rejects this saying + "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */ + struct s { int j; const int *ap[3]; }; + struct s *b; b->j = 5; + } + { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ + const int foo = 10; + if (!foo) return 0; + } + return !cs[0] && !zero.x; +#endif + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_c_const=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_c_const=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5 +$as_echo "$ac_cv_c_const" >&6; } +if test $ac_cv_c_const = no; then + +cat >>confdefs.h <<\_ACEOF +@%:@define const /**/ +_ACEOF + +fi + + +# Sort out "time.h" nonsense +{ $as_echo "$as_me:$LINENO: checking whether time.h and sys/time.h may both be included" >&5 +$as_echo_n "checking whether time.h and sys/time.h may both be included... " >&6; } +if test "${ac_cv_header_time+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include +#include + +int +main () +{ +if ((struct tm *) 0) +return 0; + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_header_time=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_header_time=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_header_time" >&5 +$as_echo "$ac_cv_header_time" >&6; } +if test $ac_cv_header_time = yes; then + +cat >>confdefs.h <<\_ACEOF +@%:@define TIME_WITH_SYS_TIME 1 +_ACEOF + +fi + + +{ $as_echo "$as_me:$LINENO: checking whether struct tm is in sys/time.h or time.h" >&5 +$as_echo_n "checking whether struct tm is in sys/time.h or time.h... " >&6; } +if test "${ac_cv_struct_tm+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include + +int +main () +{ +struct tm tm; + int *p = &tm.tm_sec; + return !p; + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_struct_tm=time.h +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_struct_tm=sys/time.h +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_struct_tm" >&5 +$as_echo "$ac_cv_struct_tm" >&6; } +if test $ac_cv_struct_tm = sys/time.h; then + +cat >>confdefs.h <<\_ACEOF +@%:@define TM_IN_SYS_TIME 1 +_ACEOF + +fi + + +# Set RETSIGTYPE to the proper return type for a signal handler (void or int) +{ $as_echo "$as_me:$LINENO: checking return type of signal handlers" >&5 +$as_echo_n "checking return type of signal handlers... " >&6; } +if test "${ac_cv_type_signal+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include + +int +main () +{ +return *(signal (0, 0)) (0) == 1; + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_type_signal=int +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_type_signal=void +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_type_signal" >&5 +$as_echo "$ac_cv_type_signal" >&6; } + +cat >>confdefs.h <<_ACEOF +@%:@define RETSIGTYPE $ac_cv_type_signal +_ACEOF + + + +# Roderick Bloem (rbloem@colorado.edu) : On Irix we need ttold +case "$target" in + mips-sgi-irix*) + cat >>confdefs.h <<\_ACEOF +@%:@define NEED_TTOLD 1 +_ACEOF +;; +esac + +#---------------------------------------------------------------------- +# Checks for library functions. +#---------------------------------------------------------------------- + +if test $ac_cv_c_compiler_gnu = yes; then + { $as_echo "$as_me:$LINENO: checking whether $CC needs -traditional" >&5 +$as_echo_n "checking whether $CC needs -traditional... " >&6; } +if test "${ac_cv_prog_gcc_traditional+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_pattern="Autoconf.*'x'" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +Autoconf TIOCGETP +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "$ac_pattern" >/dev/null 2>&1; then + ac_cv_prog_gcc_traditional=yes +else + ac_cv_prog_gcc_traditional=no +fi +rm -f conftest* + + + if test $ac_cv_prog_gcc_traditional = no; then + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +Autoconf TCGETA +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "$ac_pattern" >/dev/null 2>&1; then + ac_cv_prog_gcc_traditional=yes +fi +rm -f conftest* + + fi +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_prog_gcc_traditional" >&5 +$as_echo "$ac_cv_prog_gcc_traditional" >&6; } + if test $ac_cv_prog_gcc_traditional = yes; then + CC="$CC -traditional" + fi +fi + +{ $as_echo "$as_me:$LINENO: checking for working memcmp" >&5 +$as_echo_n "checking for working memcmp... " >&6; } +if test "${ac_cv_func_memcmp_working+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then + ac_cv_func_memcmp_working=no +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ + + /* Some versions of memcmp are not 8-bit clean. */ + char c0 = '\100', c1 = '\200', c2 = '\201'; + if (memcmp(&c0, &c2, 1) >= 0 || memcmp(&c1, &c2, 1) >= 0) + return 1; + + /* The Next x86 OpenStep bug shows up only when comparing 16 bytes + or more and with at least one buffer not starting on a 4-byte boundary. + William Lewis provided this test program. */ + { + char foo[21]; + char bar[21]; + int i; + for (i = 0; i < 4; i++) + { + char *a = foo + i; + char *b = bar + i; + strcpy (a, "--------01111111"); + strcpy (b, "--------10000000"); + if (memcmp (a, b, 16) >= 0) + return 1; + } + return 0; + } + + ; + return 0; +} +_ACEOF +rm -f conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { ac_try='./conftest$ac_exeext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + ac_cv_func_memcmp_working=yes +else + $as_echo "$as_me: program exited with status $ac_status" >&5 +$as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +( exit $ac_status ) +ac_cv_func_memcmp_working=no +fi +rm -rf conftest.dSYM +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +fi + + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_func_memcmp_working" >&5 +$as_echo "$ac_cv_func_memcmp_working" >&6; } +test $ac_cv_func_memcmp_working = no && case " $LIB@&t@OBJS " in + *" memcmp.$ac_objext "* ) ;; + *) LIB@&t@OBJS="$LIB@&t@OBJS memcmp.$ac_objext" + ;; +esac + + +{ $as_echo "$as_me:$LINENO: checking return type of signal handlers" >&5 +$as_echo_n "checking return type of signal handlers... " >&6; } +if test "${ac_cv_type_signal+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include + +int +main () +{ +return *(signal (0, 0)) (0) == 1; + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_type_signal=int +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_type_signal=void +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_type_signal" >&5 +$as_echo "$ac_cv_type_signal" >&6; } + +cat >>confdefs.h <<_ACEOF +@%:@define RETSIGTYPE $ac_cv_type_signal +_ACEOF + + + + + + + + + + +for ac_func in gettimeofday strchr strstr setvbuf getenv unlink mkstemp close +do +as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +{ $as_echo "$as_me:$LINENO: checking for $ac_func" >&5 +$as_echo_n "checking for $ac_func... " >&6; } +if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +/* Define $ac_func to an innocuous variant, in case declares $ac_func. + For example, HP-UX 11i declares gettimeofday. */ +#define $ac_func innocuous_$ac_func + +/* System header to define __stub macros and hopefully few prototypes, + which can conflict with char $ac_func (); below. + Prefer to if __STDC__ is defined, since + exists even on freestanding compilers. */ + +#ifdef __STDC__ +# include +#else +# include +#endif + +#undef $ac_func + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char $ac_func (); +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. 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Please make sure it is defined." >&2;} + + rm -f "$tmp/stdin" + case $ac_file in + -) cat "$tmp/out" && rm -f "$tmp/out";; + *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";; + esac \ + || { { $as_echo "$as_me:$LINENO: error: could not create $ac_file" >&5 +$as_echo "$as_me: error: could not create $ac_file" >&2;} + { (exit 1); exit 1; }; } + ;; + + + + esac + +done # for ac_tag + + +{ (exit 0); exit 0; } +_ACEOF +chmod +x $CONFIG_STATUS +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + { { $as_echo "$as_me:$LINENO: error: write failure creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: error: write failure creating $CONFIG_STATUS" >&2;} + { (exit 1); exit 1; }; } + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || { (exit 1); exit 1; } +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:$LINENO: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + Index: vis_dev/vis-2.1/autom4te.cache/requests =================================================================== --- vis_dev/vis-2.1/autom4te.cache/requests (revision 11) +++ vis_dev/vis-2.1/autom4te.cache/requests (revision 11) @@ -0,0 +1,134 @@ +# This file was generated. +# It contains the lists of macros which have been traced. +# It can be safely removed. + +@request = ( + bless( [ + '0', + 1, + [ + '/usr/share/autoconf' + ], + [ + '/usr/share/autoconf/autoconf/autoconf.m4f', + 'configure.in' + ], + { + '_LT_AC_TAGCONFIG' => 1, + 'AM_PROG_F77_C_O' => 1, + 'm4_pattern_forbid' => 1, + 'AC_CANONICAL_TARGET' => 1, + 'AC_CONFIG_LIBOBJ_DIR' => 1, + 'AC_C_VOLATILE' => 1, + 'AC_TYPE_OFF_T' => 1, + 'AC_FUNC_CLOSEDIR_VOID' => 1, + 'AC_REPLACE_FNMATCH' => 1, + 'AC_PROG_LIBTOOL' => 1, + 'AC_FUNC_STAT' => 1, + 'AC_FUNC_WAIT3' => 1, + 'AC_HEADER_TIME' => 1, + 'AC_FUNC_LSTAT' => 1, + 'AC_STRUCT_TM' => 1, + 'AM_AUTOMAKE_VERSION' => 1, + 'AC_FUNC_GETMNTENT' => 1, + 'AC_TYPE_MODE_T' => 1, + 'AC_CHECK_HEADERS' => 1, + 'AC_FUNC_STRTOD' => 1, + 'LT_CONFIG_LTDL_DIR' => 1, + 'AC_FUNC_STRNLEN' => 1, + 'm4_sinclude' => 1, + 'AC_PROG_CXX' => 1, + 'AC_PATH_X' => 1, + 'AC_FUNC_LSTAT_FOLLOWS_SLASHED_SYMLINK' => 1, + 'AC_PROG_AWK' => 1, + '_m4_warn' => 1, + 'AC_HEADER_STDC' => 1, + 'AC_HEADER_MAJOR' => 1, + 'AM_PROG_CXX_C_O' => 1, + 'LT_INIT' => 1, + 'AC_FUNC_ERROR_AT_LINE' => 1, + 'AC_PROG_GCC_TRADITIONAL' => 1, + 'AC_LIBSOURCE' => 1, + 'AC_FUNC_MBRTOWC' => 1, + 'AC_STRUCT_ST_BLOCKS' => 1, + 'AC_TYPE_SIGNAL' => 1, + 'AC_CANONICAL_BUILD' => 1, + 'AM_PROG_FC_C_O' => 1, + 'AC_TYPE_UID_T' => 1, + 'AC_PROG_MAKE_SET' => 1, + 'AC_CONFIG_AUX_DIR' => 1, + '_AM_SUBST_NOTMAKE' => 1, + 'm4_pattern_allow' => 1, + 'sinclude' => 1, + 'AC_DEFINE_TRACE_LITERAL' => 1, + 'AC_FUNC_STRERROR_R' => 1, + 'AC_PROG_CC' => 1, + 'AC_DECL_SYS_SIGLIST' => 1, + 'AC_FUNC_FORK' => 1, + '_AM_COND_ELSE' => 1, + 'AC_FUNC_STRCOLL' => 1, + 'AC_FUNC_VPRINTF' => 1, + 'AC_PROG_YACC' => 1, + 'AC_SUBST_TRACE' => 1, + 'AC_INIT' => 1, + 'AC_STRUCT_TIMEZONE' => 1, + '_AM_COND_IF' => 1, + 'AC_FUNC_CHOWN' => 1, + 'AC_SUBST' => 1, + 'AC_FUNC_ALLOCA' => 1, + 'AC_FUNC_GETPGRP' => 1, + 'AC_FC_SRCEXT' => 1, + 'AC_CANONICAL_HOST' => 1, + 'AC_PROG_RANLIB' => 1, + 'AC_FUNC_SETPGRP' => 1, + 'AM_INIT_AUTOMAKE' => 1, + 'AC_CONFIG_SUBDIRS' => 1, + 'AC_FUNC_MMAP' => 1, + 'AC_FUNC_REALLOC' => 1, + 'AC_TYPE_SIZE_T' => 1, + 'AC_CHECK_TYPES' => 1, + 'AC_CONFIG_LINKS' => 1, + 'AC_REQUIRE_AUX_FILE' => 1, + 'LT_SUPPORTED_TAG' => 1, + 'AC_CHECK_MEMBERS' => 1, + 'AM_MAINTAINER_MODE' => 1, + 'AC_FUNC_UTIME_NULL' => 1, + 'AC_FUNC_SELECT_ARGTYPES' => 1, + 'AM_GNU_GETTEXT_INTL_SUBDIR' => 1, + 'AC_HEADER_STAT' => 1, + 'AC_FUNC_STRFTIME' => 1, + 'AC_PROG_CPP' => 1, + 'AC_C_INLINE' => 1, + '_AM_COND_ENDIF' => 1, + 'AC_PROG_LEX' => 1, + 'AC_C_CONST' => 1, + 'AC_TYPE_PID_T' => 1, + 'AM_ENABLE_MULTILIB' => 1, + 'AC_CONFIG_FILES' => 1, + 'include' => 1, + 'AC_FUNC_SETVBUF_REVERSED' => 1, + 'AC_PROG_INSTALL' => 1, + 'AM_GNU_GETTEXT' => 1, + 'AC_CHECK_LIB' => 1, + 'AC_FUNC_OBSTACK' => 1, + 'AC_FUNC_MALLOC' => 1, + 'AC_FUNC_GETGROUPS' => 1, + 'AC_FUNC_GETLOADAVG' => 1, + 'AC_FC_FREEFORM' => 1, + 'AH_OUTPUT' => 1, + 'AC_FUNC_FSEEKO' => 1, + 'AM_PROG_CC_C_O' => 1, + 'AC_FUNC_MKTIME' => 1, + 'AC_CANONICAL_SYSTEM' => 1, + 'AM_CONDITIONAL' => 1, + 'AC_CONFIG_HEADERS' => 1, + 'AC_HEADER_SYS_WAIT' => 1, + 'AC_PROG_LN_S' => 1, + 'AC_FUNC_MEMCMP' => 1, + 'm4_include' => 1, + 'AC_HEADER_DIRENT' => 1, + 'AC_CHECK_FUNCS' => 1 + } + ], 'Autom4te::Request' ) + ); + Index: vis_dev/vis-2.1/autom4te.cache/traces.0 =================================================================== --- vis_dev/vis-2.1/autom4te.cache/traces.0 (revision 11) +++ vis_dev/vis-2.1/autom4te.cache/traces.0 (revision 11) @@ -0,0 +1,497 @@ +m4trace:configure.in:42: -1- AC_INIT([src/cmd/cmd.h]) +m4trace:configure.in:42: -1- m4_pattern_forbid([^_?A[CHUM]_]) +m4trace:configure.in:42: -1- m4_pattern_forbid([_AC_]) +m4trace:configure.in:42: -1- m4_pattern_forbid([^LIBOBJS$], [do not use LIBOBJS directly, use AC_LIBOBJ (see section `AC_LIBOBJ vs LIBOBJS']) +m4trace:configure.in:42: -1- m4_pattern_allow([^AS_FLAGS$]) +m4trace:configure.in:42: -1- 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configure script is free software; the Free Software Foundation +# gives unlimited permission to copy, distribute and modify it. +## --------------------- ## +## M4sh Initialization. ## +## --------------------- ## + +# Be more Bourne compatible +DUALCASE=1; export DUALCASE # for MKS sh +if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then + emulate sh + NULLCMD=: + # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which + # is contrary to our usage. Disable this feature. + alias -g '${1+"$@"}'='"$@"' + setopt NO_GLOB_SUBST +else + case `(set -o) 2>/dev/null` in + *posix*) set -o posix ;; +esac + +fi + + + + +# PATH needs CR +# Avoid depending upon Character Ranges. +as_cr_letters='abcdefghijklmnopqrstuvwxyz' +as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' +as_cr_Letters=$as_cr_letters$as_cr_LETTERS +as_cr_digits='0123456789' +as_cr_alnum=$as_cr_Letters$as_cr_digits + +as_nl=' +' +export as_nl +# Printing a long string crashes Solaris 7 /usr/bin/printf. +as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo +as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo +if (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then + as_echo='printf %s\n' + as_echo_n='printf %s' +else + if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then + as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' + as_echo_n='/usr/ucb/echo -n' + else + as_echo_body='eval expr "X$1" : "X\\(.*\\)"' + as_echo_n_body='eval + arg=$1; + case $arg in + *"$as_nl"*) + expr "X$arg" : "X\\(.*\\)$as_nl"; + arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; + esac; + expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" + ' + export as_echo_n_body + as_echo_n='sh -c $as_echo_n_body as_echo' + fi + export as_echo_body + as_echo='sh -c $as_echo_body as_echo' +fi + +# The user is always right. +if test "${PATH_SEPARATOR+set}" != set; then + PATH_SEPARATOR=: + (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { + (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || + PATH_SEPARATOR=';' + } +fi + +# Support unset when possible. +if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then + as_unset=unset +else + as_unset=false +fi + + +# IFS +# We need space, tab and new line, in precisely that order. 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Use of quotes ensures accuracy. + *) ac_configure_args="$ac_configure_args '$ac_arg'" ;; + esac + fi +done +if $ac_cache_corrupted; then + { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} + { $as_echo "$as_me:$LINENO: error: changes in the environment can compromise the build" >&5 +$as_echo "$as_me: error: changes in the environment can compromise the build" >&2;} + { { $as_echo "$as_me:$LINENO: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&5 +$as_echo "$as_me: error: run \`make distclean' and/or \`rm $cache_file' and start over" >&2;} + { (exit 1); exit 1; }; } +fi + + + + + + + + + + + + + + + + + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + + +# Look for install.sh, config.guess, and config.sub in the "helpers" dir +ac_aux_dir= +for ac_dir in helpers "$srcdir"/helpers; do + if test -f "$ac_dir/install-sh"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install-sh -c" + break + elif test -f "$ac_dir/install.sh"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/install.sh -c" + break + elif test -f "$ac_dir/shtool"; then + ac_aux_dir=$ac_dir + ac_install_sh="$ac_aux_dir/shtool install -c" + break + fi +done +if test -z "$ac_aux_dir"; then + { { $as_echo "$as_me:$LINENO: error: cannot find install-sh or install.sh in helpers \"$srcdir\"/helpers" >&5 +$as_echo "$as_me: error: cannot find install-sh or install.sh in helpers \"$srcdir\"/helpers" >&2;} + { (exit 1); exit 1; }; } +fi + +# These three variables are undocumented and unsupported, +# and are intended to be withdrawn in a future Autoconf release. +# They can cause serious problems if a builder's source tree is in a directory +# whose full name contains unusual characters. +ac_config_guess="$SHELL $ac_aux_dir/config.guess" # Please don't use this var. +ac_config_sub="$SHELL $ac_aux_dir/config.sub" # Please don't use this var. +ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var. + + + +#---------------------------------------------------------------------- + +# Configuration options +#---------------------------------------------------------------------- + +# Give the configurer a chance to set the location of the GLU tree + + + +# Check whether --with-glu-libdir was given. +if test "${with_glu_libdir+set}" = set; then + withval=$with_glu_libdir; glulibdir=$withval +else + glulibdir="" +fi + + + + +# Check whether --with-glu-incdir was given. +if test "${with_glu_incdir+set}" = set; then + withval=$with_glu_incdir; gluincdir=$withval +else + gluincdir="" +fi + + +# Give the configurer a chance to set a different location for the VIS +# headers and library + + + +# Check whether --with-vis-libdir was given. +if test "${with_vis_libdir+set}" = set; then + withval=$with_vis_libdir; vislibdir=$withval +else + vislibdir="." +fi + + +# Give the configurer a chance to set a different location for the VIS +# source. When specified, "srcdir" points to "master" source, and +# "local_srcdir" points to the source under local development. + + + +# Check whether --with-local-srcdir was given. +if test "${with_local_srcdir+set}" = set; then + withval=$with_local_srcdir; local_srcdir=$withval +else + local_srcdir=$srcdir +fi + + +# Give the configurer a chance to set the BDD library + + + +# Check whether --with-bdd was given. +if test "${with_bdd+set}" = set; then + withval=$with_bdd; BDDLIB=$withval +else + BDDLIB=cu +fi + + +#---------------------------------------------------------------------- +# Checks for programs we need +#---------------------------------------------------------------------- +# Extract the first word of "zchaff", so it can be a program name with args. +set dummy zchaff; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_ZCHAFF+set}" = set; then + $as_echo_n "(cached) " >&6 +else + case $ZCHAFF in + [\\/]* | ?:[\\/]*) + ac_cv_path_ZCHAFF="$ZCHAFF" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_path_ZCHAFF="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + + ;; +esac +fi +ZCHAFF=$ac_cv_path_ZCHAFF +if test -n "$ZCHAFF"; then + { $as_echo "$as_me:$LINENO: result: $ZCHAFF" >&5 +$as_echo "$ZCHAFF" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +# Extract the first word of "sharpSAT", so it can be a program name with args. +set dummy sharpSAT; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_SHARPSAT+set}" = set; then + $as_echo_n "(cached) " >&6 +else + case $SHARPSAT in + [\\/]* | ?:[\\/]*) + ac_cv_path_SHARPSAT="$SHARPSAT" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_path_SHARPSAT="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + + ;; +esac +fi +SHARPSAT=$ac_cv_path_SHARPSAT +if test -n "$SHARPSAT"; then + { $as_echo "$as_me:$LINENO: result: $SHARPSAT" >&5 +$as_echo "$SHARPSAT" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +# Extract the first word of "ar", so it can be a program name with args. +set dummy ar; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_path_AR+set}" = set; then + $as_echo_n "(cached) " >&6 +else + case $AR in + [\\/]* | ?:[\\/]*) + ac_cv_path_AR="$AR" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_path_AR="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + + test -z "$ac_cv_path_AR" && ac_cv_path_AR="ar" + ;; +esac +fi +AR=$ac_cv_path_AR +if test -n "$AR"; then + { $as_echo "$as_me:$LINENO: result: $AR" >&5 +$as_echo "$AR" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. +set dummy ${ac_tool_prefix}ranlib; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_RANLIB+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$RANLIB"; then + ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +RANLIB=$ac_cv_prog_RANLIB +if test -n "$RANLIB"; then + { $as_echo "$as_me:$LINENO: result: $RANLIB" >&5 +$as_echo "$RANLIB" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_RANLIB"; then + ac_ct_RANLIB=$RANLIB + # Extract the first word of "ranlib", so it can be a program name with args. +set dummy ranlib; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_RANLIB"; then + ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_RANLIB="ranlib" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB +if test -n "$ac_ct_RANLIB"; then + { $as_echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5 +$as_echo "$ac_ct_RANLIB" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_RANLIB" = x; then + RANLIB=":" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:$LINENO: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + RANLIB=$ac_ct_RANLIB + fi +else + RANLIB="$ac_cv_prog_RANLIB" +fi + + +# Make sure we can run config.sub. +$SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 || + { { $as_echo "$as_me:$LINENO: error: cannot run $SHELL $ac_aux_dir/config.sub" >&5 +$as_echo "$as_me: error: cannot run $SHELL $ac_aux_dir/config.sub" >&2;} + { (exit 1); exit 1; }; } + +{ $as_echo "$as_me:$LINENO: checking build system type" >&5 +$as_echo_n "checking build system type... " >&6; } +if test "${ac_cv_build+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_build_alias=$build_alias +test "x$ac_build_alias" = x && + ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"` +test "x$ac_build_alias" = x && + { { $as_echo "$as_me:$LINENO: error: cannot guess build type; you must specify one" >&5 +$as_echo "$as_me: error: cannot guess build type; you must specify one" >&2;} + { (exit 1); exit 1; }; } +ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` || + { { $as_echo "$as_me:$LINENO: error: $SHELL $ac_aux_dir/config.sub $ac_build_alias failed" >&5 +$as_echo "$as_me: error: $SHELL $ac_aux_dir/config.sub $ac_build_alias failed" >&2;} + { (exit 1); exit 1; }; } + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_build" >&5 +$as_echo "$ac_cv_build" >&6; } +case $ac_cv_build in +*-*-*) ;; +*) { { $as_echo "$as_me:$LINENO: error: invalid value of canonical build" >&5 +$as_echo "$as_me: error: invalid value of canonical build" >&2;} + { (exit 1); exit 1; }; };; +esac +build=$ac_cv_build +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_build +shift +build_cpu=$1 +build_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +build_os=$* +IFS=$ac_save_IFS +case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:$LINENO: checking host system type" >&5 +$as_echo_n "checking host system type... " >&6; } +if test "${ac_cv_host+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test "x$host_alias" = x; then + ac_cv_host=$ac_cv_build +else + ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || + { { $as_echo "$as_me:$LINENO: error: $SHELL $ac_aux_dir/config.sub $host_alias failed" >&5 +$as_echo "$as_me: error: $SHELL $ac_aux_dir/config.sub $host_alias failed" >&2;} + { (exit 1); exit 1; }; } +fi + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_host" >&5 +$as_echo "$ac_cv_host" >&6; } +case $ac_cv_host in +*-*-*) ;; +*) { { $as_echo "$as_me:$LINENO: error: invalid value of canonical host" >&5 +$as_echo "$as_me: error: invalid value of canonical host" >&2;} + { (exit 1); exit 1; }; };; +esac +host=$ac_cv_host +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_host +shift +host_cpu=$1 +host_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +host_os=$* +IFS=$ac_save_IFS +case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac + + +{ $as_echo "$as_me:$LINENO: checking target system type" >&5 +$as_echo_n "checking target system type... " >&6; } +if test "${ac_cv_target+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test "x$target_alias" = x; then + ac_cv_target=$ac_cv_host +else + ac_cv_target=`$SHELL "$ac_aux_dir/config.sub" $target_alias` || + { { $as_echo "$as_me:$LINENO: error: $SHELL $ac_aux_dir/config.sub $target_alias failed" >&5 +$as_echo "$as_me: error: $SHELL $ac_aux_dir/config.sub $target_alias failed" >&2;} + { (exit 1); exit 1; }; } +fi + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_target" >&5 +$as_echo "$ac_cv_target" >&6; } +case $ac_cv_target in +*-*-*) ;; +*) { { $as_echo "$as_me:$LINENO: error: invalid value of canonical target" >&5 +$as_echo "$as_me: error: invalid value of canonical target" >&2;} + { (exit 1); exit 1; }; };; +esac +target=$ac_cv_target +ac_save_IFS=$IFS; IFS='-' +set x $ac_cv_target +shift +target_cpu=$1 +target_vendor=$2 +shift; shift +# Remember, the first character of IFS is used to create $*, +# except with old shells: +target_os=$* +IFS=$ac_save_IFS +case $target_os in *\ *) target_os=`echo "$target_os" | sed 's/ /-/g'`;; esac + + +# The aliases save the names the user supplied, while $host etc. +# will get canonicalized. +test -n "$target_alias" && + test "$program_prefix$program_suffix$program_transform_name" = \ + NONENONEs,x,x, && + program_prefix=${target_alias}- + + +# Determine the name of the C compiler we're going to use + +# Check whether --enable-gcc was given. +if test "${enable_gcc+set}" = set; then + enableval=$enable_gcc; gcc_ok=$enableval +else + gcc_ok=no +fi + + +# We cannot set CC=g++ directly because many configuration test programs +# do not compile with g++. Hence, when the user specifies --enable-gcc=g++, +# we set CC=gcc during configuration, and then CC=g++ at the end. +# The same applies to icpc and icc. +if test "$gcc_ok" != no; then + case "$gcc_ok" in + yes | g++) + CC=gcc ;; + icpc) + CC=icc ;; + *) + CC=$gcc_ok + esac +else + if test -z "$CC" ; then + # Balakrishna Kumthekar + # As we do not support cc on RS6000, Cygwin and SunOS. + case "$target" in + rs6000-ibm-aix* | *-pc-cygwin32 | sparc-sun-sunos*) + CC=gcc ;; + *) + CC=cc ;; + esac + fi +fi +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. +set dummy ${ac_tool_prefix}gcc; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}gcc" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:$LINENO: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$ac_cv_prog_CC"; then + ac_ct_CC=$CC + # Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="gcc" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:$LINENO: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +else + CC="$ac_cv_prog_CC" +fi + +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. +set dummy ${ac_tool_prefix}cc; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="${ac_tool_prefix}cc" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:$LINENO: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + + fi +fi +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + ac_prog_rejected=no +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# != 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" + fi +fi +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:$LINENO: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + +fi +if test -z "$CC"; then + if test -n "$ac_tool_prefix"; then + for ac_prog in cl.exe + do + # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. +set dummy $ac_tool_prefix$ac_prog; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_CC="$ac_tool_prefix$ac_prog" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +CC=$ac_cv_prog_CC +if test -n "$CC"; then + { $as_echo "$as_me:$LINENO: result: $CC" >&5 +$as_echo "$CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$CC" && break + done +fi +if test -z "$CC"; then + ac_ct_CC=$CC + for ac_prog in cl.exe +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_ac_ct_CC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$ac_ct_CC"; then + ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_ac_ct_CC="$ac_prog" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +ac_ct_CC=$ac_cv_prog_ac_ct_CC +if test -n "$ac_ct_CC"; then + { $as_echo "$as_me:$LINENO: result: $ac_ct_CC" >&5 +$as_echo "$ac_ct_CC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$ac_ct_CC" && break +done + + if test "x$ac_ct_CC" = x; then + CC="" + else + case $cross_compiling:$ac_tool_warned in +yes:) +{ $as_echo "$as_me:$LINENO: WARNING: using cross tools not prefixed with host triplet" >&5 +$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} +ac_tool_warned=yes ;; +esac + CC=$ac_ct_CC + fi +fi + +fi + + +test -z "$CC" && { { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { $as_echo "$as_me:$LINENO: error: no acceptable C compiler found in \$PATH +See \`config.log' for more details." >&5 +$as_echo "$as_me: error: no acceptable C compiler found in \$PATH +See \`config.log' for more details." >&2;} + { (exit 1); exit 1; }; }; } + +# Provide some information about the compiler. +$as_echo "$as_me:$LINENO: checking for C compiler version" >&5 +set X $ac_compile +ac_compiler=$2 +{ (ac_try="$ac_compiler --version >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compiler --version >&5") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } +{ (ac_try="$ac_compiler -v >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compiler -v >&5") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } +{ (ac_try="$ac_compiler -V >&5" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compiler -V >&5") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } + +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +ac_clean_files_save=$ac_clean_files +ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out" +# Try to create an executable without -o first, disregard a.out. +# It will help us diagnose broken compilers, and finding out an intuition +# of exeext. +{ $as_echo "$as_me:$LINENO: checking for C compiler default output file name" >&5 +$as_echo_n "checking for C compiler default output file name... " >&6; } +ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'` + +# The possible output files: +ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*" + +ac_rmfiles= +for ac_file in $ac_files +do + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + * ) ac_rmfiles="$ac_rmfiles $ac_file";; + esac +done +rm -f $ac_rmfiles + +if { (ac_try="$ac_link_default" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link_default") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; then + # Autoconf-2.13 could set the ac_cv_exeext variable to `no'. +# So ignore a value of `no', otherwise this would lead to `EXEEXT = no' +# in a Makefile. We should not override ac_cv_exeext if it was cached, +# so that the user can short-circuit this test for compilers unknown to +# Autoconf. +for ac_file in $ac_files '' +do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) + ;; + [ab].out ) + # We found the default executable, but exeext='' is most + # certainly right. + break;; + *.* ) + if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; + then :; else + ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + fi + # We set ac_cv_exeext here because the later test for it is not + # safe: cross compilers may not add the suffix if given an `-o' + # argument, so we may need to know it at that point already. + # Even if this section looks crufty: it has the advantage of + # actually working. + break;; + * ) + break;; + esac +done +test "$ac_cv_exeext" = no && ac_cv_exeext= + +else + ac_file='' +fi + +{ $as_echo "$as_me:$LINENO: result: $ac_file" >&5 +$as_echo "$ac_file" >&6; } +if test -z "$ac_file"; then + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { $as_echo "$as_me:$LINENO: error: C compiler cannot create executables +See \`config.log' for more details." >&5 +$as_echo "$as_me: error: C compiler cannot create executables +See \`config.log' for more details." >&2;} + { (exit 77); exit 77; }; }; } +fi + +ac_exeext=$ac_cv_exeext + +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:$LINENO: checking whether the C compiler works" >&5 +$as_echo_n "checking whether the C compiler works... " >&6; } +# FIXME: These cross compiler hacks should be removed for Autoconf 3.0 +# If not cross compiling, check that we can run a simple program. +if test "$cross_compiling" != yes; then + if { ac_try='./$ac_file' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + cross_compiling=no + else + if test "$cross_compiling" = maybe; then + cross_compiling=yes + else + { { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { $as_echo "$as_me:$LINENO: error: cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details." >&5 +$as_echo "$as_me: error: cannot run C compiled programs. +If you meant to cross compile, use \`--host'. +See \`config.log' for more details." >&2;} + { (exit 1); exit 1; }; }; } + fi + fi +fi +{ $as_echo "$as_me:$LINENO: result: yes" >&5 +$as_echo "yes" >&6; } + +rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out +ac_clean_files=$ac_clean_files_save +# Check that the compiler produces executables we can run. If not, either +# the compiler is broken, or we cross compile. +{ $as_echo "$as_me:$LINENO: checking whether we are cross compiling" >&5 +$as_echo_n "checking whether we are cross compiling... " >&6; } +{ $as_echo "$as_me:$LINENO: result: $cross_compiling" >&5 +$as_echo "$cross_compiling" >&6; } + +{ $as_echo "$as_me:$LINENO: checking for suffix of executables" >&5 +$as_echo_n "checking for suffix of executables... " >&6; } +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; then + # If both `conftest.exe' and `conftest' are `present' (well, observable) +# catch `conftest.exe'. For instance with Cygwin, `ls conftest' will +# work properly (i.e., refer to `conftest.exe'), while it won't with +# `rm'. +for ac_file in conftest.exe conftest conftest.*; do + test -f "$ac_file" || continue + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; + *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` + break;; + * ) break;; + esac +done +else + { { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { $as_echo "$as_me:$LINENO: error: cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." >&5 +$as_echo "$as_me: error: cannot compute suffix of executables: cannot compile and link +See \`config.log' for more details." >&2;} + { (exit 1); exit 1; }; }; } +fi + +rm -f conftest$ac_cv_exeext +{ $as_echo "$as_me:$LINENO: result: $ac_cv_exeext" >&5 +$as_echo "$ac_cv_exeext" >&6; } + +rm -f conftest.$ac_ext +EXEEXT=$ac_cv_exeext +ac_exeext=$EXEEXT +{ $as_echo "$as_me:$LINENO: checking for suffix of object files" >&5 +$as_echo_n "checking for suffix of object files... " >&6; } +if test "${ac_cv_objext+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.o conftest.obj +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; then + for ac_file in conftest.o conftest.obj conftest.*; do + test -f "$ac_file" || continue; + case $ac_file in + *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; + *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` + break;; + esac +done +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +{ { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { $as_echo "$as_me:$LINENO: error: cannot compute suffix of object files: cannot compile +See \`config.log' for more details." >&5 +$as_echo "$as_me: error: cannot compute suffix of object files: cannot compile +See \`config.log' for more details." >&2;} + { (exit 1); exit 1; }; }; } +fi + +rm -f conftest.$ac_cv_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_objext" >&5 +$as_echo "$ac_cv_objext" >&6; } +OBJEXT=$ac_cv_objext +ac_objext=$OBJEXT +{ $as_echo "$as_me:$LINENO: checking whether we are using the GNU C compiler" >&5 +$as_echo_n "checking whether we are using the GNU C compiler... " >&6; } +if test "${ac_cv_c_compiler_gnu+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ +#ifndef __GNUC__ + choke me +#endif + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_compiler_gnu=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_compiler_gnu=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +ac_cv_c_compiler_gnu=$ac_compiler_gnu + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_c_compiler_gnu" >&5 +$as_echo "$ac_cv_c_compiler_gnu" >&6; } +if test $ac_compiler_gnu = yes; then + GCC=yes +else + GCC= +fi +ac_test_CFLAGS=${CFLAGS+set} +ac_save_CFLAGS=$CFLAGS +{ $as_echo "$as_me:$LINENO: checking whether $CC accepts -g" >&5 +$as_echo_n "checking whether $CC accepts -g... " >&6; } +if test "${ac_cv_prog_cc_g+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_save_c_werror_flag=$ac_c_werror_flag + ac_c_werror_flag=yes + ac_cv_prog_cc_g=no + CFLAGS="-g" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_prog_cc_g=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + CFLAGS="" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + : +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_c_werror_flag=$ac_save_c_werror_flag + CFLAGS="-g" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_prog_cc_g=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + ac_c_werror_flag=$ac_save_c_werror_flag +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_prog_cc_g" >&5 +$as_echo "$ac_cv_prog_cc_g" >&6; } +if test "$ac_test_CFLAGS" = set; then + CFLAGS=$ac_save_CFLAGS +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi +{ $as_echo "$as_me:$LINENO: checking for $CC option to accept ISO C89" >&5 +$as_echo_n "checking for $CC option to accept ISO C89... " >&6; } +if test "${ac_cv_prog_cc_c89+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_cv_prog_cc_c89=no +ac_save_CC=$CC +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include +#include +#include +/* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ +struct buf { int x; }; +FILE * (*rcsopen) (struct buf *, struct stat *, int); +static char *e (p, i) + char **p; + int i; +{ + return p[i]; +} +static char *f (char * (*g) (char **, int), char **p, ...) +{ + char *s; + va_list v; + va_start (v,p); + s = g (p, va_arg (v,int)); + va_end (v); + return s; +} + +/* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has + function prototypes and stuff, but not '\xHH' hex character constants. + These don't provoke an error unfortunately, instead are silently treated + as 'x'. The following induces an error, until -std is added to get + proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an + array size at least. It's necessary to write '\x00'==0 to get something + that's true only with -std. */ +int osf4_cc_array ['\x00' == 0 ? 1 : -1]; + +/* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters + inside strings and character constants. */ +#define FOO(x) 'x' +int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; + +int test (int i, double x); +struct s1 {int (*f) (int a);}; +struct s2 {int (*f) (double a);}; +int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); +int argc; +char **argv; +int +main () +{ +return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; + ; + return 0; +} +_ACEOF +for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ + -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" +do + CC="$ac_save_CC $ac_arg" + rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_prog_cc_c89=$ac_arg +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -f core conftest.err conftest.$ac_objext + test "x$ac_cv_prog_cc_c89" != "xno" && break +done +rm -f conftest.$ac_ext +CC=$ac_save_CC + +fi +# AC_CACHE_VAL +case "x$ac_cv_prog_cc_c89" in + x) + { $as_echo "$as_me:$LINENO: result: none needed" >&5 +$as_echo "none needed" >&6; } ;; + xno) + { $as_echo "$as_me:$LINENO: result: unsupported" >&5 +$as_echo "unsupported" >&6; } ;; + *) + CC="$CC $ac_cv_prog_cc_c89" + { $as_echo "$as_me:$LINENO: result: $ac_cv_prog_cc_c89" >&5 +$as_echo "$ac_cv_prog_cc_c89" >&6; } ;; +esac + + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +# Check whether --enable-64 was given. +if test "${enable_64+set}" = set; then + enableval=$enable_64; use_sixty_four=$enableval +else + use_sixty_four=no +fi + + +# Gcc does not support 32-bit pointers on the Alphas. +if test "$gcc_ok" != no; then + use_sixty_four=yes +fi + + +# Roderick Bloem (rbloem@colorado.edu): making a special case for +# ultrix install, since it's annoying about setting groupids. +case "$target" in + mips-dec-ultrix*) + INSTALL="helpers/install-sh -c" + INSTALL_PROGRAM="\${INSTALL}" + INSTALL_DATA="\${INSTALL} -m 644";; + + *) + # Find a good install program. We prefer a C program (faster), +# so one script is as good as another. But avoid the broken or +# incompatible versions: +# SysV /etc/install, /usr/sbin/install +# SunOS /usr/etc/install +# IRIX /sbin/install +# AIX /bin/install +# AmigaOS /C/install, which installs bootblocks on floppy discs +# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag +# AFS /usr/afsws/bin/install, which mishandles nonexistent args +# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" +# OS/2's system install, which has a completely different semantic +# ./install, which can be erroneously created by make from ./install.sh. +# Reject install programs that cannot install multiple files. +{ $as_echo "$as_me:$LINENO: checking for a BSD-compatible install" >&5 +$as_echo_n "checking for a BSD-compatible install... " >&6; } +if test -z "$INSTALL"; then +if test "${ac_cv_path_install+set}" = set; then + $as_echo_n "(cached) " >&6 +else + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + # Account for people who put trailing slashes in PATH elements. +case $as_dir/ in + ./ | .// | /cC/* | \ + /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ + ?:\\/os2\\/install\\/* | ?:\\/OS2\\/INSTALL\\/* | \ + /usr/ucb/* ) ;; + *) + # OSF1 and SCO ODT 3.0 have their own names for install. + # Don't use installbsd from OSF since it installs stuff as root + # by default. + for ac_prog in ginstall scoinst install; do + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then + if test $ac_prog = install && + grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # AIX install. It has an incompatible calling convention. + : + elif test $ac_prog = install && + grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then + # program-specific install script used by HP pwplus--don't use. + : + else + rm -rf conftest.one conftest.two conftest.dir + echo one > conftest.one + echo two > conftest.two + mkdir conftest.dir + if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && + test -s conftest.one && test -s conftest.two && + test -s conftest.dir/conftest.one && + test -s conftest.dir/conftest.two + then + ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" + break 3 + fi + fi + fi + done + done + ;; +esac + +done +IFS=$as_save_IFS + +rm -rf conftest.one conftest.two conftest.dir + +fi + if test "${ac_cv_path_install+set}" = set; then + INSTALL=$ac_cv_path_install + else + # As a last resort, use the slow shell script. Don't cache a + # value for INSTALL within a source directory, because that will + # break other packages using the cache if that directory is + # removed, or if the value is a relative name. + INSTALL=$ac_install_sh + fi +fi +{ $as_echo "$as_me:$LINENO: result: $INSTALL" >&5 +$as_echo "$INSTALL" >&6; } + +# Use test -z because SunOS4 sh mishandles braces in ${var-val}. +# It thinks the first close brace ends the variable substitution. +test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' + +test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' + +test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' + ;; +esac + +# Determine the compiler flags to use + +DEBUG_CFLAGS="-g" +DEBUG_LDFLAGS="" + +case "$target" in + + i686-pc-linux-gnu) + # Linux with Intel compiler + # -ansi: ANSI C conformance + # -ip: inter-procedural optimization + OPTIMIZE_CFLAGS="-g -O3 -ansi -ip" + ;; + + sparc-sun-solaris* | i386-pc-solaris*) + # Sparc and X86 Solaris: + # -xO3: Highest safe level of optimization + # -native: Optimize for the native processor (if supported) + # -dalign: Generate double-word load/store for performance + # (only for SPARC) + # and other arcane compilation flags. + if test "$GCC" = yes; then + OPTIMIZE_CFLAGS="-O" + else + case "$target" in + sparc-sun-solaris*) + ALIGN=" -dalign" ;; + *) + ALIGN="" ;; + esac + { $as_echo "$as_me:$LINENO: checking for -native" >&5 +$as_echo_n "checking for -native... " >&6; } + CFLAGS="-xO3 -native$ALIGN" + +if test "${ac_cv_have_native+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then + ac_cv_have_native=no +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + + main(){exit(0);} + +_ACEOF +rm -f conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { ac_try='./conftest$ac_exeext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + ac_cv_have_native=yes +else + $as_echo "$as_me: program exited with status $ac_status" >&5 +$as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +( exit $ac_status ) +ac_cv_have_native=no +fi +rm -rf conftest.dSYM +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +fi + + +fi + + if test $ac_cv_have_native = yes ; then + { $as_echo "$as_me:$LINENO: result: working" >&5 +$as_echo "working" >&6; } + OPTIMIZE_CFLAGS="-xO3 -native$ALIGN" + else + { $as_echo "$as_me:$LINENO: result: broken" >&5 +$as_echo "broken" >&6; } + { $as_echo "$as_me:$LINENO: checking for fallback optimization flags" >&5 +$as_echo_n "checking for fallback optimization flags... " >&6; } + CFLAGS="-xO3 -fns -fsimple=2$ALIGN -ftrap=%none -xlibmil" + if test "${ac_cv_have_fallback+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then + ac_cv_have_fallback=no +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + + main(){exit(0);} + +_ACEOF +rm -f conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { ac_try='./conftest$ac_exeext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + ac_cv_have_fallback=yes +else + $as_echo "$as_me: program exited with status $ac_status" >&5 +$as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +( exit $ac_status ) +ac_cv_have_fallback=no +fi +rm -rf conftest.dSYM +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +fi + + +fi + + if test $ac_cv_have_fallback = yes ; then + { $as_echo "$as_me:$LINENO: result: working" >&5 +$as_echo "working" >&6; } + OPTIMIZE_CFLAGS="-xO3 -fns -fsimple=2$ALIGN -ftrap=%none -xlibmil" + else + { $as_echo "$as_me:$LINENO: result: broken" >&5 +$as_echo "broken" >&6; } + OPTIMIZE_CFLAGS="-O" + fi + fi + fi + ;; + + mips-dec-ultrix*) + # MIPS-based DECstations running Ultrix: + # -std1: Produce non-ANSI code warnings, and define __STDC__ + # -O: Use the global "ucode" optimizer + # -Olimit 5000: Don't optimize routines bigger than 5000 basic blocks + OPTIMIZE_CFLAGS="-std1 -O -Olimit 5000" ;; + + alpha-dec-osf*) + # DEC Alpha running OSF: + + # 64-bit mode: + # -g3: Produce symbol table information for optimized code + # -O4: Enable every optimization + # -std: Enforce the ANSI standard with extensions, define __STDC__ + # -ieee_with_no_inexact: Disable (potentially slow) signaling + # for inexact floating-point results + # -tune host: Tune instructions for the compilation host machine + OPTIMIZE_CFLAGS="-g3 -O4 -std -ieee_with_no_inexact -tune host" + DEBUG_CFLAGS="-g -std -ieee_with_no_inexact" + + # -non_shared: Do not use shared libraries + # -om: Generate an OMAGIC file for the om optimizer + OPTIMIZE_LDFLAGS="-non_shared" + + if test "$use_sixty_four" = "no"; then + # 32-bit mode: + # -xtaso: Make the compiler respond to #pragma pointer_size directives + OPTIMIZE_CFLAGS="$OPTIMIZE_CFLAGS -xtaso" + DEBUG_CFLAGS="$DEBUG_CFLAGS -xtaso" + + # -taso: Load the executable into the lower 31-bit address space + OPTIMIZE_LDFLAGS="$OPTIMIZE_LDFLAGS -om -taso" + DEBUG_LDFLAGS="$DEBUG_LDFLAGS -taso" + + cat >>confdefs.h <<\_ACEOF +#define SIZEOF_VOID_P 4 +_ACEOF + + ac_sizeof_voidp=4 + fi + ;; + + hppa*-*-hpux*) + # HP running HPUX + # -Aa: Behave as an ANSI compiler + # -D_HPUX_SOURCE: Include "HP-specific" symbols in the header + # files (e.g., this means sys/resource.h has struct rusage) + # +Onolimit: removes resource restrictions for optimization + OPTIMIZE_CFLAGS="-O -Aa +Onolimit -D_HPUX_SOURCE" + DEBUG_CFLAGS="-g -Aa -D_HPUX_SOURCE" ;; + + *) + # Other systems: + OPTIMIZE_CFLAGS="-O" ;; + +esac + +if test "$GCC" = yes; then + case "$target" in + i686-pc-linux-gnu | i386-pc-solaris* | i386-pc-cygwin32 | i386-*-freebsd*) + { $as_echo "$as_me:$LINENO: checking for -mcpu and -malign compiler options" >&5 +$as_echo_n "checking for -mcpu and -malign compiler options... " >&6; } + CFLAGS="-g -O3 -mcpu=pentiumpro -malign-double" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_have_mcpu=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_have_mcpu=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "$ac_have_mcpu" = yes; then + { $as_echo "$as_me:$LINENO: result: working" >&5 +$as_echo "working" >&6; } + OPTIMIZE_CFLAGS="-g -O3 -mcpu=pentiumpro -malign-double" + else + { $as_echo "$as_me:$LINENO: result: broken" >&5 +$as_echo "broken" >&6; } + OPTIMIZE_CFLAGS="-g -O3" + fi + ;; + sparc-sun-solaris*) + { $as_echo "$as_me:$LINENO: checking for -mtune compiler option" >&5 +$as_echo_n "checking for -mtune compiler option... " >&6; } + CFLAGS="-g -O3 -mtune=ultrasparc" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_have_mtune=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_have_mtune=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + if test "$ac_have_mtune" = yes; then + { $as_echo "$as_me:$LINENO: result: working" >&5 +$as_echo "working" >&6; } + OPTIMIZE_CFLAGS="-g -O3 -mtune=ultrasparc" + else + { $as_echo "$as_me:$LINENO: result: not working" >&5 +$as_echo "not working" >&6; } + OPTIMIZE_CFLAGS="-g -O3" + fi + ;; + *) + OPTIMIZE_CFLAGS="-g -O3" + ;; + esac + OPTIMIZE_LDFLAGS="" + DEBUG_CFLAGS="-g" + DEBUG_LDFLAGS="" +fi + + +# Check whether --with-comp-mode was given. +if test "${with_comp_mode+set}" = set; then + withval=$with_comp_mode; comp_mode=$withval +else + comp_mode=optimize +fi + + + + +LINKER="$CC" + +case "$comp_mode" in + debug) + CFLAGS="$DEBUG_CFLAGS" + LDFLAGS="$DEBUG_LDFLAGS" ;; + purify) + CFLAGS="$DEBUG_CFLAGS" + LDFLAGS="$DEBUG_LDFLAGS" + cat >>confdefs.h <<\_ACEOF +#define PURIFY 1 +_ACEOF + + LINKER="purify -cache-dir=/tmp $CC" + PLINKER="purify -log-file=./purify.log -cachedir=/tmp $CC" ;; + quantify) + CFLAGS="$OPTIMIZE_CFLAGS" + LDFLAGS="$OPTIMIZE_LDFLAGS" + cat >>confdefs.h <<\_ACEOF +#define QUANTIFY 1 +_ACEOF + + cat >>confdefs.h <<\_ACEOF +#define NDEBUG 1 +_ACEOF + + LINKER="quantify $CC" ;; + optimize | *) + CFLAGS="$OPTIMIZE_CFLAGS" + LDFLAGS="$OPTIMIZE_LDFLAGS" + cat >>confdefs.h <<\_ACEOF +#define NDEBUG 1 +_ACEOF + ;; +esac + +for ac_prog in flex lex +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_LEX+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$LEX"; then + ac_cv_prog_LEX="$LEX" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_LEX="$ac_prog" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +LEX=$ac_cv_prog_LEX +if test -n "$LEX"; then + { $as_echo "$as_me:$LINENO: result: $LEX" >&5 +$as_echo "$LEX" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$LEX" && break +done +test -n "$LEX" || LEX=":" + +if test "x$LEX" != "x:"; then + cat >conftest.l <<_ACEOF +%% +a { ECHO; } +b { REJECT; } +c { yymore (); } +d { yyless (1); } +e { yyless (input () != 0); } +f { unput (yytext[0]); } +. { BEGIN INITIAL; } +%% +#ifdef YYTEXT_POINTER +extern char *yytext; +#endif +int +main (void) +{ + return ! yylex () + ! yywrap (); +} +_ACEOF +{ (ac_try="$LEX conftest.l" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$LEX conftest.l") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } +{ $as_echo "$as_me:$LINENO: checking lex output file root" >&5 +$as_echo_n "checking lex output file root... " >&6; } +if test "${ac_cv_prog_lex_root+set}" = set; then + $as_echo_n "(cached) " >&6 +else + +if test -f lex.yy.c; then + ac_cv_prog_lex_root=lex.yy +elif test -f lexyy.c; then + ac_cv_prog_lex_root=lexyy +else + { { $as_echo "$as_me:$LINENO: error: cannot find output from $LEX; giving up" >&5 +$as_echo "$as_me: error: cannot find output from $LEX; giving up" >&2;} + { (exit 1); exit 1; }; } +fi +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_prog_lex_root" >&5 +$as_echo "$ac_cv_prog_lex_root" >&6; } +LEX_OUTPUT_ROOT=$ac_cv_prog_lex_root + +if test -z "${LEXLIB+set}"; then + { $as_echo "$as_me:$LINENO: checking lex library" >&5 +$as_echo_n "checking lex library... " >&6; } +if test "${ac_cv_lib_lex+set}" = set; then + $as_echo_n "(cached) " >&6 +else + + ac_save_LIBS=$LIBS + ac_cv_lib_lex='none needed' + for ac_lib in '' -lfl -ll; do + LIBS="$ac_lib $ac_save_LIBS" + cat >conftest.$ac_ext <<_ACEOF +`cat $LEX_OUTPUT_ROOT.c` +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_lex=$ac_lib +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext + test "$ac_cv_lib_lex" != 'none needed' && break + done + LIBS=$ac_save_LIBS + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_lex" >&5 +$as_echo "$ac_cv_lib_lex" >&6; } + test "$ac_cv_lib_lex" != 'none needed' && LEXLIB=$ac_cv_lib_lex +fi + + +{ $as_echo "$as_me:$LINENO: checking whether yytext is a pointer" >&5 +$as_echo_n "checking whether yytext is a pointer... " >&6; } +if test "${ac_cv_prog_lex_yytext_pointer+set}" = set; then + $as_echo_n "(cached) " >&6 +else + # POSIX says lex can declare yytext either as a pointer or an array; the +# default is implementation-dependent. Figure out which it is, since +# not all implementations provide the %pointer and %array declarations. +ac_cv_prog_lex_yytext_pointer=no +ac_save_LIBS=$LIBS +LIBS="$LEXLIB $ac_save_LIBS" +cat >conftest.$ac_ext <<_ACEOF +#define YYTEXT_POINTER 1 +`cat $LEX_OUTPUT_ROOT.c` +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_prog_lex_yytext_pointer=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_save_LIBS + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_prog_lex_yytext_pointer" >&5 +$as_echo "$ac_cv_prog_lex_yytext_pointer" >&6; } +if test $ac_cv_prog_lex_yytext_pointer = yes; then + +cat >>confdefs.h <<\_ACEOF +#define YYTEXT_POINTER 1 +_ACEOF + +fi +rm -f conftest.l $LEX_OUTPUT_ROOT.c + +fi +{ $as_echo "$as_me:$LINENO: checking if $LEX accepts the -o and -P options" >&5 +$as_echo_n "checking if $LEX accepts the -o and -P options... " >&6; } + +if test "${ac_cv_flex_accepts_op+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_cv_flex_accepts_op=yes ; +echo "%%\ +%%" | $LEX -Ptest -o/dev/null >/dev/null 2>&1 || ac_cv_flex_accepts_op=no +fi + +if test $ac_cv_flex_accepts_op = yes ; then + { $as_echo "$as_me:$LINENO: result: yes" >&5 +$as_echo "yes" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } + { $as_echo "$as_me:$LINENO: WARNING: You either need a newer version of flex, or need to modify +the defintion of LEX in the Makefile to point to a version that does +accept -p -t and -o." >&5 +$as_echo "$as_me: WARNING: You either need a newer version of flex, or need to modify +the defintion of LEX in the Makefile to point to a version that does +accept -p -t and -o." >&2;} +fi + +for ac_prog in 'bison -y' byacc +do + # Extract the first word of "$ac_prog", so it can be a program name with args. +set dummy $ac_prog; ac_word=$2 +{ $as_echo "$as_me:$LINENO: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if test "${ac_cv_prog_YACC+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -n "$YACC"; then + ac_cv_prog_YACC="$YACC" # Let the user override the test. +else +as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then + ac_cv_prog_YACC="$ac_prog" + $as_echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done +done +IFS=$as_save_IFS + +fi +fi +YACC=$ac_cv_prog_YACC +if test -n "$YACC"; then + { $as_echo "$as_me:$LINENO: result: $YACC" >&5 +$as_echo "$YACC" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + + + test -n "$YACC" && break +done +test -n "$YACC" || YACC="yacc" + +{ $as_echo "$as_me:$LINENO: checking if $YACC accepts the -p, -t, and -o options" >&5 +$as_echo_n "checking if $YACC accepts the -p, -t, and -o options... " >&6; } +if test "${ac_cv_yacc_accepts_pto+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_cv_yacc_accepts_pto=yes ; +echo "%token terminal\ +%%\ +nonterminal: terminal\ +%%" > config.in +$YACC -ptest -o /dev/null config.in >/dev/null 2>&1 || ac_cv_yacc_accepts_pto=no +rm -f config.in +fi + +if test $ac_cv_yacc_accepts_pto = yes ; then + { $as_echo "$as_me:$LINENO: result: yes" >&5 +$as_echo "yes" >&6; } +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } + { $as_echo "$as_me:$LINENO: WARNING: You either need a newer version of bison, or need to modify +the defintion of YACC in the Makefile to point to a version that does +accept -p -t and -o." >&5 +$as_echo "$as_me: WARNING: You either need a newer version of bison, or need to modify +the defintion of YACC in the Makefile to point to a version that does +accept -p -t and -o." >&2;} +fi + +#---------------------------------------------------------------------- +# Checks for headers and libraries +#---------------------------------------------------------------------- +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu +{ $as_echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5 +$as_echo_n "checking how to run the C preprocessor... " >&6; } +# On Suns, sometimes $CPP names a directory. +if test -n "$CPP" && test -d "$CPP"; then + CPP= +fi +if test -z "$CPP"; then + if test "${ac_cv_prog_CPP+set}" = set; then + $as_echo_n "(cached) " >&6 +else + # Double quotes because CPP needs to be expanded + for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" + do + ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + : +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + # Broken: fails on valid input. +continue +fi + +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + # Broken: success on invalid input. +continue +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + # Passes both tests. +ac_preproc_ok=: +break +fi + +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then + break +fi + + done + ac_cv_prog_CPP=$CPP + +fi + CPP=$ac_cv_prog_CPP +else + ac_cv_prog_CPP=$CPP +fi +{ $as_echo "$as_me:$LINENO: result: $CPP" >&5 +$as_echo "$CPP" >&6; } +ac_preproc_ok=false +for ac_c_preproc_warn_flag in '' yes +do + # Use a header file that comes with gcc, so configuring glibc + # with a fresh cross-compiler works. + # Prefer to if __STDC__ is defined, since + # exists even on freestanding compilers. + # On the NeXT, cc -E runs the code through the compiler's parser, + # not just through cpp. "Syntax error" is here to catch this case. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#ifdef __STDC__ +# include +#else +# include +#endif + Syntax error +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + : +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + # Broken: fails on valid input. +continue +fi + +rm -f conftest.err conftest.$ac_ext + + # OK, works on sane cases. Now check whether nonexistent headers + # can be detected and how. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + # Broken: success on invalid input. +continue +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + # Passes both tests. +ac_preproc_ok=: +break +fi + +rm -f conftest.err conftest.$ac_ext + +done +# Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. +rm -f conftest.err conftest.$ac_ext +if $ac_preproc_ok; then + : +else + { { $as_echo "$as_me:$LINENO: error: in \`$ac_pwd':" >&5 +$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} +{ { $as_echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." >&5 +$as_echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check +See \`config.log' for more details." >&2;} + { (exit 1); exit 1; }; }; } +fi + +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' +ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' +ac_compiler_gnu=$ac_cv_c_compiler_gnu + + +{ $as_echo "$as_me:$LINENO: checking for grep that handles long lines and -e" >&5 +$as_echo_n "checking for grep that handles long lines and -e... " >&6; } +if test "${ac_cv_path_GREP+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test -z "$GREP"; then + ac_path_GREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in grep ggrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue +# Check for GNU ac_path_GREP and select it if it is found. + # Check for GNU $ac_path_GREP +case `"$ac_path_GREP" --version 2>&1` in +*GNU*) + ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'GREP' >> "conftest.nl" + "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + ac_count=`expr $ac_count + 1` + if test $ac_count -gt ${ac_path_GREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_GREP="$ac_path_GREP" + ac_path_GREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_GREP_found && break 3 + done + done +done +IFS=$as_save_IFS + if test -z "$ac_cv_path_GREP"; then + { { $as_echo "$as_me:$LINENO: error: no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 +$as_echo "$as_me: error: no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} + { (exit 1); exit 1; }; } + fi +else + ac_cv_path_GREP=$GREP +fi + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_path_GREP" >&5 +$as_echo "$ac_cv_path_GREP" >&6; } + GREP="$ac_cv_path_GREP" + + +{ $as_echo "$as_me:$LINENO: checking for egrep" >&5 +$as_echo_n "checking for egrep... " >&6; } +if test "${ac_cv_path_EGREP+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 + then ac_cv_path_EGREP="$GREP -E" + else + if test -z "$EGREP"; then + ac_path_EGREP_found=false + # Loop through the user's path and test for each of PROGNAME-LIST + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_prog in egrep; do + for ac_exec_ext in '' $ac_executable_extensions; do + ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" + { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue +# Check for GNU ac_path_EGREP and select it if it is found. + # Check for GNU $ac_path_EGREP +case `"$ac_path_EGREP" --version 2>&1` in +*GNU*) + ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; +*) + ac_count=0 + $as_echo_n 0123456789 >"conftest.in" + while : + do + cat "conftest.in" "conftest.in" >"conftest.tmp" + mv "conftest.tmp" "conftest.in" + cp "conftest.in" "conftest.nl" + $as_echo 'EGREP' >> "conftest.nl" + "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break + diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break + ac_count=`expr $ac_count + 1` + if test $ac_count -gt ${ac_path_EGREP_max-0}; then + # Best one so far, save it but keep looking for a better one + ac_cv_path_EGREP="$ac_path_EGREP" + ac_path_EGREP_max=$ac_count + fi + # 10*(2^10) chars as input seems more than enough + test $ac_count -gt 10 && break + done + rm -f conftest.in conftest.tmp conftest.nl conftest.out;; +esac + + $ac_path_EGREP_found && break 3 + done + done +done +IFS=$as_save_IFS + if test -z "$ac_cv_path_EGREP"; then + { { $as_echo "$as_me:$LINENO: error: no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 +$as_echo "$as_me: error: no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} + { (exit 1); exit 1; }; } + fi +else + ac_cv_path_EGREP=$EGREP +fi + + fi +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_path_EGREP" >&5 +$as_echo "$ac_cv_path_EGREP" >&6; } + EGREP="$ac_cv_path_EGREP" + + +{ $as_echo "$as_me:$LINENO: checking for ANSI C header files" >&5 +$as_echo_n "checking for ANSI C header files... " >&6; } +if test "${ac_cv_header_stdc+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include +#include +#include + +int +main () +{ + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_header_stdc=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_header_stdc=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext + +if test $ac_cv_header_stdc = yes; then + # SunOS 4.x string.h does not declare mem*, contrary to ANSI. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "memchr" >/dev/null 2>&1; then + : +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include + +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "free" >/dev/null 2>&1; then + : +else + ac_cv_header_stdc=no +fi +rm -f conftest* + +fi + +if test $ac_cv_header_stdc = yes; then + # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. + if test "$cross_compiling" = yes; then + : +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include +#if ((' ' & 0x0FF) == 0x020) +# define ISLOWER(c) ('a' <= (c) && (c) <= 'z') +# define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) +#else +# define ISLOWER(c) \ + (('a' <= (c) && (c) <= 'i') \ + || ('j' <= (c) && (c) <= 'r') \ + || ('s' <= (c) && (c) <= 'z')) +# define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) +#endif + +#define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) +int +main () +{ + int i; + for (i = 0; i < 256; i++) + if (XOR (islower (i), ISLOWER (i)) + || toupper (i) != TOUPPER (i)) + return 2; + return 0; +} +_ACEOF +rm -f conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { ac_try='./conftest$ac_exeext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + : +else + $as_echo "$as_me: program exited with status $ac_status" >&5 +$as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +( exit $ac_status ) +ac_cv_header_stdc=no +fi +rm -rf conftest.dSYM +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +fi + + +fi +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5 +$as_echo "$ac_cv_header_stdc" >&6; } +if test $ac_cv_header_stdc = yes; then + +cat >>confdefs.h <<\_ACEOF +#define STDC_HEADERS 1 +_ACEOF + +fi + + + + +# add -lucb to LIBS and -L/usr/ucblib to LIBDIRS +# if there's a libucb.a available +# (Solaris needs this for signals) + +ac_save_ldflags="$LDFLAGS" +LDFLAGS=-L/usr/ucblib +{ $as_echo "$as_me:$LINENO: checking for main in -lucb" >&5 +$as_echo_n "checking for main in -lucb... " >&6; } +if test "${ac_cv_lib_ucb_main+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lucb $LIBS" +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + + +int +main () +{ +return main (); + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_ucb_main=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_lib_ucb_main=no +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_ucb_main" >&5 +$as_echo "$ac_cv_lib_ucb_main" >&6; } +if test "x$ac_cv_lib_ucb_main" = x""yes; then + LIBDIRS="$LIBDIRS -L/usr/ucblib" +fi + +LDFLAGS="$ac_save_ldflags" + +# add -lbsd if there's a libbsd.a available +# (e.g., Linux needs this for bsd_ioctl) + +{ $as_echo "$as_me:$LINENO: checking for main in -lbsd" >&5 +$as_echo_n "checking for main in -lbsd... " >&6; } +if test "${ac_cv_lib_bsd_main+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lbsd $LIBS" +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + + +int +main () +{ +return main (); + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_bsd_main=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_lib_bsd_main=no +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_bsd_main" >&5 +$as_echo "$ac_cv_lib_bsd_main" >&6; } +if test "x$ac_cv_lib_bsd_main" = x""yes; then + cat >>confdefs.h <<_ACEOF +#define HAVE_LIBBSD 1 +_ACEOF + + LIBS="-lbsd $LIBS" + +fi + + +# Check if libreadline exists and the function readline can be used. +# This implies checking for the availability of libtermcap or of a +# suitable replacement. (We only look for libncurses.) +if test "${vis_cv_termcap_lib+set}" = set; then + $as_echo_n "(cached) " >&6 +else + { $as_echo "$as_me:$LINENO: checking for tgetent in -ltermcap" >&5 +$as_echo_n "checking for tgetent in -ltermcap... " >&6; } +if test "${ac_cv_lib_termcap_tgetent+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-ltermcap $LIBS" +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char tgetent (); +int +main () +{ +return tgetent (); + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_termcap_tgetent=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_lib_termcap_tgetent=no +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_termcap_tgetent" >&5 +$as_echo "$ac_cv_lib_termcap_tgetent" >&6; } +if test "x$ac_cv_lib_termcap_tgetent" = x""yes; then + vis_cv_termcap_lib=-ltermcap +else + { $as_echo "$as_me:$LINENO: checking for tgetent in -lncurses" >&5 +$as_echo_n "checking for tgetent in -lncurses... " >&6; } +if test "${ac_cv_lib_ncurses_tgetent+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lncurses $LIBS" +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char tgetent (); +int +main () +{ +return tgetent (); + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_ncurses_tgetent=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_lib_ncurses_tgetent=no +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_ncurses_tgetent" >&5 +$as_echo "$ac_cv_lib_ncurses_tgetent" >&6; } +if test "x$ac_cv_lib_ncurses_tgetent" = x""yes; then + vis_cv_termcap_lib=-lncurses +else + bash_cv_termcap_lib=none +fi + +fi + +fi + +if test "$vis_cv_termcap_lib" != none; then + { $as_echo "$as_me:$LINENO: checking for readline in -lreadline" >&5 +$as_echo_n "checking for readline in -lreadline... " >&6; } +if test "${ac_cv_lib_readline_readline+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_check_lib_save_LIBS=$LIBS +LIBS="-lreadline $vis_cv_termcap_lib $LIBS" +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char readline (); +int +main () +{ +return readline (); + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_lib_readline_readline=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_lib_readline_readline=no +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext conftest.$ac_ext +LIBS=$ac_check_lib_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_lib_readline_readline" >&5 +$as_echo "$ac_cv_lib_readline_readline" >&6; } +if test "x$ac_cv_lib_readline_readline" = x""yes; then + ac_readline_flag=1 +else + ac_readline_flag=0 +fi + + if test $ac_readline_flag = 1 ; then + LIBS="$LIBS -lreadline $vis_cv_termcap_lib" ; cat >>confdefs.h <<\_ACEOF +#define HAVE_LIBREADLINE 1 +_ACEOF + + fi +fi + +# Check for the dirent header file, which is quite a mess + + + + + +ac_header_dirent=no +for ac_hdr in dirent.h sys/ndir.h sys/dir.h ndir.h; do + as_ac_Header=`$as_echo "ac_cv_header_dirent_$ac_hdr" | $as_tr_sh` +{ $as_echo "$as_me:$LINENO: checking for $ac_hdr that defines DIR" >&5 +$as_echo_n "checking for $ac_hdr that defines DIR... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include <$ac_hdr> + +int +main () +{ +if ((DIR *) 0) +return 0; + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + eval "$as_ac_Header=yes" +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + eval "$as_ac_Header=no" +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +as_val=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + if test "x$as_val" = x""yes; then + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_hdr" | $as_tr_cpp` 1 +_ACEOF + +ac_header_dirent=$ac_hdr; break +fi + +done +# Two versions of opendir et al. are in -ldir and -lx on SCO Xenix. +if test $ac_header_dirent = dirent.h; then + { $as_echo "$as_me:$LINENO: checking for library containing opendir" >&5 +$as_echo_n "checking for library containing opendir... " >&6; } +if test "${ac_cv_search_opendir+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char opendir (); +int +main () +{ +return opendir (); + ; + return 0; +} +_ACEOF +for ac_lib in '' dir; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_search_opendir=$ac_res +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext + if test "${ac_cv_search_opendir+set}" = set; then + break +fi +done +if test "${ac_cv_search_opendir+set}" = set; then + : +else + ac_cv_search_opendir=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_search_opendir" >&5 +$as_echo "$ac_cv_search_opendir" >&6; } +ac_res=$ac_cv_search_opendir +if test "$ac_res" != no; then + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + +fi + +else + { $as_echo "$as_me:$LINENO: checking for library containing opendir" >&5 +$as_echo_n "checking for library containing opendir... " >&6; } +if test "${ac_cv_search_opendir+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_func_search_save_LIBS=$LIBS +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char opendir (); +int +main () +{ +return opendir (); + ; + return 0; +} +_ACEOF +for ac_lib in '' x; do + if test -z "$ac_lib"; then + ac_res="none required" + else + ac_res=-l$ac_lib + LIBS="-l$ac_lib $ac_func_search_save_LIBS" + fi + rm -f conftest.$ac_objext conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest$ac_exeext && { + test "$cross_compiling" = yes || + $as_test_x conftest$ac_exeext + }; then + ac_cv_search_opendir=$ac_res +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + +fi + +rm -rf conftest.dSYM +rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ + conftest$ac_exeext + if test "${ac_cv_search_opendir+set}" = set; then + break +fi +done +if test "${ac_cv_search_opendir+set}" = set; then + : +else + ac_cv_search_opendir=no +fi +rm conftest.$ac_ext +LIBS=$ac_func_search_save_LIBS +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_search_opendir" >&5 +$as_echo "$ac_cv_search_opendir" >&6; } +ac_res=$ac_cv_search_opendir +if test "$ac_res" != no; then + test "$ac_res" = "none required" || LIBS="$ac_res $LIBS" + +fi + +fi + + +# Check for these system header files +# On IRIX 5.3, sys/types and inttypes.h are conflicting. + + + + + + + + + +for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ + inttypes.h stdint.h unistd.h +do +as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 +$as_echo_n "checking for $ac_header... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +$ac_includes_default + +#include <$ac_header> +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + eval "$as_ac_Header=yes" +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + eval "$as_ac_Header=no" +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +as_val=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + if test "x$as_val" = x""yes; then + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + + + + + + + + +for ac_header in sys/termios.h sys/ioctl.h sys/time.h signal.h sys/signal.h readline/readline.h readline/history.h +do +as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + { $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 +$as_echo_n "checking for $ac_header... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +else + # Is the header compilable? +{ $as_echo "$as_me:$LINENO: checking $ac_header usability" >&5 +$as_echo_n "checking $ac_header usability... " >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +$ac_includes_default +#include <$ac_header> +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_header_compiler=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_compiler=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +{ $as_echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 +$as_echo "$ac_header_compiler" >&6; } + +# Is the header present? +{ $as_echo "$as_me:$LINENO: checking $ac_header presence" >&5 +$as_echo_n "checking $ac_header presence... " >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include <$ac_header> +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + ac_header_preproc=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_preproc=no +fi + +rm -f conftest.err conftest.$ac_ext +{ $as_echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 +$as_echo "$ac_header_preproc" >&6; } + +# So? What about this header? +case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in + yes:no: ) + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 +$as_echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 +$as_echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} + ac_header_preproc=yes + ;; + no:yes:* ) + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 +$as_echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 +$as_echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 +$as_echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 +$as_echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 +$as_echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 +$as_echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} + + ;; +esac +{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 +$as_echo_n "checking for $ac_header... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +else + eval "$as_ac_Header=\$ac_header_preproc" +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + +fi +as_val=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + if test "x$as_val" = x""yes; then + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +# This is for Linux + +for ac_header in bsd/sgtty.h +do +as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + { $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 +$as_echo_n "checking for $ac_header... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } +else + # Is the header compilable? +{ $as_echo "$as_me:$LINENO: checking $ac_header usability" >&5 +$as_echo_n "checking $ac_header usability... " >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +$ac_includes_default +#include <$ac_header> +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_header_compiler=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_compiler=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +{ $as_echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 +$as_echo "$ac_header_compiler" >&6; } + +# Is the header present? +{ $as_echo "$as_me:$LINENO: checking $ac_header presence" >&5 +$as_echo_n "checking $ac_header presence... " >&6; } +cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include <$ac_header> +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + ac_header_preproc=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_header_preproc=no +fi + +rm -f conftest.err conftest.$ac_ext +{ $as_echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 +$as_echo "$ac_header_preproc" >&6; } + +# So? What about this header? +case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in + yes:no: ) + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 +$as_echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 +$as_echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} + ac_header_preproc=yes + ;; + no:yes:* ) + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 +$as_echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 +$as_echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 +$as_echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 +$as_echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 +$as_echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} + { $as_echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 +$as_echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} + + ;; +esac +{ $as_echo "$as_me:$LINENO: checking for $ac_header" >&5 +$as_echo_n "checking for $ac_header... " >&6; } +if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +else + eval "$as_ac_Header=\$ac_header_preproc" +fi +ac_res=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + { $as_echo "$as_me:$LINENO: result: $ac_res" >&5 +$as_echo "$ac_res" >&6; } + +fi +as_val=`eval 'as_val=${'$as_ac_Header'} + $as_echo "$as_val"'` + if test "x$as_val" = x""yes; then + cat >>confdefs.h <<_ACEOF +#define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 +_ACEOF + +fi + +done + + +# Some systems want both sys/ioctl.h and sys/termios.h, but others can +# only have one -- check for that + +{ $as_echo "$as_me:$LINENO: checking whether sys/termios.h and sys/ioctl.h should both be included" >&5 +$as_echo_n "checking whether sys/termios.h and sys/ioctl.h should both be included... " >&6; } + +if test "${ac_cv_ioctl_with_termios+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +#include +#include + +_ACEOF +if { (ac_try="$ac_cpp conftest.$ac_ext" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } >/dev/null && { + test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || + test ! -s conftest.err + }; then + ac_cv_ioctl_with_termios=1 +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_ioctl_with_termios=0 +fi + +rm -f conftest.err conftest.$ac_ext +fi + +if test $ac_cv_ioctl_with_termios = 1 ; then + { $as_echo "$as_me:$LINENO: result: yes" >&5 +$as_echo "yes" >&6; } ; cat >>confdefs.h <<\_ACEOF +#define IOCTL_WITH_TERMIOS 1 +_ACEOF + +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + +# cmdFile.c wants to be able to use TIOCGETC to do file completion, +# but some systems (e.g., HPUX) don't have this +# + +{ $as_echo "$as_me:$LINENO: checking for TIOCGETC" >&5 +$as_echo_n "checking for TIOCGETC... " >&6; } + +if test "${ac_cv_have_ioctl_with_tiocgetc+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test $ac_cv_ioctl_with_termios = 1 ; then + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include +#ifdef TIOCGETC + yes +#endif +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "yes" >/dev/null 2>&1; then + ac_cv_have_ioctl_with_tiocgetc=yes +else + ac_cv_have_ioctl_with_tiocgetc=no +fi +rm -f conftest* + +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#ifdef TIOCGETC + yes +#endif +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "yes" >/dev/null 2>&1; then + ac_cv_have_ioctl_with_tiocgetc=yes +else + ac_cv_have_ioctl_with_tiocgetc=no +fi +rm -f conftest* + +fi +fi + +if test $ac_cv_have_ioctl_with_tiocgetc = "yes" ; then + { $as_echo "$as_me:$LINENO: result: yes" >&5 +$as_echo "yes" >&6; } ; cat >>confdefs.h <<\_ACEOF +#define HAVE_IOCTL_WITH_TIOCGETC 1 +_ACEOF + +else + { $as_echo "$as_me:$LINENO: result: no" >&5 +$as_echo "no" >&6; } +fi + +# # cmdFile.c wants to turn off interrupts, but some systems don't +# # seem to know how to do that using TIOCLBIS +# # +# # This is probably fairly fragile, and it's probably cmdFile.c that should +# # be fixed +# # +# # This has been very unreliable (e.g., on Solaris), so the facility has +# # been turned off +# +# if test $ac_cv_have_ioctl_with_tiocgetc = "yes" ; then +# +# AC_MSG_CHECKING(for TIOCLBIS) +# +# AC_CACHE_VAL(ac_cv_have_term_interrupts, +# [AC_EGREP_CPP(yes, +# [#include +# #include +# #ifdef TIOCLBIS +# yes +# #endif +# ], ac_cv_have_term_interrupts=1, +# ac_cv_have_term_interrupts=0 )]) +# +# if test $ac_cv_have_term_interrupts = 1 ; then +# AC_MSG_RESULT(yes) ; AC_DEFINE(HAVE_TERM_INTERRUPTS) +# else +# AC_MSG_RESULT(no) +# fi +# +# fi # ac_cv_have_ioctl_with_tiocgetc + +#---------------------------------------------------------------------- +# Checks for typedefs, structures, and compiler characteristics. +#---------------------------------------------------------------------- + +# Check to see if the compiler understands "const" +# #define it empty otherwise +{ $as_echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5 +$as_echo_n "checking for an ANSI C-conforming const... " >&6; } +if test "${ac_cv_c_const+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ + +int +main () +{ +/* FIXME: Include the comments suggested by Paul. */ +#ifndef __cplusplus + /* Ultrix mips cc rejects this. */ + typedef int charset[2]; + const charset cs; + /* SunOS 4.1.1 cc rejects this. */ + char const *const *pcpcc; + char **ppc; + /* NEC SVR4.0.2 mips cc rejects this. */ + struct point {int x, y;}; + static struct point const zero = {0,0}; + /* AIX XL C 1.02.0.0 rejects this. + It does not let you subtract one const X* pointer from another in + an arm of an if-expression whose if-part is not a constant + expression */ + const char *g = "string"; + pcpcc = &g + (g ? g-g : 0); + /* HPUX 7.0 cc rejects these. */ + ++pcpcc; + ppc = (char**) pcpcc; + pcpcc = (char const *const *) ppc; + { /* SCO 3.2v4 cc rejects this. */ + char *t; + char const *s = 0 ? (char *) 0 : (char const *) 0; + + *t++ = 0; + if (s) return 0; + } + { /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */ + int x[] = {25, 17}; + const int *foo = &x[0]; + ++foo; + } + { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */ + typedef const int *iptr; + iptr p = 0; + ++p; + } + { /* AIX XL C 1.02.0.0 rejects this saying + "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */ + struct s { int j; const int *ap[3]; }; + struct s *b; b->j = 5; + } + { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ + const int foo = 10; + if (!foo) return 0; + } + return !cs[0] && !zero.x; +#endif + + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_c_const=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_c_const=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5 +$as_echo "$ac_cv_c_const" >&6; } +if test $ac_cv_c_const = no; then + +cat >>confdefs.h <<\_ACEOF +#define const /**/ +_ACEOF + +fi + + +# Sort out "time.h" nonsense +{ $as_echo "$as_me:$LINENO: checking whether time.h and sys/time.h may both be included" >&5 +$as_echo_n "checking whether time.h and sys/time.h may both be included... " >&6; } +if test "${ac_cv_header_time+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include +#include + +int +main () +{ +if ((struct tm *) 0) +return 0; + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_header_time=yes +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_header_time=no +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_header_time" >&5 +$as_echo "$ac_cv_header_time" >&6; } +if test $ac_cv_header_time = yes; then + +cat >>confdefs.h <<\_ACEOF +#define TIME_WITH_SYS_TIME 1 +_ACEOF + +fi + + +{ $as_echo "$as_me:$LINENO: checking whether struct tm is in sys/time.h or time.h" >&5 +$as_echo_n "checking whether struct tm is in sys/time.h or time.h... " >&6; } +if test "${ac_cv_struct_tm+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include + +int +main () +{ +struct tm tm; + int *p = &tm.tm_sec; + return !p; + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_struct_tm=time.h +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_struct_tm=sys/time.h +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_struct_tm" >&5 +$as_echo "$ac_cv_struct_tm" >&6; } +if test $ac_cv_struct_tm = sys/time.h; then + +cat >>confdefs.h <<\_ACEOF +#define TM_IN_SYS_TIME 1 +_ACEOF + +fi + + +# Set RETSIGTYPE to the proper return type for a signal handler (void or int) +{ $as_echo "$as_me:$LINENO: checking return type of signal handlers" >&5 +$as_echo_n "checking return type of signal handlers... " >&6; } +if test "${ac_cv_type_signal+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include + +int +main () +{ +return *(signal (0, 0)) (0) == 1; + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_type_signal=int +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_type_signal=void +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_type_signal" >&5 +$as_echo "$ac_cv_type_signal" >&6; } + +cat >>confdefs.h <<_ACEOF +#define RETSIGTYPE $ac_cv_type_signal +_ACEOF + + + +# Roderick Bloem (rbloem@colorado.edu) : On Irix we need ttold +case "$target" in + mips-sgi-irix*) + cat >>confdefs.h <<\_ACEOF +#define NEED_TTOLD 1 +_ACEOF +;; +esac + +#---------------------------------------------------------------------- +# Checks for library functions. +#---------------------------------------------------------------------- + +if test $ac_cv_c_compiler_gnu = yes; then + { $as_echo "$as_me:$LINENO: checking whether $CC needs -traditional" >&5 +$as_echo_n "checking whether $CC needs -traditional... " >&6; } +if test "${ac_cv_prog_gcc_traditional+set}" = set; then + $as_echo_n "(cached) " >&6 +else + ac_pattern="Autoconf.*'x'" + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +Autoconf TIOCGETP +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "$ac_pattern" >/dev/null 2>&1; then + ac_cv_prog_gcc_traditional=yes +else + ac_cv_prog_gcc_traditional=no +fi +rm -f conftest* + + + if test $ac_cv_prog_gcc_traditional = no; then + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +Autoconf TCGETA +_ACEOF +if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | + $EGREP "$ac_pattern" >/dev/null 2>&1; then + ac_cv_prog_gcc_traditional=yes +fi +rm -f conftest* + + fi +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_prog_gcc_traditional" >&5 +$as_echo "$ac_cv_prog_gcc_traditional" >&6; } + if test $ac_cv_prog_gcc_traditional = yes; then + CC="$CC -traditional" + fi +fi + +{ $as_echo "$as_me:$LINENO: checking for working memcmp" >&5 +$as_echo_n "checking for working memcmp... " >&6; } +if test "${ac_cv_func_memcmp_working+set}" = set; then + $as_echo_n "(cached) " >&6 +else + if test "$cross_compiling" = yes; then + ac_cv_func_memcmp_working=no +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +$ac_includes_default +int +main () +{ + + /* Some versions of memcmp are not 8-bit clean. */ + char c0 = '\100', c1 = '\200', c2 = '\201'; + if (memcmp(&c0, &c2, 1) >= 0 || memcmp(&c1, &c2, 1) >= 0) + return 1; + + /* The Next x86 OpenStep bug shows up only when comparing 16 bytes + or more and with at least one buffer not starting on a 4-byte boundary. + William Lewis provided this test program. */ + { + char foo[21]; + char bar[21]; + int i; + for (i = 0; i < 4; i++) + { + char *a = foo + i; + char *b = bar + i; + strcpy (a, "--------01111111"); + strcpy (b, "--------10000000"); + if (memcmp (a, b, 16) >= 0) + return 1; + } + return 0; + } + + ; + return 0; +} +_ACEOF +rm -f conftest$ac_exeext +if { (ac_try="$ac_link" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_link") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { ac_try='./conftest$ac_exeext' + { (case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_try") 2>&5 + ac_status=$? + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); }; }; then + ac_cv_func_memcmp_working=yes +else + $as_echo "$as_me: program exited with status $ac_status" >&5 +$as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + +( exit $ac_status ) +ac_cv_func_memcmp_working=no +fi +rm -rf conftest.dSYM +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext +fi + + +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_func_memcmp_working" >&5 +$as_echo "$ac_cv_func_memcmp_working" >&6; } +test $ac_cv_func_memcmp_working = no && case " $LIBOBJS " in + *" memcmp.$ac_objext "* ) ;; + *) LIBOBJS="$LIBOBJS memcmp.$ac_objext" + ;; +esac + + +{ $as_echo "$as_me:$LINENO: checking return type of signal handlers" >&5 +$as_echo_n "checking return type of signal handlers... " >&6; } +if test "${ac_cv_type_signal+set}" = set; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +#include +#include + +int +main () +{ +return *(signal (0, 0)) (0) == 1; + ; + return 0; +} +_ACEOF +rm -f conftest.$ac_objext +if { (ac_try="$ac_compile" +case "(($ac_try" in + *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; + *) ac_try_echo=$ac_try;; +esac +eval ac_try_echo="\"\$as_me:$LINENO: $ac_try_echo\"" +$as_echo "$ac_try_echo") >&5 + (eval "$ac_compile") 2>conftest.er1 + ac_status=$? + grep -v '^ *+' conftest.er1 >conftest.err + rm -f conftest.er1 + cat conftest.err >&5 + $as_echo "$as_me:$LINENO: \$? = $ac_status" >&5 + (exit $ac_status); } && { + test -z "$ac_c_werror_flag" || + test ! -s conftest.err + } && test -s conftest.$ac_objext; then + ac_cv_type_signal=int +else + $as_echo "$as_me: failed program was:" >&5 +sed 's/^/| /' conftest.$ac_ext >&5 + + ac_cv_type_signal=void +fi + +rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext +fi +{ $as_echo "$as_me:$LINENO: result: $ac_cv_type_signal" >&5 +$as_echo "$ac_cv_type_signal" >&6; } + +cat >>confdefs.h <<_ACEOF +#define RETSIGTYPE $ac_cv_type_signal +_ACEOF + + + + + + + + + + +for ac_func in gettimeofday strchr strstr setvbuf getenv unlink mkstemp close +do +as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` +{ $as_echo "$as_me:$LINENO: checking for $ac_func" >&5 +$as_echo_n "checking for $ac_func... " >&6; } +if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then + $as_echo_n "(cached) " >&6 +else + cat >conftest.$ac_ext <<_ACEOF +/* confdefs.h. */ +_ACEOF +cat confdefs.h >>conftest.$ac_ext +cat >>conftest.$ac_ext <<_ACEOF +/* end confdefs.h. */ +/* Define $ac_func to an innocuous variant, in case declares $ac_func. + For example, HP-UX 11i declares gettimeofday. */ +#define $ac_func innocuous_$ac_func + +/* System header to define __stub macros and hopefully few prototypes, + which can conflict with char $ac_func (); below. + Prefer to if __STDC__ is defined, since + exists even on freestanding compilers. */ + +#ifdef __STDC__ +# include +#else +# include +#endif + +#undef $ac_func + +/* Override any GCC internal prototype to avoid an error. + Use char because int might match the return type of a GCC + builtin and then its argument prototype would still apply. */ +#ifdef __cplusplus +extern "C" +#endif +char $ac_func (); +/* The GNU C library defines this for functions which it implements + to always fail with ENOSYS. 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Please make sure it is defined." >&2;} + + rm -f "$tmp/stdin" + case $ac_file in + -) cat "$tmp/out" && rm -f "$tmp/out";; + *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";; + esac \ + || { { $as_echo "$as_me:$LINENO: error: could not create $ac_file" >&5 +$as_echo "$as_me: error: could not create $ac_file" >&2;} + { (exit 1); exit 1; }; } + ;; + + + + esac + +done # for ac_tag + + +{ (exit 0); exit 0; } +_ACEOF +chmod +x $CONFIG_STATUS +ac_clean_files=$ac_clean_files_save + +test $ac_write_fail = 0 || + { { $as_echo "$as_me:$LINENO: error: write failure creating $CONFIG_STATUS" >&5 +$as_echo "$as_me: error: write failure creating $CONFIG_STATUS" >&2;} + { (exit 1); exit 1; }; } + + +# configure is writing to config.log, and then calls config.status. +# config.status does its own redirection, appending to config.log. +# Unfortunately, on DOS this fails, as config.log is still kept open +# by configure, so config.status won't be able to write to it; its +# output is simply discarded. So we exec the FD to /dev/null, +# effectively closing config.log, so it can be properly (re)opened and +# appended to by config.status. When coming back to configure, we +# need to make the FD available again. +if test "$no_create" != yes; then + ac_cs_success=: + ac_config_status_args= + test "$silent" = yes && + ac_config_status_args="$ac_config_status_args --quiet" + exec 5>/dev/null + $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false + exec 5>>config.log + # Use ||, not &&, to avoid exiting from the if with $? = 1, which + # would make configure fail if this is the last instruction. + $ac_cs_success || { (exit 1); exit 1; } +fi +if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then + { $as_echo "$as_me:$LINENO: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 +$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} +fi + Index: vis_dev/vis-2.1/configure.in =================================================================== --- vis_dev/vis-2.1/configure.in (revision 11) +++ vis_dev/vis-2.1/configure.in (revision 11) @@ -0,0 +1,549 @@ +dnl Run autoconf on this file to produce the system configuration +dnl script "configure" + +# FileName [ configure.in ] +# +# PackageName [ vis ] +# +# Synopsis [ System configuration script for autoconf ] +# +# SeeAlso [ Makefile.in ] +# +# Author [ Stephen Edwards ] +# +# Copyright [ +# Copyright (c) 1994-1996 The Regents of the Univ. of California. +# All rights reserved. +# +# Permission is hereby granted, without written agreement and without license +# or royalty fees, to use, copy, modify, and distribute this software and its +# documentation for any purpose, provided that the above copyright notice and +# the following two paragraphs appear in all copies of this software. +# +# IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR +# DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT +# OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF +# CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, +# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND +# FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN +# "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO PROVIDE +# MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. +# ] +# +# Revision [$Id: configure.in,v 1.62 2004/08/20 18:31:32 fabio Exp $] + +# Require autoconf version 2.11 or above -- it checks to see if the C +# compiler actually works! + +AC_PREREQ(2.11) + +AC_INIT(src/cmd/cmd.h) + +# Look for install.sh, config.guess, and config.sub in the "helpers" dir +AC_CONFIG_AUX_DIR(helpers) + +#---------------------------------------------------------------------- + +# Configuration options +#---------------------------------------------------------------------- + +# Give the configurer a chance to set the location of the GLU tree + +AC_SUBST(glulibdir) +AC_ARG_WITH(glu-libdir, +[ --with-glu-libdir= Specify directories to search for the GLU library. + Expects to find /libglu.a], +[glulibdir=$withval], [glulibdir=""]) + +AC_SUBST(gluincdir) +AC_ARG_WITH(glu-incdir, +[ --with-glu-incdir= Specify directories to search for the GLU headers], +[gluincdir=$withval], [gluincdir=""]) + +# Give the configurer a chance to set a different location for the VIS +# headers and library + +AC_SUBST(vislibdir) +AC_ARG_WITH(vis-libdir, +[ --with-vis-libdir= Specify directories to search for the VIS + and headers. Defaults to \".\". + Expects to find /libvis.a], +[vislibdir=$withval], +[vislibdir="."]) + +# Give the configurer a chance to set a different location for the VIS +# source. When specified, "srcdir" points to "master" source, and +# "local_srcdir" points to the source under local development. + +AC_SUBST(local_srcdir) +AC_ARG_WITH(local-srcdir, +[ --with-local-srcdir= Specify the root directory to search for + source for packages (the PKGS list). + Expects to find, e.g., /tbl/tbl.c], +[local_srcdir=$withval], +[local_srcdir=$srcdir]) + +# Give the configurer a chance to set the BDD library + +AC_SUBST(BDDLIB) +AC_ARG_WITH(bdd, +[ --with-bdd= Specify the BDD library to link against. + Defaults to --with-bdd=cu.], +[BDDLIB=$withval], +[BDDLIB=cu]) + +#---------------------------------------------------------------------- +# Checks for programs we need +#---------------------------------------------------------------------- +AC_PATH_PROG(ZCHAFF,zchaff) +AC_PATH_PROG(SHARPSAT,sharpSAT) +AC_PATH_PROG(AR, ar, ar) +AC_PROG_RANLIB + +AC_CANONICAL_SYSTEM +AC_SUBST(target) + +# Determine the name of the C compiler we're going to use + +AC_ARG_ENABLE(gcc, + [ --enable-gcc Allow use of gcc if available], + [gcc_ok=$enableval], [gcc_ok=no]) + +# We cannot set CC=g++ directly because many configuration test programs +# do not compile with g++. Hence, when the user specifies --enable-gcc=g++, +# we set CC=gcc during configuration, and then CC=g++ at the end. +# The same applies to icpc and icc. +if test "$gcc_ok" != no; then + case "$gcc_ok" in + yes | g++) + CC=gcc ;; + icpc) + CC=icc ;; + *) + CC=$gcc_ok + esac +else + if test -z "$CC" ; then + # Balakrishna Kumthekar + # As we do not support cc on RS6000, Cygwin and SunOS. + case "$target" in + rs6000-ibm-aix* | *-pc-cygwin32 | sparc-sun-sunos*) + CC=gcc ;; + *) + CC=cc ;; + esac + fi +fi +AC_PROG_CC + +AC_ARG_ENABLE(64, + [ --enable-64 Use 64-bit pointers on 64-bit Alpha machines], + [use_sixty_four=$enableval], [use_sixty_four=no]) + +# Gcc does not support 32-bit pointers on the Alphas. +if test "$gcc_ok" != no; then + use_sixty_four=yes +fi + + +# Roderick Bloem (rbloem@colorado.edu): making a special case for +# ultrix install, since it's annoying about setting groupids. +case "$target" in + mips-dec-ultrix*) + INSTALL="helpers/install-sh -c" + INSTALL_PROGRAM="\${INSTALL}" + INSTALL_DATA="\${INSTALL} -m 644";; + + *) + AC_PROG_INSTALL ;; +esac + +# Determine the compiler flags to use + +DEBUG_CFLAGS="-g" +DEBUG_LDFLAGS="" + +case "$target" in + + i686-pc-linux-gnu) + # Linux with Intel compiler + # -ansi: ANSI C conformance + # -ip: inter-procedural optimization + OPTIMIZE_CFLAGS="-g -O3 -ansi -ip" + ;; + + sparc-sun-solaris* | i386-pc-solaris*) + # Sparc and X86 Solaris: + # -xO3: Highest safe level of optimization + # -native: Optimize for the native processor (if supported) + # -dalign: Generate double-word load/store for performance + # (only for SPARC) + # and other arcane compilation flags. + if test "$GCC" = yes; then + OPTIMIZE_CFLAGS="-O" + else + case "$target" in + sparc-sun-solaris*) + ALIGN=" -dalign" ;; + *) + ALIGN="" ;; + esac + AC_MSG_CHECKING([for -native]) + CFLAGS="-xO3 -native$ALIGN" + AC_CACHE_VAL(ac_cv_have_native, + [ AC_TRY_RUN([ + main(){exit(0);} + ],ac_cv_have_native=yes,ac_cv_have_native=no,ac_cv_have_native=no)]) + if test $ac_cv_have_native = yes ; then + AC_MSG_RESULT(working) + OPTIMIZE_CFLAGS="-xO3 -native$ALIGN" + else + AC_MSG_RESULT(broken) + AC_MSG_CHECKING([for fallback optimization flags]) + CFLAGS="-xO3 -fns -fsimple=2$ALIGN -ftrap=%none -xlibmil" + AC_CACHE_VAL(ac_cv_have_fallback, + [ AC_TRY_RUN([ + main(){exit(0);} + ],ac_cv_have_fallback=yes,ac_cv_have_fallback=no,ac_cv_have_fallback=no)]) + if test $ac_cv_have_fallback = yes ; then + AC_MSG_RESULT(working) + OPTIMIZE_CFLAGS="-xO3 -fns -fsimple=2$ALIGN -ftrap=%none -xlibmil" + else + AC_MSG_RESULT(broken) + OPTIMIZE_CFLAGS="-O" + fi + fi + fi + ;; + + mips-dec-ultrix*) + # MIPS-based DECstations running Ultrix: + # -std1: Produce non-ANSI code warnings, and define __STDC__ + # -O: Use the global "ucode" optimizer + # -Olimit 5000: Don't optimize routines bigger than 5000 basic blocks + OPTIMIZE_CFLAGS="-std1 -O -Olimit 5000" ;; + + alpha-dec-osf*) + # DEC Alpha running OSF: + + # 64-bit mode: + # -g3: Produce symbol table information for optimized code + # -O4: Enable every optimization + # -std: Enforce the ANSI standard with extensions, define __STDC__ + # -ieee_with_no_inexact: Disable (potentially slow) signaling + # for inexact floating-point results + # -tune host: Tune instructions for the compilation host machine + OPTIMIZE_CFLAGS="-g3 -O4 -std -ieee_with_no_inexact -tune host" + DEBUG_CFLAGS="-g -std -ieee_with_no_inexact" + + # -non_shared: Do not use shared libraries + # -om: Generate an OMAGIC file for the om optimizer + OPTIMIZE_LDFLAGS="-non_shared" + + if test "$use_sixty_four" = "no"; then + # 32-bit mode: + # -xtaso: Make the compiler respond to #pragma pointer_size directives + OPTIMIZE_CFLAGS="$OPTIMIZE_CFLAGS -xtaso" + DEBUG_CFLAGS="$DEBUG_CFLAGS -xtaso" + + # -taso: Load the executable into the lower 31-bit address space + OPTIMIZE_LDFLAGS="$OPTIMIZE_LDFLAGS -om -taso" + DEBUG_LDFLAGS="$DEBUG_LDFLAGS -taso" + + AC_DEFINE(SIZEOF_VOID_P, 4) + ac_sizeof_voidp=4 + fi + ;; + + hppa*-*-hpux*) + # HP running HPUX + # -Aa: Behave as an ANSI compiler + # -D_HPUX_SOURCE: Include "HP-specific" symbols in the header + # files (e.g., this means sys/resource.h has struct rusage) + # +Onolimit: removes resource restrictions for optimization + OPTIMIZE_CFLAGS="-O -Aa +Onolimit -D_HPUX_SOURCE" + DEBUG_CFLAGS="-g -Aa -D_HPUX_SOURCE" ;; + + *) + # Other systems: + OPTIMIZE_CFLAGS="-O" ;; + +esac + +if test "$GCC" = yes; then + case "$target" in + i686-pc-linux-gnu | i386-pc-solaris* | i386-pc-cygwin32 | i386-*-freebsd*) + AC_MSG_CHECKING([for -mcpu and -malign compiler options]) + CFLAGS="-g -O3 -mcpu=pentiumpro -malign-double" + AC_TRY_COMPILE(,,ac_have_mcpu=yes,ac_have_mcpu=no) + if test "$ac_have_mcpu" = yes; then + AC_MSG_RESULT(working) + OPTIMIZE_CFLAGS="-g -O3 -mcpu=pentiumpro -malign-double" + else + AC_MSG_RESULT(broken) + OPTIMIZE_CFLAGS="-g -O3" + fi + ;; + sparc-sun-solaris*) + AC_MSG_CHECKING([for -mtune compiler option]) + CFLAGS="-g -O3 -mtune=ultrasparc" + AC_TRY_COMPILE(,,ac_have_mtune=yes,ac_have_mtune=no) + if test "$ac_have_mtune" = yes; then + AC_MSG_RESULT(working) + OPTIMIZE_CFLAGS="-g -O3 -mtune=ultrasparc" + else + AC_MSG_RESULT(not working) + OPTIMIZE_CFLAGS="-g -O3" + fi + ;; + *) + OPTIMIZE_CFLAGS="-g -O3" + ;; + esac + OPTIMIZE_LDFLAGS="" + DEBUG_CFLAGS="-g" + DEBUG_LDFLAGS="" +fi + +AC_ARG_WITH(comp-mode, +[ --with-comp-mode= Specify a special compilation mode: + optimize (the default): Produce optimized + code, with symbol table information + if supported on the platform/compiler, + and without asserts. + debug: Produce unoptimized code with symbol table + information and asserts enabled + purify: Unoptimized code linked with purify + quantify: Optimized code without asserts + linked with quantify], +[comp_mode=$withval], +[comp_mode=optimize]) +AC_SUBST(LINKER) +AC_SUBST(PLINKER) + +LINKER="$CC" + +case "$comp_mode" in + debug) + CFLAGS="$DEBUG_CFLAGS" + LDFLAGS="$DEBUG_LDFLAGS" ;; + purify) + CFLAGS="$DEBUG_CFLAGS" + LDFLAGS="$DEBUG_LDFLAGS" + AC_DEFINE(PURIFY) + LINKER="purify -cache-dir=/tmp $CC" + PLINKER="purify -log-file=./purify.log -cachedir=/tmp $CC" ;; + quantify) + CFLAGS="$OPTIMIZE_CFLAGS" + LDFLAGS="$OPTIMIZE_LDFLAGS" + AC_DEFINE(QUANTIFY) + AC_DEFINE(NDEBUG) + LINKER="quantify $CC" ;; + optimize | *) + CFLAGS="$OPTIMIZE_CFLAGS" + LDFLAGS="$OPTIMIZE_LDFLAGS" + AC_DEFINE(NDEBUG) ;; +esac + +AC_PROG_LEX +AC_MSG_CHECKING(if $LEX accepts the -o and -P options) + +AC_CACHE_VAL(ac_cv_flex_accepts_op, +[ ac_cv_flex_accepts_op=yes ; +echo "%%\ +%%" | $LEX -Ptest -o/dev/null >/dev/null 2>&1 || ac_cv_flex_accepts_op=no ]) +if test $ac_cv_flex_accepts_op = yes ; then + AC_MSG_RESULT(yes) +else + AC_MSG_RESULT(no) + AC_MSG_WARN([You either need a newer version of flex, or need to modify +the defintion of LEX in the Makefile to point to a version that does +accept -p -t and -o.]) +fi + +AC_PROG_YACC +AC_MSG_CHECKING([if $YACC accepts the -p, -t, and -o options]) +AC_CACHE_VAL(ac_cv_yacc_accepts_pto, +[ ac_cv_yacc_accepts_pto=yes ; +echo "%token terminal\ +%%\ +nonterminal: terminal\ +%%" > config.in +$YACC -ptest -o /dev/null config.in >/dev/null 2>&1 || ac_cv_yacc_accepts_pto=no +rm -f config.in ]) +if test $ac_cv_yacc_accepts_pto = yes ; then + AC_MSG_RESULT(yes) +else + AC_MSG_RESULT(no) + AC_MSG_WARN([You either need a newer version of bison, or need to modify +the defintion of YACC in the Makefile to point to a version that does +accept -p -t and -o.]) +fi + +#---------------------------------------------------------------------- +# Checks for headers and libraries +#---------------------------------------------------------------------- +AC_HEADER_STDC + +AC_SUBST(LIBDIRS) + +# add -lucb to LIBS and -L/usr/ucblib to LIBDIRS +# if there's a libucb.a available +# (Solaris needs this for signals) + +ac_save_ldflags="$LDFLAGS" +LDFLAGS=-L/usr/ucblib +AC_CHECK_LIB(ucb,main,LIBDIRS="$LIBDIRS -L/usr/ucblib") +LDFLAGS="$ac_save_ldflags" + +# add -lbsd if there's a libbsd.a available +# (e.g., Linux needs this for bsd_ioctl) +AC_CHECK_LIB(bsd,main) + +# Check if libreadline exists and the function readline can be used. +# This implies checking for the availability of libtermcap or of a +# suitable replacement. (We only look for libncurses.) +AC_CACHE_VAL(vis_cv_termcap_lib, +[AC_CHECK_LIB(termcap, tgetent, vis_cv_termcap_lib=-ltermcap, + [AC_CHECK_LIB(ncurses, tgetent, vis_cv_termcap_lib=-lncurses, + bash_cv_termcap_lib=none)])]) +if test "$vis_cv_termcap_lib" != none; then + AC_CHECK_LIB(readline, readline, ac_readline_flag=1, + ac_readline_flag=0, $vis_cv_termcap_lib) + if test $ac_readline_flag = 1 ; then + LIBS="$LIBS -lreadline $vis_cv_termcap_lib" ; AC_DEFINE(HAVE_LIBREADLINE) + fi +fi + +# Check for the dirent header file, which is quite a mess +AC_HEADER_DIRENT + +# Check for these system header files +AC_CHECK_HEADERS(sys/termios.h sys/ioctl.h sys/time.h signal.h sys/signal.h readline/readline.h readline/history.h) + +# This is for Linux +AC_CHECK_HEADERS(bsd/sgtty.h) + +# Some systems want both sys/ioctl.h and sys/termios.h, but others can +# only have one -- check for that + +AC_MSG_CHECKING(whether sys/termios.h and sys/ioctl.h should both be included) + +AC_CACHE_VAL(ac_cv_ioctl_with_termios, +[AC_TRY_CPP([ +#include +#include +], ac_cv_ioctl_with_termios=1, ac_cv_ioctl_with_termios=0 )]) +if test $ac_cv_ioctl_with_termios = 1 ; then + AC_MSG_RESULT(yes) ; AC_DEFINE(IOCTL_WITH_TERMIOS) +else + AC_MSG_RESULT(no) +fi + +# cmdFile.c wants to be able to use TIOCGETC to do file completion, +# but some systems (e.g., HPUX) don't have this +# + +AC_MSG_CHECKING(for TIOCGETC) + +AC_CACHE_VAL(ac_cv_have_ioctl_with_tiocgetc, +[if test $ac_cv_ioctl_with_termios = 1 ; then + AC_EGREP_CPP(yes, +[#include +#include +#ifdef TIOCGETC + yes +#endif], + ac_cv_have_ioctl_with_tiocgetc=yes, + ac_cv_have_ioctl_with_tiocgetc=no) +else + AC_EGREP_CPP(yes, +[#include +#ifdef TIOCGETC + yes +#endif], + ac_cv_have_ioctl_with_tiocgetc=yes, + ac_cv_have_ioctl_with_tiocgetc=no) +fi]) +if test $ac_cv_have_ioctl_with_tiocgetc = "yes" ; then + AC_MSG_RESULT(yes) ; AC_DEFINE(HAVE_IOCTL_WITH_TIOCGETC) +else + AC_MSG_RESULT(no) +fi + +# # cmdFile.c wants to turn off interrupts, but some systems don't +# # seem to know how to do that using TIOCLBIS +# # +# # This is probably fairly fragile, and it's probably cmdFile.c that should +# # be fixed +# # +# # This has been very unreliable (e.g., on Solaris), so the facility has +# # been turned off +# +# if test $ac_cv_have_ioctl_with_tiocgetc = "yes" ; then +# +# AC_MSG_CHECKING(for TIOCLBIS) +# +# AC_CACHE_VAL(ac_cv_have_term_interrupts, +# [AC_EGREP_CPP(yes, +# [#include +# #include +# #ifdef TIOCLBIS +# yes +# #endif +# ], ac_cv_have_term_interrupts=1, +# ac_cv_have_term_interrupts=0 )]) +# +# if test $ac_cv_have_term_interrupts = 1 ; then +# AC_MSG_RESULT(yes) ; AC_DEFINE(HAVE_TERM_INTERRUPTS) +# else +# AC_MSG_RESULT(no) +# fi +# +# fi # ac_cv_have_ioctl_with_tiocgetc + +#---------------------------------------------------------------------- +# Checks for typedefs, structures, and compiler characteristics. +#---------------------------------------------------------------------- + +# Check to see if the compiler understands "const" +# #define it empty otherwise +AC_C_CONST + +# Sort out "time.h" nonsense +AC_HEADER_TIME + +AC_STRUCT_TM + +# Set RETSIGTYPE to the proper return type for a signal handler (void or int) +AC_TYPE_SIGNAL + +# Roderick Bloem (rbloem@colorado.edu) : On Irix we need ttold +case "$target" in + mips-sgi-irix*) + AC_DEFINE(NEED_TTOLD);; +esac + +#---------------------------------------------------------------------- +# Checks for library functions. +#---------------------------------------------------------------------- + +AC_PROG_GCC_TRADITIONAL +AC_FUNC_MEMCMP +AC_TYPE_SIGNAL +AC_CHECK_FUNCS(gettimeofday strchr strstr setvbuf getenv unlink mkstemp close) + +#----------------------------------------------------------------------- +# Check for mawk, gawk, nawk, awk in that order +#----------------------------------------------------------------------- +AC_PROG_AWK + +#---------------------------------------------------------------------- +# Create the Makefile from Makefile.in +#---------------------------------------------------------------------- +if test "$gcc_ok" = "g++"; then + CC=$gcc_ok +fi +AC_OUTPUT(Makefile) Index: vis_dev/vis-2.1/examples/arbiter/README =================================================================== --- vis_dev/vis-2.1/examples/arbiter/README (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/README (revision 11) @@ -0,0 +1,87 @@ +A simple arbitration circuit for VIS TTC +Yuji Kukimoto +kukimoto@eecs.berkeley.edu + +STG: see figures.ps +circuit structure: see figures.ps + +Overall picture: + +Three requesting modules (called clients) are competing to get a bus +access. At any point, only one module is allowed to get a bus access. +Each client has a controller attached to it, from which an +acknowledgment is given. All the controllers communicate with an +arbiter so that at any time at most one controller gives an +acknowledgment. The arbiter is a simple three-state machine. It has +a single output indicating which controller can be selected among the +three at each time tick. If the "active" input of the controller is +0, the output is X, meaning that no one is selected. + +The protocol here is that a controller takes a control from the +arbiter if it is selected by the arbiter and it has a request. +Otherwise, the control is passed to the next controller. A signal +pass_ctrl is set to one iff the controller needs to pass a control to +another controller. There are two cases: 1) when the controller is +done processing a request, 2) when the controller has no request +waiting, but is selected. In both cases, the variable is set to one in +the next clock so that another controller waiting for an access can +take a control. The "active" signal of the arbiter is set to one iff +one of the pass_ctrl is set to one. + +A client has to keep a request signal high until an acknowledgment is +given. Even after an acknowledgment is returned from the +corresponding controller, req can be high for a finite amount of time. +This means that different requests take different time to complete. +Fairness constraints arise here since we do not want to keep req high +for infinite time. + +I. CTL Model Checking + +A. Property: + + 1. mutual exclusion + 2. AG(req->AF(ack)) + + # safety: mutual exclusion + AG ( !(ackA = 1 * ackB = 1 + ackB = 1 * ackC = 1 + ackC = 1 * ackA=1) ); + + # liveness: + AG( (reqA = 1) -> AF(ackA = 1) ); + AG( (reqB = 1) -> AF(ackB = 1) ); + AG( (reqC = 1) -> AF(ackC = 1) ); + +B. Fairness: + + !(clientA.state=HAVE_TOKEN); + !(clientB.state=HAVE_TOKEN); + !(clientC.state=HAVE_TOKEN); + +C. Files: + + arbiter.v: a fair arbiter. the liveness property passes under fairness + constraints. arbiter_bug.v is another version of arbiter.v, where the state + transition graph of the arbiter is slightly different. This is not a + fair arbiter. + + arbiter.fair: fairness constraints + + arbiter.ctl: ctl files + +II. Language emptiness check: + +A. File: arbiter_le.v + +An observer is added to check if the liveness property for clientA is +satisfied. The observer is a non-deterministic machine which +represents the complement of the liveness property. Ending up in +state BAD in the observer means that the behavior is bad. Thus, +observer.state=BAD is added to the fairness constraints. The +corresponding fairness file is arbiter_le.fair. The language emptiness +check passes, implying that the design is correct. + +B. Note: + +Complementing the liveness property is not so intuitive even though +the property is very simple. It turned out that we really need a +non-deterministic machine to representing this property under Buchi +constraint. Index: vis_dev/vis-2.1/examples/arbiter/arbiter.ctl =================================================================== --- vis_dev/vis-2.1/examples/arbiter/arbiter.ctl (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/arbiter.ctl (revision 11) @@ -0,0 +1,7 @@ +# safety: mutual exclusion +AG ( !(ackA = 1 * ackB = 1 + ackB = 1 * ackC = 1 + ackC = 1 * ackA=1) ); + +# liveness: +AG( (reqA = 1) -> AF(ackA = 1) ); +AG( (reqB = 1) -> AF(ackB = 1) ); +AG( (reqC = 1) -> AF(ackC = 1) ); Index: vis_dev/vis-2.1/examples/arbiter/arbiter.fair =================================================================== --- vis_dev/vis-2.1/examples/arbiter/arbiter.fair (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/arbiter.fair (revision 11) @@ -0,0 +1,3 @@ +!(clientA.state=HAVE_TOKEN); +!(clientB.state=HAVE_TOKEN); +!(clientC.state=HAVE_TOKEN); Index: vis_dev/vis-2.1/examples/arbiter/arbiter.ltl =================================================================== --- vis_dev/vis-2.1/examples/arbiter/arbiter.ltl (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/arbiter.ltl (revision 11) @@ -0,0 +1,7 @@ +# safety: mutual exclusion +G !(ackA=1 * ackB=1 + ackB=1 * ackC=1 + ackC=1 * ackA=1); + +# liveness: +G(reqA=1 -> F ackA=1); +G(reqB=1 -> F ackB=1); +G(reqC=1 -> F ackC=1); Index: vis_dev/vis-2.1/examples/arbiter/arbiter.mv =================================================================== --- vis_dev/vis-2.1/examples/arbiter/arbiter.mv (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/arbiter.mv (revision 11) @@ -0,0 +1,531 @@ +# vl2mv arbiter.v +# version: 0.2 +# date: 15:54:08 11/04/96 (PST) +.model main +# I/O ports +.outputs ackA +.outputs ackB +.outputs ackC + +.mv sel 4 A B C X +# assign active = pass_tokenA || pass_tokenB || pass_tokenC +# pass_tokenA || pass_tokenB +.names pass_tokenA pass_tokenB _n1 +.def 1 +0 0 0 +# pass_tokenA || pass_tokenB || pass_tokenC +.names _n1 pass_tokenC _n2 +.def 1 +0 0 0 +.names _n2 active$raw_n0 +- =_n2 +.mv _n3 4 A B C X +.names _n3 +A +.subckt controller controllerA req=reqA ack=ackA sel=sel pass_token=pass_tokenA id=_n3 +.mv _n4 4 A B C X +.names _n4 +B +.subckt controller controllerB req=reqB ack=ackB sel=sel pass_token=pass_tokenB id=_n4 +.mv _n5 4 A B C X +.names _n5 +C +.subckt controller controllerC req=reqC ack=ackC sel=sel pass_token=pass_tokenC id=_n5 +.subckt arbiter arbiter sel=sel active=active +.subckt client clientA req=reqA ack=ackA +.subckt client clientB req=reqB ack=ackB +.subckt client clientC req=reqC ack=ackC +# conflict arbitrators +.names active$raw_n0 active +0 0 +1 1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model controller +# I/O ports +.inputs sel +.inputs req +.outputs pass_token +.outputs ack +.inputs id + +.mv sel 4 A B C X +.mv state 3 IDLE READY BUSY +.mv id 4 A B C X +# state = 0 +.mv state$raw_n6 3 IDLE READY BUSY +.names state$raw_n6 +IDLE +# non-blocking assignments for initial +# ack = 0 +.names ack$raw_n7 +0 +# non-blocking assignments for initial +# pass_token = 1 +.names pass_token$raw_n8 +1 +# non-blocking assignments for initial +# assign is_selected = (sel == id ) +# sel == id +.names sel id _na +.def 0 +- =sel 1 +.names _na is_selected$raw_n9 +- =_na +.mv _nd 3 IDLE READY BUSY +.names _nd +IDLE +.names state _nd _nc +.def 0 +- =state 1 +.names _nc _nb +1 1 +0 0 +.names is_selected _ne +- =is_selected +.names req _nf +- =req +# state = 1 +.mv state$req_n10$true 3 IDLE READY BUSY +.names state$req_n10$true +READY +# pass_token = 0 +.names pass_token$req_n11$true +0 +# pass_token = 1 +.names pass_token$req_n12$false +1 +# if/else (req ) +.names pass_token$req_n11$true pass_token$req_n12$false req pass_token$req$raw_n15 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$req$raw_n19 3 IDLE READY BUSY +.names state$req_n10$true state req state$req$raw_n19 +- - 0 =state +- - 1 =state$req_n10$true +# pass_token = 0 +.names pass_token$is_selected_n1b$false +0 +# if/else (is_selected ) +.names pass_token$req$raw_n15 pass_token$is_selected_n1b$false is_selected pass_token$is_selected$raw_n1f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$is_selected$raw_n21 3 IDLE READY BUSY +.names state$req$raw_n19 state is_selected state$is_selected$raw_n21 +- - 0 =state +- - 1 =state$req$raw_n19 +.mv _n26 3 IDLE READY BUSY +.names _n26 +READY +.names state _n26 _n25 +.def 0 +- =state 1 +.names _n25 _n24 +1 1 +0 0 +# state = 2 +.mv state$_n24_n27$true 3 IDLE READY BUSY +.names state$_n24_n27$true +BUSY +# ack = 1 +.names ack$_n24_n28$true +1 +.mv _n2b 3 IDLE READY BUSY +.names _n2b +BUSY +.names state _n2b _n2a +.def 0 +- =state 1 +.names _n2a _n29 +1 1 +0 0 +.names req _n2c +0 1 +1 0 +.names _n2c _n2d +- =_n2c +# state = 0 +.mv state$_n2c_n2e$true 3 IDLE READY BUSY +.names state$_n2c_n2e$true +IDLE +# ack = 0 +.names ack$_n2c_n2f$true +0 +# pass_token = 1 +.names pass_token$_n2c_n30$true +1 +# if/else (!req ) +.names pass_token$_n2c_n30$true pass_token _n2c pass_token$_n2c$raw_n37 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_n2c$raw_n39 3 IDLE READY BUSY +.names state$_n2c_n2e$true state _n2c state$_n2c$raw_n39 +- - 0 =state +- - 1 =state$_n2c_n2e$true +.names ack$_n2c_n2f$true ack _n2c ack$_n2c$raw_n3a +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# case (state ) +.mv state$_n29$raw_n42 3 IDLE READY BUSY +.names state$_n2c$raw_n39 state _n29 state$_n29$raw_n42 +- - 0 =state +- - 1 =state$_n2c$raw_n39 +.names pass_token$_n2c$raw_n37 pass_token _n29 pass_token$_n29$raw_n43 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names ack$_n2c$raw_n3a ack _n29 ack$_n29$raw_n45 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_n24$raw_n47 3 IDLE READY BUSY +.names state$_n24_n27$true state$_n29$raw_n42 _n24 state$_n24$raw_n47 +- - 0 =state$_n29$raw_n42 +- - 1 =state$_n24_n27$true +.names ack$_n24_n28$true ack$_n29$raw_n45 _n24 ack$_n24$raw_n48 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names pass_token pass_token$_n29$raw_n43 _n24 pass_token$_n24$raw_n4f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_nb$raw_n52 3 IDLE READY BUSY +.names state$is_selected$raw_n21 state$_n24$raw_n47 _nb state$_nb$raw_n52 +- - 0 =state$_n24$raw_n47 +- - 1 =state$is_selected$raw_n21 +.names pass_token$is_selected$raw_n1f pass_token$_n24$raw_n4f _nb pass_token$_nb$raw_n53 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names ack ack$_n24$raw_n48 _nb ack$_nb$raw_n5b +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names is_selected$raw_n9 is_selected +0 0 +1 1 +.names _nb _ne _nf _n24 _n29 _n2d _n5d +.def 0 + 1 1 1 - - - 1 + 0 - - 1 - - 1 + 0 - - 0 1 1 1 +.mv _n5e 3 IDLE READY BUSY +.names _n5d state$_nb$raw_n52 state _n5e +1 - - =state$_nb$raw_n52 +0 - - =state +.names _nb _ne _nf _n24 _n29 _n2d _n62 +.def 0 + 1 1 1 - - - 1 + 1 1 0 - - - 1 + 1 0 - - - - 1 + 0 - - 0 1 1 1 +.names _n62 pass_token$_nb$raw_n53 pass_token _n63 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _nb _n24 _n29 _n2d _n64 +.def 0 + 0 1 - - 1 + 0 0 1 1 1 +.names _n64 ack$_nb$raw_n5b ack _n65 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +# non-blocking assignments +# latches +.r pass_token$raw_n8 pass_token +0 0 +1 1 +.latch _n63 pass_token +.r state$raw_n6 state +- =state$raw_n6 +.latch _n5e state +.r ack$raw_n7 ack +0 0 +1 1 +.latch _n65 ack +# quasi-continuous assignment +.end + + +.model arbiter +# I/O ports +.outputs sel +.inputs active + +.mv sel 4 A B C X +.mv state 4 A B C X +# state = 0 +.mv state$raw_n66 4 A B C X +.names state$raw_n66 +A +# non-blocking assignments for initial +# assign sel = active ? state : 3 +.mv sel$raw_n67 4 A B C X +.mv _n68 4 A B C X +.names _n68 +X +# active ? state : 3 +.mv _n69 4 A B C X +.names state _n68 active _n69 +- - 0 =_n68 +- - 1 =state +.names _n69 sel$raw_n67 +- =_n69 +.names active _n6a +- =active +.mv _n6d 4 A B C X +.names _n6d +A +.names state _n6d _n6c +.def 0 +- =state 1 +.names _n6c _n6b +1 1 +0 0 +# state = 1 +.mv state$_n6b_n6e$true 4 A B C X +.names state$_n6b_n6e$true +B +.mv _n71 4 A B C X +.names _n71 +B +.names state _n71 _n70 +.def 0 +- =state 1 +.names _n70 _n6f +1 1 +0 0 +# state = 2 +.mv state$_n6f_n72$true 4 A B C X +.names state$_n6f_n72$true +C +.mv _n75 4 A B C X +.names _n75 +C +.names state _n75 _n74 +.def 0 +- =state 1 +.names _n74 _n73 +1 1 +0 0 +# state = 0 +.mv state$_n73_n76$true 4 A B C X +.names state$_n73_n76$true +A +# case (state ) +.mv state$_n73$raw_n79 4 A B C X +.names state$_n73_n76$true state _n73 state$_n73$raw_n79 +- - 0 =state +- - 1 =state$_n73_n76$true +.mv state$_n6f$raw_n7a 4 A B C X +.names state$_n6f_n72$true state$_n73$raw_n79 _n6f state$_n6f$raw_n7a +- - 0 =state$_n73$raw_n79 +- - 1 =state$_n6f_n72$true +.mv state$_n6b$raw_n7e 4 A B C X +.names state$_n6b_n6e$true state$_n6f$raw_n7a _n6b state$_n6b$raw_n7e +- - 0 =state$_n6f$raw_n7a +- - 1 =state$_n6b_n6e$true +# if/else (active ) +.mv state$active$raw_n84 4 A B C X +.names state$_n6b$raw_n7e state active state$active$raw_n84 +- - 0 =state +- - 1 =state$_n6b$raw_n7e +# conflict arbitrators +.names sel$raw_n67 sel +- =sel$raw_n67 +.names _n6a _n6b _n6f _n73 _n85 +.def 0 + 1 1 - - 1 + 1 0 1 - 1 + 1 0 0 1 1 +.mv _n86 4 A B C X +.names _n85 state$active$raw_n84 state _n86 +1 - - =state$active$raw_n84 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n66 state +- =state$raw_n66 +.latch _n86 state +# quasi-continuous assignment +.end + + +.model client +# I/O ports +.outputs req +.inputs ack + +.mv state 3 NO_REQ REQ HAVE_TOKEN +# req = 0 +.names req$raw_n89 +0 +# non-blocking assignments for initial +# state = 0 +.mv state$raw_n8a 3 NO_REQ REQ HAVE_TOKEN +.names state$raw_n8a +NO_REQ +# non-blocking assignments for initial +# assign rand_choice = $NDset ( 0,1 ) +.names rand_choice +0 +1 +.mv _n8f 3 NO_REQ REQ HAVE_TOKEN +.names _n8f +NO_REQ +.names state _n8f _n8e +.def 0 +- =state 1 +.names _n8e _n8d +1 1 +0 0 +.names rand_choice _n90 +- =rand_choice +# req = 1 +.names req$rand_choice_n91$true +1 +# state = 1 +.mv state$rand_choice_n92$true 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_n92$true +REQ +# if/else (rand_choice ) +.names req$rand_choice_n91$true req rand_choice req$rand_choice$raw_n97 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$rand_choice$raw_n99 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_n92$true state rand_choice state$rand_choice$raw_n99 +- - 0 =state +- - 1 =state$rand_choice_n92$true +.mv _n9c 3 NO_REQ REQ HAVE_TOKEN +.names _n9c +REQ +.names state _n9c _n9b +.def 0 +- =state 1 +.names _n9b _n9a +1 1 +0 0 +.names ack _n9d +- =ack +# state = 2 +.mv state$ack_n9e$true 3 NO_REQ REQ HAVE_TOKEN +.names state$ack_n9e$true +HAVE_TOKEN +# if/else (ack ) +.mv state$ack$raw_na1 3 NO_REQ REQ HAVE_TOKEN +.names state$ack_n9e$true state ack state$ack$raw_na1 +- - 0 =state +- - 1 =state$ack_n9e$true +.mv _na4 3 NO_REQ REQ HAVE_TOKEN +.names _na4 +HAVE_TOKEN +.names state _na4 _na3 +.def 0 +- =state 1 +.names _na3 _na2 +1 1 +0 0 +.names rand_choice _na5 +- =rand_choice +# req = 0 +.names req$rand_choice_na6$true +0 +# state = 0 +.mv state$rand_choice_na7$true 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_na7$true +NO_REQ +# if/else (rand_choice ) +.names req$rand_choice_na6$true req rand_choice req$rand_choice$raw_nac +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$rand_choice$raw_nae 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_na7$true state rand_choice state$rand_choice$raw_nae +- - 0 =state +- - 1 =state$rand_choice_na7$true +# case (state ) +.names req$rand_choice$raw_nac req _na2 req$_na2$raw_nb3 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_na2$raw_nb5 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice$raw_nae state _na2 state$_na2$raw_nb5 +- - 0 =state +- - 1 =state$rand_choice$raw_nae +.mv state$_n9a$raw_nb6 3 NO_REQ REQ HAVE_TOKEN +.names state$ack$raw_na1 state$_na2$raw_nb5 _n9a state$_n9a$raw_nb6 +- - 0 =state$_na2$raw_nb5 +- - 1 =state$ack$raw_na1 +.names req req$_na2$raw_nb3 _n9a req$_n9a$raw_nb9 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names req$rand_choice$raw_n97 req$_n9a$raw_nb9 _n8d req$_n8d$raw_nbc +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_n8d$raw_nbe 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice$raw_n99 state$_n9a$raw_nb6 _n8d state$_n8d$raw_nbe +- - 0 =state$_n9a$raw_nb6 +- - 1 =state$rand_choice$raw_n99 +# conflict arbitrators +.names _n8d _n90 _n9a _na2 _na5 _nc5 +.def 0 + 1 1 - - - 1 + 0 - 0 1 1 1 +.names _nc5 req$_n8d$raw_nbc req _nc6 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n8d _n90 _n9a _n9d _na2 _na5 _nc7 +.def 0 + 1 1 - - - - 1 + 0 - 1 1 - - 1 + 0 - 0 - 1 1 1 +.mv _nc8 3 NO_REQ REQ HAVE_TOKEN +.names _nc7 state$_n8d$raw_nbe state _nc8 +1 - - =state$_n8d$raw_nbe +0 - - =state +# non-blocking assignments +# latches +.r req$raw_n89 req +0 0 +1 1 +.latch _nc6 req +.r state$raw_n8a state +- =state$raw_n8a +.latch _nc8 state +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/arbiter/arbiter.v =================================================================== --- vis_dev/vis-2.1/examples/arbiter/arbiter.v (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/arbiter.v (revision 11) @@ -0,0 +1,126 @@ +typedef enum {A, B, C, X} selection; +typedef enum {IDLE, READY, BUSY} controller_state; +typedef enum {NO_REQ, REQ, HAVE_TOKEN} client_state; + +module main(clk); +input clk; +output ackA, ackB, ackC; + +selection wire sel; +wire active; + +assign active = pass_tokenA || pass_tokenB || pass_tokenC; + +controller controllerA(clk, reqA, ackA, sel, pass_tokenA, A); +controller controllerB(clk, reqB, ackB, sel, pass_tokenB, B); +controller controllerC(clk, reqC, ackC, sel, pass_tokenC, C); +arbiter arbiter(clk, sel, active); + +client clientA(clk, reqA, ackA); +client clientB(clk, reqB, ackB); +client clientC(clk, reqC, ackC); + +endmodule + +module controller(clk, req, ack, sel, pass_token, id); +input clk, req, sel, id; +output ack, pass_token; + +selection wire sel, id; +reg ack, pass_token; +controller_state reg state; + +initial state = IDLE; +initial ack = 0; +initial pass_token = 1; + +wire is_selected; +assign is_selected = (sel == id); + +always @(posedge clk) begin + case(state) + IDLE: + if (is_selected) + if (req) + begin + state = READY; + pass_token = 0; /* dropping off this line causes a safety bug */ + end + else + pass_token = 1; + else + pass_token = 0; + READY: + begin + state = BUSY; + ack = 1; + end + BUSY: + if (!req) + begin + state = IDLE; + ack = 0; + pass_token = 1; + end + endcase +end +endmodule + +module arbiter(clk, sel, active); +input clk, active; +output sel; + +selection wire sel; +selection reg state; + +initial state = A; + +assign sel = active ? state: X; + +always @(posedge clk) begin + if (active) + case(state) + A: + state = B; + B: + state = C; + C: + state = A; + endcase +end +endmodule + +module client(clk, req, ack); +input clk, ack; +output req; + +reg req; +client_state reg state; + +wire rand_choice; + +initial req = 0; +initial state = NO_REQ; + +assign rand_choice = $ND(0,1); + +always @(posedge clk) begin + case(state) + NO_REQ: + if (rand_choice) + begin + req = 1; + state = REQ; + end + REQ: + if (ack) + state = HAVE_TOKEN; + HAVE_TOKEN: + if (rand_choice) + begin + req = 0; + state = NO_REQ; + end + endcase +end +endmodule Index: vis_dev/vis-2.1/examples/arbiter/arbiter_bug.mv =================================================================== --- vis_dev/vis-2.1/examples/arbiter/arbiter_bug.mv (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/arbiter_bug.mv (revision 11) @@ -0,0 +1,524 @@ +# vl2mv arbiter_bug.v +# version: 0.2 +# date: 15:54:13 11/04/96 (PST) +.model main +# I/O ports +.outputs ackA +.outputs ackB +.outputs ackC + +.mv sel 4 A B C X +# assign active = pass_tokenA || pass_tokenB || pass_tokenC +# pass_tokenA || pass_tokenB +.names pass_tokenA pass_tokenB _n1 +.def 1 +0 0 0 +# pass_tokenA || pass_tokenB || pass_tokenC +.names _n1 pass_tokenC _n2 +.def 1 +0 0 0 +.names _n2 active$raw_n0 +- =_n2 +.mv _n3 4 A B C X +.names _n3 +A +.subckt controller controllerA req=reqA ack=ackA sel=sel pass_token=pass_tokenA id=_n3 +.mv _n4 4 A B C X +.names _n4 +B +.subckt controller controllerB req=reqB ack=ackB sel=sel pass_token=pass_tokenB id=_n4 +.mv _n5 4 A B C X +.names _n5 +C +.subckt controller controllerC req=reqC ack=ackC sel=sel pass_token=pass_tokenC id=_n5 +.subckt arbiter arbiter sel=sel active=active +.subckt client clientA req=reqA ack=ackA +.subckt client clientB req=reqB ack=ackB +.subckt client clientC req=reqC ack=ackC +# conflict arbitrators +.names active$raw_n0 active +0 0 +1 1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model controller +# I/O ports +.inputs sel +.inputs req +.outputs pass_token +.outputs ack +.inputs id + +.mv sel 4 A B C X +.mv state 3 IDLE READY BUSY +.mv id 4 A B C X +# state = 0 +.mv state$raw_n6 3 IDLE READY BUSY +.names state$raw_n6 +IDLE +# non-blocking assignments for initial +# ack = 0 +.names ack$raw_n7 +0 +# non-blocking assignments for initial +# pass_token = 1 +.names pass_token$raw_n8 +1 +# non-blocking assignments for initial +# assign is_selected = (sel == id ) +# sel == id +.names sel id _na +.def 0 +- =sel 1 +.names _na is_selected$raw_n9 +- =_na +.mv _nd 3 IDLE READY BUSY +.names _nd +IDLE +.names state _nd _nc +.def 0 +- =state 1 +.names _nc _nb +1 1 +0 0 +.names is_selected _ne +- =is_selected +.names req _nf +- =req +# state = 1 +.mv state$req_n10$true 3 IDLE READY BUSY +.names state$req_n10$true +READY +# pass_token = 0 +.names pass_token$req_n11$true +0 +# pass_token = 1 +.names pass_token$req_n12$false +1 +# if/else (req ) +.names pass_token$req_n11$true pass_token$req_n12$false req pass_token$req$raw_n15 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$req$raw_n19 3 IDLE READY BUSY +.names state$req_n10$true state req state$req$raw_n19 +- - 0 =state +- - 1 =state$req_n10$true +# pass_token = 0 +.names pass_token$is_selected_n1b$false +0 +# if/else (is_selected ) +.names pass_token$req$raw_n15 pass_token$is_selected_n1b$false is_selected pass_token$is_selected$raw_n1f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$is_selected$raw_n21 3 IDLE READY BUSY +.names state$req$raw_n19 state is_selected state$is_selected$raw_n21 +- - 0 =state +- - 1 =state$req$raw_n19 +.mv _n26 3 IDLE READY BUSY +.names _n26 +READY +.names state _n26 _n25 +.def 0 +- =state 1 +.names _n25 _n24 +1 1 +0 0 +# state = 2 +.mv state$_n24_n27$true 3 IDLE READY BUSY +.names state$_n24_n27$true +BUSY +# ack = 1 +.names ack$_n24_n28$true +1 +.mv _n2b 3 IDLE READY BUSY +.names _n2b +BUSY +.names state _n2b _n2a +.def 0 +- =state 1 +.names _n2a _n29 +1 1 +0 0 +.names req _n2c +0 1 +1 0 +.names _n2c _n2d +- =_n2c +# state = 0 +.mv state$_n2c_n2e$true 3 IDLE READY BUSY +.names state$_n2c_n2e$true +IDLE +# ack = 0 +.names ack$_n2c_n2f$true +0 +# pass_token = 1 +.names pass_token$_n2c_n30$true +1 +# if/else (!req ) +.names pass_token$_n2c_n30$true pass_token _n2c pass_token$_n2c$raw_n37 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_n2c$raw_n39 3 IDLE READY BUSY +.names state$_n2c_n2e$true state _n2c state$_n2c$raw_n39 +- - 0 =state +- - 1 =state$_n2c_n2e$true +.names ack$_n2c_n2f$true ack _n2c ack$_n2c$raw_n3a +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# case (state ) +.mv state$_n29$raw_n42 3 IDLE READY BUSY +.names state$_n2c$raw_n39 state _n29 state$_n29$raw_n42 +- - 0 =state +- - 1 =state$_n2c$raw_n39 +.names pass_token$_n2c$raw_n37 pass_token _n29 pass_token$_n29$raw_n43 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names ack$_n2c$raw_n3a ack _n29 ack$_n29$raw_n45 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_n24$raw_n47 3 IDLE READY BUSY +.names state$_n24_n27$true state$_n29$raw_n42 _n24 state$_n24$raw_n47 +- - 0 =state$_n29$raw_n42 +- - 1 =state$_n24_n27$true +.names ack$_n24_n28$true ack$_n29$raw_n45 _n24 ack$_n24$raw_n48 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names pass_token pass_token$_n29$raw_n43 _n24 pass_token$_n24$raw_n4f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_nb$raw_n52 3 IDLE READY BUSY +.names state$is_selected$raw_n21 state$_n24$raw_n47 _nb state$_nb$raw_n52 +- - 0 =state$_n24$raw_n47 +- - 1 =state$is_selected$raw_n21 +.names pass_token$is_selected$raw_n1f pass_token$_n24$raw_n4f _nb pass_token$_nb$raw_n53 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names ack ack$_n24$raw_n48 _nb ack$_nb$raw_n5b +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names is_selected$raw_n9 is_selected +0 0 +1 1 +.names _nb _ne _nf _n24 _n29 _n2d _n5d +.def 0 + 1 1 1 - - - 1 + 0 - - 1 - - 1 + 0 - - 0 1 1 1 +.mv _n5e 3 IDLE READY BUSY +.names _n5d state$_nb$raw_n52 state _n5e +1 - - =state$_nb$raw_n52 +0 - - =state +.names _nb _ne _nf _n24 _n29 _n2d _n62 +.def 0 + 1 1 1 - - - 1 + 1 1 0 - - - 1 + 1 0 - - - - 1 + 0 - - 0 1 1 1 +.names _n62 pass_token$_nb$raw_n53 pass_token _n63 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _nb _n24 _n29 _n2d _n64 +.def 0 + 0 1 - - 1 + 0 0 1 1 1 +.names _n64 ack$_nb$raw_n5b ack _n65 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +# non-blocking assignments +# latches +.r pass_token$raw_n8 pass_token +0 0 +1 1 +.latch _n63 pass_token +.r state$raw_n6 state +- =state$raw_n6 +.latch _n5e state +.r ack$raw_n7 ack +0 0 +1 1 +.latch _n65 ack +# quasi-continuous assignment +.end + + +.model arbiter +# I/O ports +.outputs sel +.inputs active + +.mv sel 4 A B C X +.mv state 4 A B C X +# state = 0 +.mv state$raw_n66 4 A B C X +.names state$raw_n66 +A +# non-blocking assignments for initial +# assign sel = active ? state : 3 +.mv sel$raw_n67 4 A B C X +.mv _n68 4 A B C X +.names _n68 +X +# active ? state : 3 +.mv _n69 4 A B C X +.names state _n68 active _n69 +- - 0 =_n68 +- - 1 =state +.names _n69 sel$raw_n67 +- =_n69 +.mv _n6c 4 A B C X +.names _n6c +A +.names state _n6c _n6b +.def 0 +- =state 1 +.names _n6b _n6a +1 1 +0 0 +# state = 1 +.mv state$_n6a_n6d$true 4 A B C X +.names state$_n6a_n6d$true +B +.mv _n70 4 A B C X +.names _n70 +B +.names state _n70 _n6f +.def 0 +- =state 1 +.names _n6f _n6e +1 1 +0 0 +# state = 2 +.mv state$_n6e_n71$true 4 A B C X +.names state$_n6e_n71$true +C +.mv _n74 4 A B C X +.names _n74 +C +.names state _n74 _n73 +.def 0 +- =state 1 +.names _n73 _n72 +1 1 +0 0 +# state = 0 +.mv state$_n72_n75$true 4 A B C X +.names state$_n72_n75$true +A +# case (state ) +.mv state$_n72$raw_n78 4 A B C X +.names state$_n72_n75$true state _n72 state$_n72$raw_n78 +- - 0 =state +- - 1 =state$_n72_n75$true +.mv state$_n6e$raw_n79 4 A B C X +.names state$_n6e_n71$true state$_n72$raw_n78 _n6e state$_n6e$raw_n79 +- - 0 =state$_n72$raw_n78 +- - 1 =state$_n6e_n71$true +.mv state$_n6a$raw_n7d 4 A B C X +.names state$_n6a_n6d$true state$_n6e$raw_n79 _n6a state$_n6a$raw_n7d +- - 0 =state$_n6e$raw_n79 +- - 1 =state$_n6a_n6d$true +# conflict arbitrators +.names sel$raw_n67 sel +- =sel$raw_n67 +.names _n6a _n6e _n72 _n81 +.def 0 + 1 - - 1 + 0 1 - 1 + 0 0 1 1 +.mv _n82 4 A B C X +.names _n81 state$_n6a$raw_n7d state _n82 +1 - - =state$_n6a$raw_n7d +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n66 state +- =state$raw_n66 +.latch _n82 state +# quasi-continuous assignment +.end + + +.model client +# I/O ports +.outputs req +.inputs ack + +.mv state 3 NO_REQ REQ HAVE_TOKEN +# req = 0 +.names req$raw_n85 +0 +# non-blocking assignments for initial +# state = 0 +.mv state$raw_n86 3 NO_REQ REQ HAVE_TOKEN +.names state$raw_n86 +NO_REQ +# non-blocking assignments for initial +# assign rand_choice = $NDset ( 0,1 ) +.names rand_choice +0 +1 +.mv _n8b 3 NO_REQ REQ HAVE_TOKEN +.names _n8b +NO_REQ +.names state _n8b _n8a +.def 0 +- =state 1 +.names _n8a _n89 +1 1 +0 0 +.names rand_choice _n8c +- =rand_choice +# req = 1 +.names req$rand_choice_n8d$true +1 +# state = 1 +.mv state$rand_choice_n8e$true 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_n8e$true +REQ +# if/else (rand_choice ) +.names req$rand_choice_n8d$true req rand_choice req$rand_choice$raw_n93 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$rand_choice$raw_n95 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_n8e$true state rand_choice state$rand_choice$raw_n95 +- - 0 =state +- - 1 =state$rand_choice_n8e$true +.mv _n98 3 NO_REQ REQ HAVE_TOKEN +.names _n98 +REQ +.names state _n98 _n97 +.def 0 +- =state 1 +.names _n97 _n96 +1 1 +0 0 +.names ack _n99 +- =ack +# state = 2 +.mv state$ack_n9a$true 3 NO_REQ REQ HAVE_TOKEN +.names state$ack_n9a$true +HAVE_TOKEN +# if/else (ack ) +.mv state$ack$raw_n9d 3 NO_REQ REQ HAVE_TOKEN +.names state$ack_n9a$true state ack state$ack$raw_n9d +- - 0 =state +- - 1 =state$ack_n9a$true +.mv _na0 3 NO_REQ REQ HAVE_TOKEN +.names _na0 +HAVE_TOKEN +.names state _na0 _n9f +.def 0 +- =state 1 +.names _n9f _n9e +1 1 +0 0 +.names rand_choice _na1 +- =rand_choice +# req = 0 +.names req$rand_choice_na2$true +0 +# state = 0 +.mv state$rand_choice_na3$true 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_na3$true +NO_REQ +# if/else (rand_choice ) +.names req$rand_choice_na2$true req rand_choice req$rand_choice$raw_na8 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$rand_choice$raw_naa 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_na3$true state rand_choice state$rand_choice$raw_naa +- - 0 =state +- - 1 =state$rand_choice_na3$true +# case (state ) +.names req$rand_choice$raw_na8 req _n9e req$_n9e$raw_naf +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_n9e$raw_nb1 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice$raw_naa state _n9e state$_n9e$raw_nb1 +- - 0 =state +- - 1 =state$rand_choice$raw_naa +.mv state$_n96$raw_nb2 3 NO_REQ REQ HAVE_TOKEN +.names state$ack$raw_n9d state$_n9e$raw_nb1 _n96 state$_n96$raw_nb2 +- - 0 =state$_n9e$raw_nb1 +- - 1 =state$ack$raw_n9d +.names req req$_n9e$raw_naf _n96 req$_n96$raw_nb5 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names req$rand_choice$raw_n93 req$_n96$raw_nb5 _n89 req$_n89$raw_nb8 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_n89$raw_nba 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice$raw_n95 state$_n96$raw_nb2 _n89 state$_n89$raw_nba +- - 0 =state$_n96$raw_nb2 +- - 1 =state$rand_choice$raw_n95 +# conflict arbitrators +.names _n89 _n8c _n96 _n9e _na1 _nc1 +.def 0 + 1 1 - - - 1 + 0 - 0 1 1 1 +.names _nc1 req$_n89$raw_nb8 req _nc2 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n89 _n8c _n96 _n99 _n9e _na1 _nc3 +.def 0 + 1 1 - - - - 1 + 0 - 1 1 - - 1 + 0 - 0 - 1 1 1 +.mv _nc4 3 NO_REQ REQ HAVE_TOKEN +.names _nc3 state$_n89$raw_nba state _nc4 +1 - - =state$_n89$raw_nba +0 - - =state +# non-blocking assignments +# latches +.r req$raw_n85 req +0 0 +1 1 +.latch _nc2 req +.r state$raw_n86 state +- =state$raw_n86 +.latch _nc4 state +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/arbiter/arbiter_bug.v =================================================================== --- vis_dev/vis-2.1/examples/arbiter/arbiter_bug.v (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/arbiter_bug.v (revision 11) @@ -0,0 +1,125 @@ +typedef enum {A, B, C, X} selection; +typedef enum {IDLE, READY, BUSY} controller_state; +typedef enum {NO_REQ, REQ, HAVE_TOKEN} client_state; + +module main(clk); +input clk; +output ackA, ackB, ackC; + +selection wire sel; +wire active; + +assign active = pass_tokenA || pass_tokenB || pass_tokenC; + +controller controllerA(clk, reqA, ackA, sel, pass_tokenA, A); +controller controllerB(clk, reqB, ackB, sel, pass_tokenB, B); +controller controllerC(clk, reqC, ackC, sel, pass_tokenC, C); +arbiter arbiter(clk, sel, active); + +client clientA(clk, reqA, ackA); +client clientB(clk, reqB, ackB); +client clientC(clk, reqC, ackC); + +endmodule + +module controller(clk, req, ack, sel, pass_token, id); +input clk, req, sel, id; +output ack, pass_token; + +selection wire sel, id; +reg ack, pass_token; +controller_state reg state; + +initial state = IDLE; +initial ack = 0; +initial pass_token = 1; + +wire is_selected; +assign is_selected = (sel == id); + +always @(posedge clk) begin + case(state) + IDLE: + if (is_selected) + if (req) + begin + state = READY; + pass_token = 0; /* dropping off this line causes a safety bug */ + end + else + pass_token = 1; + else + pass_token = 0; + READY: + begin + state = BUSY; + ack = 1; + end + BUSY: + if (!req) + begin + state = IDLE; + ack = 0; + pass_token = 1; + end + endcase +end +endmodule + +module arbiter(clk, sel, active); +input clk, active; +output sel; + +selection wire sel; +selection reg state; + +initial state = A; + +assign sel = active ? state: X; + +always @(posedge clk) begin + case(state) + A: + state = B; + B: + state = C; + C: + state = A; + endcase +end +endmodule + +module client(clk, req, ack); +input clk, ack; +output req; + +reg req; +client_state reg state; + +wire rand_choice; + +initial req = 0; +initial state = NO_REQ; + +assign rand_choice = $ND(0,1); + +always @(posedge clk) begin + case(state) + NO_REQ: + if (rand_choice) + begin + req = 1; + state = REQ; + end + REQ: + if (ack) + state = HAVE_TOKEN; + HAVE_TOKEN: + if (rand_choice) + begin + req = 0; + state = NO_REQ; + end + endcase +end +endmodule Index: vis_dev/vis-2.1/examples/arbiter/arbiter_le.fair =================================================================== --- vis_dev/vis-2.1/examples/arbiter/arbiter_le.fair (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/arbiter_le.fair (revision 11) @@ -0,0 +1,4 @@ +!(clientA.state=HAVE_TOKEN); +!(clientB.state=HAVE_TOKEN); +!(clientC.state=HAVE_TOKEN); +observer.state=BAD; Index: vis_dev/vis-2.1/examples/arbiter/arbiter_le.mv =================================================================== --- vis_dev/vis-2.1/examples/arbiter/arbiter_le.mv (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/arbiter_le.mv (revision 11) @@ -0,0 +1,618 @@ +# vl2mv arbiter_le.v +# version: 0.2 +# date: 15:54:18 11/04/96 (PST) +.model main +# I/O ports +.outputs ackA +.outputs ackB +.outputs ackC + +.mv sel 4 A B C X +# assign active = pass_tokenA || pass_tokenB || pass_tokenC +# pass_tokenA || pass_tokenB +.names pass_tokenA pass_tokenB _n1 +.def 1 +0 0 0 +# pass_tokenA || pass_tokenB || pass_tokenC +.names _n1 pass_tokenC _n2 +.def 1 +0 0 0 +.names _n2 active$raw_n0 +- =_n2 +.mv _n3 4 A B C X +.names _n3 +A +.subckt controller controllerA req=reqA ack=ackA sel=sel pass_token=pass_tokenA id=_n3 +.mv _n4 4 A B C X +.names _n4 +B +.subckt controller controllerB req=reqB ack=ackB sel=sel pass_token=pass_tokenB id=_n4 +.mv _n5 4 A B C X +.names _n5 +C +.subckt controller controllerC req=reqC ack=ackC sel=sel pass_token=pass_tokenC id=_n5 +.subckt arbiter arbiter sel=sel active=active +.subckt client clientA req=reqA ack=ackA +.subckt client clientB req=reqB ack=ackB +.subckt client clientC req=reqC ack=ackC +.subckt observer observer req=reqA ack=ackA +# conflict arbitrators +.names active$raw_n0 active +0 0 +1 1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model controller +# I/O ports +.inputs sel +.inputs req +.outputs pass_token +.outputs ack +.inputs id + +.mv sel 4 A B C X +.mv state 3 IDLE READY BUSY +.mv id 4 A B C X +# state = 0 +.mv state$raw_n6 3 IDLE READY BUSY +.names state$raw_n6 +IDLE +# non-blocking assignments for initial +# ack = 0 +.names ack$raw_n7 +0 +# non-blocking assignments for initial +# pass_token = 1 +.names pass_token$raw_n8 +1 +# non-blocking assignments for initial +# assign is_selected = (sel == id ) +# sel == id +.names sel id _na +.def 0 +- =sel 1 +.names _na is_selected$raw_n9 +- =_na +.mv _nd 3 IDLE READY BUSY +.names _nd +IDLE +.names state _nd _nc +.def 0 +- =state 1 +.names _nc _nb +1 1 +0 0 +.names is_selected _ne +- =is_selected +.names req _nf +- =req +# state = 1 +.mv state$req_n10$true 3 IDLE READY BUSY +.names state$req_n10$true +READY +# pass_token = 0 +.names pass_token$req_n11$true +0 +# pass_token = 1 +.names pass_token$req_n12$false +1 +# if/else (req ) +.names pass_token$req_n11$true pass_token$req_n12$false req pass_token$req$raw_n15 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$req$raw_n19 3 IDLE READY BUSY +.names state$req_n10$true state req state$req$raw_n19 +- - 0 =state +- - 1 =state$req_n10$true +# pass_token = 0 +.names pass_token$is_selected_n1b$false +0 +# if/else (is_selected ) +.names pass_token$req$raw_n15 pass_token$is_selected_n1b$false is_selected pass_token$is_selected$raw_n1f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$is_selected$raw_n21 3 IDLE READY BUSY +.names state$req$raw_n19 state is_selected state$is_selected$raw_n21 +- - 0 =state +- - 1 =state$req$raw_n19 +.mv _n26 3 IDLE READY BUSY +.names _n26 +READY +.names state _n26 _n25 +.def 0 +- =state 1 +.names _n25 _n24 +1 1 +0 0 +# state = 2 +.mv state$_n24_n27$true 3 IDLE READY BUSY +.names state$_n24_n27$true +BUSY +# ack = 1 +.names ack$_n24_n28$true +1 +.mv _n2b 3 IDLE READY BUSY +.names _n2b +BUSY +.names state _n2b _n2a +.def 0 +- =state 1 +.names _n2a _n29 +1 1 +0 0 +.names req _n2c +0 1 +1 0 +.names _n2c _n2d +- =_n2c +# state = 0 +.mv state$_n2c_n2e$true 3 IDLE READY BUSY +.names state$_n2c_n2e$true +IDLE +# ack = 0 +.names ack$_n2c_n2f$true +0 +# pass_token = 1 +.names pass_token$_n2c_n30$true +1 +# if/else (!req ) +.names pass_token$_n2c_n30$true pass_token _n2c pass_token$_n2c$raw_n37 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_n2c$raw_n39 3 IDLE READY BUSY +.names state$_n2c_n2e$true state _n2c state$_n2c$raw_n39 +- - 0 =state +- - 1 =state$_n2c_n2e$true +.names ack$_n2c_n2f$true ack _n2c ack$_n2c$raw_n3a +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# case (state ) +.mv state$_n29$raw_n42 3 IDLE READY BUSY +.names state$_n2c$raw_n39 state _n29 state$_n29$raw_n42 +- - 0 =state +- - 1 =state$_n2c$raw_n39 +.names pass_token$_n2c$raw_n37 pass_token _n29 pass_token$_n29$raw_n43 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names ack$_n2c$raw_n3a ack _n29 ack$_n29$raw_n45 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_n24$raw_n47 3 IDLE READY BUSY +.names state$_n24_n27$true state$_n29$raw_n42 _n24 state$_n24$raw_n47 +- - 0 =state$_n29$raw_n42 +- - 1 =state$_n24_n27$true +.names ack$_n24_n28$true ack$_n29$raw_n45 _n24 ack$_n24$raw_n48 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names pass_token pass_token$_n29$raw_n43 _n24 pass_token$_n24$raw_n4f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_nb$raw_n52 3 IDLE READY BUSY +.names state$is_selected$raw_n21 state$_n24$raw_n47 _nb state$_nb$raw_n52 +- - 0 =state$_n24$raw_n47 +- - 1 =state$is_selected$raw_n21 +.names pass_token$is_selected$raw_n1f pass_token$_n24$raw_n4f _nb pass_token$_nb$raw_n53 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names ack ack$_n24$raw_n48 _nb ack$_nb$raw_n5b +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names is_selected$raw_n9 is_selected +0 0 +1 1 +.names _nb _ne _nf _n24 _n29 _n2d _n5d +.def 0 + 1 1 1 - - - 1 + 0 - - 1 - - 1 + 0 - - 0 1 1 1 +.mv _n5e 3 IDLE READY BUSY +.names _n5d state$_nb$raw_n52 state _n5e +1 - - =state$_nb$raw_n52 +0 - - =state +.names _nb _ne _nf _n24 _n29 _n2d _n62 +.def 0 + 1 1 1 - - - 1 + 1 1 0 - - - 1 + 1 0 - - - - 1 + 0 - - 0 1 1 1 +.names _n62 pass_token$_nb$raw_n53 pass_token _n63 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _nb _n24 _n29 _n2d _n64 +.def 0 + 0 1 - - 1 + 0 0 1 1 1 +.names _n64 ack$_nb$raw_n5b ack _n65 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +# non-blocking assignments +# latches +.r pass_token$raw_n8 pass_token +0 0 +1 1 +.latch _n63 pass_token +.r state$raw_n6 state +- =state$raw_n6 +.latch _n5e state +.r ack$raw_n7 ack +0 0 +1 1 +.latch _n65 ack +# quasi-continuous assignment +.end + + +.model arbiter +# I/O ports +.outputs sel +.inputs active + +.mv sel 4 A B C X +.mv state 4 A B C X +# state = 0 +.mv state$raw_n66 4 A B C X +.names state$raw_n66 +A +# non-blocking assignments for initial +# assign sel = active ? state : 3 +.mv sel$raw_n67 4 A B C X +.mv _n68 4 A B C X +.names _n68 +X +# active ? state : 3 +.mv _n69 4 A B C X +.names state _n68 active _n69 +- - 0 =_n68 +- - 1 =state +.names _n69 sel$raw_n67 +- =_n69 +.names active _n6a +- =active +.mv _n6d 4 A B C X +.names _n6d +A +.names state _n6d _n6c +.def 0 +- =state 1 +.names _n6c _n6b +1 1 +0 0 +# state = 1 +.mv state$_n6b_n6e$true 4 A B C X +.names state$_n6b_n6e$true +B +.mv _n71 4 A B C X +.names _n71 +B +.names state _n71 _n70 +.def 0 +- =state 1 +.names _n70 _n6f +1 1 +0 0 +# state = 2 +.mv state$_n6f_n72$true 4 A B C X +.names state$_n6f_n72$true +C +.mv _n75 4 A B C X +.names _n75 +C +.names state _n75 _n74 +.def 0 +- =state 1 +.names _n74 _n73 +1 1 +0 0 +# state = 0 +.mv state$_n73_n76$true 4 A B C X +.names state$_n73_n76$true +A +# case (state ) +.mv state$_n73$raw_n79 4 A B C X +.names state$_n73_n76$true state _n73 state$_n73$raw_n79 +- - 0 =state +- - 1 =state$_n73_n76$true +.mv state$_n6f$raw_n7a 4 A B C X +.names state$_n6f_n72$true state$_n73$raw_n79 _n6f state$_n6f$raw_n7a +- - 0 =state$_n73$raw_n79 +- - 1 =state$_n6f_n72$true +.mv state$_n6b$raw_n7e 4 A B C X +.names state$_n6b_n6e$true state$_n6f$raw_n7a _n6b state$_n6b$raw_n7e +- - 0 =state$_n6f$raw_n7a +- - 1 =state$_n6b_n6e$true +# if/else (active ) +.mv state$active$raw_n84 4 A B C X +.names state$_n6b$raw_n7e state active state$active$raw_n84 +- - 0 =state +- - 1 =state$_n6b$raw_n7e +# conflict arbitrators +.names sel$raw_n67 sel +- =sel$raw_n67 +.names _n6a _n6b _n6f _n73 _n85 +.def 0 + 1 1 - - 1 + 1 0 1 - 1 + 1 0 0 1 1 +.mv _n86 4 A B C X +.names _n85 state$active$raw_n84 state _n86 +1 - - =state$active$raw_n84 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n66 state +- =state$raw_n66 +.latch _n86 state +# quasi-continuous assignment +.end + + +.model client +# I/O ports +.outputs req +.inputs ack + +.mv state 3 NO_REQ REQ HAVE_TOKEN +# req = 0 +.names req$raw_n89 +0 +# non-blocking assignments for initial +# state = 0 +.mv state$raw_n8a 3 NO_REQ REQ HAVE_TOKEN +.names state$raw_n8a +NO_REQ +# non-blocking assignments for initial +# assign rand_choice = $NDset ( 0,1 ) +.names rand_choice +0 +1 +.mv _n8f 3 NO_REQ REQ HAVE_TOKEN +.names _n8f +NO_REQ +.names state _n8f _n8e +.def 0 +- =state 1 +.names _n8e _n8d +1 1 +0 0 +.names rand_choice _n90 +- =rand_choice +# req = 1 +.names req$rand_choice_n91$true +1 +# state = 1 +.mv state$rand_choice_n92$true 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_n92$true +REQ +# if/else (rand_choice ) +.names req$rand_choice_n91$true req rand_choice req$rand_choice$raw_n97 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$rand_choice$raw_n99 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_n92$true state rand_choice state$rand_choice$raw_n99 +- - 0 =state +- - 1 =state$rand_choice_n92$true +.mv _n9c 3 NO_REQ REQ HAVE_TOKEN +.names _n9c +REQ +.names state _n9c _n9b +.def 0 +- =state 1 +.names _n9b _n9a +1 1 +0 0 +.names ack _n9d +- =ack +# state = 2 +.mv state$ack_n9e$true 3 NO_REQ REQ HAVE_TOKEN +.names state$ack_n9e$true +HAVE_TOKEN +# if/else (ack ) +.mv state$ack$raw_na1 3 NO_REQ REQ HAVE_TOKEN +.names state$ack_n9e$true state ack state$ack$raw_na1 +- - 0 =state +- - 1 =state$ack_n9e$true +.mv _na4 3 NO_REQ REQ HAVE_TOKEN +.names _na4 +HAVE_TOKEN +.names state _na4 _na3 +.def 0 +- =state 1 +.names _na3 _na2 +1 1 +0 0 +.names rand_choice _na5 +- =rand_choice +# req = 0 +.names req$rand_choice_na6$true +0 +# state = 0 +.mv state$rand_choice_na7$true 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_na7$true +NO_REQ +# if/else (rand_choice ) +.names req$rand_choice_na6$true req rand_choice req$rand_choice$raw_nac +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$rand_choice$raw_nae 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice_na7$true state rand_choice state$rand_choice$raw_nae +- - 0 =state +- - 1 =state$rand_choice_na7$true +# case (state ) +.names req$rand_choice$raw_nac req _na2 req$_na2$raw_nb3 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_na2$raw_nb5 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice$raw_nae state _na2 state$_na2$raw_nb5 +- - 0 =state +- - 1 =state$rand_choice$raw_nae +.mv state$_n9a$raw_nb6 3 NO_REQ REQ HAVE_TOKEN +.names state$ack$raw_na1 state$_na2$raw_nb5 _n9a state$_n9a$raw_nb6 +- - 0 =state$_na2$raw_nb5 +- - 1 =state$ack$raw_na1 +.names req req$_na2$raw_nb3 _n9a req$_n9a$raw_nb9 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names req$rand_choice$raw_n97 req$_n9a$raw_nb9 _n8d req$_n8d$raw_nbc +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv state$_n8d$raw_nbe 3 NO_REQ REQ HAVE_TOKEN +.names state$rand_choice$raw_n99 state$_n9a$raw_nb6 _n8d state$_n8d$raw_nbe +- - 0 =state$_n9a$raw_nb6 +- - 1 =state$rand_choice$raw_n99 +# conflict arbitrators +.names _n8d _n90 _n9a _na2 _na5 _nc5 +.def 0 + 1 1 - - - 1 + 0 - 0 1 1 1 +.names _nc5 req$_n8d$raw_nbc req _nc6 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n8d _n90 _n9a _n9d _na2 _na5 _nc7 +.def 0 + 1 1 - - - - 1 + 0 - 1 1 - - 1 + 0 - 0 - 1 1 1 +.mv _nc8 3 NO_REQ REQ HAVE_TOKEN +.names _nc7 state$_n8d$raw_nbe state _nc8 +1 - - =state$_n8d$raw_nbe +0 - - =state +# non-blocking assignments +# latches +.r req$raw_n89 req +0 0 +1 1 +.latch _nc6 req +.r state$raw_n8a state +- =state$raw_n8a +.latch _nc8 state +# quasi-continuous assignment +.end + + +.model observer +# I/O ports +.inputs req +.inputs ack + +.mv state 3 IDLE BAD GOOD +# state = 0 +.mv state$raw_ncb 3 IDLE BAD GOOD +.names state$raw_ncb +IDLE +# non-blocking assignments for initial +# assign rand_choice = $NDset ( 0,1 ) +.names rand_choice +0 +1 +.mv _nd0 3 IDLE BAD GOOD +.names _nd0 +IDLE +.names state _nd0 _ncf +.def 0 +- =state 1 +.names _ncf _nce +1 1 +0 0 +# req && rand_choice +.names req rand_choice _nd1 +.def 0 +1 1 1 +.names _nd1 _nd2 +- =_nd1 +# state = 1 +.mv state$_nd1_nd3$true 3 IDLE BAD GOOD +.names state$_nd1_nd3$true +BAD +# if/else (req && rand_choice ) +.mv state$_nd1$raw_nd6 3 IDLE BAD GOOD +.names state$_nd1_nd3$true state _nd1 state$_nd1$raw_nd6 +- - 0 =state +- - 1 =state$_nd1_nd3$true +.mv _nd9 3 IDLE BAD GOOD +.names _nd9 +BAD +.names state _nd9 _nd8 +.def 0 +- =state 1 +.names _nd8 _nd7 +1 1 +0 0 +.names ack _nda +- =ack +# state = 2 +.mv state$ack_ndb$true 3 IDLE BAD GOOD +.names state$ack_ndb$true +GOOD +# if/else (ack ) +.mv state$ack$raw_nde 3 IDLE BAD GOOD +.names state$ack_ndb$true state ack state$ack$raw_nde +- - 0 =state +- - 1 =state$ack_ndb$true +# case (state ) +.mv state$_nd7$raw_ne1 3 IDLE BAD GOOD +.names state$ack$raw_nde state _nd7 state$_nd7$raw_ne1 +- - 0 =state +- - 1 =state$ack$raw_nde +.mv state$_nce$raw_ne2 3 IDLE BAD GOOD +.names state$_nd1$raw_nd6 state$_nd7$raw_ne1 _nce state$_nce$raw_ne2 +- - 0 =state$_nd7$raw_ne1 +- - 1 =state$_nd1$raw_nd6 +# conflict arbitrators +.names _nce _nd2 _nd7 _nda _ne6 +.def 0 + 1 1 - - 1 + 0 - 1 1 1 +.mv _ne7 3 IDLE BAD GOOD +.names _ne6 state$_nce$raw_ne2 state _ne7 +1 - - =state$_nce$raw_ne2 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_ncb state +- =state$raw_ncb +.latch _ne7 state +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/arbiter/arbiter_le.v =================================================================== --- vis_dev/vis-2.1/examples/arbiter/arbiter_le.v (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/arbiter_le.v (revision 11) @@ -0,0 +1,151 @@ +typedef enum {A, B, C, X} selection; +typedef enum {IDLE, READY, BUSY} controller_state; +typedef enum {NO_REQ, REQ, HAVE_TOKEN} client_state; + +module main(clk); +input clk; +output ackA, ackB, ackC; + +selection wire sel; +wire active; + +assign active = pass_tokenA || pass_tokenB || pass_tokenC; + +controller controllerA(clk, reqA, ackA, sel, pass_tokenA, A); +controller controllerB(clk, reqB, ackB, sel, pass_tokenB, B); +controller controllerC(clk, reqC, ackC, sel, pass_tokenC, C); +arbiter arbiter(clk, sel, active); + +client clientA(clk, reqA, ackA); +client clientB(clk, reqB, ackB); +client clientC(clk, reqC, ackC); + +observer observer(clk, reqA, ackA); + +endmodule + +module controller(clk, req, ack, sel, pass_token, id); +input clk, req, sel, id; +output ack, pass_token; + +selection wire sel, id; +reg ack, pass_token; +controller_state reg state; + +initial state = IDLE; +initial ack = 0; +initial pass_token = 1; + +wire is_selected; +assign is_selected = (sel == id); + +always @(posedge clk) begin + case(state) + IDLE: + if (is_selected) + if (req) + begin + state = READY; + pass_token = 0; /* dropping off this line causes a safety bug */ + end + else + pass_token = 1; + else + pass_token = 0; + READY: + begin + state = BUSY; + ack = 1; + end + BUSY: + if (!req) + begin + state = IDLE; + ack = 0; + pass_token = 1; + end + endcase +end +endmodule + +module arbiter(clk, sel, active); +input clk, active; +output sel; + +selection wire sel; +selection reg state; + +initial state = A; + +assign sel = active ? state: X; + +always @(posedge clk) begin + if (active) + case(state) + A: + state = B; + B: + state = C; + C: + state = A; + endcase +end +endmodule + +module client(clk, req, ack); +input clk, ack; +output req; + +reg req; +client_state reg state; + +wire rand_choice; + +initial req = 0; +initial state = NO_REQ; + +assign rand_choice = $ND(0,1); + +always @(posedge clk) begin + case(state) + NO_REQ: + if (rand_choice) + begin + req = 1; + state = REQ; + end + REQ: + if (ack) + state = HAVE_TOKEN; + HAVE_TOKEN: + if (rand_choice) + begin + req = 0; + state = NO_REQ; + end + endcase +end +endmodule + +typedef enum {IDLE, BAD, GOOD} observer_state; + +module observer(clk, req, ack); +input clk, req, ack; + +observer_state reg state; +initial state = IDLE; + +wire rand_choice; +assign rand_choice = $ND(0,1); + +always @(posedge clk) begin + case(state) + IDLE: + if (req && rand_choice) + state = BAD; + BAD: + if (ack) + state = GOOD; + endcase +end +endmodule Index: vis_dev/vis-2.1/examples/arbiter/check_result =================================================================== --- vis_dev/vis-2.1/examples/arbiter/check_result (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/check_result (revision 11) @@ -0,0 +1,4 @@ +# BMC: no counterexample found of length up to 5 +# BMC: formula failed +# BMC: formula failed +# BMC: formula failed Index: vis_dev/vis-2.1/examples/arbiter/check_script =================================================================== --- vis_dev/vis-2.1/examples/arbiter/check_script (revision 11) +++ vis_dev/vis-2.1/examples/arbiter/check_script (revision 11) @@ -0,0 +1,6 @@ +read_blif_mv arbiter.mv +flatten_hierarchy +build_partition_maigs +bounded_model_check -m1 -k5 -v1 arbiter.ltl +time +quit -s Index: vis_dev/vis-2.1/examples/bpb/README =================================================================== --- vis_dev/vis-2.1/examples/bpb/README (revision 11) +++ vis_dev/vis-2.1/examples/bpb/README (revision 11) @@ -0,0 +1,6 @@ +$Id: README,v 1.3 1998/12/09 18:01:27 fabio Exp $ + +This directory contains a simplified model of a branch prediction +buffer. The VIS script runs reachability analysis. + +Author: Srilatha Manne Index: vis_dev/vis-2.1/examples/bpb/bpb.mv =================================================================== --- vis_dev/vis-2.1/examples/bpb/bpb.mv (revision 11) +++ vis_dev/vis-2.1/examples/bpb/bpb.mv (revision 11) @@ -0,0 +1,5242 @@ +# vl2mv btbforvis.v +# version: 0.2 +# date: 14:40:38 11/27/96 (MST) +.model branchPredictionBuffer +# I/O ports +.inputs buffer_offset<0> buffer_offset<1> +.inputs inst_addr<0> inst_addr<1> +.inputs stall +.inputs branch_result +.outputs prediction<0> prediction<1> prediction<2> prediction<3> +.inputs update +.inputs buffer_addr<0> buffer_addr<1> +# state_bank0 [0] = 'b01 +.names _n2<0> +0 +.names _n2<1> +0 +.names _n3<0> +0 +.names _n3<1> +0 +.names _n3<0> _n2<0> _n5<0> +.def 0 +0 1 1 +1 0 1 +.names _n3<1> _n2<1> _n5<1> +.def 0 +0 1 1 +1 0 1 +.names _n5<0> _n5<1> _n6 +.def 1 +0 0 0 +.names _n6 _n4 +0 1 +1 0 +.names _n7<0> +0 +.names _n7<1> +0 +.names _n1<0> _n7<0> _n4 state_bank0$raw_n0<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1<1> _n7<1> _n4 state_bank0$raw_n0<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _na<0> +1 +.names _na<1> +0 +.names _na<0> _n2<0> _nc<0> +.def 0 +0 1 1 +1 0 1 +.names _na<1> _n2<1> _nc<1> +.def 0 +0 1 1 +1 0 1 +.names _nc<0> _nc<1> _nd +.def 1 +0 0 0 +.names _nd _nb +0 1 +1 0 +.names _ne<0> +0 +.names _ne<1> +0 +.names _n1<0> _ne<0> _nb state_bank0$raw_n0<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1<1> _ne<1> _nb state_bank0$raw_n0<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n11<0> +0 +.names _n11<1> +1 +.names _n11<0> _n2<0> _n13<0> +.def 0 +0 1 1 +1 0 1 +.names _n11<1> _n2<1> _n13<1> +.def 0 +0 1 1 +1 0 1 +.names _n13<0> _n13<1> _n14 +.def 1 +0 0 0 +.names _n14 _n12 +0 1 +1 0 +.names _n15<0> +0 +.names _n15<1> +0 +.names _n1<0> _n15<0> _n12 state_bank0$raw_n0<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1<1> _n15<1> _n12 state_bank0$raw_n0<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n18<0> +1 +.names _n18<1> +1 +.names _n18<0> _n2<0> _n1a<0> +.def 0 +0 1 1 +1 0 1 +.names _n18<1> _n2<1> _n1a<1> +.def 0 +0 1 1 +1 0 1 +.names _n1a<0> _n1a<1> _n1b +.def 1 +0 0 0 +.names _n1b _n19 +0 1 +1 0 +.names _n1c<0> +0 +.names _n1c<1> +0 +.names _n1<0> _n1c<0> _n19 state_bank0$raw_n0<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1<1> _n1c<1> _n19 state_bank0$raw_n0<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1f<0> +1 +.names _n1f<1> +0 +.names _n1f<0> _n1<0> +- =_n1f<0> +.names _n1f<1> _n1<1> +- =_n1f<1> +# state_bank1 [0] = 'b01 +.names _n22<0> +0 +.names _n22<1> +0 +.names _n23<0> +0 +.names _n23<1> +0 +.names _n23<0> _n22<0> _n25<0> +.def 0 +0 1 1 +1 0 1 +.names _n23<1> _n22<1> _n25<1> +.def 0 +0 1 1 +1 0 1 +.names _n25<0> _n25<1> _n26 +.def 1 +0 0 0 +.names _n26 _n24 +0 1 +1 0 +.names _n27<0> +0 +.names _n27<1> +0 +.names _n21<0> _n27<0> _n24 state_bank1$raw_n20<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n21<1> _n27<1> _n24 state_bank1$raw_n20<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2a<0> +1 +.names _n2a<1> +0 +.names _n2a<0> _n22<0> _n2c<0> +.def 0 +0 1 1 +1 0 1 +.names _n2a<1> _n22<1> _n2c<1> +.def 0 +0 1 1 +1 0 1 +.names _n2c<0> _n2c<1> _n2d +.def 1 +0 0 0 +.names _n2d _n2b +0 1 +1 0 +.names _n2e<0> +0 +.names _n2e<1> +0 +.names _n21<0> _n2e<0> _n2b state_bank1$raw_n20<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n21<1> _n2e<1> _n2b state_bank1$raw_n20<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n31<0> +0 +.names _n31<1> +1 +.names _n31<0> _n22<0> _n33<0> +.def 0 +0 1 1 +1 0 1 +.names _n31<1> _n22<1> _n33<1> +.def 0 +0 1 1 +1 0 1 +.names _n33<0> _n33<1> _n34 +.def 1 +0 0 0 +.names _n34 _n32 +0 1 +1 0 +.names _n35<0> +0 +.names _n35<1> +0 +.names _n21<0> _n35<0> _n32 state_bank1$raw_n20<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n21<1> _n35<1> _n32 state_bank1$raw_n20<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n38<0> +1 +.names _n38<1> +1 +.names _n38<0> _n22<0> _n3a<0> +.def 0 +0 1 1 +1 0 1 +.names _n38<1> _n22<1> _n3a<1> +.def 0 +0 1 1 +1 0 1 +.names _n3a<0> _n3a<1> _n3b +.def 1 +0 0 0 +.names _n3b _n39 +0 1 +1 0 +.names _n3c<0> +0 +.names _n3c<1> +0 +.names _n21<0> _n3c<0> _n39 state_bank1$raw_n20<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n21<1> _n3c<1> _n39 state_bank1$raw_n20<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n3f<0> +1 +.names _n3f<1> +0 +.names _n3f<0> _n21<0> +- =_n3f<0> +.names _n3f<1> _n21<1> +- =_n3f<1> +# state_bank2 [0] = 'b01 +.names _n42<0> +0 +.names _n42<1> +0 +.names _n43<0> +0 +.names _n43<1> +0 +.names _n43<0> _n42<0> _n45<0> +.def 0 +0 1 1 +1 0 1 +.names _n43<1> _n42<1> _n45<1> +.def 0 +0 1 1 +1 0 1 +.names _n45<0> _n45<1> _n46 +.def 1 +0 0 0 +.names _n46 _n44 +0 1 +1 0 +.names _n47<0> +0 +.names _n47<1> +0 +.names _n41<0> _n47<0> _n44 state_bank2$raw_n40<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n41<1> _n47<1> _n44 state_bank2$raw_n40<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n4a<0> +1 +.names _n4a<1> +0 +.names _n4a<0> _n42<0> _n4c<0> +.def 0 +0 1 1 +1 0 1 +.names _n4a<1> _n42<1> _n4c<1> +.def 0 +0 1 1 +1 0 1 +.names _n4c<0> _n4c<1> _n4d +.def 1 +0 0 0 +.names _n4d _n4b +0 1 +1 0 +.names _n4e<0> +0 +.names _n4e<1> +0 +.names _n41<0> _n4e<0> _n4b state_bank2$raw_n40<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n41<1> _n4e<1> _n4b state_bank2$raw_n40<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n51<0> +0 +.names _n51<1> +1 +.names _n51<0> _n42<0> _n53<0> +.def 0 +0 1 1 +1 0 1 +.names _n51<1> _n42<1> _n53<1> +.def 0 +0 1 1 +1 0 1 +.names _n53<0> _n53<1> _n54 +.def 1 +0 0 0 +.names _n54 _n52 +0 1 +1 0 +.names _n55<0> +0 +.names _n55<1> +0 +.names _n41<0> _n55<0> _n52 state_bank2$raw_n40<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n41<1> _n55<1> _n52 state_bank2$raw_n40<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n58<0> +1 +.names _n58<1> +1 +.names _n58<0> _n42<0> _n5a<0> +.def 0 +0 1 1 +1 0 1 +.names _n58<1> _n42<1> _n5a<1> +.def 0 +0 1 1 +1 0 1 +.names _n5a<0> _n5a<1> _n5b +.def 1 +0 0 0 +.names _n5b _n59 +0 1 +1 0 +.names _n5c<0> +0 +.names _n5c<1> +0 +.names _n41<0> _n5c<0> _n59 state_bank2$raw_n40<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n41<1> _n5c<1> _n59 state_bank2$raw_n40<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5f<0> +1 +.names _n5f<1> +0 +.names _n5f<0> _n41<0> +- =_n5f<0> +.names _n5f<1> _n41<1> +- =_n5f<1> +# state_bank3 [0] = 'b01 +.names _n62<0> +0 +.names _n62<1> +0 +.names _n63<0> +0 +.names _n63<1> +0 +.names _n63<0> _n62<0> _n65<0> +.def 0 +0 1 1 +1 0 1 +.names _n63<1> _n62<1> _n65<1> +.def 0 +0 1 1 +1 0 1 +.names _n65<0> _n65<1> _n66 +.def 1 +0 0 0 +.names _n66 _n64 +0 1 +1 0 +.names _n67<0> +0 +.names _n67<1> +0 +.names _n61<0> _n67<0> _n64 state_bank3$raw_n60<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n61<1> _n67<1> _n64 state_bank3$raw_n60<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n6a<0> +1 +.names _n6a<1> +0 +.names _n6a<0> _n62<0> _n6c<0> +.def 0 +0 1 1 +1 0 1 +.names _n6a<1> _n62<1> _n6c<1> +.def 0 +0 1 1 +1 0 1 +.names _n6c<0> _n6c<1> _n6d +.def 1 +0 0 0 +.names _n6d _n6b +0 1 +1 0 +.names _n6e<0> +0 +.names _n6e<1> +0 +.names _n61<0> _n6e<0> _n6b state_bank3$raw_n60<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n61<1> _n6e<1> _n6b state_bank3$raw_n60<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n71<0> +0 +.names _n71<1> +1 +.names _n71<0> _n62<0> _n73<0> +.def 0 +0 1 1 +1 0 1 +.names _n71<1> _n62<1> _n73<1> +.def 0 +0 1 1 +1 0 1 +.names _n73<0> _n73<1> _n74 +.def 1 +0 0 0 +.names _n74 _n72 +0 1 +1 0 +.names _n75<0> +0 +.names _n75<1> +0 +.names _n61<0> _n75<0> _n72 state_bank3$raw_n60<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n61<1> _n75<1> _n72 state_bank3$raw_n60<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n78<0> +1 +.names _n78<1> +1 +.names _n78<0> _n62<0> _n7a<0> +.def 0 +0 1 1 +1 0 1 +.names _n78<1> _n62<1> _n7a<1> +.def 0 +0 1 1 +1 0 1 +.names _n7a<0> _n7a<1> _n7b +.def 1 +0 0 0 +.names _n7b _n79 +0 1 +1 0 +.names _n7c<0> +0 +.names _n7c<1> +0 +.names _n61<0> _n7c<0> _n79 state_bank3$raw_n60<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n61<1> _n7c<1> _n79 state_bank3$raw_n60<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n7f<0> +1 +.names _n7f<1> +0 +.names _n7f<0> _n61<0> +- =_n7f<0> +.names _n7f<1> _n61<1> +- =_n7f<1> +# state_bank0 [1] = 'b01 +.names _n82<0> +1 +.names _n82<1> +0 +.names _n83<0> +0 +.names _n83<1> +0 +.names _n83<0> _n82<0> _n85<0> +.def 0 +0 1 1 +1 0 1 +.names _n83<1> _n82<1> _n85<1> +.def 0 +0 1 1 +1 0 1 +.names _n85<0> _n85<1> _n86 +.def 1 +0 0 0 +.names _n86 _n84 +0 1 +1 0 +.names _n81<0> state_bank0$raw_n0<*0*><0> _n84 state_bank0$raw_n80<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n81<1> state_bank0$raw_n0<*0*><1> _n84 state_bank0$raw_n80<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n89<0> +1 +.names _n89<1> +0 +.names _n89<0> _n82<0> _n8b<0> +.def 0 +0 1 1 +1 0 1 +.names _n89<1> _n82<1> _n8b<1> +.def 0 +0 1 1 +1 0 1 +.names _n8b<0> _n8b<1> _n8c +.def 1 +0 0 0 +.names _n8c _n8a +0 1 +1 0 +.names _n81<0> state_bank0$raw_n0<*1*><0> _n8a state_bank0$raw_n80<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n81<1> state_bank0$raw_n0<*1*><1> _n8a state_bank0$raw_n80<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n8f<0> +0 +.names _n8f<1> +1 +.names _n8f<0> _n82<0> _n91<0> +.def 0 +0 1 1 +1 0 1 +.names _n8f<1> _n82<1> _n91<1> +.def 0 +0 1 1 +1 0 1 +.names _n91<0> _n91<1> _n92 +.def 1 +0 0 0 +.names _n92 _n90 +0 1 +1 0 +.names _n81<0> state_bank0$raw_n0<*2*><0> _n90 state_bank0$raw_n80<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n81<1> state_bank0$raw_n0<*2*><1> _n90 state_bank0$raw_n80<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n95<0> +1 +.names _n95<1> +1 +.names _n95<0> _n82<0> _n97<0> +.def 0 +0 1 1 +1 0 1 +.names _n95<1> _n82<1> _n97<1> +.def 0 +0 1 1 +1 0 1 +.names _n97<0> _n97<1> _n98 +.def 1 +0 0 0 +.names _n98 _n96 +0 1 +1 0 +.names _n81<0> state_bank0$raw_n0<*3*><0> _n96 state_bank0$raw_n80<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n81<1> state_bank0$raw_n0<*3*><1> _n96 state_bank0$raw_n80<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n9b<0> +1 +.names _n9b<1> +0 +.names _n9b<0> _n81<0> +- =_n9b<0> +.names _n9b<1> _n81<1> +- =_n9b<1> +# state_bank1 [1] = 'b01 +.names _n9e<0> +1 +.names _n9e<1> +0 +.names _n9f<0> +0 +.names _n9f<1> +0 +.names _n9f<0> _n9e<0> _na1<0> +.def 0 +0 1 1 +1 0 1 +.names _n9f<1> _n9e<1> _na1<1> +.def 0 +0 1 1 +1 0 1 +.names _na1<0> _na1<1> _na2 +.def 1 +0 0 0 +.names _na2 _na0 +0 1 +1 0 +.names _n9d<0> state_bank1$raw_n20<*0*><0> _na0 state_bank1$raw_n9c<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n9d<1> state_bank1$raw_n20<*0*><1> _na0 state_bank1$raw_n9c<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _na5<0> +1 +.names _na5<1> +0 +.names _na5<0> _n9e<0> _na7<0> +.def 0 +0 1 1 +1 0 1 +.names _na5<1> _n9e<1> _na7<1> +.def 0 +0 1 1 +1 0 1 +.names _na7<0> _na7<1> _na8 +.def 1 +0 0 0 +.names _na8 _na6 +0 1 +1 0 +.names _n9d<0> state_bank1$raw_n20<*1*><0> _na6 state_bank1$raw_n9c<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n9d<1> state_bank1$raw_n20<*1*><1> _na6 state_bank1$raw_n9c<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nab<0> +0 +.names _nab<1> +1 +.names _nab<0> _n9e<0> _nad<0> +.def 0 +0 1 1 +1 0 1 +.names _nab<1> _n9e<1> _nad<1> +.def 0 +0 1 1 +1 0 1 +.names _nad<0> _nad<1> _nae +.def 1 +0 0 0 +.names _nae _nac +0 1 +1 0 +.names _n9d<0> state_bank1$raw_n20<*2*><0> _nac state_bank1$raw_n9c<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n9d<1> state_bank1$raw_n20<*2*><1> _nac state_bank1$raw_n9c<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nb1<0> +1 +.names _nb1<1> +1 +.names _nb1<0> _n9e<0> _nb3<0> +.def 0 +0 1 1 +1 0 1 +.names _nb1<1> _n9e<1> _nb3<1> +.def 0 +0 1 1 +1 0 1 +.names _nb3<0> _nb3<1> _nb4 +.def 1 +0 0 0 +.names _nb4 _nb2 +0 1 +1 0 +.names _n9d<0> state_bank1$raw_n20<*3*><0> _nb2 state_bank1$raw_n9c<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n9d<1> state_bank1$raw_n20<*3*><1> _nb2 state_bank1$raw_n9c<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nb7<0> +1 +.names _nb7<1> +0 +.names _nb7<0> _n9d<0> +- =_nb7<0> +.names _nb7<1> _n9d<1> +- =_nb7<1> +# state_bank2 [1] = 'b01 +.names _nba<0> +1 +.names _nba<1> +0 +.names _nbb<0> +0 +.names _nbb<1> +0 +.names _nbb<0> _nba<0> _nbd<0> +.def 0 +0 1 1 +1 0 1 +.names _nbb<1> _nba<1> _nbd<1> +.def 0 +0 1 1 +1 0 1 +.names _nbd<0> _nbd<1> _nbe +.def 1 +0 0 0 +.names _nbe _nbc +0 1 +1 0 +.names _nb9<0> state_bank2$raw_n40<*0*><0> _nbc state_bank2$raw_nb8<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nb9<1> state_bank2$raw_n40<*0*><1> _nbc state_bank2$raw_nb8<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nc1<0> +1 +.names _nc1<1> +0 +.names _nc1<0> _nba<0> _nc3<0> +.def 0 +0 1 1 +1 0 1 +.names _nc1<1> _nba<1> _nc3<1> +.def 0 +0 1 1 +1 0 1 +.names _nc3<0> _nc3<1> _nc4 +.def 1 +0 0 0 +.names _nc4 _nc2 +0 1 +1 0 +.names _nb9<0> state_bank2$raw_n40<*1*><0> _nc2 state_bank2$raw_nb8<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nb9<1> state_bank2$raw_n40<*1*><1> _nc2 state_bank2$raw_nb8<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nc7<0> +0 +.names _nc7<1> +1 +.names _nc7<0> _nba<0> _nc9<0> +.def 0 +0 1 1 +1 0 1 +.names _nc7<1> _nba<1> _nc9<1> +.def 0 +0 1 1 +1 0 1 +.names _nc9<0> _nc9<1> _nca +.def 1 +0 0 0 +.names _nca _nc8 +0 1 +1 0 +.names _nb9<0> state_bank2$raw_n40<*2*><0> _nc8 state_bank2$raw_nb8<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nb9<1> state_bank2$raw_n40<*2*><1> _nc8 state_bank2$raw_nb8<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _ncd<0> +1 +.names _ncd<1> +1 +.names _ncd<0> _nba<0> _ncf<0> +.def 0 +0 1 1 +1 0 1 +.names _ncd<1> _nba<1> _ncf<1> +.def 0 +0 1 1 +1 0 1 +.names _ncf<0> _ncf<1> _nd0 +.def 1 +0 0 0 +.names _nd0 _nce +0 1 +1 0 +.names _nb9<0> state_bank2$raw_n40<*3*><0> _nce state_bank2$raw_nb8<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nb9<1> state_bank2$raw_n40<*3*><1> _nce state_bank2$raw_nb8<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nd3<0> +1 +.names _nd3<1> +0 +.names _nd3<0> _nb9<0> +- =_nd3<0> +.names _nd3<1> _nb9<1> +- =_nd3<1> +# state_bank3 [1] = 'b01 +.names _nd6<0> +1 +.names _nd6<1> +0 +.names _nd7<0> +0 +.names _nd7<1> +0 +.names _nd7<0> _nd6<0> _nd9<0> +.def 0 +0 1 1 +1 0 1 +.names _nd7<1> _nd6<1> _nd9<1> +.def 0 +0 1 1 +1 0 1 +.names _nd9<0> _nd9<1> _nda +.def 1 +0 0 0 +.names _nda _nd8 +0 1 +1 0 +.names _nd5<0> state_bank3$raw_n60<*0*><0> _nd8 state_bank3$raw_nd4<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nd5<1> state_bank3$raw_n60<*0*><1> _nd8 state_bank3$raw_nd4<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _ndd<0> +1 +.names _ndd<1> +0 +.names _ndd<0> _nd6<0> _ndf<0> +.def 0 +0 1 1 +1 0 1 +.names _ndd<1> _nd6<1> _ndf<1> +.def 0 +0 1 1 +1 0 1 +.names _ndf<0> _ndf<1> _ne0 +.def 1 +0 0 0 +.names _ne0 _nde +0 1 +1 0 +.names _nd5<0> state_bank3$raw_n60<*1*><0> _nde state_bank3$raw_nd4<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nd5<1> state_bank3$raw_n60<*1*><1> _nde state_bank3$raw_nd4<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _ne3<0> +0 +.names _ne3<1> +1 +.names _ne3<0> _nd6<0> _ne5<0> +.def 0 +0 1 1 +1 0 1 +.names _ne3<1> _nd6<1> _ne5<1> +.def 0 +0 1 1 +1 0 1 +.names _ne5<0> _ne5<1> _ne6 +.def 1 +0 0 0 +.names _ne6 _ne4 +0 1 +1 0 +.names _nd5<0> state_bank3$raw_n60<*2*><0> _ne4 state_bank3$raw_nd4<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nd5<1> state_bank3$raw_n60<*2*><1> _ne4 state_bank3$raw_nd4<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _ne9<0> +1 +.names _ne9<1> +1 +.names _ne9<0> _nd6<0> _neb<0> +.def 0 +0 1 1 +1 0 1 +.names _ne9<1> _nd6<1> _neb<1> +.def 0 +0 1 1 +1 0 1 +.names _neb<0> _neb<1> _nec +.def 1 +0 0 0 +.names _nec _nea +0 1 +1 0 +.names _nd5<0> state_bank3$raw_n60<*3*><0> _nea state_bank3$raw_nd4<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nd5<1> state_bank3$raw_n60<*3*><1> _nea state_bank3$raw_nd4<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nef<0> +1 +.names _nef<1> +0 +.names _nef<0> _nd5<0> +- =_nef<0> +.names _nef<1> _nd5<1> +- =_nef<1> +# state_bank0 [2] = 'b01 +.names _nf2<0> +0 +.names _nf2<1> +1 +.names _nf3<0> +0 +.names _nf3<1> +0 +.names _nf3<0> _nf2<0> _nf5<0> +.def 0 +0 1 1 +1 0 1 +.names _nf3<1> _nf2<1> _nf5<1> +.def 0 +0 1 1 +1 0 1 +.names _nf5<0> _nf5<1> _nf6 +.def 1 +0 0 0 +.names _nf6 _nf4 +0 1 +1 0 +.names _nf1<0> state_bank0$raw_n80<*0*><0> _nf4 state_bank0$raw_nf0<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nf1<1> state_bank0$raw_n80<*0*><1> _nf4 state_bank0$raw_nf0<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nf9<0> +1 +.names _nf9<1> +0 +.names _nf9<0> _nf2<0> _nfb<0> +.def 0 +0 1 1 +1 0 1 +.names _nf9<1> _nf2<1> _nfb<1> +.def 0 +0 1 1 +1 0 1 +.names _nfb<0> _nfb<1> _nfc +.def 1 +0 0 0 +.names _nfc _nfa +0 1 +1 0 +.names _nf1<0> state_bank0$raw_n80<*1*><0> _nfa state_bank0$raw_nf0<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nf1<1> state_bank0$raw_n80<*1*><1> _nfa state_bank0$raw_nf0<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nff<0> +0 +.names _nff<1> +1 +.names _nff<0> _nf2<0> _n101<0> +.def 0 +0 1 1 +1 0 1 +.names _nff<1> _nf2<1> _n101<1> +.def 0 +0 1 1 +1 0 1 +.names _n101<0> _n101<1> _n102 +.def 1 +0 0 0 +.names _n102 _n100 +0 1 +1 0 +.names _nf1<0> state_bank0$raw_n80<*2*><0> _n100 state_bank0$raw_nf0<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nf1<1> state_bank0$raw_n80<*2*><1> _n100 state_bank0$raw_nf0<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n105<0> +1 +.names _n105<1> +1 +.names _n105<0> _nf2<0> _n107<0> +.def 0 +0 1 1 +1 0 1 +.names _n105<1> _nf2<1> _n107<1> +.def 0 +0 1 1 +1 0 1 +.names _n107<0> _n107<1> _n108 +.def 1 +0 0 0 +.names _n108 _n106 +0 1 +1 0 +.names _nf1<0> state_bank0$raw_n80<*3*><0> _n106 state_bank0$raw_nf0<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _nf1<1> state_bank0$raw_n80<*3*><1> _n106 state_bank0$raw_nf0<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n10b<0> +1 +.names _n10b<1> +0 +.names _n10b<0> _nf1<0> +- =_n10b<0> +.names _n10b<1> _nf1<1> +- =_n10b<1> +# state_bank1 [2] = 'b01 +.names _n10e<0> +0 +.names _n10e<1> +1 +.names _n10f<0> +0 +.names _n10f<1> +0 +.names _n10f<0> _n10e<0> _n111<0> +.def 0 +0 1 1 +1 0 1 +.names _n10f<1> _n10e<1> _n111<1> +.def 0 +0 1 1 +1 0 1 +.names _n111<0> _n111<1> _n112 +.def 1 +0 0 0 +.names _n112 _n110 +0 1 +1 0 +.names _n10d<0> state_bank1$raw_n9c<*0*><0> _n110 state_bank1$raw_n10c<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n10d<1> state_bank1$raw_n9c<*0*><1> _n110 state_bank1$raw_n10c<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n115<0> +1 +.names _n115<1> +0 +.names _n115<0> _n10e<0> _n117<0> +.def 0 +0 1 1 +1 0 1 +.names _n115<1> _n10e<1> _n117<1> +.def 0 +0 1 1 +1 0 1 +.names _n117<0> _n117<1> _n118 +.def 1 +0 0 0 +.names _n118 _n116 +0 1 +1 0 +.names _n10d<0> state_bank1$raw_n9c<*1*><0> _n116 state_bank1$raw_n10c<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n10d<1> state_bank1$raw_n9c<*1*><1> _n116 state_bank1$raw_n10c<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n11b<0> +0 +.names _n11b<1> +1 +.names _n11b<0> _n10e<0> _n11d<0> +.def 0 +0 1 1 +1 0 1 +.names _n11b<1> _n10e<1> _n11d<1> +.def 0 +0 1 1 +1 0 1 +.names _n11d<0> _n11d<1> _n11e +.def 1 +0 0 0 +.names _n11e _n11c +0 1 +1 0 +.names _n10d<0> state_bank1$raw_n9c<*2*><0> _n11c state_bank1$raw_n10c<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n10d<1> state_bank1$raw_n9c<*2*><1> _n11c state_bank1$raw_n10c<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n121<0> +1 +.names _n121<1> +1 +.names _n121<0> _n10e<0> _n123<0> +.def 0 +0 1 1 +1 0 1 +.names _n121<1> _n10e<1> _n123<1> +.def 0 +0 1 1 +1 0 1 +.names _n123<0> _n123<1> _n124 +.def 1 +0 0 0 +.names _n124 _n122 +0 1 +1 0 +.names _n10d<0> state_bank1$raw_n9c<*3*><0> _n122 state_bank1$raw_n10c<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n10d<1> state_bank1$raw_n9c<*3*><1> _n122 state_bank1$raw_n10c<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n127<0> +1 +.names _n127<1> +0 +.names _n127<0> _n10d<0> +- =_n127<0> +.names _n127<1> _n10d<1> +- =_n127<1> +# state_bank2 [2] = 'b01 +.names _n12a<0> +0 +.names _n12a<1> +1 +.names _n12b<0> +0 +.names _n12b<1> +0 +.names _n12b<0> _n12a<0> _n12d<0> +.def 0 +0 1 1 +1 0 1 +.names _n12b<1> _n12a<1> _n12d<1> +.def 0 +0 1 1 +1 0 1 +.names _n12d<0> _n12d<1> _n12e +.def 1 +0 0 0 +.names _n12e _n12c +0 1 +1 0 +.names _n129<0> state_bank2$raw_nb8<*0*><0> _n12c state_bank2$raw_n128<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n129<1> state_bank2$raw_nb8<*0*><1> _n12c state_bank2$raw_n128<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n131<0> +1 +.names _n131<1> +0 +.names _n131<0> _n12a<0> _n133<0> +.def 0 +0 1 1 +1 0 1 +.names _n131<1> _n12a<1> _n133<1> +.def 0 +0 1 1 +1 0 1 +.names _n133<0> _n133<1> _n134 +.def 1 +0 0 0 +.names _n134 _n132 +0 1 +1 0 +.names _n129<0> state_bank2$raw_nb8<*1*><0> _n132 state_bank2$raw_n128<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n129<1> state_bank2$raw_nb8<*1*><1> _n132 state_bank2$raw_n128<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n137<0> +0 +.names _n137<1> +1 +.names _n137<0> _n12a<0> _n139<0> +.def 0 +0 1 1 +1 0 1 +.names _n137<1> _n12a<1> _n139<1> +.def 0 +0 1 1 +1 0 1 +.names _n139<0> _n139<1> _n13a +.def 1 +0 0 0 +.names _n13a _n138 +0 1 +1 0 +.names _n129<0> state_bank2$raw_nb8<*2*><0> _n138 state_bank2$raw_n128<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n129<1> state_bank2$raw_nb8<*2*><1> _n138 state_bank2$raw_n128<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n13d<0> +1 +.names _n13d<1> +1 +.names _n13d<0> _n12a<0> _n13f<0> +.def 0 +0 1 1 +1 0 1 +.names _n13d<1> _n12a<1> _n13f<1> +.def 0 +0 1 1 +1 0 1 +.names _n13f<0> _n13f<1> _n140 +.def 1 +0 0 0 +.names _n140 _n13e +0 1 +1 0 +.names _n129<0> state_bank2$raw_nb8<*3*><0> _n13e state_bank2$raw_n128<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n129<1> state_bank2$raw_nb8<*3*><1> _n13e state_bank2$raw_n128<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n143<0> +1 +.names _n143<1> +0 +.names _n143<0> _n129<0> +- =_n143<0> +.names _n143<1> _n129<1> +- =_n143<1> +# state_bank3 [2] = 'b01 +.names _n146<0> +0 +.names _n146<1> +1 +.names _n147<0> +0 +.names _n147<1> +0 +.names _n147<0> _n146<0> _n149<0> +.def 0 +0 1 1 +1 0 1 +.names _n147<1> _n146<1> _n149<1> +.def 0 +0 1 1 +1 0 1 +.names _n149<0> _n149<1> _n14a +.def 1 +0 0 0 +.names _n14a _n148 +0 1 +1 0 +.names _n145<0> state_bank3$raw_nd4<*0*><0> _n148 state_bank3$raw_n144<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n145<1> state_bank3$raw_nd4<*0*><1> _n148 state_bank3$raw_n144<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n14d<0> +1 +.names _n14d<1> +0 +.names _n14d<0> _n146<0> _n14f<0> +.def 0 +0 1 1 +1 0 1 +.names _n14d<1> _n146<1> _n14f<1> +.def 0 +0 1 1 +1 0 1 +.names _n14f<0> _n14f<1> _n150 +.def 1 +0 0 0 +.names _n150 _n14e +0 1 +1 0 +.names _n145<0> state_bank3$raw_nd4<*1*><0> _n14e state_bank3$raw_n144<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n145<1> state_bank3$raw_nd4<*1*><1> _n14e state_bank3$raw_n144<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n153<0> +0 +.names _n153<1> +1 +.names _n153<0> _n146<0> _n155<0> +.def 0 +0 1 1 +1 0 1 +.names _n153<1> _n146<1> _n155<1> +.def 0 +0 1 1 +1 0 1 +.names _n155<0> _n155<1> _n156 +.def 1 +0 0 0 +.names _n156 _n154 +0 1 +1 0 +.names _n145<0> state_bank3$raw_nd4<*2*><0> _n154 state_bank3$raw_n144<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n145<1> state_bank3$raw_nd4<*2*><1> _n154 state_bank3$raw_n144<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n159<0> +1 +.names _n159<1> +1 +.names _n159<0> _n146<0> _n15b<0> +.def 0 +0 1 1 +1 0 1 +.names _n159<1> _n146<1> _n15b<1> +.def 0 +0 1 1 +1 0 1 +.names _n15b<0> _n15b<1> _n15c +.def 1 +0 0 0 +.names _n15c _n15a +0 1 +1 0 +.names _n145<0> state_bank3$raw_nd4<*3*><0> _n15a state_bank3$raw_n144<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n145<1> state_bank3$raw_nd4<*3*><1> _n15a state_bank3$raw_n144<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n15f<0> +1 +.names _n15f<1> +0 +.names _n15f<0> _n145<0> +- =_n15f<0> +.names _n15f<1> _n145<1> +- =_n15f<1> +# state_bank0 [3] = 'b01 +.names _n162<0> +1 +.names _n162<1> +1 +.names _n163<0> +0 +.names _n163<1> +0 +.names _n163<0> _n162<0> _n165<0> +.def 0 +0 1 1 +1 0 1 +.names _n163<1> _n162<1> _n165<1> +.def 0 +0 1 1 +1 0 1 +.names _n165<0> _n165<1> _n166 +.def 1 +0 0 0 +.names _n166 _n164 +0 1 +1 0 +.names _n161<0> state_bank0$raw_nf0<*0*><0> _n164 state_bank0$raw_n160<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n161<1> state_bank0$raw_nf0<*0*><1> _n164 state_bank0$raw_n160<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n169<0> +1 +.names _n169<1> +0 +.names _n169<0> _n162<0> _n16b<0> +.def 0 +0 1 1 +1 0 1 +.names _n169<1> _n162<1> _n16b<1> +.def 0 +0 1 1 +1 0 1 +.names _n16b<0> _n16b<1> _n16c +.def 1 +0 0 0 +.names _n16c _n16a +0 1 +1 0 +.names _n161<0> state_bank0$raw_nf0<*1*><0> _n16a state_bank0$raw_n160<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n161<1> state_bank0$raw_nf0<*1*><1> _n16a state_bank0$raw_n160<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n16f<0> +0 +.names _n16f<1> +1 +.names _n16f<0> _n162<0> _n171<0> +.def 0 +0 1 1 +1 0 1 +.names _n16f<1> _n162<1> _n171<1> +.def 0 +0 1 1 +1 0 1 +.names _n171<0> _n171<1> _n172 +.def 1 +0 0 0 +.names _n172 _n170 +0 1 +1 0 +.names _n161<0> state_bank0$raw_nf0<*2*><0> _n170 state_bank0$raw_n160<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n161<1> state_bank0$raw_nf0<*2*><1> _n170 state_bank0$raw_n160<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n175<0> +1 +.names _n175<1> +1 +.names _n175<0> _n162<0> _n177<0> +.def 0 +0 1 1 +1 0 1 +.names _n175<1> _n162<1> _n177<1> +.def 0 +0 1 1 +1 0 1 +.names _n177<0> _n177<1> _n178 +.def 1 +0 0 0 +.names _n178 _n176 +0 1 +1 0 +.names _n161<0> state_bank0$raw_nf0<*3*><0> _n176 state_bank0$raw_n160<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n161<1> state_bank0$raw_nf0<*3*><1> _n176 state_bank0$raw_n160<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n17b<0> +1 +.names _n17b<1> +0 +.names _n17b<0> _n161<0> +- =_n17b<0> +.names _n17b<1> _n161<1> +- =_n17b<1> +# state_bank1 [3] = 'b01 +.names _n17e<0> +1 +.names _n17e<1> +1 +.names _n17f<0> +0 +.names _n17f<1> +0 +.names _n17f<0> _n17e<0> _n181<0> +.def 0 +0 1 1 +1 0 1 +.names _n17f<1> _n17e<1> _n181<1> +.def 0 +0 1 1 +1 0 1 +.names _n181<0> _n181<1> _n182 +.def 1 +0 0 0 +.names _n182 _n180 +0 1 +1 0 +.names _n17d<0> state_bank1$raw_n10c<*0*><0> _n180 state_bank1$raw_n17c<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n17d<1> state_bank1$raw_n10c<*0*><1> _n180 state_bank1$raw_n17c<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n185<0> +1 +.names _n185<1> +0 +.names _n185<0> _n17e<0> _n187<0> +.def 0 +0 1 1 +1 0 1 +.names _n185<1> _n17e<1> _n187<1> +.def 0 +0 1 1 +1 0 1 +.names _n187<0> _n187<1> _n188 +.def 1 +0 0 0 +.names _n188 _n186 +0 1 +1 0 +.names _n17d<0> state_bank1$raw_n10c<*1*><0> _n186 state_bank1$raw_n17c<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n17d<1> state_bank1$raw_n10c<*1*><1> _n186 state_bank1$raw_n17c<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n18b<0> +0 +.names _n18b<1> +1 +.names _n18b<0> _n17e<0> _n18d<0> +.def 0 +0 1 1 +1 0 1 +.names _n18b<1> _n17e<1> _n18d<1> +.def 0 +0 1 1 +1 0 1 +.names _n18d<0> _n18d<1> _n18e +.def 1 +0 0 0 +.names _n18e _n18c +0 1 +1 0 +.names _n17d<0> state_bank1$raw_n10c<*2*><0> _n18c state_bank1$raw_n17c<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n17d<1> state_bank1$raw_n10c<*2*><1> _n18c state_bank1$raw_n17c<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n191<0> +1 +.names _n191<1> +1 +.names _n191<0> _n17e<0> _n193<0> +.def 0 +0 1 1 +1 0 1 +.names _n191<1> _n17e<1> _n193<1> +.def 0 +0 1 1 +1 0 1 +.names _n193<0> _n193<1> _n194 +.def 1 +0 0 0 +.names _n194 _n192 +0 1 +1 0 +.names _n17d<0> state_bank1$raw_n10c<*3*><0> _n192 state_bank1$raw_n17c<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n17d<1> state_bank1$raw_n10c<*3*><1> _n192 state_bank1$raw_n17c<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n197<0> +1 +.names _n197<1> +0 +.names _n197<0> _n17d<0> +- =_n197<0> +.names _n197<1> _n17d<1> +- =_n197<1> +# state_bank2 [3] = 'b01 +.names _n19a<0> +1 +.names _n19a<1> +1 +.names _n19b<0> +0 +.names _n19b<1> +0 +.names _n19b<0> _n19a<0> _n19d<0> +.def 0 +0 1 1 +1 0 1 +.names _n19b<1> _n19a<1> _n19d<1> +.def 0 +0 1 1 +1 0 1 +.names _n19d<0> _n19d<1> _n19e +.def 1 +0 0 0 +.names _n19e _n19c +0 1 +1 0 +.names _n199<0> state_bank2$raw_n128<*0*><0> _n19c state_bank2$raw_n198<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n199<1> state_bank2$raw_n128<*0*><1> _n19c state_bank2$raw_n198<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1a1<0> +1 +.names _n1a1<1> +0 +.names _n1a1<0> _n19a<0> _n1a3<0> +.def 0 +0 1 1 +1 0 1 +.names _n1a1<1> _n19a<1> _n1a3<1> +.def 0 +0 1 1 +1 0 1 +.names _n1a3<0> _n1a3<1> _n1a4 +.def 1 +0 0 0 +.names _n1a4 _n1a2 +0 1 +1 0 +.names _n199<0> state_bank2$raw_n128<*1*><0> _n1a2 state_bank2$raw_n198<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n199<1> state_bank2$raw_n128<*1*><1> _n1a2 state_bank2$raw_n198<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1a7<0> +0 +.names _n1a7<1> +1 +.names _n1a7<0> _n19a<0> _n1a9<0> +.def 0 +0 1 1 +1 0 1 +.names _n1a7<1> _n19a<1> _n1a9<1> +.def 0 +0 1 1 +1 0 1 +.names _n1a9<0> _n1a9<1> _n1aa +.def 1 +0 0 0 +.names _n1aa _n1a8 +0 1 +1 0 +.names _n199<0> state_bank2$raw_n128<*2*><0> _n1a8 state_bank2$raw_n198<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n199<1> state_bank2$raw_n128<*2*><1> _n1a8 state_bank2$raw_n198<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1ad<0> +1 +.names _n1ad<1> +1 +.names _n1ad<0> _n19a<0> _n1af<0> +.def 0 +0 1 1 +1 0 1 +.names _n1ad<1> _n19a<1> _n1af<1> +.def 0 +0 1 1 +1 0 1 +.names _n1af<0> _n1af<1> _n1b0 +.def 1 +0 0 0 +.names _n1b0 _n1ae +0 1 +1 0 +.names _n199<0> state_bank2$raw_n128<*3*><0> _n1ae state_bank2$raw_n198<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n199<1> state_bank2$raw_n128<*3*><1> _n1ae state_bank2$raw_n198<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1b3<0> +1 +.names _n1b3<1> +0 +.names _n1b3<0> _n199<0> +- =_n1b3<0> +.names _n1b3<1> _n199<1> +- =_n1b3<1> +# state_bank3 [3] = 'b01 +.names _n1b6<0> +1 +.names _n1b6<1> +1 +.names _n1b7<0> +0 +.names _n1b7<1> +0 +.names _n1b7<0> _n1b6<0> _n1b9<0> +.def 0 +0 1 1 +1 0 1 +.names _n1b7<1> _n1b6<1> _n1b9<1> +.def 0 +0 1 1 +1 0 1 +.names _n1b9<0> _n1b9<1> _n1ba +.def 1 +0 0 0 +.names _n1ba _n1b8 +0 1 +1 0 +.names _n1b5<0> state_bank3$raw_n144<*0*><0> _n1b8 state_bank3$raw_n1b4<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1b5<1> state_bank3$raw_n144<*0*><1> _n1b8 state_bank3$raw_n1b4<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1bd<0> +1 +.names _n1bd<1> +0 +.names _n1bd<0> _n1b6<0> _n1bf<0> +.def 0 +0 1 1 +1 0 1 +.names _n1bd<1> _n1b6<1> _n1bf<1> +.def 0 +0 1 1 +1 0 1 +.names _n1bf<0> _n1bf<1> _n1c0 +.def 1 +0 0 0 +.names _n1c0 _n1be +0 1 +1 0 +.names _n1b5<0> state_bank3$raw_n144<*1*><0> _n1be state_bank3$raw_n1b4<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1b5<1> state_bank3$raw_n144<*1*><1> _n1be state_bank3$raw_n1b4<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1c3<0> +0 +.names _n1c3<1> +1 +.names _n1c3<0> _n1b6<0> _n1c5<0> +.def 0 +0 1 1 +1 0 1 +.names _n1c3<1> _n1b6<1> _n1c5<1> +.def 0 +0 1 1 +1 0 1 +.names _n1c5<0> _n1c5<1> _n1c6 +.def 1 +0 0 0 +.names _n1c6 _n1c4 +0 1 +1 0 +.names _n1b5<0> state_bank3$raw_n144<*2*><0> _n1c4 state_bank3$raw_n1b4<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1b5<1> state_bank3$raw_n144<*2*><1> _n1c4 state_bank3$raw_n1b4<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1c9<0> +1 +.names _n1c9<1> +1 +.names _n1c9<0> _n1b6<0> _n1cb<0> +.def 0 +0 1 1 +1 0 1 +.names _n1c9<1> _n1b6<1> _n1cb<1> +.def 0 +0 1 1 +1 0 1 +.names _n1cb<0> _n1cb<1> _n1cc +.def 1 +0 0 0 +.names _n1cc _n1ca +0 1 +1 0 +.names _n1b5<0> state_bank3$raw_n144<*3*><0> _n1ca state_bank3$raw_n1b4<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1b5<1> state_bank3$raw_n144<*3*><1> _n1ca state_bank3$raw_n1b4<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1cf<0> +1 +.names _n1cf<1> +0 +.names _n1cf<0> _n1b5<0> +- =_n1cf<0> +.names _n1cf<1> _n1b5<1> +- =_n1cf<1> +# prediction = 'b0000 +.names _n1d1<0> +0 +.names _n1d1<1> +0 +.names _n1d1<2> +0 +.names _n1d1<3> +0 +.names _n1d1<0> prediction$raw_n1d0<0> +- =_n1d1<0> +.names _n1d1<1> prediction$raw_n1d0<1> +- =_n1d1<1> +.names _n1d1<2> prediction$raw_n1d0<2> +- =_n1d1<2> +.names _n1d1<3> prediction$raw_n1d0<3> +- =_n1d1<3> +# non-blocking assignments for initial +.names stall _n1d2 +0 1 +1 0 +.names _n1d2 _n1d3 +- =_n1d2 +.names state_bank3<*0*><0> state_bank3<*1*><0> state_bank3<*2*><0> state_bank3<*3*><0> inst_addr<1> inst_addr<0> _n1d4<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank3<*0*><1> state_bank3<*1*><1> state_bank3<*2*><1> state_bank3<*3*><1> inst_addr<1> inst_addr<0> _n1d4<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n1d5<0> +1 +.names _n1d5<1> +0 +# state_bank3 [inst_addr ] > 1 +.names _n1d8 +0 +.names _n1d4<0> _n1d5<0> _n1d8 _n1d7<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n1da +0 +.names _n1d4<0> _n1d5<0> _n1da _n1d9 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n1d4<1> _n1d5<1> _n1d9 _n1d7<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n1d4<1> _n1d5<1> _n1d9 _n1db +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n1d7<0> _n1d7<1> _n1dc +.def 0 +0 0 1 +.names _n1db _n1dc _n1dd +.def 1 +0 0 0 +.names _n1dd _n1d6 +0 1 +1 0 +.names _n1d6 _n1de +- =_n1d6 +# prediction [3] = 1 +.names prediction$_n1d6_n1df$true<3> +1 +.names prediction<0> prediction$_n1d6_n1df$true<0> +- =prediction<0> +.names prediction<1> prediction$_n1d6_n1df$true<1> +- =prediction<1> +.names prediction<2> prediction$_n1d6_n1df$true<2> +- =prediction<2> +# prediction [3] = 0 +.names prediction$_n1d6_n1e0$false<3> +0 +.names prediction<0> prediction$_n1d6_n1e0$false<0> +- =prediction<0> +.names prediction<1> prediction$_n1d6_n1e0$false<1> +- =prediction<1> +.names prediction<2> prediction$_n1d6_n1e0$false<2> +- =prediction<2> +# if/else (state_bank3 [inst_addr ] > 1) +.names prediction$_n1d6_n1df$true<0> prediction$_n1d6_n1e0$false<0> _n1d6 prediction$_n1d6$raw_n1e2<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n1d6_n1df$true<1> prediction$_n1d6_n1e0$false<1> _n1d6 prediction$_n1d6$raw_n1e2<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n1d6_n1df$true<2> prediction$_n1d6_n1e0$false<2> _n1d6 prediction$_n1d6$raw_n1e2<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n1d6_n1df$true<3> prediction$_n1d6_n1e0$false<3> _n1d6 prediction$_n1d6$raw_n1e2<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*0*><0> state_bank2<*1*><0> state_bank2<*2*><0> state_bank2<*3*><0> inst_addr<1> inst_addr<0> _n1e9<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank2<*0*><1> state_bank2<*1*><1> state_bank2<*2*><1> state_bank2<*3*><1> inst_addr<1> inst_addr<0> _n1e9<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n1ea<0> +1 +.names _n1ea<1> +0 +# state_bank2 [inst_addr ] > 1 +.names _n1ed +0 +.names _n1e9<0> _n1ea<0> _n1ed _n1ec<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n1ef +0 +.names _n1e9<0> _n1ea<0> _n1ef _n1ee +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n1e9<1> _n1ea<1> _n1ee _n1ec<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n1e9<1> _n1ea<1> _n1ee _n1f0 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n1ec<0> _n1ec<1> _n1f1 +.def 0 +0 0 1 +.names _n1f0 _n1f1 _n1f2 +.def 1 +0 0 0 +.names _n1f2 _n1eb +0 1 +1 0 +.names _n1eb _n1f3 +- =_n1eb +# prediction [2] = 1 +.names prediction$_n1eb_n1f4$true<2> +1 +.names prediction$_n1d6$raw_n1e2<0> prediction$_n1eb_n1f4$true<0> +- =prediction$_n1d6$raw_n1e2<0> +.names prediction$_n1d6$raw_n1e2<1> prediction$_n1eb_n1f4$true<1> +- =prediction$_n1d6$raw_n1e2<1> +.names prediction$_n1d6$raw_n1e2<3> prediction$_n1eb_n1f4$true<3> +- =prediction$_n1d6$raw_n1e2<3> +# prediction [2] = 0 +.names prediction$_n1eb_n1f5$false<2> +0 +.names prediction$_n1d6$raw_n1e2<0> prediction$_n1eb_n1f5$false<0> +- =prediction$_n1d6$raw_n1e2<0> +.names prediction$_n1d6$raw_n1e2<1> prediction$_n1eb_n1f5$false<1> +- =prediction$_n1d6$raw_n1e2<1> +.names prediction$_n1d6$raw_n1e2<3> prediction$_n1eb_n1f5$false<3> +- =prediction$_n1d6$raw_n1e2<3> +# if/else (state_bank2 [inst_addr ] > 1) +.names prediction$_n1eb_n1f4$true<0> prediction$_n1eb_n1f5$false<0> _n1eb prediction$_n1eb$raw_n1f6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n1eb_n1f4$true<1> prediction$_n1eb_n1f5$false<1> _n1eb prediction$_n1eb$raw_n1f6<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n1eb_n1f4$true<2> prediction$_n1eb_n1f5$false<2> _n1eb prediction$_n1eb$raw_n1f6<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n1eb_n1f4$true<3> prediction$_n1eb_n1f5$false<3> _n1eb prediction$_n1eb$raw_n1f6<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*0*><0> state_bank1<*1*><0> state_bank1<*2*><0> state_bank1<*3*><0> inst_addr<1> inst_addr<0> _n1fe<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank1<*0*><1> state_bank1<*1*><1> state_bank1<*2*><1> state_bank1<*3*><1> inst_addr<1> inst_addr<0> _n1fe<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n1ff<0> +1 +.names _n1ff<1> +0 +# state_bank1 [inst_addr ] > 1 +.names _n202 +0 +.names _n1fe<0> _n1ff<0> _n202 _n201<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n204 +0 +.names _n1fe<0> _n1ff<0> _n204 _n203 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n1fe<1> _n1ff<1> _n203 _n201<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n1fe<1> _n1ff<1> _n203 _n205 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n201<0> _n201<1> _n206 +.def 0 +0 0 1 +.names _n205 _n206 _n207 +.def 1 +0 0 0 +.names _n207 _n200 +0 1 +1 0 +.names _n200 _n208 +- =_n200 +# prediction [1] = 1 +.names prediction$_n200_n209$true<1> +1 +.names prediction$_n1eb$raw_n1f6<0> prediction$_n200_n209$true<0> +- =prediction$_n1eb$raw_n1f6<0> +.names prediction$_n1eb$raw_n1f6<2> prediction$_n200_n209$true<2> +- =prediction$_n1eb$raw_n1f6<2> +.names prediction$_n1eb$raw_n1f6<3> prediction$_n200_n209$true<3> +- =prediction$_n1eb$raw_n1f6<3> +# prediction [1] = 0 +.names prediction$_n200_n20a$false<1> +0 +.names prediction$_n1eb$raw_n1f6<0> prediction$_n200_n20a$false<0> +- =prediction$_n1eb$raw_n1f6<0> +.names prediction$_n1eb$raw_n1f6<2> prediction$_n200_n20a$false<2> +- =prediction$_n1eb$raw_n1f6<2> +.names prediction$_n1eb$raw_n1f6<3> prediction$_n200_n20a$false<3> +- =prediction$_n1eb$raw_n1f6<3> +# if/else (state_bank1 [inst_addr ] > 1) +.names prediction$_n200_n209$true<0> prediction$_n200_n20a$false<0> _n200 prediction$_n200$raw_n20b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n200_n209$true<1> prediction$_n200_n20a$false<1> _n200 prediction$_n200$raw_n20b<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n200_n209$true<2> prediction$_n200_n20a$false<2> _n200 prediction$_n200$raw_n20b<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n200_n209$true<3> prediction$_n200_n20a$false<3> _n200 prediction$_n200$raw_n20b<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0<*0*><0> state_bank0<*1*><0> state_bank0<*2*><0> state_bank0<*3*><0> inst_addr<1> inst_addr<0> _n213<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank0<*0*><1> state_bank0<*1*><1> state_bank0<*2*><1> state_bank0<*3*><1> inst_addr<1> inst_addr<0> _n213<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n214<0> +1 +.names _n214<1> +0 +# state_bank0 [inst_addr ] > 1 +.names _n217 +0 +.names _n213<0> _n214<0> _n217 _n216<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n219 +0 +.names _n213<0> _n214<0> _n219 _n218 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n213<1> _n214<1> _n218 _n216<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n213<1> _n214<1> _n218 _n21a +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n216<0> _n216<1> _n21b +.def 0 +0 0 1 +.names _n21a _n21b _n21c +.def 1 +0 0 0 +.names _n21c _n215 +0 1 +1 0 +.names _n215 _n21d +- =_n215 +# prediction [0] = 1 +.names prediction$_n215_n21e$true<0> +1 +.names prediction$_n200$raw_n20b<1> prediction$_n215_n21e$true<1> +- =prediction$_n200$raw_n20b<1> +.names prediction$_n200$raw_n20b<2> prediction$_n215_n21e$true<2> +- =prediction$_n200$raw_n20b<2> +.names prediction$_n200$raw_n20b<3> prediction$_n215_n21e$true<3> +- =prediction$_n200$raw_n20b<3> +# prediction [0] = 0 +.names prediction$_n215_n21f$false<0> +0 +.names prediction$_n200$raw_n20b<1> prediction$_n215_n21f$false<1> +- =prediction$_n200$raw_n20b<1> +.names prediction$_n200$raw_n20b<2> prediction$_n215_n21f$false<2> +- =prediction$_n200$raw_n20b<2> +.names prediction$_n200$raw_n20b<3> prediction$_n215_n21f$false<3> +- =prediction$_n200$raw_n20b<3> +# if/else (state_bank0 [inst_addr ] > 1) +.names prediction$_n215_n21e$true<0> prediction$_n215_n21f$false<0> _n215 prediction$_n215$raw_n220<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n215_n21e$true<1> prediction$_n215_n21f$false<1> _n215 prediction$_n215$raw_n220<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n215_n21e$true<2> prediction$_n215_n21f$false<2> _n215 prediction$_n215$raw_n220<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n215_n21e$true<3> prediction$_n215_n21f$false<3> _n215 prediction$_n215$raw_n220<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (!stall ) +.names prediction$_n215$raw_n220<0> prediction<0> _n1d2 prediction$_n1d2$raw_n22a<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n215$raw_n220<1> prediction<1> _n1d2 prediction$_n1d2$raw_n22a<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n215$raw_n220<2> prediction<2> _n1d2 prediction$_n1d2$raw_n22a<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names prediction$_n215$raw_n220<3> prediction<3> _n1d2 prediction$_n1d2$raw_n22a<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names update _n22f +- =update +.names branch_result _n230 +- =branch_result +.names _n232<0> +0 +.names _n232<1> +0 +# buffer_offset == 0 +.names buffer_offset<0> _n232<0> _n233<0> +.def 0 +0 1 1 +1 0 1 +.names buffer_offset<1> _n232<1> _n233<1> +.def 0 +0 1 1 +1 0 1 +.names _n233<0> _n233<1> _n234 +.def 1 +0 0 0 +.names _n234 _n231 +0 1 +1 0 +.names _n231 _n235 +- =_n231 +# state_bank0 [buffer_addr ] = state_bank0 [buffer_addr ] + 1 +.names _n238<0> +0 +.names _n238<1> +0 +.names _n238<0> buffer_addr<0> _n23a<0> +.def 0 +0 1 1 +1 0 1 +.names _n238<1> buffer_addr<1> _n23a<1> +.def 0 +0 1 1 +1 0 1 +.names _n23a<0> _n23a<1> _n23b +.def 1 +0 0 0 +.names _n23b _n239 +0 1 +1 0 +.names _n237<0> state_bank0<*0*><0> _n239 state_bank0$_n231_n236$true<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n237<1> state_bank0<*0*><1> _n239 state_bank0$_n231_n236$true<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n23e<0> +1 +.names _n23e<1> +0 +.names _n23e<0> buffer_addr<0> _n240<0> +.def 0 +0 1 1 +1 0 1 +.names _n23e<1> buffer_addr<1> _n240<1> +.def 0 +0 1 1 +1 0 1 +.names _n240<0> _n240<1> _n241 +.def 1 +0 0 0 +.names _n241 _n23f +0 1 +1 0 +.names _n237<0> state_bank0<*1*><0> _n23f state_bank0$_n231_n236$true<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n237<1> state_bank0<*1*><1> _n23f state_bank0$_n231_n236$true<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n244<0> +0 +.names _n244<1> +1 +.names _n244<0> buffer_addr<0> _n246<0> +.def 0 +0 1 1 +1 0 1 +.names _n244<1> buffer_addr<1> _n246<1> +.def 0 +0 1 1 +1 0 1 +.names _n246<0> _n246<1> _n247 +.def 1 +0 0 0 +.names _n247 _n245 +0 1 +1 0 +.names _n237<0> state_bank0<*2*><0> _n245 state_bank0$_n231_n236$true<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n237<1> state_bank0<*2*><1> _n245 state_bank0$_n231_n236$true<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n24a<0> +1 +.names _n24a<1> +1 +.names _n24a<0> buffer_addr<0> _n24c<0> +.def 0 +0 1 1 +1 0 1 +.names _n24a<1> buffer_addr<1> _n24c<1> +.def 0 +0 1 1 +1 0 1 +.names _n24c<0> _n24c<1> _n24d +.def 1 +0 0 0 +.names _n24d _n24b +0 1 +1 0 +.names _n237<0> state_bank0<*3*><0> _n24b state_bank0$_n231_n236$true<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n237<1> state_bank0<*3*><1> _n24b state_bank0$_n231_n236$true<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0<*0*><0> state_bank0<*1*><0> state_bank0<*2*><0> state_bank0<*3*><0> buffer_addr<1> buffer_addr<0> _n250<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank0<*0*><1> state_bank0<*1*><1> state_bank0<*2*><1> state_bank0<*3*><1> buffer_addr<1> buffer_addr<0> _n250<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n251<0> +1 +.names _n251<1> +0 +# state_bank0 [buffer_addr ] + 1 +.names _n253 +0 +.names _n250<0> _n251<0> _n253 _n252<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n255 +0 +.names _n250<0> _n251<0> _n255 _n254 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n250<1> _n251<1> _n254 _n252<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n252<0> _n237<0> +- =_n252<0> +.names _n252<1> _n237<1> +- =_n252<1> +.names _n257<0> +1 +.names _n257<1> +0 +# buffer_offset == 1 +.names buffer_offset<0> _n257<0> _n258<0> +.def 0 +0 1 1 +1 0 1 +.names buffer_offset<1> _n257<1> _n258<1> +.def 0 +0 1 1 +1 0 1 +.names _n258<0> _n258<1> _n259 +.def 1 +0 0 0 +.names _n259 _n256 +0 1 +1 0 +.names _n256 _n25a +- =_n256 +# state_bank1 [buffer_addr ] = state_bank1 [buffer_addr ] + 1 +.names _n25d<0> +0 +.names _n25d<1> +0 +.names _n25d<0> buffer_addr<0> _n25f<0> +.def 0 +0 1 1 +1 0 1 +.names _n25d<1> buffer_addr<1> _n25f<1> +.def 0 +0 1 1 +1 0 1 +.names _n25f<0> _n25f<1> _n260 +.def 1 +0 0 0 +.names _n260 _n25e +0 1 +1 0 +.names _n25c<0> state_bank1<*0*><0> _n25e state_bank1$_n256_n25b$true<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n25c<1> state_bank1<*0*><1> _n25e state_bank1$_n256_n25b$true<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n263<0> +1 +.names _n263<1> +0 +.names _n263<0> buffer_addr<0> _n265<0> +.def 0 +0 1 1 +1 0 1 +.names _n263<1> buffer_addr<1> _n265<1> +.def 0 +0 1 1 +1 0 1 +.names _n265<0> _n265<1> _n266 +.def 1 +0 0 0 +.names _n266 _n264 +0 1 +1 0 +.names _n25c<0> state_bank1<*1*><0> _n264 state_bank1$_n256_n25b$true<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n25c<1> state_bank1<*1*><1> _n264 state_bank1$_n256_n25b$true<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n269<0> +0 +.names _n269<1> +1 +.names _n269<0> buffer_addr<0> _n26b<0> +.def 0 +0 1 1 +1 0 1 +.names _n269<1> buffer_addr<1> _n26b<1> +.def 0 +0 1 1 +1 0 1 +.names _n26b<0> _n26b<1> _n26c +.def 1 +0 0 0 +.names _n26c _n26a +0 1 +1 0 +.names _n25c<0> state_bank1<*2*><0> _n26a state_bank1$_n256_n25b$true<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n25c<1> state_bank1<*2*><1> _n26a state_bank1$_n256_n25b$true<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n26f<0> +1 +.names _n26f<1> +1 +.names _n26f<0> buffer_addr<0> _n271<0> +.def 0 +0 1 1 +1 0 1 +.names _n26f<1> buffer_addr<1> _n271<1> +.def 0 +0 1 1 +1 0 1 +.names _n271<0> _n271<1> _n272 +.def 1 +0 0 0 +.names _n272 _n270 +0 1 +1 0 +.names _n25c<0> state_bank1<*3*><0> _n270 state_bank1$_n256_n25b$true<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n25c<1> state_bank1<*3*><1> _n270 state_bank1$_n256_n25b$true<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*0*><0> state_bank1<*1*><0> state_bank1<*2*><0> state_bank1<*3*><0> buffer_addr<1> buffer_addr<0> _n275<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank1<*0*><1> state_bank1<*1*><1> state_bank1<*2*><1> state_bank1<*3*><1> buffer_addr<1> buffer_addr<0> _n275<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n276<0> +1 +.names _n276<1> +0 +# state_bank1 [buffer_addr ] + 1 +.names _n278 +0 +.names _n275<0> _n276<0> _n278 _n277<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n27a +0 +.names _n275<0> _n276<0> _n27a _n279 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n275<1> _n276<1> _n279 _n277<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n277<0> _n25c<0> +- =_n277<0> +.names _n277<1> _n25c<1> +- =_n277<1> +.names _n27c<0> +0 +.names _n27c<1> +1 +# buffer_offset == 2 +.names buffer_offset<0> _n27c<0> _n27d<0> +.def 0 +0 1 1 +1 0 1 +.names buffer_offset<1> _n27c<1> _n27d<1> +.def 0 +0 1 1 +1 0 1 +.names _n27d<0> _n27d<1> _n27e +.def 1 +0 0 0 +.names _n27e _n27b +0 1 +1 0 +.names _n27b _n27f +- =_n27b +# state_bank2 [buffer_addr ] = state_bank2 [buffer_addr ] + 1 +.names _n282<0> +0 +.names _n282<1> +0 +.names _n282<0> buffer_addr<0> _n284<0> +.def 0 +0 1 1 +1 0 1 +.names _n282<1> buffer_addr<1> _n284<1> +.def 0 +0 1 1 +1 0 1 +.names _n284<0> _n284<1> _n285 +.def 1 +0 0 0 +.names _n285 _n283 +0 1 +1 0 +.names _n281<0> state_bank2<*0*><0> _n283 state_bank2$_n27b_n280$true<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n281<1> state_bank2<*0*><1> _n283 state_bank2$_n27b_n280$true<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n288<0> +1 +.names _n288<1> +0 +.names _n288<0> buffer_addr<0> _n28a<0> +.def 0 +0 1 1 +1 0 1 +.names _n288<1> buffer_addr<1> _n28a<1> +.def 0 +0 1 1 +1 0 1 +.names _n28a<0> _n28a<1> _n28b +.def 1 +0 0 0 +.names _n28b _n289 +0 1 +1 0 +.names _n281<0> state_bank2<*1*><0> _n289 state_bank2$_n27b_n280$true<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n281<1> state_bank2<*1*><1> _n289 state_bank2$_n27b_n280$true<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n28e<0> +0 +.names _n28e<1> +1 +.names _n28e<0> buffer_addr<0> _n290<0> +.def 0 +0 1 1 +1 0 1 +.names _n28e<1> buffer_addr<1> _n290<1> +.def 0 +0 1 1 +1 0 1 +.names _n290<0> _n290<1> _n291 +.def 1 +0 0 0 +.names _n291 _n28f +0 1 +1 0 +.names _n281<0> state_bank2<*2*><0> _n28f state_bank2$_n27b_n280$true<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n281<1> state_bank2<*2*><1> _n28f state_bank2$_n27b_n280$true<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n294<0> +1 +.names _n294<1> +1 +.names _n294<0> buffer_addr<0> _n296<0> +.def 0 +0 1 1 +1 0 1 +.names _n294<1> buffer_addr<1> _n296<1> +.def 0 +0 1 1 +1 0 1 +.names _n296<0> _n296<1> _n297 +.def 1 +0 0 0 +.names _n297 _n295 +0 1 +1 0 +.names _n281<0> state_bank2<*3*><0> _n295 state_bank2$_n27b_n280$true<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n281<1> state_bank2<*3*><1> _n295 state_bank2$_n27b_n280$true<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*0*><0> state_bank2<*1*><0> state_bank2<*2*><0> state_bank2<*3*><0> buffer_addr<1> buffer_addr<0> _n29a<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank2<*0*><1> state_bank2<*1*><1> state_bank2<*2*><1> state_bank2<*3*><1> buffer_addr<1> buffer_addr<0> _n29a<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n29b<0> +1 +.names _n29b<1> +0 +# state_bank2 [buffer_addr ] + 1 +.names _n29d +0 +.names _n29a<0> _n29b<0> _n29d _n29c<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n29f +0 +.names _n29a<0> _n29b<0> _n29f _n29e +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n29a<1> _n29b<1> _n29e _n29c<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n29c<0> _n281<0> +- =_n29c<0> +.names _n29c<1> _n281<1> +- =_n29c<1> +# state_bank3 [buffer_addr ] = state_bank3 [buffer_addr ] + 1 +.names _n2a2<0> +0 +.names _n2a2<1> +0 +.names _n2a2<0> buffer_addr<0> _n2a4<0> +.def 0 +0 1 1 +1 0 1 +.names _n2a2<1> buffer_addr<1> _n2a4<1> +.def 0 +0 1 1 +1 0 1 +.names _n2a4<0> _n2a4<1> _n2a5 +.def 1 +0 0 0 +.names _n2a5 _n2a3 +0 1 +1 0 +.names _n2a1<0> state_bank3<*0*><0> _n2a3 state_bank3$_n27b_n2a0$false<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2a1<1> state_bank3<*0*><1> _n2a3 state_bank3$_n27b_n2a0$false<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2a8<0> +1 +.names _n2a8<1> +0 +.names _n2a8<0> buffer_addr<0> _n2aa<0> +.def 0 +0 1 1 +1 0 1 +.names _n2a8<1> buffer_addr<1> _n2aa<1> +.def 0 +0 1 1 +1 0 1 +.names _n2aa<0> _n2aa<1> _n2ab +.def 1 +0 0 0 +.names _n2ab _n2a9 +0 1 +1 0 +.names _n2a1<0> state_bank3<*1*><0> _n2a9 state_bank3$_n27b_n2a0$false<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2a1<1> state_bank3<*1*><1> _n2a9 state_bank3$_n27b_n2a0$false<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2ae<0> +0 +.names _n2ae<1> +1 +.names _n2ae<0> buffer_addr<0> _n2b0<0> +.def 0 +0 1 1 +1 0 1 +.names _n2ae<1> buffer_addr<1> _n2b0<1> +.def 0 +0 1 1 +1 0 1 +.names _n2b0<0> _n2b0<1> _n2b1 +.def 1 +0 0 0 +.names _n2b1 _n2af +0 1 +1 0 +.names _n2a1<0> state_bank3<*2*><0> _n2af state_bank3$_n27b_n2a0$false<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2a1<1> state_bank3<*2*><1> _n2af state_bank3$_n27b_n2a0$false<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2b4<0> +1 +.names _n2b4<1> +1 +.names _n2b4<0> buffer_addr<0> _n2b6<0> +.def 0 +0 1 1 +1 0 1 +.names _n2b4<1> buffer_addr<1> _n2b6<1> +.def 0 +0 1 1 +1 0 1 +.names _n2b6<0> _n2b6<1> _n2b7 +.def 1 +0 0 0 +.names _n2b7 _n2b5 +0 1 +1 0 +.names _n2a1<0> state_bank3<*3*><0> _n2b5 state_bank3$_n27b_n2a0$false<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2a1<1> state_bank3<*3*><1> _n2b5 state_bank3$_n27b_n2a0$false<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><0> state_bank3<*1*><0> state_bank3<*2*><0> state_bank3<*3*><0> buffer_addr<1> buffer_addr<0> _n2ba<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank3<*0*><1> state_bank3<*1*><1> state_bank3<*2*><1> state_bank3<*3*><1> buffer_addr<1> buffer_addr<0> _n2ba<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n2bb<0> +1 +.names _n2bb<1> +0 +# state_bank3 [buffer_addr ] + 1 +.names _n2bd +0 +.names _n2ba<0> _n2bb<0> _n2bd _n2bc<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n2bf +0 +.names _n2ba<0> _n2bb<0> _n2bf _n2be +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n2ba<1> _n2bb<1> _n2be _n2bc<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n2bc<0> _n2a1<0> +- =_n2bc<0> +.names _n2bc<1> _n2a1<1> +- =_n2bc<1> +# if/else (buffer_offset == 2) +.names state_bank2$_n27b_n280$true<*0*><0> state_bank2<*0*><0> _n27b state_bank2$_n27b$raw_n2c2<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n27b_n280$true<*0*><1> state_bank2<*0*><1> _n27b state_bank2$_n27b$raw_n2c2<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n27b_n280$true<*1*><0> state_bank2<*1*><0> _n27b state_bank2$_n27b$raw_n2c2<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n27b_n280$true<*1*><1> state_bank2<*1*><1> _n27b state_bank2$_n27b$raw_n2c2<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n27b_n280$true<*2*><0> state_bank2<*2*><0> _n27b state_bank2$_n27b$raw_n2c2<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n27b_n280$true<*2*><1> state_bank2<*2*><1> _n27b state_bank2$_n27b$raw_n2c2<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n27b_n280$true<*3*><0> state_bank2<*3*><0> _n27b state_bank2$_n27b$raw_n2c2<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n27b_n280$true<*3*><1> state_bank2<*3*><1> _n27b state_bank2$_n27b$raw_n2c2<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><0> state_bank3$_n27b_n2a0$false<*0*><0> _n27b state_bank3$_n27b$raw_n2cb<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><1> state_bank3$_n27b_n2a0$false<*0*><1> _n27b state_bank3$_n27b$raw_n2cb<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><0> state_bank3$_n27b_n2a0$false<*1*><0> _n27b state_bank3$_n27b$raw_n2cb<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><1> state_bank3$_n27b_n2a0$false<*1*><1> _n27b state_bank3$_n27b$raw_n2cb<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><0> state_bank3$_n27b_n2a0$false<*2*><0> _n27b state_bank3$_n27b$raw_n2cb<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><1> state_bank3$_n27b_n2a0$false<*2*><1> _n27b state_bank3$_n27b$raw_n2cb<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><0> state_bank3$_n27b_n2a0$false<*3*><0> _n27b state_bank3$_n27b$raw_n2cb<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><1> state_bank3$_n27b_n2a0$false<*3*><1> _n27b state_bank3$_n27b$raw_n2cb<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (buffer_offset == 1) +.names state_bank1$_n256_n25b$true<*0*><0> state_bank1<*0*><0> _n256 state_bank1$_n256$raw_n2d6<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n256_n25b$true<*0*><1> state_bank1<*0*><1> _n256 state_bank1$_n256$raw_n2d6<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n256_n25b$true<*1*><0> state_bank1<*1*><0> _n256 state_bank1$_n256$raw_n2d6<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n256_n25b$true<*1*><1> state_bank1<*1*><1> _n256 state_bank1$_n256$raw_n2d6<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n256_n25b$true<*2*><0> state_bank1<*2*><0> _n256 state_bank1$_n256$raw_n2d6<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n256_n25b$true<*2*><1> state_bank1<*2*><1> _n256 state_bank1$_n256$raw_n2d6<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n256_n25b$true<*3*><0> state_bank1<*3*><0> _n256 state_bank1$_n256$raw_n2d6<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n256_n25b$true<*3*><1> state_bank1<*3*><1> _n256 state_bank1$_n256$raw_n2d6<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><0> state_bank3$_n27b$raw_n2cb<*0*><0> _n256 state_bank3$_n256$raw_n2df<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><1> state_bank3$_n27b$raw_n2cb<*0*><1> _n256 state_bank3$_n256$raw_n2df<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><0> state_bank3$_n27b$raw_n2cb<*1*><0> _n256 state_bank3$_n256$raw_n2df<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><1> state_bank3$_n27b$raw_n2cb<*1*><1> _n256 state_bank3$_n256$raw_n2df<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><0> state_bank3$_n27b$raw_n2cb<*2*><0> _n256 state_bank3$_n256$raw_n2df<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><1> state_bank3$_n27b$raw_n2cb<*2*><1> _n256 state_bank3$_n256$raw_n2df<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><0> state_bank3$_n27b$raw_n2cb<*3*><0> _n256 state_bank3$_n256$raw_n2df<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><1> state_bank3$_n27b$raw_n2cb<*3*><1> _n256 state_bank3$_n256$raw_n2df<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*0*><0> state_bank2$_n27b$raw_n2c2<*0*><0> _n256 state_bank2$_n256$raw_n2e8<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*0*><1> state_bank2$_n27b$raw_n2c2<*0*><1> _n256 state_bank2$_n256$raw_n2e8<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*1*><0> state_bank2$_n27b$raw_n2c2<*1*><0> _n256 state_bank2$_n256$raw_n2e8<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*1*><1> state_bank2$_n27b$raw_n2c2<*1*><1> _n256 state_bank2$_n256$raw_n2e8<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*2*><0> state_bank2$_n27b$raw_n2c2<*2*><0> _n256 state_bank2$_n256$raw_n2e8<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*2*><1> state_bank2$_n27b$raw_n2c2<*2*><1> _n256 state_bank2$_n256$raw_n2e8<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*3*><0> state_bank2$_n27b$raw_n2c2<*3*><0> _n256 state_bank2$_n256$raw_n2e8<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*3*><1> state_bank2$_n27b$raw_n2c2<*3*><1> _n256 state_bank2$_n256$raw_n2e8<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (buffer_offset == 0) +.names state_bank0$_n231_n236$true<*0*><0> state_bank0<*0*><0> _n231 state_bank0$_n231$raw_n2f3<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231_n236$true<*0*><1> state_bank0<*0*><1> _n231 state_bank0$_n231$raw_n2f3<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231_n236$true<*1*><0> state_bank0<*1*><0> _n231 state_bank0$_n231$raw_n2f3<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231_n236$true<*1*><1> state_bank0<*1*><1> _n231 state_bank0$_n231$raw_n2f3<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231_n236$true<*2*><0> state_bank0<*2*><0> _n231 state_bank0$_n231$raw_n2f3<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231_n236$true<*2*><1> state_bank0<*2*><1> _n231 state_bank0$_n231$raw_n2f3<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231_n236$true<*3*><0> state_bank0<*3*><0> _n231 state_bank0$_n231$raw_n2f3<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231_n236$true<*3*><1> state_bank0<*3*><1> _n231 state_bank0$_n231$raw_n2f3<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><0> state_bank3$_n256$raw_n2df<*0*><0> _n231 state_bank3$_n231$raw_n2fc<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><1> state_bank3$_n256$raw_n2df<*0*><1> _n231 state_bank3$_n231$raw_n2fc<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><0> state_bank3$_n256$raw_n2df<*1*><0> _n231 state_bank3$_n231$raw_n2fc<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><1> state_bank3$_n256$raw_n2df<*1*><1> _n231 state_bank3$_n231$raw_n2fc<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><0> state_bank3$_n256$raw_n2df<*2*><0> _n231 state_bank3$_n231$raw_n2fc<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><1> state_bank3$_n256$raw_n2df<*2*><1> _n231 state_bank3$_n231$raw_n2fc<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><0> state_bank3$_n256$raw_n2df<*3*><0> _n231 state_bank3$_n231$raw_n2fc<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><1> state_bank3$_n256$raw_n2df<*3*><1> _n231 state_bank3$_n231$raw_n2fc<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*0*><0> state_bank2$_n256$raw_n2e8<*0*><0> _n231 state_bank2$_n231$raw_n305<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*0*><1> state_bank2$_n256$raw_n2e8<*0*><1> _n231 state_bank2$_n231$raw_n305<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*1*><0> state_bank2$_n256$raw_n2e8<*1*><0> _n231 state_bank2$_n231$raw_n305<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*1*><1> state_bank2$_n256$raw_n2e8<*1*><1> _n231 state_bank2$_n231$raw_n305<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*2*><0> state_bank2$_n256$raw_n2e8<*2*><0> _n231 state_bank2$_n231$raw_n305<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*2*><1> state_bank2$_n256$raw_n2e8<*2*><1> _n231 state_bank2$_n231$raw_n305<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*3*><0> state_bank2$_n256$raw_n2e8<*3*><0> _n231 state_bank2$_n231$raw_n305<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*3*><1> state_bank2$_n256$raw_n2e8<*3*><1> _n231 state_bank2$_n231$raw_n305<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*0*><0> state_bank1$_n256$raw_n2d6<*0*><0> _n231 state_bank1$_n231$raw_n30e<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*0*><1> state_bank1$_n256$raw_n2d6<*0*><1> _n231 state_bank1$_n231$raw_n30e<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*1*><0> state_bank1$_n256$raw_n2d6<*1*><0> _n231 state_bank1$_n231$raw_n30e<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*1*><1> state_bank1$_n256$raw_n2d6<*1*><1> _n231 state_bank1$_n231$raw_n30e<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*2*><0> state_bank1$_n256$raw_n2d6<*2*><0> _n231 state_bank1$_n231$raw_n30e<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*2*><1> state_bank1$_n256$raw_n2d6<*2*><1> _n231 state_bank1$_n231$raw_n30e<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*3*><0> state_bank1$_n256$raw_n2d6<*3*><0> _n231 state_bank1$_n231$raw_n30e<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*3*><1> state_bank1$_n256$raw_n2d6<*3*><1> _n231 state_bank1$_n231$raw_n30e<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n318<0> +0 +.names _n318<1> +0 +# buffer_offset == 0 +.names buffer_offset<0> _n318<0> _n319<0> +.def 0 +0 1 1 +1 0 1 +.names buffer_offset<1> _n318<1> _n319<1> +.def 0 +0 1 1 +1 0 1 +.names _n319<0> _n319<1> _n31a +.def 1 +0 0 0 +.names _n31a _n317 +0 1 +1 0 +.names _n317 _n31b +- =_n317 +# state_bank0 [buffer_addr ] = state_bank0 [buffer_addr ] - 1 +.names _n31e<0> +0 +.names _n31e<1> +0 +.names _n31e<0> buffer_addr<0> _n320<0> +.def 0 +0 1 1 +1 0 1 +.names _n31e<1> buffer_addr<1> _n320<1> +.def 0 +0 1 1 +1 0 1 +.names _n320<0> _n320<1> _n321 +.def 1 +0 0 0 +.names _n321 _n31f +0 1 +1 0 +.names _n31d<0> state_bank0<*0*><0> _n31f state_bank0$_n317_n31c$true<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n31d<1> state_bank0<*0*><1> _n31f state_bank0$_n317_n31c$true<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n324<0> +1 +.names _n324<1> +0 +.names _n324<0> buffer_addr<0> _n326<0> +.def 0 +0 1 1 +1 0 1 +.names _n324<1> buffer_addr<1> _n326<1> +.def 0 +0 1 1 +1 0 1 +.names _n326<0> _n326<1> _n327 +.def 1 +0 0 0 +.names _n327 _n325 +0 1 +1 0 +.names _n31d<0> state_bank0<*1*><0> _n325 state_bank0$_n317_n31c$true<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n31d<1> state_bank0<*1*><1> _n325 state_bank0$_n317_n31c$true<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n32a<0> +0 +.names _n32a<1> +1 +.names _n32a<0> buffer_addr<0> _n32c<0> +.def 0 +0 1 1 +1 0 1 +.names _n32a<1> buffer_addr<1> _n32c<1> +.def 0 +0 1 1 +1 0 1 +.names _n32c<0> _n32c<1> _n32d +.def 1 +0 0 0 +.names _n32d _n32b +0 1 +1 0 +.names _n31d<0> state_bank0<*2*><0> _n32b state_bank0$_n317_n31c$true<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n31d<1> state_bank0<*2*><1> _n32b state_bank0$_n317_n31c$true<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n330<0> +1 +.names _n330<1> +1 +.names _n330<0> buffer_addr<0> _n332<0> +.def 0 +0 1 1 +1 0 1 +.names _n330<1> buffer_addr<1> _n332<1> +.def 0 +0 1 1 +1 0 1 +.names _n332<0> _n332<1> _n333 +.def 1 +0 0 0 +.names _n333 _n331 +0 1 +1 0 +.names _n31d<0> state_bank0<*3*><0> _n331 state_bank0$_n317_n31c$true<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n31d<1> state_bank0<*3*><1> _n331 state_bank0$_n317_n31c$true<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0<*0*><0> state_bank0<*1*><0> state_bank0<*2*><0> state_bank0<*3*><0> buffer_addr<1> buffer_addr<0> _n336<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank0<*0*><1> state_bank0<*1*><1> state_bank0<*2*><1> state_bank0<*3*><1> buffer_addr<1> buffer_addr<0> _n336<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n337<0> +1 +.names _n337<1> +0 +# state_bank0 [buffer_addr ] - 1 +.names _n339 +0 +.names _n336<0> _n337<0> _n339 _n338<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33b +0 +.names _n336<0> _n337<0> _n33b _n33a +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n336<1> _n337<1> _n33a _n338<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n338<0> _n31d<0> +- =_n338<0> +.names _n338<1> _n31d<1> +- =_n338<1> +.names _n33d<0> +1 +.names _n33d<1> +0 +# buffer_offset == 1 +.names buffer_offset<0> _n33d<0> _n33e<0> +.def 0 +0 1 1 +1 0 1 +.names buffer_offset<1> _n33d<1> _n33e<1> +.def 0 +0 1 1 +1 0 1 +.names _n33e<0> _n33e<1> _n33f +.def 1 +0 0 0 +.names _n33f _n33c +0 1 +1 0 +.names _n33c _n340 +- =_n33c +# state_bank1 [buffer_addr ] = state_bank1 [buffer_addr ] - 1 +.names _n343<0> +0 +.names _n343<1> +0 +.names _n343<0> buffer_addr<0> _n345<0> +.def 0 +0 1 1 +1 0 1 +.names _n343<1> buffer_addr<1> _n345<1> +.def 0 +0 1 1 +1 0 1 +.names _n345<0> _n345<1> _n346 +.def 1 +0 0 0 +.names _n346 _n344 +0 1 +1 0 +.names _n342<0> state_bank1<*0*><0> _n344 state_bank1$_n33c_n341$true<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n342<1> state_bank1<*0*><1> _n344 state_bank1$_n33c_n341$true<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n349<0> +1 +.names _n349<1> +0 +.names _n349<0> buffer_addr<0> _n34b<0> +.def 0 +0 1 1 +1 0 1 +.names _n349<1> buffer_addr<1> _n34b<1> +.def 0 +0 1 1 +1 0 1 +.names _n34b<0> _n34b<1> _n34c +.def 1 +0 0 0 +.names _n34c _n34a +0 1 +1 0 +.names _n342<0> state_bank1<*1*><0> _n34a state_bank1$_n33c_n341$true<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n342<1> state_bank1<*1*><1> _n34a state_bank1$_n33c_n341$true<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n34f<0> +0 +.names _n34f<1> +1 +.names _n34f<0> buffer_addr<0> _n351<0> +.def 0 +0 1 1 +1 0 1 +.names _n34f<1> buffer_addr<1> _n351<1> +.def 0 +0 1 1 +1 0 1 +.names _n351<0> _n351<1> _n352 +.def 1 +0 0 0 +.names _n352 _n350 +0 1 +1 0 +.names _n342<0> state_bank1<*2*><0> _n350 state_bank1$_n33c_n341$true<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n342<1> state_bank1<*2*><1> _n350 state_bank1$_n33c_n341$true<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n355<0> +1 +.names _n355<1> +1 +.names _n355<0> buffer_addr<0> _n357<0> +.def 0 +0 1 1 +1 0 1 +.names _n355<1> buffer_addr<1> _n357<1> +.def 0 +0 1 1 +1 0 1 +.names _n357<0> _n357<1> _n358 +.def 1 +0 0 0 +.names _n358 _n356 +0 1 +1 0 +.names _n342<0> state_bank1<*3*><0> _n356 state_bank1$_n33c_n341$true<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n342<1> state_bank1<*3*><1> _n356 state_bank1$_n33c_n341$true<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*0*><0> state_bank1<*1*><0> state_bank1<*2*><0> state_bank1<*3*><0> buffer_addr<1> buffer_addr<0> _n35b<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank1<*0*><1> state_bank1<*1*><1> state_bank1<*2*><1> state_bank1<*3*><1> buffer_addr<1> buffer_addr<0> _n35b<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n35c<0> +1 +.names _n35c<1> +0 +# state_bank1 [buffer_addr ] - 1 +.names _n35e +0 +.names _n35b<0> _n35c<0> _n35e _n35d<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n360 +0 +.names _n35b<0> _n35c<0> _n360 _n35f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n35b<1> _n35c<1> _n35f _n35d<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n35d<0> _n342<0> +- =_n35d<0> +.names _n35d<1> _n342<1> +- =_n35d<1> +.names _n362<0> +0 +.names _n362<1> +1 +# buffer_offset == 2 +.names buffer_offset<0> _n362<0> _n363<0> +.def 0 +0 1 1 +1 0 1 +.names buffer_offset<1> _n362<1> _n363<1> +.def 0 +0 1 1 +1 0 1 +.names _n363<0> _n363<1> _n364 +.def 1 +0 0 0 +.names _n364 _n361 +0 1 +1 0 +.names _n361 _n365 +- =_n361 +# state_bank2 [buffer_addr ] = state_bank2 [buffer_addr ] - 1 +.names _n368<0> +0 +.names _n368<1> +0 +.names _n368<0> buffer_addr<0> _n36a<0> +.def 0 +0 1 1 +1 0 1 +.names _n368<1> buffer_addr<1> _n36a<1> +.def 0 +0 1 1 +1 0 1 +.names _n36a<0> _n36a<1> _n36b +.def 1 +0 0 0 +.names _n36b _n369 +0 1 +1 0 +.names _n367<0> state_bank2<*0*><0> _n369 state_bank2$_n361_n366$true<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n367<1> state_bank2<*0*><1> _n369 state_bank2$_n361_n366$true<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n36e<0> +1 +.names _n36e<1> +0 +.names _n36e<0> buffer_addr<0> _n370<0> +.def 0 +0 1 1 +1 0 1 +.names _n36e<1> buffer_addr<1> _n370<1> +.def 0 +0 1 1 +1 0 1 +.names _n370<0> _n370<1> _n371 +.def 1 +0 0 0 +.names _n371 _n36f +0 1 +1 0 +.names _n367<0> state_bank2<*1*><0> _n36f state_bank2$_n361_n366$true<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n367<1> state_bank2<*1*><1> _n36f state_bank2$_n361_n366$true<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n374<0> +0 +.names _n374<1> +1 +.names _n374<0> buffer_addr<0> _n376<0> +.def 0 +0 1 1 +1 0 1 +.names _n374<1> buffer_addr<1> _n376<1> +.def 0 +0 1 1 +1 0 1 +.names _n376<0> _n376<1> _n377 +.def 1 +0 0 0 +.names _n377 _n375 +0 1 +1 0 +.names _n367<0> state_bank2<*2*><0> _n375 state_bank2$_n361_n366$true<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n367<1> state_bank2<*2*><1> _n375 state_bank2$_n361_n366$true<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n37a<0> +1 +.names _n37a<1> +1 +.names _n37a<0> buffer_addr<0> _n37c<0> +.def 0 +0 1 1 +1 0 1 +.names _n37a<1> buffer_addr<1> _n37c<1> +.def 0 +0 1 1 +1 0 1 +.names _n37c<0> _n37c<1> _n37d +.def 1 +0 0 0 +.names _n37d _n37b +0 1 +1 0 +.names _n367<0> state_bank2<*3*><0> _n37b state_bank2$_n361_n366$true<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n367<1> state_bank2<*3*><1> _n37b state_bank2$_n361_n366$true<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*0*><0> state_bank2<*1*><0> state_bank2<*2*><0> state_bank2<*3*><0> buffer_addr<1> buffer_addr<0> _n380<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank2<*0*><1> state_bank2<*1*><1> state_bank2<*2*><1> state_bank2<*3*><1> buffer_addr<1> buffer_addr<0> _n380<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n381<0> +1 +.names _n381<1> +0 +# state_bank2 [buffer_addr ] - 1 +.names _n383 +0 +.names _n380<0> _n381<0> _n383 _n382<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n385 +0 +.names _n380<0> _n381<0> _n385 _n384 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n380<1> _n381<1> _n384 _n382<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n382<0> _n367<0> +- =_n382<0> +.names _n382<1> _n367<1> +- =_n382<1> +# state_bank3 [buffer_addr ] = state_bank3 [buffer_addr ] - 1 +.names _n388<0> +0 +.names _n388<1> +0 +.names _n388<0> buffer_addr<0> _n38a<0> +.def 0 +0 1 1 +1 0 1 +.names _n388<1> buffer_addr<1> _n38a<1> +.def 0 +0 1 1 +1 0 1 +.names _n38a<0> _n38a<1> _n38b +.def 1 +0 0 0 +.names _n38b _n389 +0 1 +1 0 +.names _n387<0> state_bank3<*0*><0> _n389 state_bank3$_n361_n386$false<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n387<1> state_bank3<*0*><1> _n389 state_bank3$_n361_n386$false<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n38e<0> +1 +.names _n38e<1> +0 +.names _n38e<0> buffer_addr<0> _n390<0> +.def 0 +0 1 1 +1 0 1 +.names _n38e<1> buffer_addr<1> _n390<1> +.def 0 +0 1 1 +1 0 1 +.names _n390<0> _n390<1> _n391 +.def 1 +0 0 0 +.names _n391 _n38f +0 1 +1 0 +.names _n387<0> state_bank3<*1*><0> _n38f state_bank3$_n361_n386$false<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n387<1> state_bank3<*1*><1> _n38f state_bank3$_n361_n386$false<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n394<0> +0 +.names _n394<1> +1 +.names _n394<0> buffer_addr<0> _n396<0> +.def 0 +0 1 1 +1 0 1 +.names _n394<1> buffer_addr<1> _n396<1> +.def 0 +0 1 1 +1 0 1 +.names _n396<0> _n396<1> _n397 +.def 1 +0 0 0 +.names _n397 _n395 +0 1 +1 0 +.names _n387<0> state_bank3<*2*><0> _n395 state_bank3$_n361_n386$false<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n387<1> state_bank3<*2*><1> _n395 state_bank3$_n361_n386$false<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n39a<0> +1 +.names _n39a<1> +1 +.names _n39a<0> buffer_addr<0> _n39c<0> +.def 0 +0 1 1 +1 0 1 +.names _n39a<1> buffer_addr<1> _n39c<1> +.def 0 +0 1 1 +1 0 1 +.names _n39c<0> _n39c<1> _n39d +.def 1 +0 0 0 +.names _n39d _n39b +0 1 +1 0 +.names _n387<0> state_bank3<*3*><0> _n39b state_bank3$_n361_n386$false<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n387<1> state_bank3<*3*><1> _n39b state_bank3$_n361_n386$false<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><0> state_bank3<*1*><0> state_bank3<*2*><0> state_bank3<*3*><0> buffer_addr<1> buffer_addr<0> _n3a0<0> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names state_bank3<*0*><1> state_bank3<*1*><1> state_bank3<*2*><1> state_bank3<*3*><1> buffer_addr<1> buffer_addr<0> _n3a0<1> +0 - - - 0 0 0 +1 - - - 0 0 1 +- 0 - - 0 1 0 +- 1 - - 0 1 1 +- - 0 - 1 0 0 +- - 1 - 1 0 1 +- - - 0 1 1 0 +- - - 1 1 1 1 +.names _n3a1<0> +1 +.names _n3a1<1> +0 +# state_bank3 [buffer_addr ] - 1 +.names _n3a3 +0 +.names _n3a0<0> _n3a1<0> _n3a3 _n3a2<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n3a5 +0 +.names _n3a0<0> _n3a1<0> _n3a5 _n3a4 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n3a0<1> _n3a1<1> _n3a4 _n3a2<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n3a2<0> _n387<0> +- =_n3a2<0> +.names _n3a2<1> _n387<1> +- =_n3a2<1> +# if/else (buffer_offset == 2) +.names state_bank2$_n361_n366$true<*0*><0> state_bank2<*0*><0> _n361 state_bank2$_n361$raw_n3a8<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n361_n366$true<*0*><1> state_bank2<*0*><1> _n361 state_bank2$_n361$raw_n3a8<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n361_n366$true<*1*><0> state_bank2<*1*><0> _n361 state_bank2$_n361$raw_n3a8<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n361_n366$true<*1*><1> state_bank2<*1*><1> _n361 state_bank2$_n361$raw_n3a8<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n361_n366$true<*2*><0> state_bank2<*2*><0> _n361 state_bank2$_n361$raw_n3a8<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n361_n366$true<*2*><1> state_bank2<*2*><1> _n361 state_bank2$_n361$raw_n3a8<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n361_n366$true<*3*><0> state_bank2<*3*><0> _n361 state_bank2$_n361$raw_n3a8<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n361_n366$true<*3*><1> state_bank2<*3*><1> _n361 state_bank2$_n361$raw_n3a8<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><0> state_bank3$_n361_n386$false<*0*><0> _n361 state_bank3$_n361$raw_n3b1<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><1> state_bank3$_n361_n386$false<*0*><1> _n361 state_bank3$_n361$raw_n3b1<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><0> state_bank3$_n361_n386$false<*1*><0> _n361 state_bank3$_n361$raw_n3b1<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><1> state_bank3$_n361_n386$false<*1*><1> _n361 state_bank3$_n361$raw_n3b1<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><0> state_bank3$_n361_n386$false<*2*><0> _n361 state_bank3$_n361$raw_n3b1<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><1> state_bank3$_n361_n386$false<*2*><1> _n361 state_bank3$_n361$raw_n3b1<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><0> state_bank3$_n361_n386$false<*3*><0> _n361 state_bank3$_n361$raw_n3b1<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><1> state_bank3$_n361_n386$false<*3*><1> _n361 state_bank3$_n361$raw_n3b1<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (buffer_offset == 1) +.names state_bank1$_n33c_n341$true<*0*><0> state_bank1<*0*><0> _n33c state_bank1$_n33c$raw_n3bc<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n33c_n341$true<*0*><1> state_bank1<*0*><1> _n33c state_bank1$_n33c$raw_n3bc<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n33c_n341$true<*1*><0> state_bank1<*1*><0> _n33c state_bank1$_n33c$raw_n3bc<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n33c_n341$true<*1*><1> state_bank1<*1*><1> _n33c state_bank1$_n33c$raw_n3bc<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n33c_n341$true<*2*><0> state_bank1<*2*><0> _n33c state_bank1$_n33c$raw_n3bc<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n33c_n341$true<*2*><1> state_bank1<*2*><1> _n33c state_bank1$_n33c$raw_n3bc<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n33c_n341$true<*3*><0> state_bank1<*3*><0> _n33c state_bank1$_n33c$raw_n3bc<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n33c_n341$true<*3*><1> state_bank1<*3*><1> _n33c state_bank1$_n33c$raw_n3bc<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><0> state_bank3$_n361$raw_n3b1<*0*><0> _n33c state_bank3$_n33c$raw_n3c5<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><1> state_bank3$_n361$raw_n3b1<*0*><1> _n33c state_bank3$_n33c$raw_n3c5<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><0> state_bank3$_n361$raw_n3b1<*1*><0> _n33c state_bank3$_n33c$raw_n3c5<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><1> state_bank3$_n361$raw_n3b1<*1*><1> _n33c state_bank3$_n33c$raw_n3c5<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><0> state_bank3$_n361$raw_n3b1<*2*><0> _n33c state_bank3$_n33c$raw_n3c5<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><1> state_bank3$_n361$raw_n3b1<*2*><1> _n33c state_bank3$_n33c$raw_n3c5<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><0> state_bank3$_n361$raw_n3b1<*3*><0> _n33c state_bank3$_n33c$raw_n3c5<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><1> state_bank3$_n361$raw_n3b1<*3*><1> _n33c state_bank3$_n33c$raw_n3c5<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*0*><0> state_bank2$_n361$raw_n3a8<*0*><0> _n33c state_bank2$_n33c$raw_n3ce<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*0*><1> state_bank2$_n361$raw_n3a8<*0*><1> _n33c state_bank2$_n33c$raw_n3ce<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*1*><0> state_bank2$_n361$raw_n3a8<*1*><0> _n33c state_bank2$_n33c$raw_n3ce<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*1*><1> state_bank2$_n361$raw_n3a8<*1*><1> _n33c state_bank2$_n33c$raw_n3ce<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*2*><0> state_bank2$_n361$raw_n3a8<*2*><0> _n33c state_bank2$_n33c$raw_n3ce<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*2*><1> state_bank2$_n361$raw_n3a8<*2*><1> _n33c state_bank2$_n33c$raw_n3ce<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*3*><0> state_bank2$_n361$raw_n3a8<*3*><0> _n33c state_bank2$_n33c$raw_n3ce<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*3*><1> state_bank2$_n361$raw_n3a8<*3*><1> _n33c state_bank2$_n33c$raw_n3ce<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (buffer_offset == 0) +.names state_bank0$_n317_n31c$true<*0*><0> state_bank0<*0*><0> _n317 state_bank0$_n317$raw_n3d9<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n317_n31c$true<*0*><1> state_bank0<*0*><1> _n317 state_bank0$_n317$raw_n3d9<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n317_n31c$true<*1*><0> state_bank0<*1*><0> _n317 state_bank0$_n317$raw_n3d9<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n317_n31c$true<*1*><1> state_bank0<*1*><1> _n317 state_bank0$_n317$raw_n3d9<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n317_n31c$true<*2*><0> state_bank0<*2*><0> _n317 state_bank0$_n317$raw_n3d9<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n317_n31c$true<*2*><1> state_bank0<*2*><1> _n317 state_bank0$_n317$raw_n3d9<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n317_n31c$true<*3*><0> state_bank0<*3*><0> _n317 state_bank0$_n317$raw_n3d9<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n317_n31c$true<*3*><1> state_bank0<*3*><1> _n317 state_bank0$_n317$raw_n3d9<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><0> state_bank3$_n33c$raw_n3c5<*0*><0> _n317 state_bank3$_n317$raw_n3e2<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*0*><1> state_bank3$_n33c$raw_n3c5<*0*><1> _n317 state_bank3$_n317$raw_n3e2<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><0> state_bank3$_n33c$raw_n3c5<*1*><0> _n317 state_bank3$_n317$raw_n3e2<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*1*><1> state_bank3$_n33c$raw_n3c5<*1*><1> _n317 state_bank3$_n317$raw_n3e2<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><0> state_bank3$_n33c$raw_n3c5<*2*><0> _n317 state_bank3$_n317$raw_n3e2<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*2*><1> state_bank3$_n33c$raw_n3c5<*2*><1> _n317 state_bank3$_n317$raw_n3e2<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><0> state_bank3$_n33c$raw_n3c5<*3*><0> _n317 state_bank3$_n317$raw_n3e2<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3<*3*><1> state_bank3$_n33c$raw_n3c5<*3*><1> _n317 state_bank3$_n317$raw_n3e2<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*0*><0> state_bank2$_n33c$raw_n3ce<*0*><0> _n317 state_bank2$_n317$raw_n3eb<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*0*><1> state_bank2$_n33c$raw_n3ce<*0*><1> _n317 state_bank2$_n317$raw_n3eb<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*1*><0> state_bank2$_n33c$raw_n3ce<*1*><0> _n317 state_bank2$_n317$raw_n3eb<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*1*><1> state_bank2$_n33c$raw_n3ce<*1*><1> _n317 state_bank2$_n317$raw_n3eb<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*2*><0> state_bank2$_n33c$raw_n3ce<*2*><0> _n317 state_bank2$_n317$raw_n3eb<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*2*><1> state_bank2$_n33c$raw_n3ce<*2*><1> _n317 state_bank2$_n317$raw_n3eb<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*3*><0> state_bank2$_n33c$raw_n3ce<*3*><0> _n317 state_bank2$_n317$raw_n3eb<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2<*3*><1> state_bank2$_n33c$raw_n3ce<*3*><1> _n317 state_bank2$_n317$raw_n3eb<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*0*><0> state_bank1$_n33c$raw_n3bc<*0*><0> _n317 state_bank1$_n317$raw_n3f4<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*0*><1> state_bank1$_n33c$raw_n3bc<*0*><1> _n317 state_bank1$_n317$raw_n3f4<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*1*><0> state_bank1$_n33c$raw_n3bc<*1*><0> _n317 state_bank1$_n317$raw_n3f4<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*1*><1> state_bank1$_n33c$raw_n3bc<*1*><1> _n317 state_bank1$_n317$raw_n3f4<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*2*><0> state_bank1$_n33c$raw_n3bc<*2*><0> _n317 state_bank1$_n317$raw_n3f4<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*2*><1> state_bank1$_n33c$raw_n3bc<*2*><1> _n317 state_bank1$_n317$raw_n3f4<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*3*><0> state_bank1$_n33c$raw_n3bc<*3*><0> _n317 state_bank1$_n317$raw_n3f4<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1<*3*><1> state_bank1$_n33c$raw_n3bc<*3*><1> _n317 state_bank1$_n317$raw_n3f4<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (branch_result ) +.names state_bank3$_n231$raw_n2fc<*0*><0> state_bank3$_n317$raw_n3e2<*0*><0> branch_result state_bank3$branch_result$raw_n401<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$_n231$raw_n2fc<*0*><1> state_bank3$_n317$raw_n3e2<*0*><1> branch_result state_bank3$branch_result$raw_n401<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$_n231$raw_n2fc<*1*><0> state_bank3$_n317$raw_n3e2<*1*><0> branch_result state_bank3$branch_result$raw_n401<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$_n231$raw_n2fc<*1*><1> state_bank3$_n317$raw_n3e2<*1*><1> branch_result state_bank3$branch_result$raw_n401<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$_n231$raw_n2fc<*2*><0> state_bank3$_n317$raw_n3e2<*2*><0> branch_result state_bank3$branch_result$raw_n401<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$_n231$raw_n2fc<*2*><1> state_bank3$_n317$raw_n3e2<*2*><1> branch_result state_bank3$branch_result$raw_n401<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$_n231$raw_n2fc<*3*><0> state_bank3$_n317$raw_n3e2<*3*><0> branch_result state_bank3$branch_result$raw_n401<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$_n231$raw_n2fc<*3*><1> state_bank3$_n317$raw_n3e2<*3*><1> branch_result state_bank3$branch_result$raw_n401<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n231$raw_n305<*0*><0> state_bank2$_n317$raw_n3eb<*0*><0> branch_result state_bank2$branch_result$raw_n40a<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n231$raw_n305<*0*><1> state_bank2$_n317$raw_n3eb<*0*><1> branch_result state_bank2$branch_result$raw_n40a<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n231$raw_n305<*1*><0> state_bank2$_n317$raw_n3eb<*1*><0> branch_result state_bank2$branch_result$raw_n40a<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n231$raw_n305<*1*><1> state_bank2$_n317$raw_n3eb<*1*><1> branch_result state_bank2$branch_result$raw_n40a<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n231$raw_n305<*2*><0> state_bank2$_n317$raw_n3eb<*2*><0> branch_result state_bank2$branch_result$raw_n40a<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n231$raw_n305<*2*><1> state_bank2$_n317$raw_n3eb<*2*><1> branch_result state_bank2$branch_result$raw_n40a<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n231$raw_n305<*3*><0> state_bank2$_n317$raw_n3eb<*3*><0> branch_result state_bank2$branch_result$raw_n40a<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$_n231$raw_n305<*3*><1> state_bank2$_n317$raw_n3eb<*3*><1> branch_result state_bank2$branch_result$raw_n40a<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n231$raw_n30e<*0*><0> state_bank1$_n317$raw_n3f4<*0*><0> branch_result state_bank1$branch_result$raw_n413<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n231$raw_n30e<*0*><1> state_bank1$_n317$raw_n3f4<*0*><1> branch_result state_bank1$branch_result$raw_n413<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n231$raw_n30e<*1*><0> state_bank1$_n317$raw_n3f4<*1*><0> branch_result state_bank1$branch_result$raw_n413<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n231$raw_n30e<*1*><1> state_bank1$_n317$raw_n3f4<*1*><1> branch_result state_bank1$branch_result$raw_n413<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n231$raw_n30e<*2*><0> state_bank1$_n317$raw_n3f4<*2*><0> branch_result state_bank1$branch_result$raw_n413<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n231$raw_n30e<*2*><1> state_bank1$_n317$raw_n3f4<*2*><1> branch_result state_bank1$branch_result$raw_n413<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n231$raw_n30e<*3*><0> state_bank1$_n317$raw_n3f4<*3*><0> branch_result state_bank1$branch_result$raw_n413<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$_n231$raw_n30e<*3*><1> state_bank1$_n317$raw_n3f4<*3*><1> branch_result state_bank1$branch_result$raw_n413<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231$raw_n2f3<*0*><0> state_bank0$_n317$raw_n3d9<*0*><0> branch_result state_bank0$branch_result$raw_n41c<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231$raw_n2f3<*0*><1> state_bank0$_n317$raw_n3d9<*0*><1> branch_result state_bank0$branch_result$raw_n41c<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231$raw_n2f3<*1*><0> state_bank0$_n317$raw_n3d9<*1*><0> branch_result state_bank0$branch_result$raw_n41c<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231$raw_n2f3<*1*><1> state_bank0$_n317$raw_n3d9<*1*><1> branch_result state_bank0$branch_result$raw_n41c<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231$raw_n2f3<*2*><0> state_bank0$_n317$raw_n3d9<*2*><0> branch_result state_bank0$branch_result$raw_n41c<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231$raw_n2f3<*2*><1> state_bank0$_n317$raw_n3d9<*2*><1> branch_result state_bank0$branch_result$raw_n41c<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231$raw_n2f3<*3*><0> state_bank0$_n317$raw_n3d9<*3*><0> branch_result state_bank0$branch_result$raw_n41c<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$_n231$raw_n2f3<*3*><1> state_bank0$_n317$raw_n3d9<*3*><1> branch_result state_bank0$branch_result$raw_n41c<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (update ) +.names state_bank3$branch_result$raw_n401<*0*><0> state_bank3<*0*><0> update state_bank3$update$raw_n435<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$branch_result$raw_n401<*0*><1> state_bank3<*0*><1> update state_bank3$update$raw_n435<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$branch_result$raw_n401<*1*><0> state_bank3<*1*><0> update state_bank3$update$raw_n435<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$branch_result$raw_n401<*1*><1> state_bank3<*1*><1> update state_bank3$update$raw_n435<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$branch_result$raw_n401<*2*><0> state_bank3<*2*><0> update state_bank3$update$raw_n435<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$branch_result$raw_n401<*2*><1> state_bank3<*2*><1> update state_bank3$update$raw_n435<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$branch_result$raw_n401<*3*><0> state_bank3<*3*><0> update state_bank3$update$raw_n435<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank3$branch_result$raw_n401<*3*><1> state_bank3<*3*><1> update state_bank3$update$raw_n435<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$branch_result$raw_n40a<*0*><0> state_bank2<*0*><0> update state_bank2$update$raw_n43e<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$branch_result$raw_n40a<*0*><1> state_bank2<*0*><1> update state_bank2$update$raw_n43e<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$branch_result$raw_n40a<*1*><0> state_bank2<*1*><0> update state_bank2$update$raw_n43e<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$branch_result$raw_n40a<*1*><1> state_bank2<*1*><1> update state_bank2$update$raw_n43e<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$branch_result$raw_n40a<*2*><0> state_bank2<*2*><0> update state_bank2$update$raw_n43e<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$branch_result$raw_n40a<*2*><1> state_bank2<*2*><1> update state_bank2$update$raw_n43e<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$branch_result$raw_n40a<*3*><0> state_bank2<*3*><0> update state_bank2$update$raw_n43e<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank2$branch_result$raw_n40a<*3*><1> state_bank2<*3*><1> update state_bank2$update$raw_n43e<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$branch_result$raw_n413<*0*><0> state_bank1<*0*><0> update state_bank1$update$raw_n447<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$branch_result$raw_n413<*0*><1> state_bank1<*0*><1> update state_bank1$update$raw_n447<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$branch_result$raw_n413<*1*><0> state_bank1<*1*><0> update state_bank1$update$raw_n447<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$branch_result$raw_n413<*1*><1> state_bank1<*1*><1> update state_bank1$update$raw_n447<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$branch_result$raw_n413<*2*><0> state_bank1<*2*><0> update state_bank1$update$raw_n447<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$branch_result$raw_n413<*2*><1> state_bank1<*2*><1> update state_bank1$update$raw_n447<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$branch_result$raw_n413<*3*><0> state_bank1<*3*><0> update state_bank1$update$raw_n447<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank1$branch_result$raw_n413<*3*><1> state_bank1<*3*><1> update state_bank1$update$raw_n447<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$branch_result$raw_n41c<*0*><0> state_bank0<*0*><0> update state_bank0$update$raw_n450<*0*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$branch_result$raw_n41c<*0*><1> state_bank0<*0*><1> update state_bank0$update$raw_n450<*0*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$branch_result$raw_n41c<*1*><0> state_bank0<*1*><0> update state_bank0$update$raw_n450<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$branch_result$raw_n41c<*1*><1> state_bank0<*1*><1> update state_bank0$update$raw_n450<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$branch_result$raw_n41c<*2*><0> state_bank0<*2*><0> update state_bank0$update$raw_n450<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$branch_result$raw_n41c<*2*><1> state_bank0<*2*><1> update state_bank0$update$raw_n450<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$branch_result$raw_n41c<*3*><0> state_bank0<*3*><0> update state_bank0$update$raw_n450<*3*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state_bank0$branch_result$raw_n41c<*3*><1> state_bank0<*3*><1> update state_bank0$update$raw_n450<*3*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names _n22f _n230 _n235 _n25a _n27f _n31b _n340 _n365 _n459 +.def 0 + 1 1 0 0 0 - - - 1 + 1 0 - - - 0 0 0 1 +.names _n459 state_bank3$update$raw_n435<*0*><0> state_bank3$update$raw_n435<*0*><1> state_bank3<*0*><0> state_bank3<*0*><1> -> _n45a<*0*><0> _n45a<*0*><1> +1 - - - - =state_bank3$update$raw_n435<*0*><0> =state_bank3$update$raw_n435<*0*><1> +0 - - - - =state_bank3<*0*><0> =state_bank3<*0*><1> +.names _n459 state_bank3$update$raw_n435<*1*><0> state_bank3$update$raw_n435<*1*><1> state_bank3<*1*><0> state_bank3<*1*><1> -> _n45a<*1*><0> _n45a<*1*><1> +1 - - - - =state_bank3$update$raw_n435<*1*><0> =state_bank3$update$raw_n435<*1*><1> +0 - - - - =state_bank3<*1*><0> =state_bank3<*1*><1> +.names _n459 state_bank3$update$raw_n435<*2*><0> state_bank3$update$raw_n435<*2*><1> state_bank3<*2*><0> state_bank3<*2*><1> -> _n45a<*2*><0> _n45a<*2*><1> +1 - - - - =state_bank3$update$raw_n435<*2*><0> =state_bank3$update$raw_n435<*2*><1> +0 - - - - =state_bank3<*2*><0> =state_bank3<*2*><1> +.names _n459 state_bank3$update$raw_n435<*3*><0> state_bank3$update$raw_n435<*3*><1> state_bank3<*3*><0> state_bank3<*3*><1> -> _n45a<*3*><0> _n45a<*3*><1> +1 - - - - =state_bank3$update$raw_n435<*3*><0> =state_bank3$update$raw_n435<*3*><1> +0 - - - - =state_bank3<*3*><0> =state_bank3<*3*><1> +.names _n22f _n230 _n235 _n25a _n27f _n31b _n340 _n365 _n45b +.def 0 + 1 1 0 0 1 - - - 1 + 1 0 - - - 0 0 1 1 +.names _n45b state_bank2$update$raw_n43e<*0*><0> state_bank2$update$raw_n43e<*0*><1> state_bank2<*0*><0> state_bank2<*0*><1> -> _n45c<*0*><0> _n45c<*0*><1> +1 - - - - =state_bank2$update$raw_n43e<*0*><0> =state_bank2$update$raw_n43e<*0*><1> +0 - - - - =state_bank2<*0*><0> =state_bank2<*0*><1> +.names _n45b state_bank2$update$raw_n43e<*1*><0> state_bank2$update$raw_n43e<*1*><1> state_bank2<*1*><0> state_bank2<*1*><1> -> _n45c<*1*><0> _n45c<*1*><1> +1 - - - - =state_bank2$update$raw_n43e<*1*><0> =state_bank2$update$raw_n43e<*1*><1> +0 - - - - =state_bank2<*1*><0> =state_bank2<*1*><1> +.names _n45b state_bank2$update$raw_n43e<*2*><0> state_bank2$update$raw_n43e<*2*><1> state_bank2<*2*><0> state_bank2<*2*><1> -> _n45c<*2*><0> _n45c<*2*><1> +1 - - - - =state_bank2$update$raw_n43e<*2*><0> =state_bank2$update$raw_n43e<*2*><1> +0 - - - - =state_bank2<*2*><0> =state_bank2<*2*><1> +.names _n45b state_bank2$update$raw_n43e<*3*><0> state_bank2$update$raw_n43e<*3*><1> state_bank2<*3*><0> state_bank2<*3*><1> -> _n45c<*3*><0> _n45c<*3*><1> +1 - - - - =state_bank2$update$raw_n43e<*3*><0> =state_bank2$update$raw_n43e<*3*><1> +0 - - - - =state_bank2<*3*><0> =state_bank2<*3*><1> +.names _n22f _n230 _n235 _n25a _n31b _n340 _n45d +.def 0 + 1 1 0 1 - - 1 + 1 0 - - 0 1 1 +.names _n45d state_bank1$update$raw_n447<*0*><0> state_bank1$update$raw_n447<*0*><1> state_bank1<*0*><0> state_bank1<*0*><1> -> _n45e<*0*><0> _n45e<*0*><1> +1 - - - - =state_bank1$update$raw_n447<*0*><0> =state_bank1$update$raw_n447<*0*><1> +0 - - - - =state_bank1<*0*><0> =state_bank1<*0*><1> +.names _n45d state_bank1$update$raw_n447<*1*><0> state_bank1$update$raw_n447<*1*><1> state_bank1<*1*><0> state_bank1<*1*><1> -> _n45e<*1*><0> _n45e<*1*><1> +1 - - - - =state_bank1$update$raw_n447<*1*><0> =state_bank1$update$raw_n447<*1*><1> +0 - - - - =state_bank1<*1*><0> =state_bank1<*1*><1> +.names _n45d state_bank1$update$raw_n447<*2*><0> state_bank1$update$raw_n447<*2*><1> state_bank1<*2*><0> state_bank1<*2*><1> -> _n45e<*2*><0> _n45e<*2*><1> +1 - - - - =state_bank1$update$raw_n447<*2*><0> =state_bank1$update$raw_n447<*2*><1> +0 - - - - =state_bank1<*2*><0> =state_bank1<*2*><1> +.names _n45d state_bank1$update$raw_n447<*3*><0> state_bank1$update$raw_n447<*3*><1> state_bank1<*3*><0> state_bank1<*3*><1> -> _n45e<*3*><0> _n45e<*3*><1> +1 - - - - =state_bank1$update$raw_n447<*3*><0> =state_bank1$update$raw_n447<*3*><1> +0 - - - - =state_bank1<*3*><0> =state_bank1<*3*><1> +.names _n1d3 _n1de _n1f3 _n208 _n21d _n45f +.def 0 + 1 1 - - - 1 + 1 0 - - - 1 + 1 - 1 - - 1 + 1 - 0 - - 1 + 1 - - 1 - 1 + 1 - - 0 - 1 + 1 - - - 1 1 + 1 - - - 0 1 +.names _n45f prediction$_n1d2$raw_n22a<0> prediction$_n1d2$raw_n22a<1> prediction$_n1d2$raw_n22a<2> prediction$_n1d2$raw_n22a<3> prediction<0> prediction<1> prediction<2> prediction<3> -> _n460<0> _n460<1> _n460<2> _n460<3> +1 - - - - - - - - =prediction$_n1d2$raw_n22a<0> =prediction$_n1d2$raw_n22a<1> =prediction$_n1d2$raw_n22a<2> =prediction$_n1d2$raw_n22a<3> +0 - - - - - - - - =prediction<0> =prediction<1> =prediction<2> =prediction<3> +.names _n22f _n230 _n235 _n31b _n461 +.def 0 + 1 1 1 - 1 + 1 0 - 1 1 +.names _n461 state_bank0$update$raw_n450<*0*><0> state_bank0$update$raw_n450<*0*><1> state_bank0<*0*><0> state_bank0<*0*><1> -> _n462<*0*><0> _n462<*0*><1> +1 - - - - =state_bank0$update$raw_n450<*0*><0> =state_bank0$update$raw_n450<*0*><1> +0 - - - - =state_bank0<*0*><0> =state_bank0<*0*><1> +.names _n461 state_bank0$update$raw_n450<*1*><0> state_bank0$update$raw_n450<*1*><1> state_bank0<*1*><0> state_bank0<*1*><1> -> _n462<*1*><0> _n462<*1*><1> +1 - - - - =state_bank0$update$raw_n450<*1*><0> =state_bank0$update$raw_n450<*1*><1> +0 - - - - =state_bank0<*1*><0> =state_bank0<*1*><1> +.names _n461 state_bank0$update$raw_n450<*2*><0> state_bank0$update$raw_n450<*2*><1> state_bank0<*2*><0> state_bank0<*2*><1> -> _n462<*2*><0> _n462<*2*><1> +1 - - - - =state_bank0$update$raw_n450<*2*><0> =state_bank0$update$raw_n450<*2*><1> +0 - - - - =state_bank0<*2*><0> =state_bank0<*2*><1> +.names _n461 state_bank0$update$raw_n450<*3*><0> state_bank0$update$raw_n450<*3*><1> state_bank0<*3*><0> state_bank0<*3*><1> -> _n462<*3*><0> _n462<*3*><1> +1 - - - - =state_bank0$update$raw_n450<*3*><0> =state_bank0$update$raw_n450<*3*><1> +0 - - - - =state_bank0<*3*><0> =state_bank0<*3*><1> +# non-blocking assignments +# latches +.r state_bank3$raw_n1b4<*0*><0> state_bank3<*0*><0> +.def 0 +1 1 +.r state_bank3$raw_n1b4<*1*><0> state_bank3<*1*><0> +.def 0 +1 1 +.r state_bank3$raw_n1b4<*2*><0> state_bank3<*2*><0> +.def 0 +1 1 +.r state_bank3$raw_n1b4<*3*><0> state_bank3<*3*><0> +.def 0 +1 1 +.r state_bank3$raw_n1b4<*0*><1> state_bank3<*0*><1> +.def 0 +1 1 +.r state_bank3$raw_n1b4<*1*><1> state_bank3<*1*><1> +.def 0 +1 1 +.r state_bank3$raw_n1b4<*2*><1> state_bank3<*2*><1> +.def 0 +1 1 +.r state_bank3$raw_n1b4<*3*><1> state_bank3<*3*><1> +.def 0 +1 1 +.latch _n45a<*0*><0> state_bank3<*0*><0> +.latch _n45a<*1*><0> state_bank3<*1*><0> +.latch _n45a<*2*><0> state_bank3<*2*><0> +.latch _n45a<*3*><0> state_bank3<*3*><0> +.latch _n45a<*0*><1> state_bank3<*0*><1> +.latch _n45a<*1*><1> state_bank3<*1*><1> +.latch _n45a<*2*><1> state_bank3<*2*><1> +.latch _n45a<*3*><1> state_bank3<*3*><1> +.r state_bank2$raw_n198<*0*><0> state_bank2<*0*><0> +.def 0 +1 1 +.r state_bank2$raw_n198<*1*><0> state_bank2<*1*><0> +.def 0 +1 1 +.r state_bank2$raw_n198<*2*><0> state_bank2<*2*><0> +.def 0 +1 1 +.r state_bank2$raw_n198<*3*><0> state_bank2<*3*><0> +.def 0 +1 1 +.r state_bank2$raw_n198<*0*><1> state_bank2<*0*><1> +.def 0 +1 1 +.r state_bank2$raw_n198<*1*><1> state_bank2<*1*><1> +.def 0 +1 1 +.r state_bank2$raw_n198<*2*><1> state_bank2<*2*><1> +.def 0 +1 1 +.r state_bank2$raw_n198<*3*><1> state_bank2<*3*><1> +.def 0 +1 1 +.latch _n45c<*0*><0> state_bank2<*0*><0> +.latch _n45c<*1*><0> state_bank2<*1*><0> +.latch _n45c<*2*><0> state_bank2<*2*><0> +.latch _n45c<*3*><0> state_bank2<*3*><0> +.latch _n45c<*0*><1> state_bank2<*0*><1> +.latch _n45c<*1*><1> state_bank2<*1*><1> +.latch _n45c<*2*><1> state_bank2<*2*><1> +.latch _n45c<*3*><1> state_bank2<*3*><1> +.r prediction$raw_n1d0<0> prediction<0> +.def 0 +1 1 +.r prediction$raw_n1d0<1> prediction<1> +.def 0 +1 1 +.r prediction$raw_n1d0<2> prediction<2> +.def 0 +1 1 +.r prediction$raw_n1d0<3> prediction<3> +.def 0 +1 1 +.latch _n460<0> prediction<0> +.latch _n460<1> prediction<1> +.latch _n460<2> prediction<2> +.latch _n460<3> prediction<3> +.r state_bank1$raw_n17c<*0*><0> state_bank1<*0*><0> +.def 0 +1 1 +.r state_bank1$raw_n17c<*1*><0> state_bank1<*1*><0> +.def 0 +1 1 +.r state_bank1$raw_n17c<*2*><0> state_bank1<*2*><0> +.def 0 +1 1 +.r state_bank1$raw_n17c<*3*><0> state_bank1<*3*><0> +.def 0 +1 1 +.r state_bank1$raw_n17c<*0*><1> state_bank1<*0*><1> +.def 0 +1 1 +.r state_bank1$raw_n17c<*1*><1> state_bank1<*1*><1> +.def 0 +1 1 +.r state_bank1$raw_n17c<*2*><1> state_bank1<*2*><1> +.def 0 +1 1 +.r state_bank1$raw_n17c<*3*><1> state_bank1<*3*><1> +.def 0 +1 1 +.latch _n45e<*0*><0> state_bank1<*0*><0> +.latch _n45e<*1*><0> state_bank1<*1*><0> +.latch _n45e<*2*><0> state_bank1<*2*><0> +.latch _n45e<*3*><0> state_bank1<*3*><0> +.latch _n45e<*0*><1> state_bank1<*0*><1> +.latch _n45e<*1*><1> state_bank1<*1*><1> +.latch _n45e<*2*><1> state_bank1<*2*><1> +.latch _n45e<*3*><1> state_bank1<*3*><1> +.r state_bank0$raw_n160<*0*><0> state_bank0<*0*><0> +.def 0 +1 1 +.r state_bank0$raw_n160<*1*><0> state_bank0<*1*><0> +.def 0 +1 1 +.r state_bank0$raw_n160<*2*><0> state_bank0<*2*><0> +.def 0 +1 1 +.r state_bank0$raw_n160<*3*><0> state_bank0<*3*><0> +.def 0 +1 1 +.r state_bank0$raw_n160<*0*><1> state_bank0<*0*><1> +.def 0 +1 1 +.r state_bank0$raw_n160<*1*><1> state_bank0<*1*><1> +.def 0 +1 1 +.r state_bank0$raw_n160<*2*><1> state_bank0<*2*><1> +.def 0 +1 1 +.r state_bank0$raw_n160<*3*><1> state_bank0<*3*><1> +.def 0 +1 1 +.latch _n462<*0*><0> state_bank0<*0*><0> +.latch _n462<*1*><0> state_bank0<*1*><0> +.latch _n462<*2*><0> state_bank0<*2*><0> +.latch _n462<*3*><0> state_bank0<*3*><0> +.latch _n462<*0*><1> state_bank0<*0*><1> +.latch _n462<*1*><1> state_bank0<*1*><1> +.latch _n462<*2*><1> state_bank0<*2*><1> +.latch _n462<*3*><1> state_bank0<*3*><1> +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/bpb/bpb.v =================================================================== --- vis_dev/vis-2.1/examples/bpb/bpb.v (revision 11) +++ vis_dev/vis-2.1/examples/bpb/bpb.v (revision 11) @@ -0,0 +1,88 @@ +module branchPredictionBuffer(clock,stall,inst_addr,update,branch_result,buffer_addr,buffer_offset, prediction); + parameter PRED_BUFFER_SIZE = 4; // 128 lines with 4 entries/line + parameter PRED_BUFFER_BITS = 2; + input [PRED_BUFFER_BITS-1:0] inst_addr; // We need to decode up to 4 instructions. + input branch_result; // Result of a branch calculation. + input [PRED_BUFFER_BITS-1:0] buffer_addr; + input [1:0] buffer_offset; + input clock; + input stall; // Stalls when instructions are not available. + input update; // Tells the buffer that an update is ready. + output [3:0] prediction; // Prediction bits sent out to decoder stage. + + reg [3:0] prediction; + reg [1:0] state_bank0 [PRED_BUFFER_SIZE-1:0]; + reg [1:0] state_bank1 [PRED_BUFFER_SIZE-1:0]; + reg [1:0] state_bank2 [PRED_BUFFER_SIZE-1:0]; + reg [1:0] state_bank3 [PRED_BUFFER_SIZE-1:0]; + + + integer i; + + // synopsys translate_off + // Always begin in a weak, not taken state + initial begin + for (i=0; i 1) + prediction[3] = 1; + else + prediction[3] = 0; + if (state_bank2[inst_addr] > 1) + prediction[2] = 1; + else + prediction[2] = 0; + if (state_bank1[inst_addr] > 1) + prediction[1] = 1; + else + prediction[1] = 0; + if (state_bank0[inst_addr] > 1) + prediction[0] = 1; + else + prediction[0] = 0; + end // if (!stall) + end // always @ (posedge clock && !stall) + + + // Assuming here that reading and updating occur at different parts of + // the clock cycle. We only need to update one location at a time. + always @(negedge clock) begin + if (update) begin + if (branch_result) begin // The branch was taken. + if (buffer_offset == 0) + state_bank0[buffer_addr] = state_bank0[buffer_addr] + 1; + else if (buffer_offset == 1) + state_bank1[buffer_addr] = state_bank1[buffer_addr] + 1; + else if (buffer_offset == 2) + state_bank2[buffer_addr] = state_bank2[buffer_addr] + 1; + else + state_bank3[buffer_addr] = state_bank3[buffer_addr] + 1; + end // if (branch_result) + + else begin + if (buffer_offset == 0) + state_bank0[buffer_addr] = state_bank0[buffer_addr] - 1; + else if (buffer_offset == 1) + state_bank1[buffer_addr] = state_bank1[buffer_addr] - 1; + else if (buffer_offset == 2) + state_bank2[buffer_addr] = state_bank2[buffer_addr] - 1; + else + state_bank3[buffer_addr] = state_bank3[buffer_addr] - 1; + end // else: !if(branch_result) + end // if (update) + end // always @ (negedge clock && !stall && update) + + +endmodule // branchPredictionBuffer Index: vis_dev/vis-2.1/examples/bpb/check_result =================================================================== --- vis_dev/vis-2.1/examples/bpb/check_result (revision 11) +++ vis_dev/vis-2.1/examples/bpb/check_result (revision 11) @@ -0,0 +1,2 @@ +FSM depth = 32 +reachable states = 6.87195e+10 Index: vis_dev/vis-2.1/examples/bpb/check_script =================================================================== --- vis_dev/vis-2.1/examples/bpb/check_script (revision 11) +++ vis_dev/vis-2.1/examples/bpb/check_script (revision 11) @@ -0,0 +1,7 @@ +read_blif_mv bpb.mv +flatten_hierarchy +static_order +dynamic_var_ordering -e sift +build_partition_mdds +compute_reach -s 1 -v 1 +quit -s Index: vis_dev/vis-2.1/examples/coherence/LISTOFPROPERTIES =================================================================== --- vis_dev/vis-2.1/examples/coherence/LISTOFPROPERTIES (revision 11) +++ vis_dev/vis-2.1/examples/coherence/LISTOFPROPERTIES (revision 11) @@ -0,0 +1,16 @@ +Here is a list of properties to check: +1) Liveness: If a processor requests a read then it will eventually be +serviced. + +2) Safety: If a cache has exclusive access to a block, then the other cache + has no access to that block + +3) Safety: If the block is in state SHARED in the cache controller, its corresponding + bit is set in the Rlist of the directory. + +4) Safety: If the block is in state EXCLUSIVE in the cache controller, its corresponding + bit is set in the Wlist of the directory + + + + Index: vis_dev/vis-2.1/examples/coherence/README =================================================================== --- vis_dev/vis-2.1/examples/coherence/README (revision 11) +++ vis_dev/vis-2.1/examples/coherence/README (revision 11) @@ -0,0 +1,16 @@ +Here is a list of properties to check: +1) Liveness: If a processor requests a read then it will eventually be +serviced. + +2) Safety: If a cache has exclusive access to a block, then the other cache + has no access to that block + +3) Safety: If the block is in state SHARED in the cache controller, its corresponding + bit is set in the Rlist of the directory. + +4) Safety: If the block is in state EXCLUSIVE in the cache controller, its corresponding + bit is set in the Wlist of the directory + + + + Index: vis_dev/vis-2.1/examples/coherence/cache_ctrl.v =================================================================== --- vis_dev/vis-2.1/examples/coherence/cache_ctrl.v (revision 11) +++ vis_dev/vis-2.1/examples/coherence/cache_ctrl.v (revision 11) @@ -0,0 +1,175 @@ +module CACHE_CTRLER ( + clk, + read_req, write_req, data, address, // input: requests from processor + acknowledge, // output: to processor + write_back_req, inval, blocknum, // input: requests from directory + blk_ok, blk_data, // input: answers from directory + back_data, cache_req,blk_add, // output: to directory + ); + +input clk; +input read_req, write_req, data; // input: requests from processor +input [`address_size:0] address; // input: requests from processor +input [`address_size:0] blocknum; // input: requests from directory +input write_back_req, inval; // input: requests from directory +input blk_ok, blk_data; // input: answers from directory +output acknowledge; // output: to processor +output back_data; // output: to directory +output cache_req; // output: to directory +output [`address_size:0] blk_add; // output: to directory + +Cache_reqstatus reg cache_req; +wire back_data; +wire acknowledge; +reg blk_add; + + +// Registers local to the cache controler +Block_status reg block_state; +Cache_status reg cache_state; +reg [`address_size:0] block_add; // memory address of the block +reg block_val; // value of the block + +initial begin + cache_state = Ready; + block_state = INVALID; + block_add = 0; + block_val = 0; + blk_add = 0; + cache_req = noop; +end + +assign back_data =(cache_req==ok)?block_val:0; +assign acknowledge = ((cache_state == Rgrant)||(cache_state == Wgrant))?1:0; + +always @(posedge clk) begin + + +case ( cache_state ) + Ready: begin //ready to service a directory request + if ((inval)&&(block_add ==blocknum)) // block invalidation request + begin + block_state = INVALID ; + cache_req = ok; + cache_state = Ready; + end + else if (write_back_req) + begin + block_state = SHARED ; + cache_req = ok; + cache_state = Ready; + end + else if (read_req) + begin + if ((block_add != address) || (block_state == INVALID)) + begin // read miss + cache_req = blk_rreq; // ask to read block from memory + blk_add = address; + cache_state = Rwait; + block_state = INVALID; //invalidates if replacement + end + else + begin // read hit + cache_state = Rgrant; + cache_req = noop; + end + end + else if (write_req) + begin + if ((block_add != address) || (block_state != EXCLUSIVE)) + begin // write miss + cache_req = blk_excl; // ask exclusive block from memory + blk_add = address; + cache_state = Wwait; + block_state = INVALID; //invalidates if replacement + end + else + begin // write hit + cache_state = Wgrant; + cache_req = noop; + end + end + else + begin + cache_req = noop; + blk_add = 0; + end + end + + Rgrant: begin // read acknowledge to processor + if ((inval)&&(block_add == blocknum)) + begin + block_state = INVALID; + cache_req = ok; + cache_state = Ready; + end + else + begin + cache_state = Ready; + end + end + + Wgrant: begin + if ((inval)&&(block_add == blocknum)) + begin + block_state = INVALID; + cache_req = ok; + cache_state = Ready; + end + else + begin + block_val = data; + cache_state = Ready; + end + end + + Rwait: begin + if ((inval)&&(block_add == blocknum)) + begin + block_state = INVALID; + cache_req = ok; + cache_state = Ready; + end + else if (write_back_req) + begin + cache_state = Ready; + //cache_req = ok; + end + else if ( blk_ok ) + begin + block_val = blk_data; + block_add = blk_add; + block_state = SHARED; + cache_req = noop; + cache_state = Rgrant; + end + else cache_state = Rwait; + end + + Wwait: begin + if ((inval)&&(block_add == blocknum)) + begin + block_state = INVALID; + cache_req = ok; + cache_state = Ready; + end + else if (write_back_req) + begin + cache_state = Ready; + //cache_req = ok; + end + else if ( blk_ok ) + begin + block_val = blk_data; + block_add = blk_add; + block_state = EXCLUSIVE; + cache_req = noop; + cache_state = Wgrant; + end + else cache_state = Wwait; + end + + default: cache_req = noop; + endcase; +end // end of always statement describing cache controller automaton +endmodule Index: vis_dev/vis-2.1/examples/coherence/check_result =================================================================== --- vis_dev/vis-2.1/examples/coherence/check_result (revision 11) +++ vis_dev/vis-2.1/examples/coherence/check_result (revision 11) @@ -0,0 +1,1 @@ +# AMC: Verified formula FALSE at level 9 of 9 : Index: vis_dev/vis-2.1/examples/coherence/check_script =================================================================== --- vis_dev/vis-2.1/examples/coherence/check_script (revision 11) +++ vis_dev/vis-2.1/examples/coherence/check_script (revision 11) @@ -0,0 +1,9 @@ +read_blif_mv coherence.mv +flatten_hierarchy +static_order +build_partition_mdds +set amc_sizeof_group 8 +set amc_prove_false +approximate_model_check coherence2.ctl +time +quit -s Index: vis_dev/vis-2.1/examples/coherence/coh-order =================================================================== --- vis_dev/vis-2.1/examples/coherence/coh-order (revision 11) +++ vis_dev/vis-2.1/examples/coherence/coh-order (revision 11) @@ -0,0 +1,61 @@ +# vis release 1.1 (compiled 25-Apr-96 at 11:35 AM) +# network name: COHERANCE +# generated: Tue May 14 18:26:43 1996 +# +# name type mddId vals levs +proc1.proc_state latch 1 3 (0, 1) +proc1.proc_state$NS shadow 2 3 (2, 3) +inst1 primary-input 0 3 (4, 5) +cc1.cache_state latch 3 5 (6, 7, 8) +cc1.cache_state$NS shadow 4 5 (9, 10, 11) +cache_req1 latch 10 4 (12, 13) +cache_req1$NS shadow 11 4 (14, 15) +cc1.block_state latch 31 3 (20, 21) +cc1.block_state$NS shadow 32 3 (22, 23) +direc.arbiter_state latch 46 6 (24, 25, 26) +direc.arbiter_state$NS shadow 47 6 (27, 28, 29) +any_address1<0> primary-input 7 2 (30) +blk_add1<0> latch 8 2 (31) +blk_add1<0>$NS shadow 9 2 (32) +direc.cache_Wlist1<*1*> latch 20 2 (33) +direc.cache_Wlist1<*1*>$NS shadow 21 2 (34) +cc1.block_add<0> latch 5 2 (35) +cc1.block_add<0>$NS shadow 6 2 (36) +direc.cache_Wlist1<*0*> latch 22 2 (37) +direc.cache_Wlist1<*0*>$NS shadow 23 2 (38) +direc.cache_Rlist1<*1*> latch 24 2 (39) +direc.cache_Rlist1<*1*>$NS shadow 25 2 (40) +direc.cache_Rlist1<*0*> latch 26 2 (41) +direc.cache_Rlist1<*0*>$NS shadow 27 2 (42) +direc.cache_Rlist2<*0*> latch 16 2 (43) +direc.cache_Rlist2<*0*>$NS shadow 17 2 (44) +cc1.block_val latch 28 2 (45) +cc1.block_val$NS shadow 29 2 (46) +any_value1 primary-input 30 2 (47) +direc.main_mem<*0*> latch 42 2 (48) +direc.main_mem<*0*>$NS shadow 43 2 (49) +direc.main_mem<*1*> latch 40 2 (50) +direc.main_mem<*1*>$NS shadow 41 2 (51) +cc2.block_val latch 37 2 (52) +cc2.block_val$NS shadow 38 2 (53) +any_value2 primary-input 39 2 (54) +cc2.block_add<0> latch 53 2 (55) +cc2.block_add<0>$NS shadow 54 2 (56) +direc.cache_Rlist2<*1*> latch 18 2 (57) +direc.cache_Rlist2<*1*>$NS shadow 19 2 (58) +any_address2<0> primary-input 55 2 (59) +cc2.block_state latch 44 3 (60, 61) +cc2.block_state$NS shadow 45 3 (62, 63) +direc.cache_Wlist2<*0*> latch 14 2 (64) +direc.cache_Wlist2<*0*>$NS shadow 15 2 (65) +direc.cache_Wlist2<*1*> latch 12 2 (66) +direc.cache_Wlist2<*1*>$NS shadow 13 2 (67) +blk_add2<0> latch 33 2 (68) +blk_add2<0>$NS shadow 34 2 (69) +proc2.proc_state latch 49 3 (70, 71) +proc2.proc_state$NS shadow 50 3 (72, 73) +inst2 primary-input 48 3 (74, 75) +cc2.cache_state latch 51 5 (80, 81, 82) +cc2.cache_state$NS shadow 52 5 (83, 84, 85) +cache_req2 latch 35 4 (86, 87) +cache_req2$NS shadow 36 4 (88, 89) Index: vis_dev/vis-2.1/examples/coherence/coherence.mv =================================================================== --- vis_dev/vis-2.1/examples/coherence/coherence.mv (revision 11) +++ vis_dev/vis-2.1/examples/coherence/coherence.mv (revision 11) @@ -0,0 +1,3710 @@ +# vl2mv coherence.v +# version: 0.2 +# date: 10:43:41 05/16/96 (PDT) +.model COHERANCE +# I/O ports +.inputs any_value2 +.inputs any_address2<0> +.inputs any_value1 +.inputs any_address1<0> +.inputs inst2 +.inputs inst1 + +.mv cache_req2 4 ok blk_rreq blk_excl noop +.mv cache_req1 4 ok blk_rreq blk_excl noop +.mv inst2 3 COMPUTE READ_WORD WRITE_WORD +.mv inst1 3 COMPUTE READ_WORD WRITE_WORD +.subckt PROC proc1 read_req=read_req1 write_req=write_req1 data=data1 address<0>=address1<0> acknowledge=acknowledge1 any_address<0>=any_address1<0> any_value=any_value1 inst=inst1 +.subckt CACHE_CTRLER cc1 read_req=read_req1 write_req=write_req1 data=data1 address<0>=address1<0> acknowledge=acknowledge1 write_back_req=write_back_req1 inval=inval1 blocknum<0>=blocknum<0> blk_ok=blk_ok1 blk_data=blk_data back_data=back_data1 cache_req=cache_req1 blk_add<0>=blk_add1<0> +.subckt PROC proc2 read_req=read_req2 write_req=write_req2 data=data2 address<0>=address2<0> acknowledge=acknowledge2 any_address<0>=any_address2<0> any_value=any_value2 inst=inst2 +.subckt CACHE_CTRLER cc2 read_req=read_req2 write_req=write_req2 data=data2 address<0>=address2<0> acknowledge=acknowledge2 write_back_req=write_back_req2 inval=inval2 blocknum<0>=blocknum<0> blk_ok=blk_ok2 blk_data=blk_data back_data=back_data2 cache_req=cache_req2 blk_add<0>=blk_add2<0> +.subckt DIRECTORY direc write_back_req1=write_back_req1 inval1=inval1 write_back_req2=write_back_req2 inval2=inval2 blocknum<0>=blocknum<0> blk_ok1=blk_ok1 blk_data=blk_data blk_ok2=blk_ok2 back_data1=back_data1 cache_req1=cache_req1 blk_add1<0>=blk_add1<0> back_data2=back_data2 cache_req2=cache_req2 blk_add2<0>=blk_add2<0> +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model PROC +# I/O ports +.inputs inst +.inputs any_value +.outputs write_req +.outputs read_req +.inputs any_address<0> +.outputs address<0> +.outputs data +.inputs acknowledge + +.mv proc_state 3 IDLE READING WRITING +.mv inst 3 COMPUTE READ_WORD WRITE_WORD +# proc_state = 0 +.mv proc_state$raw_n0 3 IDLE READING WRITING +.names proc_state$raw_n0 +IDLE +# non-blocking assignments for initial +# assign read_req = ((proc_state == IDLE ) ? ((inst == READ_WORD ) ? 1 : 0) : ((proc_state == READING ) ? 1 : 0)) +.mv _n3 3 IDLE READING WRITING +.names _n3 +IDLE +# proc_state == 0 +.names proc_state _n3 _n2 +.def 0 +- =proc_state 1 +.mv _n5 3 COMPUTE READ_WORD WRITE_WORD +.names _n5 +READ_WORD +# inst == 1 +.names inst _n5 _n4 +.def 0 +- =inst 1 +.names _n6 +1 +.names _n7 +0 +# (inst == 1) ? 1 : 0 +.names _n6 _n7 _n4 _n8 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _nb 3 IDLE READING WRITING +.names _nb +READING +# proc_state == 1 +.names proc_state _nb _na +.def 0 +- =proc_state 1 +.names _nc +1 +.names _nd +0 +# (proc_state == 1) ? 1 : 0 +.names _nc _nd _na _ne +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# (proc_state == 0) ? ((inst == 1) ? 1 : 0) : ((proc_state == 1) ? 1 : 0) +.names _n8 _ne _n2 _n10 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n10 read_req$raw_n1 +- =_n10 +# assign write_req = ((proc_state == IDLE ) ? ((inst == WRITE_WORD ) ? 1 : 0) : ((proc_state == WRITING ) ? 1 : 0)) +.mv _n14 3 IDLE READING WRITING +.names _n14 +IDLE +# proc_state == 0 +.names proc_state _n14 _n13 +.def 0 +- =proc_state 1 +.mv _n16 3 COMPUTE READ_WORD WRITE_WORD +.names _n16 +WRITE_WORD +# inst == 2 +.names inst _n16 _n15 +.def 0 +- =inst 1 +.names _n17 +1 +.names _n18 +0 +# (inst == 2) ? 1 : 0 +.names _n17 _n18 _n15 _n19 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _n1c 3 IDLE READING WRITING +.names _n1c +WRITING +# proc_state == 2 +.names proc_state _n1c _n1b +.def 0 +- =proc_state 1 +.names _n1d +1 +.names _n1e +0 +# (proc_state == 2) ? 1 : 0 +.names _n1d _n1e _n1b _n1f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# (proc_state == 0) ? ((inst == 2) ? 1 : 0) : ((proc_state == 2) ? 1 : 0) +.names _n19 _n1f _n13 _n21 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n21 write_req$raw_n12 +- =_n21 +# assign data = any_value +.names any_value data$raw_n23 +- =any_value +# assign address = any_address +.names any_address<0> address$raw_n24<0> +- =any_address<0> +.mv _n27 3 IDLE READING WRITING +.names _n27 +IDLE +.names proc_state _n27 _n26 +.def 0 +- =proc_state 1 +.names _n26 _n25 +1 1 +0 0 +.mv _n2a 3 COMPUTE READ_WORD WRITE_WORD +.names _n2a +COMPUTE +.names inst _n2a _n29 +.def 0 +- =inst 1 +.names _n29 _n28 +1 1 +0 0 +# proc_state = 0 +.mv proc_state$_n28_n2b$true 3 IDLE READING WRITING +.names proc_state$_n28_n2b$true +IDLE +.mv _n2e 3 COMPUTE READ_WORD WRITE_WORD +.names _n2e +READ_WORD +.names inst _n2e _n2d +.def 0 +- =inst 1 +.names _n2d _n2c +1 1 +0 0 +# proc_state = 1 +.mv proc_state$_n2c_n2f$true 3 IDLE READING WRITING +.names proc_state$_n2c_n2f$true +READING +.mv _n32 3 COMPUTE READ_WORD WRITE_WORD +.names _n32 +WRITE_WORD +.names inst _n32 _n31 +.def 0 +- =inst 1 +.names _n31 _n30 +1 1 +0 0 +# proc_state = 2 +.mv proc_state$_n30_n33$true 3 IDLE READING WRITING +.names proc_state$_n30_n33$true +WRITING +# proc_state = 0 +.mv proc_state$raw_n34 3 IDLE READING WRITING +.names proc_state$raw_n34 +IDLE +# case (inst ) +.mv proc_state$_n30$raw_n36 3 IDLE READING WRITING +.names proc_state$_n30_n33$true proc_state$raw_n34 _n30 proc_state$_n30$raw_n36 +- - 0 =proc_state$raw_n34 +- - 1 =proc_state$_n30_n33$true +.mv proc_state$_n2c$raw_n3a 3 IDLE READING WRITING +.names proc_state$_n2c_n2f$true proc_state$_n30$raw_n36 _n2c proc_state$_n2c$raw_n3a +- - 0 =proc_state$_n30$raw_n36 +- - 1 =proc_state$_n2c_n2f$true +.mv proc_state$_n28$raw_n3e 3 IDLE READING WRITING +.names proc_state$_n28_n2b$true proc_state$_n2c$raw_n3a _n28 proc_state$_n28$raw_n3e +- - 0 =proc_state$_n2c$raw_n3a +- - 1 =proc_state$_n28_n2b$true +.mv _n43 3 IDLE READING WRITING +.names _n43 +READING +.names proc_state _n43 _n42 +.def 0 +- =proc_state 1 +.names _n42 _n41 +1 1 +0 0 +.names acknowledge _n44 +- =acknowledge +# proc_state = 0 +.mv proc_state$acknowledge_n45$true 3 IDLE READING WRITING +.names proc_state$acknowledge_n45$true +IDLE +# if/else (acknowledge ) +.mv proc_state$acknowledge$raw_n48 3 IDLE READING WRITING +.names proc_state$acknowledge_n45$true proc_state acknowledge proc_state$acknowledge$raw_n48 +- - 0 =proc_state +- - 1 =proc_state$acknowledge_n45$true +.mv _n4b 3 IDLE READING WRITING +.names _n4b +WRITING +.names proc_state _n4b _n4a +.def 0 +- =proc_state 1 +.names _n4a _n49 +1 1 +0 0 +.names acknowledge _n4c +- =acknowledge +# proc_state = 0 +.mv proc_state$acknowledge_n4d$true 3 IDLE READING WRITING +.names proc_state$acknowledge_n4d$true +IDLE +# if/else (acknowledge ) +.mv proc_state$acknowledge$raw_n50 3 IDLE READING WRITING +.names proc_state$acknowledge_n4d$true proc_state acknowledge proc_state$acknowledge$raw_n50 +- - 0 =proc_state +- - 1 =proc_state$acknowledge_n4d$true +# case (proc_state ) +.mv proc_state$_n49$raw_n53 3 IDLE READING WRITING +.names proc_state$acknowledge$raw_n50 proc_state _n49 proc_state$_n49$raw_n53 +- - 0 =proc_state +- - 1 =proc_state$acknowledge$raw_n50 +.mv proc_state$_n41$raw_n54 3 IDLE READING WRITING +.names proc_state$acknowledge$raw_n48 proc_state$_n49$raw_n53 _n41 proc_state$_n41$raw_n54 +- - 0 =proc_state$_n49$raw_n53 +- - 1 =proc_state$acknowledge$raw_n48 +.mv proc_state$_n25$raw_n58 3 IDLE READING WRITING +.names proc_state$_n28$raw_n3e proc_state$_n41$raw_n54 _n25 proc_state$_n25$raw_n58 +- - 0 =proc_state$_n41$raw_n54 +- - 1 =proc_state$_n28$raw_n3e +# conflict arbitrators +.names _n25 _n28 _n2c _n30 _n41 _n44 _n49 _n4c _n5c +.def 0 + 1 1 - - - - - - 1 + 1 0 1 - - - - - 1 + 1 0 0 1 - - - - 1 + 1 0 0 0 - - - - 1 + 0 - - - 1 1 - - 1 + 0 - - - 0 - 1 1 1 +.mv _n5d 3 IDLE READING WRITING +.names _n5c proc_state$_n25$raw_n58 proc_state _n5d +1 - - =proc_state$_n25$raw_n58 +0 - - =proc_state +.names write_req$raw_n12 write_req +0 0 +1 1 +.names read_req$raw_n1 read_req +0 0 +1 1 +.names address$raw_n24<0> address<0> +- =address$raw_n24<0> +.names data$raw_n23 data +0 0 +1 1 +# non-blocking assignments +# latches +.r proc_state$raw_n0 proc_state +- =proc_state$raw_n0 +.latch _n5d proc_state +# quasi-continuous assignment +.end + + +.model CACHE_CTRLER +# I/O ports +.outputs back_data +.inputs write_req +.outputs blk_add<0> +.inputs inval +.inputs blk_data +.inputs read_req +.inputs address<0> +.inputs data +.inputs blk_ok +.inputs blocknum<0> +.outputs cache_req +.inputs write_back_req +.outputs acknowledge + +.mv block_state 3 INVALID SHARED EXCLUSIVE +.mv cache_state 5 Ready Rwait Wwait Rgrant Wgrant +.mv cache_req 4 ok blk_rreq blk_excl noop +# cache_state = 0 +.mv cache_state$raw_n65 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$raw_n65 +Ready +# block_state = 0 +.mv block_state$raw_n66 3 INVALID SHARED EXCLUSIVE +.names block_state$raw_n66 +INVALID +# block_add = 0 +.names block_add$raw_n67<0> +0 +# block_val = 0 +.names block_val$raw_n68 +0 +# blk_add = 0 +.names blk_add$raw_n69<0> +0 +# cache_req = 3 +.mv cache_req$raw_n6a 4 ok blk_rreq blk_excl noop +.names cache_req$raw_n6a +noop +# non-blocking assignments for initial +# assign back_data = (cache_req == ok ) ? block_val : 0 +.mv _n6d 4 ok blk_rreq blk_excl noop +.names _n6d +ok +# cache_req == 0 +.names cache_req _n6d _n6c +.def 0 +- =cache_req 1 +.names _n6e +0 +# (cache_req == 0) ? block_val : 0 +.names block_val _n6e _n6c _n6f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n6f back_data$raw_n6b +- =_n6f +# assign acknowledge = ((cache_state == Rgrant ) || (cache_state == Wgrant )) ? 1 : 0 +.mv _n73 5 Ready Rwait Wwait Rgrant Wgrant +.names _n73 +Rgrant +# cache_state == 3 +.names cache_state _n73 _n72 +.def 0 +- =cache_state 1 +.mv _n75 5 Ready Rwait Wwait Rgrant Wgrant +.names _n75 +Wgrant +# cache_state == 4 +.names cache_state _n75 _n74 +.def 0 +- =cache_state 1 +# (cache_state == 3) || (cache_state == 4) +.names _n72 _n74 _n76 +.def 1 +0 0 0 +.names _n77 +1 +.names _n78 +0 +# ((cache_state == 3) || (cache_state == 4)) ? 1 : 0 +.names _n77 _n78 _n76 _n79 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n79 acknowledge$raw_n71 +- =_n79 +.mv _n7d 5 Ready Rwait Wwait Rgrant Wgrant +.names _n7d +Ready +.names cache_state _n7d _n7c +.def 0 +- =cache_state 1 +.names _n7c _n7b +1 1 +0 0 +# block_add == blocknum +.names block_add<0> blocknum<0> _n7f<0> +.def 0 +0 1 1 +1 0 1 +.names _n7f<0> _n80 +.def 1 +0 0 +.names _n80 _n7e +0 1 +1 0 +# (inval ) && (block_add == blocknum ) +.names inval _n7e _n81 +.def 0 +1 1 1 +.names _n81 _n82 +- =_n81 +# block_state = 0 +.mv block_state$_n81_n83$true 3 INVALID SHARED EXCLUSIVE +.names block_state$_n81_n83$true +INVALID +# cache_req = 0 +.mv cache_req$_n81_n84$true 4 ok blk_rreq blk_excl noop +.names cache_req$_n81_n84$true +ok +# cache_state = 0 +.mv cache_state$_n81_n85$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n81_n85$true +Ready +.names write_back_req _n86 +- =write_back_req +# block_state = 1 +.mv block_state$write_back_req_n87$true 3 INVALID SHARED EXCLUSIVE +.names block_state$write_back_req_n87$true +SHARED +# cache_req = 0 +.mv cache_req$write_back_req_n88$true 4 ok blk_rreq blk_excl noop +.names cache_req$write_back_req_n88$true +ok +# cache_state = 0 +.mv cache_state$write_back_req_n89$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$write_back_req_n89$true +Ready +.names read_req _n8a +- =read_req +# block_add != address +.names block_add<0> address<0> _n8c<0> +.def 0 +0 1 1 +1 0 1 +.names _n8c<0> _n8d +.def 1 +0 0 +.names _n8d _n8b +- =_n8d +.mv _n8f 3 INVALID SHARED EXCLUSIVE +.names _n8f +INVALID +# block_state == 0 +.names block_state _n8f _n8e +.def 0 +- =block_state 1 +# (block_add != address ) || (block_state == 0) +.names _n8b _n8e _n90 +.def 1 +0 0 0 +.names _n90 _n91 +- =_n90 +# cache_req = 1 +.mv cache_req$_n90_n92$true 4 ok blk_rreq blk_excl noop +.names cache_req$_n90_n92$true +blk_rreq +# blk_add = address +.names address<0> blk_add$_n90_n93$true<0> +- =address<0> +# cache_state = 1 +.mv cache_state$_n90_n94$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n90_n94$true +Rwait +# block_state = 0 +.mv block_state$_n90_n95$true 3 INVALID SHARED EXCLUSIVE +.names block_state$_n90_n95$true +INVALID +# cache_state = 3 +.mv cache_state$_n90_n96$false 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n90_n96$false +Rgrant +# cache_req = 3 +.mv cache_req$_n90_n97$false 4 ok blk_rreq blk_excl noop +.names cache_req$_n90_n97$false +noop +# if/else ((block_add != address ) || (block_state == 0)) +.mv cache_state$_n90$raw_n9e 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n90_n94$true cache_state$_n90_n96$false _n90 cache_state$_n90$raw_n9e +- - 0 =cache_state$_n90_n96$false +- - 1 =cache_state$_n90_n94$true +.mv cache_req$_n90$raw_n9f 4 ok blk_rreq blk_excl noop +.names cache_req$_n90_n92$true cache_req$_n90_n97$false _n90 cache_req$_n90$raw_n9f +- - 0 =cache_req$_n90_n97$false +- - 1 =cache_req$_n90_n92$true +.names blk_add$_n90_n93$true<0> blk_add<0> _n90 blk_add$_n90$raw_na0<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv block_state$_n90$raw_na2 3 INVALID SHARED EXCLUSIVE +.names block_state$_n90_n95$true block_state _n90 block_state$_n90$raw_na2 +- - 0 =block_state +- - 1 =block_state$_n90_n95$true +.names write_req _na7 +- =write_req +# block_add != address +.names block_add<0> address<0> _na9<0> +.def 0 +0 1 1 +1 0 1 +.names _na9<0> _naa +.def 1 +0 0 +.names _naa _na8 +- =_naa +.mv _nac 3 INVALID SHARED EXCLUSIVE +.names _nac +EXCLUSIVE +# block_state != 2 +.names block_state _nac _nab +.def 1 +- =block_state 0 +# (block_add != address ) || (block_state != 2) +.names _na8 _nab _nad +.def 1 +0 0 0 +.names _nad _nae +- =_nad +# cache_req = 2 +.mv cache_req$_nad_naf$true 4 ok blk_rreq blk_excl noop +.names cache_req$_nad_naf$true +blk_excl +# blk_add = address +.names address<0> blk_add$_nad_nb0$true<0> +- =address<0> +# cache_state = 2 +.mv cache_state$_nad_nb1$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_nad_nb1$true +Wwait +# block_state = 0 +.mv block_state$_nad_nb2$true 3 INVALID SHARED EXCLUSIVE +.names block_state$_nad_nb2$true +INVALID +# cache_state = 4 +.mv cache_state$_nad_nb3$false 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_nad_nb3$false +Wgrant +# cache_req = 3 +.mv cache_req$_nad_nb4$false 4 ok blk_rreq blk_excl noop +.names cache_req$_nad_nb4$false +noop +# if/else ((block_add != address ) || (block_state != 2)) +.mv cache_state$_nad$raw_nbb 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_nad_nb1$true cache_state$_nad_nb3$false _nad cache_state$_nad$raw_nbb +- - 0 =cache_state$_nad_nb3$false +- - 1 =cache_state$_nad_nb1$true +.mv cache_req$_nad$raw_nbc 4 ok blk_rreq blk_excl noop +.names cache_req$_nad_naf$true cache_req$_nad_nb4$false _nad cache_req$_nad$raw_nbc +- - 0 =cache_req$_nad_nb4$false +- - 1 =cache_req$_nad_naf$true +.names blk_add$_nad_nb0$true<0> blk_add<0> _nad blk_add$_nad$raw_nbd<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv block_state$_nad$raw_nbf 3 INVALID SHARED EXCLUSIVE +.names block_state$_nad_nb2$true block_state _nad block_state$_nad$raw_nbf +- - 0 =block_state +- - 1 =block_state$_nad_nb2$true +# cache_req = 3 +.mv cache_req$write_req_nc4$false 4 ok blk_rreq blk_excl noop +.names cache_req$write_req_nc4$false +noop +# blk_add = 0 +.names blk_add$write_req_nc5$false<0> +0 +# if/else (write_req ) +.names blk_add$_nad$raw_nbd<0> blk_add$write_req_nc5$false<0> write_req blk_add$write_req$raw_nca<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv cache_req$write_req$raw_nce 4 ok blk_rreq blk_excl noop +.names cache_req$_nad$raw_nbc cache_req$write_req_nc4$false write_req cache_req$write_req$raw_nce +- - 0 =cache_req$write_req_nc4$false +- - 1 =cache_req$_nad$raw_nbc +.mv block_state$write_req$raw_nd0 3 INVALID SHARED EXCLUSIVE +.names block_state$_nad$raw_nbf block_state write_req block_state$write_req$raw_nd0 +- - 0 =block_state +- - 1 =block_state$_nad$raw_nbf +.mv cache_state$write_req$raw_nd1 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_nad$raw_nbb cache_state write_req cache_state$write_req$raw_nd1 +- - 0 =cache_state +- - 1 =cache_state$_nad$raw_nbb +# if/else (read_req ) +.names blk_add$_n90$raw_na0<0> blk_add$write_req$raw_nca<0> read_req blk_add$read_req$raw_nd9<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv block_state$read_req$raw_ndb 3 INVALID SHARED EXCLUSIVE +.names block_state$_n90$raw_na2 block_state$write_req$raw_nd0 read_req block_state$read_req$raw_ndb +- - 0 =block_state$write_req$raw_nd0 +- - 1 =block_state$_n90$raw_na2 +.mv cache_state$read_req$raw_ndc 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n90$raw_n9e cache_state$write_req$raw_nd1 read_req cache_state$read_req$raw_ndc +- - 0 =cache_state$write_req$raw_nd1 +- - 1 =cache_state$_n90$raw_n9e +.mv cache_req$read_req$raw_ndd 4 ok blk_rreq blk_excl noop +.names cache_req$_n90$raw_n9f cache_req$write_req$raw_nce read_req cache_req$read_req$raw_ndd +- - 0 =cache_req$write_req$raw_nce +- - 1 =cache_req$_n90$raw_n9f +# if/else (write_back_req ) +.mv block_state$write_back_req$raw_ne9 3 INVALID SHARED EXCLUSIVE +.names block_state$write_back_req_n87$true block_state$read_req$raw_ndb write_back_req block_state$write_back_req$raw_ne9 +- - 0 =block_state$read_req$raw_ndb +- - 1 =block_state$write_back_req_n87$true +.mv cache_state$write_back_req$raw_nea 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$write_back_req_n89$true cache_state$read_req$raw_ndc write_back_req cache_state$write_back_req$raw_nea +- - 0 =cache_state$read_req$raw_ndc +- - 1 =cache_state$write_back_req_n89$true +.mv cache_req$write_back_req$raw_neb 4 ok blk_rreq blk_excl noop +.names cache_req$write_back_req_n88$true cache_req$read_req$raw_ndd write_back_req cache_req$write_back_req$raw_neb +- - 0 =cache_req$read_req$raw_ndd +- - 1 =cache_req$write_back_req_n88$true +.names blk_add<0> blk_add$read_req$raw_nd9<0> write_back_req blk_add$write_back_req$raw_nef<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else ((inval ) && (block_add == blocknum )) +.mv block_state$_n81$raw_nf7 3 INVALID SHARED EXCLUSIVE +.names block_state$_n81_n83$true block_state$write_back_req$raw_ne9 _n81 block_state$_n81$raw_nf7 +- - 0 =block_state$write_back_req$raw_ne9 +- - 1 =block_state$_n81_n83$true +.mv cache_state$_n81$raw_nf8 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n81_n85$true cache_state$write_back_req$raw_nea _n81 cache_state$_n81$raw_nf8 +- - 0 =cache_state$write_back_req$raw_nea +- - 1 =cache_state$_n81_n85$true +.mv cache_req$_n81$raw_nf9 4 ok blk_rreq blk_excl noop +.names cache_req$_n81_n84$true cache_req$write_back_req$raw_neb _n81 cache_req$_n81$raw_nf9 +- - 0 =cache_req$write_back_req$raw_neb +- - 1 =cache_req$_n81_n84$true +.names blk_add<0> blk_add$write_back_req$raw_nef<0> _n81 blk_add$_n81$raw_nfd<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _n104 5 Ready Rwait Wwait Rgrant Wgrant +.names _n104 +Rgrant +.names cache_state _n104 _n103 +.def 0 +- =cache_state 1 +.names _n103 _n102 +1 1 +0 0 +# block_add == blocknum +.names block_add<0> blocknum<0> _n106<0> +.def 0 +0 1 1 +1 0 1 +.names _n106<0> _n107 +.def 1 +0 0 +.names _n107 _n105 +0 1 +1 0 +# (inval ) && (block_add == blocknum ) +.names inval _n105 _n108 +.def 0 +1 1 1 +.names _n108 _n109 +- =_n108 +# block_state = 0 +.mv block_state$_n108_n10a$true 3 INVALID SHARED EXCLUSIVE +.names block_state$_n108_n10a$true +INVALID +# cache_req = 0 +.mv cache_req$_n108_n10b$true 4 ok blk_rreq blk_excl noop +.names cache_req$_n108_n10b$true +ok +# cache_state = 0 +.mv cache_state$_n108_n10c$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n108_n10c$true +Ready +# cache_state = 0 +.mv cache_state$_n108_n10d$false 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n108_n10d$false +Ready +# if/else ((inval ) && (block_add == blocknum )) +.mv cache_state$_n108$raw_n112 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n108_n10c$true cache_state$_n108_n10d$false _n108 cache_state$_n108$raw_n112 +- - 0 =cache_state$_n108_n10d$false +- - 1 =cache_state$_n108_n10c$true +.mv block_state$_n108$raw_n114 3 INVALID SHARED EXCLUSIVE +.names block_state$_n108_n10a$true block_state _n108 block_state$_n108$raw_n114 +- - 0 =block_state +- - 1 =block_state$_n108_n10a$true +.mv cache_req$_n108$raw_n116 4 ok blk_rreq blk_excl noop +.names cache_req$_n108_n10b$true cache_req _n108 cache_req$_n108$raw_n116 +- - 0 =cache_req +- - 1 =cache_req$_n108_n10b$true +.mv _n11a 5 Ready Rwait Wwait Rgrant Wgrant +.names _n11a +Wgrant +.names cache_state _n11a _n119 +.def 0 +- =cache_state 1 +.names _n119 _n118 +1 1 +0 0 +# block_add == blocknum +.names block_add<0> blocknum<0> _n11c<0> +.def 0 +0 1 1 +1 0 1 +.names _n11c<0> _n11d +.def 1 +0 0 +.names _n11d _n11b +0 1 +1 0 +# (inval ) && (block_add == blocknum ) +.names inval _n11b _n11e +.def 0 +1 1 1 +.names _n11e _n11f +- =_n11e +# block_state = 0 +.mv block_state$_n11e_n120$true 3 INVALID SHARED EXCLUSIVE +.names block_state$_n11e_n120$true +INVALID +# cache_req = 0 +.mv cache_req$_n11e_n121$true 4 ok blk_rreq blk_excl noop +.names cache_req$_n11e_n121$true +ok +# cache_state = 0 +.mv cache_state$_n11e_n122$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n11e_n122$true +Ready +# block_val = data +.names data block_val$_n11e_n123$false +- =data +# cache_state = 0 +.mv cache_state$_n11e_n124$false 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n11e_n124$false +Ready +# if/else ((inval ) && (block_add == blocknum )) +.mv cache_state$_n11e$raw_n129 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n11e_n122$true cache_state$_n11e_n124$false _n11e cache_state$_n11e$raw_n129 +- - 0 =cache_state$_n11e_n124$false +- - 1 =cache_state$_n11e_n122$true +.mv block_state$_n11e$raw_n12b 3 INVALID SHARED EXCLUSIVE +.names block_state$_n11e_n120$true block_state _n11e block_state$_n11e$raw_n12b +- - 0 =block_state +- - 1 =block_state$_n11e_n120$true +.mv cache_req$_n11e$raw_n12d 4 ok blk_rreq blk_excl noop +.names cache_req$_n11e_n121$true cache_req _n11e cache_req$_n11e$raw_n12d +- - 0 =cache_req +- - 1 =cache_req$_n11e_n121$true +.names block_val block_val$_n11e_n123$false _n11e block_val$_n11e$raw_n12f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _n133 5 Ready Rwait Wwait Rgrant Wgrant +.names _n133 +Rwait +.names cache_state _n133 _n132 +.def 0 +- =cache_state 1 +.names _n132 _n131 +1 1 +0 0 +# block_add == blocknum +.names block_add<0> blocknum<0> _n135<0> +.def 0 +0 1 1 +1 0 1 +.names _n135<0> _n136 +.def 1 +0 0 +.names _n136 _n134 +0 1 +1 0 +# (inval ) && (block_add == blocknum ) +.names inval _n134 _n137 +.def 0 +1 1 1 +.names _n137 _n138 +- =_n137 +# block_state = 0 +.mv block_state$_n137_n139$true 3 INVALID SHARED EXCLUSIVE +.names block_state$_n137_n139$true +INVALID +# cache_req = 0 +.mv cache_req$_n137_n13a$true 4 ok blk_rreq blk_excl noop +.names cache_req$_n137_n13a$true +ok +# cache_state = 0 +.mv cache_state$_n137_n13b$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n137_n13b$true +Ready +.names write_back_req _n13c +- =write_back_req +# cache_state = 0 +.mv cache_state$write_back_req_n13d$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$write_back_req_n13d$true +Ready +.names blk_ok _n13e +- =blk_ok +# block_val = blk_data +.names blk_data block_val$blk_ok_n13f$true +- =blk_data +# block_add = blk_add +.names blk_add<0> block_add$blk_ok_n140$true<0> +- =blk_add<0> +# block_state = 1 +.mv block_state$blk_ok_n141$true 3 INVALID SHARED EXCLUSIVE +.names block_state$blk_ok_n141$true +SHARED +# cache_req = 3 +.mv cache_req$blk_ok_n142$true 4 ok blk_rreq blk_excl noop +.names cache_req$blk_ok_n142$true +noop +# cache_state = 3 +.mv cache_state$blk_ok_n143$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$blk_ok_n143$true +Rgrant +# cache_state = 1 +.mv cache_state$blk_ok_n144$false 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$blk_ok_n144$false +Rwait +# if/else (blk_ok ) +.mv cache_state$blk_ok$raw_n14c 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$blk_ok_n143$true cache_state$blk_ok_n144$false blk_ok cache_state$blk_ok$raw_n14c +- - 0 =cache_state$blk_ok_n144$false +- - 1 =cache_state$blk_ok_n143$true +.mv block_state$blk_ok$raw_n14f 3 INVALID SHARED EXCLUSIVE +.names block_state$blk_ok_n141$true block_state blk_ok block_state$blk_ok$raw_n14f +- - 0 =block_state +- - 1 =block_state$blk_ok_n141$true +.names block_add$blk_ok_n140$true<0> block_add<0> blk_ok block_add$blk_ok$raw_n150<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv cache_req$blk_ok$raw_n153 4 ok blk_rreq blk_excl noop +.names cache_req$blk_ok_n142$true cache_req blk_ok cache_req$blk_ok$raw_n153 +- - 0 =cache_req +- - 1 =cache_req$blk_ok_n142$true +.names block_val$blk_ok_n13f$true block_val blk_ok block_val$blk_ok$raw_n154 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (write_back_req ) +.mv cache_state$write_back_req$raw_n158 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$write_back_req_n13d$true cache_state$blk_ok$raw_n14c write_back_req cache_state$write_back_req$raw_n158 +- - 0 =cache_state$blk_ok$raw_n14c +- - 1 =cache_state$write_back_req_n13d$true +.mv block_state$write_back_req$raw_n15a 3 INVALID SHARED EXCLUSIVE +.names block_state block_state$blk_ok$raw_n14f write_back_req block_state$write_back_req$raw_n15a +- - 0 =block_state$blk_ok$raw_n14f +- - 1 =block_state +.names block_add<0> block_add$blk_ok$raw_n150<0> write_back_req block_add$write_back_req$raw_n15b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names block_val block_val$blk_ok$raw_n154 write_back_req block_val$write_back_req$raw_n15e +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv cache_req$write_back_req$raw_n160 4 ok blk_rreq blk_excl noop +.names cache_req cache_req$blk_ok$raw_n153 write_back_req cache_req$write_back_req$raw_n160 +- - 0 =cache_req$blk_ok$raw_n153 +- - 1 =cache_req +# if/else ((inval ) && (block_add == blocknum )) +.mv block_state$_n137$raw_n164 3 INVALID SHARED EXCLUSIVE +.names block_state$_n137_n139$true block_state$write_back_req$raw_n15a _n137 block_state$_n137$raw_n164 +- - 0 =block_state$write_back_req$raw_n15a +- - 1 =block_state$_n137_n139$true +.mv cache_state$_n137$raw_n165 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n137_n13b$true cache_state$write_back_req$raw_n158 _n137 cache_state$_n137$raw_n165 +- - 0 =cache_state$write_back_req$raw_n158 +- - 1 =cache_state$_n137_n13b$true +.mv cache_req$_n137$raw_n166 4 ok blk_rreq blk_excl noop +.names cache_req$_n137_n13a$true cache_req$write_back_req$raw_n160 _n137 cache_req$_n137$raw_n166 +- - 0 =cache_req$write_back_req$raw_n160 +- - 1 =cache_req$_n137_n13a$true +.names block_add<0> block_add$write_back_req$raw_n15b<0> _n137 block_add$_n137$raw_n16b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names block_val block_val$write_back_req$raw_n15e _n137 block_val$_n137$raw_n16f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _n173 5 Ready Rwait Wwait Rgrant Wgrant +.names _n173 +Wwait +.names cache_state _n173 _n172 +.def 0 +- =cache_state 1 +.names _n172 _n171 +1 1 +0 0 +# block_add == blocknum +.names block_add<0> blocknum<0> _n175<0> +.def 0 +0 1 1 +1 0 1 +.names _n175<0> _n176 +.def 1 +0 0 +.names _n176 _n174 +0 1 +1 0 +# (inval ) && (block_add == blocknum ) +.names inval _n174 _n177 +.def 0 +1 1 1 +.names _n177 _n178 +- =_n177 +# block_state = 0 +.mv block_state$_n177_n179$true 3 INVALID SHARED EXCLUSIVE +.names block_state$_n177_n179$true +INVALID +# cache_req = 0 +.mv cache_req$_n177_n17a$true 4 ok blk_rreq blk_excl noop +.names cache_req$_n177_n17a$true +ok +# cache_state = 0 +.mv cache_state$_n177_n17b$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n177_n17b$true +Ready +.names write_back_req _n17c +- =write_back_req +# cache_state = 0 +.mv cache_state$write_back_req_n17d$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$write_back_req_n17d$true +Ready +.names blk_ok _n17e +- =blk_ok +# block_val = blk_data +.names blk_data block_val$blk_ok_n17f$true +- =blk_data +# block_add = blk_add +.names blk_add<0> block_add$blk_ok_n180$true<0> +- =blk_add<0> +# block_state = 2 +.mv block_state$blk_ok_n181$true 3 INVALID SHARED EXCLUSIVE +.names block_state$blk_ok_n181$true +EXCLUSIVE +# cache_req = 3 +.mv cache_req$blk_ok_n182$true 4 ok blk_rreq blk_excl noop +.names cache_req$blk_ok_n182$true +noop +# cache_state = 4 +.mv cache_state$blk_ok_n183$true 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$blk_ok_n183$true +Wgrant +# cache_state = 2 +.mv cache_state$blk_ok_n184$false 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$blk_ok_n184$false +Wwait +# if/else (blk_ok ) +.mv cache_state$blk_ok$raw_n18c 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$blk_ok_n183$true cache_state$blk_ok_n184$false blk_ok cache_state$blk_ok$raw_n18c +- - 0 =cache_state$blk_ok_n184$false +- - 1 =cache_state$blk_ok_n183$true +.mv block_state$blk_ok$raw_n18f 3 INVALID SHARED EXCLUSIVE +.names block_state$blk_ok_n181$true block_state blk_ok block_state$blk_ok$raw_n18f +- - 0 =block_state +- - 1 =block_state$blk_ok_n181$true +.names block_add$blk_ok_n180$true<0> block_add<0> blk_ok block_add$blk_ok$raw_n190<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv cache_req$blk_ok$raw_n193 4 ok blk_rreq blk_excl noop +.names cache_req$blk_ok_n182$true cache_req blk_ok cache_req$blk_ok$raw_n193 +- - 0 =cache_req +- - 1 =cache_req$blk_ok_n182$true +.names block_val$blk_ok_n17f$true block_val blk_ok block_val$blk_ok$raw_n194 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (write_back_req ) +.mv cache_state$write_back_req$raw_n198 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$write_back_req_n17d$true cache_state$blk_ok$raw_n18c write_back_req cache_state$write_back_req$raw_n198 +- - 0 =cache_state$blk_ok$raw_n18c +- - 1 =cache_state$write_back_req_n17d$true +.mv block_state$write_back_req$raw_n19a 3 INVALID SHARED EXCLUSIVE +.names block_state block_state$blk_ok$raw_n18f write_back_req block_state$write_back_req$raw_n19a +- - 0 =block_state$blk_ok$raw_n18f +- - 1 =block_state +.names block_add<0> block_add$blk_ok$raw_n190<0> write_back_req block_add$write_back_req$raw_n19b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names block_val block_val$blk_ok$raw_n194 write_back_req block_val$write_back_req$raw_n19e +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv cache_req$write_back_req$raw_n1a0 4 ok blk_rreq blk_excl noop +.names cache_req cache_req$blk_ok$raw_n193 write_back_req cache_req$write_back_req$raw_n1a0 +- - 0 =cache_req$blk_ok$raw_n193 +- - 1 =cache_req +# if/else ((inval ) && (block_add == blocknum )) +.mv block_state$_n177$raw_n1a4 3 INVALID SHARED EXCLUSIVE +.names block_state$_n177_n179$true block_state$write_back_req$raw_n19a _n177 block_state$_n177$raw_n1a4 +- - 0 =block_state$write_back_req$raw_n19a +- - 1 =block_state$_n177_n179$true +.mv cache_state$_n177$raw_n1a5 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n177_n17b$true cache_state$write_back_req$raw_n198 _n177 cache_state$_n177$raw_n1a5 +- - 0 =cache_state$write_back_req$raw_n198 +- - 1 =cache_state$_n177_n17b$true +.mv cache_req$_n177$raw_n1a6 4 ok blk_rreq blk_excl noop +.names cache_req$_n177_n17a$true cache_req$write_back_req$raw_n1a0 _n177 cache_req$_n177$raw_n1a6 +- - 0 =cache_req$write_back_req$raw_n1a0 +- - 1 =cache_req$_n177_n17a$true +.names block_add<0> block_add$write_back_req$raw_n19b<0> _n177 block_add$_n177$raw_n1ab<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names block_val block_val$write_back_req$raw_n19e _n177 block_val$_n177$raw_n1af +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# cache_req = 3 +.mv cache_req$raw_n1b1 4 ok blk_rreq blk_excl noop +.names cache_req$raw_n1b1 +noop +# case (cache_state ) +.mv cache_req$_n171$raw_n1bb 4 ok blk_rreq blk_excl noop +.names cache_req$_n177$raw_n1a6 cache_req$raw_n1b1 _n171 cache_req$_n171$raw_n1bb +- - 0 =cache_req$raw_n1b1 +- - 1 =cache_req$_n177$raw_n1a6 +.mv block_state$_n171$raw_n1bc 3 INVALID SHARED EXCLUSIVE +.names block_state$_n177$raw_n1a4 block_state _n171 block_state$_n171$raw_n1bc +- - 0 =block_state +- - 1 =block_state$_n177$raw_n1a4 +.names block_add$_n177$raw_n1ab<0> block_add<0> _n171 block_add$_n171$raw_n1bd<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv cache_state$_n171$raw_n1bf 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n177$raw_n1a5 cache_state _n171 cache_state$_n171$raw_n1bf +- - 0 =cache_state +- - 1 =cache_state$_n177$raw_n1a5 +.names block_val$_n177$raw_n1af block_val _n171 block_val$_n171$raw_n1c0 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv block_state$_n131$raw_n1c9 3 INVALID SHARED EXCLUSIVE +.names block_state$_n137$raw_n164 block_state$_n171$raw_n1bc _n131 block_state$_n131$raw_n1c9 +- - 0 =block_state$_n171$raw_n1bc +- - 1 =block_state$_n137$raw_n164 +.names block_add$_n137$raw_n16b<0> block_add$_n171$raw_n1bd<0> _n131 block_add$_n131$raw_n1ca<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv cache_state$_n131$raw_n1cc 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n137$raw_n165 cache_state$_n171$raw_n1bf _n131 cache_state$_n131$raw_n1cc +- - 0 =cache_state$_n171$raw_n1bf +- - 1 =cache_state$_n137$raw_n165 +.names block_val$_n137$raw_n16f block_val$_n171$raw_n1c0 _n131 block_val$_n131$raw_n1cd +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv cache_req$_n131$raw_n1cf 4 ok blk_rreq blk_excl noop +.names cache_req$_n137$raw_n166 cache_req$_n171$raw_n1bb _n131 cache_req$_n131$raw_n1cf +- - 0 =cache_req$_n171$raw_n1bb +- - 1 =cache_req$_n137$raw_n166 +.mv block_state$_n118$raw_n1de 3 INVALID SHARED EXCLUSIVE +.names block_state$_n11e$raw_n12b block_state$_n131$raw_n1c9 _n118 block_state$_n118$raw_n1de +- - 0 =block_state$_n131$raw_n1c9 +- - 1 =block_state$_n11e$raw_n12b +.mv cache_state$_n118$raw_n1df 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n11e$raw_n129 cache_state$_n131$raw_n1cc _n118 cache_state$_n118$raw_n1df +- - 0 =cache_state$_n131$raw_n1cc +- - 1 =cache_state$_n11e$raw_n129 +.names block_val$_n11e$raw_n12f block_val$_n131$raw_n1cd _n118 block_val$_n118$raw_n1e0 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv cache_req$_n118$raw_n1e2 4 ok blk_rreq blk_excl noop +.names cache_req$_n11e$raw_n12d cache_req$_n131$raw_n1cf _n118 cache_req$_n118$raw_n1e2 +- - 0 =cache_req$_n131$raw_n1cf +- - 1 =cache_req$_n11e$raw_n12d +.names block_add<0> block_add$_n131$raw_n1ca<0> _n118 block_add$_n118$raw_n1e8<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv block_state$_n102$raw_n1f0 3 INVALID SHARED EXCLUSIVE +.names block_state$_n108$raw_n114 block_state$_n118$raw_n1de _n102 block_state$_n102$raw_n1f0 +- - 0 =block_state$_n118$raw_n1de +- - 1 =block_state$_n108$raw_n114 +.mv cache_state$_n102$raw_n1f1 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n108$raw_n112 cache_state$_n118$raw_n1df _n102 cache_state$_n102$raw_n1f1 +- - 0 =cache_state$_n118$raw_n1df +- - 1 =cache_state$_n108$raw_n112 +.mv cache_req$_n102$raw_n1f2 4 ok blk_rreq blk_excl noop +.names cache_req$_n108$raw_n116 cache_req$_n118$raw_n1e2 _n102 cache_req$_n102$raw_n1f2 +- - 0 =cache_req$_n118$raw_n1e2 +- - 1 =cache_req$_n108$raw_n116 +.names block_add<0> block_add$_n118$raw_n1e8<0> _n102 block_add$_n102$raw_n1f7<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names block_val block_val$_n118$raw_n1e0 _n102 block_val$_n102$raw_n1fb +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv block_state$_n7b$raw_n202 3 INVALID SHARED EXCLUSIVE +.names block_state$_n81$raw_nf7 block_state$_n102$raw_n1f0 _n7b block_state$_n7b$raw_n202 +- - 0 =block_state$_n102$raw_n1f0 +- - 1 =block_state$_n81$raw_nf7 +.mv cache_state$_n7b$raw_n203 5 Ready Rwait Wwait Rgrant Wgrant +.names cache_state$_n81$raw_nf8 cache_state$_n102$raw_n1f1 _n7b cache_state$_n7b$raw_n203 +- - 0 =cache_state$_n102$raw_n1f1 +- - 1 =cache_state$_n81$raw_nf8 +.mv cache_req$_n7b$raw_n204 4 ok blk_rreq blk_excl noop +.names cache_req$_n81$raw_nf9 cache_req$_n102$raw_n1f2 _n7b cache_req$_n7b$raw_n204 +- - 0 =cache_req$_n102$raw_n1f2 +- - 1 =cache_req$_n81$raw_nf9 +.names blk_add$_n81$raw_nfd<0> blk_add<0> _n7b blk_add$_n7b$raw_n205<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names block_add<0> block_add$_n102$raw_n1f7<0> _n7b block_add$_n7b$raw_n20b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names block_val block_val$_n102$raw_n1fb _n7b block_val$_n7b$raw_n20e +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names back_data$raw_n6b back_data +0 0 +1 1 +.names _n7b _n82 _n86 _n8a _n91 _na7 _nae _n211 +.def 0 + 1 0 0 1 1 - - 1 + 1 0 0 0 - 1 1 1 + 1 0 0 0 - 0 - 1 +.names _n211 blk_add$_n7b$raw_n205<0> blk_add<0> -> _n212<0> +1 - - =blk_add$_n7b$raw_n205<0> +0 - - =blk_add<0> +.names _n7b _n82 _n86 _n8a _n91 _na7 _nae _n102 _n109 _n118 _n11f _n131 _n138 _n13c _n13e _n171 _n178 _n17c _n17e _n213 +.def 0 + 1 1 - - - - - - - - - - - - - - - - - 1 + 1 0 1 - - - - - - - - - - - - - - - - 1 + 1 0 0 1 1 - - - - - - - - - - - - - - 1 + 1 0 0 0 - 1 1 - - - - - - - - - - - - 1 + 0 - - - - - - 1 1 - - - - - - - - - - 1 + 0 - - - - - - 0 - 1 1 - - - - - - - - 1 + 0 - - - - - - 0 - 0 - 1 1 - - - - - - 1 + 0 - - - - - - 0 - 0 - 1 0 0 1 - - - - 1 + 0 - - - - - - 0 - 0 - 0 - - - 1 1 - - 1 + 0 - - - - - - 0 - 0 - 0 - - - 1 0 0 1 1 +.mv _n214 3 INVALID SHARED EXCLUSIVE +.names _n213 block_state$_n7b$raw_n202 block_state _n214 +1 - - =block_state$_n7b$raw_n202 +0 - - =block_state +.names _n7b _n102 _n118 _n131 _n138 _n13c _n13e _n171 _n178 _n17c _n17e _n219 +.def 0 + 0 0 0 1 0 0 1 - - - - 1 + 0 0 0 0 - - - 1 0 0 1 1 +.names _n219 block_add$_n7b$raw_n20b<0> block_add<0> -> _n21a<0> +1 - - =block_add$_n7b$raw_n20b<0> +0 - - =block_add<0> +.names _n7b _n82 _n86 _n8a _n91 _na7 _nae _n102 _n109 _n118 _n11f _n131 _n138 _n13c _n13e _n171 _n178 _n17c _n17e _n21b +.def 0 + 1 1 - - - - - - - - - - - - - - - - - 1 + 1 0 1 - - - - - - - - - - - - - - - - 1 + 1 0 0 1 1 - - - - - - - - - - - - - - 1 + 1 0 0 1 0 - - - - - - - - - - - - - - 1 + 1 0 0 0 - 1 1 - - - - - - - - - - - - 1 + 1 0 0 0 - 1 0 - - - - - - - - - - - - 1 + 0 - - - - - - 1 1 - - - - - - - - - - 1 + 0 - - - - - - 1 0 - - - - - - - - - - 1 + 0 - - - - - - 0 - 1 1 - - - - - - - - 1 + 0 - - - - - - 0 - 1 0 - - - - - - - - 1 + 0 - - - - - - 0 - 0 - 1 1 - - - - - - 1 + 0 - - - - - - 0 - 0 - 1 0 1 - - - - - 1 + 0 - - - - - - 0 - 0 - 1 0 0 1 - - - - 1 + 0 - - - - - - 0 - 0 - 1 0 0 0 - - - - 1 + 0 - - - - - - 0 - 0 - 0 - - - 1 1 - - 1 + 0 - - - - - - 0 - 0 - 0 - - - 1 0 1 - 1 + 0 - - - - - - 0 - 0 - 0 - - - 1 0 0 1 1 + 0 - - - - - - 0 - 0 - 0 - - - 1 0 0 0 1 +.mv _n21c 5 Ready Rwait Wwait Rgrant Wgrant +.names _n21b cache_state$_n7b$raw_n203 cache_state _n21c +1 - - =cache_state$_n7b$raw_n203 +0 - - =cache_state +.names _n7b _n102 _n118 _n11f _n131 _n138 _n13c _n13e _n171 _n178 _n17c _n17e _n221 +.def 0 + 0 0 1 0 - - - - - - - - 1 + 0 0 0 - 1 0 0 1 - - - - 1 + 0 0 0 - 0 - - - 1 0 0 1 1 +.names _n221 block_val$_n7b$raw_n20e block_val _n222 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n7b _n82 _n86 _n8a _n91 _na7 _nae _n102 _n109 _n118 _n11f _n131 _n138 _n13c _n13e _n171 _n178 _n17c _n17e _n223 +.def 0 + 1 1 - - - - - - - - - - - - - - - - - 1 + 1 0 1 - - - - - - - - - - - - - - - - 1 + 1 0 0 1 1 - - - - - - - - - - - - - - 1 + 1 0 0 1 0 - - - - - - - - - - - - - - 1 + 1 0 0 0 - 1 1 - - - - - - - - - - - - 1 + 1 0 0 0 - 1 0 - - - - - - - - - - - - 1 + 1 0 0 0 - 0 - - - - - - - - - - - - - 1 + 0 - - - - - - 1 1 - - - - - - - - - - 1 + 0 - - - - - - 0 - 1 1 - - - - - - - - 1 + 0 - - - - - - 0 - 0 - 1 1 - - - - - - 1 + 0 - - - - - - 0 - 0 - 1 0 0 1 - - - - 1 + 0 - - - - - - 0 - 0 - 0 - - - 1 1 - - 1 + 0 - - - - - - 0 - 0 - 0 - - - 1 0 0 1 1 + 0 - - - - - - 0 - 0 - 0 - - - 0 - - - 1 +.mv _n224 4 ok blk_rreq blk_excl noop +.names _n223 cache_req$_n7b$raw_n204 cache_req _n224 +1 - - =cache_req$_n7b$raw_n204 +0 - - =cache_req +.names acknowledge$raw_n71 acknowledge +0 0 +1 1 +# non-blocking assignments +# latches +.r blk_add$raw_n69<0> blk_add<0> +.def 0 +1 1 +.latch _n212<0> blk_add<0> +.r block_state$raw_n66 block_state +- =block_state$raw_n66 +.latch _n214 block_state +.r block_add$raw_n67<0> block_add<0> +.def 0 +1 1 +.latch _n21a<0> block_add<0> +.r cache_state$raw_n65 cache_state +- =cache_state$raw_n65 +.latch _n21c cache_state +.r cache_req$raw_n6a cache_req +- =cache_req$raw_n6a +.latch _n224 cache_req +.r block_val$raw_n68 block_val +0 0 +1 1 +.latch _n222 block_val +# quasi-continuous assignment +.end + + +.model DIRECTORY +# I/O ports +.outputs blk_ok2 +.outputs write_back_req2 +.outputs blk_ok1 +.outputs write_back_req1 +.inputs blk_add2<0> +.outputs inval2 +.inputs blk_add1<0> +.outputs blk_data +.outputs inval1 +.inputs cache_req2 +.inputs back_data2 +.inputs cache_req1 +.inputs back_data1 +.outputs blocknum<0> + +.mv cache_req2 4 ok blk_rreq blk_excl noop +.mv cache_req1 4 ok blk_rreq blk_excl noop +.mv arbiter_state 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +# arbiter_state = 0 +.mv arbiter_state$raw_n229 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$raw_n229 +ONE +# main_mem [0] = 0 +.names _n22c<0> +0 +.names _n22d<0> +0 +.names _n22d<0> _n22c<0> _n22f<0> +.def 0 +0 1 1 +1 0 1 +.names _n22f<0> _n230 +.def 1 +0 0 +.names _n230 _n22e +0 1 +1 0 +.names _n231 +0 +.names _n22b _n231 _n22e main_mem$raw_n22a<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n233<0> +1 +.names _n233<0> _n22c<0> _n235<0> +.def 0 +0 1 1 +1 0 1 +.names _n235<0> _n236 +.def 1 +0 0 +.names _n236 _n234 +0 1 +1 0 +.names _n237 +0 +.names _n22b _n237 _n234 main_mem$raw_n22a<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n22b +0 +# cache_Rlist1 [0] = 0 +.names _n23b<0> +0 +.names _n23c<0> +0 +.names _n23c<0> _n23b<0> _n23e<0> +.def 0 +0 1 1 +1 0 1 +.names _n23e<0> _n23f +.def 1 +0 0 +.names _n23f _n23d +0 1 +1 0 +.names _n240 +0 +.names _n23a _n240 _n23d cache_Rlist1$raw_n239<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n242<0> +1 +.names _n242<0> _n23b<0> _n244<0> +.def 0 +0 1 1 +1 0 1 +.names _n244<0> _n245 +.def 1 +0 0 +.names _n245 _n243 +0 1 +1 0 +.names _n246 +0 +.names _n23a _n246 _n243 cache_Rlist1$raw_n239<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n23a +0 +# cache_Rlist2 [0] = 0 +.names _n24a<0> +0 +.names _n24b<0> +0 +.names _n24b<0> _n24a<0> _n24d<0> +.def 0 +0 1 1 +1 0 1 +.names _n24d<0> _n24e +.def 1 +0 0 +.names _n24e _n24c +0 1 +1 0 +.names _n24f +0 +.names _n249 _n24f _n24c cache_Rlist2$raw_n248<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n251<0> +1 +.names _n251<0> _n24a<0> _n253<0> +.def 0 +0 1 1 +1 0 1 +.names _n253<0> _n254 +.def 1 +0 0 +.names _n254 _n252 +0 1 +1 0 +.names _n255 +0 +.names _n249 _n255 _n252 cache_Rlist2$raw_n248<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n249 +0 +# cache_Wlist1 [0] = 0 +.names _n259<0> +0 +.names _n25a<0> +0 +.names _n25a<0> _n259<0> _n25c<0> +.def 0 +0 1 1 +1 0 1 +.names _n25c<0> _n25d +.def 1 +0 0 +.names _n25d _n25b +0 1 +1 0 +.names _n25e +0 +.names _n258 _n25e _n25b cache_Wlist1$raw_n257<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n260<0> +1 +.names _n260<0> _n259<0> _n262<0> +.def 0 +0 1 1 +1 0 1 +.names _n262<0> _n263 +.def 1 +0 0 +.names _n263 _n261 +0 1 +1 0 +.names _n264 +0 +.names _n258 _n264 _n261 cache_Wlist1$raw_n257<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n258 +0 +# cache_Wlist2 [0] = 0 +.names _n268<0> +0 +.names _n269<0> +0 +.names _n269<0> _n268<0> _n26b<0> +.def 0 +0 1 1 +1 0 1 +.names _n26b<0> _n26c +.def 1 +0 0 +.names _n26c _n26a +0 1 +1 0 +.names _n26d +0 +.names _n267 _n26d _n26a cache_Wlist2$raw_n266<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n26f<0> +1 +.names _n26f<0> _n268<0> _n271<0> +.def 0 +0 1 1 +1 0 1 +.names _n271<0> _n272 +.def 1 +0 0 +.names _n272 _n270 +0 1 +1 0 +.names _n273 +0 +.names _n267 _n273 _n270 cache_Wlist2$raw_n266<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n267 +0 +# main_mem [1] = 0 +.names _n277<0> +1 +.names _n278<0> +0 +.names _n278<0> _n277<0> _n27a<0> +.def 0 +0 1 1 +1 0 1 +.names _n27a<0> _n27b +.def 1 +0 0 +.names _n27b _n279 +0 1 +1 0 +.names _n276 main_mem$raw_n22a<*0*> _n279 main_mem$raw_n275<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n27d<0> +1 +.names _n27d<0> _n277<0> _n27f<0> +.def 0 +0 1 1 +1 0 1 +.names _n27f<0> _n280 +.def 1 +0 0 +.names _n280 _n27e +0 1 +1 0 +.names _n276 main_mem$raw_n22a<*1*> _n27e main_mem$raw_n275<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n276 +0 +# cache_Rlist1 [1] = 0 +.names _n284<0> +1 +.names _n285<0> +0 +.names _n285<0> _n284<0> _n287<0> +.def 0 +0 1 1 +1 0 1 +.names _n287<0> _n288 +.def 1 +0 0 +.names _n288 _n286 +0 1 +1 0 +.names _n283 cache_Rlist1$raw_n239<*0*> _n286 cache_Rlist1$raw_n282<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n28a<0> +1 +.names _n28a<0> _n284<0> _n28c<0> +.def 0 +0 1 1 +1 0 1 +.names _n28c<0> _n28d +.def 1 +0 0 +.names _n28d _n28b +0 1 +1 0 +.names _n283 cache_Rlist1$raw_n239<*1*> _n28b cache_Rlist1$raw_n282<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n283 +0 +# cache_Rlist2 [1] = 0 +.names _n291<0> +1 +.names _n292<0> +0 +.names _n292<0> _n291<0> _n294<0> +.def 0 +0 1 1 +1 0 1 +.names _n294<0> _n295 +.def 1 +0 0 +.names _n295 _n293 +0 1 +1 0 +.names _n290 cache_Rlist2$raw_n248<*0*> _n293 cache_Rlist2$raw_n28f<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n297<0> +1 +.names _n297<0> _n291<0> _n299<0> +.def 0 +0 1 1 +1 0 1 +.names _n299<0> _n29a +.def 1 +0 0 +.names _n29a _n298 +0 1 +1 0 +.names _n290 cache_Rlist2$raw_n248<*1*> _n298 cache_Rlist2$raw_n28f<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n290 +0 +# cache_Wlist1 [1] = 0 +.names _n29e<0> +1 +.names _n29f<0> +0 +.names _n29f<0> _n29e<0> _n2a1<0> +.def 0 +0 1 1 +1 0 1 +.names _n2a1<0> _n2a2 +.def 1 +0 0 +.names _n2a2 _n2a0 +0 1 +1 0 +.names _n29d cache_Wlist1$raw_n257<*0*> _n2a0 cache_Wlist1$raw_n29c<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2a4<0> +1 +.names _n2a4<0> _n29e<0> _n2a6<0> +.def 0 +0 1 1 +1 0 1 +.names _n2a6<0> _n2a7 +.def 1 +0 0 +.names _n2a7 _n2a5 +0 1 +1 0 +.names _n29d cache_Wlist1$raw_n257<*1*> _n2a5 cache_Wlist1$raw_n29c<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n29d +0 +# cache_Wlist2 [1] = 0 +.names _n2ab<0> +1 +.names _n2ac<0> +0 +.names _n2ac<0> _n2ab<0> _n2ae<0> +.def 0 +0 1 1 +1 0 1 +.names _n2ae<0> _n2af +.def 1 +0 0 +.names _n2af _n2ad +0 1 +1 0 +.names _n2aa cache_Wlist2$raw_n266<*0*> _n2ad cache_Wlist2$raw_n2a9<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2b1<0> +1 +.names _n2b1<0> _n2ab<0> _n2b3<0> +.def 0 +0 1 1 +1 0 1 +.names _n2b3<0> _n2b4 +.def 1 +0 0 +.names _n2b4 _n2b2 +0 1 +1 0 +.names _n2aa cache_Wlist2$raw_n266<*1*> _n2b2 cache_Wlist2$raw_n2a9<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2aa +0 +# non-blocking assignments for initial +# assign inval1 = ((arbiter_state == TWO ) && (cache_req2 == blk_excl )) ? 1 : 0 +.mv _n2b8 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n2b8 +TWO +# arbiter_state == 2 +.names arbiter_state _n2b8 _n2b7 +.def 0 +- =arbiter_state 1 +.mv _n2ba 4 ok blk_rreq blk_excl noop +.names _n2ba +blk_excl +# cache_req2 == 2 +.names cache_req2 _n2ba _n2b9 +.def 0 +- =cache_req2 1 +# (arbiter_state == 2) && (cache_req2 == 2) +.names _n2b7 _n2b9 _n2bb +.def 0 +1 1 1 +.names _n2bc +1 +.names _n2bd +0 +# ((arbiter_state == 2) && (cache_req2 == 2)) ? 1 : 0 +.names _n2bc _n2bd _n2bb _n2be +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2be inval1$raw_n2b6 +- =_n2be +# assign inval2 = ((arbiter_state == ONE ) && (cache_req1 == blk_excl )) ? 1 : 0 +.mv _n2c2 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n2c2 +ONE +# arbiter_state == 0 +.names arbiter_state _n2c2 _n2c1 +.def 0 +- =arbiter_state 1 +.mv _n2c4 4 ok blk_rreq blk_excl noop +.names _n2c4 +blk_excl +# cache_req1 == 2 +.names cache_req1 _n2c4 _n2c3 +.def 0 +- =cache_req1 1 +# (arbiter_state == 0) && (cache_req1 == 2) +.names _n2c1 _n2c3 _n2c5 +.def 0 +1 1 1 +.names _n2c6 +1 +.names _n2c7 +0 +# ((arbiter_state == 0) && (cache_req1 == 2)) ? 1 : 0 +.names _n2c6 _n2c7 _n2c5 _n2c8 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2c8 inval2$raw_n2c0 +- =_n2c8 +# assign write_back_req1 = ((arbiter_state == TWOWAIT ) && (cache_req1 != ok )) ? 1 : 0 +.mv _n2cc 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n2cc +TWOWAIT +# arbiter_state == 3 +.names arbiter_state _n2cc _n2cb +.def 0 +- =arbiter_state 1 +.mv _n2ce 4 ok blk_rreq blk_excl noop +.names _n2ce +ok +# cache_req1 != 0 +.names cache_req1 _n2ce _n2cd +.def 1 +- =cache_req1 0 +# (arbiter_state == 3) && (cache_req1 != 0) +.names _n2cb _n2cd _n2cf +.def 0 +1 1 1 +.names _n2d0 +1 +.names _n2d1 +0 +# ((arbiter_state == 3) && (cache_req1 != 0)) ? 1 : 0 +.names _n2d0 _n2d1 _n2cf _n2d2 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2d2 write_back_req1$raw_n2ca +- =_n2d2 +# assign write_back_req2 = ((arbiter_state == ONEWAIT ) && (cache_req2 != ok )) ? 1 : 0 +.mv _n2d6 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n2d6 +ONEWAIT +# arbiter_state == 1 +.names arbiter_state _n2d6 _n2d5 +.def 0 +- =arbiter_state 1 +.mv _n2d8 4 ok blk_rreq blk_excl noop +.names _n2d8 +ok +# cache_req2 != 0 +.names cache_req2 _n2d8 _n2d7 +.def 1 +- =cache_req2 0 +# (arbiter_state == 1) && (cache_req2 != 0) +.names _n2d5 _n2d7 _n2d9 +.def 0 +1 1 1 +.names _n2da +1 +.names _n2db +0 +# ((arbiter_state == 1) && (cache_req2 != 0)) ? 1 : 0 +.names _n2da _n2db _n2d9 _n2dc +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2dc write_back_req2$raw_n2d4 +- =_n2dc +# assign blk_data = (arbiter_state == ONESERVE ) ? main_mem [blk_add1 ] : (arbiter_state == TWOSERVE ) ? main_mem [blk_add2 ] : 0 +.mv _n2e0 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n2e0 +ONESERVE +# arbiter_state == 4 +.names arbiter_state _n2e0 _n2df +.def 0 +- =arbiter_state 1 +.names main_mem<*0*> main_mem<*1*> blk_add1<0> _n2e1 +0 - 0 0 +1 - 0 1 +- 0 1 0 +- 1 1 1 +.mv _n2e3 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n2e3 +TWOSERVE +# arbiter_state == 5 +.names arbiter_state _n2e3 _n2e2 +.def 0 +- =arbiter_state 1 +.names main_mem<*0*> main_mem<*1*> blk_add2<0> _n2e4 +0 - 0 0 +1 - 0 1 +- 0 1 0 +- 1 1 1 +.names _n2e5 +0 +# (arbiter_state == 5) ? main_mem [blk_add2 ] : 0 +.names _n2e4 _n2e5 _n2e2 _n2e6 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# (arbiter_state == 4) ? main_mem [blk_add1 ] : (arbiter_state == 5) ? main_mem [blk_add2 ] : 0 +.names _n2e1 _n2e6 _n2df _n2e8 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2e8 blk_data$raw_n2de +- =_n2e8 +# assign blk_ok1 = (arbiter_state == ONESERVE ) ? 1 : 0 +.mv _n2ec 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n2ec +ONESERVE +# arbiter_state == 4 +.names arbiter_state _n2ec _n2eb +.def 0 +- =arbiter_state 1 +.names _n2ed +1 +.names _n2ee +0 +# (arbiter_state == 4) ? 1 : 0 +.names _n2ed _n2ee _n2eb _n2ef +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2ef blk_ok1$raw_n2ea +- =_n2ef +# assign blk_ok2 = (arbiter_state == TWOSERVE ) ? 1 : 0 +.mv _n2f3 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n2f3 +TWOSERVE +# arbiter_state == 5 +.names arbiter_state _n2f3 _n2f2 +.def 0 +- =arbiter_state 1 +.names _n2f4 +1 +.names _n2f5 +0 +# (arbiter_state == 5) ? 1 : 0 +.names _n2f4 _n2f5 _n2f2 _n2f6 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2f6 blk_ok2$raw_n2f1 +- =_n2f6 +# assign blocknum = ((arbiter_state == ONE ) && (cache_req1 == blk_excl )) ? blk_add1 : ((arbiter_state == TWO ) && (cache_req2 == blk_excl )) ? blk_add2 : 0 +.mv _n2fa 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n2fa +ONE +# arbiter_state == 0 +.names arbiter_state _n2fa _n2f9 +.def 0 +- =arbiter_state 1 +.mv _n2fc 4 ok blk_rreq blk_excl noop +.names _n2fc +blk_excl +# cache_req1 == 2 +.names cache_req1 _n2fc _n2fb +.def 0 +- =cache_req1 1 +# (arbiter_state == 0) && (cache_req1 == 2) +.names _n2f9 _n2fb _n2fd +.def 0 +1 1 1 +.mv _n2ff 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n2ff +TWO +# arbiter_state == 2 +.names arbiter_state _n2ff _n2fe +.def 0 +- =arbiter_state 1 +.mv _n301 4 ok blk_rreq blk_excl noop +.names _n301 +blk_excl +# cache_req2 == 2 +.names cache_req2 _n301 _n300 +.def 0 +- =cache_req2 1 +# (arbiter_state == 2) && (cache_req2 == 2) +.names _n2fe _n300 _n302 +.def 0 +1 1 1 +.names _n303<0> +0 +# ((arbiter_state == 2) && (cache_req2 == 2)) ? blk_add2 : 0 +.names blk_add2<0> _n303<0> _n302 _n304<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# ((arbiter_state == 0) && (cache_req1 == 2)) ? blk_add1 : ((arbiter_state == 2) && (cache_req2 == 2)) ? blk_add2 : 0 +.names blk_add1<0> _n304<0> _n2fd _n306<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n306<0> blocknum$raw_n2f8<0> +- =_n306<0> +.mv _n30a 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n30a +ONE +.names arbiter_state _n30a _n309 +.def 0 +- =arbiter_state 1 +.names _n309 _n308 +1 1 +0 0 +.mv _n30c 4 ok blk_rreq blk_excl noop +.names _n30c +blk_rreq +# cache_req1 == 1 +.names cache_req1 _n30c _n30b +.def 0 +- =cache_req1 1 +.names _n30b _n30d +- =_n30b +.names cache_Wlist2<*0*> cache_Wlist2<*1*> blk_add1<0> _n30f +0 - 0 0 +1 - 0 1 +- 0 1 0 +- 1 1 1 +.names _n310 +1 +# cache_Wlist2 [blk_add1 ] == 1 +.names _n30f _n310 _n311 +.def 0 +0 1 1 +1 0 1 +.names _n311 _n30e +0 1 +1 0 +.names _n30e _n313 +- =_n30e +# cache_Rlist1 [blk_add1 ] = 1 +.names _n316<0> +0 +.names _n316<0> blk_add1<0> _n318<0> +.def 0 +0 1 1 +1 0 1 +.names _n318<0> _n319 +.def 1 +0 0 +.names _n319 _n317 +0 1 +1 0 +.names _n315 cache_Rlist1<*0*> _n317 cache_Rlist1$_n30e_n314$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n31b<0> +1 +.names _n31b<0> blk_add1<0> _n31d<0> +.def 0 +0 1 1 +1 0 1 +.names _n31d<0> _n31e +.def 1 +0 0 +.names _n31e _n31c +0 1 +1 0 +.names _n315 cache_Rlist1<*1*> _n31c cache_Rlist1$_n30e_n314$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n315 +1 +# cache_Wlist2 [blk_add1 ] = 0 +.names _n322<0> +0 +.names _n322<0> blk_add1<0> _n324<0> +.def 0 +0 1 1 +1 0 1 +.names _n324<0> _n325 +.def 1 +0 0 +.names _n325 _n323 +0 1 +1 0 +.names _n321 cache_Wlist2<*0*> _n323 cache_Wlist2$_n30e_n320$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n327<0> +1 +.names _n327<0> blk_add1<0> _n329<0> +.def 0 +0 1 1 +1 0 1 +.names _n329<0> _n32a +.def 1 +0 0 +.names _n32a _n328 +0 1 +1 0 +.names _n321 cache_Wlist2<*1*> _n328 cache_Wlist2$_n30e_n320$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n321 +0 +# cache_Rlist2 [blk_add1 ] = 1 +.names _n32e<0> +0 +.names _n32e<0> blk_add1<0> _n330<0> +.def 0 +0 1 1 +1 0 1 +.names _n330<0> _n331 +.def 1 +0 0 +.names _n331 _n32f +0 1 +1 0 +.names _n32d cache_Rlist2<*0*> _n32f cache_Rlist2$_n30e_n32c$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n333<0> +1 +.names _n333<0> blk_add1<0> _n335<0> +.def 0 +0 1 1 +1 0 1 +.names _n335<0> _n336 +.def 1 +0 0 +.names _n336 _n334 +0 1 +1 0 +.names _n32d cache_Rlist2<*1*> _n334 cache_Rlist2$_n30e_n32c$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n32d +1 +# arbiter_state = 1 +.mv arbiter_state$_n30e_n338$true 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n30e_n338$true +ONEWAIT +# cache_Wlist1 [0] = 0 +.names _n33b<0> +0 +.names _n33c<0> +0 +.names _n33c<0> _n33b<0> _n33e<0> +.def 0 +0 1 1 +1 0 1 +.names _n33e<0> _n33f +.def 1 +0 0 +.names _n33f _n33d +0 1 +1 0 +.names _n33a cache_Wlist1<*0*> _n33d cache_Wlist1$_n30e_n339$false<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n341<0> +1 +.names _n341<0> _n33b<0> _n343<0> +.def 0 +0 1 1 +1 0 1 +.names _n343<0> _n344 +.def 1 +0 0 +.names _n344 _n342 +0 1 +1 0 +.names _n33a cache_Wlist1<*1*> _n342 cache_Wlist1$_n30e_n339$false<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n33a +0 +# cache_Wlist1 [1] = 0 +.names _n348<0> +1 +.names _n349<0> +0 +.names _n349<0> _n348<0> _n34b<0> +.def 0 +0 1 1 +1 0 1 +.names _n34b<0> _n34c +.def 1 +0 0 +.names _n34c _n34a +0 1 +1 0 +.names _n347 cache_Wlist1$_n30e_n339$false<*0*> _n34a cache_Wlist1$_n30e_n346$false<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n34e<0> +1 +.names _n34e<0> _n348<0> _n350<0> +.def 0 +0 1 1 +1 0 1 +.names _n350<0> _n351 +.def 1 +0 0 +.names _n351 _n34f +0 1 +1 0 +.names _n347 cache_Wlist1$_n30e_n339$false<*1*> _n34f cache_Wlist1$_n30e_n346$false<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n347 +0 +# cache_Rlist1 [blk_add1 ] = 1 +.names _n355<0> +0 +.names _n355<0> blk_add1<0> _n357<0> +.def 0 +0 1 1 +1 0 1 +.names _n357<0> _n358 +.def 1 +0 0 +.names _n358 _n356 +0 1 +1 0 +.names _n354 cache_Rlist1<*0*> _n356 cache_Rlist1$_n30e_n353$false<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n35a<0> +1 +.names _n35a<0> blk_add1<0> _n35c<0> +.def 0 +0 1 1 +1 0 1 +.names _n35c<0> _n35d +.def 1 +0 0 +.names _n35d _n35b +0 1 +1 0 +.names _n354 cache_Rlist1<*1*> _n35b cache_Rlist1$_n30e_n353$false<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n354 +1 +# arbiter_state = 4 +.mv arbiter_state$_n30e_n35f$false 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n30e_n35f$false +ONESERVE +# if/else (cache_Wlist2 [blk_add1 ] == 1) +.names cache_Rlist1$_n30e_n314$true<*0*> cache_Rlist1$_n30e_n353$false<*0*> _n30e cache_Rlist1$_n30e$raw_n366<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n30e_n314$true<*1*> cache_Rlist1$_n30e_n353$false<*1*> _n30e cache_Rlist1$_n30e$raw_n366<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv arbiter_state$_n30e$raw_n369 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n30e_n338$true arbiter_state$_n30e_n35f$false _n30e arbiter_state$_n30e$raw_n369 +- - 0 =arbiter_state$_n30e_n35f$false +- - 1 =arbiter_state$_n30e_n338$true +.names cache_Wlist2$_n30e_n320$true<*0*> cache_Wlist2<*0*> _n30e cache_Wlist2$_n30e$raw_n36a<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n30e_n320$true<*1*> cache_Wlist2<*1*> _n30e cache_Wlist2$_n30e$raw_n36a<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n30e_n32c$true<*0*> cache_Rlist2<*0*> _n30e cache_Rlist2$_n30e$raw_n36d<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n30e_n32c$true<*1*> cache_Rlist2<*1*> _n30e cache_Rlist2$_n30e$raw_n36d<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1<*0*> cache_Wlist1$_n30e_n346$false<*0*> _n30e cache_Wlist1$_n30e$raw_n372<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1<*1*> cache_Wlist1$_n30e_n346$false<*1*> _n30e cache_Wlist1$_n30e$raw_n372<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _n378 4 ok blk_rreq blk_excl noop +.names _n378 +blk_excl +# cache_req1 == 2 +.names cache_req1 _n378 _n377 +.def 0 +- =cache_req1 1 +.names _n377 _n379 +- =_n377 +# cache_Wlist1 [blk_add1 ] = 1 +.names _n37c<0> +0 +.names _n37c<0> blk_add1<0> _n37e<0> +.def 0 +0 1 1 +1 0 1 +.names _n37e<0> _n37f +.def 1 +0 0 +.names _n37f _n37d +0 1 +1 0 +.names _n37b cache_Wlist1<*0*> _n37d cache_Wlist1$_n377_n37a$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n381<0> +1 +.names _n381<0> blk_add1<0> _n383<0> +.def 0 +0 1 1 +1 0 1 +.names _n383<0> _n384 +.def 1 +0 0 +.names _n384 _n382 +0 1 +1 0 +.names _n37b cache_Wlist1<*1*> _n382 cache_Wlist1$_n377_n37a$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n37b +1 +# cache_Rlist1 [blk_add1 ] = 0 +.names _n388<0> +0 +.names _n388<0> blk_add1<0> _n38a<0> +.def 0 +0 1 1 +1 0 1 +.names _n38a<0> _n38b +.def 1 +0 0 +.names _n38b _n389 +0 1 +1 0 +.names _n387 cache_Rlist1<*0*> _n389 cache_Rlist1$_n377_n386$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n38d<0> +1 +.names _n38d<0> blk_add1<0> _n38f<0> +.def 0 +0 1 1 +1 0 1 +.names _n38f<0> _n390 +.def 1 +0 0 +.names _n390 _n38e +0 1 +1 0 +.names _n387 cache_Rlist1<*1*> _n38e cache_Rlist1$_n377_n386$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n387 +0 +# cache_Rlist2 [blk_add1 ] = 0 +.names _n394<0> +0 +.names _n394<0> blk_add1<0> _n396<0> +.def 0 +0 1 1 +1 0 1 +.names _n396<0> _n397 +.def 1 +0 0 +.names _n397 _n395 +0 1 +1 0 +.names _n393 cache_Rlist2<*0*> _n395 cache_Rlist2$_n377_n392$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n399<0> +1 +.names _n399<0> blk_add1<0> _n39b<0> +.def 0 +0 1 1 +1 0 1 +.names _n39b<0> _n39c +.def 1 +0 0 +.names _n39c _n39a +0 1 +1 0 +.names _n393 cache_Rlist2<*1*> _n39a cache_Rlist2$_n377_n392$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n393 +0 +# cache_Wlist2 [blk_add1 ] = 0 +.names _n3a0<0> +0 +.names _n3a0<0> blk_add1<0> _n3a2<0> +.def 0 +0 1 1 +1 0 1 +.names _n3a2<0> _n3a3 +.def 1 +0 0 +.names _n3a3 _n3a1 +0 1 +1 0 +.names _n39f cache_Wlist2<*0*> _n3a1 cache_Wlist2$_n377_n39e$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n3a5<0> +1 +.names _n3a5<0> blk_add1<0> _n3a7<0> +.def 0 +0 1 1 +1 0 1 +.names _n3a7<0> _n3a8 +.def 1 +0 0 +.names _n3a8 _n3a6 +0 1 +1 0 +.names _n39f cache_Wlist2<*1*> _n3a6 cache_Wlist2$_n377_n39e$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n39f +0 +# arbiter_state = 4 +.mv arbiter_state$_n377_n3aa$true 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n377_n3aa$true +ONESERVE +# arbiter_state = 2 +.mv arbiter_state$_n377_n3ab$false 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n377_n3ab$false +TWO +# if/else (cache_req1 == 2) +.mv arbiter_state$_n377$raw_n3b5 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n377_n3aa$true arbiter_state$_n377_n3ab$false _n377 arbiter_state$_n377$raw_n3b5 +- - 0 =arbiter_state$_n377_n3ab$false +- - 1 =arbiter_state$_n377_n3aa$true +.names cache_Wlist1$_n377_n37a$true<*0*> cache_Wlist1<*0*> _n377 cache_Wlist1$_n377$raw_n3b6<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1$_n377_n37a$true<*1*> cache_Wlist1<*1*> _n377 cache_Wlist1$_n377$raw_n3b6<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n377_n39e$true<*0*> cache_Wlist2<*0*> _n377 cache_Wlist2$_n377$raw_n3b9<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n377_n39e$true<*1*> cache_Wlist2<*1*> _n377 cache_Wlist2$_n377$raw_n3b9<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n377_n392$true<*0*> cache_Rlist2<*0*> _n377 cache_Rlist2$_n377$raw_n3bc<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n377_n392$true<*1*> cache_Rlist2<*1*> _n377 cache_Rlist2$_n377$raw_n3bc<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n377_n386$true<*0*> cache_Rlist1<*0*> _n377 cache_Rlist1$_n377$raw_n3bf<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n377_n386$true<*1*> cache_Rlist1<*1*> _n377 cache_Rlist1$_n377$raw_n3bf<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (cache_req1 == 1) +.names cache_Wlist1$_n30e$raw_n372<*0*> cache_Wlist1$_n377$raw_n3b6<*0*> _n30b cache_Wlist1$_n30b$raw_n3c9<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1$_n30e$raw_n372<*1*> cache_Wlist1$_n377$raw_n3b6<*1*> _n30b cache_Wlist1$_n30b$raw_n3c9<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n30e$raw_n36a<*0*> cache_Wlist2$_n377$raw_n3b9<*0*> _n30b cache_Wlist2$_n30b$raw_n3cc<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n30e$raw_n36a<*1*> cache_Wlist2$_n377$raw_n3b9<*1*> _n30b cache_Wlist2$_n30b$raw_n3cc<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n30e$raw_n36d<*0*> cache_Rlist2$_n377$raw_n3bc<*0*> _n30b cache_Rlist2$_n30b$raw_n3cf<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n30e$raw_n36d<*1*> cache_Rlist2$_n377$raw_n3bc<*1*> _n30b cache_Rlist2$_n30b$raw_n3cf<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n30e$raw_n366<*0*> cache_Rlist1$_n377$raw_n3bf<*0*> _n30b cache_Rlist1$_n30b$raw_n3d2<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n30e$raw_n366<*1*> cache_Rlist1$_n377$raw_n3bf<*1*> _n30b cache_Rlist1$_n30b$raw_n3d2<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv arbiter_state$_n30b$raw_n3d5 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n30e$raw_n369 arbiter_state$_n377$raw_n3b5 _n30b arbiter_state$_n30b$raw_n3d5 +- - 0 =arbiter_state$_n377$raw_n3b5 +- - 1 =arbiter_state$_n30e$raw_n369 +.mv _n3e2 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n3e2 +ONESERVE +.names arbiter_state _n3e2 _n3e1 +.def 0 +- =arbiter_state 1 +.names _n3e1 _n3e0 +1 1 +0 0 +# arbiter_state = 2 +.mv arbiter_state$_n3e0_n3e3$true 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n3e0_n3e3$true +TWO +.mv _n3e6 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n3e6 +ONEWAIT +.names arbiter_state _n3e6 _n3e5 +.def 0 +- =arbiter_state 1 +.names _n3e5 _n3e4 +1 1 +0 0 +.mv _n3e8 4 ok blk_rreq blk_excl noop +.names _n3e8 +ok +# cache_req2 == 0 +.names cache_req2 _n3e8 _n3e7 +.def 0 +- =cache_req2 1 +.names _n3e7 _n3e9 +- =_n3e7 +# main_mem [blk_add1 ] = back_data2 +.names _n3ec<0> +0 +.names _n3ec<0> blk_add1<0> _n3ee<0> +.def 0 +0 1 1 +1 0 1 +.names _n3ee<0> _n3ef +.def 1 +0 0 +.names _n3ef _n3ed +0 1 +1 0 +.names _n3eb main_mem<*0*> _n3ed main_mem$_n3e7_n3ea$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n3f1<0> +1 +.names _n3f1<0> blk_add1<0> _n3f3<0> +.def 0 +0 1 1 +1 0 1 +.names _n3f3<0> _n3f4 +.def 1 +0 0 +.names _n3f4 _n3f2 +0 1 +1 0 +.names _n3eb main_mem<*1*> _n3f2 main_mem$_n3e7_n3ea$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names back_data2 _n3eb +- =back_data2 +# arbiter_state = 4 +.mv arbiter_state$_n3e7_n3f6$true 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n3e7_n3f6$true +ONESERVE +# if/else (cache_req2 == 0) +.names main_mem$_n3e7_n3ea$true<*0*> main_mem<*0*> _n3e7 main_mem$_n3e7$raw_n3fb<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names main_mem$_n3e7_n3ea$true<*1*> main_mem<*1*> _n3e7 main_mem$_n3e7$raw_n3fb<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv arbiter_state$_n3e7$raw_n3fe 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n3e7_n3f6$true arbiter_state _n3e7 arbiter_state$_n3e7$raw_n3fe +- - 0 =arbiter_state +- - 1 =arbiter_state$_n3e7_n3f6$true +.mv _n401 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n401 +TWO +.names arbiter_state _n401 _n400 +.def 0 +- =arbiter_state 1 +.names _n400 _n3ff +1 1 +0 0 +.mv _n403 4 ok blk_rreq blk_excl noop +.names _n403 +blk_rreq +# cache_req2 == 1 +.names cache_req2 _n403 _n402 +.def 0 +- =cache_req2 1 +.names _n402 _n404 +- =_n402 +.names cache_Wlist1<*0*> cache_Wlist1<*1*> blk_add2<0> _n406 +0 - 0 0 +1 - 0 1 +- 0 1 0 +- 1 1 1 +.names _n407 +1 +# cache_Wlist1 [blk_add2 ] == 1 +.names _n406 _n407 _n408 +.def 0 +0 1 1 +1 0 1 +.names _n408 _n405 +0 1 +1 0 +.names _n405 _n40a +- =_n405 +# cache_Rlist2 [blk_add2 ] = 1 +.names _n40d<0> +0 +.names _n40d<0> blk_add2<0> _n40f<0> +.def 0 +0 1 1 +1 0 1 +.names _n40f<0> _n410 +.def 1 +0 0 +.names _n410 _n40e +0 1 +1 0 +.names _n40c cache_Rlist2<*0*> _n40e cache_Rlist2$_n405_n40b$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n412<0> +1 +.names _n412<0> blk_add2<0> _n414<0> +.def 0 +0 1 1 +1 0 1 +.names _n414<0> _n415 +.def 1 +0 0 +.names _n415 _n413 +0 1 +1 0 +.names _n40c cache_Rlist2<*1*> _n413 cache_Rlist2$_n405_n40b$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n40c +1 +# cache_Wlist1 [blk_add2 ] = 0 +.names _n419<0> +0 +.names _n419<0> blk_add2<0> _n41b<0> +.def 0 +0 1 1 +1 0 1 +.names _n41b<0> _n41c +.def 1 +0 0 +.names _n41c _n41a +0 1 +1 0 +.names _n418 cache_Wlist1<*0*> _n41a cache_Wlist1$_n405_n417$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n41e<0> +1 +.names _n41e<0> blk_add2<0> _n420<0> +.def 0 +0 1 1 +1 0 1 +.names _n420<0> _n421 +.def 1 +0 0 +.names _n421 _n41f +0 1 +1 0 +.names _n418 cache_Wlist1<*1*> _n41f cache_Wlist1$_n405_n417$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n418 +0 +# cache_Rlist1 [blk_add2 ] = 1 +.names _n425<0> +0 +.names _n425<0> blk_add2<0> _n427<0> +.def 0 +0 1 1 +1 0 1 +.names _n427<0> _n428 +.def 1 +0 0 +.names _n428 _n426 +0 1 +1 0 +.names _n424 cache_Rlist1<*0*> _n426 cache_Rlist1$_n405_n423$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n42a<0> +1 +.names _n42a<0> blk_add2<0> _n42c<0> +.def 0 +0 1 1 +1 0 1 +.names _n42c<0> _n42d +.def 1 +0 0 +.names _n42d _n42b +0 1 +1 0 +.names _n424 cache_Rlist1<*1*> _n42b cache_Rlist1$_n405_n423$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n424 +1 +# arbiter_state = 3 +.mv arbiter_state$_n405_n42f$true 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n405_n42f$true +TWOWAIT +# cache_Wlist2 [0] = 0 +.names _n432<0> +0 +.names _n433<0> +0 +.names _n433<0> _n432<0> _n435<0> +.def 0 +0 1 1 +1 0 1 +.names _n435<0> _n436 +.def 1 +0 0 +.names _n436 _n434 +0 1 +1 0 +.names _n431 cache_Wlist2<*0*> _n434 cache_Wlist2$_n405_n430$false<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n438<0> +1 +.names _n438<0> _n432<0> _n43a<0> +.def 0 +0 1 1 +1 0 1 +.names _n43a<0> _n43b +.def 1 +0 0 +.names _n43b _n439 +0 1 +1 0 +.names _n431 cache_Wlist2<*1*> _n439 cache_Wlist2$_n405_n430$false<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n431 +0 +# cache_Wlist2 [1] = 0 +.names _n43f<0> +1 +.names _n440<0> +0 +.names _n440<0> _n43f<0> _n442<0> +.def 0 +0 1 1 +1 0 1 +.names _n442<0> _n443 +.def 1 +0 0 +.names _n443 _n441 +0 1 +1 0 +.names _n43e cache_Wlist2$_n405_n430$false<*0*> _n441 cache_Wlist2$_n405_n43d$false<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n445<0> +1 +.names _n445<0> _n43f<0> _n447<0> +.def 0 +0 1 1 +1 0 1 +.names _n447<0> _n448 +.def 1 +0 0 +.names _n448 _n446 +0 1 +1 0 +.names _n43e cache_Wlist2$_n405_n430$false<*1*> _n446 cache_Wlist2$_n405_n43d$false<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n43e +0 +# cache_Rlist2 [blk_add2 ] = 1 +.names _n44c<0> +0 +.names _n44c<0> blk_add2<0> _n44e<0> +.def 0 +0 1 1 +1 0 1 +.names _n44e<0> _n44f +.def 1 +0 0 +.names _n44f _n44d +0 1 +1 0 +.names _n44b cache_Rlist2<*0*> _n44d cache_Rlist2$_n405_n44a$false<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n451<0> +1 +.names _n451<0> blk_add2<0> _n453<0> +.def 0 +0 1 1 +1 0 1 +.names _n453<0> _n454 +.def 1 +0 0 +.names _n454 _n452 +0 1 +1 0 +.names _n44b cache_Rlist2<*1*> _n452 cache_Rlist2$_n405_n44a$false<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n44b +1 +# arbiter_state = 5 +.mv arbiter_state$_n405_n456$false 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n405_n456$false +TWOSERVE +# if/else (cache_Wlist1 [blk_add2 ] == 1) +.names cache_Rlist2$_n405_n40b$true<*0*> cache_Rlist2$_n405_n44a$false<*0*> _n405 cache_Rlist2$_n405$raw_n45c<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n405_n40b$true<*1*> cache_Rlist2$_n405_n44a$false<*1*> _n405 cache_Rlist2$_n405$raw_n45c<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv arbiter_state$_n405$raw_n460 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n405_n42f$true arbiter_state$_n405_n456$false _n405 arbiter_state$_n405$raw_n460 +- - 0 =arbiter_state$_n405_n456$false +- - 1 =arbiter_state$_n405_n42f$true +.names cache_Wlist1$_n405_n417$true<*0*> cache_Wlist1<*0*> _n405 cache_Wlist1$_n405$raw_n461<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1$_n405_n417$true<*1*> cache_Wlist1<*1*> _n405 cache_Wlist1$_n405$raw_n461<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n405_n423$true<*0*> cache_Rlist1<*0*> _n405 cache_Rlist1$_n405$raw_n465<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n405_n423$true<*1*> cache_Rlist1<*1*> _n405 cache_Rlist1$_n405$raw_n465<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2<*0*> cache_Wlist2$_n405_n43d$false<*0*> _n405 cache_Wlist2$_n405$raw_n469<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2<*1*> cache_Wlist2$_n405_n43d$false<*1*> _n405 cache_Wlist2$_n405$raw_n469<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _n46f 4 ok blk_rreq blk_excl noop +.names _n46f +blk_excl +# cache_req2 == 2 +.names cache_req2 _n46f _n46e +.def 0 +- =cache_req2 1 +.names _n46e _n470 +- =_n46e +# cache_Wlist1 [blk_add2 ] = 0 +.names _n473<0> +0 +.names _n473<0> blk_add2<0> _n475<0> +.def 0 +0 1 1 +1 0 1 +.names _n475<0> _n476 +.def 1 +0 0 +.names _n476 _n474 +0 1 +1 0 +.names _n472 cache_Wlist1<*0*> _n474 cache_Wlist1$_n46e_n471$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n478<0> +1 +.names _n478<0> blk_add2<0> _n47a<0> +.def 0 +0 1 1 +1 0 1 +.names _n47a<0> _n47b +.def 1 +0 0 +.names _n47b _n479 +0 1 +1 0 +.names _n472 cache_Wlist1<*1*> _n479 cache_Wlist1$_n46e_n471$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n472 +0 +# cache_Rlist1 [blk_add2 ] = 0 +.names _n47f<0> +0 +.names _n47f<0> blk_add2<0> _n481<0> +.def 0 +0 1 1 +1 0 1 +.names _n481<0> _n482 +.def 1 +0 0 +.names _n482 _n480 +0 1 +1 0 +.names _n47e cache_Rlist1<*0*> _n480 cache_Rlist1$_n46e_n47d$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n484<0> +1 +.names _n484<0> blk_add2<0> _n486<0> +.def 0 +0 1 1 +1 0 1 +.names _n486<0> _n487 +.def 1 +0 0 +.names _n487 _n485 +0 1 +1 0 +.names _n47e cache_Rlist1<*1*> _n485 cache_Rlist1$_n46e_n47d$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n47e +0 +# cache_Rlist2 [blk_add2 ] = 0 +.names _n48b<0> +0 +.names _n48b<0> blk_add2<0> _n48d<0> +.def 0 +0 1 1 +1 0 1 +.names _n48d<0> _n48e +.def 1 +0 0 +.names _n48e _n48c +0 1 +1 0 +.names _n48a cache_Rlist2<*0*> _n48c cache_Rlist2$_n46e_n489$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n490<0> +1 +.names _n490<0> blk_add2<0> _n492<0> +.def 0 +0 1 1 +1 0 1 +.names _n492<0> _n493 +.def 1 +0 0 +.names _n493 _n491 +0 1 +1 0 +.names _n48a cache_Rlist2<*1*> _n491 cache_Rlist2$_n46e_n489$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n48a +0 +# cache_Wlist2 [blk_add2 ] = 1 +.names _n497<0> +0 +.names _n497<0> blk_add2<0> _n499<0> +.def 0 +0 1 1 +1 0 1 +.names _n499<0> _n49a +.def 1 +0 0 +.names _n49a _n498 +0 1 +1 0 +.names _n496 cache_Wlist2<*0*> _n498 cache_Wlist2$_n46e_n495$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n49c<0> +1 +.names _n49c<0> blk_add2<0> _n49e<0> +.def 0 +0 1 1 +1 0 1 +.names _n49e<0> _n49f +.def 1 +0 0 +.names _n49f _n49d +0 1 +1 0 +.names _n496 cache_Wlist2<*1*> _n49d cache_Wlist2$_n46e_n495$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n496 +1 +# arbiter_state = 5 +.mv arbiter_state$_n46e_n4a1$true 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n46e_n4a1$true +TWOSERVE +# arbiter_state = 0 +.mv arbiter_state$_n46e_n4a2$false 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n46e_n4a2$false +ONE +# if/else (cache_req2 == 2) +.mv arbiter_state$_n46e$raw_n4ac 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n46e_n4a1$true arbiter_state$_n46e_n4a2$false _n46e arbiter_state$_n46e$raw_n4ac +- - 0 =arbiter_state$_n46e_n4a2$false +- - 1 =arbiter_state$_n46e_n4a1$true +.names cache_Wlist1$_n46e_n471$true<*0*> cache_Wlist1<*0*> _n46e cache_Wlist1$_n46e$raw_n4ad<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1$_n46e_n471$true<*1*> cache_Wlist1<*1*> _n46e cache_Wlist1$_n46e$raw_n4ad<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n46e_n495$true<*0*> cache_Wlist2<*0*> _n46e cache_Wlist2$_n46e$raw_n4b0<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n46e_n495$true<*1*> cache_Wlist2<*1*> _n46e cache_Wlist2$_n46e$raw_n4b0<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n46e_n489$true<*0*> cache_Rlist2<*0*> _n46e cache_Rlist2$_n46e$raw_n4b3<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n46e_n489$true<*1*> cache_Rlist2<*1*> _n46e cache_Rlist2$_n46e$raw_n4b3<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n46e_n47d$true<*0*> cache_Rlist1<*0*> _n46e cache_Rlist1$_n46e$raw_n4b6<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n46e_n47d$true<*1*> cache_Rlist1<*1*> _n46e cache_Rlist1$_n46e$raw_n4b6<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (cache_req2 == 1) +.names cache_Wlist1$_n405$raw_n461<*0*> cache_Wlist1$_n46e$raw_n4ad<*0*> _n402 cache_Wlist1$_n402$raw_n4c0<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1$_n405$raw_n461<*1*> cache_Wlist1$_n46e$raw_n4ad<*1*> _n402 cache_Wlist1$_n402$raw_n4c0<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n405$raw_n469<*0*> cache_Wlist2$_n46e$raw_n4b0<*0*> _n402 cache_Wlist2$_n402$raw_n4c3<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n405$raw_n469<*1*> cache_Wlist2$_n46e$raw_n4b0<*1*> _n402 cache_Wlist2$_n402$raw_n4c3<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n405$raw_n45c<*0*> cache_Rlist2$_n46e$raw_n4b3<*0*> _n402 cache_Rlist2$_n402$raw_n4c6<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n405$raw_n45c<*1*> cache_Rlist2$_n46e$raw_n4b3<*1*> _n402 cache_Rlist2$_n402$raw_n4c6<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n405$raw_n465<*0*> cache_Rlist1$_n46e$raw_n4b6<*0*> _n402 cache_Rlist1$_n402$raw_n4c9<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n405$raw_n465<*1*> cache_Rlist1$_n46e$raw_n4b6<*1*> _n402 cache_Rlist1$_n402$raw_n4c9<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv arbiter_state$_n402$raw_n4cc 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n405$raw_n460 arbiter_state$_n46e$raw_n4ac _n402 arbiter_state$_n402$raw_n4cc +- - 0 =arbiter_state$_n46e$raw_n4ac +- - 1 =arbiter_state$_n405$raw_n460 +.mv _n4d9 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n4d9 +TWOSERVE +.names arbiter_state _n4d9 _n4d8 +.def 0 +- =arbiter_state 1 +.names _n4d8 _n4d7 +1 1 +0 0 +# arbiter_state = 0 +.mv arbiter_state$_n4d7_n4da$true 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n4d7_n4da$true +ONE +.mv _n4dd 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n4dd +TWOWAIT +.names arbiter_state _n4dd _n4dc +.def 0 +- =arbiter_state 1 +.names _n4dc _n4db +1 1 +0 0 +.mv _n4df 4 ok blk_rreq blk_excl noop +.names _n4df +ok +# cache_req1 == 0 +.names cache_req1 _n4df _n4de +.def 0 +- =cache_req1 1 +.names _n4de _n4e0 +- =_n4de +# main_mem [blk_add2 ] = back_data1 +.names _n4e3<0> +0 +.names _n4e3<0> blk_add2<0> _n4e5<0> +.def 0 +0 1 1 +1 0 1 +.names _n4e5<0> _n4e6 +.def 1 +0 0 +.names _n4e6 _n4e4 +0 1 +1 0 +.names _n4e2 main_mem<*0*> _n4e4 main_mem$_n4de_n4e1$true<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n4e8<0> +1 +.names _n4e8<0> blk_add2<0> _n4ea<0> +.def 0 +0 1 1 +1 0 1 +.names _n4ea<0> _n4eb +.def 1 +0 0 +.names _n4eb _n4e9 +0 1 +1 0 +.names _n4e2 main_mem<*1*> _n4e9 main_mem$_n4de_n4e1$true<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names back_data1 _n4e2 +- =back_data1 +# arbiter_state = 5 +.mv arbiter_state$_n4de_n4ed$true 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n4de_n4ed$true +TWOSERVE +# if/else (cache_req1 == 0) +.names main_mem$_n4de_n4e1$true<*0*> main_mem<*0*> _n4de main_mem$_n4de$raw_n4f2<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names main_mem$_n4de_n4e1$true<*1*> main_mem<*1*> _n4de main_mem$_n4de$raw_n4f2<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv arbiter_state$_n4de$raw_n4f5 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n4de_n4ed$true arbiter_state _n4de arbiter_state$_n4de$raw_n4f5 +- - 0 =arbiter_state +- - 1 =arbiter_state$_n4de_n4ed$true +# case (arbiter_state ) +.names main_mem$_n4de$raw_n4f2<*0*> main_mem<*0*> _n4db main_mem$_n4db$raw_n4fa<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names main_mem$_n4de$raw_n4f2<*1*> main_mem<*1*> _n4db main_mem$_n4db$raw_n4fa<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv arbiter_state$_n4db$raw_n4fd 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n4de$raw_n4f5 arbiter_state _n4db arbiter_state$_n4db$raw_n4fd +- - 0 =arbiter_state +- - 1 =arbiter_state$_n4de$raw_n4f5 +.mv arbiter_state$_n4d7$raw_n4ff 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n4d7_n4da$true arbiter_state$_n4db$raw_n4fd _n4d7 arbiter_state$_n4d7$raw_n4ff +- - 0 =arbiter_state$_n4db$raw_n4fd +- - 1 =arbiter_state$_n4d7_n4da$true +.names main_mem<*0*> main_mem$_n4db$raw_n4fa<*0*> _n4d7 main_mem$_n4d7$raw_n501<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names main_mem<*1*> main_mem$_n4db$raw_n4fa<*1*> _n4d7 main_mem$_n4d7$raw_n501<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv arbiter_state$_n3ff$raw_n50e 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n402$raw_n4cc arbiter_state$_n4d7$raw_n4ff _n3ff arbiter_state$_n3ff$raw_n50e +- - 0 =arbiter_state$_n4d7$raw_n4ff +- - 1 =arbiter_state$_n402$raw_n4cc +.names cache_Wlist1$_n402$raw_n4c0<*0*> cache_Wlist1<*0*> _n3ff cache_Wlist1$_n3ff$raw_n50f<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1$_n402$raw_n4c0<*1*> cache_Wlist1<*1*> _n3ff cache_Wlist1$_n3ff$raw_n50f<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n402$raw_n4c3<*0*> cache_Wlist2<*0*> _n3ff cache_Wlist2$_n3ff$raw_n512<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n402$raw_n4c3<*1*> cache_Wlist2<*1*> _n3ff cache_Wlist2$_n3ff$raw_n512<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n402$raw_n4c6<*0*> cache_Rlist2<*0*> _n3ff cache_Rlist2$_n3ff$raw_n515<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n402$raw_n4c6<*1*> cache_Rlist2<*1*> _n3ff cache_Rlist2$_n3ff$raw_n515<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n402$raw_n4c9<*0*> cache_Rlist1<*0*> _n3ff cache_Rlist1$_n3ff$raw_n518<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n402$raw_n4c9<*1*> cache_Rlist1<*1*> _n3ff cache_Rlist1$_n3ff$raw_n518<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names main_mem<*0*> main_mem$_n4d7$raw_n501<*0*> _n3ff main_mem$_n3ff$raw_n51c<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names main_mem<*1*> main_mem$_n4d7$raw_n501<*1*> _n3ff main_mem$_n3ff$raw_n51c<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names main_mem$_n3e7$raw_n3fb<*0*> main_mem$_n3ff$raw_n51c<*0*> _n3e4 main_mem$_n3e4$raw_n522<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names main_mem$_n3e7$raw_n3fb<*1*> main_mem$_n3ff$raw_n51c<*1*> _n3e4 main_mem$_n3e4$raw_n522<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv arbiter_state$_n3e4$raw_n525 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n3e7$raw_n3fe arbiter_state$_n3ff$raw_n50e _n3e4 arbiter_state$_n3e4$raw_n525 +- - 0 =arbiter_state$_n3ff$raw_n50e +- - 1 =arbiter_state$_n3e7$raw_n3fe +.names cache_Wlist1<*0*> cache_Wlist1$_n3ff$raw_n50f<*0*> _n3e4 cache_Wlist1$_n3e4$raw_n529<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1<*1*> cache_Wlist1$_n3ff$raw_n50f<*1*> _n3e4 cache_Wlist1$_n3e4$raw_n529<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2<*0*> cache_Wlist2$_n3ff$raw_n512<*0*> _n3e4 cache_Wlist2$_n3e4$raw_n52c<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2<*1*> cache_Wlist2$_n3ff$raw_n512<*1*> _n3e4 cache_Wlist2$_n3e4$raw_n52c<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2<*0*> cache_Rlist2$_n3ff$raw_n515<*0*> _n3e4 cache_Rlist2$_n3e4$raw_n52f<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2<*1*> cache_Rlist2$_n3ff$raw_n515<*1*> _n3e4 cache_Rlist2$_n3e4$raw_n52f<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1<*0*> cache_Rlist1$_n3ff$raw_n518<*0*> _n3e4 cache_Rlist1$_n3e4$raw_n532<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1<*1*> cache_Rlist1$_n3ff$raw_n518<*1*> _n3e4 cache_Rlist1$_n3e4$raw_n532<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv arbiter_state$_n3e0$raw_n537 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n3e0_n3e3$true arbiter_state$_n3e4$raw_n525 _n3e0 arbiter_state$_n3e0$raw_n537 +- - 0 =arbiter_state$_n3e4$raw_n525 +- - 1 =arbiter_state$_n3e0_n3e3$true +.names main_mem<*0*> main_mem$_n3e4$raw_n522<*0*> _n3e0 main_mem$_n3e0$raw_n539<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names main_mem<*1*> main_mem$_n3e4$raw_n522<*1*> _n3e0 main_mem$_n3e0$raw_n539<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1<*0*> cache_Wlist1$_n3e4$raw_n529<*0*> _n3e0 cache_Wlist1$_n3e0$raw_n53c<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1<*1*> cache_Wlist1$_n3e4$raw_n529<*1*> _n3e0 cache_Wlist1$_n3e0$raw_n53c<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2<*0*> cache_Wlist2$_n3e4$raw_n52c<*0*> _n3e0 cache_Wlist2$_n3e0$raw_n53f<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2<*1*> cache_Wlist2$_n3e4$raw_n52c<*1*> _n3e0 cache_Wlist2$_n3e0$raw_n53f<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2<*0*> cache_Rlist2$_n3e4$raw_n52f<*0*> _n3e0 cache_Rlist2$_n3e0$raw_n542<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2<*1*> cache_Rlist2$_n3e4$raw_n52f<*1*> _n3e0 cache_Rlist2$_n3e0$raw_n542<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1<*0*> cache_Rlist1$_n3e4$raw_n532<*0*> _n3e0 cache_Rlist1$_n3e0$raw_n545<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1<*1*> cache_Rlist1$_n3e4$raw_n532<*1*> _n3e0 cache_Rlist1$_n3e0$raw_n545<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1$_n30b$raw_n3c9<*0*> cache_Wlist1$_n3e0$raw_n53c<*0*> _n308 cache_Wlist1$_n308$raw_n54e<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist1$_n30b$raw_n3c9<*1*> cache_Wlist1$_n3e0$raw_n53c<*1*> _n308 cache_Wlist1$_n308$raw_n54e<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n30b$raw_n3cc<*0*> cache_Wlist2$_n3e0$raw_n53f<*0*> _n308 cache_Wlist2$_n308$raw_n551<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Wlist2$_n30b$raw_n3cc<*1*> cache_Wlist2$_n3e0$raw_n53f<*1*> _n308 cache_Wlist2$_n308$raw_n551<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n30b$raw_n3cf<*0*> cache_Rlist2$_n3e0$raw_n542<*0*> _n308 cache_Rlist2$_n308$raw_n554<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist2$_n30b$raw_n3cf<*1*> cache_Rlist2$_n3e0$raw_n542<*1*> _n308 cache_Rlist2$_n308$raw_n554<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n30b$raw_n3d2<*0*> cache_Rlist1$_n3e0$raw_n545<*0*> _n308 cache_Rlist1$_n308$raw_n557<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cache_Rlist1$_n30b$raw_n3d2<*1*> cache_Rlist1$_n3e0$raw_n545<*1*> _n308 cache_Rlist1$_n308$raw_n557<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv arbiter_state$_n308$raw_n55a 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names arbiter_state$_n30b$raw_n3d5 arbiter_state$_n3e0$raw_n537 _n308 arbiter_state$_n308$raw_n55a +- - 0 =arbiter_state$_n3e0$raw_n537 +- - 1 =arbiter_state$_n30b$raw_n3d5 +.names main_mem<*0*> main_mem$_n3e0$raw_n539<*0*> _n308 main_mem$_n308$raw_n560<*0*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names main_mem<*1*> main_mem$_n3e0$raw_n539<*1*> _n308 main_mem$_n308$raw_n560<*1*> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names blk_ok2$raw_n2f1 blk_ok2 +0 0 +1 1 +.names _n308 _n3e0 _n3e4 _n3e9 _n3ff _n4d7 _n4db _n4e0 _n568 +.def 0 + 0 0 1 1 - - - - 1 + 0 0 0 - 0 0 1 1 1 +.names _n568 main_mem$_n308$raw_n560<*0*> main_mem<*0*> _n569<*0*> +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n568 main_mem$_n308$raw_n560<*1*> main_mem<*1*> _n569<*1*> +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names write_back_req2$raw_n2d4 write_back_req2 +0 0 +1 1 +.names blk_ok1$raw_n2ea blk_ok1 +0 0 +1 1 +.names write_back_req1$raw_n2ca write_back_req1 +0 0 +1 1 +.names inval2$raw_n2c0 inval2 +0 0 +1 1 +.names blk_data$raw_n2de blk_data +0 0 +1 1 +.names inval1$raw_n2b6 inval1 +0 0 +1 1 +.names _n308 _n30d _n313 _n379 _n3e0 _n3e4 _n3ff _n404 _n40a _n470 _n56a +.def 0 + 1 1 0 - - - - - - - 1 + 1 1 0 - - - - - - - 1 + 1 0 - 1 - - - - - - 1 + 0 - - - 0 0 1 1 1 - 1 + 0 - - - 0 0 1 0 - 1 1 +.names _n56a cache_Wlist1$_n308$raw_n54e<*0*> cache_Wlist1<*0*> _n56b<*0*> +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n56a cache_Wlist1$_n308$raw_n54e<*1*> cache_Wlist1<*1*> _n56b<*1*> +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n308 _n30d _n313 _n379 _n3e0 _n3e4 _n3ff _n404 _n40a _n470 _n56c +.def 0 + 1 1 1 - - - - - - - 1 + 1 0 - 1 - - - - - - 1 + 0 - - - 0 0 1 1 0 - 1 + 0 - - - 0 0 1 1 0 - 1 + 0 - - - 0 0 1 0 - 1 1 +.names _n56c cache_Wlist2$_n308$raw_n551<*0*> cache_Wlist2<*0*> _n56d<*0*> +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n56c cache_Wlist2$_n308$raw_n551<*1*> cache_Wlist2<*1*> _n56d<*1*> +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n308 _n30d _n313 _n379 _n3e0 _n3e4 _n3ff _n404 _n40a _n470 _n56e +.def 0 + 1 1 1 - - - - - - - 1 + 1 0 - 1 - - - - - - 1 + 0 - - - 0 0 1 1 1 - 1 + 0 - - - 0 0 1 1 0 - 1 + 0 - - - 0 0 1 0 - 1 1 +.names _n56e cache_Rlist2$_n308$raw_n554<*0*> cache_Rlist2<*0*> _n56f<*0*> +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n56e cache_Rlist2$_n308$raw_n554<*1*> cache_Rlist2<*1*> _n56f<*1*> +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names blocknum$raw_n2f8<0> blocknum<0> +- =blocknum$raw_n2f8<0> +.names _n308 _n30d _n313 _n379 _n3e0 _n3e4 _n3ff _n404 _n40a _n470 _n570 +.def 0 + 1 1 1 - - - - - - - 1 + 1 1 0 - - - - - - - 1 + 1 0 - 1 - - - - - - 1 + 0 - - - 0 0 1 1 1 - 1 + 0 - - - 0 0 1 0 - 1 1 +.names _n570 cache_Rlist1$_n308$raw_n557<*0*> cache_Rlist1<*0*> _n571<*0*> +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n570 cache_Rlist1$_n308$raw_n557<*1*> cache_Rlist1<*1*> _n571<*1*> +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n308 _n30d _n313 _n379 _n3e0 _n3e4 _n3e9 _n3ff _n404 _n40a _n470 _n4d7 _n4db _n4e0 _n572 +.def 0 + 1 1 1 - - - - - - - - - - - 1 + 1 1 0 - - - - - - - - - - - 1 + 1 0 - 1 - - - - - - - - - - 1 + 1 0 - 0 - - - - - - - - - - 1 + 0 - - - 1 - - - - - - - - - 1 + 0 - - - 0 1 1 - - - - - - - 1 + 0 - - - 0 0 - 1 1 1 - - - - 1 + 0 - - - 0 0 - 1 1 0 - - - - 1 + 0 - - - 0 0 - 1 0 - 1 - - - 1 + 0 - - - 0 0 - 1 0 - 0 - - - 1 + 0 - - - 0 0 - 0 - - - 1 - - 1 + 0 - - - 0 0 - 0 - - - 0 1 1 1 +.mv _n573 6 ONE ONEWAIT TWO TWOWAIT ONESERVE TWOSERVE +.names _n572 arbiter_state$_n308$raw_n55a arbiter_state _n573 +1 - - =arbiter_state$_n308$raw_n55a +0 - - =arbiter_state +# non-blocking assignments +# latches +.r main_mem$raw_n275<*0*> main_mem<*0*> +.def 0 +1 1 +.r main_mem$raw_n275<*1*> main_mem<*1*> +.def 0 +1 1 +.latch _n569<*0*> main_mem<*0*> +.latch _n569<*1*> main_mem<*1*> +.r cache_Wlist1$raw_n29c<*0*> cache_Wlist1<*0*> +.def 0 +1 1 +.r cache_Wlist1$raw_n29c<*1*> cache_Wlist1<*1*> +.def 0 +1 1 +.latch _n56b<*0*> cache_Wlist1<*0*> +.latch _n56b<*1*> cache_Wlist1<*1*> +.r cache_Wlist2$raw_n2a9<*0*> cache_Wlist2<*0*> +.def 0 +1 1 +.r cache_Wlist2$raw_n2a9<*1*> cache_Wlist2<*1*> +.def 0 +1 1 +.latch _n56d<*0*> cache_Wlist2<*0*> +.latch _n56d<*1*> cache_Wlist2<*1*> +.r cache_Rlist2$raw_n28f<*0*> cache_Rlist2<*0*> +.def 0 +1 1 +.r cache_Rlist2$raw_n28f<*1*> cache_Rlist2<*1*> +.def 0 +1 1 +.latch _n56f<*0*> cache_Rlist2<*0*> +.latch _n56f<*1*> cache_Rlist2<*1*> +.r cache_Rlist1$raw_n282<*0*> cache_Rlist1<*0*> +.def 0 +1 1 +.r cache_Rlist1$raw_n282<*1*> cache_Rlist1<*1*> +.def 0 +1 1 +.latch _n571<*0*> cache_Rlist1<*0*> +.latch _n571<*1*> cache_Rlist1<*1*> +.r arbiter_state$raw_n229 arbiter_state +- =arbiter_state$raw_n229 +.latch _n573 arbiter_state +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/coherence/coherence.v =================================================================== --- vis_dev/vis-2.1/examples/coherence/coherence.v (revision 11) +++ vis_dev/vis-2.1/examples/coherence/coherence.v (revision 11) @@ -0,0 +1,74 @@ + `define address_size 0 // nb of bits - 1 of addressÊof blocs in memory + `define mem_size 1 // number of blocks in memory - 1 + + typedef enum {INVALID, SHARED, EXCLUSIVE} Block_status; + typedef enum { Ready, Rwait, Wwait, Rgrant, Wgrant} + Cache_status; + typedef enum { COMPUTE, READ_WORD, WRITE_WORD } Instruction_type; + typedef enum { IDLE, READING, WRITING } Processor_state; + typedef enum { ONE, ONEWAIT,TWO, TWOWAIT, ONESERVE, TWOSERVE} Arbiter_status; +// typedef enum { HIT,MISS,NOP} Cache_rwtype; + typedef enum {ok, blk_rreq, blk_excl, noop} Cache_reqstatus; + +// This is the main module +// It has 3 types of sub,modules + +module COHERANCE(clk, + any_address1, any_value1,inst1, //address, data, instruction for 1 + any_address2, any_value2,inst2); + + +input [`address_size:0] any_address1; +input [`address_size:0] any_address2; +input any_value1; +input any_value2; +input inst1; +input inst2; +input clk; + + +wire acknowledge1; // output: to processor +wire read_req1, write_req1, data1; // input: requests from processor +wire [`address_size:0] address1; // input: requests from processor +Instruction_type wire inst1; +wire acknowledge2; // output: to processor +wire read_req2, write_req2, data2; // input: requests from processor +wire [`address_size:0] address2; // input: requests from processor +Instruction_type wire inst2; +wire back_data; + wire blk_add1; + wire blk_add2; + wire blk_data; + wire write_back_req1; + wire write_back_req2; + wire blk_ok1; + wire blk_ok2; + wire inval1; + wire inval2; + wire inval3; + wire [`address_size:0] blocknum; + wire wbr1; + wire wbr2; + Cache_reqstatus wire cache_req1; + Cache_reqstatus wire cache_req2; + + +PROC proc1(clk, read_req1, write_req1, data1, address1, acknowledge1, any_address1, any_value1, inst1); +CACHE_CTRLER cc1(clk,read_req1, write_req1, data1, address1,acknowledge1,write_back_req1, inval1, blocknum,blk_ok1, blk_data,back_data1, cache_req1,blk_add1); + +PROC proc2(clk, read_req2, write_req2, data2, address2, acknowledge2, any_address2, any_value2, inst2); +CACHE_CTRLER cc2(clk,read_req2, write_req2, data2, address2,acknowledge2,write_back_req2, inval2, blocknum,blk_ok2, blk_data,back_data2, cache_req2,blk_add2); + +DIRECTORY direc(clk,write_back_req1, inval1,write_back_req2, inval2,blocknum, blk_ok1, blk_data,blk_ok2, back_data1, cache_req1, blk_add1,back_data2, cache_req2, blk_add2); + +endmodule +`include cache_ctrl.v +`include processor.v +`include directory.v + + + + + + + Index: vis_dev/vis-2.1/examples/coherence/coherence1.ctl =================================================================== --- vis_dev/vis-2.1/examples/coherence/coherence1.ctl (revision 11) +++ vis_dev/vis-2.1/examples/coherence/coherence1.ctl (revision 11) @@ -0,0 +1,9 @@ +#The directory contains information about the cache content +#that is coherent with the information in the cache controller +# If the block is in state SHARED in the cache controller, its corresponding +# bit is set in the Rlist of the directory + +AG(((direc.cache_Rlist1<*1*> = 1) -> AX((cc1.block_state=SHARED) * (cc1.block_add<0>=1))) + ((((cc1.block_state=SHARED) * (cc1.block_add<0>=1))) -> (direc.cache_Rlist1<*1*> = 1))); + + + Index: vis_dev/vis-2.1/examples/coherence/coherence2.ctl =================================================================== --- vis_dev/vis-2.1/examples/coherence/coherence2.ctl (revision 11) +++ vis_dev/vis-2.1/examples/coherence/coherence2.ctl (revision 11) @@ -0,0 +1,6 @@ +#The directory contains information about the cache content +#that is coherent with the information in the cache controller +# If the block is in state EXCLUSIVE in the cache controller, its corresponding +# bit is set in the Wlist of the directory + +AG(((cc1.block_state = EXCLUSIVE)*(cc1.block_add<0> = 0)) -> (direc.cache_Wlist1<*0*> = 1)); Index: vis_dev/vis-2.1/examples/coherence/directory.v =================================================================== --- vis_dev/vis-2.1/examples/coherence/directory.v (revision 11) +++ vis_dev/vis-2.1/examples/coherence/directory.v (revision 11) @@ -0,0 +1,207 @@ +module DIRECTORY( + clk, + write_back_req1, inval1, // output: requests from directory + write_back_req2, inval2, // output: requests from directory + blocknum, // output: requests from directory + blk_ok1, blk_data, // output: answers from directory + blk_ok2, // output: answers from directory + back_data1, cache_req1, blk_add1, // input: to directory + back_data2, cache_req2, blk_add2); // input: to directory + + + input clk; + output [`address_size:0] blocknum; // output: requests from directory + output write_back_req1, inval1; // output: requests from directory + output blk_ok1; // output: answers from directory + output blk_data; + input back_data1; // input: to directory + output write_back_req2, inval2; // output: requests from directory + output blk_ok2; // output: answers from directory + input back_data2; // input: to directory + input [`address_size:0] blk_add1; // input: to directory + input [`address_size:0] blk_add2; // input: to directory + input cache_req1; // input to directory + input cache_req2; // input to directory + + reg main_mem [`mem_size:0]; + reg cache_Rlist1 [`mem_size:0]; + reg cache_Rlist2 [`mem_size:0]; + + reg cache_Wlist1 [`mem_size:0]; + reg cache_Wlist2 [`mem_size:0]; + + wire blk_data; + wire write_back_req1; + wire write_back_req2; + + wire blk_ok1; + wire blk_ok2; + + wire inval1; + wire inval2; + + wire [`address_size:0] blocknum; + + Cache_reqstatus wire cache_req1; + Cache_reqstatus wire cache_req2; + + + Arbiter_status reg arbiter_state; + + initial begin + arbiter_state = ONE; +// initialize all memory + for (i=0; i<=`mem_size; i =i+1) + begin + main_mem[i] =0; + cache_Rlist1[i]=0; + cache_Rlist2[i]=0; + cache_Wlist1[i]=0; + cache_Wlist2[i]=0; + end + end + + assign inval1 = ((arbiter_state==TWO)&&(cache_req2==blk_excl))?1:0; + assign inval2 = ((arbiter_state==ONE)&&(cache_req1==blk_excl))?1:0; + assign write_back_req1 = ((arbiter_state==TWOWAIT)&&(cache_req1 != ok))?1:0; + assign write_back_req2 = ((arbiter_state==ONEWAIT)&&(cache_req2 != ok))?1:0; + assign blk_data = (arbiter_state==ONESERVE) ? main_mem[blk_add1]: + (arbiter_state==TWOSERVE) ? main_mem[blk_add2]: 0; + assign blk_ok1 = (arbiter_state==ONESERVE) ? 1:0; + assign blk_ok2 = (arbiter_state==TWOSERVE) ? 1:0; + assign blocknum = ((arbiter_state==ONE)&&(cache_req1==blk_excl))? + blk_add1: + ((arbiter_state==TWO)&&(cache_req2==blk_excl))? + blk_add2:0; + + always @(posedge clk) begin + + // Ok now I put in the arbiter + // a one clock cycle delay + // asumption a cc will not put down its request until serviced + +case ( arbiter_state ) + ONE: begin + if (cache_req1 == blk_rreq) + begin + if (cache_Wlist2[blk_add1]==1) + // one requests a read and someone has that address in wx + begin + cache_Rlist1[blk_add1] = 1; + // The processor that returned the data is no longer in write X + cache_Wlist2[blk_add1] = 0; + cache_Rlist2[blk_add1] = 1; + arbiter_state = ONEWAIT; + end + else + begin + //one request a read and non-one has the address in wx + // any block in write access overwritten in cache1 + // remove all address from Wlist1 + for (i=0; i<=`mem_size; i =i+1) + begin + cache_Wlist1[i]=0; + end + cache_Rlist1[blk_add1] = 1; + arbiter_state = ONESERVE; + end + end + // one requests a write + else if (cache_req1 == blk_excl) + begin + cache_Wlist1[blk_add1] = 1; + cache_Rlist1[blk_add1] = 0; + cache_Rlist2[blk_add1] = 0; + cache_Wlist2[blk_add1] = 0; + arbiter_state = ONESERVE; + end + else + begin + arbiter_state = TWO; + end + end + + // servicing a request from cache 1 + + ONESERVE: arbiter_state = TWO; + + // waiting for write_back from cache 2 + + + ONEWAIT: begin + if (cache_req2 == ok) + // if the processor has just returned data which it was asked for + // update memory if write ex clcache + begin + main_mem[blk_add1] = back_data2; + arbiter_state = ONESERVE; + end + end +// +// Symmetric statements for TWO +// + TWO: begin + if (cache_req2 == blk_rreq) + begin + if (cache_Wlist1[blk_add2]==1) +// TWO requests a read and someone has that address in wx + begin + cache_Rlist2[blk_add2] = 1; +// The processor that returned the data is no longer in write X + cache_Wlist1[blk_add2] = 0; + cache_Rlist1[blk_add2] = 1; + arbiter_state = TWOWAIT; + end + else + begin +//TWO request a read and non-one has the address in wx +// any block in write access overwritten in cache1 +// remove all address from Wlist2 + for (i=0; i<=`mem_size; i =i+1) + begin + cache_Wlist2[i]=0; + end + cache_Rlist2[blk_add2] = 1; + arbiter_state = TWOSERVE; + end + end +// two requests a write + else if (cache_req2 == blk_excl) + begin + // blocknum = blk_add2; + cache_Wlist1[blk_add2] = 0; + cache_Rlist1[blk_add2] = 0; + cache_Rlist2[blk_add2] = 0; + cache_Wlist2[blk_add2] = 1; + arbiter_state = TWOSERVE; + end + else + begin + arbiter_state = ONE; + end + end + +// servicing a request from cache 2 + + TWOSERVE: arbiter_state = ONE; + +// if waiting for write_back + + + TWOWAIT: begin +// if the processor has just returned data which it was asked for +// update memory if write ex clcache + if (cache_req1 == ok) + begin + main_mem[blk_add2] = back_data1; + arbiter_state = TWOSERVE; + end + end + default:; + endcase; + end +endmodule + + + + Index: vis_dev/vis-2.1/examples/coherence/exclusive1.ctl =================================================================== --- vis_dev/vis-2.1/examples/coherence/exclusive1.ctl (revision 11) +++ vis_dev/vis-2.1/examples/coherence/exclusive1.ctl (revision 11) @@ -0,0 +1,5 @@ +# Two caches do not have exclusive access to the same block + +AG(((cc1.block_state=EXCLUSIVE) * (cc2.block_state=EXCLUSIVE)) -> + (((cc1.block_add<0> = 0) *(cc2.block_add<0>=1)+ + ((cc1.block_add<0> = 1)*(cc2.block_add<0>=0))))); Index: vis_dev/vis-2.1/examples/coherence/exclusive2.ctl =================================================================== --- vis_dev/vis-2.1/examples/coherence/exclusive2.ctl (revision 11) +++ vis_dev/vis-2.1/examples/coherence/exclusive2.ctl (revision 11) @@ -0,0 +1,8 @@ +# If a cache has exclusive access to a block, then the other cache +# has no access to that block +# Property for block 0 owned by cache 1 + +AG(((cc1.block_state=EXCLUSIVE) * (cc1.block_add<0> = 0)) -> + ((cc2.block_state=INVALID) + ! (cc2.block_add<0> = 0)) ); + + Index: vis_dev/vis-2.1/examples/coherence/liveness1.ctl =================================================================== --- vis_dev/vis-2.1/examples/coherence/liveness1.ctl (revision 11) +++ vis_dev/vis-2.1/examples/coherence/liveness1.ctl (revision 11) @@ -0,0 +1,4 @@ +# liveness property one: a read request from processor 1 will eventually +# be serviced + +AG (( proc1.proc_state = READING ) -> AF (proc1.acknowledge = 1)); Index: vis_dev/vis-2.1/examples/coherence/liveness2.ctl =================================================================== --- vis_dev/vis-2.1/examples/coherence/liveness2.ctl (revision 11) +++ vis_dev/vis-2.1/examples/coherence/liveness2.ctl (revision 11) @@ -0,0 +1,1 @@ +AG(proc1.proc_state = READING -> AF(proc1.proc_state=IDLE)); Index: vis_dev/vis-2.1/examples/coherence/p2.ctl =================================================================== --- vis_dev/vis-2.1/examples/coherence/p2.ctl (revision 11) +++ vis_dev/vis-2.1/examples/coherence/p2.ctl (revision 11) @@ -0,0 +1,8 @@ +# If a cache has exclusive access to a block, then the other cache +# has no access to that block +# Property for block 0 owned by cache 1 +AG(((cc1.block_state=EXCLUSIVE) * (cc1.block_add<0> = 1)) -> + ((cc2.block_state=INVALID) + ! (cc2.block_add<0> = 1))); + + + Index: vis_dev/vis-2.1/examples/coherence/p3.ctl =================================================================== --- vis_dev/vis-2.1/examples/coherence/p3.ctl (revision 11) +++ vis_dev/vis-2.1/examples/coherence/p3.ctl (revision 11) @@ -0,0 +1,9 @@ +#The directory contains information about the cache content +#that is coherent with the information in the cache controller +# If the block is in state SHARED in the cache controller, its corresponding +# bit is set in the Rlist of the directory +AG(((direc.cache_Rlist1<*0*> = 1) -> AX((cc1.block_state=SHARED) * (cc1.block_add<0>=0))) + + ((((cc1.block_state=SHARED) * (cc1.block_add<0>=1))) -> (direc.cache_Rlist1<*0*> = 1))); + + + Index: vis_dev/vis-2.1/examples/coherence/p4.ctl =================================================================== --- vis_dev/vis-2.1/examples/coherence/p4.ctl (revision 11) +++ vis_dev/vis-2.1/examples/coherence/p4.ctl (revision 11) @@ -0,0 +1,8 @@ +#The directory contains information about the cache content +#that is coherent with the information in the cache controller +# If the block is in state EXCLUSIVE in the cache controller, its corresponding +# bit is set in the Wlist of the directory +# FAILS +AG(((cc1.cache_req = blk_rreq)*(direc.arbiter_state = ONE)*(cc1.blk_add<0>=0)*(direc.cache_Wlist2<*0*> = 1)) -> (cc2.block_state = EXCLUSIVE)); + + Index: vis_dev/vis-2.1/examples/coherence/p5.ctl =================================================================== --- vis_dev/vis-2.1/examples/coherence/p5.ctl (revision 11) +++ vis_dev/vis-2.1/examples/coherence/p5.ctl (revision 11) @@ -0,0 +1,7 @@ +# Safety property one: a read request from processor 1 will eventually +# be serviced +AG (( proc1.proc_state = READING ) -> AF (proc1.acknowledge = 1)); + + + + Index: vis_dev/vis-2.1/examples/coherence/processor.v =================================================================== --- vis_dev/vis-2.1/examples/coherence/processor.v (revision 11) +++ vis_dev/vis-2.1/examples/coherence/processor.v (revision 11) @@ -0,0 +1,74 @@ +module PROC ( + clk, + read_req, write_req, data, address, // output: requests to cache + acknowledge, // input: answer from cache + any_address, any_value, inst // input: for non determinism + ); + +input clk; +output read_req, write_req, data; // output: requests to cache +output [`address_size:0] address; // output: request to cache +input acknowledge; // input: answer from cache +input [`address_size:0] any_address; +input any_value; +input inst; + +wire read_req, write_req, data; +wire [`address_size:0] address; +Instruction_type wire inst; +Processor_state reg proc_state; + // local data of the processor + +initial begin + proc_state = IDLE; +end + +assign read_req = ((proc_state==IDLE)?((inst==READ_WORD)?1:0):((proc_state == READING)?1:0)); +assign write_req = ((proc_state==IDLE)?((inst==WRITE_WORD)?1:0):((proc_state == WRITING)?1:0)); +assign data = any_value; +assign address = any_address; + +always @(posedge clk) begin + case ( proc_state ) + + IDLE : + begin + case (inst) + + COMPUTE: begin + proc_state = IDLE; + end + + READ_WORD: begin + proc_state = READING; + end + + WRITE_WORD: begin + proc_state = WRITING; + end + + default: begin + proc_state = IDLE; + end + + endcase; + end + READING : + if (acknowledge) // data arrived from cache + begin + proc_state = IDLE; + end + + + WRITING : + if (acknowledge) // data arrived from cache + begin + proc_state = IDLE; + end + + + endcase; +end // end of always statement describing processor automaton +endmodule + + Index: vis_dev/vis-2.1/examples/counter/affalse =================================================================== --- vis_dev/vis-2.1/examples/counter/affalse (revision 11) +++ vis_dev/vis-2.1/examples/counter/affalse (revision 11) @@ -0,0 +1,1 @@ +AF FALSE; Index: vis_dev/vis-2.1/examples/counter/check_result =================================================================== --- vis_dev/vis-2.1/examples/counter/check_result (revision 11) +++ vis_dev/vis-2.1/examples/counter/check_result (revision 11) @@ -0,0 +1,3 @@ +# MC: formula failed --- AF(FALSE) +# LE: language is not empty +# MC: formula passed --- AG(AF(bit2.carry_out=1)) Index: vis_dev/vis-2.1/examples/counter/check_script =================================================================== --- vis_dev/vis-2.1/examples/counter/check_script (revision 11) +++ vis_dev/vis-2.1/examples/counter/check_script (revision 11) @@ -0,0 +1,7 @@ +read_blif_mv counter.mv +init_verify +model_check -d 0 affalse +lang_empty -d 0 +model_check -d 0 counter.ctl +time +quit -s Index: vis_dev/vis-2.1/examples/counter/counter.ctl =================================================================== --- vis_dev/vis-2.1/examples/counter/counter.ctl (revision 11) +++ vis_dev/vis-2.1/examples/counter/counter.ctl (revision 11) @@ -0,0 +1,1 @@ +AG AF (bit2.carry_out=1) ; Index: vis_dev/vis-2.1/examples/counter/counter.mv =================================================================== --- vis_dev/vis-2.1/examples/counter/counter.mv (revision 11) +++ vis_dev/vis-2.1/examples/counter/counter.mv (revision 11) @@ -0,0 +1,120 @@ +# vl2mv counter.v +# version: 0.2 +# date: 11:12:24 12/11/95 (PST) +.model counter +# I/O ports + +.names _n0 +1 +.subckt counter_cell bit0 carry_in=_n0 carry_out=out0 +.subckt counter_cell bit1 carry_in=out0 carry_out=out1 +.subckt counter_cell bit2 carry_in=out1 carry_out=out2 +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model counter_cell +# I/O ports +.inputs carry_in +.outputs carry_out + +# assign carry_out = value & carry_in +# value & carry_in +.names value carry_in _n2 +.def 0 +1 1 1 +.names _n2 carry_out$raw_n1 +- =_n2 +# value = 0 +.names value$raw_n3 +0 +# non-blocking assignments for initial +.names _n6 +0 +.names value _n6 _n7 +.def 0 +0 1 1 +1 0 1 +.names _n7 _n5 +0 1 +1 0 +.names _n5 _n4 +1 1 +0 0 +# value = carry_in +.names carry_in value$_n4_n9$true +- =carry_in +.names _nc +1 +.names value _nc _nd +.def 0 +0 1 1 +1 0 1 +.names _nd _nb +0 1 +1 0 +.names _nb _na +1 1 +0 0 +.names _n10 +0 +# carry_in == 0 +.names carry_in _n10 _n11 +.def 0 +0 1 1 +1 0 1 +.names _n11 _nf +0 1 +1 0 +.names _nf _n13 +- =_nf +# value = 1 +.names value$_nf_n14$true +1 +# value = 0 +.names value$_nf_n15$false +0 +# if/else (carry_in == 0) +.names value$_nf_n14$true value$_nf_n15$false _nf value$_nf$raw_n17 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# case (value ) +.names value$_nf$raw_n17 value _na value$_na$raw_n1d +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names value$_n4_n9$true value$_na$raw_n1d _n4 value$_n4$raw_n1f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names _n4 _na _n13 _n24 +.def 0 + 1 - - 1 + 0 1 1 1 + 0 1 0 1 +.names _n24 value$_n4$raw_n1f value _n25 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names carry_out$raw_n1 carry_out +0 0 +1 1 +# non-blocking assignments +# latches +.r value$raw_n3 value +0 0 +1 1 +.latch _n25 value +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/counter/counter.v =================================================================== --- vis_dev/vis-2.1/examples/counter/counter.v (revision 11) +++ vis_dev/vis-2.1/examples/counter/counter.v (revision 11) @@ -0,0 +1,42 @@ +/* translation of counter.smv to verilog + + Sriram Krishnan 7/93. + + + +*/ + + + +module counter(clk); +input clk; + +wire out0, out1, out2; + +counter_cell bit0 (clk, 1, out0); +counter_cell bit1 (clk, out0, out1); +counter_cell bit2 (clk, out1, out2); + +endmodule + +module counter_cell(clk, carry_in, carry_out); +input clk; +input carry_in; +output carry_out; +reg value; + +assign carry_out = value & carry_in; + +initial value = 0; + +always @(posedge clk) begin +// value = (value + carry_in) % 2; + case(value) + 0: value = carry_in; + 1: if (carry_in ==0) + value = 1; + else value = 0; + endcase +end +endmodule + Index: vis_dev/vis-2.1/examples/counter/test.prop =================================================================== --- vis_dev/vis-2.1/examples/counter/test.prop (revision 11) +++ vis_dev/vis-2.1/examples/counter/test.prop (revision 11) @@ -0,0 +1,1 @@ +( FALSE ) Index: vis_dev/vis-2.1/examples/counter/test_bmc =================================================================== --- vis_dev/vis-2.1/examples/counter/test_bmc (revision 11) +++ vis_dev/vis-2.1/examples/counter/test_bmc (revision 11) @@ -0,0 +1,10 @@ +read_blif_mv counter.mv +flatten_hierarchy +static_order +build_partition_mdds +set_init -v 1 +robustness -v 1 +build_partition_maigs +conv_bdd_cnf counter.ctl +quit -s +bounded_model_check -m 4 -k 10 -v 1 test.prop Index: vis_dev/vis-2.1/examples/crd/README =================================================================== --- vis_dev/vis-2.1/examples/crd/README (revision 11) +++ vis_dev/vis-2.1/examples/crd/README (revision 11) @@ -0,0 +1,21 @@ +read_blif_mv crd.mv +init +mc crd_rs.ctl +#we are just checking for reachability +mc lang_empt.ctl +# the language should not be empty at this stage. +read_fairness crd.fair +mc lang_empt.ctl +# it should still not be empty +mc starvation.ctl +#should pass +mc starvation2.ctl +#should pass. this just uses monitor "starvation" instead of at the root. +#in hsis we did this with fairness constraints on starvation, but we +# cannot express these with Buchi conditions (same as in ping_pong. +mc safety.ctl +#this should pass +read_fairness safety.fair +# we have put fairness constraints on the monitor "collision" +mc lang_empt.ctl +#this should pass since we only accept bad behavior. Index: vis_dev/vis-2.1/examples/crd/affalse =================================================================== --- vis_dev/vis-2.1/examples/crd/affalse (revision 11) +++ vis_dev/vis-2.1/examples/crd/affalse (revision 11) @@ -0,0 +1,1 @@ +AF FALSE; Index: vis_dev/vis-2.1/examples/crd/agtrue =================================================================== --- vis_dev/vis-2.1/examples/crd/agtrue (revision 11) +++ vis_dev/vis-2.1/examples/crd/agtrue (revision 11) @@ -0,0 +1,1 @@ +AG TRUE; Index: vis_dev/vis-2.1/examples/crd/check_result =================================================================== --- vis_dev/vis-2.1/examples/crd/check_result (revision 11) +++ vis_dev/vis-2.1/examples/crd/check_result (revision 11) @@ -0,0 +1,7 @@ +# MC: formula passed --- AG(TRUE) +# LE: language is not empty +# MC: formula failed --- AF(FALSE) +# MC: formula passed --- AG((status_A=car_waiting -> AF(status_A=cars_passing))) +# MC: formula passed --- AG((starv.state=NOT_OK -> AF(starv.state=OK))) +# MC: formula passed --- AG((!(status_A=cars_passing) + !(status_B=cars_passing))) +# LE: language emptiness check passes Index: vis_dev/vis-2.1/examples/crd/check_script =================================================================== --- vis_dev/vis-2.1/examples/crd/check_script (revision 11) +++ vis_dev/vis-2.1/examples/crd/check_script (revision 11) @@ -0,0 +1,16 @@ +read_blif_mv crd.mv +init_verify +model_check -d 0 agtrue +print_fairness +lang_empty -d 0 +model_check -d 0 affalse +read_fairness crd.fair +print_fairness +model_check -d 0 starvation.ctl +model_check -d 0 starvation2.ctl +model_check -d 0 safety.ctl +read_fairness safety.fair +print_fairness +lang_empty -d 0 +time +quit -s Index: vis_dev/vis-2.1/examples/crd/crd.fair =================================================================== --- vis_dev/vis-2.1/examples/crd/crd.fair (revision 11) +++ vis_dev/vis-2.1/examples/crd/crd.fair (revision 11) @@ -0,0 +1,5 @@ +!(police.state=go_A_init); +!(police.state=go_B_init); +!(road_A.state=STOPPED_init); +!(road_B.state=STOPPED_init); + Index: vis_dev/vis-2.1/examples/crd/crd.mv =================================================================== --- vis_dev/vis-2.1/examples/crd/crd.mv (revision 11) +++ vis_dev/vis-2.1/examples/crd/crd.mv (revision 11) @@ -0,0 +1,885 @@ +# vl2mv crd.v +# version: 0.2 +# date: 11:12:45 12/11/95 (PST) +.model environment +# I/O ports +.outputs test +.outputs status_A + +.mv status_B 3 no_cars car_waiting cars_passing +.mv signal_B 3 stop go slow +.mv status_A 3 no_cars car_waiting cars_passing +.mv signal_A 3 stop go slow +.mv signal 3 go_slow go_A go_B +.subckt POLICEMAN police status_A=status_A status_B=status_B signal=signal +# assign signal_A = (signal == go_A ) ? 1 : (signal == go_slow ) ? 2 : 0 +.mv signal_A$raw_n0 3 stop go slow +.mv _n2 3 go_slow go_A go_B +.names _n2 +go_A +# signal == 1 +.names signal _n2 _n1 +.def 0 +- =signal 1 +.mv _n4 3 go_slow go_A go_B +.names _n4 +go_slow +# signal == 0 +.names signal _n4 _n3 +.def 0 +- =signal 1 +.mv _n5 3 stop go slow +.names _n5 +slow +.mv _n6 3 stop go slow +.names _n6 +stop +# (signal == 0) ? 2 : 0 +.mv _n7 3 stop go slow +.names _n5 _n6 _n3 _n7 +- - 0 =_n6 +- - 1 =_n5 +.mv _n8 3 stop go slow +.names _n8 +go +# (signal == 1) ? 1 : (signal == 0) ? 2 : 0 +.mv _n9 3 stop go slow +.names _n8 _n7 _n1 _n9 +- - 0 =_n7 +- - 1 =_n8 +.names _n9 signal_A$raw_n0 +- =_n9 +# assign signal_B = (signal == go_B ) ? 1 : (signal == go_slow ) ? 2 : 0 +.mv signal_B$raw_na 3 stop go slow +.mv _nc 3 go_slow go_A go_B +.names _nc +go_B +# signal == 2 +.names signal _nc _nb +.def 0 +- =signal 1 +.mv _ne 3 go_slow go_A go_B +.names _ne +go_slow +# signal == 0 +.names signal _ne _nd +.def 0 +- =signal 1 +.mv _nf 3 stop go slow +.names _nf +slow +.mv _n10 3 stop go slow +.names _n10 +stop +# (signal == 0) ? 2 : 0 +.mv _n11 3 stop go slow +.names _nf _n10 _nd _n11 +- - 0 =_n10 +- - 1 =_nf +.mv _n12 3 stop go slow +.names _n12 +go +# (signal == 2) ? 1 : (signal == 0) ? 2 : 0 +.mv _n13 3 stop go slow +.names _n12 _n11 _nb _n13 +- - 0 =_n11 +- - 1 =_n12 +.names _n13 signal_B$raw_na +- =_n13 +.subckt ROAD road_A signal=signal_A status=status_A +.subckt ROAD road_B signal=signal_B status=status_B +# assign test = ((status_A == cars_passing ) && (status_B == cars_passing )) ? 0 : 1 +.mv _n16 3 no_cars car_waiting cars_passing +.names _n16 +cars_passing +# status_A == 2 +.names status_A _n16 _n15 +.def 0 +- =status_A 1 +.mv _n18 3 no_cars car_waiting cars_passing +.names _n18 +cars_passing +# status_B == 2 +.names status_B _n18 _n17 +.def 0 +- =status_B 1 +# (status_A == 2) && (status_B == 2) +.names _n15 _n17 _n19 +.def 0 +1 1 1 +.names _n1a +0 +.names _n1b +1 +# ((status_A == 2) && (status_B == 2)) ? 0 : 1 +.names _n1a _n1b _n19 _n1c +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1c test$raw_n14 +- =_n1c +.subckt collision col status_A=status_A status_B=status_B +.subckt starvation starv stat=status_A +# conflict arbitrators +.names test$raw_n14 test +0 0 +1 1 +.names signal_B$raw_na signal_B +- =signal_B$raw_na +.names signal_A$raw_n0 signal_A +- =signal_A$raw_n0 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model POLICEMAN +# I/O ports +.inputs status_B +.inputs status_A +.outputs signal + +.mv status_B 3 no_cars car_waiting cars_passing +.mv status_A 3 no_cars car_waiting cars_passing +.mv signal 3 go_slow go_A go_B +.mv state 4 go_A_init go_A_state go_B_init go_B_state +# assign ri_state = $NDset ( 0,1 ) +.names ri_state +0 +1 +.names _n22 +0 +.names ri_state _n22 _n23 +.def 0 +0 1 1 +1 0 1 +.names _n23 _n21 +0 1 +1 0 +.names _n21 _n20 +1 1 +0 0 +# state = 0 +.mv state$_n20_n25$true 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n20_n25$true +go_A_init +.names _n28 +1 +.names ri_state _n28 _n29 +.def 0 +0 1 1 +1 0 1 +.names _n29 _n27 +0 1 +1 0 +.names _n27 _n26 +1 1 +0 0 +# state = 2 +.mv state$_n26_n2b$true 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n26_n2b$true +go_B_init +# case (ri_state ) +.mv state$_n26$raw_n2e 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n26_n2b$true state$_n26_n2b$true _n26 state$_n26$raw_n2e +- - 0 =state$_n26_n2b$true +- - 1 =state$_n26_n2b$true +.mv state$_n20$raw_n2f 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n20_n25$true state$_n26$raw_n2e _n20 state$_n20$raw_n2f +- - 0 =state$_n26$raw_n2e +- - 1 =state$_n20_n25$true +# non-blocking assignments for initial +# assign signal = ((state == go_A_init ) || (state == go_B_init )) ? 0 : (state == go_A_state ) ? 1 : 2 +.mv signal$raw_n33 3 go_slow go_A go_B +.mv _n35 4 go_A_init go_A_state go_B_init go_B_state +.names _n35 +go_A_init +# state == 0 +.names state _n35 _n34 +.def 0 +- =state 1 +.mv _n37 4 go_A_init go_A_state go_B_init go_B_state +.names _n37 +go_B_init +# state == 2 +.names state _n37 _n36 +.def 0 +- =state 1 +# (state == 0) || (state == 2) +.names _n34 _n36 _n38 +.def 1 +0 0 0 +.mv _n3a 4 go_A_init go_A_state go_B_init go_B_state +.names _n3a +go_A_state +# state == 1 +.names state _n3a _n39 +.def 0 +- =state 1 +.mv _n3b 3 go_slow go_A go_B +.names _n3b +go_A +.mv _n3c 3 go_slow go_A go_B +.names _n3c +go_B +# (state == 1) ? 1 : 2 +.mv _n3d 3 go_slow go_A go_B +.names _n3b _n3c _n39 _n3d +- - 0 =_n3c +- - 1 =_n3b +.mv _n3e 3 go_slow go_A go_B +.names _n3e +go_slow +# ((state == 0) || (state == 2)) ? 0 : (state == 1) ? 1 : 2 +.mv _n3f 3 go_slow go_A go_B +.names _n3e _n3d _n38 _n3f +- - 0 =_n3d +- - 1 =_n3e +.names _n3f signal$raw_n33 +- =_n3f +# assign r_state = $NDset ( 0,1 ) +.names r_state +0 +1 +.mv _n44 4 go_A_init go_A_state go_B_init go_B_state +.names _n44 +go_A_init +.names state _n44 _n43 +.def 0 +- =state 1 +.names _n43 _n42 +1 1 +0 0 +.names _n47 +0 +.names r_state _n47 _n48 +.def 0 +0 1 1 +1 0 1 +.names _n48 _n46 +0 1 +1 0 +.names _n46 _n45 +1 1 +0 0 +# state = 0 +.mv state$_n45_n4a$true 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n45_n4a$true +go_A_init +.names _n4d +1 +.names r_state _n4d _n4e +.def 0 +0 1 1 +1 0 1 +.names _n4e _n4c +0 1 +1 0 +.names _n4c _n4b +1 1 +0 0 +# state = 1 +.mv state$_n4b_n50$true 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n4b_n50$true +go_A_state +# case (r_state ) +.mv state$_n4b$raw_n53 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n4b_n50$true state _n4b state$_n4b$raw_n53 +- - 0 =state +- - 1 =state$_n4b_n50$true +.mv state$_n45$raw_n54 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n45_n4a$true state$_n4b$raw_n53 _n45 state$_n45$raw_n54 +- - 0 =state$_n4b$raw_n53 +- - 1 =state$_n45_n4a$true +.mv _n5a 4 go_A_init go_A_state go_B_init go_B_state +.names _n5a +go_B_init +.names state _n5a _n59 +.def 0 +- =state 1 +.names _n59 _n58 +1 1 +0 0 +.names _n5d +0 +.names r_state _n5d _n5e +.def 0 +0 1 1 +1 0 1 +.names _n5e _n5c +0 1 +1 0 +.names _n5c _n5b +1 1 +0 0 +# state = 2 +.mv state$_n5b_n60$true 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n5b_n60$true +go_B_init +.names _n63 +1 +.names r_state _n63 _n64 +.def 0 +0 1 1 +1 0 1 +.names _n64 _n62 +0 1 +1 0 +.names _n62 _n61 +1 1 +0 0 +# state = 3 +.mv state$_n61_n66$true 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n61_n66$true +go_B_state +# case (r_state ) +.mv state$_n61$raw_n69 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n61_n66$true state _n61 state$_n61$raw_n69 +- - 0 =state +- - 1 =state$_n61_n66$true +.mv state$_n5b$raw_n6a 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n5b_n60$true state$_n61$raw_n69 _n5b state$_n5b$raw_n6a +- - 0 =state$_n61$raw_n69 +- - 1 =state$_n5b_n60$true +.mv _n6f 3 go_slow go_A go_B +.names _n6f +go_A +# signal == 1 +.names signal _n6f _n6e +.def 0 +- =signal 1 +.mv _n71 3 no_cars car_waiting cars_passing +.names _n71 +car_waiting +# status_B == 1 +.names status_B _n71 _n70 +.def 0 +- =status_B 1 +# (signal == 1) && (status_B == 1) +.names _n6e _n70 _n72 +.def 0 +1 1 1 +.names _n72 _n73 +- =_n72 +# state = 2 +.mv state$_n72_n74$true 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n72_n74$true +go_B_init +.mv _n76 3 go_slow go_A go_B +.names _n76 +go_B +# signal == 2 +.names signal _n76 _n75 +.def 0 +- =signal 1 +.mv _n78 3 no_cars car_waiting cars_passing +.names _n78 +car_waiting +# status_A == 1 +.names status_A _n78 _n77 +.def 0 +- =status_A 1 +# (signal == 2) && (status_A == 1) +.names _n75 _n77 _n79 +.def 0 +1 1 1 +.names _n79 _n7a +- =_n79 +# state = 0 +.mv state$_n79_n7b$true 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n79_n7b$true +go_A_init +# if/else ((signal == 2) && (status_A == 1)) +.mv state$_n79$raw_n7e 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n79_n7b$true state _n79 state$_n79$raw_n7e +- - 0 =state +- - 1 =state$_n79_n7b$true +# if/else ((signal == 1) && (status_B == 1)) +.mv state$_n72$raw_n80 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n72_n74$true state$_n79$raw_n7e _n72 state$_n72$raw_n80 +- - 0 =state$_n79$raw_n7e +- - 1 =state$_n72_n74$true +# case (state ) +.mv state$_n58$raw_n84 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n5b$raw_n6a state$_n72$raw_n80 _n58 state$_n58$raw_n84 +- - 0 =state$_n72$raw_n80 +- - 1 =state$_n5b$raw_n6a +.mv state$_n42$raw_n88 4 go_A_init go_A_state go_B_init go_B_state +.names state$_n45$raw_n54 state$_n58$raw_n84 _n42 state$_n42$raw_n88 +- - 0 =state$_n58$raw_n84 +- - 1 =state$_n45$raw_n54 +# conflict arbitrators +.names signal$raw_n33 signal +- =signal$raw_n33 +.names _n42 _n45 _n4b _n58 _n5b _n61 _n73 _n7a _n8b +.def 0 + 1 1 - - - - - - 1 + 1 0 1 - - - - - 1 + 0 - - 1 1 - - - 1 + 0 - - 1 0 1 - - 1 + 0 - - 0 - - 1 - 1 + 0 - - 0 - - 0 1 1 +.mv _n8c 4 go_A_init go_A_state go_B_init go_B_state +.names _n8b state$_n42$raw_n88 state _n8c +1 - - =state$_n42$raw_n88 +0 - - =state +# non-blocking assignments +# latches +.r state$_n20$raw_n2f state +- =state$_n20$raw_n2f +.latch _n8c state +# quasi-continuous assignment +.end + + +.model ROAD +# I/O ports +.outputs status +.inputs signal + +.mv status 3 no_cars car_waiting cars_passing +.mv signal 3 stop go slow +.mv state 4 STOPPED_init STOPPED GO_init GO +# state = 0 +.mv state$raw_n93 4 STOPPED_init STOPPED GO_init GO +.names state$raw_n93 +STOPPED_init +# non-blocking assignments for initial +# assign status = (state == STOPPED_init ) ? 0 : (state == STOPPED ) ? 1 : (state == GO_init ) ? 2 : (state == GO ) ? 0 : 0 +.mv status$raw_n94 3 no_cars car_waiting cars_passing +.mv _n96 4 STOPPED_init STOPPED GO_init GO +.names _n96 +STOPPED_init +# state == 0 +.names state _n96 _n95 +.def 0 +- =state 1 +.mv _n98 4 STOPPED_init STOPPED GO_init GO +.names _n98 +STOPPED +# state == 1 +.names state _n98 _n97 +.def 0 +- =state 1 +.mv _n9a 4 STOPPED_init STOPPED GO_init GO +.names _n9a +GO_init +# state == 2 +.names state _n9a _n99 +.def 0 +- =state 1 +.mv _n9c 4 STOPPED_init STOPPED GO_init GO +.names _n9c +GO +# state == 3 +.names state _n9c _n9b +.def 0 +- =state 1 +.mv _n9d 3 no_cars car_waiting cars_passing +.names _n9d +no_cars +.mv _n9e 3 no_cars car_waiting cars_passing +.names _n9e +no_cars +# (state == 3) ? 0 : 0 +.mv _n9f 3 no_cars car_waiting cars_passing +.names _n9d _n9e _n9b _n9f +- - 0 =_n9e +- - 1 =_n9d +.mv _na0 3 no_cars car_waiting cars_passing +.names _na0 +cars_passing +# (state == 2) ? 2 : (state == 3) ? 0 : 0 +.mv _na1 3 no_cars car_waiting cars_passing +.names _na0 _n9f _n99 _na1 +- - 0 =_n9f +- - 1 =_na0 +.mv _na2 3 no_cars car_waiting cars_passing +.names _na2 +car_waiting +# (state == 1) ? 1 : (state == 2) ? 2 : (state == 3) ? 0 : 0 +.mv _na3 3 no_cars car_waiting cars_passing +.names _na2 _na1 _n97 _na3 +- - 0 =_na1 +- - 1 =_na2 +.mv _na4 3 no_cars car_waiting cars_passing +.names _na4 +no_cars +# (state == 0) ? 0 : (state == 1) ? 1 : (state == 2) ? 2 : (state == 3) ? 0 : 0 +.mv _na5 3 no_cars car_waiting cars_passing +.names _na4 _na3 _n95 _na5 +- - 0 =_na3 +- - 1 =_na4 +.names _na5 status$raw_n94 +- =_na5 +# assign r_state = $NDset ( 0,1 ) +.names r_state +0 +1 +.mv _naa 4 STOPPED_init STOPPED GO_init GO +.names _naa +STOPPED_init +.names state _naa _na9 +.def 0 +- =state 1 +.names _na9 _na8 +1 1 +0 0 +.names _nad +0 +.names r_state _nad _nae +.def 0 +0 1 1 +1 0 1 +.names _nae _nac +0 1 +1 0 +.names _nac _nab +1 1 +0 0 +# state = 0 +.mv state$_nab_nb0$true 4 STOPPED_init STOPPED GO_init GO +.names state$_nab_nb0$true +STOPPED_init +.names _nb3 +1 +.names r_state _nb3 _nb4 +.def 0 +0 1 1 +1 0 1 +.names _nb4 _nb2 +0 1 +1 0 +.names _nb2 _nb1 +1 1 +0 0 +# state = 1 +.mv state$_nb1_nb6$true 4 STOPPED_init STOPPED GO_init GO +.names state$_nb1_nb6$true +STOPPED +# case (r_state ) +.mv state$_nb1$raw_nb9 4 STOPPED_init STOPPED GO_init GO +.names state$_nb1_nb6$true state _nb1 state$_nb1$raw_nb9 +- - 0 =state +- - 1 =state$_nb1_nb6$true +.mv state$_nab$raw_nba 4 STOPPED_init STOPPED GO_init GO +.names state$_nab_nb0$true state$_nb1$raw_nb9 _nab state$_nab$raw_nba +- - 0 =state$_nb1$raw_nb9 +- - 1 =state$_nab_nb0$true +.mv _nc0 4 STOPPED_init STOPPED GO_init GO +.names _nc0 +STOPPED +.names state _nc0 _nbf +.def 0 +- =state 1 +.names _nbf _nbe +1 1 +0 0 +.mv _nc2 3 stop go slow +.names _nc2 +go +# signal == 1 +.names signal _nc2 _nc1 +.def 0 +- =signal 1 +.names _nc1 _nc3 +- =_nc1 +# state = 2 +.mv state$_nc1_nc4$true 4 STOPPED_init STOPPED GO_init GO +.names state$_nc1_nc4$true +GO_init +# if/else (signal == 1) +.mv state$_nc1$raw_nc7 4 STOPPED_init STOPPED GO_init GO +.names state$_nc1_nc4$true state _nc1 state$_nc1$raw_nc7 +- - 0 =state +- - 1 =state$_nc1_nc4$true +.mv _nca 4 STOPPED_init STOPPED GO_init GO +.names _nca +GO_init +.names state _nca _nc9 +.def 0 +- =state 1 +.names _nc9 _nc8 +1 1 +0 0 +.mv _ncc 3 stop go slow +.names _ncc +stop +# signal == 0 +.names signal _ncc _ncb +.def 0 +- =signal 1 +.names _ncb _ncd +- =_ncb +# state = 0 +.mv state$_ncb_nce$true 4 STOPPED_init STOPPED GO_init GO +.names state$_ncb_nce$true +STOPPED_init +.names _nd1 +0 +.names r_state _nd1 _nd2 +.def 0 +0 1 1 +1 0 1 +.names _nd2 _nd0 +0 1 +1 0 +.names _nd0 _ncf +1 1 +0 0 +# state = 2 +.mv state$_ncf_nd4$true 4 STOPPED_init STOPPED GO_init GO +.names state$_ncf_nd4$true +GO_init +.names _nd7 +1 +.names r_state _nd7 _nd8 +.def 0 +0 1 1 +1 0 1 +.names _nd8 _nd6 +0 1 +1 0 +.names _nd6 _nd5 +1 1 +0 0 +# state = 3 +.mv state$_nd5_nda$true 4 STOPPED_init STOPPED GO_init GO +.names state$_nd5_nda$true +GO +# case (r_state ) +.mv state$_nd5$raw_ndd 4 STOPPED_init STOPPED GO_init GO +.names state$_nd5_nda$true state _nd5 state$_nd5$raw_ndd +- - 0 =state +- - 1 =state$_nd5_nda$true +.mv state$_ncf$raw_nde 4 STOPPED_init STOPPED GO_init GO +.names state$_ncf_nd4$true state$_nd5$raw_ndd _ncf state$_ncf$raw_nde +- - 0 =state$_nd5$raw_ndd +- - 1 =state$_ncf_nd4$true +# if/else (signal == 0) +.mv state$_ncb$raw_ne3 4 STOPPED_init STOPPED GO_init GO +.names state$_ncb_nce$true state$_ncf$raw_nde _ncb state$_ncb$raw_ne3 +- - 0 =state$_ncf$raw_nde +- - 1 =state$_ncb_nce$true +.mv _ne8 4 STOPPED_init STOPPED GO_init GO +.names _ne8 +GO +.names state _ne8 _ne7 +.def 0 +- =state 1 +.names _ne7 _ne6 +1 1 +0 0 +# state = 0 +.mv state$_ne6_ne9$true 4 STOPPED_init STOPPED GO_init GO +.names state$_ne6_ne9$true +STOPPED_init +# case (state ) +.mv state$_ne6$raw_nec 4 STOPPED_init STOPPED GO_init GO +.names state$_ne6_ne9$true state _ne6 state$_ne6$raw_nec +- - 0 =state +- - 1 =state$_ne6_ne9$true +.mv state$_nc8$raw_nee 4 STOPPED_init STOPPED GO_init GO +.names state$_ncb$raw_ne3 state$_ne6$raw_nec _nc8 state$_nc8$raw_nee +- - 0 =state$_ne6$raw_nec +- - 1 =state$_ncb$raw_ne3 +.mv state$_nbe$raw_nf2 4 STOPPED_init STOPPED GO_init GO +.names state$_nc1$raw_nc7 state$_nc8$raw_nee _nbe state$_nbe$raw_nf2 +- - 0 =state$_nc8$raw_nee +- - 1 =state$_nc1$raw_nc7 +.mv state$_na8$raw_nf6 4 STOPPED_init STOPPED GO_init GO +.names state$_nab$raw_nba state$_nbe$raw_nf2 _na8 state$_na8$raw_nf6 +- - 0 =state$_nbe$raw_nf2 +- - 1 =state$_nab$raw_nba +# conflict arbitrators +.names status$raw_n94 status +- =status$raw_n94 +.names _na8 _nab _nb1 _nbe _nc3 _nc8 _ncd _ncf _nd5 _ne6 _nf9 +.def 0 + 1 1 - - - - - - - - 1 + 1 0 1 - - - - - - - 1 + 0 - - 1 1 - - - - - 1 + 0 - - 0 - 1 1 - - - 1 + 0 - - 0 - 1 0 1 - - 1 + 0 - - 0 - 1 0 0 1 - 1 + 0 - - 0 - 0 - - - 1 1 +.mv _nfa 4 STOPPED_init STOPPED GO_init GO +.names _nf9 state$_na8$raw_nf6 state _nfa +1 - - =state$_na8$raw_nf6 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n93 state +- =state$raw_n93 +.latch _nfa state +# quasi-continuous assignment +.end + + +.model collision +# I/O ports +.inputs status_B +.inputs status_A + +.mv status_B 3 no_cars car_waiting cars_passing +.mv status_A 3 no_cars car_waiting cars_passing +.mv state 2 GOOD BAD +# state = 0 +.mv state$raw_n100 2 GOOD BAD +.names state$raw_n100 +GOOD +# non-blocking assignments for initial +.mv _n103 2 GOOD BAD +.names _n103 +GOOD +.names state _n103 _n102 +.def 0 +- =state 1 +.names _n102 _n101 +1 1 +0 0 +.mv _n105 3 no_cars car_waiting cars_passing +.names _n105 +cars_passing +# status_A == 2 +.names status_A _n105 _n104 +.def 0 +- =status_A 1 +.mv _n107 3 no_cars car_waiting cars_passing +.names _n107 +cars_passing +# status_B == 2 +.names status_B _n107 _n106 +.def 0 +- =status_B 1 +# (status_A == 2) && (status_B == 2) +.names _n104 _n106 _n108 +.def 0 +1 1 1 +.names _n108 _n109 +- =_n108 +# state = 1 +.mv state$_n108_n10a$true 2 GOOD BAD +.names state$_n108_n10a$true +BAD +# if/else ((status_A == 2) && (status_B == 2)) +.mv state$_n108$raw_n10d 2 GOOD BAD +.names state$_n108_n10a$true state _n108 state$_n108$raw_n10d +- - 0 =state +- - 1 =state$_n108_n10a$true +# case (state ) +.mv state$_n101$raw_n110 2 GOOD BAD +.names state$_n108$raw_n10d state _n101 state$_n101$raw_n110 +- - 0 =state +- - 1 =state$_n108$raw_n10d +# conflict arbitrators +.names _n101 _n109 _n111 +.def 0 + 1 1 1 +.mv _n112 2 GOOD BAD +.names _n111 state$_n101$raw_n110 state _n112 +1 - - =state$_n101$raw_n110 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n100 state +- =state$raw_n100 +.latch _n112 state +# quasi-continuous assignment +.end + + +.model starvation +# I/O ports +.inputs stat + +.mv state 2 OK NOT_OK +.mv stat 3 no_cars car_waiting cars_passing +# state = 0 +.mv state$raw_n114 2 OK NOT_OK +.names state$raw_n114 +OK +# non-blocking assignments for initial +.mv _n117 2 OK NOT_OK +.names _n117 +OK +.names state _n117 _n116 +.def 0 +- =state 1 +.names _n116 _n115 +1 1 +0 0 +.mv _n119 3 no_cars car_waiting cars_passing +.names _n119 +car_waiting +# stat == 1 +.names stat _n119 _n118 +.def 0 +- =stat 1 +.names _n118 _n11a +- =_n118 +# state = 1 +.mv state$_n118_n11b$true 2 OK NOT_OK +.names state$_n118_n11b$true +NOT_OK +# if/else (stat == 1) +.mv state$_n118$raw_n11e 2 OK NOT_OK +.names state$_n118_n11b$true state _n118 state$_n118$raw_n11e +- - 0 =state +- - 1 =state$_n118_n11b$true +.mv _n121 2 OK NOT_OK +.names _n121 +NOT_OK +.names state _n121 _n120 +.def 0 +- =state 1 +.names _n120 _n11f +1 1 +0 0 +.mv _n123 3 no_cars car_waiting cars_passing +.names _n123 +cars_passing +# stat == 2 +.names stat _n123 _n122 +.def 0 +- =stat 1 +.names _n122 _n124 +- =_n122 +# state = 0 +.mv state$_n122_n125$true 2 OK NOT_OK +.names state$_n122_n125$true +OK +# if/else (stat == 2) +.mv state$_n122$raw_n128 2 OK NOT_OK +.names state$_n122_n125$true state _n122 state$_n122$raw_n128 +- - 0 =state +- - 1 =state$_n122_n125$true +# case (state ) +.mv state$_n11f$raw_n12b 2 OK NOT_OK +.names state$_n122$raw_n128 state _n11f state$_n11f$raw_n12b +- - 0 =state +- - 1 =state$_n122$raw_n128 +.mv state$_n115$raw_n12d 2 OK NOT_OK +.names state$_n118$raw_n11e state$_n11f$raw_n12b _n115 state$_n115$raw_n12d +- - 0 =state$_n11f$raw_n12b +- - 1 =state$_n118$raw_n11e +# conflict arbitrators +.names _n115 _n11a _n11f _n124 _n130 +.def 0 + 1 1 - - 1 + 0 - 1 1 1 +.mv _n131 2 OK NOT_OK +.names _n130 state$_n115$raw_n12d state _n131 +1 - - =state$_n115$raw_n12d +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n114 state +- =state$raw_n114 +.latch _n131 state +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/crd/crd.v =================================================================== --- vis_dev/vis-2.1/examples/crd/crd.v (revision 11) +++ vis_dev/vis-2.1/examples/crd/crd.v (revision 11) @@ -0,0 +1,187 @@ +// The crossroads +// Originally written by R. P. Kurshan +// Translated by Rajeev K. Ranjan + +typedef enum {no_cars, car_waiting, cars_passing} traffic_status; +typedef enum {stop, go, slow} traffic_signal; +typedef enum {go_slow, go_A, go_B} police_signal; +typedef enum {STOPPED_init, STOPPED, GO_init, GO} car_status; +typedef enum {go_A_init, go_A_state, go_B_init, go_B_state} police_state; + + +module environment(clk, status_A, test); +input clk; +output status_A; +output test; + +traffic_signal wire signal_A, signal_B; +traffic_status wire status_A, status_B; +police_signal wire signal; +wire test; + +POLICEMAN police (clk, status_A, status_B, signal); + +assign signal_A = (signal == go_A) ? go : (signal == go_slow) ? slow : stop; +assign signal_B = (signal == go_B) ? go : (signal == go_slow) ? slow : stop; + + +ROAD road_A (clk, signal_A, status_A); +ROAD road_B (clk, signal_B, status_B); +assign test = ((status_A == cars_passing) && (status_B == cars_passing)) ? 0 :1; + +collision col(clk, status_A, status_B); +starvation starv(clk,status_A); + +endmodule + + +module POLICEMAN(clk, status_A, status_B, signal); +input clk; +input status_A, status_B; +output signal; +traffic_status wire status_A, status_B; +police_signal wire signal; +police_state reg state; +wire r_state, ri_state; + +assign ri_state = $ND(0,1); + initial + begin + case(ri_state) + 0:state = go_A_init; + 1:state = go_B_init; + endcase + end + + assign signal = ((state == go_A_init) || (state == go_B_init)) ? go_slow : + (state == go_A_state) ? go_A : go_B; + assign r_state = $ND(0,1); + always @(posedge clk) begin + case(state) + go_A_init: begin + case(r_state) + 0:state = go_A_init; + 1:state = go_A_state; + endcase + end + go_B_init: begin + case(r_state) + 0:state = go_B_init; + 1:state = go_B_state; + endcase + end + // go_A_state: + // if (status_B == car_waiting) + // state = go_B_init; + // go_B_state: + // if (status_A == car_waiting) + // state = go_A_init; + + default: + begin + if ((signal == go_A) && (status_B == car_waiting)) + state = go_B_init; + else + if ((signal == go_B) && (status_A == car_waiting)) + state = go_A_init; + end + endcase + end +endmodule + + +module ROAD(clk, signal, status); +input clk; +input signal; +output status; +traffic_signal wire signal; +traffic_status wire status; +car_status reg state; +wire r_state; + + initial state = STOPPED_init; + + assign status = (state == STOPPED_init) ? no_cars: + (state == STOPPED) ? car_waiting : + (state == GO_init) ? cars_passing: + (state == GO) ? no_cars: no_cars; + assign r_state = $ND(0,1); + + always @(posedge clk) begin + case(state) + STOPPED_init: + begin + case(r_state) + 0:state = STOPPED_init; + 1:state = STOPPED; + endcase + end + + STOPPED: + begin + if (signal == go) + state = GO_init; + end + GO_init: + begin + if (signal == stop) + state = STOPPED_init; + else + begin + case(r_state) + 0:state = GO_init; + 1:state = GO; + endcase + end + end + GO: + state = STOPPED_init; + default: ; + endcase + end +endmodule + +typedef enum {GOOD, BAD} status; + +module collision(clk, status_A, status_B); +input clk, status_A, status_B; +traffic_status wire status_A, status_B; +status reg state; + + initial state = GOOD; + always @(posedge clk) begin + case(state) + GOOD: + if ((status_A == cars_passing) && (status_B == cars_passing)) + state = BAD; + endcase + end +endmodule + + +typedef enum {OK, NOT_OK} prop1_status; + +module starvation(clk, stat); +input clk, stat; +traffic_status wire stat; +prop1_status reg state; + +initial state = OK; +always @(posedge clk) begin + case(state) + OK: + begin + if (stat == car_waiting) + state = NOT_OK; + end + NOT_OK: + begin + if (stat == cars_passing) + state = OK; + end + default:; + + endcase +end +endmodule + Index: vis_dev/vis-2.1/examples/crd/safety.ctl =================================================================== --- vis_dev/vis-2.1/examples/crd/safety.ctl (revision 11) +++ vis_dev/vis-2.1/examples/crd/safety.ctl (revision 11) @@ -0,0 +1,1 @@ +AG(!(status_A=cars_passing) + ! (status_B=cars_passing)); Index: vis_dev/vis-2.1/examples/crd/safety.fair =================================================================== --- vis_dev/vis-2.1/examples/crd/safety.fair (revision 11) +++ vis_dev/vis-2.1/examples/crd/safety.fair (revision 11) @@ -0,0 +1,19 @@ + +#.include crd.fairness +!(police.state=go_A_init); +!(police.state=go_B_init); +!(road_A.state=STOPPED_init); +!(road_B.state=STOPPED_init); + + +#.properties +#.automaton /usr/lib/blah/blah +#.blifmv safety.mv +#.connections(status_A=status_A, status_B=status_B) +#.state st1 = state:GOOD +#.posfair +#.subsets {st1} +#.endfair +#.endautomaton +#.endproperties +!(col.state=GOOD); Index: vis_dev/vis-2.1/examples/crd/starvation.ctl =================================================================== --- vis_dev/vis-2.1/examples/crd/starvation.ctl (revision 11) +++ vis_dev/vis-2.1/examples/crd/starvation.ctl (revision 11) @@ -0,0 +1,1 @@ +AG((status_A=car_waiting) -> AF (status_A=cars_passing)); Index: vis_dev/vis-2.1/examples/crd/starvation2.ctl =================================================================== --- vis_dev/vis-2.1/examples/crd/starvation2.ctl (revision 11) +++ vis_dev/vis-2.1/examples/crd/starvation2.ctl (revision 11) @@ -0,0 +1,1 @@ +AG((starv.state = NOT_OK) -> AF (starv.state =OK)); Index: vis_dev/vis-2.1/examples/ctlp3/README =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/README (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/README (revision 11) @@ -0,0 +1,12 @@ +There are two versions of the 3 philosopher here. The one +ctlp3 is the same as in hsis (except for conversion to +deterministic tables) + +The second is a modification which used symbolic variables. + +Both can be run with the script +rlmv ctlp3x.v +init +mc ctlp3x.ctl // this fails +rf ctlp3x.fair +mc ctlp3x.ctl // this passes Index: vis_dev/vis-2.1/examples/ctlp3/affalse =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/affalse (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/affalse (revision 11) @@ -0,0 +1,1 @@ +AF FALSE; Index: vis_dev/vis-2.1/examples/ctlp3/agtrue =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/agtrue (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/agtrue (revision 11) @@ -0,0 +1,1 @@ +AG TRUE; Index: vis_dev/vis-2.1/examples/ctlp3/check_result =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/check_result (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/check_result (revision 11) @@ -0,0 +1,11 @@ +# MC: formula failed --- AF(FALSE) +# LE: language is not empty +# MC: formula passed --- AG(TRUE) +# MC: formula failed --- AG((ph0.state=HUNGRY -> AF(ph0.state=EATING))) +# INV: formula passed --- (((((ph0.state=READING + ph1.state=READING) + ph2.state=READING) * !((ph0.state=READING * ph1.state=READING))) * !((ph1.state=READING * ph2.state=READING))) * !((ph0.state=READING * ph2.state=READING))) +# LE: language is not empty +# MC: formula passed --- AG((ph0.state=HUNGRY -> AF(ph0.state=EATING))) +# LTL_MC: formula passed +# INV: formula passed --- (((((ph0.state=READING + ph1.state=READING) + ph2.state=READING) * !((ph0.state=READING * ph1.state=READING))) * !((ph1.state=READING * ph2.state=READING))) * !((ph0.state=READING * ph2.state=READING))) +# INV: formula passed --- (((((ph0.state=READING + ph1.state=READING) + ph2.state=READING) * !((ph0.state=READING * ph1.state=READING))) * !((ph1.state=READING * ph2.state=READING))) * !((ph0.state=READING * ph2.state=READING))) +# LE: language is not empty Index: vis_dev/vis-2.1/examples/ctlp3/check_script =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/check_script (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/check_script (revision 11) @@ -0,0 +1,19 @@ +read_blif_mv ctlp3.mv +init_verify +model_check -d 0 affalse +print_fairness +lang_empty -d 0 +model_check -d 0 agtrue +model_check -d 0 ctlp3.ctl +check_invariant ctlp3.inv +read_fairness ctlp3.fair +print_fairness +lang_empty -d 0 +model_check -d 0 ctlp3.ctl +ltl_model_check -d 0 ctlp3.ltl +build_partition_maigs +check_invariant -A 4 -v 1 ctlp3.inv +check_invariant -A 3 -v 1 ctlp3.inv +lang_empty -d 0 -A 1 +time +quit -s Index: vis_dev/vis-2.1/examples/ctlp3/ctlp3.ctl =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/ctlp3.ctl (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/ctlp3.ctl (revision 11) @@ -0,0 +1,1 @@ +AG( (ph0.state=HUNGRY)-> AF(ph0.state=EATING)); Index: vis_dev/vis-2.1/examples/ctlp3/ctlp3.fair =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/ctlp3.fair (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/ctlp3.fair (revision 11) @@ -0,0 +1,6 @@ +!(ph0.state=EATING); +!(ph1.state=EATING); +!(ph2.state=EATING); +!(str.state=0); +!(str.state=1); + Index: vis_dev/vis-2.1/examples/ctlp3/ctlp3.inv =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/ctlp3.inv (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/ctlp3.inv (revision 11) @@ -0,0 +1,4 @@ +((ph0.state=READING)+ (ph1.state=READING)+ (ph2.state=READING)) +* (!((ph0.state=READING)* (ph1.state=READING))) +* (!((ph1.state=READING)* (ph2.state=READING))) +* (!((ph0.state=READING)* (ph2.state=READING))); Index: vis_dev/vis-2.1/examples/ctlp3/ctlp3.ltl =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/ctlp3.ltl (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/ctlp3.ltl (revision 11) @@ -0,0 +1,1 @@ +G( (ph0.state=HUNGRY)-> F(ph0.state=EATING)); Index: vis_dev/vis-2.1/examples/ctlp3/ctlp3.mv =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/ctlp3.mv (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/ctlp3.mv (revision 11) @@ -0,0 +1,320 @@ +# vl2mv ctlp3.v +# version: 0.2 +# date: 11:13:08 12/11/95 (PST) +.model diners +# I/O ports + +.mv s0 4 THINKING HUNGRY EATING READING +.mv s1 4 THINKING HUNGRY EATING READING +.mv s2 4 THINKING HUNGRY EATING READING +.mv _n0 4 THINKING HUNGRY EATING READING +.names _n0 +EATING +.subckt philosopher ph0 out=s0 left=s1 right=s2 init=_n0 +.mv _n1 4 THINKING HUNGRY EATING READING +.names _n1 +READING +.subckt philosopher ph1 out=s1 left=s2 right=s0 init=_n1 +.mv _n2 4 THINKING HUNGRY EATING READING +.names _n2 +HUNGRY +.subckt philosopher ph2 out=s2 left=s0 right=s1 init=_n2 +.subckt starvation str starv=s0 +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model philosopher +# I/O ports +.inputs left +.outputs out +.inputs init +.inputs right + +.mv left 4 THINKING HUNGRY EATING READING +.mv out 4 THINKING HUNGRY EATING READING +.mv r0_state 4 THINKING HUNGRY EATING READING +.mv r1_state 4 THINKING HUNGRY EATING READING +.mv state 4 THINKING HUNGRY EATING READING +.mv init 4 THINKING HUNGRY EATING READING +.mv right 4 THINKING HUNGRY EATING READING +# state = init +.mv state$raw_n3 4 THINKING HUNGRY EATING READING +.names init state$raw_n3 +- =init +# non-blocking assignments for initial +# assign r0_state = $NDset ( 0,1 ) +.names r0_state +THINKING +HUNGRY +# assign r1_state = $NDset ( 0,2 ) +.names r1_state +THINKING +EATING +# assign out = state +.mv out$raw_n8 4 THINKING HUNGRY EATING READING +.names state out$raw_n8 +- =state +.mv _nb 4 THINKING HUNGRY EATING READING +.names _nb +READING +.names state _nb _na +.def 0 +- =state 1 +.names _na _n9 +1 1 +0 0 +.mv _nd 4 THINKING HUNGRY EATING READING +.names _nd +THINKING +# left == 0 +.names left _nd _nc +.def 0 +- =left 1 +.names _nc _ne +- =_nc +# state = 0 +.mv state$_nc_nf$true 4 THINKING HUNGRY EATING READING +.names state$_nc_nf$true +THINKING +# if/else (left == 0) +.mv state$_nc$raw_n12 4 THINKING HUNGRY EATING READING +.names state$_nc_nf$true state _nc state$_nc$raw_n12 +- - 0 =state +- - 1 =state$_nc_nf$true +.mv _n15 4 THINKING HUNGRY EATING READING +.names _n15 +THINKING +.names state _n15 _n14 +.def 0 +- =state 1 +.names _n14 _n13 +1 1 +0 0 +.mv _n17 4 THINKING HUNGRY EATING READING +.names _n17 +READING +# right == 3 +.names right _n17 _n16 +.def 0 +- =right 1 +.names _n16 _n18 +- =_n16 +# state = 3 +.mv state$_n16_n19$true 4 THINKING HUNGRY EATING READING +.names state$_n16_n19$true +READING +# state = r0_state +.mv state$_n16_n1a$false 4 THINKING HUNGRY EATING READING +.names r0_state state$_n16_n1a$false +- =r0_state +# if/else (right == 3) +.mv state$_n16$raw_n1c 4 THINKING HUNGRY EATING READING +.names state$_n16_n19$true state$_n16_n1a$false _n16 state$_n16$raw_n1c +- - 0 =state$_n16_n1a$false +- - 1 =state$_n16_n19$true +.mv _n21 4 THINKING HUNGRY EATING READING +.names _n21 +EATING +.names state _n21 _n20 +.def 0 +- =state 1 +.names _n20 _n1f +1 1 +0 0 +# state = r1_state +.mv state$_n1f_n22$true 4 THINKING HUNGRY EATING READING +.names r1_state state$_n1f_n22$true +- =r1_state +.mv _n25 4 THINKING HUNGRY EATING READING +.names _n25 +HUNGRY +.names state _n25 _n24 +.def 0 +- =state 1 +.names _n24 _n23 +1 1 +0 0 +.mv _n27 4 THINKING HUNGRY EATING READING +.names _n27 +EATING +# left != 2 +.names left _n27 _n26 +.def 1 +- =left 0 +.mv _n29 4 THINKING HUNGRY EATING READING +.names _n29 +HUNGRY +# right != 1 +.names right _n29 _n28 +.def 1 +- =right 0 +# left != 2 && right != 1 +.names _n26 _n28 _n2a +.def 0 +1 1 1 +.mv _n2c 4 THINKING HUNGRY EATING READING +.names _n2c +EATING +# right != 2 +.names right _n2c _n2b +.def 1 +- =right 0 +# left != 2 && right != 1 && right != 2 +.names _n2a _n2b _n2d +.def 0 +1 1 1 +.names _n2d _n2e +- =_n2d +# state = 2 +.mv state$_n2d_n2f$true 4 THINKING HUNGRY EATING READING +.names state$_n2d_n2f$true +EATING +# if/else (left != 2 && right != 1 && right != 2) +.mv state$_n2d$raw_n32 4 THINKING HUNGRY EATING READING +.names state$_n2d_n2f$true state _n2d state$_n2d$raw_n32 +- - 0 =state +- - 1 =state$_n2d_n2f$true +# case (state ) +.mv state$_n23$raw_n35 4 THINKING HUNGRY EATING READING +.names state$_n2d$raw_n32 state _n23 state$_n23$raw_n35 +- - 0 =state +- - 1 =state$_n2d$raw_n32 +.mv state$_n1f$raw_n36 4 THINKING HUNGRY EATING READING +.names state$_n1f_n22$true state$_n23$raw_n35 _n1f state$_n1f$raw_n36 +- - 0 =state$_n23$raw_n35 +- - 1 =state$_n1f_n22$true +.mv state$_n13$raw_n3a 4 THINKING HUNGRY EATING READING +.names state$_n16$raw_n1c state$_n1f$raw_n36 _n13 state$_n13$raw_n3a +- - 0 =state$_n1f$raw_n36 +- - 1 =state$_n16$raw_n1c +.mv state$_n9$raw_n3e 4 THINKING HUNGRY EATING READING +.names state$_nc$raw_n12 state$_n13$raw_n3a _n9 state$_n9$raw_n3e +- - 0 =state$_n13$raw_n3a +- - 1 =state$_nc$raw_n12 +# conflict arbitrators +.names out$raw_n8 out +- =out$raw_n8 +.names _n9 _ne _n13 _n18 _n1f _n23 _n2e _n42 +.def 0 + 1 1 - - - - - 1 + 0 - 1 1 - - - 1 + 0 - 1 0 - - - 1 + 0 - 0 - 1 - - 1 + 0 - 0 - 0 1 1 1 +.mv _n43 4 THINKING HUNGRY EATING READING +.names _n42 state$_n9$raw_n3e state _n43 +1 - - =state$_n9$raw_n3e +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n3 state +- =state$raw_n3 +.latch _n43 state +# quasi-continuous assignment +.end + + +.model starvation +# I/O ports +.inputs starv + +.mv starv 4 THINKING HUNGRY EATING READING +# state = 0 +.names state$raw_n49 +0 +# non-blocking assignments for initial +.names _n4c +0 +.names state _n4c _n4d +.def 0 +0 1 1 +1 0 1 +.names _n4d _n4b +0 1 +1 0 +.names _n4b _n4a +1 1 +0 0 +.mv _n50 4 THINKING HUNGRY EATING READING +.names _n50 +HUNGRY +# starv == 1 +.names starv _n50 _n4f +.def 0 +- =starv 1 +.names _n4f _n51 +- =_n4f +# state = 1 +.names state$_n4f_n52$true +1 +# if/else (starv == 1) +.names state$_n4f_n52$true state _n4f state$_n4f$raw_n55 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n59 +1 +.names state _n59 _n5a +.def 0 +0 1 1 +1 0 1 +.names _n5a _n58 +0 1 +1 0 +.names _n58 _n57 +1 1 +0 0 +.mv _n5d 4 THINKING HUNGRY EATING READING +.names _n5d +THINKING +# starv == 0 +.names starv _n5d _n5c +.def 0 +- =starv 1 +.names _n5c _n5e +- =_n5c +# state = 0 +.names state$_n5c_n5f$true +0 +# if/else (starv == 0) +.names state$_n5c_n5f$true state _n5c state$_n5c$raw_n62 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# case (state ) +.names state$_n5c$raw_n62 state _n57 state$_n57$raw_n66 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state$_n4f$raw_n55 state$_n57$raw_n66 _n4a state$_n4a$raw_n68 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names _n4a _n51 _n57 _n5e _n6d +.def 0 + 1 1 - - 1 + 0 - 1 1 1 +.names _n6d state$_n4a$raw_n68 state _n6e +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +# non-blocking assignments +# latches +.r state$raw_n49 state +0 0 +1 1 +.latch _n6e state +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/ctlp3/ctlp3.partial =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/ctlp3.partial (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/ctlp3.partial (revision 11) @@ -0,0 +1,2 @@ +1 +ph0.state ph1.state Index: vis_dev/vis-2.1/examples/ctlp3/ctlp3.v =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/ctlp3.v (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/ctlp3.v (revision 11) @@ -0,0 +1,76 @@ +/* Dining philosophers of E. W. Dijkstra + based on S/R implementation by R. Kurshan + Ramin Hojati, May 1993 + +*/ +typedef enum {THINKING, HUNGRY, EATING, READING} t_state; + +/************************************************************************/ +module diners(clk); +input clk; + +t_state wire s0, s1, s2; + +philosopher ph0(clk, s0, s1, s2, EATING); +philosopher ph1(clk, s1, s2, s0, READING); +philosopher ph2(clk, s2, s0, s1, HUNGRY); + +starvation str(clk, s0); + +endmodule + +/************************************************************************/ +module philosopher(clk, out, left, right, init); +input clk; +input left, right, init; +output out; +t_state wire left, right, init, out; +t_state reg state; +t_state wire r0_state,r1_state; + + +initial state = init; + +assign r0_state = $ND(THINKING,HUNGRY); +assign r1_state = $ND(THINKING,EATING); +assign out = state; + +always @(posedge clk) begin + case(state) + READING: + if (left == THINKING) state = THINKING; + + THINKING: + begin + if ( right == READING ) state = READING; + else state = r0_state; + end + + EATING: + state = r1_state; + + HUNGRY: + if ( left != EATING && right != HUNGRY && right != EATING) + state = EATING; + endcase +end +endmodule + +/************************************************************************/ +module starvation( clk, starv ); + input clk; + input starv; + t_state wire starv; + reg state; + +initial state = 0; + +always @(posedge clk) begin + case(state) + 0: if ( starv == HUNGRY ) state = 1; + + 1: if ( starv == THINKING ) state = 0; + + endcase +end +endmodule Index: vis_dev/vis-2.1/examples/ctlp3/symmetry.final =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/symmetry.final (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/symmetry.final (revision 11) @@ -0,0 +1,1 @@ +0 Index: vis_dev/vis-2.1/examples/ctlp3/symmetry.graph =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/symmetry.graph (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/symmetry.graph (revision 11) @@ -0,0 +1,697 @@ +314 382 +123 0 +5 123 +124 1 +8 124 +125 2 +11 125 +126 3 +74 126 +127 4 +77 127 +128 5 +80 128 +129 6 +73 129 +130 7 +76 130 +131 8 +79 131 +132 9 +75 132 +133 10 +78 133 +134 11 +81 134 +135 12 +80 135 +136 13 +2 136 +137 14 +79 137 +138 15 +0 138 +139 16 +81 139 +140 17 +1 140 +141 18 +116 141 +142 18 +20 142 +143 18 +46 143 +144 19 +108 144 +145 19 +18 145 +146 19 +45 146 +147 20 +4 147 +148 20 +21 148 +149 20 +39 149 +150 21 +71 150 +151 21 +80 151 +152 21 +43 152 +153 22 +115 153 +154 22 +24 154 +155 22 +44 155 +156 23 +110 156 +157 23 +22 157 +158 23 +42 158 +159 24 +7 159 +160 24 +25 160 +161 24 +40 161 +162 25 +70 162 +163 25 +79 163 +164 25 +41 164 +165 26 +114 165 +166 26 +28 166 +167 26 +50 167 +168 27 +109 168 +169 27 +26 169 +170 27 +49 170 +171 28 +10 171 +172 28 +29 172 +173 28 +47 173 +174 29 +72 174 +175 29 +81 175 +176 29 +48 176 +177 30 +1 177 +178 31 +2 178 +179 32 +0 179 +180 33 +2 180 +181 34 +0 181 +182 35 +1 182 +183 37 +106 183 +184 38 +107 184 +185 39 +112 185 +186 40 +113 186 +187 41 +65 187 +188 42 +14 188 +189 43 +67 189 +190 44 +55 190 +191 45 +12 191 +192 46 +52 192 +193 47 +111 193 +194 48 +69 194 +195 49 +16 195 +196 50 +58 196 +197 51 +0 197 +198 52 +80 198 +199 53 +2 199 +200 54 +102 200 +201 55 +79 201 +202 56 +0 202 +203 57 +1 203 +204 58 +81 204 +205 59 +31 205 +206 59 +84 206 +207 60 +61 207 +208 60 +33 208 +209 61 +30 209 +210 61 +85 210 +211 62 +59 211 +212 62 +32 212 +213 63 +34 213 +214 63 +86 214 +215 64 +63 215 +216 64 +35 216 +217 65 +79 217 +218 66 +0 218 +219 67 +80 219 +220 68 +102 220 +221 69 +81 221 +222 70 +79 222 +223 70 +62 223 +224 71 +80 224 +225 71 +60 225 +226 72 +81 226 +227 72 +64 227 +228 79 +117 228 +229 79 +101 229 +230 80 +118 230 +231 80 +36 231 +232 81 +119 232 +233 81 +122 233 +234 83 +102 234 +235 83 +51 235 +236 84 +0 236 +237 85 +2 237 +238 86 +1 238 +239 87 +83 239 +240 87 +102 240 +241 87 +37 241 +242 88 +120 242 +243 88 +87 243 +244 88 +38 244 +245 89 +38 245 +246 89 +91 246 +247 89 +37 247 +248 89 +92 248 +249 90 +15 249 +250 91 +66 250 +251 92 +51 251 +252 93 +53 252 +253 94 +56 253 +254 95 +13 254 +255 96 +17 255 +256 97 +57 256 +257 98 +62 257 +258 99 +64 258 +259 100 +60 259 +260 102 +121 260 +261 102 +82 261 +262 103 +42 262 +263 103 +93 263 +264 103 +44 264 +265 103 +90 265 +266 103 +40 266 +267 103 +41 267 +268 103 +98 268 +269 104 +49 269 +270 104 +94 270 +271 104 +50 271 +272 104 +96 272 +273 104 +47 273 +274 104 +48 274 +275 104 +99 275 +276 105 +45 276 +277 105 +97 277 +278 105 +46 278 +279 105 +95 279 +280 105 +39 280 +281 105 +43 281 +282 105 +100 282 +283 106 +54 283 +284 107 +68 284 +285 108 +80 285 +286 108 +57 286 +287 109 +81 287 +288 109 +56 288 +289 110 +79 289 +290 110 +53 290 +291 111 +81 291 +292 112 +80 292 +293 113 +79 293 +294 114 +9 294 +295 114 +17 295 +296 115 +6 296 +297 115 +15 297 +298 116 +3 298 +299 116 +13 299 +300 117 +103 300 +301 117 +23 301 +302 117 +79 302 +303 118 +105 303 +304 118 +19 304 +305 118 +80 305 +306 119 +104 306 +307 119 +27 307 +308 119 +81 308 +309 120 +102 309 +310 120 +66 310 +311 121 +89 311 +312 121 +88 312 +313 121 +102 313 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +2 +2 +2 +2 +2 +2 +4 +4 +4 +4 +4 +4 +4 +4 +4 +4 +4 +4 +8 +8 +8 +8 +8 +8 +10 +11 +11 +11 +11 +11 +11 +11 +11 +11 +11 +11 +11 +11 +11 +13 +13 +13 +13 +13 +13 +13 +13 +15 +15 +15 +15 +15 +15 +17 +17 +17 +17 +17 +19 +19 +19 +22 +22 +22 +23 +23 +23 +24 +24 +24 +27 +28 +31 +31 +31 +33 +33 +37 +41 +41 +41 +41 +41 +41 +41 +41 +41 +41 +41 +43 +44 +47 +47 +47 +54 +54 +56 +56 +56 +59 +59 +59 +61 +61 +61 +64 +64 +64 +68 +71 +75 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +3 +3 +3 +3 +3 +3 +5 +6 +7 +5 +6 +7 +5 +6 +7 +5 +6 +7 +5 +6 +7 +5 +6 +7 +5 +6 +7 +5 +6 +7 +5 +6 +7 +5 +6 +7 +5 +6 +7 +5 +6 +7 +9 +9 +9 +9 +9 +9 +12 +12 +12 +12 +12 +12 +12 +12 +12 +12 +12 +12 +12 +12 +14 +14 +14 +14 +14 +14 +14 +14 +16 +16 +16 +16 +16 +16 +16 +16 +16 +16 +16 +16 +18 +18 +18 +18 +18 +20 +21 +20 +21 +20 +21 +25 +26 +25 +26 +25 +26 +29 +30 +32 +32 +32 +34 +35 +36 +34 +35 +36 +38 +39 +40 +40 +42 +42 +42 +42 +42 +42 +42 +42 +42 +42 +42 +45 +46 +48 +49 +50 +51 +52 +53 +53 +48 +49 +50 +51 +52 +53 +53 +48 +49 +50 +51 +52 +53 +53 +55 +55 +57 +58 +57 +58 +57 +58 +60 +60 +60 +62 +63 +62 +63 +62 +63 +65 +66 +67 +65 +66 +67 +65 +66 +67 +69 +70 +72 +73 +74 Index: vis_dev/vis-2.1/examples/ctlp3/symmetry.info =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/symmetry.info (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/symmetry.info (revision 11) @@ -0,0 +1,315 @@ +Node Class Description + 0 0 Combinational (s0) InputPin-nodes: 123 + 1 0 Combinational (s1) InputPin-nodes: 124 + 2 0 Combinational (s2) InputPin-nodes: 125 + 3 0 Combinational (ph0.state$_n16_n1a$false) InputPin-nodes: 126 + 4 0 Combinational (ph0.state$_n1f_n22$true) InputPin-nodes: 127 + 5 0 Combinational (ph0.out$raw_n8) InputPin-nodes: 128 + 6 0 Combinational (ph1.state$_n16_n1a$false) InputPin-nodes: 129 + 7 0 Combinational (ph1.state$_n1f_n22$true) InputPin-nodes: 130 + 8 0 Combinational (ph1.out$raw_n8) InputPin-nodes: 131 + 9 0 Combinational (ph2.state$_n16_n1a$false) InputPin-nodes: 132 + 10 0 Combinational (ph2.state$_n1f_n22$true) InputPin-nodes: 133 + 11 0 Combinational (ph2.out$raw_n8) InputPin-nodes: 134 + 12 2 Combinational (ph0._na) InputPin-nodes: 135 + 13 2 Combinational (ph0._n16) InputPin-nodes: 136 + 14 2 Combinational (ph1._na) InputPin-nodes: 137 + 15 2 Combinational (ph1._n16) InputPin-nodes: 138 + 16 2 Combinational (ph2._na) InputPin-nodes: 139 + 17 2 Combinational (ph2._n16) InputPin-nodes: 140 + 18 4 Combinational (ph0.state$_n13$raw_n3a) InputPin-nodes: 141 142 143 + 19 4 Combinational (ph0.state$_n9$raw_n3e) InputPin-nodes: 144 145 146 + 20 4 Combinational (ph0.state$_n1f$raw_n36) InputPin-nodes: 147 148 149 + 21 4 Combinational (ph0.state$_n23$raw_n35) InputPin-nodes: 150 151 152 + 22 4 Combinational (ph1.state$_n13$raw_n3a) InputPin-nodes: 153 154 155 + 23 4 Combinational (ph1.state$_n9$raw_n3e) InputPin-nodes: 156 157 158 + 24 4 Combinational (ph1.state$_n1f$raw_n36) InputPin-nodes: 159 160 161 + 25 4 Combinational (ph1.state$_n23$raw_n35) InputPin-nodes: 162 163 164 + 26 4 Combinational (ph2.state$_n13$raw_n3a) InputPin-nodes: 165 166 167 + 27 4 Combinational (ph2.state$_n9$raw_n3e) InputPin-nodes: 168 169 170 + 28 4 Combinational (ph2.state$_n1f$raw_n36) InputPin-nodes: 171 172 173 + 29 4 Combinational (ph2.state$_n23$raw_n35) InputPin-nodes: 174 175 176 + 30 8 Combinational (ph0._n26) InputPin-nodes: 177 + 31 8 Combinational (ph1._n26) InputPin-nodes: 178 + 32 8 Combinational (ph1._n2b) InputPin-nodes: 179 + 33 8 Combinational (ph0._n2b) InputPin-nodes: 180 + 34 8 Combinational (ph2._n26) InputPin-nodes: 181 + 35 8 Combinational (ph2._n2b) InputPin-nodes: 182 + 36 10 Combinational (ph0.state$INIT) InputPin-nodes: + 37 11 Combinational (str._n57) InputPin-nodes: 183 + 38 11 Combinational (str._n4a) InputPin-nodes: 184 + 39 11 Combinational (ph0._n1f) InputPin-nodes: 185 + 40 11 Combinational (ph1._n1f) InputPin-nodes: 186 + 41 11 Combinational (ph1._n23) InputPin-nodes: 187 + 42 11 Combinational (ph1._n9) InputPin-nodes: 188 + 43 11 Combinational (ph0._n23) InputPin-nodes: 189 + 44 11 Combinational (ph1._n13) InputPin-nodes: 190 + 45 11 Combinational (ph0._n9) InputPin-nodes: 191 + 46 11 Combinational (ph0._n13) InputPin-nodes: 192 + 47 11 Combinational (ph2._n1f) InputPin-nodes: 193 + 48 11 Combinational (ph2._n23) InputPin-nodes: 194 + 49 11 Combinational (ph2._n9) InputPin-nodes: 195 + 50 11 Combinational (ph2._n13) InputPin-nodes: 196 + 51 13 Combinational (str._n5c) InputPin-nodes: 197 + 52 13 Combinational (ph0._n14) InputPin-nodes: 198 + 53 13 Combinational (ph1._nc) InputPin-nodes: 199 + 54 13 Combinational (str._n5a) InputPin-nodes: 200 + 55 13 Combinational (ph1._n14) InputPin-nodes: 201 + 56 13 Combinational (ph2._nc) InputPin-nodes: 202 + 57 13 Combinational (ph0._nc) InputPin-nodes: 203 + 58 13 Combinational (ph2._n14) InputPin-nodes: 204 + 59 15 Combinational (ph1._n2a) InputPin-nodes: 205 206 + 60 15 Combinational (ph0._n2d) InputPin-nodes: 207 208 + 61 15 Combinational (ph0._n2a) InputPin-nodes: 209 210 + 62 15 Combinational (ph1._n2d) InputPin-nodes: 211 212 + 63 15 Combinational (ph2._n2a) InputPin-nodes: 213 214 + 64 15 Combinational (ph2._n2d) InputPin-nodes: 215 216 + 65 17 Combinational (ph1._n24) InputPin-nodes: 217 + 66 17 Combinational (str._n4f) InputPin-nodes: 218 + 67 17 Combinational (ph0._n24) InputPin-nodes: 219 + 68 17 Combinational (str._n4d) InputPin-nodes: 220 + 69 17 Combinational (ph2._n24) InputPin-nodes: 221 + 70 19 Combinational (ph1.state$_n2d$raw_n32) InputPin-nodes: 222 223 + 71 19 Combinational (ph0.state$_n2d$raw_n32) InputPin-nodes: 224 225 + 72 19 Combinational (ph2.state$_n2d$raw_n32) InputPin-nodes: 226 227 + 73 22 PseudoInput (ph1.r0_state) InputPin-nodes: + 74 22 PseudoInput (ph0.r0_state) InputPin-nodes: + 75 22 PseudoInput (ph2.r0_state) InputPin-nodes: + 76 23 PseudoInput (ph1.r1_state) InputPin-nodes: + 77 23 PseudoInput (ph0.r1_state) InputPin-nodes: + 78 23 PseudoInput (ph2.r1_state) InputPin-nodes: + 79 24 Latch (ph1.state) InputPin-nodes: 228 229 + 80 24 Latch (ph0.state) InputPin-nodes: 230 231 + 81 24 Latch (ph2.state) InputPin-nodes: 232 233 + 82 27 Combinational (str.state$INIT) InputPin-nodes: + 83 28 Combinational (str.state$_n5c$raw_n62) InputPin-nodes: 234 235 + 84 31 Combinational (ph1._n28) InputPin-nodes: 236 + 85 31 Combinational (ph0._n28) InputPin-nodes: 237 + 86 31 Combinational (ph2._n28) InputPin-nodes: 238 + 87 33 Combinational (str.state$_n57$raw_n66) InputPin-nodes: 239 240 241 + 88 33 Combinational (str.state$_n4a$raw_n68) InputPin-nodes: 242 243 244 + 89 37 Combinational (str._n6d) InputPin-nodes: 245 246 247 248 + 90 41 Combinational (ph1._n18) InputPin-nodes: 249 + 91 41 Combinational (str._n51) InputPin-nodes: 250 + 92 41 Combinational (str._n5e) InputPin-nodes: 251 + 93 41 Combinational (ph1._ne) InputPin-nodes: 252 + 94 41 Combinational (ph2._ne) InputPin-nodes: 253 + 95 41 Combinational (ph0._n18) InputPin-nodes: 254 + 96 41 Combinational (ph2._n18) InputPin-nodes: 255 + 97 41 Combinational (ph0._ne) InputPin-nodes: 256 + 98 41 Combinational (ph1._n2e) InputPin-nodes: 257 + 99 41 Combinational (ph2._n2e) InputPin-nodes: 258 +100 41 Combinational (ph0._n2e) InputPin-nodes: 259 +101 43 Combinational (ph1.state$INIT) InputPin-nodes: +102 44 Latch (str.state) InputPin-nodes: 260 261 +103 47 Combinational (ph1._n42) InputPin-nodes: 262 263 264 265 266 267 268 +104 47 Combinational (ph2._n42) InputPin-nodes: 269 270 271 272 273 274 275 +105 47 Combinational (ph0._n42) InputPin-nodes: 276 277 278 279 280 281 282 +106 54 Combinational (str._n58) InputPin-nodes: 283 +107 54 Combinational (str._n4b) InputPin-nodes: 284 +108 56 Combinational (ph0.state$_nc$raw_n12) InputPin-nodes: 285 286 +109 56 Combinational (ph2.state$_nc$raw_n12) InputPin-nodes: 287 288 +110 56 Combinational (ph1.state$_nc$raw_n12) InputPin-nodes: 289 290 +111 59 Combinational (ph2._n20) InputPin-nodes: 291 +112 59 Combinational (ph0._n20) InputPin-nodes: 292 +113 59 Combinational (ph1._n20) InputPin-nodes: 293 +114 61 Combinational (ph2.state$_n16$raw_n1c) InputPin-nodes: 294 295 +115 61 Combinational (ph1.state$_n16$raw_n1c) InputPin-nodes: 296 297 +116 61 Combinational (ph0.state$_n16$raw_n1c) InputPin-nodes: 298 299 +117 64 Combinational (ph1._n43) InputPin-nodes: 300 301 302 +118 64 Combinational (ph0._n43) InputPin-nodes: 303 304 305 +119 64 Combinational (ph2._n43) InputPin-nodes: 306 307 308 +120 68 Combinational (str.state$_n4f$raw_n55) InputPin-nodes: 309 310 +121 71 Combinational (str._n6e) InputPin-nodes: 311 312 313 +122 75 Combinational (ph2.state$INIT) InputPin-nodes: +123 1 InputPin of Node 0 (s0) Fed by node 5 (ph0.out$raw_n8) +124 1 InputPin of Node 1 (s1) Fed by node 8 (ph1.out$raw_n8) +125 1 InputPin of Node 2 (s2) Fed by node 11 (ph2.out$raw_n8) +126 1 InputPin of Node 3 (ph0.state$_n16_n1a$false) Fed by node 74 (ph0.r0_state) +127 1 InputPin of Node 4 (ph0.state$_n1f_n22$true) Fed by node 77 (ph0.r1_state) +128 1 InputPin of Node 5 (ph0.out$raw_n8) Fed by node 80 (ph0.state) +129 1 InputPin of Node 6 (ph1.state$_n16_n1a$false) Fed by node 73 (ph1.r0_state) +130 1 InputPin of Node 7 (ph1.state$_n1f_n22$true) Fed by node 76 (ph1.r1_state) +131 1 InputPin of Node 8 (ph1.out$raw_n8) Fed by node 79 (ph1.state) +132 1 InputPin of Node 9 (ph2.state$_n16_n1a$false) Fed by node 75 (ph2.r0_state) +133 1 InputPin of Node 10 (ph2.state$_n1f_n22$true) Fed by node 78 (ph2.r1_state) +134 1 InputPin of Node 11 (ph2.out$raw_n8) Fed by node 81 (ph2.state) +135 3 InputPin of Node 12 (ph0._na) Fed by node 80 (ph0.state) +136 3 InputPin of Node 13 (ph0._n16) Fed by node 2 (s2) +137 3 InputPin of Node 14 (ph1._na) Fed by node 79 (ph1.state) +138 3 InputPin of Node 15 (ph1._n16) Fed by node 0 (s0) +139 3 InputPin of Node 16 (ph2._na) Fed by node 81 (ph2.state) +140 3 InputPin of Node 17 (ph2._n16) Fed by node 1 (s1) +141 5 InputPin of Node 18 (ph0.state$_n13$raw_n3a) Fed by node 116 (ph0.state$_n16$raw_n1c) +142 6 InputPin of Node 18 (ph0.state$_n13$raw_n3a) Fed by node 20 (ph0.state$_n1f$raw_n36) +143 7 InputPin of Node 18 (ph0.state$_n13$raw_n3a) Fed by node 46 (ph0._n13) +144 5 InputPin of Node 19 (ph0.state$_n9$raw_n3e) Fed by node 108 (ph0.state$_nc$raw_n12) +145 6 InputPin of Node 19 (ph0.state$_n9$raw_n3e) Fed by node 18 (ph0.state$_n13$raw_n3a) +146 7 InputPin of Node 19 (ph0.state$_n9$raw_n3e) Fed by node 45 (ph0._n9) +147 5 InputPin of Node 20 (ph0.state$_n1f$raw_n36) Fed by node 4 (ph0.state$_n1f_n22$true) +148 6 InputPin of Node 20 (ph0.state$_n1f$raw_n36) Fed by node 21 (ph0.state$_n23$raw_n35) +149 7 InputPin of Node 20 (ph0.state$_n1f$raw_n36) Fed by node 39 (ph0._n1f) +150 5 InputPin of Node 21 (ph0.state$_n23$raw_n35) Fed by node 71 (ph0.state$_n2d$raw_n32) +151 6 InputPin of Node 21 (ph0.state$_n23$raw_n35) Fed by node 80 (ph0.state) +152 7 InputPin of Node 21 (ph0.state$_n23$raw_n35) Fed by node 43 (ph0._n23) +153 5 InputPin of Node 22 (ph1.state$_n13$raw_n3a) Fed by node 115 (ph1.state$_n16$raw_n1c) +154 6 InputPin of Node 22 (ph1.state$_n13$raw_n3a) Fed by node 24 (ph1.state$_n1f$raw_n36) +155 7 InputPin of Node 22 (ph1.state$_n13$raw_n3a) Fed by node 44 (ph1._n13) +156 5 InputPin of Node 23 (ph1.state$_n9$raw_n3e) Fed by node 110 (ph1.state$_nc$raw_n12) +157 6 InputPin of Node 23 (ph1.state$_n9$raw_n3e) Fed by node 22 (ph1.state$_n13$raw_n3a) +158 7 InputPin of Node 23 (ph1.state$_n9$raw_n3e) Fed by node 42 (ph1._n9) +159 5 InputPin of Node 24 (ph1.state$_n1f$raw_n36) Fed by node 7 (ph1.state$_n1f_n22$true) +160 6 InputPin of Node 24 (ph1.state$_n1f$raw_n36) Fed by node 25 (ph1.state$_n23$raw_n35) +161 7 InputPin of Node 24 (ph1.state$_n1f$raw_n36) Fed by node 40 (ph1._n1f) +162 5 InputPin of Node 25 (ph1.state$_n23$raw_n35) Fed by node 70 (ph1.state$_n2d$raw_n32) +163 6 InputPin of Node 25 (ph1.state$_n23$raw_n35) Fed by node 79 (ph1.state) +164 7 InputPin of Node 25 (ph1.state$_n23$raw_n35) Fed by node 41 (ph1._n23) +165 5 InputPin of Node 26 (ph2.state$_n13$raw_n3a) Fed by node 114 (ph2.state$_n16$raw_n1c) +166 6 InputPin of Node 26 (ph2.state$_n13$raw_n3a) Fed by node 28 (ph2.state$_n1f$raw_n36) +167 7 InputPin of Node 26 (ph2.state$_n13$raw_n3a) Fed by node 50 (ph2._n13) +168 5 InputPin of Node 27 (ph2.state$_n9$raw_n3e) Fed by node 109 (ph2.state$_nc$raw_n12) +169 6 InputPin of Node 27 (ph2.state$_n9$raw_n3e) Fed by node 26 (ph2.state$_n13$raw_n3a) +170 7 InputPin of Node 27 (ph2.state$_n9$raw_n3e) Fed by node 49 (ph2._n9) +171 5 InputPin of Node 28 (ph2.state$_n1f$raw_n36) Fed by node 10 (ph2.state$_n1f_n22$true) +172 6 InputPin of Node 28 (ph2.state$_n1f$raw_n36) Fed by node 29 (ph2.state$_n23$raw_n35) +173 7 InputPin of Node 28 (ph2.state$_n1f$raw_n36) Fed by node 47 (ph2._n1f) +174 5 InputPin of Node 29 (ph2.state$_n23$raw_n35) Fed by node 72 (ph2.state$_n2d$raw_n32) +175 6 InputPin of Node 29 (ph2.state$_n23$raw_n35) Fed by node 81 (ph2.state) +176 7 InputPin of Node 29 (ph2.state$_n23$raw_n35) Fed by node 48 (ph2._n23) +177 9 InputPin of Node 30 (ph0._n26) Fed by node 1 (s1) +178 9 InputPin of Node 31 (ph1._n26) Fed by node 2 (s2) +179 9 InputPin of Node 32 (ph1._n2b) Fed by node 0 (s0) +180 9 InputPin of Node 33 (ph0._n2b) Fed by node 2 (s2) +181 9 InputPin of Node 34 (ph2._n26) Fed by node 0 (s0) +182 9 InputPin of Node 35 (ph2._n2b) Fed by node 1 (s1) +183 12 InputPin of Node 37 (str._n57) Fed by node 106 (str._n58) +184 12 InputPin of Node 38 (str._n4a) Fed by node 107 (str._n4b) +185 12 InputPin of Node 39 (ph0._n1f) Fed by node 112 (ph0._n20) +186 12 InputPin of Node 40 (ph1._n1f) Fed by node 113 (ph1._n20) +187 12 InputPin of Node 41 (ph1._n23) Fed by node 65 (ph1._n24) +188 12 InputPin of Node 42 (ph1._n9) Fed by node 14 (ph1._na) +189 12 InputPin of Node 43 (ph0._n23) Fed by node 67 (ph0._n24) +190 12 InputPin of Node 44 (ph1._n13) Fed by node 55 (ph1._n14) +191 12 InputPin of Node 45 (ph0._n9) Fed by node 12 (ph0._na) +192 12 InputPin of Node 46 (ph0._n13) Fed by node 52 (ph0._n14) +193 12 InputPin of Node 47 (ph2._n1f) Fed by node 111 (ph2._n20) +194 12 InputPin of Node 48 (ph2._n23) Fed by node 69 (ph2._n24) +195 12 InputPin of Node 49 (ph2._n9) Fed by node 16 (ph2._na) +196 12 InputPin of Node 50 (ph2._n13) Fed by node 58 (ph2._n14) +197 14 InputPin of Node 51 (str._n5c) Fed by node 0 (s0) +198 14 InputPin of Node 52 (ph0._n14) Fed by node 80 (ph0.state) +199 14 InputPin of Node 53 (ph1._nc) Fed by node 2 (s2) +200 14 InputPin of Node 54 (str._n5a) Fed by node 102 (str.state) +201 14 InputPin of Node 55 (ph1._n14) Fed by node 79 (ph1.state) +202 14 InputPin of Node 56 (ph2._nc) Fed by node 0 (s0) +203 14 InputPin of Node 57 (ph0._nc) Fed by node 1 (s1) +204 14 InputPin of Node 58 (ph2._n14) Fed by node 81 (ph2.state) +205 16 InputPin of Node 59 (ph1._n2a) Fed by node 31 (ph1._n26) +206 16 InputPin of Node 59 (ph1._n2a) Fed by node 84 (ph1._n28) +207 16 InputPin of Node 60 (ph0._n2d) Fed by node 61 (ph0._n2a) +208 16 InputPin of Node 60 (ph0._n2d) Fed by node 33 (ph0._n2b) +209 16 InputPin of Node 61 (ph0._n2a) Fed by node 30 (ph0._n26) +210 16 InputPin of Node 61 (ph0._n2a) Fed by node 85 (ph0._n28) +211 16 InputPin of Node 62 (ph1._n2d) Fed by node 59 (ph1._n2a) +212 16 InputPin of Node 62 (ph1._n2d) Fed by node 32 (ph1._n2b) +213 16 InputPin of Node 63 (ph2._n2a) Fed by node 34 (ph2._n26) +214 16 InputPin of Node 63 (ph2._n2a) Fed by node 86 (ph2._n28) +215 16 InputPin of Node 64 (ph2._n2d) Fed by node 63 (ph2._n2a) +216 16 InputPin of Node 64 (ph2._n2d) Fed by node 35 (ph2._n2b) +217 18 InputPin of Node 65 (ph1._n24) Fed by node 79 (ph1.state) +218 18 InputPin of Node 66 (str._n4f) Fed by node 0 (s0) +219 18 InputPin of Node 67 (ph0._n24) Fed by node 80 (ph0.state) +220 18 InputPin of Node 68 (str._n4d) Fed by node 102 (str.state) +221 18 InputPin of Node 69 (ph2._n24) Fed by node 81 (ph2.state) +222 20 InputPin of Node 70 (ph1.state$_n2d$raw_n32) Fed by node 79 (ph1.state) +223 21 InputPin of Node 70 (ph1.state$_n2d$raw_n32) Fed by node 62 (ph1._n2d) +224 20 InputPin of Node 71 (ph0.state$_n2d$raw_n32) Fed by node 80 (ph0.state) +225 21 InputPin of Node 71 (ph0.state$_n2d$raw_n32) Fed by node 60 (ph0._n2d) +226 20 InputPin of Node 72 (ph2.state$_n2d$raw_n32) Fed by node 81 (ph2.state) +227 21 InputPin of Node 72 (ph2.state$_n2d$raw_n32) Fed by node 64 (ph2._n2d) +228 25 InputPin of Node 79 (ph1.state) Fed by node 117 (ph1._n43) +229 26 InputPin of Node 79 (ph1.state) Fed by node 101 (ph1.state$INIT) +230 25 InputPin of Node 80 (ph0.state) Fed by node 118 (ph0._n43) +231 26 InputPin of Node 80 (ph0.state) Fed by node 36 (ph0.state$INIT) +232 25 InputPin of Node 81 (ph2.state) Fed by node 119 (ph2._n43) +233 26 InputPin of Node 81 (ph2.state) Fed by node 122 (ph2.state$INIT) +234 29 InputPin of Node 83 (str.state$_n5c$raw_n62) Fed by node 102 (str.state) +235 30 InputPin of Node 83 (str.state$_n5c$raw_n62) Fed by node 51 (str._n5c) +236 32 InputPin of Node 84 (ph1._n28) Fed by node 0 (s0) +237 32 InputPin of Node 85 (ph0._n28) Fed by node 2 (s2) +238 32 InputPin of Node 86 (ph2._n28) Fed by node 1 (s1) +239 34 InputPin of Node 87 (str.state$_n57$raw_n66) Fed by node 83 (str.state$_n5c$raw_n62) +240 35 InputPin of Node 87 (str.state$_n57$raw_n66) Fed by node 102 (str.state) +241 36 InputPin of Node 87 (str.state$_n57$raw_n66) Fed by node 37 (str._n57) +242 34 InputPin of Node 88 (str.state$_n4a$raw_n68) Fed by node 120 (str.state$_n4f$raw_n55) +243 35 InputPin of Node 88 (str.state$_n4a$raw_n68) Fed by node 87 (str.state$_n57$raw_n66) +244 36 InputPin of Node 88 (str.state$_n4a$raw_n68) Fed by node 38 (str._n4a) +245 38 InputPin of Node 89 (str._n6d) Fed by node 38 (str._n4a) +246 39 InputPin of Node 89 (str._n6d) Fed by node 91 (str._n51) +247 40 InputPin of Node 89 (str._n6d) Fed by node 37 (str._n57) +248 40 InputPin of Node 89 (str._n6d) Fed by node 92 (str._n5e) +249 42 InputPin of Node 90 (ph1._n18) Fed by node 15 (ph1._n16) +250 42 InputPin of Node 91 (str._n51) Fed by node 66 (str._n4f) +251 42 InputPin of Node 92 (str._n5e) Fed by node 51 (str._n5c) +252 42 InputPin of Node 93 (ph1._ne) Fed by node 53 (ph1._nc) +253 42 InputPin of Node 94 (ph2._ne) Fed by node 56 (ph2._nc) +254 42 InputPin of Node 95 (ph0._n18) Fed by node 13 (ph0._n16) +255 42 InputPin of Node 96 (ph2._n18) Fed by node 17 (ph2._n16) +256 42 InputPin of Node 97 (ph0._ne) Fed by node 57 (ph0._nc) +257 42 InputPin of Node 98 (ph1._n2e) Fed by node 62 (ph1._n2d) +258 42 InputPin of Node 99 (ph2._n2e) Fed by node 64 (ph2._n2d) +259 42 InputPin of Node 100 (ph0._n2e) Fed by node 60 (ph0._n2d) +260 45 InputPin of Node 102 (str.state) Fed by node 121 (str._n6e) +261 46 InputPin of Node 102 (str.state) Fed by node 82 (str.state$INIT) +262 48 InputPin of Node 103 (ph1._n42) Fed by node 42 (ph1._n9) +263 49 InputPin of Node 103 (ph1._n42) Fed by node 93 (ph1._ne) +264 50 InputPin of Node 103 (ph1._n42) Fed by node 44 (ph1._n13) +265 51 InputPin of Node 103 (ph1._n42) Fed by node 90 (ph1._n18) +266 52 InputPin of Node 103 (ph1._n42) Fed by node 40 (ph1._n1f) +267 53 InputPin of Node 103 (ph1._n42) Fed by node 41 (ph1._n23) +268 53 InputPin of Node 103 (ph1._n42) Fed by node 98 (ph1._n2e) +269 48 InputPin of Node 104 (ph2._n42) Fed by node 49 (ph2._n9) +270 49 InputPin of Node 104 (ph2._n42) Fed by node 94 (ph2._ne) +271 50 InputPin of Node 104 (ph2._n42) Fed by node 50 (ph2._n13) +272 51 InputPin of Node 104 (ph2._n42) Fed by node 96 (ph2._n18) +273 52 InputPin of Node 104 (ph2._n42) Fed by node 47 (ph2._n1f) +274 53 InputPin of Node 104 (ph2._n42) Fed by node 48 (ph2._n23) +275 53 InputPin of Node 104 (ph2._n42) Fed by node 99 (ph2._n2e) +276 48 InputPin of Node 105 (ph0._n42) Fed by node 45 (ph0._n9) +277 49 InputPin of Node 105 (ph0._n42) Fed by node 97 (ph0._ne) +278 50 InputPin of Node 105 (ph0._n42) Fed by node 46 (ph0._n13) +279 51 InputPin of Node 105 (ph0._n42) Fed by node 95 (ph0._n18) +280 52 InputPin of Node 105 (ph0._n42) Fed by node 39 (ph0._n1f) +281 53 InputPin of Node 105 (ph0._n42) Fed by node 43 (ph0._n23) +282 53 InputPin of Node 105 (ph0._n42) Fed by node 100 (ph0._n2e) +283 55 InputPin of Node 106 (str._n58) Fed by node 54 (str._n5a) +284 55 InputPin of Node 107 (str._n4b) Fed by node 68 (str._n4d) +285 57 InputPin of Node 108 (ph0.state$_nc$raw_n12) Fed by node 80 (ph0.state) +286 58 InputPin of Node 108 (ph0.state$_nc$raw_n12) Fed by node 57 (ph0._nc) +287 57 InputPin of Node 109 (ph2.state$_nc$raw_n12) Fed by node 81 (ph2.state) +288 58 InputPin of Node 109 (ph2.state$_nc$raw_n12) Fed by node 56 (ph2._nc) +289 57 InputPin of Node 110 (ph1.state$_nc$raw_n12) Fed by node 79 (ph1.state) +290 58 InputPin of Node 110 (ph1.state$_nc$raw_n12) Fed by node 53 (ph1._nc) +291 60 InputPin of Node 111 (ph2._n20) Fed by node 81 (ph2.state) +292 60 InputPin of Node 112 (ph0._n20) Fed by node 80 (ph0.state) +293 60 InputPin of Node 113 (ph1._n20) Fed by node 79 (ph1.state) +294 62 InputPin of Node 114 (ph2.state$_n16$raw_n1c) Fed by node 9 (ph2.state$_n16_n1a$false) +295 63 InputPin of Node 114 (ph2.state$_n16$raw_n1c) Fed by node 17 (ph2._n16) +296 62 InputPin of Node 115 (ph1.state$_n16$raw_n1c) Fed by node 6 (ph1.state$_n16_n1a$false) +297 63 InputPin of Node 115 (ph1.state$_n16$raw_n1c) Fed by node 15 (ph1._n16) +298 62 InputPin of Node 116 (ph0.state$_n16$raw_n1c) Fed by node 3 (ph0.state$_n16_n1a$false) +299 63 InputPin of Node 116 (ph0.state$_n16$raw_n1c) Fed by node 13 (ph0._n16) +300 65 InputPin of Node 117 (ph1._n43) Fed by node 103 (ph1._n42) +301 66 InputPin of Node 117 (ph1._n43) Fed by node 23 (ph1.state$_n9$raw_n3e) +302 67 InputPin of Node 117 (ph1._n43) Fed by node 79 (ph1.state) +303 65 InputPin of Node 118 (ph0._n43) Fed by node 105 (ph0._n42) +304 66 InputPin of Node 118 (ph0._n43) Fed by node 19 (ph0.state$_n9$raw_n3e) +305 67 InputPin of Node 118 (ph0._n43) Fed by node 80 (ph0.state) +306 65 InputPin of Node 119 (ph2._n43) Fed by node 104 (ph2._n42) +307 66 InputPin of Node 119 (ph2._n43) Fed by node 27 (ph2.state$_n9$raw_n3e) +308 67 InputPin of Node 119 (ph2._n43) Fed by node 81 (ph2.state) +309 69 InputPin of Node 120 (str.state$_n4f$raw_n55) Fed by node 102 (str.state) +310 70 InputPin of Node 120 (str.state$_n4f$raw_n55) Fed by node 66 (str._n4f) +311 72 InputPin of Node 121 (str._n6e) Fed by node 89 (str._n6d) +312 73 InputPin of Node 121 (str._n6e) Fed by node 88 (str.state$_n4a$raw_n68) +313 74 InputPin of Node 121 (str._n6e) Fed by node 102 (str.state) Index: vis_dev/vis-2.1/examples/ctlp3/symmetry.map =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/symmetry.map (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/symmetry.map (revision 11) @@ -0,0 +1,2 @@ +1 +80 79 Index: vis_dev/vis-2.1/examples/ctlp3/symmetry.refined =================================================================== --- vis_dev/vis-2.1/examples/ctlp3/symmetry.refined (revision 11) +++ vis_dev/vis-2.1/examples/ctlp3/symmetry.refined (revision 11) @@ -0,0 +1,315 @@ +314 382 304 +300 7 138 179 181 197 202 218 236 +297 5 140 177 182 203 238 +298 5 136 178 180 199 237 +8 1 298 +5 1 147 +2 1 123 +6 1 296 +3 1 159 +0 1 124 +7 1 294 +4 1 171 +1 1 125 +23 1 191 +274 2 254 299 +21 1 188 +272 2 249 297 +22 1 195 +273 2 255 295 +38 1 145 +41 1 304 +35 1 142 +32 1 148 +36 1 157 +39 1 301 +33 1 154 +30 1 160 +37 1 169 +40 1 307 +34 1 166 +31 1 172 +80 1 209 +78 1 205 +81 1 212 +83 1 208 +79 1 213 +82 1 216 +90 1 231 +288 2 241 247 +287 2 244 245 +283 2 149 280 +281 2 161 266 +284 2 164 267 +275 2 158 262 +286 2 152 281 +278 2 155 264 +277 2 146 276 +280 2 143 278 +282 2 173 273 +285 2 176 274 +276 2 170 269 +279 2 167 271 +289 2 235 251 +107 1 192 +290 2 252 290 +108 1 283 +105 1 190 +291 2 253 288 +292 2 256 286 +106 1 196 +117 1 211 +295 2 225 259 +119 1 207 +293 2 223 257 +118 1 215 +294 2 227 258 +126 1 187 +296 2 250 310 +128 1 189 +129 1 284 +127 1 194 +135 1 162 +137 1 150 +136 1 174 +144 1 129 +146 1 126 +145 1 132 +147 1 130 +149 1 127 +148 1 133 +301 9 131 137 163 201 217 222 289 293 302 +303 9 128 135 151 198 219 224 285 292 305 +302 9 134 139 175 204 221 226 287 291 308 +156 1 261 +157 1 239 +160 1 206 +162 1 210 +161 1 214 +166 1 243 +167 1 312 +174 1 311 +183 1 265 +178 1 246 +179 1 248 +180 1 263 +181 1 270 +185 1 279 +184 1 272 +182 1 277 +186 1 268 +187 1 275 +188 1 282 +200 1 229 +299 6 200 220 234 240 309 313 +203 1 300 +204 1 306 +205 1 303 +225 1 183 +224 1 184 +230 1 144 +229 1 168 +228 1 156 +238 1 193 +239 1 185 +237 1 186 +244 1 165 +243 1 153 +245 1 141 +252 1 228 +254 1 230 +253 1 232 +264 1 242 +267 1 260 +271 1 233 +20 1 0 +18 1 1 +19 1 2 +17 1 3 +14 1 4 +11 1 5 +15 1 6 +12 1 7 +9 1 8 +16 1 9 +13 1 10 +10 1 11 +26 1 12 +29 1 13 +24 1 14 +27 1 15 +25 1 16 +28 1 17 +50 1 18 +62 1 18 +74 1 18 +53 1 19 +65 1 19 +77 1 19 +47 1 20 +59 1 20 +71 1 20 +44 1 21 +56 1 21 +68 1 21 +48 1 22 +60 1 22 +72 1 22 +51 1 23 +63 1 23 +75 1 23 +45 1 24 +57 1 24 +69 1 24 +42 1 25 +54 1 25 +66 1 25 +49 1 26 +61 1 26 +73 1 26 +52 1 27 +64 1 27 +76 1 27 +46 1 28 +58 1 28 +70 1 28 +43 1 29 +55 1 29 +67 1 29 +86 1 30 +84 1 31 +87 1 32 +89 1 33 +85 1 34 +88 1 35 +104 1 37 +103 1 38 +99 1 39 +97 1 40 +100 1 41 +91 1 42 +102 1 43 +94 1 44 +93 1 45 +96 1 46 +98 1 47 +101 1 48 +92 1 49 +95 1 50 +113 1 51 +111 1 52 +114 1 53 +112 1 54 +109 1 55 +115 1 56 +116 1 57 +110 1 58 +120 1 59 +120 1 59 +125 1 60 +125 1 60 +122 1 61 +122 1 61 +123 1 62 +123 1 62 +121 1 63 +121 1 63 +124 1 64 +124 1 64 +130 1 65 +134 1 66 +132 1 67 +133 1 68 +131 1 69 +138 1 70 +141 1 70 +140 1 71 +143 1 71 +139 1 72 +142 1 72 +150 1 79 +153 1 79 +152 1 80 +155 1 80 +151 1 81 +154 1 81 +158 1 83 +159 1 83 +163 1 84 +165 1 85 +164 1 86 +168 1 87 +170 1 87 +172 1 87 +169 1 88 +171 1 88 +173 1 88 +175 1 89 +176 1 89 +177 1 89 +177 1 89 +194 1 90 +189 1 91 +190 1 92 +191 1 93 +192 1 94 +196 1 95 +195 1 96 +193 1 97 +197 1 98 +198 1 99 +199 1 100 +201 1 102 +202 1 102 +206 1 103 +209 1 103 +212 1 103 +215 1 103 +218 1 103 +221 1 103 +221 1 103 +207 1 104 +210 1 104 +213 1 104 +216 1 104 +219 1 104 +222 1 104 +222 1 104 +208 1 105 +211 1 105 +214 1 105 +217 1 105 +220 1 105 +223 1 105 +223 1 105 +227 1 106 +226 1 107 +233 1 108 +236 1 108 +232 1 109 +235 1 109 +231 1 110 +234 1 110 +241 1 111 +242 1 112 +240 1 113 +247 1 114 +250 1 114 +246 1 115 +249 1 115 +248 1 116 +251 1 116 +255 1 117 +258 1 117 +261 1 117 +257 1 118 +260 1 118 +263 1 118 +256 1 119 +259 1 119 +262 1 119 +265 1 120 +266 1 120 +268 1 121 +269 1 121 +270 1 121 Index: vis_dev/vis-2.1/examples/daio_receiver/check_result =================================================================== --- vis_dev/vis-2.1/examples/daio_receiver/check_result (revision 11) +++ vis_dev/vis-2.1/examples/daio_receiver/check_result (revision 11) @@ -0,0 +1,2 @@ +# MC: the number of non-trivial forced segments 12 +# INV: formula failed --- !(((((((bit_count_A<6>=0 * bit_count_A<5>=0) * bit_count_A<4>=0) * bit_count_A<3>=1) * bit_count_A<2>=1) * bit_count_A<1>=1) * bit_count_A<0>=1)) Index: vis_dev/vis-2.1/examples/daio_receiver/check_script =================================================================== --- vis_dev/vis-2.1/examples/daio_receiver/check_script (revision 11) +++ vis_dev/vis-2.1/examples/daio_receiver/check_script (revision 11) @@ -0,0 +1,4 @@ +read_blif_mv daio_receiver.mv +init_verify +check_invariant -d 1 -i -w var.system -t 5000 daio_receiver.inv +quit Index: vis_dev/vis-2.1/examples/daio_receiver/daio_receiver.inv =================================================================== --- vis_dev/vis-2.1/examples/daio_receiver/daio_receiver.inv (revision 11) +++ vis_dev/vis-2.1/examples/daio_receiver/daio_receiver.inv (revision 11) @@ -0,0 +1,2 @@ +#FAIL: +!(bit_count_A[6:0]=15); Index: vis_dev/vis-2.1/examples/daio_receiver/daio_receiver.mv =================================================================== --- vis_dev/vis-2.1/examples/daio_receiver/daio_receiver.mv (revision 11) +++ vis_dev/vis-2.1/examples/daio_receiver/daio_receiver.mv (revision 11) @@ -0,0 +1,5503 @@ +# vl2mv daio_receiver.v +# version: 0.2 +# date: 01:47:25 01/02/01 () +.model daio_receiver +# I/O ports +.outputs load_buff +.outputs clock_out +.inputs biphase_violation +.inputs bit_in +.inputs xtal<0> xtal<1> xtal<2> xtal<3> +.outputs parity +.outputs shift_reg<0> shift_reg<1> shift_reg<2> shift_reg<3> shift_reg<4> shift_reg<5> shift_reg<6> shift_reg<7> shift_reg<8> shift_reg<9> shift_reg<10> shift_reg<11> shift_reg<12> shift_reg<13> shift_reg<14> shift_reg<15> shift_reg<16> shift_reg<17> shift_reg<18> shift_reg<19> +.inputs carrier_loss +.inputs rx_control<0> rx_control<1> rx_control<2> rx_control<3> +.inputs reset +.outputs load_A +.outputs rx_status<0> rx_status<1> rx_status<2> rx_status<3> +.inputs preamble_3 +.outputs frame_ofs<0> frame_ofs<1> +.outputs load_B +.inputs preamble_2 +.inputs preamble_1 +.mv pc 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +# assign rx_status = {rx_status_3 , rx_status_2 , rx_status_1 , rx_status_0 } +.names rx_status_0 _n1<0> +- =rx_status_0 +.names _n2 +0 +.names rx_status_1 _n1<1> +- =rx_status_1 +.names _n3 +0 +.names rx_status_2 _n1<2> +- =rx_status_2 +.names _n4 +0 +.names rx_status_3 _n1<3> +- =rx_status_3 +.names _n5 +0 +.names _n1<0> rx_status$raw_n0<0> +- =_n1<0> +.names _n1<1> rx_status$raw_n0<1> +- =_n1<1> +.names _n1<2> rx_status$raw_n0<2> +- =_n1<2> +.names _n1<3> rx_status$raw_n0<3> +- =_n1<3> +# bit_count_A = 0 +.names bit_count_A$raw_n6<0> +0 +.names bit_count_A$raw_n6<1> +0 +.names bit_count_A$raw_n6<2> +0 +.names bit_count_A$raw_n6<3> +0 +.names bit_count_A$raw_n6<4> +0 +.names bit_count_A$raw_n6<5> +0 +.names bit_count_A$raw_n6<6> +0 +# bit_count_B = 0 +.names bit_count_B$raw_n7<0> +0 +.names bit_count_B$raw_n7<1> +0 +.names bit_count_B$raw_n7<2> +0 +.names bit_count_B$raw_n7<3> +0 +.names bit_count_B$raw_n7<4> +0 +.names bit_count_B$raw_n7<5> +0 +.names bit_count_B$raw_n7<6> +0 +# frame_counter = 0 +.names frame_counter$raw_n8<0> +0 +.names frame_counter$raw_n8<1> +0 +.names frame_counter$raw_n8<2> +0 +.names frame_counter$raw_n8<3> +0 +.names frame_counter$raw_n8<4> +0 +.names frame_counter$raw_n8<5> +0 +.names frame_counter$raw_n8<6> +0 +.names frame_counter$raw_n8<7> +0 +.names frame_counter$raw_n8<8> +0 +# clock_out = 0 +.names clock_out$raw_n9 +0 +# rx_status_3 = 0 +.names rx_status_3$raw_na +0 +# rx_status_2 = 0 +.names rx_status_2$raw_nb +0 +# rx_status_1 = 0 +.names rx_status_1$raw_nc +0 +# rx_status_0 = 0 +.names rx_status_0$raw_nd +0 +# parity = 0 +.names parity$raw_ne +0 +# load_A = 0 +.names load_A$raw_nf +0 +# load_B = 0 +.names load_B$raw_n10 +0 +# load_buff = 0 +.names load_buff$raw_n11 +0 +# shift_reg = 0 +.names shift_reg$raw_n12<0> +0 +.names shift_reg$raw_n12<1> +0 +.names shift_reg$raw_n12<2> +0 +.names shift_reg$raw_n12<3> +0 +.names shift_reg$raw_n12<4> +0 +.names shift_reg$raw_n12<5> +0 +.names shift_reg$raw_n12<6> +0 +.names shift_reg$raw_n12<7> +0 +.names shift_reg$raw_n12<8> +0 +.names shift_reg$raw_n12<9> +0 +.names shift_reg$raw_n12<10> +0 +.names shift_reg$raw_n12<11> +0 +.names shift_reg$raw_n12<12> +0 +.names shift_reg$raw_n12<13> +0 +.names shift_reg$raw_n12<14> +0 +.names shift_reg$raw_n12<15> +0 +.names shift_reg$raw_n12<16> +0 +.names shift_reg$raw_n12<17> +0 +.names shift_reg$raw_n12<18> +0 +.names shift_reg$raw_n12<19> +0 +# pc = 0 +.mv pc$raw_n13 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$raw_n13 +L0 +# non-blocking assignments for initial +# assign frame_ofs [1 : 0] = frame_counter [1 : 0] +.names frame_counter<0> frame_ofs$raw_n14<0> +- =frame_counter<0> +.names frame_counter<1> frame_ofs$raw_n14<1> +- =frame_counter<1> +.names reset _n15 +- =reset +# rx_status_3 = 0 +.names rx_status_3$reset_n16$true +0 +# rx_status_2 = 0 +.names rx_status_2$reset_n17$true +0 +# load_A = 0 +.names load_A$reset_n18$true +0 +# load_B = 0 +.names load_B$reset_n19$true +0 +# load_buff = 0 +.names load_buff$reset_n1a$true +0 +# bit_count_A = 0 +.names bit_count_A$reset_n1b$true<0> +0 +.names bit_count_A$reset_n1b$true<1> +0 +.names bit_count_A$reset_n1b$true<2> +0 +.names bit_count_A$reset_n1b$true<3> +0 +.names bit_count_A$reset_n1b$true<4> +0 +.names bit_count_A$reset_n1b$true<5> +0 +.names bit_count_A$reset_n1b$true<6> +0 +# bit_count_B = 0 +.names bit_count_B$reset_n1c$true<0> +0 +.names bit_count_B$reset_n1c$true<1> +0 +.names bit_count_B$reset_n1c$true<2> +0 +.names bit_count_B$reset_n1c$true<3> +0 +.names bit_count_B$reset_n1c$true<4> +0 +.names bit_count_B$reset_n1c$true<5> +0 +.names bit_count_B$reset_n1c$true<6> +0 +# frame_counter = 0 +.names frame_counter$reset_n1d$true<0> +0 +.names frame_counter$reset_n1d$true<1> +0 +.names frame_counter$reset_n1d$true<2> +0 +.names frame_counter$reset_n1d$true<3> +0 +.names frame_counter$reset_n1d$true<4> +0 +.names frame_counter$reset_n1d$true<5> +0 +.names frame_counter$reset_n1d$true<6> +0 +.names frame_counter$reset_n1d$true<7> +0 +.names frame_counter$reset_n1d$true<8> +0 +# pc = 0 +.mv pc$reset_n1e$true 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$reset_n1e$true +L0 +.mv _n21 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n21 +L0 +.names pc _n21 _n20 +.def 0 +- =pc 1 +.names _n20 _n1f +1 1 +0 0 +.names rx_control<2> _n23 +.def 1 +0 0 +.names _n23 _n22 +- =_n23 +# pc = 1 +.mv pc$rx_control_n24$true 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$rx_control_n24$true +L1 +# if/else (rx_control [2]) +.mv pc$rx_control$raw_n27 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names rx_control<2> _n28 +.def 1 +0 0 +.names pc$rx_control_n24$true pc _n28 pc$rx_control$raw_n27 +- - 0 =pc +- - 1 =pc$rx_control_n24$true +.mv _n2b 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n2b +L1 +.names pc _n2b _n2a +.def 0 +- =pc 1 +.names _n2a _n29 +1 1 +0 0 +.names _n2e<0> +0 +.names _n2e<1> +0 +.names rx_control<0> _n2e<0> _n2f<0> +.def 0 +0 1 1 +1 0 1 +.names rx_control<1> _n2e<1> _n2f<1> +.def 0 +0 1 1 +1 0 1 +.names _n2f<0> _n2f<1> _n30 +.def 1 +0 0 0 +.names _n30 _n2d +0 1 +1 0 +.names _n2d _n2c +1 1 +0 0 +# clock_out = xtal [0] +.names xtal<0> clock_out$_n2c_n31$true +- =xtal<0> +.names _n34<0> +1 +.names _n34<1> +0 +.names rx_control<0> _n34<0> _n35<0> +.def 0 +0 1 1 +1 0 1 +.names rx_control<1> _n34<1> _n35<1> +.def 0 +0 1 1 +1 0 1 +.names _n35<0> _n35<1> _n36 +.def 1 +0 0 0 +.names _n36 _n33 +0 1 +1 0 +.names _n33 _n32 +1 1 +0 0 +# clock_out = xtal [1] +.names xtal<1> clock_out$_n32_n37$true +- =xtal<1> +.names _n3a<0> +0 +.names _n3a<1> +1 +.names rx_control<0> _n3a<0> _n3b<0> +.def 0 +0 1 1 +1 0 1 +.names rx_control<1> _n3a<1> _n3b<1> +.def 0 +0 1 1 +1 0 1 +.names _n3b<0> _n3b<1> _n3c +.def 1 +0 0 0 +.names _n3c _n39 +0 1 +1 0 +.names _n39 _n38 +1 1 +0 0 +# clock_out = xtal [2] +.names xtal<2> clock_out$_n38_n3d$true +- =xtal<2> +.names _n40<0> +1 +.names _n40<1> +1 +.names rx_control<0> _n40<0> _n41<0> +.def 0 +0 1 1 +1 0 1 +.names rx_control<1> _n40<1> _n41<1> +.def 0 +0 1 1 +1 0 1 +.names _n41<0> _n41<1> _n42 +.def 1 +0 0 0 +.names _n42 _n3f +0 1 +1 0 +.names _n3f _n3e +1 1 +0 0 +# clock_out = xtal [3] +.names xtal<3> clock_out$_n3e_n43$true +- =xtal<3> +# case (rx_control [1 : 0]) +.names clock_out$_n3e_n43$true clock_out _n3e clock_out$_n3e$raw_n46 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names clock_out$_n38_n3d$true clock_out$_n3e$raw_n46 _n38 clock_out$_n38$raw_n48 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names clock_out$_n32_n37$true clock_out$_n38$raw_n48 _n32 clock_out$_n32$raw_n4d +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names clock_out$_n2c_n31$true clock_out$_n32$raw_n4d _n2c clock_out$_n2c$raw_n52 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# pc = 2 +.mv pc$_n29_n57$true 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n29_n57$true +L2 +.mv _n5a 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n5a +L2 +.names pc _n5a _n59 +.def 0 +- =pc 1 +.names _n59 _n58 +1 1 +0 0 +.names preamble_1 _n5b +- =preamble_1 +# bit_count_A = 4 +.names bit_count_A$preamble_1_n5c$true<0> +0 +.names bit_count_A$preamble_1_n5c$true<1> +0 +.names bit_count_A$preamble_1_n5c$true<2> +1 +.names bit_count_A$preamble_1_n5c$true<3> +0 +.names bit_count_A$preamble_1_n5c$true<4> +0 +.names bit_count_A$preamble_1_n5c$true<5> +0 +.names bit_count_A$preamble_1_n5c$true<6> +0 +# pc = 3 +.mv pc$preamble_1_n5d$true 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$preamble_1_n5d$true +L3 +# if/else (preamble_1 ) +.names bit_count_A$preamble_1_n5c$true<0> bit_count_A<0> preamble_1 bit_count_A$preamble_1$raw_n62<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$preamble_1_n5c$true<1> bit_count_A<1> preamble_1 bit_count_A$preamble_1$raw_n62<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$preamble_1_n5c$true<2> bit_count_A<2> preamble_1 bit_count_A$preamble_1$raw_n62<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$preamble_1_n5c$true<3> bit_count_A<3> preamble_1 bit_count_A$preamble_1$raw_n62<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$preamble_1_n5c$true<4> bit_count_A<4> preamble_1 bit_count_A$preamble_1$raw_n62<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$preamble_1_n5c$true<5> bit_count_A<5> preamble_1 bit_count_A$preamble_1$raw_n62<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$preamble_1_n5c$true<6> bit_count_A<6> preamble_1 bit_count_A$preamble_1$raw_n62<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$preamble_1$raw_n6a 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$preamble_1_n5d$true pc preamble_1 pc$preamble_1$raw_n6a +- - 0 =pc +- - 1 =pc$preamble_1_n5d$true +.mv _n6d 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n6d +L3 +.names pc _n6d _n6c +.def 0 +- =pc 1 +.names _n6c _n6b +1 1 +0 0 +.names _n6e<0> +0 +.names _n6e<1> +0 +.names _n6e<2> +0 +.names _n6e<3> +0 +.names _n6e<4> +0 +.names _n6e<5> +1 +.names _n6e<6> +0 +# bit_count_A < 32 +.names _n71 +0 +.names bit_count_A<0> _n6e<0> _n71 _n70<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n73 +0 +.names bit_count_A<0> _n6e<0> _n73 _n72 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<1> _n6e<1> _n72 _n70<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<1> _n6e<1> _n72 _n74 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<2> _n6e<2> _n74 _n70<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<2> _n6e<2> _n74 _n75 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<3> _n6e<3> _n75 _n70<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<3> _n6e<3> _n75 _n76 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<4> _n6e<4> _n76 _n70<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<4> _n6e<4> _n76 _n77 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<5> _n6e<5> _n77 _n70<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<5> _n6e<5> _n77 _n78 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<6> _n6e<6> _n78 _n70<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<6> _n6e<6> _n78 _n79 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n70<0> _n70<1> _n70<2> _n70<3> _n70<4> _n70<5> _n70<6> _n7a +.def 1 +0 0 0 0 0 0 0 0 +.names _n79 _n7a _n6f +.def 0 +1 1 1 +.names _n6f _n7b +- =_n6f +.names _n7d<0> +1 +.names _n7d<1> +1 +.names _n7d<2> +1 +.names _n7d<3> +1 +.names _n7d<4> +1 +.names _n7d<5> +0 +.names _n7d<6> +0 +# bit_count_A == 31 +.names bit_count_A<0> _n7d<0> _n7e<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<1> _n7d<1> _n7e<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<2> _n7d<2> _n7e<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<3> _n7d<3> _n7e<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<4> _n7d<4> _n7e<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<5> _n7d<5> _n7e<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<6> _n7d<6> _n7e<6> +.def 0 +0 1 1 +1 0 1 +.names _n7e<0> _n7e<1> _n7e<2> _n7e<3> _n7e<4> _n7e<5> _n7e<6> _n7f +.def 1 +0 0 0 0 0 0 0 0 +.names _n7f _n7c +0 1 +1 0 +.names _n7c _n80 +- =_n7c +# load_A = 1 +.names load_A$_n7c_n81$true +1 +# if/else (bit_count_A == 31) +.names load_A$_n7c_n81$true load_A _n7c load_A$_n7c$raw_n84 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n87<0> +0 +.names _n87<1> +1 +.names _n87<2> +0 +.names _n87<3> +0 +.names _n87<4> +0 +.names _n87<5> +0 +.names _n87<6> +0 +# bit_count_A == 2 +.names bit_count_A<0> _n87<0> _n88<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<1> _n87<1> _n88<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<2> _n87<2> _n88<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<3> _n87<3> _n88<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<4> _n87<4> _n88<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<5> _n87<5> _n88<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<6> _n87<6> _n88<6> +.def 0 +0 1 1 +1 0 1 +.names _n88<0> _n88<1> _n88<2> _n88<3> _n88<4> _n88<5> _n88<6> _n89 +.def 1 +0 0 0 0 0 0 0 0 +.names _n89 _n86 +0 1 +1 0 +.names _n86 _n8a +- =_n86 +# load_B = 0 +.names load_B$_n86_n8b$true +0 +# if/else (bit_count_A == 2) +.names load_B$_n86_n8b$true load_B _n86 load_B$_n86$raw_n91 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n95<0> +1 +.names _n95<1> +1 +.names _n95<2> +0 +.names _n95<3> +0 +.names _n95<4> +0 +.names _n95<5> +0 +.names _n95<6> +0 +# bit_count_A == 3 +.names bit_count_A<0> _n95<0> _n96<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<1> _n95<1> _n96<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<2> _n95<2> _n96<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<3> _n95<3> _n96<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<4> _n95<4> _n96<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<5> _n95<5> _n96<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<6> _n95<6> _n96<6> +.def 0 +0 1 1 +1 0 1 +.names _n96<0> _n96<1> _n96<2> _n96<3> _n96<4> _n96<5> _n96<6> _n97 +.def 1 +0 0 0 0 0 0 0 0 +.names _n97 _n94 +0 1 +1 0 +.names _n94 _n98 +- =_n94 +# load_buff = 1 +.names load_buff$_n94_n99$true +1 +# if/else (bit_count_A == 3) +.names load_buff$_n94_n99$true load_buff _n94 load_buff$_n94$raw_na0 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _na7<0> +1 +.names _na7<1> +0 +.names _na7<2> +1 +.names _na7<3> +0 +.names _na7<4> +0 +.names _na7<5> +0 +.names _na7<6> +0 +# bit_count_A == 5 +.names bit_count_A<0> _na7<0> _na8<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<1> _na7<1> _na8<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<2> _na7<2> _na8<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<3> _na7<3> _na8<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<4> _na7<4> _na8<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<5> _na7<5> _na8<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<6> _na7<6> _na8<6> +.def 0 +0 1 1 +1 0 1 +.names _na8<0> _na8<1> _na8<2> _na8<3> _na8<4> _na8<5> _na8<6> _na9 +.def 1 +0 0 0 0 0 0 0 0 +.names _na9 _na6 +0 1 +1 0 +.names _na6 _naa +- =_na6 +# load_buff = 0 +.names load_buff$_na6_nab$true +0 +# if/else (bit_count_A == 5) +.names load_buff$_na6_nab$true load_buff$_n94$raw_na0 _na6 load_buff$_na6$raw_nac +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# bit_count_A = bit_count_A + 1 +.names _nba<0> +1 +.names _nba<1> +0 +.names _nba<2> +0 +.names _nba<3> +0 +.names _nba<4> +0 +.names _nba<5> +0 +.names _nba<6> +0 +# bit_count_A + 1 +.names _nbc +0 +.names bit_count_A<0> _nba<0> _nbc _nbb<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _nbe +0 +.names bit_count_A<0> _nba<0> _nbe _nbd +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<1> _nba<1> _nbd _nbb<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<1> _nba<1> _nbd _nbf +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<2> _nba<2> _nbf _nbb<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<2> _nba<2> _nbf _nc0 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<3> _nba<3> _nc0 _nbb<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<3> _nba<3> _nc0 _nc1 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<4> _nba<4> _nc1 _nbb<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<4> _nba<4> _nc1 _nc2 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<5> _nba<5> _nc2 _nbb<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<5> _nba<5> _nc2 _nc3 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<6> _nba<6> _nc3 _nbb<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _nbb<0> bit_count_A$_n6f_nb9$true<0> +- =_nbb<0> +.names _nbb<1> bit_count_A$_n6f_nb9$true<1> +- =_nbb<1> +.names _nbb<2> bit_count_A$_n6f_nb9$true<2> +- =_nbb<2> +.names _nbb<3> bit_count_A$_n6f_nb9$true<3> +- =_nbb<3> +.names _nbb<4> bit_count_A$_n6f_nb9$true<4> +- =_nbb<4> +.names _nbb<5> bit_count_A$_n6f_nb9$true<5> +- =_nbb<5> +.names _nbb<6> bit_count_A$_n6f_nb9$true<6> +- =_nbb<6> +# pc = 4 +.mv pc$_n6f_nc4$false 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n6f_nc4$false +L4 +# if/else (bit_count_A < 32) +.names load_buff$_na6$raw_nac load_buff _n6f load_buff$_n6f$raw_ncd +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n6f_nb9$true<0> bit_count_A<0> _n6f bit_count_A$_n6f$raw_ncf<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n6f_nb9$true<1> bit_count_A<1> _n6f bit_count_A$_n6f$raw_ncf<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n6f_nb9$true<2> bit_count_A<2> _n6f bit_count_A$_n6f$raw_ncf<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n6f_nb9$true<3> bit_count_A<3> _n6f bit_count_A$_n6f$raw_ncf<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n6f_nb9$true<4> bit_count_A<4> _n6f bit_count_A$_n6f$raw_ncf<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n6f_nb9$true<5> bit_count_A<5> _n6f bit_count_A$_n6f$raw_ncf<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n6f_nb9$true<6> bit_count_A<6> _n6f bit_count_A$_n6f$raw_ncf<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_A$_n7c$raw_n84 load_A _n6f load_A$_n6f$raw_nd7 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B$_n86$raw_n91 load_B _n6f load_B$_n6f$raw_nd9 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n6f$raw_ndb 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc pc$_n6f_nc4$false _n6f pc$_n6f$raw_ndb +- - 0 =pc$_n6f_nc4$false +- - 1 =pc +.mv _nde 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _nde +L4 +.names pc _nde _ndd +.def 0 +- =pc 1 +.names _ndd _ndc +1 1 +0 0 +# bit_count_B = 1 +.names bit_count_B$_ndc_ndf$true<0> +1 +.names bit_count_B$_ndc_ndf$true<1> +0 +.names bit_count_B$_ndc_ndf$true<2> +0 +.names bit_count_B$_ndc_ndf$true<3> +0 +.names bit_count_B$_ndc_ndf$true<4> +0 +.names bit_count_B$_ndc_ndf$true<5> +0 +.names bit_count_B$_ndc_ndf$true<6> +0 +# frame_counter = 1 +.names frame_counter$_ndc_ne0$true<0> +1 +.names frame_counter$_ndc_ne0$true<1> +0 +.names frame_counter$_ndc_ne0$true<2> +0 +.names frame_counter$_ndc_ne0$true<3> +0 +.names frame_counter$_ndc_ne0$true<4> +0 +.names frame_counter$_ndc_ne0$true<5> +0 +.names frame_counter$_ndc_ne0$true<6> +0 +.names frame_counter$_ndc_ne0$true<7> +0 +.names frame_counter$_ndc_ne0$true<8> +0 +# pc = 5 +.mv pc$_ndc_ne1$true 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_ndc_ne1$true +L5 +.mv _ne4 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _ne4 +L5 +.names pc _ne4 _ne3 +.def 0 +- =pc 1 +.names _ne3 _ne2 +1 1 +0 0 +.names _ne5<0> +0 +.names _ne5<1> +0 +.names _ne5<2> +0 +.names _ne5<3> +0 +.names _ne5<4> +0 +.names _ne5<5> +1 +.names _ne5<6> +0 +# bit_count_B < 32 +.names _ne8 +0 +.names bit_count_B<0> _ne5<0> _ne8 _ne7<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _nea +0 +.names bit_count_B<0> _ne5<0> _nea _ne9 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<1> _ne5<1> _ne9 _ne7<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<1> _ne5<1> _ne9 _neb +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<2> _ne5<2> _neb _ne7<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<2> _ne5<2> _neb _nec +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<3> _ne5<3> _nec _ne7<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<3> _ne5<3> _nec _ned +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<4> _ne5<4> _ned _ne7<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<4> _ne5<4> _ned _nee +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<5> _ne5<5> _nee _ne7<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<5> _ne5<5> _nee _nef +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<6> _ne5<6> _nef _ne7<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<6> _ne5<6> _nef _nf0 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _ne7<0> _ne7<1> _ne7<2> _ne7<3> _ne7<4> _ne7<5> _ne7<6> _nf1 +.def 1 +0 0 0 0 0 0 0 0 +.names _nf0 _nf1 _ne6 +.def 0 +1 1 1 +.names _ne6 _nf2 +- =_ne6 +.names _nf4<0> +0 +.names _nf4<1> +0 +.names _nf4<2> +1 +.names _nf4<3> +0 +.names _nf4<4> +0 +.names _nf4<5> +0 +.names _nf4<6> +0 +# bit_count_B == 4 +.names bit_count_B<0> _nf4<0> _nf5<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<1> _nf4<1> _nf5<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<2> _nf4<2> _nf5<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<3> _nf4<3> _nf5<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<4> _nf4<4> _nf5<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<5> _nf4<5> _nf5<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<6> _nf4<6> _nf5<6> +.def 0 +0 1 1 +1 0 1 +.names _nf5<0> _nf5<1> _nf5<2> _nf5<3> _nf5<4> _nf5<5> _nf5<6> _nf6 +.def 1 +0 0 0 0 0 0 0 0 +.names _nf6 _nf3 +0 1 +1 0 +.names _nf8 +0 +# preamble_3 == 0 +.names preamble_3 _nf8 _nf9 +.def 0 +0 1 1 +1 0 1 +.names _nf9 _nf7 +0 1 +1 0 +# (bit_count_B == 4) && (preamble_3 == 0) +.names _nf3 _nf7 _nfb +.def 0 +1 1 1 +.names _nfb _nfc +- =_nfb +# rx_status_2 = 1 +.names rx_status_2$_nfb_nfd$true +1 +# if/else ((bit_count_B == 4) && (preamble_3 == 0)) +.names rx_status_2$_nfb_nfd$true rx_status_2 _nfb rx_status_2$_nfb$raw_n100 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n103<0> +1 +.names _n103<1> +1 +.names _n103<2> +1 +.names _n103<3> +1 +.names _n103<4> +1 +.names _n103<5> +0 +.names _n103<6> +0 +# bit_count_B == 31 +.names bit_count_B<0> _n103<0> _n104<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<1> _n103<1> _n104<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<2> _n103<2> _n104<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<3> _n103<3> _n104<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<4> _n103<4> _n104<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<5> _n103<5> _n104<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<6> _n103<6> _n104<6> +.def 0 +0 1 1 +1 0 1 +.names _n104<0> _n104<1> _n104<2> _n104<3> _n104<4> _n104<5> _n104<6> _n105 +.def 1 +0 0 0 0 0 0 0 0 +.names _n105 _n102 +0 1 +1 0 +.names _n102 _n106 +- =_n102 +# load_B = 1 +.names load_B$_n102_n107$true +1 +# if/else (bit_count_B == 31) +.names load_B$_n102_n107$true load_B _n102 load_B$_n102$raw_n10c +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n111<0> +0 +.names _n111<1> +1 +.names _n111<2> +0 +.names _n111<3> +0 +.names _n111<4> +0 +.names _n111<5> +0 +.names _n111<6> +0 +# bit_count_B == 2 +.names bit_count_B<0> _n111<0> _n112<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<1> _n111<1> _n112<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<2> _n111<2> _n112<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<3> _n111<3> _n112<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<4> _n111<4> _n112<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<5> _n111<5> _n112<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<6> _n111<6> _n112<6> +.def 0 +0 1 1 +1 0 1 +.names _n112<0> _n112<1> _n112<2> _n112<3> _n112<4> _n112<5> _n112<6> _n113 +.def 1 +0 0 0 0 0 0 0 0 +.names _n113 _n110 +0 1 +1 0 +.names _n110 _n114 +- =_n110 +# load_A = 0 +.names load_A$_n110_n115$true +0 +# if/else (bit_count_B == 2) +.names load_A$_n110_n115$true load_A _n110 load_A$_n110$raw_n11c +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# bit_count_B = bit_count_B + 1 +.names _n123<0> +1 +.names _n123<1> +0 +.names _n123<2> +0 +.names _n123<3> +0 +.names _n123<4> +0 +.names _n123<5> +0 +.names _n123<6> +0 +# bit_count_B + 1 +.names _n125 +0 +.names bit_count_B<0> _n123<0> _n125 _n124<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n127 +0 +.names bit_count_B<0> _n123<0> _n127 _n126 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<1> _n123<1> _n126 _n124<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<1> _n123<1> _n126 _n128 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<2> _n123<2> _n128 _n124<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<2> _n123<2> _n128 _n129 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<3> _n123<3> _n129 _n124<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<3> _n123<3> _n129 _n12a +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<4> _n123<4> _n12a _n124<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<4> _n123<4> _n12a _n12b +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<5> _n123<5> _n12b _n124<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<5> _n123<5> _n12b _n12c +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<6> _n123<6> _n12c _n124<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n124<0> bit_count_B$_ne6_n122$true<0> +- =_n124<0> +.names _n124<1> bit_count_B$_ne6_n122$true<1> +- =_n124<1> +.names _n124<2> bit_count_B$_ne6_n122$true<2> +- =_n124<2> +.names _n124<3> bit_count_B$_ne6_n122$true<3> +- =_n124<3> +.names _n124<4> bit_count_B$_ne6_n122$true<4> +- =_n124<4> +.names _n124<5> bit_count_B$_ne6_n122$true<5> +- =_n124<5> +.names _n124<6> bit_count_B$_ne6_n122$true<6> +- =_n124<6> +# pc = 6 +.mv pc$_ne6_n12d$false 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_ne6_n12d$false +L6 +# if/else (bit_count_B < 32) +.names bit_count_B$_ne6_n122$true<0> bit_count_B<0> _ne6 bit_count_B$_ne6$raw_n136<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6_n122$true<1> bit_count_B<1> _ne6 bit_count_B$_ne6$raw_n136<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6_n122$true<2> bit_count_B<2> _ne6 bit_count_B$_ne6$raw_n136<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6_n122$true<3> bit_count_B<3> _ne6 bit_count_B$_ne6$raw_n136<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6_n122$true<4> bit_count_B<4> _ne6 bit_count_B$_ne6$raw_n136<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6_n122$true<5> bit_count_B<5> _ne6 bit_count_B$_ne6$raw_n136<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6_n122$true<6> bit_count_B<6> _ne6 bit_count_B$_ne6$raw_n136<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_A$_n110$raw_n11c load_A _ne6 load_A$_ne6$raw_n13e +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B$_n102$raw_n10c load_B _ne6 load_B$_ne6$raw_n140 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_2$_nfb$raw_n100 rx_status_2 _ne6 rx_status_2$_ne6$raw_n142 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_ne6$raw_n144 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc pc$_ne6_n12d$false _ne6 pc$_ne6$raw_n144 +- - 0 =pc$_ne6_n12d$false +- - 1 =pc +.mv _n147 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n147 +L6 +.names pc _n147 _n146 +.def 0 +- =pc 1 +.names _n146 _n145 +1 1 +0 0 +.names _n148<0> +1 +.names _n148<1> +1 +.names _n148<2> +1 +.names _n148<3> +1 +.names _n148<4> +1 +.names _n148<5> +1 +.names _n148<6> +0 +.names _n148<7> +1 +.names _n148<8> +0 +# frame_counter < 191 +.names _n14b +0 +.names frame_counter<0> _n148<0> _n14b _n14a<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n14d +0 +.names frame_counter<0> _n148<0> _n14d _n14c +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names frame_counter<1> _n148<1> _n14c _n14a<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<1> _n148<1> _n14c _n14e +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names frame_counter<2> _n148<2> _n14e _n14a<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<2> _n148<2> _n14e _n14f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names frame_counter<3> _n148<3> _n14f _n14a<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<3> _n148<3> _n14f _n150 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names frame_counter<4> _n148<4> _n150 _n14a<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<4> _n148<4> _n150 _n151 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names frame_counter<5> _n148<5> _n151 _n14a<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<5> _n148<5> _n151 _n152 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names frame_counter<6> _n148<6> _n152 _n14a<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<6> _n148<6> _n152 _n153 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names frame_counter<7> _n148<7> _n153 _n14a<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<7> _n148<7> _n153 _n154 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names frame_counter<8> _n148<8> _n154 _n14a<8> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<8> _n148<8> _n154 _n155 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n14a<0> _n14a<1> _n14a<2> _n14a<3> _n14a<4> _n14a<5> _n14a<6> _n14a<7> _n14a<8> _n156 +.def 1 +0 0 0 0 0 0 0 0 0 0 +.names _n155 _n156 _n149 +.def 0 +1 1 1 +.names _n149 _n157 +- =_n149 +# bit_count_A = 1 +.names bit_count_A$_n149_n158$true<0> +1 +.names bit_count_A$_n149_n158$true<1> +0 +.names bit_count_A$_n149_n158$true<2> +0 +.names bit_count_A$_n149_n158$true<3> +0 +.names bit_count_A$_n149_n158$true<4> +0 +.names bit_count_A$_n149_n158$true<5> +0 +.names bit_count_A$_n149_n158$true<6> +0 +# pc = 7 +.mv pc$_n149_n159$true 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n149_n159$true +L7 +# pc = 0 +.mv pc$_n149_n15a$false 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n149_n15a$false +L0 +# if/else (frame_counter < 191) +.mv pc$_n149$raw_n15e 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n149_n159$true pc$_n149_n15a$false _n149 pc$_n149$raw_n15e +- - 0 =pc$_n149_n15a$false +- - 1 =pc$_n149_n159$true +.names bit_count_A$_n149_n158$true<0> bit_count_A<0> _n149 bit_count_A$_n149$raw_n15f<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149_n158$true<1> bit_count_A<1> _n149 bit_count_A$_n149$raw_n15f<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149_n158$true<2> bit_count_A<2> _n149 bit_count_A$_n149$raw_n15f<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149_n158$true<3> bit_count_A<3> _n149 bit_count_A$_n149$raw_n15f<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149_n158$true<4> bit_count_A<4> _n149 bit_count_A$_n149$raw_n15f<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149_n158$true<5> bit_count_A<5> _n149 bit_count_A$_n149$raw_n15f<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149_n158$true<6> bit_count_A<6> _n149 bit_count_A$_n149$raw_n15f<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _n16b 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n16b +L7 +.names pc _n16b _n16a +.def 0 +- =pc 1 +.names _n16a _n169 +1 1 +0 0 +.names _n16c<0> +0 +.names _n16c<1> +0 +.names _n16c<2> +0 +.names _n16c<3> +0 +.names _n16c<4> +0 +.names _n16c<5> +1 +.names _n16c<6> +0 +# bit_count_A < 32 +.names _n16f +0 +.names bit_count_A<0> _n16c<0> _n16f _n16e<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n171 +0 +.names bit_count_A<0> _n16c<0> _n171 _n170 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<1> _n16c<1> _n170 _n16e<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<1> _n16c<1> _n170 _n172 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<2> _n16c<2> _n172 _n16e<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<2> _n16c<2> _n172 _n173 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<3> _n16c<3> _n173 _n16e<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<3> _n16c<3> _n173 _n174 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<4> _n16c<4> _n174 _n16e<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<4> _n16c<4> _n174 _n175 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<5> _n16c<5> _n175 _n16e<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<5> _n16c<5> _n175 _n176 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_A<6> _n16c<6> _n176 _n16e<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<6> _n16c<6> _n176 _n177 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n16e<0> _n16e<1> _n16e<2> _n16e<3> _n16e<4> _n16e<5> _n16e<6> _n178 +.def 1 +0 0 0 0 0 0 0 0 +.names _n177 _n178 _n16d +.def 0 +1 1 1 +.names _n16d _n179 +- =_n16d +.names _n17b<0> +0 +.names _n17b<1> +0 +.names _n17b<2> +1 +.names _n17b<3> +0 +.names _n17b<4> +0 +.names _n17b<5> +0 +.names _n17b<6> +0 +# bit_count_A == 4 +.names bit_count_A<0> _n17b<0> _n17c<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<1> _n17b<1> _n17c<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<2> _n17b<2> _n17c<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<3> _n17b<3> _n17c<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<4> _n17b<4> _n17c<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<5> _n17b<5> _n17c<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<6> _n17b<6> _n17c<6> +.def 0 +0 1 1 +1 0 1 +.names _n17c<0> _n17c<1> _n17c<2> _n17c<3> _n17c<4> _n17c<5> _n17c<6> _n17d +.def 1 +0 0 0 0 0 0 0 0 +.names _n17d _n17a +0 1 +1 0 +.names _n17f +0 +# preamble_2 == 0 +.names preamble_2 _n17f _n180 +.def 0 +0 1 1 +1 0 1 +.names _n180 _n17e +0 1 +1 0 +# (bit_count_A == 4) && (preamble_2 == 0) +.names _n17a _n17e _n182 +.def 0 +1 1 1 +.names _n182 _n183 +- =_n182 +# rx_status_2 = 1 +.names rx_status_2$_n182_n184$true +1 +# if/else ((bit_count_A == 4) && (preamble_2 == 0)) +.names rx_status_2$_n182_n184$true rx_status_2 _n182 rx_status_2$_n182$raw_n187 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n18a<0> +1 +.names _n18a<1> +1 +.names _n18a<2> +1 +.names _n18a<3> +1 +.names _n18a<4> +1 +.names _n18a<5> +0 +.names _n18a<6> +0 +# bit_count_A == 31 +.names bit_count_A<0> _n18a<0> _n18b<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<1> _n18a<1> _n18b<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<2> _n18a<2> _n18b<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<3> _n18a<3> _n18b<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<4> _n18a<4> _n18b<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<5> _n18a<5> _n18b<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<6> _n18a<6> _n18b<6> +.def 0 +0 1 1 +1 0 1 +.names _n18b<0> _n18b<1> _n18b<2> _n18b<3> _n18b<4> _n18b<5> _n18b<6> _n18c +.def 1 +0 0 0 0 0 0 0 0 +.names _n18c _n189 +0 1 +1 0 +.names _n189 _n18d +- =_n189 +# load_A = 1 +.names load_A$_n189_n18e$true +1 +# if/else (bit_count_A == 31) +.names load_A$_n189_n18e$true load_A _n189 load_A$_n189$raw_n193 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n198<0> +0 +.names _n198<1> +1 +.names _n198<2> +0 +.names _n198<3> +0 +.names _n198<4> +0 +.names _n198<5> +0 +.names _n198<6> +0 +# bit_count_A == 2 +.names bit_count_A<0> _n198<0> _n199<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<1> _n198<1> _n199<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<2> _n198<2> _n199<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<3> _n198<3> _n199<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<4> _n198<4> _n199<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<5> _n198<5> _n199<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<6> _n198<6> _n199<6> +.def 0 +0 1 1 +1 0 1 +.names _n199<0> _n199<1> _n199<2> _n199<3> _n199<4> _n199<5> _n199<6> _n19a +.def 1 +0 0 0 0 0 0 0 0 +.names _n19a _n197 +0 1 +1 0 +.names _n197 _n19b +- =_n197 +# load_B = 0 +.names load_B$_n197_n19c$true +0 +# if/else (bit_count_A == 2) +.names load_B$_n197_n19c$true load_B _n197 load_B$_n197$raw_n1a4 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1aa<0> +1 +.names _n1aa<1> +1 +.names _n1aa<2> +0 +.names _n1aa<3> +0 +.names _n1aa<4> +0 +.names _n1aa<5> +0 +.names _n1aa<6> +0 +# bit_count_A == 3 +.names bit_count_A<0> _n1aa<0> _n1ab<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<1> _n1aa<1> _n1ab<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<2> _n1aa<2> _n1ab<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<3> _n1aa<3> _n1ab<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<4> _n1aa<4> _n1ab<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<5> _n1aa<5> _n1ab<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<6> _n1aa<6> _n1ab<6> +.def 0 +0 1 1 +1 0 1 +.names _n1ab<0> _n1ab<1> _n1ab<2> _n1ab<3> _n1ab<4> _n1ab<5> _n1ab<6> _n1ac +.def 1 +0 0 0 0 0 0 0 0 +.names _n1ac _n1a9 +0 1 +1 0 +.names _n1a9 _n1ad +- =_n1a9 +.names _n1af<0> +0 +.names _n1af<1> +0 +# frame_counter [1 : 0] == 0 +.names frame_counter<0> _n1af<0> _n1b0<0> +.def 0 +0 1 1 +1 0 1 +.names frame_counter<1> _n1af<1> _n1b0<1> +.def 0 +0 1 1 +1 0 1 +.names _n1b0<0> _n1b0<1> _n1b1 +.def 1 +0 0 0 +.names _n1b1 _n1ae +0 1 +1 0 +.names _n1ae _n1b2 +- =_n1ae +# load_buff = 1 +.names load_buff$_n1ae_n1b3$true +1 +# if/else (frame_counter [1 : 0] == 0) +.names load_buff$_n1ae_n1b3$true load_buff _n1ae load_buff$_n1ae$raw_n1bc +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (bit_count_A == 3) +.names load_buff$_n1ae$raw_n1bc load_buff _n1a9 load_buff$_n1a9$raw_n1cc +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1d5<0> +1 +.names _n1d5<1> +0 +.names _n1d5<2> +1 +.names _n1d5<3> +0 +.names _n1d5<4> +0 +.names _n1d5<5> +0 +.names _n1d5<6> +0 +# bit_count_A == 5 +.names bit_count_A<0> _n1d5<0> _n1d6<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<1> _n1d5<1> _n1d6<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<2> _n1d5<2> _n1d6<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<3> _n1d5<3> _n1d6<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<4> _n1d5<4> _n1d6<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<5> _n1d5<5> _n1d6<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_A<6> _n1d5<6> _n1d6<6> +.def 0 +0 1 1 +1 0 1 +.names _n1d6<0> _n1d6<1> _n1d6<2> _n1d6<3> _n1d6<4> _n1d6<5> _n1d6<6> _n1d7 +.def 1 +0 0 0 0 0 0 0 0 +.names _n1d7 _n1d4 +0 1 +1 0 +.names _n1d4 _n1d8 +- =_n1d4 +# load_buff = 0 +.names load_buff$_n1d4_n1d9$true +0 +# if/else (bit_count_A == 5) +.names load_buff$_n1d4_n1d9$true load_buff$_n1a9$raw_n1cc _n1d4 load_buff$_n1d4$raw_n1da +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# bit_count_A = bit_count_A + 1 +.names _n1ec<0> +1 +.names _n1ec<1> +0 +.names _n1ec<2> +0 +.names _n1ec<3> +0 +.names _n1ec<4> +0 +.names _n1ec<5> +0 +.names _n1ec<6> +0 +# bit_count_A + 1 +.names _n1ee +0 +.names bit_count_A<0> _n1ec<0> _n1ee _n1ed<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n1f0 +0 +.names bit_count_A<0> _n1ec<0> _n1f0 _n1ef +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<1> _n1ec<1> _n1ef _n1ed<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<1> _n1ec<1> _n1ef _n1f1 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<2> _n1ec<2> _n1f1 _n1ed<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<2> _n1ec<2> _n1f1 _n1f2 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<3> _n1ec<3> _n1f2 _n1ed<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<3> _n1ec<3> _n1f2 _n1f3 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<4> _n1ec<4> _n1f3 _n1ed<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<4> _n1ec<4> _n1f3 _n1f4 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<5> _n1ec<5> _n1f4 _n1ed<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_A<5> _n1ec<5> _n1f4 _n1f5 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_A<6> _n1ec<6> _n1f5 _n1ed<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n1ed<0> bit_count_A$_n16d_n1eb$true<0> +- =_n1ed<0> +.names _n1ed<1> bit_count_A$_n16d_n1eb$true<1> +- =_n1ed<1> +.names _n1ed<2> bit_count_A$_n16d_n1eb$true<2> +- =_n1ed<2> +.names _n1ed<3> bit_count_A$_n16d_n1eb$true<3> +- =_n1ed<3> +.names _n1ed<4> bit_count_A$_n16d_n1eb$true<4> +- =_n1ed<4> +.names _n1ed<5> bit_count_A$_n16d_n1eb$true<5> +- =_n1ed<5> +.names _n1ed<6> bit_count_A$_n16d_n1eb$true<6> +- =_n1ed<6> +# pc = 8 +.mv pc$_n16d_n1f6$false 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n16d_n1f6$false +L8 +# if/else (bit_count_A < 32) +.names load_buff$_n1d4$raw_n1da load_buff _n16d load_buff$_n16d$raw_n201 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d_n1eb$true<0> bit_count_A<0> _n16d bit_count_A$_n16d$raw_n203<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d_n1eb$true<1> bit_count_A<1> _n16d bit_count_A$_n16d$raw_n203<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d_n1eb$true<2> bit_count_A<2> _n16d bit_count_A$_n16d$raw_n203<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d_n1eb$true<3> bit_count_A<3> _n16d bit_count_A$_n16d$raw_n203<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d_n1eb$true<4> bit_count_A<4> _n16d bit_count_A$_n16d$raw_n203<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d_n1eb$true<5> bit_count_A<5> _n16d bit_count_A$_n16d$raw_n203<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d_n1eb$true<6> bit_count_A<6> _n16d bit_count_A$_n16d$raw_n203<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_A$_n189$raw_n193 load_A _n16d load_A$_n16d$raw_n20b +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B$_n197$raw_n1a4 load_B _n16d load_B$_n16d$raw_n20d +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_2$_n182$raw_n187 rx_status_2 _n16d rx_status_2$_n16d$raw_n20f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n16d$raw_n211 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc pc$_n16d_n1f6$false _n16d pc$_n16d$raw_n211 +- - 0 =pc$_n16d_n1f6$false +- - 1 =pc +.mv _n214 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n214 +L8 +.names pc _n214 _n213 +.def 0 +- =pc 1 +.names _n213 _n212 +1 1 +0 0 +# bit_count_B = 1 +.names bit_count_B$_n212_n215$true<0> +1 +.names bit_count_B$_n212_n215$true<1> +0 +.names bit_count_B$_n212_n215$true<2> +0 +.names bit_count_B$_n212_n215$true<3> +0 +.names bit_count_B$_n212_n215$true<4> +0 +.names bit_count_B$_n212_n215$true<5> +0 +.names bit_count_B$_n212_n215$true<6> +0 +# pc = 9 +.mv pc$_n212_n216$true 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n212_n216$true +L9 +.mv _n219 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n219 +L9 +.names pc _n219 _n218 +.def 0 +- =pc 1 +.names _n218 _n217 +1 1 +0 0 +.names _n21a<0> +0 +.names _n21a<1> +0 +.names _n21a<2> +0 +.names _n21a<3> +0 +.names _n21a<4> +0 +.names _n21a<5> +1 +.names _n21a<6> +0 +# bit_count_B < 32 +.names _n21d +0 +.names bit_count_B<0> _n21a<0> _n21d _n21c<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n21f +0 +.names bit_count_B<0> _n21a<0> _n21f _n21e +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<1> _n21a<1> _n21e _n21c<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<1> _n21a<1> _n21e _n220 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<2> _n21a<2> _n220 _n21c<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<2> _n21a<2> _n220 _n221 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<3> _n21a<3> _n221 _n21c<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<3> _n21a<3> _n221 _n222 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<4> _n21a<4> _n222 _n21c<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<4> _n21a<4> _n222 _n223 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<5> _n21a<5> _n223 _n21c<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<5> _n21a<5> _n223 _n224 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names bit_count_B<6> _n21a<6> _n224 _n21c<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<6> _n21a<6> _n224 _n225 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n21c<0> _n21c<1> _n21c<2> _n21c<3> _n21c<4> _n21c<5> _n21c<6> _n226 +.def 1 +0 0 0 0 0 0 0 0 +.names _n225 _n226 _n21b +.def 0 +1 1 1 +.names _n21b _n227 +- =_n21b +.names _n229<0> +0 +.names _n229<1> +0 +.names _n229<2> +1 +.names _n229<3> +0 +.names _n229<4> +0 +.names _n229<5> +0 +.names _n229<6> +0 +# bit_count_B == 4 +.names bit_count_B<0> _n229<0> _n22a<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<1> _n229<1> _n22a<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<2> _n229<2> _n22a<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<3> _n229<3> _n22a<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<4> _n229<4> _n22a<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<5> _n229<5> _n22a<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<6> _n229<6> _n22a<6> +.def 0 +0 1 1 +1 0 1 +.names _n22a<0> _n22a<1> _n22a<2> _n22a<3> _n22a<4> _n22a<5> _n22a<6> _n22b +.def 1 +0 0 0 0 0 0 0 0 +.names _n22b _n228 +0 1 +1 0 +.names _n22d +0 +# preamble_3 == 0 +.names preamble_3 _n22d _n22e +.def 0 +0 1 1 +1 0 1 +.names _n22e _n22c +0 1 +1 0 +# (bit_count_B == 4) && (preamble_3 == 0) +.names _n228 _n22c _n230 +.def 0 +1 1 1 +.names _n230 _n231 +- =_n230 +# rx_status_2 = 1 +.names rx_status_2$_n230_n232$true +1 +# if/else ((bit_count_B == 4) && (preamble_3 == 0)) +.names rx_status_2$_n230_n232$true rx_status_2 _n230 rx_status_2$_n230$raw_n235 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n238<0> +1 +.names _n238<1> +1 +.names _n238<2> +1 +.names _n238<3> +1 +.names _n238<4> +1 +.names _n238<5> +0 +.names _n238<6> +0 +# bit_count_B == 31 +.names bit_count_B<0> _n238<0> _n239<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<1> _n238<1> _n239<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<2> _n238<2> _n239<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<3> _n238<3> _n239<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<4> _n238<4> _n239<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<5> _n238<5> _n239<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<6> _n238<6> _n239<6> +.def 0 +0 1 1 +1 0 1 +.names _n239<0> _n239<1> _n239<2> _n239<3> _n239<4> _n239<5> _n239<6> _n23a +.def 1 +0 0 0 0 0 0 0 0 +.names _n23a _n237 +0 1 +1 0 +.names _n237 _n23b +- =_n237 +# load_B = 1 +.names load_B$_n237_n23c$true +1 +# if/else (bit_count_B == 31) +.names load_B$_n237_n23c$true load_B _n237 load_B$_n237$raw_n241 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n246<0> +0 +.names _n246<1> +1 +.names _n246<2> +0 +.names _n246<3> +0 +.names _n246<4> +0 +.names _n246<5> +0 +.names _n246<6> +0 +# bit_count_B == 2 +.names bit_count_B<0> _n246<0> _n247<0> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<1> _n246<1> _n247<1> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<2> _n246<2> _n247<2> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<3> _n246<3> _n247<3> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<4> _n246<4> _n247<4> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<5> _n246<5> _n247<5> +.def 0 +0 1 1 +1 0 1 +.names bit_count_B<6> _n246<6> _n247<6> +.def 0 +0 1 1 +1 0 1 +.names _n247<0> _n247<1> _n247<2> _n247<3> _n247<4> _n247<5> _n247<6> _n248 +.def 1 +0 0 0 0 0 0 0 0 +.names _n248 _n245 +0 1 +1 0 +.names _n245 _n249 +- =_n245 +# load_A = 0 +.names load_A$_n245_n24a$true +0 +# if/else (bit_count_B == 2) +.names load_A$_n245_n24a$true load_A _n245 load_A$_n245$raw_n251 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# bit_count_B = bit_count_B + 1 +.names _n258<0> +1 +.names _n258<1> +0 +.names _n258<2> +0 +.names _n258<3> +0 +.names _n258<4> +0 +.names _n258<5> +0 +.names _n258<6> +0 +# bit_count_B + 1 +.names _n25a +0 +.names bit_count_B<0> _n258<0> _n25a _n259<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n25c +0 +.names bit_count_B<0> _n258<0> _n25c _n25b +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<1> _n258<1> _n25b _n259<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<1> _n258<1> _n25b _n25d +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<2> _n258<2> _n25d _n259<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<2> _n258<2> _n25d _n25e +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<3> _n258<3> _n25e _n259<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<3> _n258<3> _n25e _n25f +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<4> _n258<4> _n25f _n259<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<4> _n258<4> _n25f _n260 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<5> _n258<5> _n260 _n259<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names bit_count_B<5> _n258<5> _n260 _n261 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names bit_count_B<6> _n258<6> _n261 _n259<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n259<0> bit_count_B$_n21b_n257$true<0> +- =_n259<0> +.names _n259<1> bit_count_B$_n21b_n257$true<1> +- =_n259<1> +.names _n259<2> bit_count_B$_n21b_n257$true<2> +- =_n259<2> +.names _n259<3> bit_count_B$_n21b_n257$true<3> +- =_n259<3> +.names _n259<4> bit_count_B$_n21b_n257$true<4> +- =_n259<4> +.names _n259<5> bit_count_B$_n21b_n257$true<5> +- =_n259<5> +.names _n259<6> bit_count_B$_n21b_n257$true<6> +- =_n259<6> +# pc = 10 +.mv pc$_n21b_n262$false 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n21b_n262$false +L10 +# if/else (bit_count_B < 32) +.names bit_count_B$_n21b_n257$true<0> bit_count_B<0> _n21b bit_count_B$_n21b$raw_n26b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b_n257$true<1> bit_count_B<1> _n21b bit_count_B$_n21b$raw_n26b<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b_n257$true<2> bit_count_B<2> _n21b bit_count_B$_n21b$raw_n26b<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b_n257$true<3> bit_count_B<3> _n21b bit_count_B$_n21b$raw_n26b<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b_n257$true<4> bit_count_B<4> _n21b bit_count_B$_n21b$raw_n26b<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b_n257$true<5> bit_count_B<5> _n21b bit_count_B$_n21b$raw_n26b<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b_n257$true<6> bit_count_B<6> _n21b bit_count_B$_n21b$raw_n26b<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_A$_n245$raw_n251 load_A _n21b load_A$_n21b$raw_n273 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B$_n237$raw_n241 load_B _n21b load_B$_n21b$raw_n275 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_2$_n230$raw_n235 rx_status_2 _n21b rx_status_2$_n21b$raw_n277 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n21b$raw_n279 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc pc$_n21b_n262$false _n21b pc$_n21b$raw_n279 +- - 0 =pc$_n21b_n262$false +- - 1 =pc +.mv _n27c 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n27c +L10 +.names pc _n27c _n27b +.def 0 +- =pc 1 +.names _n27b _n27a +1 1 +0 0 +# frame_counter = frame_counter + 1 +.names _n27e<0> +1 +.names _n27e<1> +0 +.names _n27e<2> +0 +.names _n27e<3> +0 +.names _n27e<4> +0 +.names _n27e<5> +0 +.names _n27e<6> +0 +.names _n27e<7> +0 +.names _n27e<8> +0 +# frame_counter + 1 +.names _n280 +0 +.names frame_counter<0> _n27e<0> _n280 _n27f<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n282 +0 +.names frame_counter<0> _n27e<0> _n282 _n281 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names frame_counter<1> _n27e<1> _n281 _n27f<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<1> _n27e<1> _n281 _n283 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names frame_counter<2> _n27e<2> _n283 _n27f<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<2> _n27e<2> _n283 _n284 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names frame_counter<3> _n27e<3> _n284 _n27f<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<3> _n27e<3> _n284 _n285 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names frame_counter<4> _n27e<4> _n285 _n27f<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<4> _n27e<4> _n285 _n286 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names frame_counter<5> _n27e<5> _n286 _n27f<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<5> _n27e<5> _n286 _n287 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names frame_counter<6> _n27e<6> _n287 _n27f<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<6> _n27e<6> _n287 _n288 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names frame_counter<7> _n27e<7> _n288 _n27f<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names frame_counter<7> _n27e<7> _n288 _n289 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names frame_counter<8> _n27e<8> _n289 _n27f<8> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n27f<0> frame_counter$_n27a_n27d$true<0> +- =_n27f<0> +.names _n27f<1> frame_counter$_n27a_n27d$true<1> +- =_n27f<1> +.names _n27f<2> frame_counter$_n27a_n27d$true<2> +- =_n27f<2> +.names _n27f<3> frame_counter$_n27a_n27d$true<3> +- =_n27f<3> +.names _n27f<4> frame_counter$_n27a_n27d$true<4> +- =_n27f<4> +.names _n27f<5> frame_counter$_n27a_n27d$true<5> +- =_n27f<5> +.names _n27f<6> frame_counter$_n27a_n27d$true<6> +- =_n27f<6> +.names _n27f<7> frame_counter$_n27a_n27d$true<7> +- =_n27f<7> +.names _n27f<8> frame_counter$_n27a_n27d$true<8> +- =_n27f<8> +# pc = 6 +.mv pc$_n27a_n28a$true 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n27a_n28a$true +L6 +# case (pc ) +.mv pc$_n27a$raw_n28f 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n27a_n28a$true pc _n27a pc$_n27a$raw_n28f +- - 0 =pc +- - 1 =pc$_n27a_n28a$true +.names frame_counter$_n27a_n27d$true<0> frame_counter<0> _n27a frame_counter$_n27a$raw_n290<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$_n27a_n27d$true<1> frame_counter<1> _n27a frame_counter$_n27a$raw_n290<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$_n27a_n27d$true<2> frame_counter<2> _n27a frame_counter$_n27a$raw_n290<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$_n27a_n27d$true<3> frame_counter<3> _n27a frame_counter$_n27a$raw_n290<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$_n27a_n27d$true<4> frame_counter<4> _n27a frame_counter$_n27a$raw_n290<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$_n27a_n27d$true<5> frame_counter<5> _n27a frame_counter$_n27a$raw_n290<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$_n27a_n27d$true<6> frame_counter<6> _n27a frame_counter$_n27a$raw_n290<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$_n27a_n27d$true<7> frame_counter<7> _n27a frame_counter$_n27a$raw_n290<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$_n27a_n27d$true<8> frame_counter<8> _n27a frame_counter$_n27a$raw_n290<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n217$raw_n29b 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n21b$raw_n279 pc$_n27a$raw_n28f _n217 pc$_n217$raw_n29b +- - 0 =pc$_n27a$raw_n28f +- - 1 =pc$_n21b$raw_n279 +.names bit_count_B$_n21b$raw_n26b<0> bit_count_B<0> _n217 bit_count_B$_n217$raw_n2a4<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b$raw_n26b<1> bit_count_B<1> _n217 bit_count_B$_n217$raw_n2a4<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b$raw_n26b<2> bit_count_B<2> _n217 bit_count_B$_n217$raw_n2a4<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b$raw_n26b<3> bit_count_B<3> _n217 bit_count_B$_n217$raw_n2a4<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b$raw_n26b<4> bit_count_B<4> _n217 bit_count_B$_n217$raw_n2a4<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b$raw_n26b<5> bit_count_B<5> _n217 bit_count_B$_n217$raw_n2a4<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n21b$raw_n26b<6> bit_count_B<6> _n217 bit_count_B$_n217$raw_n2a4<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_A$_n21b$raw_n273 load_A _n217 load_A$_n217$raw_n2ad +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_2$_n21b$raw_n277 rx_status_2 _n217 rx_status_2$_n217$raw_n2af +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B$_n21b$raw_n275 load_B _n217 load_B$_n217$raw_n2b1 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<0> frame_counter$_n27a$raw_n290<0> _n217 frame_counter$_n217$raw_n2b4<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<1> frame_counter$_n27a$raw_n290<1> _n217 frame_counter$_n217$raw_n2b4<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<2> frame_counter$_n27a$raw_n290<2> _n217 frame_counter$_n217$raw_n2b4<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<3> frame_counter$_n27a$raw_n290<3> _n217 frame_counter$_n217$raw_n2b4<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<4> frame_counter$_n27a$raw_n290<4> _n217 frame_counter$_n217$raw_n2b4<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<5> frame_counter$_n27a$raw_n290<5> _n217 frame_counter$_n217$raw_n2b4<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<6> frame_counter$_n27a$raw_n290<6> _n217 frame_counter$_n217$raw_n2b4<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<7> frame_counter$_n27a$raw_n290<7> _n217 frame_counter$_n217$raw_n2b4<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<8> frame_counter$_n27a$raw_n290<8> _n217 frame_counter$_n217$raw_n2b4<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n212_n215$true<0> bit_count_B$_n217$raw_n2a4<0> _n212 bit_count_B$_n212$raw_n2be<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n212_n215$true<1> bit_count_B$_n217$raw_n2a4<1> _n212 bit_count_B$_n212$raw_n2be<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n212_n215$true<2> bit_count_B$_n217$raw_n2a4<2> _n212 bit_count_B$_n212$raw_n2be<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n212_n215$true<3> bit_count_B$_n217$raw_n2a4<3> _n212 bit_count_B$_n212$raw_n2be<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n212_n215$true<4> bit_count_B$_n217$raw_n2a4<4> _n212 bit_count_B$_n212$raw_n2be<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n212_n215$true<5> bit_count_B$_n217$raw_n2a4<5> _n212 bit_count_B$_n212$raw_n2be<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_n212_n215$true<6> bit_count_B$_n217$raw_n2a4<6> _n212 bit_count_B$_n212$raw_n2be<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n212$raw_n2c6 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n212_n216$true pc$_n217$raw_n29b _n212 pc$_n212$raw_n2c6 +- - 0 =pc$_n217$raw_n29b +- - 1 =pc$_n212_n216$true +.names frame_counter<0> frame_counter$_n217$raw_n2b4<0> _n212 frame_counter$_n212$raw_n2cd<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<1> frame_counter$_n217$raw_n2b4<1> _n212 frame_counter$_n212$raw_n2cd<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<2> frame_counter$_n217$raw_n2b4<2> _n212 frame_counter$_n212$raw_n2cd<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<3> frame_counter$_n217$raw_n2b4<3> _n212 frame_counter$_n212$raw_n2cd<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<4> frame_counter$_n217$raw_n2b4<4> _n212 frame_counter$_n212$raw_n2cd<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<5> frame_counter$_n217$raw_n2b4<5> _n212 frame_counter$_n212$raw_n2cd<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<6> frame_counter$_n217$raw_n2b4<6> _n212 frame_counter$_n212$raw_n2cd<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<7> frame_counter$_n217$raw_n2b4<7> _n212 frame_counter$_n212$raw_n2cd<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<8> frame_counter$_n217$raw_n2b4<8> _n212 frame_counter$_n212$raw_n2cd<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_A load_A$_n217$raw_n2ad _n212 load_A$_n212$raw_n2d7 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_2 rx_status_2$_n217$raw_n2af _n212 rx_status_2$_n212$raw_n2d9 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B load_B$_n217$raw_n2b1 _n212 load_B$_n212$raw_n2db +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n169$raw_n2df 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n16d$raw_n211 pc$_n212$raw_n2c6 _n169 pc$_n169$raw_n2df +- - 0 =pc$_n212$raw_n2c6 +- - 1 =pc$_n16d$raw_n211 +.names load_A$_n16d$raw_n20b load_A$_n212$raw_n2d7 _n169 load_A$_n169$raw_n2e0 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_2$_n16d$raw_n20f rx_status_2$_n212$raw_n2d9 _n169 rx_status_2$_n169$raw_n2e2 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B$_n16d$raw_n20d load_B$_n212$raw_n2db _n169 load_B$_n169$raw_n2e4 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_buff$_n16d$raw_n201 load_buff _n169 load_buff$_n169$raw_n2ec +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d$raw_n203<0> bit_count_A<0> _n169 bit_count_A$_n169$raw_n2ee<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d$raw_n203<1> bit_count_A<1> _n169 bit_count_A$_n169$raw_n2ee<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d$raw_n203<2> bit_count_A<2> _n169 bit_count_A$_n169$raw_n2ee<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d$raw_n203<3> bit_count_A<3> _n169 bit_count_A$_n169$raw_n2ee<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d$raw_n203<4> bit_count_A<4> _n169 bit_count_A$_n169$raw_n2ee<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d$raw_n203<5> bit_count_A<5> _n169 bit_count_A$_n169$raw_n2ee<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n16d$raw_n203<6> bit_count_A<6> _n169 bit_count_A$_n169$raw_n2ee<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<0> bit_count_B$_n212$raw_n2be<0> _n169 bit_count_B$_n169$raw_n2fa<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<1> bit_count_B$_n212$raw_n2be<1> _n169 bit_count_B$_n169$raw_n2fa<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<2> bit_count_B$_n212$raw_n2be<2> _n169 bit_count_B$_n169$raw_n2fa<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<3> bit_count_B$_n212$raw_n2be<3> _n169 bit_count_B$_n169$raw_n2fa<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<4> bit_count_B$_n212$raw_n2be<4> _n169 bit_count_B$_n169$raw_n2fa<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<5> bit_count_B$_n212$raw_n2be<5> _n169 bit_count_B$_n169$raw_n2fa<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<6> bit_count_B$_n212$raw_n2be<6> _n169 bit_count_B$_n169$raw_n2fa<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<0> frame_counter$_n212$raw_n2cd<0> _n169 frame_counter$_n169$raw_n303<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<1> frame_counter$_n212$raw_n2cd<1> _n169 frame_counter$_n169$raw_n303<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<2> frame_counter$_n212$raw_n2cd<2> _n169 frame_counter$_n169$raw_n303<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<3> frame_counter$_n212$raw_n2cd<3> _n169 frame_counter$_n169$raw_n303<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<4> frame_counter$_n212$raw_n2cd<4> _n169 frame_counter$_n169$raw_n303<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<5> frame_counter$_n212$raw_n2cd<5> _n169 frame_counter$_n169$raw_n303<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<6> frame_counter$_n212$raw_n2cd<6> _n169 frame_counter$_n169$raw_n303<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<7> frame_counter$_n212$raw_n2cd<7> _n169 frame_counter$_n169$raw_n303<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<8> frame_counter$_n212$raw_n2cd<8> _n169 frame_counter$_n169$raw_n303<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149$raw_n15f<0> bit_count_A$_n169$raw_n2ee<0> _n145 bit_count_A$_n145$raw_n310<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149$raw_n15f<1> bit_count_A$_n169$raw_n2ee<1> _n145 bit_count_A$_n145$raw_n310<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149$raw_n15f<2> bit_count_A$_n169$raw_n2ee<2> _n145 bit_count_A$_n145$raw_n310<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149$raw_n15f<3> bit_count_A$_n169$raw_n2ee<3> _n145 bit_count_A$_n145$raw_n310<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149$raw_n15f<4> bit_count_A$_n169$raw_n2ee<4> _n145 bit_count_A$_n145$raw_n310<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149$raw_n15f<5> bit_count_A$_n169$raw_n2ee<5> _n145 bit_count_A$_n145$raw_n310<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$_n149$raw_n15f<6> bit_count_A$_n169$raw_n2ee<6> _n145 bit_count_A$_n145$raw_n310<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n145$raw_n318 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n149$raw_n15e pc$_n169$raw_n2df _n145 pc$_n145$raw_n318 +- - 0 =pc$_n169$raw_n2df +- - 1 =pc$_n149$raw_n15e +.names load_buff load_buff$_n169$raw_n2ec _n145 load_buff$_n145$raw_n31d +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<0> bit_count_B$_n169$raw_n2fa<0> _n145 bit_count_B$_n145$raw_n320<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<1> bit_count_B$_n169$raw_n2fa<1> _n145 bit_count_B$_n145$raw_n320<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<2> bit_count_B$_n169$raw_n2fa<2> _n145 bit_count_B$_n145$raw_n320<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<3> bit_count_B$_n169$raw_n2fa<3> _n145 bit_count_B$_n145$raw_n320<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<4> bit_count_B$_n169$raw_n2fa<4> _n145 bit_count_B$_n145$raw_n320<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<5> bit_count_B$_n169$raw_n2fa<5> _n145 bit_count_B$_n145$raw_n320<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<6> bit_count_B$_n169$raw_n2fa<6> _n145 bit_count_B$_n145$raw_n320<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<0> frame_counter$_n169$raw_n303<0> _n145 frame_counter$_n145$raw_n329<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<1> frame_counter$_n169$raw_n303<1> _n145 frame_counter$_n145$raw_n329<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<2> frame_counter$_n169$raw_n303<2> _n145 frame_counter$_n145$raw_n329<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<3> frame_counter$_n169$raw_n303<3> _n145 frame_counter$_n145$raw_n329<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<4> frame_counter$_n169$raw_n303<4> _n145 frame_counter$_n145$raw_n329<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<5> frame_counter$_n169$raw_n303<5> _n145 frame_counter$_n145$raw_n329<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<6> frame_counter$_n169$raw_n303<6> _n145 frame_counter$_n145$raw_n329<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<7> frame_counter$_n169$raw_n303<7> _n145 frame_counter$_n145$raw_n329<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<8> frame_counter$_n169$raw_n303<8> _n145 frame_counter$_n145$raw_n329<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_A load_A$_n169$raw_n2e0 _n145 load_A$_n145$raw_n333 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_2 rx_status_2$_n169$raw_n2e2 _n145 rx_status_2$_n145$raw_n335 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B load_B$_n169$raw_n2e4 _n145 load_B$_n145$raw_n337 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6$raw_n136<0> bit_count_B$_n145$raw_n320<0> _ne2 bit_count_B$_ne2$raw_n339<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6$raw_n136<1> bit_count_B$_n145$raw_n320<1> _ne2 bit_count_B$_ne2$raw_n339<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6$raw_n136<2> bit_count_B$_n145$raw_n320<2> _ne2 bit_count_B$_ne2$raw_n339<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6$raw_n136<3> bit_count_B$_n145$raw_n320<3> _ne2 bit_count_B$_ne2$raw_n339<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6$raw_n136<4> bit_count_B$_n145$raw_n320<4> _ne2 bit_count_B$_ne2$raw_n339<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$_ne6$raw_n136<5> bit_count_B$_n145$raw_n320<5> _ne2 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+.names bit_count_A$preamble_1$raw_n62<6> bit_count_A$_n6b$raw_n399<6> _n58 bit_count_A$_n58$raw_n3c9<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n58$raw_n3d1 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$preamble_1$raw_n6a pc$_n6b$raw_n3a1 _n58 pc$_n58$raw_n3d1 +- - 0 =pc$_n6b$raw_n3a1 +- - 1 =pc$preamble_1$raw_n6a +.names load_buff load_buff$_n6b$raw_n397 _n58 load_buff$_n58$raw_n3d6 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<0> bit_count_B$_n6b$raw_n3b2<0> _n58 bit_count_B$_n58$raw_n3d9<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<1> bit_count_B$_n6b$raw_n3b2<1> _n58 bit_count_B$_n58$raw_n3d9<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<2> bit_count_B$_n6b$raw_n3b2<2> _n58 bit_count_B$_n58$raw_n3d9<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<3> bit_count_B$_n6b$raw_n3b2<3> _n58 bit_count_B$_n58$raw_n3d9<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<4> bit_count_B$_n6b$raw_n3b2<4> _n58 bit_count_B$_n58$raw_n3d9<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<5> bit_count_B$_n6b$raw_n3b2<5> _n58 bit_count_B$_n58$raw_n3d9<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<6> bit_count_B$_n6b$raw_n3b2<6> _n58 bit_count_B$_n58$raw_n3d9<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<0> frame_counter$_n6b$raw_n3bb<0> _n58 frame_counter$_n58$raw_n3e2<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<1> frame_counter$_n6b$raw_n3bb<1> _n58 frame_counter$_n58$raw_n3e2<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<2> frame_counter$_n6b$raw_n3bb<2> _n58 frame_counter$_n58$raw_n3e2<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<3> frame_counter$_n6b$raw_n3bb<3> _n58 frame_counter$_n58$raw_n3e2<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<4> frame_counter$_n6b$raw_n3bb<4> _n58 frame_counter$_n58$raw_n3e2<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<5> frame_counter$_n6b$raw_n3bb<5> _n58 frame_counter$_n58$raw_n3e2<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<6> frame_counter$_n6b$raw_n3bb<6> _n58 frame_counter$_n58$raw_n3e2<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<7> frame_counter$_n6b$raw_n3bb<7> _n58 frame_counter$_n58$raw_n3e2<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<8> frame_counter$_n6b$raw_n3bb<8> _n58 frame_counter$_n58$raw_n3e2<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_A load_A$_n6b$raw_n3a2 _n58 load_A$_n58$raw_n3ec +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_2 rx_status_2$_n6b$raw_n3c6 _n58 rx_status_2$_n58$raw_n3ee +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B load_B$_n6b$raw_n3a4 _n58 load_B$_n58$raw_n3f0 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n29$raw_n3f3 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$_n29_n57$true pc$_n58$raw_n3d1 _n29 pc$_n29$raw_n3f3 +- - 0 =pc$_n58$raw_n3d1 +- - 1 =pc$_n29_n57$true +.names clock_out$_n2c$raw_n52 clock_out _n29 clock_out$_n29$raw_n3f6 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_buff load_buff$_n58$raw_n3d6 _n29 load_buff$_n29$raw_n3f9 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<0> bit_count_A$_n58$raw_n3c9<0> _n29 bit_count_A$_n29$raw_n3fb<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<1> bit_count_A$_n58$raw_n3c9<1> _n29 bit_count_A$_n29$raw_n3fb<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<2> bit_count_A$_n58$raw_n3c9<2> _n29 bit_count_A$_n29$raw_n3fb<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<3> bit_count_A$_n58$raw_n3c9<3> _n29 bit_count_A$_n29$raw_n3fb<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<4> bit_count_A$_n58$raw_n3c9<4> _n29 bit_count_A$_n29$raw_n3fb<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<5> bit_count_A$_n58$raw_n3c9<5> _n29 bit_count_A$_n29$raw_n3fb<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<6> bit_count_A$_n58$raw_n3c9<6> _n29 bit_count_A$_n29$raw_n3fb<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<0> bit_count_B$_n58$raw_n3d9<0> _n29 bit_count_B$_n29$raw_n403<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<1> bit_count_B$_n58$raw_n3d9<1> _n29 bit_count_B$_n29$raw_n403<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<2> bit_count_B$_n58$raw_n3d9<2> _n29 bit_count_B$_n29$raw_n403<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<3> bit_count_B$_n58$raw_n3d9<3> _n29 bit_count_B$_n29$raw_n403<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<4> bit_count_B$_n58$raw_n3d9<4> _n29 bit_count_B$_n29$raw_n403<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<5> bit_count_B$_n58$raw_n3d9<5> _n29 bit_count_B$_n29$raw_n403<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<6> bit_count_B$_n58$raw_n3d9<6> _n29 bit_count_B$_n29$raw_n403<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<0> frame_counter$_n58$raw_n3e2<0> _n29 frame_counter$_n29$raw_n40c<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<1> frame_counter$_n58$raw_n3e2<1> _n29 frame_counter$_n29$raw_n40c<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<2> frame_counter$_n58$raw_n3e2<2> _n29 frame_counter$_n29$raw_n40c<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<3> frame_counter$_n58$raw_n3e2<3> _n29 frame_counter$_n29$raw_n40c<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<4> frame_counter$_n58$raw_n3e2<4> _n29 frame_counter$_n29$raw_n40c<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<5> frame_counter$_n58$raw_n3e2<5> _n29 frame_counter$_n29$raw_n40c<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<6> frame_counter$_n58$raw_n3e2<6> _n29 frame_counter$_n29$raw_n40c<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<7> frame_counter$_n58$raw_n3e2<7> _n29 frame_counter$_n29$raw_n40c<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<8> frame_counter$_n58$raw_n3e2<8> _n29 frame_counter$_n29$raw_n40c<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_A load_A$_n58$raw_n3ec _n29 load_A$_n29$raw_n416 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_2 rx_status_2$_n58$raw_n3ee _n29 rx_status_2$_n29$raw_n418 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B load_B$_n58$raw_n3f0 _n29 load_B$_n29$raw_n41a +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n1f$raw_n41c 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$rx_control$raw_n27 pc$_n29$raw_n3f3 _n1f pc$_n1f$raw_n41c +- - 0 =pc$_n29$raw_n3f3 +- - 1 =pc$rx_control$raw_n27 +.names load_buff load_buff$_n29$raw_n3f9 _n1f load_buff$_n1f$raw_n41f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<0> bit_count_A$_n29$raw_n3fb<0> _n1f bit_count_A$_n1f$raw_n421<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<1> bit_count_A$_n29$raw_n3fb<1> _n1f bit_count_A$_n1f$raw_n421<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<2> bit_count_A$_n29$raw_n3fb<2> _n1f bit_count_A$_n1f$raw_n421<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<3> bit_count_A$_n29$raw_n3fb<3> _n1f bit_count_A$_n1f$raw_n421<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<4> bit_count_A$_n29$raw_n3fb<4> _n1f bit_count_A$_n1f$raw_n421<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<5> bit_count_A$_n29$raw_n3fb<5> _n1f bit_count_A$_n1f$raw_n421<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A<6> bit_count_A$_n29$raw_n3fb<6> _n1f bit_count_A$_n1f$raw_n421<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names clock_out clock_out$_n29$raw_n3f6 _n1f clock_out$_n1f$raw_n429 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<0> bit_count_B$_n29$raw_n403<0> _n1f bit_count_B$_n1f$raw_n42b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<1> bit_count_B$_n29$raw_n403<1> _n1f bit_count_B$_n1f$raw_n42b<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<2> bit_count_B$_n29$raw_n403<2> _n1f bit_count_B$_n1f$raw_n42b<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<3> bit_count_B$_n29$raw_n403<3> _n1f bit_count_B$_n1f$raw_n42b<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<4> bit_count_B$_n29$raw_n403<4> _n1f bit_count_B$_n1f$raw_n42b<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<5> bit_count_B$_n29$raw_n403<5> _n1f bit_count_B$_n1f$raw_n42b<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B<6> bit_count_B$_n29$raw_n403<6> _n1f bit_count_B$_n1f$raw_n42b<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<0> frame_counter$_n29$raw_n40c<0> _n1f frame_counter$_n1f$raw_n434<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<1> frame_counter$_n29$raw_n40c<1> _n1f frame_counter$_n1f$raw_n434<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<2> frame_counter$_n29$raw_n40c<2> _n1f frame_counter$_n1f$raw_n434<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<3> frame_counter$_n29$raw_n40c<3> _n1f frame_counter$_n1f$raw_n434<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<4> frame_counter$_n29$raw_n40c<4> _n1f frame_counter$_n1f$raw_n434<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<5> frame_counter$_n29$raw_n40c<5> _n1f frame_counter$_n1f$raw_n434<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<6> frame_counter$_n29$raw_n40c<6> _n1f frame_counter$_n1f$raw_n434<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<7> frame_counter$_n29$raw_n40c<7> _n1f frame_counter$_n1f$raw_n434<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter<8> frame_counter$_n29$raw_n40c<8> _n1f frame_counter$_n1f$raw_n434<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_A load_A$_n29$raw_n416 _n1f load_A$_n1f$raw_n43e +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_2 rx_status_2$_n29$raw_n418 _n1f rx_status_2$_n1f$raw_n440 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B load_B$_n29$raw_n41a _n1f load_B$_n1f$raw_n442 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (reset ) +.names load_buff$reset_n1a$true load_buff$_n1f$raw_n41f reset load_buff$reset$raw_n44d +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$reset_n1b$true<0> bit_count_A$_n1f$raw_n421<0> reset bit_count_A$reset$raw_n44f<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$reset_n1b$true<1> bit_count_A$_n1f$raw_n421<1> reset bit_count_A$reset$raw_n44f<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$reset_n1b$true<2> bit_count_A$_n1f$raw_n421<2> reset bit_count_A$reset$raw_n44f<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$reset_n1b$true<3> bit_count_A$_n1f$raw_n421<3> reset bit_count_A$reset$raw_n44f<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$reset_n1b$true<4> bit_count_A$_n1f$raw_n421<4> reset bit_count_A$reset$raw_n44f<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$reset_n1b$true<5> bit_count_A$_n1f$raw_n421<5> reset bit_count_A$reset$raw_n44f<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_A$reset_n1b$true<6> bit_count_A$_n1f$raw_n421<6> reset bit_count_A$reset$raw_n44f<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$reset_n1c$true<0> bit_count_B$_n1f$raw_n42b<0> reset bit_count_B$reset$raw_n457<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$reset_n1c$true<1> bit_count_B$_n1f$raw_n42b<1> reset bit_count_B$reset$raw_n457<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$reset_n1c$true<2> bit_count_B$_n1f$raw_n42b<2> reset bit_count_B$reset$raw_n457<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$reset_n1c$true<3> bit_count_B$_n1f$raw_n42b<3> reset bit_count_B$reset$raw_n457<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$reset_n1c$true<4> bit_count_B$_n1f$raw_n42b<4> reset bit_count_B$reset$raw_n457<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$reset_n1c$true<5> bit_count_B$_n1f$raw_n42b<5> reset bit_count_B$reset$raw_n457<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names bit_count_B$reset_n1c$true<6> bit_count_B$_n1f$raw_n42b<6> reset bit_count_B$reset$raw_n457<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$reset$raw_n45f 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names pc$reset_n1e$true pc$_n1f$raw_n41c reset pc$reset$raw_n45f +- - 0 =pc$_n1f$raw_n41c +- - 1 =pc$reset_n1e$true +.names frame_counter$reset_n1d$true<0> frame_counter$_n1f$raw_n434<0> reset frame_counter$reset$raw_n460<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$reset_n1d$true<1> frame_counter$_n1f$raw_n434<1> reset frame_counter$reset$raw_n460<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$reset_n1d$true<2> frame_counter$_n1f$raw_n434<2> reset frame_counter$reset$raw_n460<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$reset_n1d$true<3> frame_counter$_n1f$raw_n434<3> reset frame_counter$reset$raw_n460<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$reset_n1d$true<4> frame_counter$_n1f$raw_n434<4> reset frame_counter$reset$raw_n460<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$reset_n1d$true<5> frame_counter$_n1f$raw_n434<5> reset frame_counter$reset$raw_n460<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$reset_n1d$true<6> frame_counter$_n1f$raw_n434<6> reset frame_counter$reset$raw_n460<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$reset_n1d$true<7> frame_counter$_n1f$raw_n434<7> reset frame_counter$reset$raw_n460<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names frame_counter$reset_n1d$true<8> frame_counter$_n1f$raw_n434<8> reset frame_counter$reset$raw_n460<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_A$reset_n18$true load_A$_n1f$raw_n43e reset load_A$reset$raw_n46a +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names load_B$reset_n19$true load_B$_n1f$raw_n442 reset load_B$reset$raw_n46d +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_2$reset_n17$true rx_status_2$_n1f$raw_n440 reset rx_status_2$reset$raw_n46f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_3$reset_n16$true rx_status_3 reset rx_status_3$reset$raw_n477 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names clock_out clock_out$_n1f$raw_n429 reset clock_out$reset$raw_n47c +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names reset _n485 +- =reset +# shift_reg = 0 +.names shift_reg$reset_n486$true<0> +0 +.names shift_reg$reset_n486$true<1> +0 +.names shift_reg$reset_n486$true<2> +0 +.names shift_reg$reset_n486$true<3> +0 +.names shift_reg$reset_n486$true<4> +0 +.names shift_reg$reset_n486$true<5> +0 +.names shift_reg$reset_n486$true<6> +0 +.names shift_reg$reset_n486$true<7> +0 +.names shift_reg$reset_n486$true<8> +0 +.names shift_reg$reset_n486$true<9> +0 +.names shift_reg$reset_n486$true<10> +0 +.names shift_reg$reset_n486$true<11> +0 +.names shift_reg$reset_n486$true<12> +0 +.names shift_reg$reset_n486$true<13> +0 +.names shift_reg$reset_n486$true<14> +0 +.names shift_reg$reset_n486$true<15> +0 +.names shift_reg$reset_n486$true<16> +0 +.names shift_reg$reset_n486$true<17> +0 +.names shift_reg$reset_n486$true<18> +0 +.names shift_reg$reset_n486$true<19> +0 +# rx_status_1 = 0 +.names rx_status_1$reset_n487$true +0 +# rx_status_0 = 0 +.names rx_status_0$reset_n488$true +0 +.mv _n48a 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n48a +L0 +# pc != 0 +.names pc _n48a _n489 +.def 1 +- =pc 0 +.mv _n48c 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n48c +L1 +# pc != 1 +.names pc _n48c _n48b +.def 1 +- =pc 0 +# pc != 0 && pc != 1 +.names _n489 _n48b _n48d +.def 0 +1 1 1 +.names _n48d _n48e +- =_n48d +# shift_reg = {shift_reg [18 : 0], bit_in } +.names bit_in _n490<0> +- =bit_in +.names _n491 +0 +.names shift_reg<0> _n490<1> +- =shift_reg<0> +.names shift_reg<1> _n490<2> +- =shift_reg<1> +.names shift_reg<2> _n490<3> +- =shift_reg<2> +.names shift_reg<3> _n490<4> +- =shift_reg<3> +.names shift_reg<4> _n490<5> +- =shift_reg<4> +.names shift_reg<5> _n490<6> +- =shift_reg<5> +.names shift_reg<6> _n490<7> +- =shift_reg<6> +.names shift_reg<7> _n490<8> +- =shift_reg<7> +.names shift_reg<8> _n490<9> +- =shift_reg<8> +.names shift_reg<9> _n490<10> +- =shift_reg<9> +.names shift_reg<10> _n490<11> +- =shift_reg<10> +.names shift_reg<11> _n490<12> +- =shift_reg<11> +.names shift_reg<12> _n490<13> +- =shift_reg<12> +.names shift_reg<13> _n490<14> +- =shift_reg<13> +.names shift_reg<14> _n490<15> +- =shift_reg<14> +.names shift_reg<15> _n490<16> +- =shift_reg<15> +.names shift_reg<16> _n490<17> +- =shift_reg<16> +.names shift_reg<17> _n490<18> +- =shift_reg<17> +.names shift_reg<18> _n490<19> +- =shift_reg<18> +.names _n490<0> shift_reg$_n48d_n48f$true<0> +- =_n490<0> +.names _n490<1> shift_reg$_n48d_n48f$true<1> +- =_n490<1> +.names _n490<2> shift_reg$_n48d_n48f$true<2> +- =_n490<2> +.names _n490<3> shift_reg$_n48d_n48f$true<3> +- =_n490<3> +.names _n490<4> shift_reg$_n48d_n48f$true<4> +- =_n490<4> +.names _n490<5> shift_reg$_n48d_n48f$true<5> +- =_n490<5> +.names _n490<6> shift_reg$_n48d_n48f$true<6> +- =_n490<6> +.names _n490<7> shift_reg$_n48d_n48f$true<7> +- =_n490<7> +.names _n490<8> shift_reg$_n48d_n48f$true<8> +- =_n490<8> +.names _n490<9> shift_reg$_n48d_n48f$true<9> +- =_n490<9> +.names _n490<10> shift_reg$_n48d_n48f$true<10> +- =_n490<10> +.names _n490<11> shift_reg$_n48d_n48f$true<11> +- =_n490<11> +.names _n490<12> shift_reg$_n48d_n48f$true<12> +- =_n490<12> +.names _n490<13> shift_reg$_n48d_n48f$true<13> +- =_n490<13> +.names _n490<14> shift_reg$_n48d_n48f$true<14> +- =_n490<14> +.names _n490<15> shift_reg$_n48d_n48f$true<15> +- =_n490<15> +.names _n490<16> shift_reg$_n48d_n48f$true<16> +- =_n490<16> +.names _n490<17> shift_reg$_n48d_n48f$true<17> +- =_n490<17> +.names _n490<18> shift_reg$_n48d_n48f$true<18> +- =_n490<18> +.names _n490<19> shift_reg$_n48d_n48f$true<19> +- =_n490<19> +.names carrier_loss _n492 +- =carrier_loss +# rx_status_0 = 1 +.names rx_status_0$carrier_loss_n493$true +1 +# if/else (carrier_loss ) +.names rx_status_0$carrier_loss_n493$true rx_status_0 carrier_loss rx_status_0$carrier_loss$raw_n498 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names biphase_violation _n49c +- =biphase_violation +# rx_status_1 = 1 +.names rx_status_1$biphase_violation_n49d$true +1 +# if/else (biphase_violation ) +.names rx_status_1$biphase_violation_n49d$true rx_status_1 biphase_violation rx_status_1$biphase_violation$raw_n4a6 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (pc != 0 && pc != 1) +.names rx_status_0$carrier_loss$raw_n498 rx_status_0 _n48d rx_status_0$_n48d$raw_n4b0 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<0> shift_reg<0> _n48d shift_reg$_n48d$raw_n4b2<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<1> shift_reg<1> _n48d shift_reg$_n48d$raw_n4b2<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<2> shift_reg<2> _n48d shift_reg$_n48d$raw_n4b2<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<3> shift_reg<3> _n48d shift_reg$_n48d$raw_n4b2<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<4> shift_reg<4> _n48d shift_reg$_n48d$raw_n4b2<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<5> shift_reg<5> _n48d shift_reg$_n48d$raw_n4b2<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<6> shift_reg<6> _n48d shift_reg$_n48d$raw_n4b2<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<7> shift_reg<7> _n48d shift_reg$_n48d$raw_n4b2<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<8> shift_reg<8> _n48d shift_reg$_n48d$raw_n4b2<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<9> shift_reg<9> _n48d shift_reg$_n48d$raw_n4b2<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<10> shift_reg<10> _n48d shift_reg$_n48d$raw_n4b2<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<11> shift_reg<11> _n48d shift_reg$_n48d$raw_n4b2<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<12> shift_reg<12> _n48d shift_reg$_n48d$raw_n4b2<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<13> shift_reg<13> _n48d shift_reg$_n48d$raw_n4b2<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<14> shift_reg<14> _n48d shift_reg$_n48d$raw_n4b2<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<15> shift_reg<15> _n48d shift_reg$_n48d$raw_n4b2<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<16> shift_reg<16> _n48d shift_reg$_n48d$raw_n4b2<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<17> shift_reg<17> _n48d shift_reg$_n48d$raw_n4b2<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<18> shift_reg<18> _n48d shift_reg$_n48d$raw_n4b2<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$_n48d_n48f$true<19> shift_reg<19> _n48d shift_reg$_n48d$raw_n4b2<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_1$biphase_violation$raw_n4a6 rx_status_1 _n48d rx_status_1$_n48d$raw_n4c7 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (reset ) +.names rx_status_0$reset_n488$true rx_status_0$_n48d$raw_n4b0 reset rx_status_0$reset$raw_n4cc +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<0> shift_reg$_n48d$raw_n4b2<0> reset shift_reg$reset$raw_n4ce<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<1> shift_reg$_n48d$raw_n4b2<1> reset shift_reg$reset$raw_n4ce<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<2> shift_reg$_n48d$raw_n4b2<2> reset shift_reg$reset$raw_n4ce<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<3> shift_reg$_n48d$raw_n4b2<3> reset shift_reg$reset$raw_n4ce<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<4> shift_reg$_n48d$raw_n4b2<4> reset shift_reg$reset$raw_n4ce<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<5> shift_reg$_n48d$raw_n4b2<5> reset shift_reg$reset$raw_n4ce<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<6> shift_reg$_n48d$raw_n4b2<6> reset shift_reg$reset$raw_n4ce<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<7> shift_reg$_n48d$raw_n4b2<7> reset shift_reg$reset$raw_n4ce<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<8> shift_reg$_n48d$raw_n4b2<8> reset shift_reg$reset$raw_n4ce<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<9> shift_reg$_n48d$raw_n4b2<9> reset shift_reg$reset$raw_n4ce<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<10> shift_reg$_n48d$raw_n4b2<10> reset shift_reg$reset$raw_n4ce<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<11> shift_reg$_n48d$raw_n4b2<11> reset shift_reg$reset$raw_n4ce<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<12> shift_reg$_n48d$raw_n4b2<12> reset shift_reg$reset$raw_n4ce<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<13> shift_reg$_n48d$raw_n4b2<13> reset shift_reg$reset$raw_n4ce<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<14> shift_reg$_n48d$raw_n4b2<14> reset shift_reg$reset$raw_n4ce<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<15> shift_reg$_n48d$raw_n4b2<15> reset shift_reg$reset$raw_n4ce<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<16> shift_reg$_n48d$raw_n4b2<16> reset shift_reg$reset$raw_n4ce<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<17> shift_reg$_n48d$raw_n4b2<17> reset shift_reg$reset$raw_n4ce<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<18> shift_reg$_n48d$raw_n4b2<18> reset shift_reg$reset$raw_n4ce<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names shift_reg$reset_n486$true<19> shift_reg$_n48d$raw_n4b2<19> reset shift_reg$reset$raw_n4ce<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names rx_status_1$reset_n487$true rx_status_1$_n48d$raw_n4c7 reset rx_status_1$reset$raw_n4e3 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _n4ec 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n4ec +L2 +# pc == 2 +.names pc _n4ec _n4eb +.def 0 +- =pc 1 +# reset || pc == 2 +.names reset _n4eb _n4ed +.def 1 +0 0 0 +.mv _n4ef 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n4ef +L4 +# pc == 4 +.names pc _n4ef _n4ee +.def 0 +- =pc 1 +# reset || pc == 2 || pc == 4 +.names _n4ed _n4ee _n4f0 +.def 1 +0 0 0 +.mv _n4f2 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n4f2 +L6 +# pc == 6 +.names pc _n4f2 _n4f1 +.def 0 +- =pc 1 +# reset || pc == 2 || pc == 4 || pc == 6 +.names _n4f0 _n4f1 _n4f3 +.def 1 +0 0 0 +.mv _n4f5 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n4f5 +L8 +# pc == 8 +.names pc _n4f5 _n4f4 +.def 0 +- =pc 1 +# reset || pc == 2 || pc == 4 || pc == 6 || pc == 8 +.names _n4f3 _n4f4 _n4f6 +.def 1 +0 0 0 +.names _n4f6 _n4f7 +- =_n4f6 +# parity = 0 +.names parity$_n4f6_n4f8$true +0 +.mv _n4fa 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n4fa +L0 +# pc != 0 +.names pc _n4fa _n4f9 +.def 1 +- =pc 0 +.mv _n4fc 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n4fc +L1 +# pc != 1 +.names pc _n4fc _n4fb +.def 1 +- =pc 0 +# pc != 0 && pc != 1 +.names _n4f9 _n4fb _n4fd +.def 0 +1 1 1 +.names _n4fd _n4fe +- =_n4fd +# parity = parity ^ bit_in +# parity ^ bit_in +.names parity bit_in _n500 +.def 0 +0 1 1 +1 0 1 +.names _n500 parity$_n4fd_n4ff$true +- =_n500 +# if/else (pc != 0 && pc != 1) +.names parity$_n4fd_n4ff$true parity _n4fd parity$_n4fd$raw_n503 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (reset || pc == 2 || pc == 4 || pc == 6 || pc == 8) +.names parity$_n4f6_n4f8$true parity$_n4fd$raw_n503 _n4f6 parity$_n4f6$raw_n506 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names _n485 _n48e _n492 _n50a +.def 0 + 1 - - 1 + 0 1 1 1 +.names _n50a rx_status_0$reset$raw_n4cc rx_status_0 _n50b +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n15 _n1f _n29 _n58 _n6b _n7b _n98 _naa _ndc _ne2 _n145 _n169 _n179 _n1ad _n1b2 _n1d8 _n50c +.def 0 + 1 - - - - - - - - - - - - - - - 1 + 0 0 0 0 1 1 1 - - - - - - - - - 1 + 0 0 0 0 1 1 - 1 - - - - - - - - 1 + 0 0 0 0 0 - - - 0 0 0 1 1 1 1 - 1 + 0 0 0 0 0 - - - 0 0 0 1 1 - - 1 1 +.names _n50c load_buff$reset$raw_n44d load_buff _n50d +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n15 _n1f _n29 _n58 _n5b _n6b _n7b _ndc _ne2 _n145 _n157 _n169 _n179 _n50e +.def 0 + 1 - - - - - - - - - - - - 1 + 0 0 0 1 1 - - - - - - - - 1 + 0 0 0 0 - 1 1 - - - - - - 1 + 0 0 0 0 - 0 - 0 0 1 1 - - 1 + 0 0 0 0 - 0 - 0 0 0 - 1 1 1 +.names _n50e bit_count_A$reset$raw_n44f<0> bit_count_A$reset$raw_n44f<1> bit_count_A$reset$raw_n44f<2> bit_count_A$reset$raw_n44f<3> bit_count_A$reset$raw_n44f<4> bit_count_A$reset$raw_n44f<5> bit_count_A$reset$raw_n44f<6> bit_count_A<0> bit_count_A<1> bit_count_A<2> bit_count_A<3> bit_count_A<4> bit_count_A<5> bit_count_A<6> -> _n50f<0> _n50f<1> _n50f<2> _n50f<3> _n50f<4> _n50f<5> _n50f<6> +1 - - - - - - - - - - - - - - =bit_count_A$reset$raw_n44f<0> =bit_count_A$reset$raw_n44f<1> =bit_count_A$reset$raw_n44f<2> =bit_count_A$reset$raw_n44f<3> =bit_count_A$reset$raw_n44f<4> =bit_count_A$reset$raw_n44f<5> =bit_count_A$reset$raw_n44f<6> +0 - - - - - - - - - - - - - - =bit_count_A<0> =bit_count_A<1> =bit_count_A<2> =bit_count_A<3> =bit_count_A<4> =bit_count_A<5> =bit_count_A<6> +.names _n15 _n1f _n29 _n2c _n32 _n38 _n3e _n510 +.def 0 + 0 0 1 1 - - - 1 + 0 0 1 0 1 - - 1 + 0 0 1 0 0 1 - 1 + 0 0 1 0 0 0 1 1 +.names _n510 clock_out$reset$raw_n47c clock_out _n511 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n15 _n1f _n29 _n58 _n6b _ndc _ne2 _nf2 _n145 _n169 _n212 _n217 _n227 _n512 +.def 0 + 1 - - - - - - - - - - - - 1 + 0 0 0 0 0 1 - - - - - - - 1 + 0 0 0 0 0 0 1 1 - - - - - 1 + 0 0 0 0 0 0 0 - 0 0 1 - - 1 + 0 0 0 0 0 0 0 - 0 0 0 1 1 1 +.names _n512 bit_count_B$reset$raw_n457<0> bit_count_B$reset$raw_n457<1> bit_count_B$reset$raw_n457<2> bit_count_B$reset$raw_n457<3> bit_count_B$reset$raw_n457<4> bit_count_B$reset$raw_n457<5> bit_count_B$reset$raw_n457<6> bit_count_B<0> bit_count_B<1> bit_count_B<2> bit_count_B<3> bit_count_B<4> bit_count_B<5> bit_count_B<6> -> _n513<0> _n513<1> _n513<2> _n513<3> _n513<4> _n513<5> _n513<6> +1 - - - - - - - - - - - - - - =bit_count_B$reset$raw_n457<0> =bit_count_B$reset$raw_n457<1> =bit_count_B$reset$raw_n457<2> =bit_count_B$reset$raw_n457<3> =bit_count_B$reset$raw_n457<4> =bit_count_B$reset$raw_n457<5> =bit_count_B$reset$raw_n457<6> +0 - - - - - - - - - - - - - - =bit_count_B<0> =bit_count_B<1> =bit_count_B<2> =bit_count_B<3> =bit_count_B<4> =bit_count_B<5> =bit_count_B<6> +.names _n15 _n1f _n22 _n29 _n58 _n5b _n6b _n7b _ndc _ne2 _nf2 _n145 _n157 _n169 _n179 _n212 _n217 _n227 _n27a _n514 +.def 0 + 1 - - - - - - - - - - - - - - - - - - 1 + 0 1 1 - - - - - - - - - - - - - - - - 1 + 0 0 - 1 - - - - - - - - - - - - - - - 1 + 0 0 - 0 1 1 - - - - - - - - - - - - - 1 + 0 0 - 0 0 - 1 0 - - - - - - - - - - - 1 + 0 0 - 0 0 - 0 - 1 - - - - - - - - - - 1 + 0 0 - 0 0 - 0 - 0 1 0 - - - - - - - - 1 + 0 0 - 0 0 - 0 - 0 0 - 1 1 - - - - - - 1 + 0 0 - 0 0 - 0 - 0 0 - 1 0 - - - - - - 1 + 0 0 - 0 0 - 0 - 0 0 - 0 - 1 0 - - - - 1 + 0 0 - 0 0 - 0 - 0 0 - 0 - 0 - 1 - - - 1 + 0 0 - 0 0 - 0 - 0 0 - 0 - 0 - 0 1 0 - 1 + 0 0 - 0 0 - 0 - 0 0 - 0 - 0 - 0 0 - 1 1 +.mv _n515 11 L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 +.names _n514 pc$reset$raw_n45f pc _n515 +1 - - =pc$reset$raw_n45f +0 - - =pc +.names _n4f7 _n4fe _n51a +.def 0 + 1 - 1 + 0 1 1 +.names _n51a parity$_n4f6$raw_n506 parity _n51b +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n485 _n48e _n51c +.def 0 + 1 - 1 + 0 1 1 +.names _n51c shift_reg$reset$raw_n4ce<0> shift_reg$reset$raw_n4ce<1> shift_reg$reset$raw_n4ce<2> shift_reg$reset$raw_n4ce<3> shift_reg$reset$raw_n4ce<4> shift_reg$reset$raw_n4ce<5> shift_reg$reset$raw_n4ce<6> shift_reg$reset$raw_n4ce<7> shift_reg$reset$raw_n4ce<8> shift_reg$reset$raw_n4ce<9> shift_reg$reset$raw_n4ce<10> shift_reg$reset$raw_n4ce<11> shift_reg$reset$raw_n4ce<12> shift_reg$reset$raw_n4ce<13> shift_reg$reset$raw_n4ce<14> shift_reg$reset$raw_n4ce<15> shift_reg$reset$raw_n4ce<16> shift_reg$reset$raw_n4ce<17> shift_reg$reset$raw_n4ce<18> shift_reg$reset$raw_n4ce<19> shift_reg<0> shift_reg<1> shift_reg<2> shift_reg<3> shift_reg<4> shift_reg<5> shift_reg<6> shift_reg<7> shift_reg<8> shift_reg<9> shift_reg<10> shift_reg<11> shift_reg<12> shift_reg<13> shift_reg<14> shift_reg<15> shift_reg<16> shift_reg<17> shift_reg<18> shift_reg<19> -> _n51d<0> _n51d<1> _n51d<2> _n51d<3> _n51d<4> _n51d<5> _n51d<6> _n51d<7> _n51d<8> _n51d<9> _n51d<10> _n51d<11> _n51d<12> _n51d<13> _n51d<14> _n51d<15> _n51d<16> _n51d<17> _n51d<18> _n51d<19> +1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =shift_reg$reset$raw_n4ce<0> =shift_reg$reset$raw_n4ce<1> =shift_reg$reset$raw_n4ce<2> =shift_reg$reset$raw_n4ce<3> =shift_reg$reset$raw_n4ce<4> =shift_reg$reset$raw_n4ce<5> =shift_reg$reset$raw_n4ce<6> =shift_reg$reset$raw_n4ce<7> =shift_reg$reset$raw_n4ce<8> =shift_reg$reset$raw_n4ce<9> =shift_reg$reset$raw_n4ce<10> =shift_reg$reset$raw_n4ce<11> =shift_reg$reset$raw_n4ce<12> =shift_reg$reset$raw_n4ce<13> =shift_reg$reset$raw_n4ce<14> =shift_reg$reset$raw_n4ce<15> =shift_reg$reset$raw_n4ce<16> =shift_reg$reset$raw_n4ce<17> =shift_reg$reset$raw_n4ce<18> =shift_reg$reset$raw_n4ce<19> +0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =shift_reg<0> =shift_reg<1> =shift_reg<2> =shift_reg<3> =shift_reg<4> =shift_reg<5> =shift_reg<6> =shift_reg<7> =shift_reg<8> =shift_reg<9> =shift_reg<10> =shift_reg<11> =shift_reg<12> =shift_reg<13> =shift_reg<14> =shift_reg<15> =shift_reg<16> =shift_reg<17> =shift_reg<18> =shift_reg<19> +.names _n15 _n1f _n29 _n58 _n6b _ndc _ne2 _n145 _n169 _n212 _n217 _n27a _n51e +.def 0 + 1 - - - - - - - - - - - 1 + 0 0 0 0 0 1 - - - - - - 1 + 0 0 0 0 0 0 0 0 0 0 0 1 1 +.names _n51e frame_counter$reset$raw_n460<0> frame_counter$reset$raw_n460<1> frame_counter$reset$raw_n460<2> frame_counter$reset$raw_n460<3> frame_counter$reset$raw_n460<4> frame_counter$reset$raw_n460<5> frame_counter$reset$raw_n460<6> frame_counter$reset$raw_n460<7> frame_counter$reset$raw_n460<8> frame_counter<0> frame_counter<1> frame_counter<2> frame_counter<3> frame_counter<4> frame_counter<5> frame_counter<6> frame_counter<7> frame_counter<8> -> _n51f<0> _n51f<1> _n51f<2> _n51f<3> _n51f<4> _n51f<5> _n51f<6> _n51f<7> _n51f<8> +1 - - - - - - - - - - - - - - - - - - =frame_counter$reset$raw_n460<0> =frame_counter$reset$raw_n460<1> =frame_counter$reset$raw_n460<2> =frame_counter$reset$raw_n460<3> =frame_counter$reset$raw_n460<4> =frame_counter$reset$raw_n460<5> =frame_counter$reset$raw_n460<6> =frame_counter$reset$raw_n460<7> =frame_counter$reset$raw_n460<8> +0 - - - - - - - - - - - - - - - - - - =frame_counter<0> =frame_counter<1> =frame_counter<2> =frame_counter<3> =frame_counter<4> =frame_counter<5> =frame_counter<6> =frame_counter<7> =frame_counter<8> +.names _n15 _n520 +.def 0 + 1 1 +.names _n520 rx_status_3$reset$raw_n477 rx_status_3 _n521 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n15 _n1f _n29 _n58 _n6b _n7b _n80 _ndc _ne2 _nf2 _n114 _n145 _n169 _n179 _n18d _n212 _n217 _n227 _n249 _n522 +.def 0 + 1 - - - - - - - - - - - - - - - - - - 1 + 0 0 0 0 1 1 1 - - - - - - - - - - - - 1 + 0 0 0 0 0 - - 0 1 1 1 - - - - - - - - 1 + 0 0 0 0 0 - - 0 0 - - 0 1 1 1 - - - - 1 + 0 0 0 0 0 - - 0 0 - - 0 0 - - 0 1 1 1 1 +.names _n522 load_A$reset$raw_n46a load_A _n523 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names rx_status$raw_n0<0> rx_status<0> +- =rx_status$raw_n0<0> +.names rx_status$raw_n0<1> rx_status<1> +- =rx_status$raw_n0<1> +.names rx_status$raw_n0<2> rx_status<2> +- =rx_status$raw_n0<2> +.names rx_status$raw_n0<3> rx_status<3> +- =rx_status$raw_n0<3> +.names _n15 _n1f _n29 _n58 _n6b _ndc _ne2 _nf2 _nfc _n145 _n169 _n179 _n183 _n212 _n217 _n227 _n231 _n524 +.def 0 + 1 - - - - - - - - - - - - - - - - 1 + 0 0 0 0 0 0 1 1 1 - - - - - - - - 1 + 0 0 0 0 0 0 0 - - 0 1 1 1 - - - - 1 + 0 0 0 0 0 0 0 - - 0 0 - - 0 1 1 1 1 +.names _n524 rx_status_2$reset$raw_n46f rx_status_2 _n525 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names frame_ofs$raw_n14<0> frame_ofs<0> +- =frame_ofs$raw_n14<0> +.names frame_ofs$raw_n14<1> frame_ofs<1> +- =frame_ofs$raw_n14<1> +.names _n15 _n1f _n29 _n58 _n6b _n7b _n8a _ndc _ne2 _nf2 _n106 _n145 _n169 _n179 _n19b _n212 _n217 _n227 _n23b _n526 +.def 0 + 1 - - - - - - - - - - - - - - - - - - 1 + 0 0 0 0 1 1 1 - - - - - - - - - - - - 1 + 0 0 0 0 0 - - 0 1 1 1 - - - - - - - - 1 + 0 0 0 0 0 - - 0 0 - - 0 1 1 1 - - - - 1 + 0 0 0 0 0 - - 0 0 - - 0 0 - - 0 1 1 1 1 +.names _n526 load_B$reset$raw_n46d load_B _n527 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n485 _n48e _n49c _n528 +.def 0 + 1 - - 1 + 0 1 1 1 +.names _n528 rx_status_1$reset$raw_n4e3 rx_status_1 _n529 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +# non-blocking assignments +# latches +.r load_buff$raw_n11 load_buff +0 0 +1 1 +.latch _n50d load_buff +.r rx_status_0$raw_nd rx_status_0 +0 0 +1 1 +.latch _n50b rx_status_0 +.r clock_out$raw_n9 clock_out +0 0 +1 1 +.latch _n511 clock_out +.r bit_count_A$raw_n6<0> bit_count_A<0> +.def 0 +1 1 +.r bit_count_A$raw_n6<1> bit_count_A<1> +.def 0 +1 1 +.r bit_count_A$raw_n6<2> bit_count_A<2> +.def 0 +1 1 +.r bit_count_A$raw_n6<3> bit_count_A<3> +.def 0 +1 1 +.r bit_count_A$raw_n6<4> bit_count_A<4> +.def 0 +1 1 +.r bit_count_A$raw_n6<5> bit_count_A<5> +.def 0 +1 1 +.r bit_count_A$raw_n6<6> bit_count_A<6> +.def 0 +1 1 +.latch _n50f<0> bit_count_A<0> +.latch _n50f<1> bit_count_A<1> +.latch _n50f<2> bit_count_A<2> +.latch _n50f<3> bit_count_A<3> +.latch _n50f<4> bit_count_A<4> +.latch _n50f<5> bit_count_A<5> +.latch _n50f<6> bit_count_A<6> +.r bit_count_B$raw_n7<0> bit_count_B<0> +.def 0 +1 1 +.r bit_count_B$raw_n7<1> bit_count_B<1> +.def 0 +1 1 +.r bit_count_B$raw_n7<2> bit_count_B<2> +.def 0 +1 1 +.r bit_count_B$raw_n7<3> bit_count_B<3> +.def 0 +1 1 +.r bit_count_B$raw_n7<4> bit_count_B<4> +.def 0 +1 1 +.r bit_count_B$raw_n7<5> bit_count_B<5> +.def 0 +1 1 +.r bit_count_B$raw_n7<6> bit_count_B<6> +.def 0 +1 1 +.latch _n513<0> bit_count_B<0> +.latch _n513<1> bit_count_B<1> +.latch _n513<2> bit_count_B<2> +.latch _n513<3> bit_count_B<3> +.latch _n513<4> bit_count_B<4> +.latch _n513<5> bit_count_B<5> +.latch _n513<6> bit_count_B<6> +.r parity$raw_ne parity +0 0 +1 1 +.latch _n51b parity +.r pc$raw_n13 pc +- =pc$raw_n13 +.latch _n515 pc +.r shift_reg$raw_n12<0> shift_reg<0> +.def 0 +1 1 +.r shift_reg$raw_n12<1> shift_reg<1> +.def 0 +1 1 +.r shift_reg$raw_n12<2> shift_reg<2> +.def 0 +1 1 +.r shift_reg$raw_n12<3> shift_reg<3> +.def 0 +1 1 +.r shift_reg$raw_n12<4> shift_reg<4> +.def 0 +1 1 +.r shift_reg$raw_n12<5> shift_reg<5> +.def 0 +1 1 +.r shift_reg$raw_n12<6> shift_reg<6> +.def 0 +1 1 +.r shift_reg$raw_n12<7> shift_reg<7> +.def 0 +1 1 +.r shift_reg$raw_n12<8> shift_reg<8> +.def 0 +1 1 +.r shift_reg$raw_n12<9> shift_reg<9> +.def 0 +1 1 +.r shift_reg$raw_n12<10> shift_reg<10> +.def 0 +1 1 +.r shift_reg$raw_n12<11> shift_reg<11> +.def 0 +1 1 +.r shift_reg$raw_n12<12> shift_reg<12> +.def 0 +1 1 +.r shift_reg$raw_n12<13> shift_reg<13> +.def 0 +1 1 +.r shift_reg$raw_n12<14> shift_reg<14> +.def 0 +1 1 +.r shift_reg$raw_n12<15> shift_reg<15> +.def 0 +1 1 +.r shift_reg$raw_n12<16> shift_reg<16> +.def 0 +1 1 +.r shift_reg$raw_n12<17> shift_reg<17> +.def 0 +1 1 +.r shift_reg$raw_n12<18> shift_reg<18> +.def 0 +1 1 +.r shift_reg$raw_n12<19> shift_reg<19> +.def 0 +1 1 +.latch _n51d<0> shift_reg<0> +.latch _n51d<1> shift_reg<1> +.latch _n51d<2> shift_reg<2> +.latch _n51d<3> shift_reg<3> +.latch _n51d<4> shift_reg<4> +.latch _n51d<5> shift_reg<5> +.latch _n51d<6> shift_reg<6> +.latch _n51d<7> shift_reg<7> +.latch _n51d<8> shift_reg<8> +.latch _n51d<9> shift_reg<9> +.latch _n51d<10> shift_reg<10> +.latch _n51d<11> shift_reg<11> +.latch _n51d<12> shift_reg<12> +.latch _n51d<13> shift_reg<13> +.latch _n51d<14> shift_reg<14> +.latch _n51d<15> shift_reg<15> +.latch _n51d<16> shift_reg<16> +.latch _n51d<17> shift_reg<17> +.latch _n51d<18> shift_reg<18> +.latch _n51d<19> shift_reg<19> +.r frame_counter$raw_n8<0> frame_counter<0> +.def 0 +1 1 +.r frame_counter$raw_n8<1> frame_counter<1> +.def 0 +1 1 +.r frame_counter$raw_n8<2> frame_counter<2> +.def 0 +1 1 +.r frame_counter$raw_n8<3> frame_counter<3> +.def 0 +1 1 +.r frame_counter$raw_n8<4> frame_counter<4> +.def 0 +1 1 +.r frame_counter$raw_n8<5> frame_counter<5> +.def 0 +1 1 +.r frame_counter$raw_n8<6> frame_counter<6> +.def 0 +1 1 +.r frame_counter$raw_n8<7> frame_counter<7> +.def 0 +1 1 +.r frame_counter$raw_n8<8> frame_counter<8> +.def 0 +1 1 +.latch _n51f<0> frame_counter<0> +.latch _n51f<1> frame_counter<1> +.latch _n51f<2> frame_counter<2> +.latch _n51f<3> frame_counter<3> +.latch _n51f<4> frame_counter<4> +.latch _n51f<5> frame_counter<5> +.latch _n51f<6> frame_counter<6> +.latch _n51f<7> frame_counter<7> +.latch _n51f<8> frame_counter<8> +.r load_A$raw_nf load_A +0 0 +1 1 +.latch _n523 load_A +.r rx_status_3$raw_na rx_status_3 +0 0 +1 1 +.latch _n521 rx_status_3 +.r load_B$raw_n10 load_B +0 0 +1 1 +.latch _n527 load_B +.r rx_status_2$raw_nb rx_status_2 +0 0 +1 1 +.latch _n525 rx_status_2 +.r rx_status_1$raw_nc rx_status_1 +0 0 +1 1 +.latch _n529 rx_status_1 +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/daio_receiver/daio_receiver.ord =================================================================== --- vis_dev/vis-2.1/examples/daio_receiver/daio_receiver.ord (revision 11) +++ vis_dev/vis-2.1/examples/daio_receiver/daio_receiver.ord (revision 11) @@ -0,0 +1,126 @@ +# vis release 1.4 (compiled 1-Jan-01 at 4:07 AM) +# network name: daio_receiver +# generated: Mon Jan 1 18:50:14 2001 +# +# name type mddId vals levs +rx_control<3> primary-input 120 2 (0) +rx_control<1> primary-input 1 2 (1) +rx_control<0> primary-input 0 2 (2) +xtal<0> primary-input 7 2 (3) +xtal<2> primary-input 5 2 (4) +xtal<1> primary-input 6 2 (5) +xtal<3> primary-input 2 2 (6) +clock_out$NS shadow 4 2 (7) +clock_out latch 3 2 (8) +rx_status_3 latch 93 2 (9) +rx_status_3$NS shadow 94 2 (10) +reset primary-input 92 2 (11) +biphase_violation primary-input 95 2 (12) +carrier_loss primary-input 96 2 (13) +bit_count_B<4>$NS shadow 15 2 (14) +bit_count_B<4> latch 14 2 (15) +bit_count_B<3>$NS shadow 13 2 (16) +bit_count_B<3> latch 12 2 (17) +bit_count_B<2>$NS shadow 11 2 (18) +bit_count_B<2> latch 10 2 (19) +bit_count_B<5>$NS shadow 17 2 (20) +bit_count_B<5> latch 16 2 (21) +bit_count_B<6>$NS shadow 19 2 (22) +bit_count_B<6> latch 18 2 (23) +bit_count_B<1>$NS shadow 9 2 (24) +bit_count_B<1> latch 8 2 (25) +rx_control<2> primary-input 91 2 (26) +pc latch 64 11 (27, 32, 33, 34) +pc$NS shadow 65 11 (28, 29, 30, 31) +bit_in primary-input 99 2 (35) +bit_count_A<5>$NS shadow 60 2 (36) +bit_count_A<5> latch 59 2 (37) +bit_count_A<6>$NS shadow 62 2 (38) +bit_count_A<6> latch 61 2 (39) +load_A$NS shadow 26 2 (40) +load_A latch 25 2 (41) +bit_count_A<4>$NS shadow 58 2 (42) +bit_count_A<4> latch 57 2 (43) +bit_count_A<3>$NS shadow 56 2 (44) +bit_count_A<3> latch 55 2 (45) +bit_count_B<0>$NS shadow 28 2 (46) +bit_count_B<0> latch 27 2 (47) +rx_status_2$NS shadow 24 2 (48) +rx_status_2 latch 23 2 (49) +load_B$NS shadow 21 2 (50) +load_B latch 20 2 (51) +bit_count_A<2>$NS shadow 54 2 (52) +bit_count_A<2> latch 53 2 (53) +bit_count_A<1>$NS shadow 52 2 (54) +bit_count_A<1> latch 51 2 (55) +bit_count_A<0>$NS shadow 50 2 (56) +bit_count_A<0> latch 49 2 (57) +frame_counter<0>$NS shadow 30 2 (58) +frame_counter<0> latch 29 2 (59) +frame_counter<1>$NS shadow 32 2 (60) +frame_counter<1> latch 31 2 (61) +frame_counter<2>$NS shadow 36 2 (62) +frame_counter<2> latch 35 2 (63) +frame_counter<4>$NS shadow 40 2 (64) +frame_counter<4> latch 39 2 (65) +frame_counter<3>$NS shadow 38 2 (66) +frame_counter<3> latch 37 2 (67) +frame_counter<5>$NS shadow 42 2 (68) +frame_counter<5> latch 41 2 (69) +frame_counter<6>$NS shadow 44 2 (70) +frame_counter<6> latch 43 2 (71) +frame_counter<7>$NS shadow 46 2 (72) +frame_counter<7> latch 45 2 (73) +frame_counter<8>$NS shadow 48 2 (74) +frame_counter<8> latch 47 2 (75) +load_buff latch 33 2 (76) +load_buff$NS shadow 34 2 (77) +shift_reg<11>$NS shadow 73 2 (78) +shift_reg<11> latch 72 2 (79) +shift_reg<12>$NS shadow 75 2 (80) +shift_reg<12> latch 74 2 (81) +shift_reg<13>$NS shadow 77 2 (82) +shift_reg<13> latch 76 2 (83) +shift_reg<14>$NS shadow 79 2 (84) +shift_reg<14> latch 78 2 (85) +shift_reg<15>$NS shadow 81 2 (86) +shift_reg<15> latch 80 2 (87) +shift_reg<16>$NS shadow 83 2 (88) +shift_reg<16> latch 82 2 (89) +shift_reg<17>$NS shadow 85 2 (90) +shift_reg<17> latch 84 2 (91) +shift_reg<18>$NS shadow 87 2 (92) +shift_reg<18> latch 86 2 (93) +shift_reg<19>$NS shadow 89 2 (94) +shift_reg<19> latch 88 2 (95) +shift_reg<10>$NS shadow 71 2 (96) +shift_reg<10> latch 70 2 (97) +shift_reg<9> latch 68 2 (98) +shift_reg<9>$NS shadow 69 2 (99) +shift_reg<8> latch 116 2 (100) +shift_reg<8>$NS shadow 117 2 (101) +shift_reg<7>$NS shadow 115 2 (102) +shift_reg<7> latch 114 2 (103) +parity$NS shadow 119 2 (104) +parity latch 118 2 (105) +shift_reg<0>$NS shadow 101 2 (106) +shift_reg<0> latch 100 2 (107) +shift_reg<1>$NS shadow 103 2 (108) +shift_reg<1> latch 102 2 (109) +shift_reg<2>$NS shadow 105 2 (110) +shift_reg<2> latch 104 2 (111) +shift_reg<3>$NS shadow 107 2 (112) +shift_reg<3> latch 106 2 (113) +shift_reg<4>$NS shadow 109 2 (114) +shift_reg<4> latch 108 2 (115) +shift_reg<5>$NS shadow 111 2 (116) +shift_reg<5> latch 110 2 (117) +shift_reg<6>$NS shadow 113 2 (118) +shift_reg<6> latch 112 2 (119) +rx_status_0$NS shadow 98 2 (120) +rx_status_0 latch 97 2 (121) +rx_status_1$NS shadow 67 2 (122) +rx_status_1 latch 66 2 (123) +preamble_2 primary-input 63 2 (124) +preamble_3 primary-input 22 2 (125) +preamble_1 primary-input 90 2 (126) Index: vis_dev/vis-2.1/examples/daio_receiver/var.system =================================================================== --- vis_dev/vis-2.1/examples/daio_receiver/var.system (revision 11) +++ vis_dev/vis-2.1/examples/daio_receiver/var.system (revision 11) @@ -0,0 +1,15 @@ +xtal<0> +xtal<1> +xtal<2> +xtal<3> +rx_control<0> +rx_control<1> +rx_control<2> +rx_control<3> +#reset +bit_in +preamble_1 +preamble_2 +preamble_3 +carrier_loss +biphase_violation Index: vis_dev/vis-2.1/examples/dcnew/affalse =================================================================== --- vis_dev/vis-2.1/examples/dcnew/affalse (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/affalse (revision 11) @@ -0,0 +1,1 @@ +AF FALSE; Index: vis_dev/vis-2.1/examples/dcnew/agtrue =================================================================== --- vis_dev/vis-2.1/examples/dcnew/agtrue (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/agtrue (revision 11) @@ -0,0 +1,1 @@ +AG TRUE; Index: vis_dev/vis-2.1/examples/dcnew/check_result =================================================================== --- vis_dev/vis-2.1/examples/dcnew/check_result (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/check_result (revision 11) @@ -0,0 +1,43 @@ +FSM depth = 11 +reachable states = 186876 +# LE: language is not empty +# MC: formula failed --- AF(FALSE) +# LE: language emptiness check passes +# MC: formula passed --- AG(TRUE) +# MC: formula failed --- AG(((lamp=lit -> EX(lamp=unlit)) * (lamp=unlit -> EX(lamp=lit)))) +# MC: formula passed --- EF((int.state=go3 + int.state=go4)) +# MC: formula passed --- EF(EG((int.state=go3 + int.state=go4))) +# MC: formula failed --- !(EF(EG((int.state=go3 + int.state=go4)))) +# MC: formula failed --- AG(AF((!(int.state=go3) * !(int.state=go4)))) +# MC: formula failed --- AG((interpretation=go -> train=absent)) +# MC: formula passed --- AG((interpretation=go -> !(train=present2))) +FSM depth = 16 +reachable states = 352544 +# LTL_MC: formula failed +FSM depth = 11 +reachable states = 445404 +# LTL_MC: formula failed +FSM depth = 18 +reachable states = 623201 +# LTL_MC: formula failed +FSM depth = 11 +reachable states = 373752 +# LTL_MC: formula passed +# MC: formula failed --- AG(((lamp=lit -> EX(lamp=unlit)) * (lamp=unlit -> EX(lamp=lit)))) +# MC: Vacuous failure : lamp=lit +# MC: Vacuous failure : lamp=unlit +# MC: Vacuous failure : lamp=unlit +# MC: Vacuous failure : lamp=lit +# MC: formula passed --- EF((int.state=go3 + int.state=go4)) +# MC: Vacuous pass : int.state=go3 +# MC: Vacuous pass : int.state=go4 +# MC: formula passed --- EF(EG((int.state=go3 + int.state=go4))) +# MC: No vacuous passes +# MC: formula failed --- !(EF(EG((int.state=go3 + int.state=go4)))) +# MC: No vacuous failures +# MC: formula failed --- AG(AF((!(int.state=go3) * !(int.state=go4)))) +# MC: No vacuous failures +# MC: formula failed --- AG((interpretation=go -> train=absent)) +# MC: No vacuous failures +# MC: formula passed --- AG((interpretation=go -> !(train=present2))) +# MC: Vacuous pass : interpretation=go Index: vis_dev/vis-2.1/examples/dcnew/check_script =================================================================== --- vis_dev/vis-2.1/examples/dcnew/check_script (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/check_script (revision 11) @@ -0,0 +1,23 @@ +read_blif_mv dcnew.mv +init_verify +compute_reach -v 1 +print_fairness +lang_empty -d 0 +model_check -d 0 affalse +read_fairness prop.fair +print_fairness +lang_empty -d 0 +reset_fairness +print_fairness +model_check -d 0 agtrue +model_check -d 0 osc2.ctl +model_check -d 0 osc3.ctl +model_check -d 0 osc4.ctl +model_check -d 0 osc5.ctl +model_check -d 0 osc6.ctl +model_check -d 0 safe.ctl +model_check -d 0 safe1.ctl +ltl_model_check -v1 -d1 dcnew.ltl +model_check -d 0 -V dcnew.ctl +time +quit -s Index: vis_dev/vis-2.1/examples/dcnew/dcnew.ctl =================================================================== --- vis_dev/vis-2.1/examples/dcnew/dcnew.ctl (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/dcnew.ctl (revision 11) @@ -0,0 +1,16 @@ +#FAIL: fails even when weakened to AG(lamp=unlit -> EX(lamp=lit)) +# or to AG(lamp=lit -> EX(lamp=unlit)) +AG(((lamp = lit)->EX(lamp=unlit))*((lamp=unlit)->EX(lamp=lit))); +#PASS: passes even when strengthened to EF(int.state=go3) +# or to EF(int.state=go4). +EF((int.state=go3)+(int.state=go4)); +#PASS: no vacuous passes +EF EG((int.state=go3)+(int.state=go4)); +#FAIL: no vacuous failures +!EF EG((int.state=go3)+(int.state=go4)); +#FAIL: no vacuous failures +AG AF(!(int.state=go3)*!(int.state=go4)); +#FAIL: no vacuous failures +AG((interpretation = go) -> (train = absent)); +#PASS: passes even when strengthened to AG !(train = present2) +AG((interpretation = go) -> !(train = present2)); Index: vis_dev/vis-2.1/examples/dcnew/dcnew.ltl =================================================================== --- vis_dev/vis-2.1/examples/dcnew/dcnew.ltl (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/dcnew.ltl (revision 11) @@ -0,0 +1,4 @@ +!G!((int.state=go3)+(int.state=go4)); +G F(!(int.state=go3)*!(int.state=go4)); +G((interpretation = go) -> (train = absent)); +G((interpretation = go) -> !(train = present2)); Index: vis_dev/vis-2.1/examples/dcnew/dcnew.mv =================================================================== --- vis_dev/vis-2.1/examples/dcnew/dcnew.mv (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/dcnew.mv (revision 11) @@ -0,0 +1,1670 @@ +# vl2mv dcnew.v +# version: 0.2 +# date: 11:13:36 12/11/95 (PST) +.model dchek +# I/O ports + +.mv interpretation 2 go stop +.mv charger 2 discharged charged +.mv ts_power 2 on off +.mv track3 2 conduct open +.mv train 3 present1 present2 absent +.mv contact 3 B middle C +.mv lamp 2 lit unlit +.mv relay 2 pulling neutral +.mv track2 2 conduct open +.mv track1 2 conduct open +.subckt track_mod trk1 track=track1 +.subckt track_mod trk2 track=track2 +.subckt track_mod trk3 track=track3 +.subckt charger_mod chg ts_power=ts_power lamp=lamp out=charger +.subckt relay_mod rly charger=charger relay=relay +.subckt lamp_mod lmp contact=contact wire3=track3 ts_power=ts_power charger=charger lamp=lamp +.subckt contact_mod cnt relay=relay contact=contact +.subckt train_mod trn out=train +.subckt track_system_mod tsm wire1=track1 wire2=track2 train=train contact=contact ts_power=ts_power +.subckt interpretation_mod int lamp=lamp out=interpretation +.subckt property_mod prop train=train interpretation=interpretation +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model track_mod +# I/O ports +.outputs track + +.mv r_state 3 good faulty1 faulty2 +.mv state 3 good faulty1 faulty2 +.mv track 2 conduct open +# state = 0 +.mv state$raw_n0 3 good faulty1 faulty2 +.names state$raw_n0 +good +# non-blocking assignments for initial +# assign r_state = $NDset ( 0,1 ) +.names r_state +good +faulty1 +# assign track = (state == good ) ? 0 : 1 +.mv track$raw_n3 2 conduct open +.mv _n5 3 good faulty1 faulty2 +.names _n5 +good +# state == 0 +.names state _n5 _n4 +.def 0 +- =state 1 +.mv _n6 2 conduct open +.names _n6 +conduct +.mv _n7 2 conduct open +.names _n7 +open +# (state == 0) ? 0 : 1 +.mv _n8 2 conduct open +.names _n6 _n7 _n4 _n8 +- - 0 =_n7 +- - 1 =_n6 +.names _n8 track$raw_n3 +- =_n8 +.mv _na 3 good faulty1 faulty2 +.names _na +faulty1 +# state == 1 +.names state _na _n9 +.def 0 +- =state 1 +.names _n9 _nb +- =_n9 +# state = 1 +.mv state$_n9_nc$true 3 good faulty1 faulty2 +.names state$_n9_nc$true +faulty1 +# if/else (state == 1) +.mv state$_n9$raw_nf 3 good faulty1 faulty2 +.names state$_n9_nc$true state _n9 state$_n9$raw_nf +- - 0 =state +- - 1 =state$_n9_nc$true +.mv _n11 3 good faulty1 faulty2 +.names _n11 +good +# state == 0 +.names state$_n9$raw_nf _n11 _n10 +.def 0 +- =state$_n9$raw_nf 1 +.names _n10 _n12 +- =_n10 +# state = r_state +.mv state$_n10_n13$true 3 good faulty1 faulty2 +.names r_state state$_n10_n13$true +- =r_state +# if/else (state == 0) +.mv state$_n10$raw_n14 3 good faulty1 faulty2 +.names state$_n10_n13$true state$_n9$raw_nf _n10 state$_n10$raw_n14 +- - 0 =state$_n9$raw_nf +- - 1 =state$_n10_n13$true +# conflict arbitrators +.names _nb _n12 _n18 +.def 0 + 1 - 1 + - 1 1 +.mv _n19 3 good faulty1 faulty2 +.names _n18 state$_n10$raw_n14 state _n19 +1 - - =state$_n10$raw_n14 +0 - - =state +.names track$raw_n3 track +- =track$raw_n3 +# non-blocking assignments +# latches +.r state$raw_n0 state +- =state$raw_n0 +.latch _n19 state +# quasi-continuous assignment +.end + + +.model charger_mod +# I/O ports +.outputs out +.inputs ts_power +.inputs lamp + +.mv out 2 discharged charged +.mv charger 2 discharged charged +.mv r_state 3 good faulty1 faulty2 +.mv state 3 good faulty1 faulty2 +.mv ts_power 2 on off +.mv lamp 2 lit unlit +# state = 0 +.mv state$raw_n1e 3 good faulty1 faulty2 +.names state$raw_n1e +good +# non-blocking assignments for initial +# charger = 0 +.mv charger$raw_n1f 2 discharged charged +.names charger$raw_n1f +discharged +# non-blocking assignments for initial +# assign r_state = $NDset ( 0,1,2 ) +.names r_state +good +faulty1 +faulty2 +# assign out = state == faulty1 ? 0 : state == faulty2 ? 1 : charger +.mv out$raw_n22 2 discharged charged +.mv _n24 3 good faulty1 faulty2 +.names _n24 +faulty1 +# state == 1 +.names state _n24 _n23 +.def 0 +- =state 1 +.mv _n26 3 good faulty1 faulty2 +.names _n26 +faulty2 +# state == 2 +.names state _n26 _n25 +.def 0 +- =state 1 +.mv _n27 2 discharged charged +.names _n27 +charged +# state == 2 ? 1 : charger +.mv _n28 2 discharged charged +.names _n27 charger _n25 _n28 +- - 0 =charger +- - 1 =_n27 +.mv _n29 2 discharged charged +.names _n29 +discharged +# state == 1 ? 0 : state == 2 ? 1 : charger +.mv _n2a 2 discharged charged +.names _n29 _n28 _n23 _n2a +- - 0 =_n28 +- - 1 =_n29 +.names _n2a out$raw_n22 +- =_n2a +.mv _n2c 3 good faulty1 faulty2 +.names _n2c +faulty1 +# state == 1 +.names state _n2c _n2b +.def 0 +- =state 1 +.names _n2b _n2d +- =_n2b +# state = 1 +.mv state$_n2b_n2e$true 3 good faulty1 faulty2 +.names state$_n2b_n2e$true +faulty1 +# if/else (state == 1) +.mv state$_n2b$raw_n31 3 good faulty1 faulty2 +.names state$_n2b_n2e$true state _n2b state$_n2b$raw_n31 +- - 0 =state +- - 1 =state$_n2b_n2e$true +.mv _n33 3 good faulty1 faulty2 +.names _n33 +faulty2 +# state == 2 +.names state$_n2b$raw_n31 _n33 _n32 +.def 0 +- =state$_n2b$raw_n31 1 +.names _n32 _n34 +- =_n32 +# state = 2 +.mv state$_n32_n35$true 3 good faulty1 faulty2 +.names state$_n32_n35$true +faulty2 +# if/else (state == 2) +.mv state$_n32$raw_n36 3 good faulty1 faulty2 +.names state$_n32_n35$true state$_n2b$raw_n31 _n32 state$_n32$raw_n36 +- - 0 =state$_n2b$raw_n31 +- - 1 =state$_n32_n35$true +.mv _n3b 3 good faulty1 faulty2 +.names _n3b +good +# state == 0 +.names state$_n32$raw_n36 _n3b _n3a +.def 0 +- =state$_n32$raw_n36 1 +.names _n3a _n3c +- =_n3a +# state = r_state +.mv state$_n3a_n3d$true 3 good faulty1 faulty2 +.names r_state state$_n3a_n3d$true +- =r_state +.mv _n3f 2 on off +.names _n3f +on +# ts_power == 0 +.names ts_power _n3f _n3e +.def 0 +- =ts_power 1 +.names _n3e _n40 +- =_n3e +# charger = 1 +.mv charger$_n3e_n41$true 2 discharged charged +.names charger$_n3e_n41$true +charged +.mv _n43 2 lit unlit +.names _n43 +lit +# lamp == 0 +.names lamp _n43 _n42 +.def 0 +- =lamp 1 +.names _n42 _n44 +- =_n42 +# charger = 0 +.mv charger$_n42_n45$true 2 discharged charged +.names charger$_n42_n45$true +discharged +# charger = charger +.mv charger$_n42_n46$false 2 discharged charged +.names charger charger$_n42_n46$false +- =charger +# if/else (lamp == 0) +.mv charger$_n42$raw_n49 2 discharged charged +.names charger$_n42_n45$true charger$_n42_n46$false _n42 charger$_n42$raw_n49 +- - 0 =charger$_n42_n46$false +- - 1 =charger$_n42_n45$true +# if/else (ts_power == 0) +.mv charger$_n3e$raw_n51 2 discharged charged +.names charger$_n3e_n41$true charger$_n42$raw_n49 _n3e charger$_n3e$raw_n51 +- - 0 =charger$_n42$raw_n49 +- - 1 =charger$_n3e_n41$true +# if/else (state == 0) +.mv state$_n3a$raw_n58 3 good faulty1 faulty2 +.names state$_n3a_n3d$true state$_n32$raw_n36 _n3a state$_n3a$raw_n58 +- - 0 =state$_n32$raw_n36 +- - 1 =state$_n3a_n3d$true +.mv charger$_n3a$raw_n5b 2 discharged charged +.names charger$_n3e$raw_n51 charger _n3a charger$_n3a$raw_n5b +- - 0 =charger +- - 1 =charger$_n3e$raw_n51 +# conflict arbitrators +.names out$raw_n22 out +- =out$raw_n22 +.names _n3c _n40 _n44 _n5e +.def 0 + 1 1 - 1 + 1 0 1 1 + 1 0 0 1 +.mv _n5f 2 discharged charged +.names _n5e charger$_n3a$raw_n5b charger _n5f +1 - - =charger$_n3a$raw_n5b +0 - - =charger +.names _n2d _n34 _n3c _n66 +.def 0 + 1 - - 1 + - 1 - 1 + - - 1 1 +.mv _n67 3 good faulty1 faulty2 +.names _n66 state$_n3a$raw_n58 state _n67 +1 - - =state$_n3a$raw_n58 +0 - - =state +# non-blocking assignments +# latches +.r charger$raw_n1f charger +- =charger$raw_n1f +.latch _n5f charger +.r state$raw_n1e state +- =state$raw_n1e +.latch _n67 state +# quasi-continuous assignment +.end + + +.model relay_mod +# I/O ports +.inputs charger +.outputs relay + +.mv charger 2 discharged charged +.mv r_state 3 good faulty1 faulty2 +.mv state 3 good faulty1 faulty2 +.mv relay 2 pulling neutral +# state = 0 +.mv state$raw_n6e 3 good faulty1 faulty2 +.names state$raw_n6e +good +# non-blocking assignments for initial +# assign r_state = $NDset ( 0,1,2 ) +.names r_state +good +faulty1 +faulty2 +# assign relay = state == faulty1 ? 1 : state == faulty2 ? 0 : state == good && charger == charged ? 0 : 1 +.mv relay$raw_n71 2 pulling neutral +.mv _n73 3 good faulty1 faulty2 +.names _n73 +faulty1 +# state == 1 +.names state _n73 _n72 +.def 0 +- =state 1 +.mv _n75 3 good faulty1 faulty2 +.names _n75 +faulty2 +# state == 2 +.names state _n75 _n74 +.def 0 +- =state 1 +.mv _n77 3 good faulty1 faulty2 +.names _n77 +good +# state == 0 +.names state _n77 _n76 +.def 0 +- =state 1 +.mv _n79 2 discharged charged +.names _n79 +charged +# charger == 1 +.names charger _n79 _n78 +.def 0 +- =charger 1 +# state == 0 && charger == 1 +.names _n76 _n78 _n7a +.def 0 +1 1 1 +.mv _n7b 2 pulling neutral +.names _n7b +pulling +.mv _n7c 2 pulling neutral +.names _n7c +neutral +# state == 0 && charger == 1 ? 0 : 1 +.mv _n7d 2 pulling neutral +.names _n7b _n7c _n7a _n7d +- - 0 =_n7c +- - 1 =_n7b +.mv _n7e 2 pulling neutral +.names _n7e +pulling +# state == 2 ? 0 : state == 0 && charger == 1 ? 0 : 1 +.mv _n7f 2 pulling neutral +.names _n7e _n7d _n74 _n7f +- - 0 =_n7d +- - 1 =_n7e +.mv _n80 2 pulling neutral +.names _n80 +neutral +# state == 1 ? 1 : state == 2 ? 0 : state == 0 && charger == 1 ? 0 : 1 +.mv _n81 2 pulling neutral +.names _n80 _n7f _n72 _n81 +- - 0 =_n7f +- - 1 =_n80 +.names _n81 relay$raw_n71 +- =_n81 +.mv _n83 3 good faulty1 faulty2 +.names _n83 +faulty1 +# state == 1 +.names state _n83 _n82 +.def 0 +- =state 1 +.names _n82 _n84 +- =_n82 +# state = 1 +.mv state$_n82_n85$true 3 good faulty1 faulty2 +.names state$_n82_n85$true +faulty1 +# if/else (state == 1) +.mv state$_n82$raw_n88 3 good faulty1 faulty2 +.names state$_n82_n85$true state _n82 state$_n82$raw_n88 +- - 0 =state +- - 1 =state$_n82_n85$true +.mv _n8a 3 good faulty1 faulty2 +.names _n8a +faulty2 +# state == 2 +.names state$_n82$raw_n88 _n8a _n89 +.def 0 +- =state$_n82$raw_n88 1 +.names _n89 _n8b +- =_n89 +# state = 2 +.mv state$_n89_n8c$true 3 good faulty1 faulty2 +.names state$_n89_n8c$true +faulty2 +# if/else (state == 2) +.mv state$_n89$raw_n8d 3 good faulty1 faulty2 +.names state$_n89_n8c$true state$_n82$raw_n88 _n89 state$_n89$raw_n8d +- - 0 =state$_n82$raw_n88 +- - 1 =state$_n89_n8c$true +.mv _n92 3 good faulty1 faulty2 +.names _n92 +good +# state == 0 +.names state$_n89$raw_n8d _n92 _n91 +.def 0 +- =state$_n89$raw_n8d 1 +.names _n91 _n93 +- =_n91 +# state = r_state +.mv state$_n91_n94$true 3 good faulty1 faulty2 +.names r_state state$_n91_n94$true +- =r_state +# if/else (state == 0) +.mv state$_n91$raw_n95 3 good faulty1 faulty2 +.names state$_n91_n94$true state$_n89$raw_n8d _n91 state$_n91$raw_n95 +- - 0 =state$_n89$raw_n8d +- - 1 =state$_n91_n94$true +# conflict arbitrators +.names _n84 _n8b _n93 _n99 +.def 0 + 1 - - 1 + - 1 - 1 + - - 1 1 +.mv _n9a 3 good faulty1 faulty2 +.names _n99 state$_n91$raw_n95 state _n9a +1 - - =state$_n91$raw_n95 +0 - - =state +.names relay$raw_n71 relay +- =relay$raw_n71 +# non-blocking assignments +# latches +.r state$raw_n6e state +- =state$raw_n6e +.latch _n9a state +# quasi-continuous assignment +.end + + +.model lamp_mod +# I/O ports +.inputs charger +.inputs wire3 +.inputs ts_power +.outputs lamp +.inputs contact + +.mv charger 2 discharged charged +.mv wire3 2 conduct open +.mv r_state 3 good faulty1 faulty2 +.mv state 3 good faulty1 faulty2 +.mv ts_power 2 on off +.mv lamp 2 lit unlit +.mv contact 3 B middle C +# state = 0 +.mv state$raw_na0 3 good faulty1 faulty2 +.names state$raw_na0 +good +# non-blocking assignments for initial +# assign r_state = $NDset ( 0,1,2 ) +.names r_state +good +faulty1 +faulty2 +# assign lamp = state == faulty1 ? 1 : state == faulty2 ? 0 : state == good && ((contact == C ) && (wire3 == conduct ) && ((ts_power == on ) | (charger == charged ))) ? 0 : 1 +.mv lamp$raw_na3 2 lit unlit +.mv _na5 3 good faulty1 faulty2 +.names _na5 +faulty1 +# state == 1 +.names state _na5 _na4 +.def 0 +- =state 1 +.mv _na7 3 good faulty1 faulty2 +.names _na7 +faulty2 +# state == 2 +.names state _na7 _na6 +.def 0 +- =state 1 +.mv _na9 3 good faulty1 faulty2 +.names _na9 +good +# state == 0 +.names state _na9 _na8 +.def 0 +- =state 1 +.mv _nab 3 B middle C +.names _nab +C +# contact == 2 +.names contact _nab _naa +.def 0 +- =contact 1 +.mv _nad 2 conduct open +.names _nad +conduct +# wire3 == 0 +.names wire3 _nad _nac +.def 0 +- =wire3 1 +# (contact == 2) && (wire3 == 0) +.names _naa _nac _nae +.def 0 +1 1 1 +.mv _nb0 2 on off +.names _nb0 +on +# ts_power == 0 +.names ts_power _nb0 _naf +.def 0 +- =ts_power 1 +.mv _nb2 2 discharged charged +.names _nb2 +charged +# charger == 1 +.names charger _nb2 _nb1 +.def 0 +- =charger 1 +# (ts_power == 0) | (charger == 1) +.names _naf _nb1 _nb3 +.def 1 +0 0 0 +# (contact == 2) && (wire3 == 0) && ((ts_power == 0) | (charger == 1)) +.names _nae _nb3 _nb4 +.def 0 +1 1 1 +# state == 0 && ((contact == 2) && (wire3 == 0) && ((ts_power == 0) | (charger == 1))) +.names _na8 _nb4 _nb5 +.def 0 +1 1 1 +.mv _nb6 2 lit unlit +.names _nb6 +lit +.mv _nb7 2 lit unlit +.names _nb7 +unlit +# state == 0 && ((contact == 2) && (wire3 == 0) && ((ts_power == 0) | (charger == 1))) ? 0 : 1 +.mv _nb8 2 lit unlit +.names _nb6 _nb7 _nb5 _nb8 +- - 0 =_nb7 +- - 1 =_nb6 +.mv _nb9 2 lit unlit +.names _nb9 +lit +# state == 2 ? 0 : state == 0 && ((contact == 2) && (wire3 == 0) && ((ts_power == 0) | (charger == 1))) ? 0 : 1 +.mv _nba 2 lit unlit +.names _nb9 _nb8 _na6 _nba +- - 0 =_nb8 +- - 1 =_nb9 +.mv _nbb 2 lit unlit +.names _nbb +unlit +# state == 1 ? 1 : state == 2 ? 0 : state == 0 && ((contact == 2) && (wire3 == 0) && ((ts_power == 0) | (charger == 1))) ? 0 : 1 +.mv _nbc 2 lit unlit +.names _nbb _nba _na4 _nbc +- - 0 =_nba +- - 1 =_nbb +.names _nbc lamp$raw_na3 +- =_nbc +.mv _nbe 3 good faulty1 faulty2 +.names _nbe +faulty1 +# state == 1 +.names state _nbe _nbd +.def 0 +- =state 1 +.names _nbd _nbf +- =_nbd +# state = 1 +.mv state$_nbd_nc0$true 3 good faulty1 faulty2 +.names state$_nbd_nc0$true +faulty1 +# if/else (state == 1) +.mv state$_nbd$raw_nc3 3 good faulty1 faulty2 +.names state$_nbd_nc0$true state _nbd state$_nbd$raw_nc3 +- - 0 =state +- - 1 =state$_nbd_nc0$true +.mv _nc5 3 good faulty1 faulty2 +.names _nc5 +faulty2 +# state == 2 +.names state$_nbd$raw_nc3 _nc5 _nc4 +.def 0 +- =state$_nbd$raw_nc3 1 +.names _nc4 _nc6 +- =_nc4 +# state = 2 +.mv state$_nc4_nc7$true 3 good faulty1 faulty2 +.names state$_nc4_nc7$true +faulty2 +# if/else (state == 2) +.mv state$_nc4$raw_nc8 3 good faulty1 faulty2 +.names state$_nc4_nc7$true state$_nbd$raw_nc3 _nc4 state$_nc4$raw_nc8 +- - 0 =state$_nbd$raw_nc3 +- - 1 =state$_nc4_nc7$true +.mv _ncd 3 good faulty1 faulty2 +.names _ncd +good +# state == 0 +.names state$_nc4$raw_nc8 _ncd _ncc +.def 0 +- =state$_nc4$raw_nc8 1 +.names _ncc _nce +- =_ncc +# state = r_state +.mv state$_ncc_ncf$true 3 good faulty1 faulty2 +.names r_state state$_ncc_ncf$true +- =r_state +# if/else (state == 0) +.mv state$_ncc$raw_nd0 3 good faulty1 faulty2 +.names state$_ncc_ncf$true state$_nc4$raw_nc8 _ncc state$_ncc$raw_nd0 +- - 0 =state$_nc4$raw_nc8 +- - 1 =state$_ncc_ncf$true +# conflict arbitrators +.names _nbf _nc6 _nce _nd4 +.def 0 + 1 - - 1 + - 1 - 1 + - - 1 1 +.mv _nd5 3 good faulty1 faulty2 +.names _nd4 state$_ncc$raw_nd0 state _nd5 +1 - - =state$_ncc$raw_nd0 +0 - - =state +.names lamp$raw_na3 lamp +- =lamp$raw_na3 +# non-blocking assignments +# latches +.r state$raw_na0 state +- =state$raw_na0 +.latch _nd5 state +# quasi-continuous assignment +.end + + +.model contact_mod +# I/O ports +.outputs contact +.inputs relay + +.mv r_state 3 good faulty1 faulty2 +.mv state 3 good faulty1 faulty2 +.mv contact 3 B middle C +.mv relay 2 pulling neutral +# state = 0 +.mv state$raw_nde 3 good faulty1 faulty2 +.names state$raw_nde +good +# non-blocking assignments for initial +# assign r_state = $NDset ( 0,1,2 ) +.names r_state +good +faulty1 +faulty2 +# assign contact = state == faulty1 ? 0 : state == faulty2 ? 2 : state == good && relay == pulling ? 2 : 0 +.mv contact$raw_ne1 3 B middle C +.mv _ne3 3 good faulty1 faulty2 +.names _ne3 +faulty1 +# state == 1 +.names state _ne3 _ne2 +.def 0 +- =state 1 +.mv _ne5 3 good faulty1 faulty2 +.names _ne5 +faulty2 +# state == 2 +.names state _ne5 _ne4 +.def 0 +- =state 1 +.mv _ne7 3 good faulty1 faulty2 +.names _ne7 +good +# state == 0 +.names state _ne7 _ne6 +.def 0 +- =state 1 +.mv _ne9 2 pulling neutral +.names _ne9 +pulling +# relay == 0 +.names relay _ne9 _ne8 +.def 0 +- =relay 1 +# state == 0 && relay == 0 +.names _ne6 _ne8 _nea +.def 0 +1 1 1 +.mv _neb 3 B middle C +.names _neb +C +.mv _nec 3 B middle C +.names _nec +B +# state == 0 && relay == 0 ? 2 : 0 +.mv _ned 3 B middle C +.names _neb _nec _nea _ned +- - 0 =_nec +- - 1 =_neb +.mv _nee 3 B middle C +.names _nee +C +# state == 2 ? 2 : state == 0 && relay == 0 ? 2 : 0 +.mv _nef 3 B middle C +.names _nee _ned _ne4 _nef +- - 0 =_ned +- - 1 =_nee +.mv _nf0 3 B middle C +.names _nf0 +B +# state == 1 ? 0 : state == 2 ? 2 : state == 0 && relay == 0 ? 2 : 0 +.mv _nf1 3 B middle C +.names _nf0 _nef _ne2 _nf1 +- - 0 =_nef +- - 1 =_nf0 +.names _nf1 contact$raw_ne1 +- =_nf1 +.mv _nf3 3 good faulty1 faulty2 +.names _nf3 +faulty1 +# state == 1 +.names state _nf3 _nf2 +.def 0 +- =state 1 +.names _nf2 _nf4 +- =_nf2 +# state = 1 +.mv state$_nf2_nf5$true 3 good faulty1 faulty2 +.names state$_nf2_nf5$true +faulty1 +# if/else (state == 1) +.mv state$_nf2$raw_nf8 3 good faulty1 faulty2 +.names state$_nf2_nf5$true state _nf2 state$_nf2$raw_nf8 +- - 0 =state +- - 1 =state$_nf2_nf5$true +.mv _nfa 3 good faulty1 faulty2 +.names _nfa +faulty2 +# state == 2 +.names state$_nf2$raw_nf8 _nfa _nf9 +.def 0 +- =state$_nf2$raw_nf8 1 +.names _nf9 _nfb +- =_nf9 +# state = 2 +.mv state$_nf9_nfc$true 3 good faulty1 faulty2 +.names state$_nf9_nfc$true +faulty2 +# if/else (state == 2) +.mv state$_nf9$raw_nfd 3 good faulty1 faulty2 +.names state$_nf9_nfc$true state$_nf2$raw_nf8 _nf9 state$_nf9$raw_nfd +- - 0 =state$_nf2$raw_nf8 +- - 1 =state$_nf9_nfc$true +.mv _n102 3 good faulty1 faulty2 +.names _n102 +good +# state == 0 +.names state$_nf9$raw_nfd _n102 _n101 +.def 0 +- =state$_nf9$raw_nfd 1 +.names _n101 _n103 +- =_n101 +# state = r_state +.mv state$_n101_n104$true 3 good faulty1 faulty2 +.names r_state state$_n101_n104$true +- =r_state +# if/else (state == 0) +.mv state$_n101$raw_n105 3 good faulty1 faulty2 +.names state$_n101_n104$true state$_nf9$raw_nfd _n101 state$_n101$raw_n105 +- - 0 =state$_nf9$raw_nfd +- - 1 =state$_n101_n104$true +# conflict arbitrators +.names _nf4 _nfb _n103 _n109 +.def 0 + 1 - - 1 + - 1 - 1 + - - 1 1 +.mv _n10a 3 good faulty1 faulty2 +.names _n109 state$_n101$raw_n105 state _n10a +1 - - =state$_n101$raw_n105 +0 - - =state +.names contact$raw_ne1 contact +- =contact$raw_ne1 +# non-blocking assignments +# latches +.r state$raw_nde state +- =state$raw_nde +.latch _n10a state +# quasi-continuous assignment +.end + + +.model train_mod +# I/O ports +.outputs out + +.mv r9_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.mv r8_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.mv r6_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.mv r5_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.mv out 3 present1 present2 absent +.mv r10_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.mv r3_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.mv r2_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.mv r4_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.mv r1_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.mv train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.mv r7_train 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +# train = 0 +.mv train$raw_n110 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names train$raw_n110 +t1 +# non-blocking assignments for initial +# assign r1_train = $NDset ( 0,1 ) +.names r1_train +t1 +t2 +# assign r2_train = $NDset ( 1,2 ) +.names r2_train +t2 +t3 +# assign r3_train = $NDset ( 2,3 ) +.names r3_train +t3 +t4 +# assign r4_train = $NDset ( 3,4 ) +.names r4_train +t4 +t5 +# assign r5_train = $NDset ( 4,5 ) +.names r5_train +t5 +t6 +# assign r6_train = $NDset ( 5,6 ) +.names r6_train +t6 +t7 +# assign r7_train = $NDset ( 6,7 ) +.names r7_train +t7 +t8 +# assign r8_train = $NDset ( 7,8 ) +.names r8_train +t8 +t9 +# assign r9_train = $NDset ( 8,9 ) +.names r9_train +t9 +t10 +# assign r10_train = $NDset ( 9,0 ) +.names r10_train +t10 +t1 +# assign out = (train == t1 ) ? 2 : 0 +.mv out$raw_n125 3 present1 present2 absent +.mv _n127 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n127 +t1 +# train == 0 +.names train _n127 _n126 +.def 0 +- =train 1 +.mv _n128 3 present1 present2 absent +.names _n128 +absent +.mv _n129 3 present1 present2 absent +.names _n129 +present1 +# (train == 0) ? 2 : 0 +.mv _n12a 3 present1 present2 absent +.names _n128 _n129 _n126 _n12a +- - 0 =_n129 +- - 1 =_n128 +.names _n12a out$raw_n125 +- =_n12a +.mv _n12d 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n12d +t1 +.names train _n12d _n12c +.def 0 +- =train 1 +.names _n12c _n12b +1 1 +0 0 +# train = r1_train +.mv train$_n12b_n12e$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names r1_train train$_n12b_n12e$true +- =r1_train +.mv _n131 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n131 +t2 +.names train _n131 _n130 +.def 0 +- =train 1 +.names _n130 _n12f +1 1 +0 0 +# train = r2_train +.mv train$_n12f_n132$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names r2_train train$_n12f_n132$true +- =r2_train +.mv _n135 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n135 +t3 +.names train _n135 _n134 +.def 0 +- =train 1 +.names _n134 _n133 +1 1 +0 0 +# train = r3_train +.mv train$_n133_n136$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names r3_train train$_n133_n136$true +- =r3_train +.mv _n139 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n139 +t4 +.names train _n139 _n138 +.def 0 +- =train 1 +.names _n138 _n137 +1 1 +0 0 +# train = r4_train +.mv train$_n137_n13a$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names r4_train train$_n137_n13a$true +- =r4_train +.mv _n13d 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n13d +t5 +.names train _n13d _n13c +.def 0 +- =train 1 +.names _n13c _n13b +1 1 +0 0 +# train = r5_train +.mv train$_n13b_n13e$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names r5_train train$_n13b_n13e$true +- =r5_train +.mv _n141 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n141 +t6 +.names train _n141 _n140 +.def 0 +- =train 1 +.names _n140 _n13f +1 1 +0 0 +# train = r6_train +.mv train$_n13f_n142$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names r6_train train$_n13f_n142$true +- =r6_train +.mv _n145 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n145 +t7 +.names train _n145 _n144 +.def 0 +- =train 1 +.names _n144 _n143 +1 1 +0 0 +# train = r7_train +.mv train$_n143_n146$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names r7_train train$_n143_n146$true +- =r7_train +.mv _n149 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n149 +t8 +.names train _n149 _n148 +.def 0 +- =train 1 +.names _n148 _n147 +1 1 +0 0 +# train = r8_train +.mv train$_n147_n14a$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names r8_train train$_n147_n14a$true +- =r8_train +.mv _n14d 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n14d +t9 +.names train _n14d _n14c +.def 0 +- =train 1 +.names _n14c _n14b +1 1 +0 0 +# train = r9_train +.mv train$_n14b_n14e$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names r9_train train$_n14b_n14e$true +- =r9_train +.mv _n151 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n151 +t10 +.names train _n151 _n150 +.def 0 +- =train 1 +.names _n150 _n14f +1 1 +0 0 +# train = r10_train +.mv train$_n14f_n152$true 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names r10_train train$_n14f_n152$true +- =r10_train +# case (train ) +.mv train$_n14f$raw_n155 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names train$_n14f_n152$true train _n14f train$_n14f$raw_n155 +- - 0 =train +- - 1 =train$_n14f_n152$true +.mv train$_n14b$raw_n156 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names train$_n14b_n14e$true train$_n14f$raw_n155 _n14b train$_n14b$raw_n156 +- - 0 =train$_n14f$raw_n155 +- - 1 =train$_n14b_n14e$true +.mv train$_n147$raw_n15a 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names train$_n147_n14a$true train$_n14b$raw_n156 _n147 train$_n147$raw_n15a +- - 0 =train$_n14b$raw_n156 +- - 1 =train$_n147_n14a$true +.mv train$_n143$raw_n15e 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names train$_n143_n146$true train$_n147$raw_n15a _n143 train$_n143$raw_n15e +- - 0 =train$_n147$raw_n15a +- - 1 =train$_n143_n146$true +.mv train$_n13f$raw_n162 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names train$_n13f_n142$true train$_n143$raw_n15e _n13f train$_n13f$raw_n162 +- - 0 =train$_n143$raw_n15e +- - 1 =train$_n13f_n142$true +.mv train$_n13b$raw_n166 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names train$_n13b_n13e$true train$_n13f$raw_n162 _n13b train$_n13b$raw_n166 +- - 0 =train$_n13f$raw_n162 +- - 1 =train$_n13b_n13e$true +.mv train$_n137$raw_n16a 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names train$_n137_n13a$true train$_n13b$raw_n166 _n137 train$_n137$raw_n16a +- - 0 =train$_n13b$raw_n166 +- - 1 =train$_n137_n13a$true +.mv train$_n133$raw_n16e 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names train$_n133_n136$true train$_n137$raw_n16a _n133 train$_n133$raw_n16e +- - 0 =train$_n137$raw_n16a +- - 1 =train$_n133_n136$true +.mv train$_n12f$raw_n172 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names train$_n12f_n132$true train$_n133$raw_n16e _n12f train$_n12f$raw_n172 +- - 0 =train$_n133$raw_n16e +- - 1 =train$_n12f_n132$true +.mv train$_n12b$raw_n176 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names train$_n12b_n12e$true train$_n12f$raw_n172 _n12b train$_n12b$raw_n176 +- - 0 =train$_n12f$raw_n172 +- - 1 =train$_n12b_n12e$true +# conflict arbitrators +.names out$raw_n125 out +- =out$raw_n125 +.names _n12b _n12f _n133 _n137 _n13b _n13f _n143 _n147 _n14b _n14f _n17a +.def 0 + 1 - - - - - - - - - 1 + 0 1 - - - - - - - - 1 + 0 0 1 - - - - - - - 1 + 0 0 0 1 - - - - - - 1 + 0 0 0 0 1 - - - - - 1 + 0 0 0 0 0 1 - - - - 1 + 0 0 0 0 0 0 1 - - - 1 + 0 0 0 0 0 0 0 1 - - 1 + 0 0 0 0 0 0 0 0 1 - 1 + 0 0 0 0 0 0 0 0 0 1 1 +.mv _n17b 10 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 +.names _n17a train$_n12b$raw_n176 train _n17b +1 - - =train$_n12b$raw_n176 +0 - - =train +# non-blocking assignments +# latches +.r train$raw_n110 train +- =train$raw_n110 +.latch _n17b train +# quasi-continuous assignment +.end + + +.model track_system_mod +# I/O ports +.inputs wire1 +.inputs wire2 +.outputs ts_power +.inputs train +.inputs contact + +.mv wire1 2 conduct open +.mv wire2 2 conduct open +.mv r_state 3 good faulty1 faulty2 +.mv state 3 good faulty1 faulty2 +.mv ts_power 2 on off +.mv train 3 present1 present2 absent +.mv contact 3 B middle C +# state = 0 +.mv state$raw_n192 3 good faulty1 faulty2 +.names state$raw_n192 +good +# non-blocking assignments for initial +# assign r_state = $NDset ( 0,1,2 ) +.names r_state +good +faulty1 +faulty2 +# assign ts_power = state == faulty1 ? 0 : state == faulty2 ? 1 : state == good && ((wire1 == conduct ) && (wire2 == conduct ) && ((train != absent ) | (contact == B ))) ? 0 : 1 +.mv ts_power$raw_n195 2 on off +.mv _n197 3 good faulty1 faulty2 +.names _n197 +faulty1 +# state == 1 +.names state _n197 _n196 +.def 0 +- =state 1 +.mv _n199 3 good faulty1 faulty2 +.names _n199 +faulty2 +# state == 2 +.names state _n199 _n198 +.def 0 +- =state 1 +.mv _n19b 3 good faulty1 faulty2 +.names _n19b +good +# state == 0 +.names state _n19b _n19a +.def 0 +- =state 1 +.mv _n19d 2 conduct open +.names _n19d +conduct +# wire1 == 0 +.names wire1 _n19d _n19c +.def 0 +- =wire1 1 +.mv _n19f 2 conduct open +.names _n19f +conduct +# wire2 == 0 +.names wire2 _n19f _n19e +.def 0 +- =wire2 1 +# (wire1 == 0) && (wire2 == 0) +.names _n19c _n19e _n1a0 +.def 0 +1 1 1 +.mv _n1a2 3 present1 present2 absent +.names _n1a2 +absent +# train != 2 +.names train _n1a2 _n1a1 +.def 1 +- =train 0 +.mv _n1a4 3 B middle C +.names _n1a4 +B +# contact == 0 +.names contact _n1a4 _n1a3 +.def 0 +- =contact 1 +# (train != 2) | (contact == 0) +.names _n1a1 _n1a3 _n1a5 +.def 1 +0 0 0 +# (wire1 == 0) && (wire2 == 0) && ((train != 2) | (contact == 0)) +.names _n1a0 _n1a5 _n1a6 +.def 0 +1 1 1 +# state == 0 && ((wire1 == 0) && (wire2 == 0) && ((train != 2) | (contact == 0))) +.names _n19a _n1a6 _n1a7 +.def 0 +1 1 1 +.mv _n1a8 2 on off +.names _n1a8 +on +.mv _n1a9 2 on off +.names _n1a9 +off +# state == 0 && ((wire1 == 0) && (wire2 == 0) && ((train != 2) | (contact == 0))) ? 0 : 1 +.mv _n1aa 2 on off +.names _n1a8 _n1a9 _n1a7 _n1aa +- - 0 =_n1a9 +- - 1 =_n1a8 +.mv _n1ab 2 on off +.names _n1ab +off +# state == 2 ? 1 : state == 0 && ((wire1 == 0) && (wire2 == 0) && ((train != 2) | (contact == 0))) ? 0 : 1 +.mv _n1ac 2 on off +.names _n1ab _n1aa _n198 _n1ac +- - 0 =_n1aa +- - 1 =_n1ab +.mv _n1ad 2 on off +.names _n1ad +on +# state == 1 ? 0 : state == 2 ? 1 : state == 0 && ((wire1 == 0) && (wire2 == 0) && ((train != 2) | (contact == 0))) ? 0 : 1 +.mv _n1ae 2 on off +.names _n1ad _n1ac _n196 _n1ae +- - 0 =_n1ac +- - 1 =_n1ad +.names _n1ae ts_power$raw_n195 +- =_n1ae +.mv _n1b0 3 good faulty1 faulty2 +.names _n1b0 +faulty1 +# state == 1 +.names state _n1b0 _n1af +.def 0 +- =state 1 +.names _n1af _n1b1 +- =_n1af +# state = 1 +.mv state$_n1af_n1b2$true 3 good faulty1 faulty2 +.names state$_n1af_n1b2$true +faulty1 +# if/else (state == 1) +.mv state$_n1af$raw_n1b5 3 good faulty1 faulty2 +.names state$_n1af_n1b2$true state _n1af state$_n1af$raw_n1b5 +- - 0 =state +- - 1 =state$_n1af_n1b2$true +.mv _n1b7 3 good faulty1 faulty2 +.names _n1b7 +faulty2 +# state == 2 +.names state$_n1af$raw_n1b5 _n1b7 _n1b6 +.def 0 +- =state$_n1af$raw_n1b5 1 +.names _n1b6 _n1b8 +- =_n1b6 +# state = 2 +.mv state$_n1b6_n1b9$true 3 good faulty1 faulty2 +.names state$_n1b6_n1b9$true +faulty2 +# if/else (state == 2) +.mv state$_n1b6$raw_n1ba 3 good faulty1 faulty2 +.names state$_n1b6_n1b9$true state$_n1af$raw_n1b5 _n1b6 state$_n1b6$raw_n1ba +- - 0 =state$_n1af$raw_n1b5 +- - 1 =state$_n1b6_n1b9$true +.mv _n1bf 3 good faulty1 faulty2 +.names _n1bf +good +# state == 0 +.names state$_n1b6$raw_n1ba _n1bf _n1be +.def 0 +- =state$_n1b6$raw_n1ba 1 +.names _n1be _n1c0 +- =_n1be +# state = r_state +.mv state$_n1be_n1c1$true 3 good faulty1 faulty2 +.names r_state state$_n1be_n1c1$true +- =r_state +# if/else (state == 0) +.mv state$_n1be$raw_n1c2 3 good faulty1 faulty2 +.names state$_n1be_n1c1$true state$_n1b6$raw_n1ba _n1be state$_n1be$raw_n1c2 +- - 0 =state$_n1b6$raw_n1ba +- - 1 =state$_n1be_n1c1$true +# conflict arbitrators +.names _n1b1 _n1b8 _n1c0 _n1c6 +.def 0 + 1 - - 1 + - 1 - 1 + - - 1 1 +.mv _n1c7 3 good faulty1 faulty2 +.names _n1c6 state$_n1be$raw_n1c2 state _n1c7 +1 - - =state$_n1be$raw_n1c2 +0 - - =state +.names ts_power$raw_n195 ts_power +- =ts_power$raw_n195 +# non-blocking assignments +# latches +.r state$raw_n192 state +- =state$raw_n192 +.latch _n1c7 state +# quasi-continuous assignment +.end + + +.model interpretation_mod +# I/O ports +.outputs out +.inputs lamp + +.mv out 2 go stop +.mv state 6 stop1 stop2 go1 go2 go3 go4 +.mv lamp 2 lit unlit +# state = 0 +.mv state$raw_n1cf 6 stop1 stop2 go1 go2 go3 go4 +.names state$raw_n1cf +stop1 +# non-blocking assignments for initial +# assign out = state == go3 | state == go4 ? 0 : 1 +.mv out$raw_n1d0 2 go stop +.mv _n1d2 6 stop1 stop2 go1 go2 go3 go4 +.names _n1d2 +go3 +# state == 4 +.names state _n1d2 _n1d1 +.def 0 +- =state 1 +.mv _n1d4 6 stop1 stop2 go1 go2 go3 go4 +.names _n1d4 +go4 +# state == 5 +.names state _n1d4 _n1d3 +.def 0 +- =state 1 +# state == 4 | state == 5 +.names _n1d1 _n1d3 _n1d5 +.def 1 +0 0 0 +.mv _n1d6 2 go stop +.names _n1d6 +go +.mv _n1d7 2 go stop +.names _n1d7 +stop +# state == 4 | state == 5 ? 0 : 1 +.mv _n1d8 2 go stop +.names _n1d6 _n1d7 _n1d5 _n1d8 +- - 0 =_n1d7 +- - 1 =_n1d6 +.names _n1d8 out$raw_n1d0 +- =_n1d8 +.mv _n1db 6 stop1 stop2 go1 go2 go3 go4 +.names _n1db +stop1 +.names state _n1db _n1da +.def 0 +- =state 1 +.names _n1da _n1d9 +1 1 +0 0 +.mv _n1dd 2 lit unlit +.names _n1dd +lit +# lamp == 0 +.names lamp _n1dd _n1dc +.def 0 +- =lamp 1 +.names _n1dc _n1de +- =_n1dc +# state = 1 +.mv state$_n1dc_n1df$true 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1dc_n1df$true +stop2 +# state = 0 +.mv state$_n1dc_n1e0$false 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1dc_n1e0$false +stop1 +# if/else (lamp == 0) +.mv state$_n1dc$raw_n1e2 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1dc_n1df$true state$_n1dc_n1e0$false _n1dc state$_n1dc$raw_n1e2 +- - 0 =state$_n1dc_n1e0$false +- - 1 =state$_n1dc_n1df$true +.mv _n1e7 6 stop1 stop2 go1 go2 go3 go4 +.names _n1e7 +stop2 +.names state _n1e7 _n1e6 +.def 0 +- =state 1 +.names _n1e6 _n1e5 +1 1 +0 0 +.mv _n1e9 2 lit unlit +.names _n1e9 +unlit +# lamp == 1 +.names lamp _n1e9 _n1e8 +.def 0 +- =lamp 1 +.names _n1e8 _n1ea +- =_n1e8 +# state = 2 +.mv state$_n1e8_n1eb$true 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1e8_n1eb$true +go1 +# state = 0 +.mv state$_n1e8_n1ec$false 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1e8_n1ec$false +stop1 +# if/else (lamp == 1) +.mv state$_n1e8$raw_n1ee 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1e8_n1eb$true state$_n1e8_n1ec$false _n1e8 state$_n1e8$raw_n1ee +- - 0 =state$_n1e8_n1ec$false +- - 1 =state$_n1e8_n1eb$true +.mv _n1f3 6 stop1 stop2 go1 go2 go3 go4 +.names _n1f3 +go1 +.names state _n1f3 _n1f2 +.def 0 +- =state 1 +.names _n1f2 _n1f1 +1 1 +0 0 +.mv _n1f5 2 lit unlit +.names _n1f5 +lit +# lamp == 0 +.names lamp _n1f5 _n1f4 +.def 0 +- =lamp 1 +.names _n1f4 _n1f6 +- =_n1f4 +# state = 3 +.mv state$_n1f4_n1f7$true 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1f4_n1f7$true +go2 +# state = 0 +.mv state$_n1f4_n1f8$false 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1f4_n1f8$false +stop1 +# if/else (lamp == 0) +.mv state$_n1f4$raw_n1fa 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1f4_n1f7$true state$_n1f4_n1f8$false _n1f4 state$_n1f4$raw_n1fa +- - 0 =state$_n1f4_n1f8$false +- - 1 =state$_n1f4_n1f7$true +.mv _n1ff 6 stop1 stop2 go1 go2 go3 go4 +.names _n1ff +go2 +.names state _n1ff _n1fe +.def 0 +- =state 1 +.names _n1fe _n1fd +1 1 +0 0 +.mv _n201 2 lit unlit +.names _n201 +unlit +# lamp == 1 +.names lamp _n201 _n200 +.def 0 +- =lamp 1 +.names _n200 _n202 +- =_n200 +# state = 4 +.mv state$_n200_n203$true 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n200_n203$true +go3 +# state = 0 +.mv state$_n200_n204$false 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n200_n204$false +stop1 +# if/else (lamp == 1) +.mv state$_n200$raw_n206 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n200_n203$true state$_n200_n204$false _n200 state$_n200$raw_n206 +- - 0 =state$_n200_n204$false +- - 1 =state$_n200_n203$true +.mv _n20b 6 stop1 stop2 go1 go2 go3 go4 +.names _n20b +go3 +.names state _n20b _n20a +.def 0 +- =state 1 +.names _n20a _n209 +1 1 +0 0 +.mv _n20d 2 lit unlit +.names _n20d +lit +# lamp == 0 +.names lamp _n20d _n20c +.def 0 +- =lamp 1 +.names _n20c _n20e +- =_n20c +# state = 5 +.mv state$_n20c_n20f$true 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n20c_n20f$true +go4 +# state = 0 +.mv state$_n20c_n210$false 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n20c_n210$false +stop1 +# if/else (lamp == 0) +.mv state$_n20c$raw_n212 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n20c_n20f$true state$_n20c_n210$false _n20c state$_n20c$raw_n212 +- - 0 =state$_n20c_n210$false +- - 1 =state$_n20c_n20f$true +.mv _n217 6 stop1 stop2 go1 go2 go3 go4 +.names _n217 +go4 +.names state _n217 _n216 +.def 0 +- =state 1 +.names _n216 _n215 +1 1 +0 0 +.mv _n219 2 lit unlit +.names _n219 +unlit +# lamp == 1 +.names lamp _n219 _n218 +.def 0 +- =lamp 1 +.names _n218 _n21a +- =_n218 +# state = 4 +.mv state$_n218_n21b$true 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n218_n21b$true +go3 +# state = 0 +.mv state$_n218_n21c$false 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n218_n21c$false +stop1 +# if/else (lamp == 1) +.mv state$_n218$raw_n21e 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n218_n21b$true state$_n218_n21c$false _n218 state$_n218$raw_n21e +- - 0 =state$_n218_n21c$false +- - 1 =state$_n218_n21b$true +# case (state ) +.mv state$_n215$raw_n223 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n218$raw_n21e state _n215 state$_n215$raw_n223 +- - 0 =state +- - 1 =state$_n218$raw_n21e +.mv state$_n209$raw_n224 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n20c$raw_n212 state$_n215$raw_n223 _n209 state$_n209$raw_n224 +- - 0 =state$_n215$raw_n223 +- - 1 =state$_n20c$raw_n212 +.mv state$_n1fd$raw_n228 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n200$raw_n206 state$_n209$raw_n224 _n1fd state$_n1fd$raw_n228 +- - 0 =state$_n209$raw_n224 +- - 1 =state$_n200$raw_n206 +.mv state$_n1f1$raw_n22c 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1f4$raw_n1fa state$_n1fd$raw_n228 _n1f1 state$_n1f1$raw_n22c +- - 0 =state$_n1fd$raw_n228 +- - 1 =state$_n1f4$raw_n1fa +.mv state$_n1e5$raw_n230 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1e8$raw_n1ee state$_n1f1$raw_n22c _n1e5 state$_n1e5$raw_n230 +- - 0 =state$_n1f1$raw_n22c +- - 1 =state$_n1e8$raw_n1ee +.mv state$_n1d9$raw_n234 6 stop1 stop2 go1 go2 go3 go4 +.names state$_n1dc$raw_n1e2 state$_n1e5$raw_n230 _n1d9 state$_n1d9$raw_n234 +- - 0 =state$_n1e5$raw_n230 +- - 1 =state$_n1dc$raw_n1e2 +# conflict arbitrators +.names out$raw_n1d0 out +- =out$raw_n1d0 +.names _n1d9 _n1de _n1e5 _n1ea _n1f1 _n1f6 _n1fd _n202 _n209 _n20e _n215 _n21a _n238 +.def 0 + 1 1 - - - - - - - - - - 1 + 1 0 - - - - - - - - - - 1 + 0 - 1 1 - - - - - - - - 1 + 0 - 1 0 - - - - - - - - 1 + 0 - 0 - 1 1 - - - - - - 1 + 0 - 0 - 1 0 - - - - - - 1 + 0 - 0 - 0 - 1 1 - - - - 1 + 0 - 0 - 0 - 1 0 - - - - 1 + 0 - 0 - 0 - 0 - 1 1 - - 1 + 0 - 0 - 0 - 0 - 1 0 - - 1 + 0 - 0 - 0 - 0 - 0 - 1 1 1 + 0 - 0 - 0 - 0 - 0 - 1 0 1 +.mv _n239 6 stop1 stop2 go1 go2 go3 go4 +.names _n238 state$_n1d9$raw_n234 state _n239 +1 - - =state$_n1d9$raw_n234 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n1cf state +- =state$raw_n1cf +.latch _n239 state +# quasi-continuous assignment +.end + + +.model property_mod +# I/O ports +.inputs interpretation +.inputs train + +.mv interpretation 2 go stop +.mv state 2 good bad +.mv train 3 present1 present2 absent +# state = 0 +.mv state$raw_n23d 2 good bad +.names state$raw_n23d +good +# non-blocking assignments for initial +.mv _n23f 3 present1 present2 absent +.names _n23f +present2 +# train == 1 +.names train _n23f _n23e +.def 0 +- =train 1 +.mv _n241 2 go stop +.names _n241 +go +# interpretation == 0 +.names interpretation _n241 _n240 +.def 0 +- =interpretation 1 +# (train == 1) && (interpretation == 0) +.names _n23e _n240 _n242 +.def 0 +1 1 1 +.mv _n244 2 good bad +.names _n244 +bad +# state == 1 +.names state _n244 _n243 +.def 0 +- =state 1 +# ((train == 1) && (interpretation == 0)) | (state == 1) +.names _n242 _n243 _n245 +.def 1 +0 0 0 +.names _n245 _n246 +- =_n245 +# state = 1 +.mv state$_n245_n247$true 2 good bad +.names state$_n245_n247$true +bad +# state = 0 +.mv state$_n245_n248$false 2 good bad +.names state$_n245_n248$false +good +# if/else (((train == 1) && (interpretation == 0)) | (state == 1)) +.mv state$_n245$raw_n24a 2 good bad +.names state$_n245_n247$true state$_n245_n248$false _n245 state$_n245$raw_n24a +- - 0 =state$_n245_n248$false +- - 1 =state$_n245_n247$true +# conflict arbitrators +.names _n246 _n24d +.def 0 + 1 1 + 0 1 +.mv _n24e 2 good bad +.names _n24d state$_n245$raw_n24a state _n24e +1 - - =state$_n245$raw_n24a +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n23d state +- =state$raw_n23d +.latch _n24e state +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/dcnew/dcnew.v =================================================================== --- vis_dev/vis-2.1/examples/dcnew/dcnew.v (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/dcnew.v (revision 11) @@ -0,0 +1,353 @@ +/* This model has for each component a failure mode that allows the +component to nondeterministically fail, from which it can not +recover. Each model has a failure mode that is realistic. */ + +/************************************************************************/ + typedef enum{conduct,open} WR; + typedef enum{discharged, charged} CH; + typedef enum{pulling,neutral} RL; + typedef enum{lit,unlit} LP; + typedef enum{B,middle,C} CT; + typedef enum{present1,present2, absent} TR; + typedef enum{on,off} TS; + typedef enum{good, faulty1, faulty2} FT; + typedef enum{go,stop} IN; + typedef enum{stop1, stop2, go1, go2, go3, go4} ST; + typedef enum{t1, t2, t3, t4, t5, t6, t7, t8,t9,t10} TRS; + +module dchek(clk); + input clk; + + WR wire track1, track2, track3; + CH wire charger; + RL wire relay; + LP wire lamp; + CT wire contact; + TR wire train; + TS wire ts_power; + IN wire interpretation; + + track_mod trk1(clk,track1); + track_mod trk2(clk,track2); + track_mod trk3(clk,track3); + charger_mod chg(clk,ts_power,lamp,charger); + relay_mod rly(clk,charger,relay); + lamp_mod lmp(clk,contact,track3,ts_power,charger,lamp); + contact_mod cnt(clk,relay,contact); + train_mod trn(clk,train); + track_system_mod tsm(clk,track1,track2,train,contact,ts_power); + interpretation_mod int(clk,lamp,interpretation); + + property_mod prop(clk, train, interpretation); + +endmodule /* dychek */ + +/************************************************************************/ +module track_mod(clk, track); + input clk; + output track; + WR wire track; + FT reg state; + FT wire r_state; + initial state = good; +assign r_state = $ND(good,faulty1); +assign track = (state == good)?conduct:open; + +always @(posedge clk) begin + if (state == faulty1) begin + state = faulty1; +// track = open; + end + if (state == good) begin + state = r_state; +// track = conduct; + end + end +endmodule /* track_mod */ + +/************************************************************************/ +module charger_mod (clk,ts_power,lamp, out); + input clk,ts_power,lamp; + output out; + TS wire ts_power; + LP wire lamp; + CH wire out; + CH reg charger; + FT reg state; + FT wire r_state; + initial state = good; + initial charger = discharged; +assign r_state = $ND(good,faulty1,faulty2); +assign out = state == faulty1?discharged: + state == faulty2?charged: + charger; + +always @(posedge clk) begin + if (state == faulty1) begin + state = faulty1; +// out = discharged; + end + if (state == faulty2) begin + state = faulty2; +// out = charged; + end + if (state == good) begin + state = r_state; +// out = charger; + if (ts_power == on) charger = charged; + else if (lamp == lit) charger = discharged; + else charger = charger; + end + end +endmodule /* charger_mod */ + +/************************************************************************/ +module relay_mod (clk, charger, relay); + input clk, charger; + output relay; + CH wire charger; + RL wire relay; + FT reg state; + FT wire r_state; + initial state = good; +assign r_state = $ND(good,faulty1,faulty2); +assign relay = state == faulty1?neutral: + state == faulty2?pulling: + state == good && charger == charged?pulling:neutral; + +always @(posedge clk) begin + if (state == faulty1) begin + state = faulty1; +// relay = neutral; + end + if (state == faulty2) begin + state = faulty2; +// relay = pulling; + end + if (state == good) begin + state = r_state; +// if (charger == charged) relay = pulling; +// else relay = neutral; + end +end +endmodule /* relay_mod */ + +/************************************************************************/ +module contact_mod(clk,relay,contact); + input clk,relay; + output contact; + RL wire relay; + CT wire contact; + FT reg state; + FT wire r_state; + initial state = good; +assign r_state = $ND(good,faulty1,faulty2); +assign contact = state == faulty1?B: + state == faulty2?C: + state == good && relay == pulling?C:B; + +always @(posedge clk) begin + if (state == faulty1) begin + state = faulty1; +// contact = B; + end + if (state == faulty2) begin + state = faulty2; +// contact = C; + end + if (state == good) begin + state = r_state; +// if (relay == pulling) contact = C; +// else contact = B; + end +end +endmodule /* contact_mod */ + +/************************************************************************/ +module train_mod (clk, out); + input clk; + output out; + TR wire out; + TRS reg train; + TRS wire r1_train; + TRS wire r2_train; + TRS wire r3_train; + TRS wire r4_train; + TRS wire r5_train; + TRS wire r6_train; + TRS wire r7_train; + TRS wire r8_train; + TRS wire r9_train; + TRS wire r10_train; + initial train = t1; +assign r1_train = $ND(t1,t2); +assign r2_train = $ND(t2,t3); +assign r3_train = $ND(t3,t4); +assign r4_train = $ND(t4,t5); +assign r5_train = $ND(t5,t6); +assign r6_train = $ND(t6,t7); +assign r7_train = $ND(t7,t8); +assign r8_train = $ND(t8,t9); +assign r9_train = $ND(t9,t10); +assign r10_train = $ND(t10,t1); +assign out = (train == t1)? absent : present1; + +always @(posedge clk) begin + case (train) + t1: train = r1_train; + t2: train = r2_train; + t3: train = r3_train; + t4: train = r4_train; + t5: train = r5_train; + t6: train = r6_train; + t7: train = r7_train; + t8: train = r8_train; + t9: train = r9_train; + t10: train = r10_train; + endcase +end +endmodule /* train_mod */ + +/************************************************************************/ +module lamp_mod (clk, contact, wire3, ts_power, charger, lamp); + input clk, contact, wire3, ts_power, charger; + output lamp; + CT wire contact; + WR wire wire3; + CH wire charger; + TS wire ts_power; + LP wire lamp; + FT reg state; + FT wire r_state; + initial state = good; +assign r_state = $ND(good,faulty1,faulty2); +assign lamp = state == faulty1? unlit: + state == faulty2? lit: + state == good && ((contact == C)&&(wire3 == conduct)&& + ((ts_power == on) | (charger == charged)))?lit:unlit; + +always @(posedge clk) begin + if (state == faulty1) begin + state = faulty1; +// lamp = unlit; + end + if (state == faulty2) begin + state = faulty2; +// lamp = lit; + end + if (state == good) begin + state = r_state; +// if ((contact == C)&&(wire3 == conduct)&& +// ((ts_power == on) | (charger == charged))) +// lamp = lit; +// else lamp = unlit; + end +end +endmodule /* lamp_mod */ + +/************************************************************************/ +module track_system_mod (clk, wire1, wire2, train, contact, ts_power); + input clk, wire1, wire2, contact, train; + output ts_power; + TR wire train; + WR wire wire1, wire2; + CT wire contact; + TS wire ts_power; + FT reg state; + FT wire r_state; + initial state = good; +assign r_state = $ND(good,faulty1,faulty2); +assign ts_power = state == faulty1?on: + state == faulty2?off: + state == good && ((wire1 == conduct) && (wire2 == conduct) && + ((train != absent) | (contact == B)))?on:off; + +always @(posedge clk) begin + if (state == faulty1) begin + state = faulty1; +// ts_power = on; + end + if (state == faulty2) begin + state = faulty2; +// ts_power = off; + end + if (state == good) begin + state = r_state; +// if ((wire1 == conduct) && (wire2 == conduct) && +// ((train != absent) | (contact == B))) +// ts_power = on; +// else ts_power = off; + end +end +endmodule /* track_system_mod */ + +/************************************************************************/ +module interpretation_mod (clk, lamp, out); + input clk, lamp; + output out; + LP wire lamp; + IN wire out; + ST reg state; + initial state = stop1; + +assign out = state == go3 | state == go4?go:stop; + +always @(posedge clk) begin + case(state) + stop1: begin + if (lamp == lit) state = stop2; + else state = stop1; + end + + stop2: begin + if (lamp == unlit) state = go1; + else state = stop1; + end + + go1: begin + if (lamp == lit) state = go2; + else state = stop1; + end + + go2: begin + if (lamp == unlit) state = go3; + else state = stop1; + end + + go3: begin + if (lamp == lit) state = go4; + else state = stop1; + end + + go4: begin + if (lamp == unlit) state = go3; + else state = stop1; + end + endcase +// if ((state == go3) | (state == go4)) out = go; +/* if (state == go3 | go4) out = go; */ +// else out = stop; +end +endmodule /* interpretation_mod */ + + typedef enum{good,bad} STT; + +/************************************************************************/ +module property_mod (clk, train, interpretation); + input clk,train,interpretation; + TR wire train; + IN wire interpretation; + STT reg state; + initial state = good; + +always @(posedge clk) begin + if (((train == present2)&&(interpretation == go)) | (state == bad)) + state = bad; + else state = good; +end +endmodule /* property_mod */ + +/* we want to put a cycle set around state = good, so that if ever + state gets to bad it is a non-safe failure. */ + +/************************************************************************/ Index: vis_dev/vis-2.1/examples/dcnew/osc2.ctl =================================================================== --- vis_dev/vis-2.1/examples/dcnew/osc2.ctl (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/osc2.ctl (revision 11) @@ -0,0 +1,1 @@ +AG(((lamp = lit)->EX(lamp=unlit))*((lamp=unlit)->EX(lamp=lit))); Index: vis_dev/vis-2.1/examples/dcnew/osc3.ctl =================================================================== --- vis_dev/vis-2.1/examples/dcnew/osc3.ctl (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/osc3.ctl (revision 11) @@ -0,0 +1,1 @@ +EF((int.state=go3)+(int.state=go4)); Index: vis_dev/vis-2.1/examples/dcnew/osc4.ctl =================================================================== --- vis_dev/vis-2.1/examples/dcnew/osc4.ctl (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/osc4.ctl (revision 11) @@ -0,0 +1,1 @@ +EF EG((int.state=go3)+(int.state=go4)); Index: vis_dev/vis-2.1/examples/dcnew/osc5.ctl =================================================================== --- vis_dev/vis-2.1/examples/dcnew/osc5.ctl (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/osc5.ctl (revision 11) @@ -0,0 +1,1 @@ +!EF EG((int.state=go3)+(int.state=go4)); Index: vis_dev/vis-2.1/examples/dcnew/osc6.ctl =================================================================== --- vis_dev/vis-2.1/examples/dcnew/osc6.ctl (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/osc6.ctl (revision 11) @@ -0,0 +1,2 @@ +#!EFEG((int.state:go3)+(int.state:go4)); +AG AF(!(int.state=go3)*!(int.state=go4)); Index: vis_dev/vis-2.1/examples/dcnew/prop.fair =================================================================== --- vis_dev/vis-2.1/examples/dcnew/prop.fair (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/prop.fair (revision 11) @@ -0,0 +1,12 @@ +#.properties +#.automaton prop +#.blifmv prop.mv +#.connections (train=train, interpretation=interpretation) +#.state st1 = state:good +#.posfair +#.subsets {st1} +#.endfair +#.endautomaton +#.endproperties + +!(prop.state = good); Index: vis_dev/vis-2.1/examples/dcnew/safe.ctl =================================================================== --- vis_dev/vis-2.1/examples/dcnew/safe.ctl (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/safe.ctl (revision 11) @@ -0,0 +1,1 @@ +AG((interpretation = go) -> (train = absent)); Index: vis_dev/vis-2.1/examples/dcnew/safe1.ctl =================================================================== --- vis_dev/vis-2.1/examples/dcnew/safe1.ctl (revision 11) +++ vis_dev/vis-2.1/examples/dcnew/safe1.ctl (revision 11) @@ -0,0 +1,1 @@ +AG((interpretation = go) -> !(train = present2)); Index: vis_dev/vis-2.1/examples/eight_queens/README =================================================================== --- vis_dev/vis-2.1/examples/eight_queens/README (revision 11) +++ vis_dev/vis-2.1/examples/eight_queens/README (revision 11) @@ -0,0 +1,9 @@ + +eight_queens.v: + +This example illustrates a reduction of the 8 queens problem to +combinational equivalence checking. In particular, the design +in eight_queens.v computes a 64 input, single output boolean function +which is true iff the input is a valid positioning of queens +on the chessboard. + Index: vis_dev/vis-2.1/examples/eight_queens/check_result =================================================================== --- vis_dev/vis-2.1/examples/eight_queens/check_result (revision 11) +++ vis_dev/vis-2.1/examples/eight_queens/check_result (revision 11) @@ -0,0 +1,1 @@ +game combinational=6293 pi=0 po=1 latches=0 pseudo=64 const=112 edges=9028 Index: vis_dev/vis-2.1/examples/eight_queens/check_script =================================================================== --- vis_dev/vis-2.1/examples/eight_queens/check_script (revision 11) +++ vis_dev/vis-2.1/examples/eight_queens/check_script (revision 11) @@ -0,0 +1,4 @@ +read_blif_mv eight_queens.mv +init_verify +print_network_stats +quit -s Index: vis_dev/vis-2.1/examples/eight_queens/eight_queens.mv =================================================================== --- vis_dev/vis-2.1/examples/eight_queens/eight_queens.mv (revision 11) +++ vis_dev/vis-2.1/examples/eight_queens/eight_queens.mv (revision 11) @@ -0,0 +1,1887 @@ +# vl2mv eight_queens.v +# version: 0.2 +# date: 11:14:02 12/11/95 (PST) +.model game +# I/O ports +.outputs consistent + +# assign a11 = $NDset ( 0,1 ) +.names a11 +0 +1 +# assign a12 = $NDset ( 0,1 ) +.names a12 +0 +1 +# assign a13 = $NDset ( 0,1 ) +.names a13 +0 +1 +# assign a14 = $NDset ( 0,1 ) +.names a14 +0 +1 +# assign a15 = $NDset ( 0,1 ) +.names a15 +0 +1 +# assign a16 = $NDset ( 0,1 ) +.names a16 +0 +1 +# assign a17 = $NDset ( 0,1 ) +.names a17 +0 +1 +# assign a18 = $NDset ( 0,1 ) +.names a18 +0 +1 +# assign a21 = $NDset ( 0,1 ) +.names a21 +0 +1 +# assign a22 = $NDset ( 0,1 ) +.names a22 +0 +1 +# assign a23 = $NDset ( 0,1 ) +.names a23 +0 +1 +# assign a24 = $NDset ( 0,1 ) +.names a24 +0 +1 +# assign a25 = $NDset ( 0,1 ) +.names a25 +0 +1 +# assign a26 = $NDset ( 0,1 ) +.names a26 +0 +1 +# assign a27 = $NDset ( 0,1 ) +.names a27 +0 +1 +# assign a28 = $NDset ( 0,1 ) +.names a28 +0 +1 +# assign a31 = $NDset ( 0,1 ) +.names a31 +0 +1 +# assign a32 = $NDset ( 0,1 ) +.names a32 +0 +1 +# assign a33 = $NDset ( 0,1 ) +.names a33 +0 +1 +# assign a34 = $NDset ( 0,1 ) +.names a34 +0 +1 +# assign a35 = $NDset ( 0,1 ) +.names a35 +0 +1 +# assign a36 = $NDset ( 0,1 ) +.names a36 +0 +1 +# assign a37 = $NDset ( 0,1 ) +.names a37 +0 +1 +# assign a38 = $NDset ( 0,1 ) +.names a38 +0 +1 +# assign a41 = $NDset ( 0,1 ) +.names a41 +0 +1 +# assign a42 = $NDset ( 0,1 ) +.names a42 +0 +1 +# assign a43 = $NDset ( 0,1 ) +.names a43 +0 +1 +# assign a44 = $NDset ( 0,1 ) +.names a44 +0 +1 +# assign a45 = $NDset ( 0,1 ) +.names a45 +0 +1 +# assign a46 = $NDset ( 0,1 ) +.names a46 +0 +1 +# assign a47 = $NDset ( 0,1 ) +.names a47 +0 +1 +# assign a48 = $NDset ( 0,1 ) +.names a48 +0 +1 +# assign a51 = $NDset ( 0,1 ) +.names a51 +0 +1 +# assign a52 = $NDset ( 0,1 ) +.names a52 +0 +1 +# assign a53 = $NDset ( 0,1 ) +.names a53 +0 +1 +# assign a54 = $NDset ( 0,1 ) +.names a54 +0 +1 +# assign a55 = $NDset ( 0,1 ) +.names a55 +0 +1 +# assign a56 = $NDset ( 0,1 ) +.names a56 +0 +1 +# assign a57 = $NDset ( 0,1 ) +.names a57 +0 +1 +# assign a58 = $NDset ( 0,1 ) +.names a58 +0 +1 +# assign a61 = $NDset ( 0,1 ) +.names a61 +0 +1 +# assign a62 = $NDset ( 0,1 ) +.names a62 +0 +1 +# assign a63 = $NDset ( 0,1 ) +.names a63 +0 +1 +# assign a64 = $NDset ( 0,1 ) +.names a64 +0 +1 +# assign a65 = $NDset ( 0,1 ) +.names a65 +0 +1 +# assign a66 = $NDset ( 0,1 ) +.names a66 +0 +1 +# assign a67 = $NDset ( 0,1 ) +.names a67 +0 +1 +# assign a68 = $NDset ( 0,1 ) +.names a68 +0 +1 +# assign a71 = $NDset ( 0,1 ) +.names a71 +0 +1 +# assign a72 = $NDset ( 0,1 ) +.names a72 +0 +1 +# assign a73 = $NDset ( 0,1 ) +.names a73 +0 +1 +# assign a74 = $NDset ( 0,1 ) +.names a74 +0 +1 +# assign a75 = $NDset ( 0,1 ) +.names a75 +0 +1 +# assign a76 = $NDset ( 0,1 ) +.names a76 +0 +1 +# assign a77 = $NDset ( 0,1 ) +.names a77 +0 +1 +# assign a78 = $NDset ( 0,1 ) +.names a78 +0 +1 +# assign a81 = $NDset ( 0,1 ) +.names a81 +0 +1 +# assign a82 = $NDset ( 0,1 ) +.names a82 +0 +1 +# assign a83 = $NDset ( 0,1 ) +.names a83 +0 +1 +# assign a84 = $NDset ( 0,1 ) +.names a84 +0 +1 +# assign a85 = $NDset ( 0,1 ) +.names a85 +0 +1 +# assign a86 = $NDset ( 0,1 ) +.names a86 +0 +1 +# assign a87 = $NDset ( 0,1 ) +.names a87 +0 +1 +# assign a88 = $NDset ( 0,1 ) +.names a88 +0 +1 +.subckt single8 H1 x1=a11 x2=a12 x3=a13 x4=a14 x5=a15 x6=a16 x7=a17 x8=a18 out=h1 +.subckt single8 H2 x1=a21 x2=a22 x3=a23 x4=a24 x5=a25 x6=a26 x7=a27 x8=a28 out=h2 +.subckt single8 H3 x1=a31 x2=a32 x3=a33 x4=a34 x5=a35 x6=a36 x7=a37 x8=a38 out=h3 +.subckt single8 H4 x1=a41 x2=a42 x3=a43 x4=a44 x5=a45 x6=a46 x7=a47 x8=a48 out=h4 +.subckt single8 H5 x1=a51 x2=a52 x3=a53 x4=a54 x5=a55 x6=a56 x7=a57 x8=a58 out=h5 +.subckt none8 H6 x1=a61 x2=a62 x3=a63 x4=a64 x5=a65 x6=a66 x7=a67 x8=a68 out=h6 +.subckt none8 H7 x1=a71 x2=a72 x3=a73 x4=a74 x5=a75 x6=a76 x7=a77 x8=a78 out=h7 +.subckt none8 H8 x1=a81 x2=a82 x3=a83 x4=a84 x5=a85 x6=a86 x7=a87 x8=a88 out=h8 +.subckt single8 V1 x1=a11 x2=a21 x3=a31 x4=a41 x5=a51 x6=a61 x7=a71 x8=a81 out=v1 +.subckt single8 V2 x1=a12 x2=a22 x3=a32 x4=a42 x5=a52 x6=a62 x7=a72 x8=a82 out=v2 +.subckt single8 V3 x1=a13 x2=a23 x3=a33 x4=a43 x5=a53 x6=a63 x7=a73 x8=a83 out=v3 +.subckt single8 V4 x1=a14 x2=a24 x3=a34 x4=a44 x5=a54 x6=a64 x7=a74 x8=a84 out=v4 +.subckt single8 V5 x1=a15 x2=a25 x3=a35 x4=a45 x5=a55 x6=a65 x7=a75 x8=a85 out=v5 +.subckt none8 V6 x1=a16 x2=a26 x3=a36 x4=a46 x5=a56 x6=a66 x7=a76 x8=a86 out=v6 +.subckt none8 V7 x1=a17 x2=a27 x3=a37 x4=a47 x5=a57 x6=a67 x7=a77 x8=a87 out=v7 +.subckt none8 V8 x1=a18 x2=a28 x3=a38 x4=a48 x5=a58 x6=a68 x7=a78 x8=a88 out=v8 +.names _n80 +0 +.names _n81 +0 +.names _n82 +0 +.names _n83 +0 +.names _n84 +0 +.names _n85 +0 +.names _n86 +0 +.subckt maxone8 L1 x1=a11 x2=_n80 x3=_n81 x4=_n82 x5=_n83 x6=_n84 x7=_n85 x8=_n86 out=l1 +.names _n87 +0 +.names _n88 +0 +.names _n89 +0 +.names _n8a +0 +.names _n8b +0 +.names _n8c +0 +.subckt maxone8 L2 x1=a21 x2=a12 x3=_n87 x4=_n88 x5=_n89 x6=_n8a x7=_n8b x8=_n8c out=l2 +.names _n8d +0 +.names _n8e +0 +.names _n8f +0 +.names _n90 +0 +.names _n91 +0 +.subckt maxone8 L3 x1=a31 x2=a22 x3=a13 x4=_n8d x5=_n8e x6=_n8f x7=_n90 x8=_n91 out=l3 +.names _n92 +0 +.names _n93 +0 +.names _n94 +0 +.names _n95 +0 +.subckt maxone8 L4 x1=a41 x2=a32 x3=a23 x4=a41 x5=_n92 x6=_n93 x7=_n94 x8=_n95 out=l4 +.names _n96 +0 +.names _n97 +0 +.names _n98 +0 +.subckt maxone8 L5 x1=a51 x2=a42 x3=a33 x4=a24 x5=a15 x6=_n96 x7=_n97 x8=_n98 out=l5 +.names _n99 +0 +.names _n9a +0 +.subckt maxone8 L6 x1=a61 x2=a52 x3=a43 x4=a34 x5=a25 x6=a16 x7=_n99 x8=_n9a out=l6 +.names _n9b +0 +.subckt maxone8 L7 x1=a71 x2=a62 x3=a53 x4=a44 x5=a35 x6=a26 x7=a17 x8=_n9b out=l7 +.subckt maxone8 L8 x1=a81 x2=a72 x3=a63 x4=a54 x5=a45 x6=a36 x7=a27 x8=a18 out=l8 +.names _n9c +0 +.subckt maxone8 L9 x1=a82 x2=a73 x3=a64 x4=a55 x5=a46 x6=a37 x7=a28 x8=_n9c out=l9 +.names _n9d +0 +.names _n9e +0 +.subckt maxone8 L10 x1=a83 x2=a74 x3=a65 x4=a56 x5=a47 x6=a38 x7=_n9d x8=_n9e out=l10 +.names _n9f +0 +.names _na0 +0 +.names _na1 +0 +.subckt maxone8 L11 x1=a84 x2=a75 x3=a66 x4=a57 x5=a48 x6=_n9f x7=_na0 x8=_na1 out=l11 +.names _na2 +0 +.names _na3 +0 +.names _na4 +0 +.names _na5 +0 +.subckt maxone8 L12 x1=a85 x2=a76 x3=a67 x4=a58 x5=_na2 x6=_na3 x7=_na4 x8=_na5 out=l12 +.names _na6 +0 +.names _na7 +0 +.names _na8 +0 +.names _na9 +0 +.names _naa +0 +.subckt maxone8 L13 x1=a86 x2=a77 x3=a68 x4=_na6 x5=_na7 x6=_na8 x7=_na9 x8=_naa out=l13 +.names _nab +0 +.names _nac +0 +.names _nad +0 +.names _nae +0 +.names _naf +0 +.names _nb0 +0 +.subckt maxone8 L14 x1=a87 x2=a78 x3=_nab x4=_nac x5=_nad x6=_nae x7=_naf x8=_nb0 out=l14 +.names _nb1 +0 +.names _nb2 +0 +.names _nb3 +0 +.names _nb4 +0 +.names _nb5 +0 +.names _nb6 +0 +.names _nb7 +0 +.subckt maxone8 L15 x1=a88 x2=_nb1 x3=_nb2 x4=_nb3 x5=_nb4 x6=_nb5 x7=_nb6 x8=_nb7 out=l15 +.names _nb8 +0 +.names _nb9 +0 +.names _nba +0 +.names _nbb +0 +.names _nbc +0 +.names _nbd +0 +.names _nbe +0 +.subckt maxone8 R1 x1=a18 x2=_nb8 x3=_nb9 x4=_nba x5=_nbb x6=_nbc x7=_nbd x8=_nbe out=r1 +.names _nbf +0 +.names _nc0 +0 +.names _nc1 +0 +.names _nc2 +0 +.names _nc3 +0 +.names _nc4 +0 +.subckt maxone8 R2 x1=a28 x2=a17 x3=_nbf x4=_nc0 x5=_nc1 x6=_nc2 x7=_nc3 x8=_nc4 out=r2 +.names _nc5 +0 +.names _nc6 +0 +.names _nc7 +0 +.names _nc8 +0 +.names _nc9 +0 +.subckt maxone8 R3 x1=a38 x2=a27 x3=a16 x4=_nc5 x5=_nc6 x6=_nc7 x7=_nc8 x8=_nc9 out=r3 +.names _nca +0 +.names _ncb +0 +.names _ncc +0 +.names _ncd +0 +.subckt maxone8 R4 x1=a48 x2=a37 x3=a26 x4=a15 x5=_nca x6=_ncb x7=_ncc x8=_ncd out=r4 +.names _nce +0 +.names _ncf +0 +.names _nd0 +0 +.subckt maxone8 R5 x1=a58 x2=a47 x3=a36 x4=a25 x5=a14 x6=_nce x7=_ncf x8=_nd0 out=r5 +.names _nd1 +0 +.names _nd2 +0 +.subckt maxone8 R6 x1=a68 x2=a57 x3=a46 x4=a35 x5=a24 x6=a13 x7=_nd1 x8=_nd2 out=r6 +.names _nd3 +0 +.subckt maxone8 R7 x1=a78 x2=a67 x3=a56 x4=a45 x5=a34 x6=a23 x7=a12 x8=_nd3 out=r7 +.subckt maxone8 R8 x1=a88 x2=a77 x3=a66 x4=a55 x5=a44 x6=a33 x7=a23 x8=a11 out=r8 +.names _nd4 +0 +.subckt maxone8 R9 x1=a87 x2=a76 x3=a65 x4=a54 x5=a43 x6=a32 x7=a21 x8=_nd4 out=r9 +.names _nd5 +0 +.names _nd6 +0 +.subckt maxone8 R10 x1=a86 x2=a75 x3=a64 x4=a53 x5=a42 x6=a31 x7=_nd5 x8=_nd6 out=r10 +.names _nd7 +0 +.names _nd8 +0 +.names _nd9 +0 +.subckt maxone8 R11 x1=a85 x2=a74 x3=a63 x4=a52 x5=a41 x6=_nd7 x7=_nd8 x8=_nd9 out=r11 +.names _nda +0 +.names _ndb +0 +.names _ndc +0 +.names _ndd +0 +.subckt maxone8 R12 x1=a84 x2=a73 x3=a62 x4=a51 x5=_nda x6=_ndb x7=_ndc x8=_ndd out=r12 +.names _nde +0 +.names _ndf +0 +.names _ne0 +0 +.names _ne1 +0 +.names _ne2 +0 +.subckt maxone8 R13 x1=a83 x2=a72 x3=a61 x4=_nde x5=_ndf x6=_ne0 x7=_ne1 x8=_ne2 out=r13 +.names _ne3 +0 +.names _ne4 +0 +.names _ne5 +0 +.names _ne6 +0 +.names _ne7 +0 +.names _ne8 +0 +.subckt maxone8 R14 x1=a82 x2=a71 x3=_ne3 x4=_ne4 x5=_ne5 x6=_ne6 x7=_ne7 x8=_ne8 out=r14 +.names _ne9 +0 +.names _nea +0 +.names _neb +0 +.names _nec +0 +.names _ned +0 +.names _nee +0 +.names _nef +0 +.subckt maxone8 R15 x1=a81 x2=_ne9 x3=_nea x4=_neb x5=_nec x6=_ned x7=_nee x8=_nef out=r15 +# assign tmp1 = (h1 && h2 && h3 && h4 && h5 && h6 && h7 && h8 ) +# h1 && h2 +.names h1 h2 _nf1 +.def 0 +1 1 1 +# h1 && h2 && h3 +.names _nf1 h3 _nf2 +.def 0 +1 1 1 +# h1 && h2 && h3 && h4 +.names _nf2 h4 _nf3 +.def 0 +1 1 1 +# h1 && h2 && h3 && h4 && h5 +.names _nf3 h5 _nf4 +.def 0 +1 1 1 +# h1 && h2 && h3 && h4 && h5 && h6 +.names _nf4 h6 _nf5 +.def 0 +1 1 1 +# h1 && h2 && h3 && h4 && h5 && h6 && h7 +.names _nf5 h7 _nf6 +.def 0 +1 1 1 +# h1 && h2 && h3 && h4 && h5 && h6 && h7 && h8 +.names _nf6 h8 _nf7 +.def 0 +1 1 1 +.names _nf7 tmp1$raw_nf0 +- =_nf7 +# assign tmp2 = (v1 && v2 && v3 && v4 && v5 && v6 && v7 && v8 ) +# v1 && v2 +.names v1 v2 _nf9 +.def 0 +1 1 1 +# v1 && v2 && v3 +.names _nf9 v3 _nfa +.def 0 +1 1 1 +# v1 && v2 && v3 && v4 +.names _nfa v4 _nfb +.def 0 +1 1 1 +# v1 && v2 && v3 && v4 && v5 +.names _nfb v5 _nfc +.def 0 +1 1 1 +# v1 && v2 && v3 && v4 && v5 && v6 +.names _nfc v6 _nfd +.def 0 +1 1 1 +# v1 && v2 && v3 && v4 && v5 && v6 && v7 +.names _nfd v7 _nfe +.def 0 +1 1 1 +# v1 && v2 && v3 && v4 && v5 && v6 && v7 && v8 +.names _nfe v8 _nff +.def 0 +1 1 1 +.names _nff tmp2$raw_nf8 +- =_nff +# assign tmp3 = (l1 && l2 && l3 && l4 && l5 && l6 && l7 && l8 ) +# l1 && l2 +.names l1 l2 _n101 +.def 0 +1 1 1 +# l1 && l2 && l3 +.names _n101 l3 _n102 +.def 0 +1 1 1 +# l1 && l2 && l3 && l4 +.names _n102 l4 _n103 +.def 0 +1 1 1 +# l1 && l2 && l3 && l4 && l5 +.names _n103 l5 _n104 +.def 0 +1 1 1 +# l1 && l2 && l3 && l4 && l5 && l6 +.names _n104 l6 _n105 +.def 0 +1 1 1 +# l1 && l2 && l3 && l4 && l5 && l6 && l7 +.names _n105 l7 _n106 +.def 0 +1 1 1 +# l1 && l2 && l3 && l4 && l5 && l6 && l7 && l8 +.names _n106 l8 _n107 +.def 0 +1 1 1 +.names _n107 tmp3$raw_n100 +- =_n107 +# assign tmp4 = (r1 && r2 && r3 && r4 && r5 && r6 && r7 && r8 ) +# r1 && r2 +.names r1 r2 _n109 +.def 0 +1 1 1 +# r1 && r2 && r3 +.names _n109 r3 _n10a +.def 0 +1 1 1 +# r1 && r2 && r3 && r4 +.names _n10a r4 _n10b +.def 0 +1 1 1 +# r1 && r2 && r3 && r4 && r5 +.names _n10b r5 _n10c +.def 0 +1 1 1 +# r1 && r2 && r3 && r4 && r5 && r6 +.names _n10c r6 _n10d +.def 0 +1 1 1 +# r1 && r2 && r3 && r4 && r5 && r6 && r7 +.names _n10d r7 _n10e +.def 0 +1 1 1 +# r1 && r2 && r3 && r4 && r5 && r6 && r7 && r8 +.names _n10e r8 _n10f +.def 0 +1 1 1 +.names _n10f tmp4$raw_n108 +- =_n10f +# assign tmp5 = (l9 && l10 && l11 && l12 && l13 && l14 && l15 ) +# l9 && l10 +.names l9 l10 _n111 +.def 0 +1 1 1 +# l9 && l10 && l11 +.names _n111 l11 _n112 +.def 0 +1 1 1 +# l9 && l10 && l11 && l12 +.names _n112 l12 _n113 +.def 0 +1 1 1 +# l9 && l10 && l11 && l12 && l13 +.names _n113 l13 _n114 +.def 0 +1 1 1 +# l9 && l10 && l11 && l12 && l13 && l14 +.names _n114 l14 _n115 +.def 0 +1 1 1 +# l9 && l10 && l11 && l12 && l13 && l14 && l15 +.names _n115 l15 _n116 +.def 0 +1 1 1 +.names _n116 tmp5$raw_n110 +- =_n116 +# assign tmp6 = (r9 && r10 && r11 && r12 && r13 && r14 && r15 ) +# r9 && r10 +.names r9 r10 _n118 +.def 0 +1 1 1 +# r9 && r10 && r11 +.names _n118 r11 _n119 +.def 0 +1 1 1 +# r9 && r10 && r11 && r12 +.names _n119 r12 _n11a +.def 0 +1 1 1 +# r9 && r10 && r11 && r12 && r13 +.names _n11a r13 _n11b +.def 0 +1 1 1 +# r9 && r10 && r11 && r12 && r13 && r14 +.names _n11b r14 _n11c +.def 0 +1 1 1 +# r9 && r10 && r11 && r12 && r13 && r14 && r15 +.names _n11c r15 _n11d +.def 0 +1 1 1 +.names _n11d tmp6$raw_n117 +- =_n11d +# assign consistent = (tmp1 && tmp2 && tmp3 && tmp4 && tmp5 && tmp6 ) +# tmp1 && tmp2 +.names tmp1 tmp2 _n11f +.def 0 +1 1 1 +# tmp1 && tmp2 && tmp3 +.names _n11f tmp3 _n120 +.def 0 +1 1 1 +# tmp1 && tmp2 && tmp3 && tmp4 +.names _n120 tmp4 _n121 +.def 0 +1 1 1 +# tmp1 && tmp2 && tmp3 && tmp4 && tmp5 +.names _n121 tmp5 _n122 +.def 0 +1 1 1 +# tmp1 && tmp2 && tmp3 && tmp4 && tmp5 && tmp6 +.names _n122 tmp6 _n123 +.def 0 +1 1 1 +.names _n123 consistent$raw_n11e +- =_n123 +# conflict arbitrators +.names tmp6$raw_n117 tmp6 +0 0 +1 1 +.names tmp5$raw_n110 tmp5 +0 0 +1 1 +.names tmp4$raw_n108 tmp4 +0 0 +1 1 +.names tmp3$raw_n100 tmp3 +0 0 +1 1 +.names tmp2$raw_nf8 tmp2 +0 0 +1 1 +.names tmp1$raw_nf0 tmp1 +0 0 +1 1 +.names consistent$raw_n11e consistent +0 0 +1 1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model single8 +# I/O ports +.inputs x3 +.inputs x4 +.inputs x5 +.inputs x6 +.inputs x7 +.outputs out +.inputs x8 +.inputs x1 +.inputs x2 + +# assign tmp1 = (x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ) +.names x2 _n125 +0 1 +1 0 +# x1 && !x2 +.names x1 _n125 _n126 +.def 0 +1 1 1 +.names x3 _n127 +0 1 +1 0 +# x1 && !x2 && !x3 +.names _n126 _n127 _n128 +.def 0 +1 1 1 +.names x4 _n129 +0 1 +1 0 +# x1 && !x2 && !x3 && !x4 +.names _n128 _n129 _n12a +.def 0 +1 1 1 +.names x5 _n12b +0 1 +1 0 +# x1 && !x2 && !x3 && !x4 && !x5 +.names _n12a _n12b _n12c +.def 0 +1 1 1 +.names x6 _n12d +0 1 +1 0 +# x1 && !x2 && !x3 && !x4 && !x5 && !x6 +.names _n12c _n12d _n12e +.def 0 +1 1 1 +.names x7 _n12f +0 1 +1 0 +# x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 +.names _n12e _n12f _n130 +.def 0 +1 1 1 +.names x8 _n131 +0 1 +1 0 +# x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 +.names _n130 _n131 _n132 +.def 0 +1 1 1 +.names _n132 tmp1$raw_n124 +- =_n132 +# assign tmp2 = (!x1 && x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ) +.names x1 _n134 +0 1 +1 0 +# !x1 && x2 +.names _n134 x2 _n135 +.def 0 +1 1 1 +.names x3 _n136 +0 1 +1 0 +# !x1 && x2 && !x3 +.names _n135 _n136 _n137 +.def 0 +1 1 1 +.names x4 _n138 +0 1 +1 0 +# !x1 && x2 && !x3 && !x4 +.names _n137 _n138 _n139 +.def 0 +1 1 1 +.names x5 _n13a +0 1 +1 0 +# !x1 && x2 && !x3 && !x4 && !x5 +.names _n139 _n13a _n13b +.def 0 +1 1 1 +.names x6 _n13c +0 1 +1 0 +# !x1 && x2 && !x3 && !x4 && !x5 && !x6 +.names _n13b _n13c _n13d +.def 0 +1 1 1 +.names x7 _n13e +0 1 +1 0 +# !x1 && x2 && !x3 && !x4 && !x5 && !x6 && !x7 +.names _n13d _n13e _n13f +.def 0 +1 1 1 +.names x8 _n140 +0 1 +1 0 +# !x1 && x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 +.names _n13f _n140 _n141 +.def 0 +1 1 1 +.names _n141 tmp2$raw_n133 +- =_n141 +# assign tmp3 = (!x1 && !x2 && x3 && !x4 && !x5 && !x6 && !x7 && !x8 ) +.names x1 _n143 +0 1 +1 0 +.names x2 _n144 +0 1 +1 0 +# !x1 && !x2 +.names _n143 _n144 _n145 +.def 0 +1 1 1 +# !x1 && !x2 && x3 +.names _n145 x3 _n146 +.def 0 +1 1 1 +.names x4 _n147 +0 1 +1 0 +# !x1 && !x2 && x3 && !x4 +.names _n146 _n147 _n148 +.def 0 +1 1 1 +.names x5 _n149 +0 1 +1 0 +# !x1 && !x2 && x3 && !x4 && !x5 +.names _n148 _n149 _n14a +.def 0 +1 1 1 +.names x6 _n14b +0 1 +1 0 +# !x1 && !x2 && x3 && !x4 && !x5 && !x6 +.names _n14a _n14b _n14c +.def 0 +1 1 1 +.names x7 _n14d +0 1 +1 0 +# !x1 && !x2 && x3 && !x4 && !x5 && !x6 && !x7 +.names _n14c _n14d _n14e +.def 0 +1 1 1 +.names x8 _n14f +0 1 +1 0 +# !x1 && !x2 && x3 && !x4 && !x5 && !x6 && !x7 && !x8 +.names _n14e _n14f _n150 +.def 0 +1 1 1 +.names _n150 tmp3$raw_n142 +- =_n150 +# assign tmp4 = (!x1 && !x2 && !x3 && x4 && !x5 && !x6 && !x7 && !x8 ) +.names x1 _n152 +0 1 +1 0 +.names x2 _n153 +0 1 +1 0 +# !x1 && !x2 +.names _n152 _n153 _n154 +.def 0 +1 1 1 +.names x3 _n155 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n154 _n155 _n156 +.def 0 +1 1 1 +# !x1 && !x2 && !x3 && x4 +.names _n156 x4 _n157 +.def 0 +1 1 1 +.names x5 _n158 +0 1 +1 0 +# !x1 && !x2 && !x3 && x4 && !x5 +.names _n157 _n158 _n159 +.def 0 +1 1 1 +.names x6 _n15a +0 1 +1 0 +# !x1 && !x2 && !x3 && x4 && !x5 && !x6 +.names _n159 _n15a _n15b +.def 0 +1 1 1 +.names x7 _n15c +0 1 +1 0 +# !x1 && !x2 && !x3 && x4 && !x5 && !x6 && !x7 +.names _n15b _n15c _n15d +.def 0 +1 1 1 +.names x8 _n15e +0 1 +1 0 +# !x1 && !x2 && !x3 && x4 && !x5 && !x6 && !x7 && !x8 +.names _n15d _n15e _n15f +.def 0 +1 1 1 +.names _n15f tmp4$raw_n151 +- =_n15f +# assign tmp5 = (!x1 && !x2 && !x3 && !x4 && x5 && !x6 && !x7 && !x8 ) +.names x1 _n161 +0 1 +1 0 +.names x2 _n162 +0 1 +1 0 +# !x1 && !x2 +.names _n161 _n162 _n163 +.def 0 +1 1 1 +.names x3 _n164 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n163 _n164 _n165 +.def 0 +1 1 1 +.names x4 _n166 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 +.names _n165 _n166 _n167 +.def 0 +1 1 1 +# !x1 && !x2 && !x3 && !x4 && x5 +.names _n167 x5 _n168 +.def 0 +1 1 1 +.names x6 _n169 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && x5 && !x6 +.names _n168 _n169 _n16a +.def 0 +1 1 1 +.names x7 _n16b +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && x5 && !x6 && !x7 +.names _n16a _n16b _n16c +.def 0 +1 1 1 +.names x8 _n16d +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && x5 && !x6 && !x7 && !x8 +.names _n16c _n16d _n16e +.def 0 +1 1 1 +.names _n16e tmp5$raw_n160 +- =_n16e +# assign tmp6 = (!x1 && !x2 && !x3 && !x4 && !x5 && x6 && !x7 && !x8 ) +.names x1 _n170 +0 1 +1 0 +.names x2 _n171 +0 1 +1 0 +# !x1 && !x2 +.names _n170 _n171 _n172 +.def 0 +1 1 1 +.names x3 _n173 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n172 _n173 _n174 +.def 0 +1 1 1 +.names x4 _n175 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 +.names _n174 _n175 _n176 +.def 0 +1 1 1 +.names x5 _n177 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 +.names _n176 _n177 _n178 +.def 0 +1 1 1 +# !x1 && !x2 && !x3 && !x4 && !x5 && x6 +.names _n178 x6 _n179 +.def 0 +1 1 1 +.names x7 _n17a +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && x6 && !x7 +.names _n179 _n17a _n17b +.def 0 +1 1 1 +.names x8 _n17c +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && x6 && !x7 && !x8 +.names _n17b _n17c _n17d +.def 0 +1 1 1 +.names _n17d tmp6$raw_n16f +- =_n17d +# assign tmp7 = (!x1 && !x2 && !x3 && !x4 && !x5 && !x6 && x7 && !x8 ) +.names x1 _n17f +0 1 +1 0 +.names x2 _n180 +0 1 +1 0 +# !x1 && !x2 +.names _n17f _n180 _n181 +.def 0 +1 1 1 +.names x3 _n182 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n181 _n182 _n183 +.def 0 +1 1 1 +.names x4 _n184 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 +.names _n183 _n184 _n185 +.def 0 +1 1 1 +.names x5 _n186 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 +.names _n185 _n186 _n187 +.def 0 +1 1 1 +.names x6 _n188 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 +.names _n187 _n188 _n189 +.def 0 +1 1 1 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && x7 +.names _n189 x7 _n18a +.def 0 +1 1 1 +.names x8 _n18b +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && x7 && !x8 +.names _n18a _n18b _n18c +.def 0 +1 1 1 +.names _n18c tmp7$raw_n17e +- =_n18c +# assign tmp8 = (!x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && x8 ) +.names x1 _n18e +0 1 +1 0 +.names x2 _n18f +0 1 +1 0 +# !x1 && !x2 +.names _n18e _n18f _n190 +.def 0 +1 1 1 +.names x3 _n191 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n190 _n191 _n192 +.def 0 +1 1 1 +.names x4 _n193 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 +.names _n192 _n193 _n194 +.def 0 +1 1 1 +.names x5 _n195 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 +.names _n194 _n195 _n196 +.def 0 +1 1 1 +.names x6 _n197 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 +.names _n196 _n197 _n198 +.def 0 +1 1 1 +.names x7 _n199 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 +.names _n198 _n199 _n19a +.def 0 +1 1 1 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && x8 +.names _n19a x8 _n19b +.def 0 +1 1 1 +.names _n19b tmp8$raw_n18d +- =_n19b +# assign out = (tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 || tmp7 || tmp8 ) +# tmp1 || tmp2 +.names tmp1 tmp2 _n19d +.def 1 +0 0 0 +# tmp1 || tmp2 || tmp3 +.names _n19d tmp3 _n19e +.def 1 +0 0 0 +# tmp1 || tmp2 || tmp3 || tmp4 +.names _n19e tmp4 _n19f +.def 1 +0 0 0 +# tmp1 || tmp2 || tmp3 || tmp4 || tmp5 +.names _n19f tmp5 _n1a0 +.def 1 +0 0 0 +# tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 +.names _n1a0 tmp6 _n1a1 +.def 1 +0 0 0 +# tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 || tmp7 +.names _n1a1 tmp7 _n1a2 +.def 1 +0 0 0 +# tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 || tmp7 || tmp8 +.names _n1a2 tmp8 _n1a3 +.def 1 +0 0 0 +.names _n1a3 out$raw_n19c +- =_n1a3 +# conflict arbitrators +.names tmp6$raw_n16f tmp6 +0 0 +1 1 +.names tmp5$raw_n160 tmp5 +0 0 +1 1 +.names tmp4$raw_n151 tmp4 +0 0 +1 1 +.names tmp3$raw_n142 tmp3 +0 0 +1 1 +.names tmp2$raw_n133 tmp2 +0 0 +1 1 +.names tmp1$raw_n124 tmp1 +0 0 +1 1 +.names out$raw_n19c out +0 0 +1 1 +.names tmp8$raw_n18d tmp8 +0 0 +1 1 +.names tmp7$raw_n17e tmp7 +0 0 +1 1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model none8 +# I/O ports +.inputs x3 +.inputs x4 +.inputs x5 +.inputs x6 +.inputs x7 +.outputs out +.inputs x8 +.inputs x1 +.inputs x2 + +# assign out = (!x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ) +.names x1 _n1a5 +0 1 +1 0 +.names x2 _n1a6 +0 1 +1 0 +# !x1 && !x2 +.names _n1a5 _n1a6 _n1a7 +.def 0 +1 1 1 +.names x3 _n1a8 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n1a7 _n1a8 _n1a9 +.def 0 +1 1 1 +.names x4 _n1aa +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 +.names _n1a9 _n1aa _n1ab +.def 0 +1 1 1 +.names x5 _n1ac +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 +.names _n1ab _n1ac _n1ad +.def 0 +1 1 1 +.names x6 _n1ae +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 +.names _n1ad _n1ae _n1af +.def 0 +1 1 1 +.names x7 _n1b0 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 +.names _n1af _n1b0 _n1b1 +.def 0 +1 1 1 +.names x8 _n1b2 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 +.names _n1b1 _n1b2 _n1b3 +.def 0 +1 1 1 +.names _n1b3 out$raw_n1a4 +- =_n1b3 +# conflict arbitrators +.names out$raw_n1a4 out +0 0 +1 1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model maxone8 +# I/O ports +.inputs x3 +.inputs x4 +.inputs x5 +.inputs x6 +.inputs x7 +.outputs out +.inputs x8 +.inputs x1 +.inputs x2 + +# assign tmp0 = (!x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ) +.names x1 _n1b5 +0 1 +1 0 +.names x2 _n1b6 +0 1 +1 0 +# !x1 && !x2 +.names _n1b5 _n1b6 _n1b7 +.def 0 +1 1 1 +.names x3 _n1b8 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n1b7 _n1b8 _n1b9 +.def 0 +1 1 1 +.names x4 _n1ba +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 +.names _n1b9 _n1ba _n1bb +.def 0 +1 1 1 +.names x5 _n1bc +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 +.names _n1bb _n1bc _n1bd +.def 0 +1 1 1 +.names x6 _n1be +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 +.names _n1bd _n1be _n1bf +.def 0 +1 1 1 +.names x7 _n1c0 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 +.names _n1bf _n1c0 _n1c1 +.def 0 +1 1 1 +.names x8 _n1c2 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 +.names _n1c1 _n1c2 _n1c3 +.def 0 +1 1 1 +.names _n1c3 tmp0$raw_n1b4 +- =_n1c3 +# assign tmp1 = (x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ) +.names x2 _n1c5 +0 1 +1 0 +# x1 && !x2 +.names x1 _n1c5 _n1c6 +.def 0 +1 1 1 +.names x3 _n1c7 +0 1 +1 0 +# x1 && !x2 && !x3 +.names _n1c6 _n1c7 _n1c8 +.def 0 +1 1 1 +.names x4 _n1c9 +0 1 +1 0 +# x1 && !x2 && !x3 && !x4 +.names _n1c8 _n1c9 _n1ca +.def 0 +1 1 1 +.names x5 _n1cb +0 1 +1 0 +# x1 && !x2 && !x3 && !x4 && !x5 +.names _n1ca _n1cb _n1cc +.def 0 +1 1 1 +.names x6 _n1cd +0 1 +1 0 +# x1 && !x2 && !x3 && !x4 && !x5 && !x6 +.names _n1cc _n1cd _n1ce +.def 0 +1 1 1 +.names x7 _n1cf +0 1 +1 0 +# x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 +.names _n1ce _n1cf _n1d0 +.def 0 +1 1 1 +.names x8 _n1d1 +0 1 +1 0 +# x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 +.names _n1d0 _n1d1 _n1d2 +.def 0 +1 1 1 +.names _n1d2 tmp1$raw_n1c4 +- =_n1d2 +# assign tmp2 = (!x1 && x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ) +.names x1 _n1d4 +0 1 +1 0 +# !x1 && x2 +.names _n1d4 x2 _n1d5 +.def 0 +1 1 1 +.names x3 _n1d6 +0 1 +1 0 +# !x1 && x2 && !x3 +.names _n1d5 _n1d6 _n1d7 +.def 0 +1 1 1 +.names x4 _n1d8 +0 1 +1 0 +# !x1 && x2 && !x3 && !x4 +.names _n1d7 _n1d8 _n1d9 +.def 0 +1 1 1 +.names x5 _n1da +0 1 +1 0 +# !x1 && x2 && !x3 && !x4 && !x5 +.names _n1d9 _n1da _n1db +.def 0 +1 1 1 +.names x6 _n1dc +0 1 +1 0 +# !x1 && x2 && !x3 && !x4 && !x5 && !x6 +.names _n1db _n1dc _n1dd +.def 0 +1 1 1 +.names x7 _n1de +0 1 +1 0 +# !x1 && x2 && !x3 && !x4 && !x5 && !x6 && !x7 +.names _n1dd _n1de _n1df +.def 0 +1 1 1 +.names x8 _n1e0 +0 1 +1 0 +# !x1 && x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 +.names _n1df _n1e0 _n1e1 +.def 0 +1 1 1 +.names _n1e1 tmp2$raw_n1d3 +- =_n1e1 +# assign tmp3 = (!x1 && !x2 && x3 && !x4 && !x5 && !x6 && !x7 && !x8 ) +.names x1 _n1e3 +0 1 +1 0 +.names x2 _n1e4 +0 1 +1 0 +# !x1 && !x2 +.names _n1e3 _n1e4 _n1e5 +.def 0 +1 1 1 +# !x1 && !x2 && x3 +.names _n1e5 x3 _n1e6 +.def 0 +1 1 1 +.names x4 _n1e7 +0 1 +1 0 +# !x1 && !x2 && x3 && !x4 +.names _n1e6 _n1e7 _n1e8 +.def 0 +1 1 1 +.names x5 _n1e9 +0 1 +1 0 +# !x1 && !x2 && x3 && !x4 && !x5 +.names _n1e8 _n1e9 _n1ea +.def 0 +1 1 1 +.names x6 _n1eb +0 1 +1 0 +# !x1 && !x2 && x3 && !x4 && !x5 && !x6 +.names _n1ea _n1eb _n1ec +.def 0 +1 1 1 +.names x7 _n1ed +0 1 +1 0 +# !x1 && !x2 && x3 && !x4 && !x5 && !x6 && !x7 +.names _n1ec _n1ed _n1ee +.def 0 +1 1 1 +.names x8 _n1ef +0 1 +1 0 +# !x1 && !x2 && x3 && !x4 && !x5 && !x6 && !x7 && !x8 +.names _n1ee _n1ef _n1f0 +.def 0 +1 1 1 +.names _n1f0 tmp3$raw_n1e2 +- =_n1f0 +# assign tmp4 = (!x1 && !x2 && !x3 && x4 && !x5 && !x6 && !x7 && !x8 ) +.names x1 _n1f2 +0 1 +1 0 +.names x2 _n1f3 +0 1 +1 0 +# !x1 && !x2 +.names _n1f2 _n1f3 _n1f4 +.def 0 +1 1 1 +.names x3 _n1f5 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n1f4 _n1f5 _n1f6 +.def 0 +1 1 1 +# !x1 && !x2 && !x3 && x4 +.names _n1f6 x4 _n1f7 +.def 0 +1 1 1 +.names x5 _n1f8 +0 1 +1 0 +# !x1 && !x2 && !x3 && x4 && !x5 +.names _n1f7 _n1f8 _n1f9 +.def 0 +1 1 1 +.names x6 _n1fa +0 1 +1 0 +# !x1 && !x2 && !x3 && x4 && !x5 && !x6 +.names _n1f9 _n1fa _n1fb +.def 0 +1 1 1 +.names x7 _n1fc +0 1 +1 0 +# !x1 && !x2 && !x3 && x4 && !x5 && !x6 && !x7 +.names _n1fb _n1fc _n1fd +.def 0 +1 1 1 +.names x8 _n1fe +0 1 +1 0 +# !x1 && !x2 && !x3 && x4 && !x5 && !x6 && !x7 && !x8 +.names _n1fd _n1fe _n1ff +.def 0 +1 1 1 +.names _n1ff tmp4$raw_n1f1 +- =_n1ff +# assign tmp5 = (!x1 && !x2 && !x3 && !x4 && x5 && !x6 && !x7 && !x8 ) +.names x1 _n201 +0 1 +1 0 +.names x2 _n202 +0 1 +1 0 +# !x1 && !x2 +.names _n201 _n202 _n203 +.def 0 +1 1 1 +.names x3 _n204 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n203 _n204 _n205 +.def 0 +1 1 1 +.names x4 _n206 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 +.names _n205 _n206 _n207 +.def 0 +1 1 1 +# !x1 && !x2 && !x3 && !x4 && x5 +.names _n207 x5 _n208 +.def 0 +1 1 1 +.names x6 _n209 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && x5 && !x6 +.names _n208 _n209 _n20a +.def 0 +1 1 1 +.names x7 _n20b +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && x5 && !x6 && !x7 +.names _n20a _n20b _n20c +.def 0 +1 1 1 +.names x8 _n20d +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && x5 && !x6 && !x7 && !x8 +.names _n20c _n20d _n20e +.def 0 +1 1 1 +.names _n20e tmp5$raw_n200 +- =_n20e +# assign tmp6 = (!x1 && !x2 && !x3 && !x4 && !x5 && x6 && !x7 && !x8 ) +.names x1 _n210 +0 1 +1 0 +.names x2 _n211 +0 1 +1 0 +# !x1 && !x2 +.names _n210 _n211 _n212 +.def 0 +1 1 1 +.names x3 _n213 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n212 _n213 _n214 +.def 0 +1 1 1 +.names x4 _n215 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 +.names _n214 _n215 _n216 +.def 0 +1 1 1 +.names x5 _n217 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 +.names _n216 _n217 _n218 +.def 0 +1 1 1 +# !x1 && !x2 && !x3 && !x4 && !x5 && x6 +.names _n218 x6 _n219 +.def 0 +1 1 1 +.names x7 _n21a +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && x6 && !x7 +.names _n219 _n21a _n21b +.def 0 +1 1 1 +.names x8 _n21c +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && x6 && !x7 && !x8 +.names _n21b _n21c _n21d +.def 0 +1 1 1 +.names _n21d tmp6$raw_n20f +- =_n21d +# assign tmp7 = (!x1 && !x2 && !x3 && !x4 && !x5 && !x6 && x7 && !x8 ) +.names x1 _n21f +0 1 +1 0 +.names x2 _n220 +0 1 +1 0 +# !x1 && !x2 +.names _n21f _n220 _n221 +.def 0 +1 1 1 +.names x3 _n222 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n221 _n222 _n223 +.def 0 +1 1 1 +.names x4 _n224 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 +.names _n223 _n224 _n225 +.def 0 +1 1 1 +.names x5 _n226 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 +.names _n225 _n226 _n227 +.def 0 +1 1 1 +.names x6 _n228 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 +.names _n227 _n228 _n229 +.def 0 +1 1 1 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && x7 +.names _n229 x7 _n22a +.def 0 +1 1 1 +.names x8 _n22b +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && x7 && !x8 +.names _n22a _n22b _n22c +.def 0 +1 1 1 +.names _n22c tmp7$raw_n21e +- =_n22c +# assign tmp8 = (!x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && x8 ) +.names x1 _n22e +0 1 +1 0 +.names x2 _n22f +0 1 +1 0 +# !x1 && !x2 +.names _n22e _n22f _n230 +.def 0 +1 1 1 +.names x3 _n231 +0 1 +1 0 +# !x1 && !x2 && !x3 +.names _n230 _n231 _n232 +.def 0 +1 1 1 +.names x4 _n233 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 +.names _n232 _n233 _n234 +.def 0 +1 1 1 +.names x5 _n235 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 +.names _n234 _n235 _n236 +.def 0 +1 1 1 +.names x6 _n237 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 +.names _n236 _n237 _n238 +.def 0 +1 1 1 +.names x7 _n239 +0 1 +1 0 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 +.names _n238 _n239 _n23a +.def 0 +1 1 1 +# !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && x8 +.names _n23a x8 _n23b +.def 0 +1 1 1 +.names _n23b tmp8$raw_n22d +- =_n23b +# assign out = (tmp0 || tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 || tmp7 || tmp8 ) +# tmp0 || tmp1 +.names tmp0 tmp1 _n23d +.def 1 +0 0 0 +# tmp0 || tmp1 || tmp2 +.names _n23d tmp2 _n23e +.def 1 +0 0 0 +# tmp0 || tmp1 || tmp2 || tmp3 +.names _n23e tmp3 _n23f +.def 1 +0 0 0 +# tmp0 || tmp1 || tmp2 || tmp3 || tmp4 +.names _n23f tmp4 _n240 +.def 1 +0 0 0 +# tmp0 || tmp1 || tmp2 || tmp3 || tmp4 || tmp5 +.names _n240 tmp5 _n241 +.def 1 +0 0 0 +# tmp0 || tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 +.names _n241 tmp6 _n242 +.def 1 +0 0 0 +# tmp0 || tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 || tmp7 +.names _n242 tmp7 _n243 +.def 1 +0 0 0 +# tmp0 || tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 || tmp7 || tmp8 +.names _n243 tmp8 _n244 +.def 1 +0 0 0 +.names _n244 out$raw_n23c +- =_n244 +# conflict arbitrators +.names tmp6$raw_n20f tmp6 +0 0 +1 1 +.names tmp5$raw_n200 tmp5 +0 0 +1 1 +.names tmp4$raw_n1f1 tmp4 +0 0 +1 1 +.names tmp3$raw_n1e2 tmp3 +0 0 +1 1 +.names tmp2$raw_n1d3 tmp2 +0 0 +1 1 +.names tmp1$raw_n1c4 tmp1 +0 0 +1 1 +.names out$raw_n23c out +0 0 +1 1 +.names tmp0$raw_n1b4 tmp0 +0 0 +1 1 +.names tmp8$raw_n22d tmp8 +0 0 +1 1 +.names tmp7$raw_n21e tmp7 +0 0 +1 1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/eight_queens/eight_queens.v =================================================================== --- vis_dev/vis-2.1/examples/eight_queens/eight_queens.v (revision 11) +++ vis_dev/vis-2.1/examples/eight_queens/eight_queens.v (revision 11) @@ -0,0 +1,220 @@ +/************************************************************************/ + +module game(clk, consistent); + input clk; + output consistent; + wire consistent; + +wire a11, a12, a13, a14, a15, a16, a17, a18, + a21, a22, a23, a24, a25, a26, a27, a28, + a31, a32, a33, a34, a35, a36, a37, a38, + a41, a42, a43, a44, a45, a46, a47, a48, + a51, a52, a53, a54, a55, a56, a57, a58, + a61, a62, a63, a64, a65, a66, a67, a68, + a71, a72, a73, a74, a75, a76, a77, a78, + a81, a82, a83, a84, a85, a86, a87, a88; + +wire h1, h2, h3, h4, h5, h6, h7, h8; +wire v1, v2, v3, v4, v5, v6, v7, v8; +wire l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15; +wire r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15; + +wire tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; + +assign a11 = $ND(0, 1); +assign a12 = $ND(0, 1); +assign a13 = $ND(0, 1); +assign a14 = $ND(0, 1); +assign a15 = $ND(0, 1); +assign a16 = $ND(0, 1); +assign a17 = $ND(0, 1); +assign a18 = $ND(0, 1); + +assign a21 = $ND(0, 1); +assign a22 = $ND(0, 1); +assign a23 = $ND(0, 1); +assign a24 = $ND(0, 1); +assign a25 = $ND(0, 1); +assign a26 = $ND(0, 1); +assign a27 = $ND(0, 1); +assign a28 = $ND(0, 1); + +assign a31 = $ND(0, 1); +assign a32 = $ND(0, 1); +assign a33 = $ND(0, 1); +assign a34 = $ND(0, 1); +assign a35 = $ND(0, 1); +assign a36 = $ND(0, 1); +assign a37 = $ND(0, 1); +assign a38 = $ND(0, 1); + +assign a41 = $ND(0, 1); +assign a42 = $ND(0, 1); +assign a43 = $ND(0, 1); +assign a44 = $ND(0, 1); +assign a45 = $ND(0, 1); +assign a46 = $ND(0, 1); +assign a47 = $ND(0, 1); +assign a48 = $ND(0, 1); + +assign a51 = $ND(0, 1); +assign a52 = $ND(0, 1); +assign a53 = $ND(0, 1); +assign a54 = $ND(0, 1); +assign a55 = $ND(0, 1); +assign a56 = $ND(0, 1); +assign a57 = $ND(0, 1); +assign a58 = $ND(0, 1); + +assign a61 = $ND(0, 1); +assign a62 = $ND(0, 1); +assign a63 = $ND(0, 1); +assign a64 = $ND(0, 1); +assign a65 = $ND(0, 1); +assign a66 = $ND(0, 1); +assign a67 = $ND(0, 1); +assign a68 = $ND(0, 1); + +assign a71 = $ND(0, 1); +assign a72 = $ND(0, 1); +assign a73 = $ND(0, 1); +assign a74 = $ND(0, 1); +assign a75 = $ND(0, 1); +assign a76 = $ND(0, 1); +assign a77 = $ND(0, 1); +assign a78 = $ND(0, 1); + +assign a81 = $ND(0, 1); +assign a82 = $ND(0, 1); +assign a83 = $ND(0, 1); +assign a84 = $ND(0, 1); +assign a85 = $ND(0, 1); +assign a86 = $ND(0, 1); +assign a87 = $ND(0, 1); +assign a88 = $ND(0, 1); + + +single8 H1( clk, a11, a12, a13, a14, a15, a16, a17, a18, h1 ); +single8 H2( clk, a21, a22, a23, a24, a25, a26, a27, a28, h2 ); +single8 H3( clk, a31, a32, a33, a34, a35, a36, a37, a38, h3 ); +single8 H4( clk, a41, a42, a43, a44, a45, a46, a47, a48, h4 ); +single8 H5( clk, a51, a52, a53, a54, a55, a56, a57, a58, h5 ); +none8 H6( clk, a61, a62, a63, a64, a65, a66, a67, a68, h6 ); +none8 H7( clk, a71, a72, a73, a74, a75, a76, a77, a78, h7 ); +none8 H8( clk, a81, a82, a83, a84, a85, a86, a87, a88, h8 ); + +single8 V1( clk, a11, a21, a31, a41, a51, a61, a71, a81, v1 ); +single8 V2( clk, a12, a22, a32, a42, a52, a62, a72, a82, v2 ); +single8 V3( clk, a13, a23, a33, a43, a53, a63, a73, a83, v3 ); +single8 V4( clk, a14, a24, a34, a44, a54, a64, a74, a84, v4 ); +single8 V5( clk, a15, a25, a35, a45, a55, a65, a75, a85, v5 ); +none8 V6( clk, a16, a26, a36, a46, a56, a66, a76, a86, v6 ); +none8 V7( clk, a17, a27, a37, a47, a57, a67, a77, a87, v7 ); +none8 V8( clk, a18, a28, a38, a48, a58, a68, a78, a88, v8 ); + +maxone8 L1( clk, a11, 0, 0, 0, 0, 0, 0, 0, l1 ); +maxone8 L2( clk, a21, a12, 0, 0, 0, 0, 0, 0, l2 ); +maxone8 L3( clk, a31, a22, a13, 0, 0, 0, 0, 0, l3 ); +maxone8 L4( clk, a41, a32, a23, a41, 0, 0, 0, 0, l4 ); +maxone8 L5( clk, a51, a42, a33, a24, a15, 0, 0, 0, l5 ); +maxone8 L6( clk, a61, a52, a43, a34, a25, a16, 0, 0, l6 ); +maxone8 L7( clk, a71, a62, a53, a44, a35, a26, a17, 0, l7 ); +maxone8 L8( clk, a81, a72, a63, a54, a45, a36, a27, a18, l8 ); + +maxone8 L9 ( clk, a82, a73, a64, a55, a46, a37, a28, 0 , l9 ); +maxone8 L10( clk, a83, a74, a65, a56, a47, a38, 0 , 0 , l10 ); +maxone8 L11( clk, a84, a75, a66, a57, a48, 0 , 0 , 0 , l11 ); +maxone8 L12( clk, a85, a76, a67, a58, 0 , 0 , 0 , 0 , l12 ); +maxone8 L13( clk, a86, a77, a68, 0 , 0 , 0 , 0 , 0 , l13 ); +maxone8 L14( clk, a87, a78, 0 , 0 , 0 , 0 , 0 , 0 , l14 ); +maxone8 L15( clk, a88, 0 , 0 , 0 , 0 , 0 , 0 , 0 , l15 ); + +maxone8 R1( clk, a18, 0, 0, 0, 0, 0, 0, 0, r1 ); +maxone8 R2( clk, a28, a17, 0, 0, 0, 0, 0, 0, r2 ); +maxone8 R3( clk, a38, a27, a16, 0, 0, 0, 0, 0, r3 ); +maxone8 R4( clk, a48, a37, a26, a15, 0, 0, 0, 0, r4 ); +maxone8 R5( clk, a58, a47, a36, a25, a14, 0, 0, 0, r5 ); +maxone8 R6( clk, a68, a57, a46, a35, a24, a13, 0, 0, r6 ); +maxone8 R7( clk, a78, a67, a56, a45, a34, a23, a12, 0, r7 ); +maxone8 R8( clk, a88, a77, a66, a55, a44, a33, a23, a11, r8 ); + +maxone8 R9 ( clk, a87, a76, a65, a54, a43, a32, a21, 0 , r9 ); +maxone8 R10( clk, a86, a75, a64, a53, a42, a31, 0 , 0 , r10 ); +maxone8 R11( clk, a85, a74, a63, a52, a41, 0 , 0 , 0 , r11 ); +maxone8 R12( clk, a84, a73, a62, a51, 0 , 0 , 0 , 0 , r12 ); +maxone8 R13( clk, a83, a72, a61, 0 , 0 , 0 , 0 , 0 , r13 ); +maxone8 R14( clk, a82, a71, 0 , 0 , 0 , 0 , 0 , 0 , r14 ); +maxone8 R15( clk, a81, 0 , 0 , 0 , 0 , 0 , 0 , 0 , r15 ); + + +assign tmp1 = ( h1 && h2 && h3 && h4 && h5 && h6 && h7 && h8 ); +assign tmp2 = ( v1 && v2 && v3 && v4 && v5 && v6 && v7 && v8 ); +assign tmp3 = ( l1 && l2 && l3 && l4 && l5 && l6 && l7 && l8 ); +assign tmp4 = ( r1 && r2 && r3 && r4 && r5 && r6 && r7 && r8 ); +assign tmp5 = ( l9 && l10 && l11 && l12 && l13 && l14 && l15 ); +assign tmp6 = ( r9 && r10 && r11 && r12 && r13 && r14 && r15 ); + +assign consistent = ( tmp1 && tmp2 && tmp3 && tmp4 && tmp5 && tmp6 ); + + +endmodule + +/************************************************************************/ +module single8(clk, x1, x2, x3, x4, x5, x6, x7, x8, out ); + input clk; + input x1, x2, x3, x4, x5, x6, x7, x8; + output out; + + wire x1, x2, x3, x4, x5, x6, x7, x8; + wire out; + wire tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; + +assign tmp1 = ( x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); +assign tmp2 = ( !x1 && x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); +assign tmp3 = ( !x1 && !x2 && x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); +assign tmp4 = ( !x1 && !x2 && !x3 && x4 && !x5 && !x6 && !x7 && !x8 ); +assign tmp5 = ( !x1 && !x2 && !x3 && !x4 && x5 && !x6 && !x7 && !x8 ); +assign tmp6 = ( !x1 && !x2 && !x3 && !x4 && !x5 && x6 && !x7 && !x8 ); +assign tmp7 = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && x7 && !x8 ); +assign tmp8 = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && x8 ); + + +assign out = ( tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 || tmp7 || tmp8 ); + +endmodule +/************************************************************************/ +module maxone8(clk, x1, x2, x3, x4, x5, x6, x7, x8, out ); + input clk; + input x1, x2, x3, x4, x5, x6, x7, x8; + output out; + + wire x1, x2, x3, x4, x5, x6, x7, x8; + wire out; + wire tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8; + +assign tmp0 = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); +assign tmp1 = ( x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); +assign tmp2 = ( !x1 && x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); +assign tmp3 = ( !x1 && !x2 && x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); +assign tmp4 = ( !x1 && !x2 && !x3 && x4 && !x5 && !x6 && !x7 && !x8 ); +assign tmp5 = ( !x1 && !x2 && !x3 && !x4 && x5 && !x6 && !x7 && !x8 ); +assign tmp6 = ( !x1 && !x2 && !x3 && !x4 && !x5 && x6 && !x7 && !x8 ); +assign tmp7 = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && x7 && !x8 ); +assign tmp8 = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && x8 ); + +assign out = ( tmp0 || tmp1 || tmp2 || tmp3 || tmp4 || tmp5 || tmp6 || tmp7 || tmp8 ); + +endmodule + +/************************************************************************/ +module none8(clk, x1, x2, x3, x4, x5, x6, x7, x8, out ); + input clk; + input x1, x2, x3, x4, x5, x6, x7, x8; + output out; + + wire x1, x2, x3, x4, x5, x6, x7, x8; + wire out; + +assign out = ( !x1 && !x2 && !x3 && !x4 && !x5 && !x6 && !x7 && !x8 ); + +endmodule Index: vis_dev/vis-2.1/examples/eisenberg/affalse =================================================================== --- vis_dev/vis-2.1/examples/eisenberg/affalse (revision 11) +++ vis_dev/vis-2.1/examples/eisenberg/affalse (revision 11) @@ -0,0 +1,1 @@ +AF FALSE; Index: vis_dev/vis-2.1/examples/eisenberg/agtrue =================================================================== --- vis_dev/vis-2.1/examples/eisenberg/agtrue (revision 11) +++ vis_dev/vis-2.1/examples/eisenberg/agtrue (revision 11) @@ -0,0 +1,1 @@ +AG TRUE; Index: vis_dev/vis-2.1/examples/eisenberg/check_result =================================================================== --- vis_dev/vis-2.1/examples/eisenberg/check_result (revision 11) +++ vis_dev/vis-2.1/examples/eisenberg/check_result (revision 11) @@ -0,0 +1,7 @@ +FSM depth = 41 +reachable states = 1611 +# LE: language is not empty +# MC: formula passed --- AG(TRUE) +# MC: formula failed --- AF(FALSE) +# LE: language is not empty +# MC: formula failed --- AF(FALSE) Index: vis_dev/vis-2.1/examples/eisenberg/check_script =================================================================== --- vis_dev/vis-2.1/examples/eisenberg/check_script (revision 11) +++ vis_dev/vis-2.1/examples/eisenberg/check_script (revision 11) @@ -0,0 +1,20 @@ +read_blif_mv eisenberg.mv +init_verify +compute_reach +dynamic_var_ordering -f sift +write_order order +flatten_hierarchy +static_order -s input_and_latch order +build_partition_mdds +compute_reach -v 1 +dynamic_var_ordering -f sift +print_fairness +lang_empty -d 0 +model_check -d 0 agtrue +model_check -d 0 affalse +read_fairness eisenberg.fair +print_fairness +lang_empty -d 0 +model_check -d 0 affalse +time +quit -s Index: vis_dev/vis-2.1/examples/eisenberg/eisenberg.ctl =================================================================== --- vis_dev/vis-2.1/examples/eisenberg/eisenberg.ctl (revision 11) +++ vis_dev/vis-2.1/examples/eisenberg/eisenberg.ctl (revision 11) @@ -0,0 +1,5 @@ +AG ((p0.pc=L1) -> AF (p0.pc=L12)) ; +AG ((p1.pc=L1) -> AF (p1.pc=L12)) ; +AG ((p0.pc=L12) -> AF (p0.pc=L16)) ; +AG ((p1.pc=L12) -> AF (p1.pc=L16)) ; +AG (!(p0.pc=L12) + !(p1.pc=L12)) ; Index: vis_dev/vis-2.1/examples/eisenberg/eisenberg.fair =================================================================== --- vis_dev/vis-2.1/examples/eisenberg/eisenberg.fair (revision 11) +++ vis_dev/vis-2.1/examples/eisenberg/eisenberg.fair (revision 11) @@ -0,0 +1,24 @@ +#.model system +#.state st0 = st_perm0:1 +#.state st1 = st_perm1:1 +#.negfair +#.subsets{st0} +#.subsets{st1} +#.endfair +#.endmodel +!(st_perm0=1); +!(st_perm1=1); + +#.model process +#.state critical_section = pc:L12 +#.state soso_section = pc:L16 +#.negfair +#.subsets{critical_section} +#.subsets{soso_section} +#.endfair +#.endmodel +!(p0.pc=L12); +!(p0.pc=L16); +!(p1.pc=L12); +!(p1.pc=L16); + Index: vis_dev/vis-2.1/examples/eisenberg/eisenberg.mv =================================================================== --- vis_dev/vis-2.1/examples/eisenberg/eisenberg.mv (revision 11) +++ vis_dev/vis-2.1/examples/eisenberg/eisenberg.mv (revision 11) @@ -0,0 +1,1274 @@ +# /tmp/yuji/next/vl2mv/snake/bin/vl2mv eisenberg.v +# version: 0.2 +# date: 14:23:49 12/19/95 (PST) +.model system +# I/O ports + +.mv out_flag1 3 idle want_in in_cs +.mv flag1 3 idle want_in in_cs +.mv flag0 3 idle want_in in_cs +.mv out_flag0 3 idle want_in in_cs +.names _n0 +0 +.subckt process p0 perm=perm0 flag0=flag0 flag1=flag1 out_flag=out_flag0 turn=turn out_turn=out_turn0 i=_n0 +.names _n1 +1 +.subckt process p1 perm=perm1 flag0=flag0 flag1=flag1 out_flag=out_flag1 turn=turn out_turn=out_turn1 i=_n1 +# assign perm0 = $NDset ( ,0,1 ) +.names perm0 +0 +1 +# assign perm1 = ~perm0 +.names perm0 _n5 +0 1 +1 0 +.names _n5 perm1$raw_n4 +- =_n5 +# flag0 = 0 +.mv flag0$raw_n6 3 idle want_in in_cs +.names flag0$raw_n6 +idle +# flag1 = 0 +.mv flag1$raw_n7 3 idle want_in in_cs +.names flag1$raw_n7 +idle +# turn = 0 +.names turn$raw_n8 +0 +# non-blocking assignments for initial +# st_perm0 = $NDset ( 0,1 ) +.names st_perm0$raw_n9$initial$_na +0 +1 +.names st_perm0$raw_n9$initial$_na st_perm0$raw_n9 +- =st_perm0$raw_n9$initial$_na +# non-blocking assignments for initial +# st_perm1 = $NDset ( 0,1 ) +.names st_perm1$raw_nb$initial$_nc +0 +1 +.names st_perm1$raw_nb$initial$_nc st_perm1$raw_nb +- =st_perm1$raw_nb$initial$_nc +# non-blocking assignments for initial +# st_perm0 = perm0 +.names perm0 st_perm0$raw_nd +- =perm0 +# st_perm1 = perm1 +.names perm1 st_perm1$raw_ne +- =perm1 +.names _n10 +1 +# perm0 == 1 +.names perm0 _n10 _n11 +.def 0 +0 1 1 +1 0 1 +.names _n11 _nf +0 1 +1 0 +.names _nf _n13 +- =_nf +# flag0 = out_flag0 +.mv flag0$_nf_n14$true 3 idle want_in in_cs +.names out_flag0 flag0$_nf_n14$true +- =out_flag0 +# turn = out_turn0 +.names out_turn0 turn$_nf_n15$true +- =out_turn0 +.names _n17 +1 +# perm1 == 1 +.names perm1 _n17 _n18 +.def 0 +0 1 1 +1 0 1 +.names _n18 _n16 +0 1 +1 0 +.names _n16 _n1a +- =_n16 +# flag1 = out_flag1 +.mv flag1$_n16_n1b$true 3 idle want_in in_cs +.names out_flag1 flag1$_n16_n1b$true +- =out_flag1 +# turn = out_turn1 +.names out_turn1 turn$_n16_n1c$true +- =out_turn1 +# if/else (perm1 == 1) +.names turn$_n16_n1c$true turn _n16 turn$_n16$raw_n25 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv flag1$_n16$raw_n27 3 idle want_in in_cs +.names flag1$_n16_n1b$true flag1 _n16 flag1$_n16$raw_n27 +- - 0 =flag1 +- - 1 =flag1$_n16_n1b$true +# if/else (perm0 == 1) +.names turn$_nf_n15$true turn$_n16$raw_n25 _nf turn$_nf$raw_n30 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv flag0$_nf$raw_n36 3 idle want_in in_cs +.names flag0$_nf_n14$true flag0 _nf flag0$_nf$raw_n36 +- - 0 =flag0 +- - 1 =flag0$_nf_n14$true +.mv flag1$_nf$raw_n3a 3 idle want_in in_cs +.names flag1 flag1$_n16$raw_n27 _nf flag1$_nf$raw_n3a +- - 0 =flag1$_n16$raw_n27 +- - 1 =flag1 +# conflict arbitrators +.names _n13 _n1a _n3d +.def 0 + 1 - 1 + 0 1 1 +.names _n3d turn$_nf$raw_n30 turn _n3e +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names perm1$raw_n4 perm1 +0 0 +1 1 +.names _n13 _n1a _n3f +.def 0 + 0 1 1 +.mv _n40 3 idle want_in in_cs +.names _n3f flag1$_nf$raw_n3a flag1 _n40 +1 - - =flag1$_nf$raw_n3a +0 - - =flag1 +.names _n13 _n46 +.def 0 + 1 1 +.mv _n47 3 idle want_in in_cs +.names _n46 flag0$_nf$raw_n36 flag0 _n47 +1 - - =flag0$_nf$raw_n36 +0 - - =flag0 +.names _n4d +.def 0 + 1 +.names _n4d st_perm1$raw_ne _n4e +.def 0 +1 0 0 +1 1 1 +.names _n4f +.def 0 + 1 +.names _n4f st_perm0$raw_nd _n50 +.def 0 +1 0 0 +1 1 1 +# non-blocking assignments +# latches +.r turn$raw_n8 turn +0 0 +1 1 +.latch _n3e turn +.r flag1$raw_n7 flag1 +- =flag1$raw_n7 +.latch _n40 flag1 +.r flag0$raw_n6 flag0 +- =flag0$raw_n6 +.latch _n47 flag0 +.r st_perm1$raw_nb st_perm1 +0 0 +1 1 +.latch _n4e st_perm1 +.r st_perm0$raw_n9 st_perm0 +0 0 +1 1 +.latch _n50 st_perm0 +# quasi-continuous assignment +.end + + +.model process +# I/O ports +.inputs turn +.outputs out_turn +.outputs out_flag +.inputs flag1 +.inputs flag0 +.inputs i +.inputs perm + +.mv flagturn 3 idle want_in in_cs +.mv flagj 3 idle want_in in_cs +.mv pc 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.mv out_flag 3 idle want_in in_cs +.mv flag1 3 idle want_in in_cs +.mv flag0 3 idle want_in in_cs +# assign flagj = (j == 0) ? flag0 : flag1 +.mv flagj$raw_n51 3 idle want_in in_cs +.names _n53 +0 +# j == 0 +.names j _n53 _n54 +.def 0 +0 1 1 +1 0 1 +.names _n54 _n52 +0 1 +1 0 +# (j == 0) ? flag0 : flag1 +.mv _n56 3 idle want_in in_cs +.names flag0 flag1 _n52 _n56 +- - 0 =flag1 +- - 1 =flag0 +.names _n56 flagj$raw_n51 +- =_n56 +# assign flagturn = (turn == 0) ? flag0 : flag1 +.mv flagturn$raw_n57 3 idle want_in in_cs +.names _n59 +0 +# turn == 0 +.names turn _n59 _n5a +.def 0 +0 1 1 +1 0 1 +.names _n5a _n58 +0 1 +1 0 +# (turn == 0) ? flag0 : flag1 +.mv _n5c 3 idle want_in in_cs +.names flag0 flag1 _n58 _n5c +- - 0 =flag1 +- - 1 =flag0 +.names _n5c flagturn$raw_n57 +- =_n5c +# assign out_flag = (pc == L1 ) ? 1 : (pc == L7 ) ? 2 : (pc == L16 ) ? 0 : (i == 0) ? flag0 : flag1 +.mv out_flag$raw_n5d 3 idle want_in in_cs +.mv _n5f 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n5f +L1 +# pc == 0 +.names pc _n5f _n5e +.def 0 +- =pc 1 +.mv _n61 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n61 +L7 +# pc == 6 +.names pc _n61 _n60 +.def 0 +- =pc 1 +.mv _n63 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n63 +L16 +# pc == 15 +.names pc _n63 _n62 +.def 0 +- =pc 1 +.names _n65 +0 +# i == 0 +.names i _n65 _n66 +.def 0 +0 1 1 +1 0 1 +.names _n66 _n64 +0 1 +1 0 +# (i == 0) ? flag0 : flag1 +.mv _n68 3 idle want_in in_cs +.names flag0 flag1 _n64 _n68 +- - 0 =flag1 +- - 1 =flag0 +.mv _n69 3 idle want_in in_cs +.names _n69 +idle +# (pc == 15) ? 0 : (i == 0) ? flag0 : flag1 +.mv _n6a 3 idle want_in in_cs +.names _n69 _n68 _n62 _n6a +- - 0 =_n68 +- - 1 =_n69 +.mv _n6b 3 idle want_in in_cs +.names _n6b +in_cs +# (pc == 6) ? 2 : (pc == 15) ? 0 : (i == 0) ? flag0 : flag1 +.mv _n6c 3 idle want_in in_cs +.names _n6b _n6a _n60 _n6c +- - 0 =_n6a +- - 1 =_n6b +.mv _n6d 3 idle want_in in_cs +.names _n6d +want_in +# (pc == 0) ? 1 : (pc == 6) ? 2 : (pc == 15) ? 0 : (i == 0) ? flag0 : flag1 +.mv _n6e 3 idle want_in in_cs +.names _n6d _n6c _n5e _n6e +- - 0 =_n6c +- - 1 =_n6d +.names _n6e out_flag$raw_n5d +- =_n6e +# assign out_turn = (pc == L11 ) ? i : (pc == L15 ) ? j : turn +.mv _n71 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n71 +L11 +# pc == 10 +.names pc _n71 _n70 +.def 0 +- =pc 1 +.mv _n73 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n73 +L15 +# pc == 14 +.names pc _n73 _n72 +.def 0 +- =pc 1 +# (pc == 14) ? j : turn +.names j turn _n72 _n74 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# (pc == 10) ? i : (pc == 14) ? j : turn +.names i _n74 _n70 _n76 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n76 out_turn$raw_n6f +- =_n76 +# assign nond_exit = $NDset ( ,0,1 ) +.names nond_exit +0 +1 +# j = 0 +.names j$raw_n7a +0 +# pc = 0 +.mv pc$raw_n7b 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$raw_n7b +L1 +# non-blocking assignments for initial +.names _n7d +1 +# perm == 1 +.names perm _n7d _n7e +.def 0 +0 1 1 +1 0 1 +.names _n7e _n7c +0 1 +1 0 +.names _n7c _n80 +- =_n7c +.mv _n83 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n83 +L1 +.names pc _n83 _n82 +.def 0 +- =pc 1 +.names _n82 _n81 +1 1 +0 0 +# pc = 1 +.mv pc$_n81_n84$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n81_n84$true +L2 +.mv _n87 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n87 +L2 +.names pc _n87 _n86 +.def 0 +- =pc 1 +.names _n86 _n85 +1 1 +0 0 +# j = turn +.names turn j$_n85_n88$true +- =turn +# pc = 2 +.mv pc$_n85_n89$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n85_n89$true +L3 +.mv _n8c 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n8c +L3 +.names pc _n8c _n8b +.def 0 +- =pc 1 +.names _n8b _n8a +1 1 +0 0 +# j != i +.names j i _n8e +.def 0 +0 1 1 +1 0 1 +.names _n8e _n8d +- =_n8e +.names _n8d _n90 +- =_n8d +# pc = 3 +.mv pc$_n8d_n91$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n8d_n91$true +L4 +# pc = 6 +.mv pc$_n8d_n92$false 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n8d_n92$false +L7 +# if/else (j != i ) +.mv pc$_n8d$raw_n94 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n8d_n91$true pc$_n8d_n92$false _n8d pc$_n8d$raw_n94 +- - 0 =pc$_n8d_n92$false +- - 1 =pc$_n8d_n91$true +.mv _n99 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n99 +L4 +.names pc _n99 _n98 +.def 0 +- =pc 1 +.names _n98 _n97 +1 1 +0 0 +.mv _n9b 3 idle want_in in_cs +.names _n9b +idle +# flagj != 0 +.names flagj _n9b _n9a +.def 1 +- =flagj 0 +.names _n9a _n9c +- =_n9a +# pc = 4 +.mv pc$_n9a_n9d$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n9a_n9d$true +L5 +# pc = 5 +.mv pc$_n9a_n9e$false 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n9a_n9e$false +L6 +# if/else (flagj != 0) +.mv pc$_n9a$raw_na0 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n9a_n9d$true pc$_n9a_n9e$false _n9a pc$_n9a$raw_na0 +- - 0 =pc$_n9a_n9e$false +- - 1 =pc$_n9a_n9d$true +.mv _na5 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _na5 +L5 +.names pc _na5 _na4 +.def 0 +- =pc 1 +.names _na4 _na3 +1 1 +0 0 +# j = turn +.names turn j$_na3_na6$true +- =turn +# pc = 2 +.mv pc$_na3_na7$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_na3_na7$true +L3 +.mv _naa 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _naa +L6 +.names pc _naa _na9 +.def 0 +- =pc 1 +.names _na9 _na8 +1 1 +0 0 +.names _nac<0> +0 +.names _nac<1> +1 +.names _nad<0> +1 +.names _nad<1> +0 +# 2 - 1 +.names _naf +0 +.names _nac<0> _nad<0> _naf _nae<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _nb1 +0 +.names _nac<0> _nad<0> _nb1 _nb0 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _nac<1> _nad<1> _nb0 _nae<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# j == 2 - 1 +.names j _nae<0> _nb2<0> +.def 0 +0 1 1 +1 0 1 +.names _nae<1> _nb2<1> +- =_nae<1> +.names _nb2<0> _nb2<1> _nb3 +.def 1 +0 0 0 +.names _nb3 _nab +0 1 +1 0 +.names _nab _nb4 +- =_nab +# j = 0 +.names j$_nab_nb5$true +0 +# j = j + 1 +.names _nb7 +1 +# j + 1 +.names _nb9 +0 +.names j _nb7 _nb9 _nb8 +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _nbb +0 +.names j _nb7 _nbb _nba +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _nb8 j$_nab_nb6$false +- =_nb8 +# if/else (j == 2 - 1) +.names j$_nab_nb5$true j$_nab_nb6$false _nab j$_nab$raw_nbd +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# pc = 2 +.mv pc$_na8_nc1$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_na8_nc1$true +L3 +.mv _nc4 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _nc4 +L7 +.names pc _nc4 _nc3 +.def 0 +- =pc 1 +.names _nc3 _nc2 +1 1 +0 0 +# pc = 7 +.mv pc$_nc2_nc5$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_nc2_nc5$true +L8 +.mv _nc8 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _nc8 +L8 +.names pc _nc8 _nc7 +.def 0 +- =pc 1 +.names _nc7 _nc6 +1 1 +0 0 +# j = 0 +.names j$_nc6_nc9$true +0 +# pc = 8 +.mv pc$_nc6_nca$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_nc6_nca$true +L9 +.mv _ncd 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _ncd +L9 +.names pc _ncd _ncc +.def 0 +- =pc 1 +.names _ncc _ncb +1 1 +0 0 +.names _nce +0 +# j < 2 +.names _nd1 +0 +.names j _nce _nd1 _nd0 +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _nd3 +0 +.names j _nce _nd3 _nd2 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _nd0 _nd4 +- =_nd0 +.names _nd2 _nd4 _ncf +.def 0 +1 1 1 +# j == i +.names j i _nd6 +.def 0 +0 1 1 +1 0 1 +.names _nd6 _nd5 +0 1 +1 0 +.mv _nd9 3 idle want_in in_cs +.names _nd9 +in_cs +# flagj != 2 +.names flagj _nd9 _nd8 +.def 1 +- =flagj 0 +# (j == i ) || (flagj != 2) +.names _nd5 _nd8 _nda +.def 1 +0 0 0 +# (j < 2) && ((j == i ) || (flagj != 2)) +.names _ncf _nda _ndb +.def 0 +1 1 1 +.names _ndb _ndc +- =_ndb +# j = j + 1 +.names _nde +1 +# j + 1 +.names _ne0 +0 +.names j _nde _ne0 _ndf +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _ne2 +0 +.names j _nde _ne2 _ne1 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _ndf j$_ndb_ndd$true +- =_ndf +# pc = 8 +.mv pc$_ndb_ne3$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_ndb_ne3$true +L9 +# pc = 9 +.mv pc$_ndb_ne4$false 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_ndb_ne4$false +L10 +# if/else ((j < 2) && ((j == i ) || (flagj != 2))) +.mv pc$_ndb$raw_ne7 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_ndb_ne3$true pc$_ndb_ne4$false _ndb pc$_ndb$raw_ne7 +- - 0 =pc$_ndb_ne4$false +- - 1 =pc$_ndb_ne3$true +.names j$_ndb_ndd$true j _ndb j$_ndb$raw_nea +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _nef 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _nef +L10 +.names pc _nef _nee +.def 0 +- =pc 1 +.names _nee _ned +1 1 +0 0 +.names _nf0 +0 +# j >= 2 +.names _nf3 +0 +.names j _nf0 _nf3 _nf2 +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _nf5 +0 +.names j _nf0 _nf5 _nf4 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _nf2 _nf6 +- =_nf2 +.names _nf4 _nf6 _nf7 +.def 0 +1 1 1 +.names _nf7 _nf1 +0 1 +1 0 +# turn == i +.names turn i _nf9 +.def 0 +0 1 1 +1 0 1 +.names _nf9 _nf8 +0 1 +1 0 +.mv _nfc 3 idle want_in in_cs +.names _nfc +idle +# flagturn == 0 +.names flagturn _nfc _nfb +.def 0 +- =flagturn 1 +# (turn == i ) || (flagturn == 0) +.names _nf8 _nfb _nfd +.def 1 +0 0 0 +# (j >= 2) && ((turn == i ) || (flagturn == 0)) +.names _nf1 _nfd _nfe +.def 0 +1 1 1 +.names _nfe _nff +- =_nfe +# pc = 10 +.mv pc$_nfe_n100$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_nfe_n100$true +L11 +# pc = 0 +.mv pc$_nfe_n101$false 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_nfe_n101$false +L1 +# if/else ((j >= 2) && ((turn == i ) || (flagturn == 0))) +.mv pc$_nfe$raw_n103 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_nfe_n100$true pc$_nfe_n101$false _nfe pc$_nfe$raw_n103 +- - 0 =pc$_nfe_n101$false +- - 1 =pc$_nfe_n100$true +.mv _n108 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n108 +L11 +.names pc _n108 _n107 +.def 0 +- =pc 1 +.names _n107 _n106 +1 1 +0 0 +# pc = 11 +.mv pc$_n106_n109$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n106_n109$true +L12 +.mv _n10c 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n10c +L12 +.names pc _n10c _n10b +.def 0 +- =pc 1 +.names _n10b _n10a +1 1 +0 0 +.names _n10e +1 +# nond_exit == 1 +.names nond_exit _n10e _n10f +.def 0 +0 1 1 +1 0 1 +.names _n10f _n10d +0 1 +1 0 +.names _n10d _n111 +- =_n10d +# pc = 12 +.mv pc$_n10d_n112$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n10d_n112$true +L13 +# pc = 11 +.mv pc$_n10d_n113$false 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n10d_n113$false +L12 +# if/else (nond_exit == 1) +.mv pc$_n10d$raw_n115 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n10d_n112$true pc$_n10d_n113$false _n10d pc$_n10d$raw_n115 +- - 0 =pc$_n10d_n113$false +- - 1 =pc$_n10d_n112$true +.mv _n11a 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n11a +L13 +.names pc _n11a _n119 +.def 0 +- =pc 1 +.names _n119 _n118 +1 1 +0 0 +.names _n11c<0> +0 +.names _n11c<1> +1 +.names _n11d<0> +1 +.names _n11d<1> +0 +# 2 - 1 +.names _n11f +0 +.names _n11c<0> _n11d<0> _n11f _n11e<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n121 +0 +.names _n11c<0> _n11d<0> _n121 _n120 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n11c<1> _n11d<1> _n120 _n11e<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# turn == 2 - 1 +.names turn _n11e<0> _n122<0> +.def 0 +0 1 1 +1 0 1 +.names _n11e<1> _n122<1> +- =_n11e<1> +.names _n122<0> _n122<1> _n123 +.def 1 +0 0 0 +.names _n123 _n11b +0 1 +1 0 +.names _n11b _n124 +- =_n11b +# j = 0 +.names j$_n11b_n125$true +0 +# j = turn + 1 +.names _n127 +1 +# turn + 1 +.names _n129 +0 +.names turn _n127 _n129 _n128 +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n12b +0 +.names turn _n127 _n12b _n12a +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n128 j$_n11b_n126$false +- =_n128 +# if/else (turn == 2 - 1) +.names j$_n11b_n125$true j$_n11b_n126$false _n11b j$_n11b$raw_n12d +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# pc = 13 +.mv pc$_n118_n131$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n118_n131$true +L14 +.mv _n134 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n134 +L14 +.names pc _n134 _n133 +.def 0 +- =pc 1 +.names _n133 _n132 +1 1 +0 0 +.mv _n136 3 idle want_in in_cs +.names _n136 +idle +# flagj == 0 +.names flagj _n136 _n135 +.def 0 +- =flagj 1 +.names _n135 _n137 +- =_n135 +.names _n139<0> +0 +.names _n139<1> +1 +.names _n13a<0> +1 +.names _n13a<1> +0 +# 2 - 1 +.names _n13c +0 +.names _n139<0> _n13a<0> _n13c _n13b<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n13e +0 +.names _n139<0> _n13a<0> _n13e _n13d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n139<1> _n13a<1> _n13d _n13b<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# j == 2 - 1 +.names j _n13b<0> _n13f<0> +.def 0 +0 1 1 +1 0 1 +.names _n13b<1> _n13f<1> +- =_n13b<1> +.names _n13f<0> _n13f<1> _n140 +.def 1 +0 0 0 +.names _n140 _n138 +0 1 +1 0 +.names _n138 _n141 +- =_n138 +# j = 0 +.names j$_n138_n142$true +0 +# j = j + 1 +.names _n144 +1 +# j + 1 +.names _n146 +0 +.names j _n144 _n146 _n145 +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n148 +0 +.names j _n144 _n148 _n147 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n145 j$_n138_n143$false +- =_n145 +# if/else (j == 2 - 1) +.names j$_n138_n142$true j$_n138_n143$false _n138 j$_n138$raw_n14a +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# pc = 13 +.mv pc$_n135_n14e$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n135_n14e$true +L14 +# pc = 14 +.mv pc$_n135_n14f$false 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n135_n14f$false +L15 +# if/else (flagj == 0) +.mv pc$_n135$raw_n152 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n135_n14e$true pc$_n135_n14f$false _n135 pc$_n135$raw_n152 +- - 0 =pc$_n135_n14f$false +- - 1 =pc$_n135_n14e$true +.names j$_n138$raw_n14a j _n135 j$_n135$raw_n155 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _n15a 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n15a +L15 +.names pc _n15a _n159 +.def 0 +- =pc 1 +.names _n159 _n158 +1 1 +0 0 +# pc = 15 +.mv pc$_n158_n15b$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n158_n15b$true +L16 +.mv _n15e 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n15e +L16 +.names pc _n15e _n15d +.def 0 +- =pc 1 +.names _n15d _n15c +1 1 +0 0 +.names _n160 +1 +# nond_exit == 1 +.names nond_exit _n160 _n161 +.def 0 +0 1 1 +1 0 1 +.names _n161 _n15f +0 1 +1 0 +.names _n15f _n163 +- =_n15f +# pc = 0 +.mv pc$_n15f_n164$true 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n15f_n164$true +L1 +# pc = 15 +.mv pc$_n15f_n165$false 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n15f_n165$false +L16 +# if/else (nond_exit == 1) +.mv pc$_n15f$raw_n167 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n15f_n164$true pc$_n15f_n165$false _n15f pc$_n15f$raw_n167 +- - 0 =pc$_n15f_n165$false +- - 1 =pc$_n15f_n164$true +# case (pc ) +.mv pc$_n15c$raw_n16c 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n15f$raw_n167 pc _n15c pc$_n15c$raw_n16c +- - 0 =pc +- - 1 =pc$_n15f$raw_n167 +.mv pc$_n158$raw_n16e 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n158_n15b$true pc$_n15c$raw_n16c _n158 pc$_n158$raw_n16e +- - 0 =pc$_n15c$raw_n16c +- - 1 =pc$_n158_n15b$true +.mv pc$_n132$raw_n173 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n135$raw_n152 pc$_n158$raw_n16e _n132 pc$_n132$raw_n173 +- - 0 =pc$_n158$raw_n16e +- - 1 =pc$_n135$raw_n152 +.names j$_n135$raw_n155 j _n132 j$_n132$raw_n176 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n118$raw_n17b 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n118_n131$true pc$_n132$raw_n173 _n118 pc$_n118$raw_n17b +- - 0 =pc$_n132$raw_n173 +- - 1 =pc$_n118_n131$true +.names j$_n11b$raw_n12d j$_n132$raw_n176 _n118 j$_n118$raw_n17c +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n10a$raw_n183 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n10d$raw_n115 pc$_n118$raw_n17b _n10a pc$_n10a$raw_n183 +- - 0 =pc$_n118$raw_n17b +- - 1 =pc$_n10d$raw_n115 +.names j j$_n118$raw_n17c _n10a j$_n10a$raw_n186 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n106$raw_n189 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n106_n109$true pc$_n10a$raw_n183 _n106 pc$_n106$raw_n189 +- - 0 =pc$_n10a$raw_n183 +- - 1 =pc$_n106_n109$true +.names j j$_n10a$raw_n186 _n106 j$_n106$raw_n18c +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_ned$raw_n18f 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_nfe$raw_n103 pc$_n106$raw_n189 _ned pc$_ned$raw_n18f +- - 0 =pc$_n106$raw_n189 +- - 1 =pc$_nfe$raw_n103 +.names j j$_n106$raw_n18c _ned j$_ned$raw_n192 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_ncb$raw_n196 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_ndb$raw_ne7 pc$_ned$raw_n18f _ncb pc$_ncb$raw_n196 +- - 0 =pc$_ned$raw_n18f +- - 1 =pc$_ndb$raw_ne7 +.names j$_ndb$raw_nea j$_ned$raw_n192 _ncb j$_ncb$raw_n197 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_nc6$raw_n19f 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_nc6_nca$true pc$_ncb$raw_n196 _nc6 pc$_nc6$raw_n19f +- - 0 =pc$_ncb$raw_n196 +- - 1 =pc$_nc6_nca$true +.names j$_nc6_nc9$true j$_ncb$raw_n197 _nc6 j$_nc6$raw_n1a0 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_nc2$raw_n1a7 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_nc2_nc5$true pc$_nc6$raw_n19f _nc2 pc$_nc2$raw_n1a7 +- - 0 =pc$_nc6$raw_n19f +- - 1 =pc$_nc2_nc5$true +.names j j$_nc6$raw_n1a0 _nc2 j$_nc2$raw_n1aa +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_na8$raw_n1ae 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_na8_nc1$true pc$_nc2$raw_n1a7 _na8 pc$_na8$raw_n1ae +- - 0 =pc$_nc2$raw_n1a7 +- - 1 =pc$_na8_nc1$true +.names j$_nab$raw_nbd j$_nc2$raw_n1aa _na8 j$_na8$raw_n1af +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_na3$raw_n1b7 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_na3_na7$true pc$_na8$raw_n1ae _na3 pc$_na3$raw_n1b7 +- - 0 =pc$_na8$raw_n1ae +- - 1 =pc$_na3_na7$true +.names j$_na3_na6$true j$_na8$raw_n1af _na3 j$_na3$raw_n1b8 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n97$raw_n1bf 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n9a$raw_na0 pc$_na3$raw_n1b7 _n97 pc$_n97$raw_n1bf +- - 0 =pc$_na3$raw_n1b7 +- - 1 =pc$_n9a$raw_na0 +.names j j$_na3$raw_n1b8 _n97 j$_n97$raw_n1c2 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n8a$raw_n1c5 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n8d$raw_n94 pc$_n97$raw_n1bf _n8a pc$_n8a$raw_n1c5 +- - 0 =pc$_n97$raw_n1bf +- - 1 =pc$_n8d$raw_n94 +.names j j$_n97$raw_n1c2 _n8a j$_n8a$raw_n1c8 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n85$raw_n1cc 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n85_n89$true pc$_n8a$raw_n1c5 _n85 pc$_n85$raw_n1cc +- - 0 =pc$_n8a$raw_n1c5 +- - 1 =pc$_n85_n89$true +.names j$_n85_n88$true j$_n8a$raw_n1c8 _n85 j$_n85$raw_n1cd +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv pc$_n81$raw_n1d4 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n81_n84$true pc$_n85$raw_n1cc _n81 pc$_n81$raw_n1d4 +- - 0 =pc$_n85$raw_n1cc +- - 1 =pc$_n81_n84$true +.names j j$_n85$raw_n1cd _n81 j$_n81$raw_n1d7 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (perm == 1) +.mv pc$_n7c$raw_n1dd 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names pc$_n81$raw_n1d4 pc _n7c pc$_n7c$raw_n1dd +- - 0 =pc +- - 1 =pc$_n81$raw_n1d4 +.names j$_n81$raw_n1d7 j _n7c j$_n7c$raw_n1de +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names flagturn$raw_n57 flagturn +- =flagturn$raw_n57 +.names flagj$raw_n51 flagj +- =flagj$raw_n51 +.names _n80 _n81 _n85 _n8a _n90 _n97 _n9c _na3 _na8 _nc2 _nc6 _ncb _ndc _ned _nff _n106 _n10a _n111 _n118 _n132 _n137 _n158 _n15c _n163 _n1e0 +.def 0 + 1 1 - - - - - - - - - - - - - - - - - - - - - - 1 + 1 0 1 - - - - - - - - - - - - - - - - - - - - - 1 + 1 0 0 1 1 - - - - - - - - - - - - - - - - - - - 1 + 1 0 0 1 0 - - - - - - - - - - - - - - - - - - - 1 + 1 0 0 0 - 1 1 - - - - - - - - - - - - - - - - - 1 + 1 0 0 0 - 1 0 - - - - - - - - - - - - - - - - - 1 + 1 0 0 0 - 0 - 1 - - - - - - - - - - - - - - - - 1 + 1 0 0 0 - 0 - 0 1 - - - - - - - - - - - - - - - 1 + 1 0 0 0 - 0 - 0 0 1 - - - - - - - - - - - - - - 1 + 1 0 0 0 - 0 - 0 0 0 1 - - - - - - - - - - - - - 1 + 1 0 0 0 - 0 - 0 0 0 0 1 1 - - - - - - - - - - - 1 + 1 0 0 0 - 0 - 0 0 0 0 1 0 - - - - - - - - - - - 1 + 1 0 0 0 - 0 - 0 0 0 0 0 - 1 1 - - - - - - - - - 1 + 1 0 0 0 - 0 - 0 0 0 0 0 - 1 0 - - - - - - - - - 1 + 1 0 0 0 - 0 - 0 0 0 0 0 - 0 - 1 - - - - - - - - 1 + 1 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 1 1 - - - - - - 1 + 1 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 1 0 - - - - - - 1 + 1 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 - 1 - - - - - 1 + 1 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 - 0 1 1 - - - 1 + 1 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 - 0 1 0 - - - 1 + 1 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 - 0 0 - 1 - - 1 + 1 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 - 0 0 - 0 1 1 1 + 1 0 0 0 - 0 - 0 0 0 0 0 - 0 - 0 0 - 0 0 - 0 1 0 1 +.mv _n1e1 16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 +.names _n1e0 pc$_n7c$raw_n1dd pc _n1e1 +1 - - =pc$_n7c$raw_n1dd +0 - - =pc +.names out_turn$raw_n6f out_turn +0 0 +1 1 +.names out_flag$raw_n5d out_flag +- =out_flag$raw_n5d +.names _n80 _n81 _n85 _n8a _n97 _na3 _na8 _nb4 _nc2 _nc6 _ncb _ndc _ned _n106 _n10a _n118 _n124 _n132 _n137 _n141 _n1eb +.def 0 + 1 0 1 - - - - - - - - - - - - - - - - - 1 + 1 0 0 0 0 1 - - - - - - - - - - - - - - 1 + 1 0 0 0 0 0 1 1 - - - - - - - - - - - - 1 + 1 0 0 0 0 0 1 0 - - - - - - - - - - - - 1 + 1 0 0 0 0 0 0 - 0 1 - - - - - - - - - - 1 + 1 0 0 0 0 0 0 - 0 0 1 1 - - - - - - - - 1 + 1 0 0 0 0 0 0 - 0 0 0 - 0 0 0 1 1 - - - 1 + 1 0 0 0 0 0 0 - 0 0 0 - 0 0 0 1 0 - - - 1 + 1 0 0 0 0 0 0 - 0 0 0 - 0 0 0 0 - 1 1 1 1 + 1 0 0 0 0 0 0 - 0 0 0 - 0 0 0 0 - 1 1 0 1 +.names _n1eb j$_n7c$raw_n1de j _n1ec +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +# non-blocking assignments +# latches +.r pc$raw_n7b pc +- =pc$raw_n7b +.latch _n1e1 pc +.r j$raw_n7a j +0 0 +1 1 +.latch _n1ec j +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/eisenberg/eisenberg.v =================================================================== --- vis_dev/vis-2.1/examples/eisenberg/eisenberg.v (revision 11) +++ vis_dev/vis-2.1/examples/eisenberg/eisenberg.v (revision 11) @@ -0,0 +1,141 @@ +/* the interleaving is emulated in the system process by permit variables */ + +`define N 2 + +/* to emulate program counter */ +typedef enum { L1, L2, L3, L4, L5, L6, L7, L8, + L9, L10, L11, L12, L13, L14, L15, L16 } loc; + +/* state of how hard a process want to enter critical section */ +typedef enum { idle, want_in, in_cs } flag_type; + +module system (clk); +input clk; + +/* flag? and turn are shared memory */ +flag_type reg flag0, flag1; +reg turn; + +flag_type wire out_flag0, out_flag1; +wire out_turn0, out_turn1; + +wire perm0, perm1; +reg st_perm0, st_perm1; +// st_pterm? just show which process is chosen + +/* the current processes */ +process p0(clk, perm0, flag0, flag1, out_flag0, turn, out_turn0, 0); +process p1(clk, perm1, flag0, flag1, out_flag1, turn, out_turn1, 1); + +/* the processes are chosen to be executed by CPU nondeterministically */ +assign perm0 = $NDset(@(posedge clk), 0, 1); +assign perm1 = ~perm0; + +/* only OS/CPU can update system memory */ +initial begin flag0=idle; flag1=idle; turn=0; end +initial st_perm0 = $ND(0,1); +initial st_perm1 = $ND(0,1); +always @(posedge clk) begin + st_perm0 = perm0; st_perm1 = perm1; + if (perm0==1) begin flag0 = out_flag0; turn = out_turn0; end + else if(perm1==1) begin flag1 = out_flag1; turn = out_turn1; end +end + +endmodule + + +/* individual process */ +module process (clk, perm, flag0, flag1, out_flag, turn, out_turn, i); +input clk; +input perm; +input flag0, flag1; +output out_flag; +input turn; +output out_turn; +input i; + +flag_type wire flag0, flag1; +flag_type wire out_flag; + +// pc and j are local to each process +loc reg pc; +reg j; + +flag_type wire flagj, flagturn; +wire nond_exit; + +assign flagj = (j==0) ? flag0 : flag1, + flagturn = (turn==0) ? flag0 : flag1; + +/* if the process decide to change system wide data */ +assign out_flag = (pc==L1) ? want_in : + (pc==L7) ? in_cs : + (pc==L16)? idle : + (i==0) ? flag0 : flag1; +assign out_turn = (pc==L11) ? i : (pc==L15) ? j : turn; +assign nond_exit = $NDset(@(posedge clk), 0, 1); + +initial begin j=0; pc=L1; end + +// ----- the program is executed forever ----- +always @(posedge clk) begin + if (perm==1) begin + case (pc) +// repeat flag[i]=want_in; + L1: begin pc=L2; end +// j=turn; + L2: begin j=turn; pc=L3; end +// while (j != i) + L3: begin if (j!=i) pc=L4; else pc=L7; end +// do if (flag[j] != idle) + L4: begin if (flagj != idle) pc=L5; else pc=L6; end +// then j = turn; + L5: begin j=turn; pc=L3; end +// else j = j+1 mod `N; + L6: begin if (j==`N-1) j=0; else j=j+1; pc=L3; end +// flag[i] = in_cs; + L7: begin pc=L8; end +// j=0; + L8: begin j=0; pc=L9; end +// while ((j<`N) && (j==i || flag[j] != in_cs)) do j=j+1; + L9: begin + if ((j<`N) && ((j==i) || (flagj!=in_cs))) + begin j=j+1; pc=L9; end + else pc=L10; + end +// until (j>=`N) && ((turn==i) || flag[turn] == idle); + L10: begin + if ((j>=`N) && ((turn==i) || (flagturn==idle))) + pc=L11; + else + pc=L1; + end +// turn = i; + L11: begin pc=L12; end +// critical section + +// ----- CRITICAL SECTION ----- + L12: begin if (nond_exit==1) pc=L13; else pc=L12; end +// j = turn+1 mod `N; + L13: begin if (turn==`N-1) j=0; else j=turn+1; pc=L14; end +// while (flag[j] == idle) do j=j+1 mod `N; + L14: begin if (flagj==idle) + begin + if (j==`N-1) j=0; + else j=j+1; + pc=L14; + end + else pc=L15; + end +// turn = j; + L15: begin pc=L16; end +// flag[i] = idle; + L16: begin if (nond_exit==1) pc=L1; else pc=L16; end + +// ----- REMAINDER SECTION ----- + default: ; + endcase + end +end + +endmodule Index: vis_dev/vis-2.1/examples/elevator/README =================================================================== --- vis_dev/vis-2.1/examples/elevator/README (revision 11) +++ vis_dev/vis-2.1/examples/elevator/README (revision 11) @@ -0,0 +1,4 @@ +This example has 2 elevators and 3 floors. The verilog code +uses a "for" construct, so that the .mv file should be made +with the -u option in vl2mv,i.e. + vl2mv -u elevator.v Index: vis_dev/vis-2.1/examples/elevator/check_result =================================================================== --- vis_dev/vis-2.1/examples/elevator/check_result (revision 11) +++ vis_dev/vis-2.1/examples/elevator/check_result (revision 11) @@ -0,0 +1,9 @@ +# INV: formula passed --- (movement=MOVING -> door=CLOSED) +# MC: formula passed --- AG((movement=MOVING -> door=CLOSED)) +# MC: formula failed --- AG((buttons<*0*>=ON -> AF(((door=OPEN * location<0>=0) * location<1>=0)))) +Networks are combinationally equivalent. +FSM depth = 26 +reachable states = 674077 +# INV: formula passed --- (e1.movement=MOVING -> e1.door=CLOSED) +# INV: formula failed --- (e1.movement=MOVING -> e2.door=CLOSED) +# INV: formula passed --- ((e1.location<0>=1 <-> main_control.locations<*1*><0>=1) * (e1.location<1>=1 <-> main_control.locations<*1*><1>=1)) Index: vis_dev/vis-2.1/examples/elevator/check_script =================================================================== --- vis_dev/vis-2.1/examples/elevator/check_script (revision 11) +++ vis_dev/vis-2.1/examples/elevator/check_script (revision 11) @@ -0,0 +1,35 @@ +read_blif_mv elevator.mv +# move to a sub module +cd e1 +init_verify +# the following should pass +check_invariant -d 0 emodel.inv +read_fairness emodel.fair +# the following should pass the first formula and fail the second +model_check -d 0 emodel.ctl +write_blif_mv emodel.mv +write_blif -c -e elevator.enc emodel.blif +read_blif -e elevator.enc emodel-simp.blif +init_verify +comb_verify emodel.mv +# move back up to the root +cd .. +init_verify +dynamic_var_ordering -f sift +print_img_info +dynamic_var_ordering -f sift +write_order order +# fast flatten - do not need to check tables at this point +flatten_hierarchy +static_order -s input_and_latch order +build_partition_mdds +print_img_info +dynamic_var_ordering -f sift +# the following takes 15 sec on cad. There are 674077 reached states +# reached in 26 BFS. +compute_reach -v 1 +read_fairness elevator.fair +check_invariant -d 0 elevator.inv +# this is so slow. maybe not good for regression testing +#lang_empty -d 0 +quit -s Index: vis_dev/vis-2.1/examples/elevator/elevator.ctl =================================================================== --- vis_dev/vis-2.1/examples/elevator/elevator.ctl (revision 11) +++ vis_dev/vis-2.1/examples/elevator/elevator.ctl (revision 11) @@ -0,0 +1,1 @@ +AG ((main_control.up_floor_buttons<*1*>=ON) -> AF ( e1.location<1>=0 * e1.location<0>=1 * e1.door=OPEN * e1.direction=UP + e2.location<1>=0 * e2.location<0>=1 * e2.door=OPEN * e2.direction=UP )); Index: vis_dev/vis-2.1/examples/elevator/elevator.enc =================================================================== --- vis_dev/vis-2.1/examples/elevator/elevator.enc (revision 11) +++ vis_dev/vis-2.1/examples/elevator/elevator.enc (revision 11) @@ -0,0 +1,221 @@ +.model elevator[0] +.inputs init<0> init<1> stop_next continue +.outputs dec inc +.table init<0> ->init<0>0 +0 0 +1 1 +.table init<1> ->init<1>0 +0 0 +1 1 +.table stop_next ->stop_next0 +0 0 +1 1 +.table continue ->continue0 +0 0 +1 1 +.table dec0 ->dec +0 0 +1 1 +.table inc0 ->inc +0 0 +1 1 +.mv _n245 2 STOPPED MOVING +.mv movement 2 STOPPED MOVING +.table _n2450 ->_n245 +0 STOPPED +1 MOVING +.table movement ->movement0 +STOPPED 0 +MOVING 1 +.mv movement$raw_n1a 2 STOPPED MOVING +.table movement$raw_n1a0 ->movement$raw_n1a +0 STOPPED +1 MOVING +.mv _n25c<*2*> 2 ON OFF +.mv buttons<*2*> 2 ON OFF +.table _n25c<*2*>0 ->_n25c<*2*> +0 ON +1 OFF +.table buttons<*2*> ->buttons<*2*>0 +ON 0 +OFF 1 +.mv buttons$raw_n1b<*2*> 2 ON OFF +.table buttons$raw_n1b<*2*>0 ->buttons$raw_n1b<*2*> +0 ON +1 OFF +.mv buttons$raw_n2d<*2*> 2 ON OFF +.table buttons$raw_n2d<*2*>0 ->buttons$raw_n2d<*2*> +0 ON +1 OFF +.mv buttons$raw_n3f<*2*> 2 ON OFF +.table buttons$raw_n3f<*2*>0 ->buttons$raw_n3f<*2*> +0 ON +1 OFF +.mv _n25c<*0*> 2 ON OFF +.mv buttons<*0*> 2 ON OFF +.table _n25c<*0*>0 ->_n25c<*0*> +0 ON +1 OFF +.table buttons<*0*> ->buttons<*0*>0 +ON 0 +OFF 1 +.mv buttons$raw_n1b<*0*> 2 ON OFF +.table buttons$raw_n1b<*0*>0 ->buttons$raw_n1b<*0*> +0 ON +1 OFF +.mv buttons$raw_n2d<*0*> 2 ON OFF +.table buttons$raw_n2d<*0*>0 ->buttons$raw_n2d<*0*> +0 ON +1 OFF +.mv buttons$raw_n3f<*0*> 2 ON OFF +.table buttons$raw_n3f<*0*>0 ->buttons$raw_n3f<*0*> +0 ON +1 OFF +.mv _n29d 4 OPEN OPENING CLOSED CLOSING +.mv door 4 OPEN OPENING CLOSED CLOSING +.table _n29d0 _n29d1 ->_n29d +0 0 OPEN +1 0 OPENING +0 1 CLOSED +1 1 CLOSING +.table door ->door0 door1 +OPEN 0 0 +OPENING 1 0 +CLOSED 0 1 +CLOSING 1 1 +.mv door$raw_n19 4 OPEN OPENING CLOSED CLOSING +.table door$raw_n190 door$raw_n191 ->door$raw_n19 +0 0 OPEN +1 0 OPENING +0 1 CLOSED +1 1 CLOSING +.table _n2b4<0>0 ->_n2b4<0> +0 0 +1 1 +.table location<0> ->location<0>0 +0 0 +1 1 +.table location$raw_n17<0>0 ->location$raw_n17<0> +0 0 +1 1 +.mv _n25c<*1*> 2 ON OFF +.mv buttons<*1*> 2 ON OFF +.table _n25c<*1*>0 ->_n25c<*1*> +0 ON +1 OFF +.table buttons<*1*> ->buttons<*1*>0 +ON 0 +OFF 1 +.mv buttons$raw_n1b<*1*> 2 ON OFF +.table buttons$raw_n1b<*1*>0 ->buttons$raw_n1b<*1*> +0 ON +1 OFF +.mv buttons$raw_n2d<*1*> 2 ON OFF +.table buttons$raw_n2d<*1*>0 ->buttons$raw_n2d<*1*> +0 ON +1 OFF +.mv buttons$raw_n3f<*1*> 2 ON OFF +.table buttons$raw_n3f<*1*>0 ->buttons$raw_n3f<*1*> +0 ON +1 OFF +.mv _n2b6 2 UP DOWN +.mv direction 2 UP DOWN +.table _n2b60 ->_n2b6 +0 UP +1 DOWN +.table direction ->direction0 +UP 0 +DOWN 1 +.mv direction$raw_n18 2 UP DOWN +.table direction$raw_n180 ->direction$raw_n18 +0 UP +1 DOWN +.table _n2cd0 ->_n2cd +0 0 +1 1 +.table open_next ->open_next0 +0 0 +1 1 +.table open_next$raw_n160 ->open_next$raw_n16 +0 0 +1 1 +.table _n2b4<1>0 ->_n2b4<1> +0 0 +1 1 +.table location<1> ->location<1>0 +0 0 +1 1 +.table location$raw_n17<1>0 ->location$raw_n17<1> +0 0 +1 1 +.latch _n245 movement +.reset movement$raw_n1a ->movement +- =movement$raw_n1a +.latch _n25c<*2*> buttons<*2*> +.reset buttons$raw_n1b<*2*> buttons$raw_n2d<*2*> buttons$raw_n3f<*2*> ->buttons<*2*> +.default ON +OFF - - =buttons$raw_n1b<*2*> +ON OFF - =buttons$raw_n2d<*2*> +ON ON OFF =buttons$raw_n3f<*2*> +.latch _n25c<*0*> buttons<*0*> +.reset buttons$raw_n1b<*0*> buttons$raw_n2d<*0*> buttons$raw_n3f<*0*> ->buttons<*0*> +.default ON +OFF - - =buttons$raw_n1b<*0*> +ON OFF - =buttons$raw_n2d<*0*> +ON ON OFF =buttons$raw_n3f<*0*> +.latch _n29d door +.reset door$raw_n19 ->door +- =door$raw_n19 +.latch _n2b4<0> location<0> +.reset location$raw_n17<0> ->location<0> +.default 0 +1 1 +.latch _n25c<*1*> buttons<*1*> +.reset buttons$raw_n1b<*1*> buttons$raw_n2d<*1*> buttons$raw_n3f<*1*> ->buttons<*1*> +.default ON +OFF - - =buttons$raw_n1b<*1*> +ON OFF - =buttons$raw_n2d<*1*> +ON ON OFF =buttons$raw_n3f<*1*> +.latch _n2b6 direction +.reset direction$raw_n18 ->direction +- =direction$raw_n18 +.latch _n2cd open_next +.reset open_next$raw_n16 ->open_next +0 0 +1 1 +.latch _n2b4<1> location<1> +.reset location$raw_n17<1> ->location<1> +.default 0 +1 1 +.table ->random_push<0> +- +.table random_push<0> ->[0]0 +.default 0 +0 0 +1 1 +.table ->random_push<1> +- +.table random_push<1> ->[1]0 +.default 0 +0 0 +1 1 +.table ->random_push<2> +- +.table random_push<2> ->[2]0 +.default 0 +0 0 +1 1 +.table ->random +0 +1 +.table random ->[3]0 +.default 0 +0 0 +1 1 +.table ->r_stop +0 +1 +.table r_stop ->[4]0 +.default 0 +0 0 +1 1 Index: vis_dev/vis-2.1/examples/elevator/elevator.fair =================================================================== --- vis_dev/vis-2.1/examples/elevator/elevator.fair (revision 11) +++ vis_dev/vis-2.1/examples/elevator/elevator.fair (revision 11) @@ -0,0 +1,8 @@ +!(e1.door=OPENING); +!(e2.door=OPENING); +!(e1.door=OPEN); +!(e2.door=OPEN); +!(e1.door=CLOSING); +!(e2.door=CLOSING); +!(e1.movement=MOVING); +!(e2.movement=MOVING); Index: vis_dev/vis-2.1/examples/elevator/elevator.inv =================================================================== --- vis_dev/vis-2.1/examples/elevator/elevator.inv (revision 11) +++ vis_dev/vis-2.1/examples/elevator/elevator.inv (revision 11) @@ -0,0 +1,4 @@ +e1.movement=MOVING -> e1.door=CLOSED; +e1.movement=MOVING -> e2.door=CLOSED; +(e1.location<0>=1 <-> main_control.locations<*1*><0>=1) * +(e1.location<1>=1 <-> main_control.locations<*1*><1>=1); Index: vis_dev/vis-2.1/examples/elevator/elevator.mv =================================================================== --- vis_dev/vis-2.1/examples/elevator/elevator.mv (revision 11) +++ vis_dev/vis-2.1/examples/elevator/elevator.mv (revision 11) @@ -0,0 +1,7530 @@ +# vl2mv elevator.v +# version: 0.2 +# date: 17:49:14 11/22/96 (PST) +.model main +# I/O ports + +# assign init11 = $NDset ( 0,1,2,3 ) +.names -> init11<0> init11<1> +0 0 +1 0 +0 1 +1 1 +# assign init22 = $NDset ( 0,1,2,3 ) +.names -> init22<0> init22<1> +0 0 +1 0 +0 1 +1 1 +# assign init1 = init11 == 3 ? 2 : init11 +.names _n6<0> +1 +.names _n6<1> +1 +# init11 == 3 +.names init11<0> _n6<0> _n7<0> +.def 0 +0 1 1 +1 0 1 +.names init11<1> _n6<1> _n7<1> +.def 0 +0 1 1 +1 0 1 +.names _n7<0> _n7<1> _n8 +.def 1 +0 0 0 +.names _n8 _n5 +0 1 +1 0 +.names _n9<0> +0 +.names _n9<1> +1 +# init11 == 3 ? 2 : init11 +.names _n9<0> init11<0> _n5 _na<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n9<1> init11<1> _n5 _na<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _na<0> init1$raw_n4<0> +- =_na<0> +.names _na<1> init1$raw_n4<1> +- =_na<1> +# assign init2 = init22 == 3 ? 2 : init22 +.names _nf<0> +1 +.names _nf<1> +1 +# init22 == 3 +.names init22<0> _nf<0> _n10<0> +.def 0 +0 1 1 +1 0 1 +.names init22<1> _nf<1> _n10<1> +.def 0 +0 1 1 +1 0 1 +.names _n10<0> _n10<1> _n11 +.def 1 +0 0 0 +.names _n11 _ne +0 1 +1 0 +.names _n12<0> +0 +.names _n12<1> +1 +# init22 == 3 ? 2 : init22 +.names _n12<0> init22<0> _ne _n13<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n12<1> init22<1> _ne _n13<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n13<0> init2$raw_nd<0> +- =_n13<0> +.names _n13<1> init2$raw_nd<1> +- =_n13<1> +.subckt elevator e1 stop_next=stop_next<1> inc=inc<1> dec=dec<1> continue=continue<1> init<0>=init1<0> init<1>=init1<1> +.subckt elevator e2 stop_next=stop_next<2> inc=inc<2> dec=dec<2> continue=continue<2> init<0>=init2<0> init<1>=init2<1> +.subckt main_control main_control inc<1>=inc<1> inc<2>=inc<2> dec<1>=dec<1> dec<2>=dec<2> stop_next<1>=stop_next<1> stop_next<2>=stop_next<2> continue<1>=continue<1> continue<2>=continue<2> init1<0>=init1<0> init1<1>=init1<1> init2<0>=init2<0> init2<1>=init2<1> +# conflict arbitrators +.names init2$raw_nd<0> init2<0> +- =init2$raw_nd<0> +.names init2$raw_nd<1> init2<1> +- =init2$raw_nd<1> +.names init1$raw_n4<0> init1<0> +- =init1$raw_n4<0> +.names init1$raw_n4<1> init1<1> +- =init1$raw_n4<1> +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model elevator +# I/O ports +.outputs dec +.outputs inc +.inputs init<0> init<1> +.inputs stop_next +.inputs continue + +.mv movement 2 STOPPED MOVING +.mv buttons<*0*> 2 ON OFF +.mv buttons<*1*> 2 ON OFF +.mv buttons<*2*> 2 ON OFF +.mv door 4 OPEN OPENING CLOSED CLOSING +.mv direction 2 UP DOWN +# open_next = 0 +.names open_next$raw_n16 +0 +# non-blocking assignments for initial +# location = init +.names init<0> location$raw_n17<0> +- =init<0> +.names init<1> location$raw_n17<1> +- =init<1> +# non-blocking assignments for initial +# direction = 0 +.mv direction$raw_n18 2 UP DOWN +.names direction$raw_n18 +UP +# non-blocking assignments for initial +# door = 0 +.mv door$raw_n19 4 OPEN OPENING CLOSED CLOSING +.names door$raw_n19 +OPEN +# non-blocking assignments for initial +# movement = 0 +.mv movement$raw_n1a 2 STOPPED MOVING +.names movement$raw_n1a +STOPPED +# non-blocking assignments for initial +# buttons [0] = 1 +.mv buttons$raw_n1b<*0*> 2 ON OFF +.mv buttons$raw_n1b<*1*> 2 ON OFF +.mv buttons$raw_n1b<*2*> 2 ON OFF +.mv _n1c 2 ON OFF +.names _n1d<0> +0 +.names _n1d<1> +0 +.names _n1e<0> +0 +.names _n1e<1> +0 +.names _n1e<0> _n1d<0> _n20<0> +.def 0 +0 1 1 +1 0 1 +.names _n1e<1> _n1d<1> _n20<1> +.def 0 +0 1 1 +1 0 1 +.names _n20<0> _n20<1> _n21 +.def 1 +0 0 0 +.names _n21 _n1f +0 1 +1 0 +.mv _n22 2 ON OFF +.names _n22 +ON +.names _n1c _n22 _n1f buttons$raw_n1b<*0*> +- - 0 =_n22 +- - 1 =_n1c +.names _n23<0> +1 +.names _n23<1> +0 +.names _n23<0> _n1d<0> _n25<0> +.def 0 +0 1 1 +1 0 1 +.names _n23<1> _n1d<1> _n25<1> +.def 0 +0 1 1 +1 0 1 +.names _n25<0> _n25<1> _n26 +.def 1 +0 0 0 +.names _n26 _n24 +0 1 +1 0 +.mv _n27 2 ON OFF +.names _n27 +ON +.names _n1c _n27 _n24 buttons$raw_n1b<*1*> +- - 0 =_n27 +- - 1 =_n1c +.names _n28<0> +0 +.names _n28<1> +1 +.names _n28<0> _n1d<0> _n2a<0> +.def 0 +0 1 1 +1 0 1 +.names _n28<1> _n1d<1> _n2a<1> +.def 0 +0 1 1 +1 0 1 +.names _n2a<0> _n2a<1> _n2b +.def 1 +0 0 0 +.names _n2b _n29 +0 1 +1 0 +.mv _n2c 2 ON OFF +.names _n2c +ON +.names _n1c _n2c _n29 buttons$raw_n1b<*2*> +- - 0 =_n2c +- - 1 =_n1c +.names _n1c +OFF +# non-blocking assignments for initial +# buttons [1] = 1 +.mv buttons$raw_n2d<*0*> 2 ON OFF +.mv buttons$raw_n2d<*1*> 2 ON OFF +.mv buttons$raw_n2d<*2*> 2 ON OFF +.mv _n2e 2 ON OFF +.names _n2f<0> +1 +.names _n2f<1> +0 +.names _n30<0> +0 +.names _n30<1> +0 +.names _n30<0> _n2f<0> _n32<0> +.def 0 +0 1 1 +1 0 1 +.names _n30<1> _n2f<1> _n32<1> +.def 0 +0 1 1 +1 0 1 +.names _n32<0> _n32<1> _n33 +.def 1 +0 0 0 +.names _n33 _n31 +0 1 +1 0 +.mv _n34 2 ON OFF +.names _n34 +ON +.names _n2e _n34 _n31 buttons$raw_n2d<*0*> +- - 0 =_n34 +- - 1 =_n2e +.names _n35<0> +1 +.names _n35<1> +0 +.names _n35<0> _n2f<0> _n37<0> +.def 0 +0 1 1 +1 0 1 +.names _n35<1> _n2f<1> _n37<1> +.def 0 +0 1 1 +1 0 1 +.names _n37<0> _n37<1> _n38 +.def 1 +0 0 0 +.names _n38 _n36 +0 1 +1 0 +.mv _n39 2 ON OFF +.names _n39 +ON +.names _n2e _n39 _n36 buttons$raw_n2d<*1*> +- - 0 =_n39 +- - 1 =_n2e +.names _n3a<0> +0 +.names _n3a<1> +1 +.names _n3a<0> _n2f<0> _n3c<0> +.def 0 +0 1 1 +1 0 1 +.names _n3a<1> _n2f<1> _n3c<1> +.def 0 +0 1 1 +1 0 1 +.names _n3c<0> _n3c<1> _n3d +.def 1 +0 0 0 +.names _n3d _n3b +0 1 +1 0 +.mv _n3e 2 ON OFF +.names _n3e +ON +.names _n2e _n3e _n3b buttons$raw_n2d<*2*> +- - 0 =_n3e +- - 1 =_n2e +.names _n2e +OFF +# non-blocking assignments for initial +# buttons [2] = 1 +.mv buttons$raw_n3f<*0*> 2 ON OFF +.mv buttons$raw_n3f<*1*> 2 ON OFF +.mv buttons$raw_n3f<*2*> 2 ON OFF +.mv _n40 2 ON OFF +.names _n41<0> +0 +.names _n41<1> +1 +.names _n42<0> +0 +.names _n42<1> +0 +.names _n42<0> _n41<0> _n44<0> +.def 0 +0 1 1 +1 0 1 +.names _n42<1> _n41<1> _n44<1> +.def 0 +0 1 1 +1 0 1 +.names _n44<0> _n44<1> _n45 +.def 1 +0 0 0 +.names _n45 _n43 +0 1 +1 0 +.mv _n46 2 ON OFF +.names _n46 +ON +.names _n40 _n46 _n43 buttons$raw_n3f<*0*> +- - 0 =_n46 +- - 1 =_n40 +.names _n47<0> +1 +.names _n47<1> +0 +.names _n47<0> _n41<0> _n49<0> +.def 0 +0 1 1 +1 0 1 +.names _n47<1> _n41<1> _n49<1> +.def 0 +0 1 1 +1 0 1 +.names _n49<0> _n49<1> _n4a +.def 1 +0 0 0 +.names _n4a _n48 +0 1 +1 0 +.mv _n4b 2 ON OFF +.names _n4b +ON +.names _n40 _n4b _n48 buttons$raw_n3f<*1*> +- - 0 =_n4b +- - 1 =_n40 +.names _n4c<0> +0 +.names _n4c<1> +1 +.names _n4c<0> _n41<0> _n4e<0> +.def 0 +0 1 1 +1 0 1 +.names _n4c<1> _n41<1> _n4e<1> +.def 0 +0 1 1 +1 0 1 +.names _n4e<0> _n4e<1> _n4f +.def 1 +0 0 0 +.names _n4f _n4d +0 1 +1 0 +.mv _n50 2 ON OFF +.names _n50 +ON +.names _n40 _n50 _n4d buttons$raw_n3f<*2*> +- - 0 =_n50 +- - 1 =_n40 +.names _n40 +OFF +# non-blocking assignments for initial +# assign random_push = $NDset ( 0,1,2,3,4,5,6,7 ) +.names -> random_push<0> random_push<1> random_push<2> +0 0 0 +1 0 0 +0 1 0 +1 1 0 +0 0 1 +1 0 1 +0 1 1 +1 1 1 +# assign button_below = ((location == 2) && (buttons [1] == ON || buttons [0] == ON )) || ((location == 1) && buttons [0] == ON ) +.names _n55<0> +0 +.names _n55<1> +1 +# location == 2 +.names location<0> _n55<0> _n56<0> +.def 0 +0 1 1 +1 0 1 +.names location<1> _n55<1> _n56<1> +.def 0 +0 1 1 +1 0 1 +.names _n56<0> _n56<1> _n57 +.def 1 +0 0 0 +.names _n57 _n54 +0 1 +1 0 +.names _n59<0> +1 +.names _n59<1> +0 +.mv _n5a 2 ON OFF +.names buttons<*0*> buttons<*1*> buttons<*2*> _n59<1> _n59<0> _n5a +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.mv _n5b 2 ON OFF +.names _n5b +ON +# buttons [1] == 0 +.names _n5a _n5b _n58 +.def 0 +- =_n5a 1 +.names _n5d<0> +0 +.names _n5d<1> +0 +.mv _n5e 2 ON OFF +.names buttons<*0*> buttons<*1*> buttons<*2*> _n5d<1> _n5d<0> _n5e +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.mv _n5f 2 ON OFF +.names _n5f +ON +# buttons [0] == 0 +.names _n5e _n5f _n5c +.def 0 +- =_n5e 1 +# buttons [1] == 0 || buttons [0] == 0 +.names _n58 _n5c _n60 +.def 1 +0 0 0 +# (location == 2) && (buttons [1] == 0 || buttons [0] == 0) +.names _n54 _n60 _n61 +.def 0 +1 1 1 +.names _n63<0> +1 +.names _n63<1> +0 +# location == 1 +.names location<0> _n63<0> _n64<0> +.def 0 +0 1 1 +1 0 1 +.names location<1> _n63<1> _n64<1> +.def 0 +0 1 1 +1 0 1 +.names _n64<0> _n64<1> _n65 +.def 1 +0 0 0 +.names _n65 _n62 +0 1 +1 0 +.names _n67<0> +0 +.names _n67<1> +0 +.mv _n68 2 ON OFF +.names buttons<*0*> buttons<*1*> buttons<*2*> _n67<1> _n67<0> _n68 +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.mv _n69 2 ON OFF +.names _n69 +ON +# buttons [0] == 0 +.names _n68 _n69 _n66 +.def 0 +- =_n68 1 +# (location == 1) && buttons [0] == 0 +.names _n62 _n66 _n6a +.def 0 +1 1 1 +# ((location == 2) && (buttons [1] == 0 || buttons [0] == 0)) || ((location == 1) && buttons [0] == 0) +.names _n61 _n6a _n6b +.def 1 +0 0 0 +.names _n6b button_below$raw_n53 +- =_n6b +# assign button_above = ((location == 0) && (buttons [2] == ON || buttons [1] == ON )) || ((location == 1) && (buttons [2] == ON )) +.names _n6e<0> +0 +.names _n6e<1> +0 +# location == 0 +.names location<0> _n6e<0> _n6f<0> +.def 0 +0 1 1 +1 0 1 +.names location<1> _n6e<1> _n6f<1> +.def 0 +0 1 1 +1 0 1 +.names _n6f<0> _n6f<1> _n70 +.def 1 +0 0 0 +.names _n70 _n6d +0 1 +1 0 +.names _n72<0> +0 +.names _n72<1> +1 +.mv _n73 2 ON OFF +.names buttons<*0*> buttons<*1*> buttons<*2*> _n72<1> _n72<0> _n73 +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.mv _n74 2 ON OFF +.names _n74 +ON +# buttons [2] == 0 +.names _n73 _n74 _n71 +.def 0 +- =_n73 1 +.names _n76<0> +1 +.names _n76<1> +0 +.mv _n77 2 ON OFF +.names buttons<*0*> buttons<*1*> buttons<*2*> _n76<1> _n76<0> _n77 +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.mv _n78 2 ON OFF +.names _n78 +ON +# buttons [1] == 0 +.names _n77 _n78 _n75 +.def 0 +- =_n77 1 +# buttons [2] == 0 || buttons [1] == 0 +.names _n71 _n75 _n79 +.def 1 +0 0 0 +# (location == 0) && (buttons [2] == 0 || buttons [1] == 0) +.names _n6d _n79 _n7a +.def 0 +1 1 1 +.names _n7c<0> +1 +.names _n7c<1> +0 +# location == 1 +.names location<0> _n7c<0> _n7d<0> +.def 0 +0 1 1 +1 0 1 +.names location<1> _n7c<1> _n7d<1> +.def 0 +0 1 1 +1 0 1 +.names _n7d<0> _n7d<1> _n7e +.def 1 +0 0 0 +.names _n7e _n7b +0 1 +1 0 +.names _n80<0> +0 +.names _n80<1> +1 +.mv _n81 2 ON OFF +.names buttons<*0*> buttons<*1*> buttons<*2*> _n80<1> _n80<0> _n81 +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.mv _n82 2 ON OFF +.names _n82 +ON +# buttons [2] == 0 +.names _n81 _n82 _n7f +.def 0 +- =_n81 1 +# (location == 1) && (buttons [2] == 0) +.names _n7b _n7f _n83 +.def 0 +1 1 1 +# ((location == 0) && (buttons [2] == 0 || buttons [1] == 0)) || ((location == 1) && (buttons [2] == 0)) +.names _n7a _n83 _n84 +.def 1 +0 0 0 +.names _n84 button_above$raw_n6c +- =_n84 +.names _n86<0> +0 +.names _n86<1> +0 +# 0 == location +.names _n86<0> location<0> _n87<0> +.def 0 +0 1 1 +1 0 1 +.names _n86<1> location<1> _n87<1> +.def 0 +0 1 1 +1 0 1 +.names _n87<0> _n87<1> _n88 +.def 1 +0 0 0 +.names _n88 _n85 +0 1 +1 0 +.names _n85 _n89 +- =_n85 +# buttons [0] = 1 +.mv buttons$_n85_n8a$true<*0*> 2 ON OFF +.mv buttons$_n85_n8a$true<*1*> 2 ON OFF +.mv buttons$_n85_n8a$true<*2*> 2 ON OFF +.mv _n8b 2 ON OFF +.names _n8c<0> +0 +.names _n8c<1> +0 +.names _n8d<0> +0 +.names _n8d<1> +0 +.names _n8d<0> _n8c<0> _n8f<0> +.def 0 +0 1 1 +1 0 1 +.names _n8d<1> _n8c<1> _n8f<1> +.def 0 +0 1 1 +1 0 1 +.names _n8f<0> _n8f<1> _n90 +.def 1 +0 0 0 +.names _n90 _n8e +0 1 +1 0 +.names _n8b buttons<*0*> _n8e buttons$_n85_n8a$true<*0*> +- - 0 =buttons<*0*> +- - 1 =_n8b +.names _n91<0> +1 +.names _n91<1> +0 +.names _n91<0> _n8c<0> _n93<0> +.def 0 +0 1 1 +1 0 1 +.names _n91<1> _n8c<1> _n93<1> +.def 0 +0 1 1 +1 0 1 +.names _n93<0> _n93<1> _n94 +.def 1 +0 0 0 +.names _n94 _n92 +0 1 +1 0 +.names _n8b buttons<*1*> _n92 buttons$_n85_n8a$true<*1*> +- - 0 =buttons<*1*> +- - 1 =_n8b +.names _n95<0> +0 +.names _n95<1> +1 +.names _n95<0> _n8c<0> _n97<0> +.def 0 +0 1 1 +1 0 1 +.names _n95<1> _n8c<1> _n97<1> +.def 0 +0 1 1 +1 0 1 +.names _n97<0> _n97<1> _n98 +.def 1 +0 0 0 +.names _n98 _n96 +0 1 +1 0 +.names _n8b buttons<*2*> _n96 buttons$_n85_n8a$true<*2*> +- - 0 =buttons<*2*> +- - 1 =_n8b +.names _n8b +OFF +.names random_push<0> _n9a +.def 1 +0 0 +.names _n9a _n99 +- =_n9a +# buttons [0] = 0 +.mv buttons$random_push_n9b$true<*0*> 2 ON OFF +.mv buttons$random_push_n9b$true<*1*> 2 ON OFF +.mv buttons$random_push_n9b$true<*2*> 2 ON OFF +.mv _n9c 2 ON OFF +.names _n9d<0> +0 +.names _n9d<1> +0 +.names _n9e<0> +0 +.names _n9e<1> +0 +.names _n9e<0> _n9d<0> _na0<0> +.def 0 +0 1 1 +1 0 1 +.names _n9e<1> _n9d<1> _na0<1> +.def 0 +0 1 1 +1 0 1 +.names _na0<0> _na0<1> _na1 +.def 1 +0 0 0 +.names _na1 _n9f +0 1 +1 0 +.names _n9c buttons<*0*> _n9f buttons$random_push_n9b$true<*0*> +- - 0 =buttons<*0*> +- - 1 =_n9c +.names _na2<0> +1 +.names _na2<1> +0 +.names _na2<0> _n9d<0> _na4<0> +.def 0 +0 1 1 +1 0 1 +.names _na2<1> _n9d<1> _na4<1> +.def 0 +0 1 1 +1 0 1 +.names _na4<0> _na4<1> _na5 +.def 1 +0 0 0 +.names _na5 _na3 +0 1 +1 0 +.names _n9c buttons<*1*> _na3 buttons$random_push_n9b$true<*1*> +- - 0 =buttons<*1*> +- - 1 =_n9c +.names _na6<0> +0 +.names _na6<1> +1 +.names _na6<0> _n9d<0> _na8<0> +.def 0 +0 1 1 +1 0 1 +.names _na6<1> _n9d<1> _na8<1> +.def 0 +0 1 1 +1 0 1 +.names _na8<0> _na8<1> _na9 +.def 1 +0 0 0 +.names _na9 _na7 +0 1 +1 0 +.names _n9c buttons<*2*> _na7 buttons$random_push_n9b$true<*2*> +- - 0 =buttons<*2*> +- - 1 =_n9c +.names _n9c +ON +# if/else (random_push [0]) +.mv buttons$random_push$raw_nac<*0*> 2 ON OFF +.mv buttons$random_push$raw_nac<*1*> 2 ON OFF +.mv buttons$random_push$raw_nac<*2*> 2 ON OFF +.names random_push<0> _nad +.def 1 +0 0 +.names buttons$random_push_n9b$true<*0*> buttons<*0*> _nad buttons$random_push$raw_nac<*0*> +- - 0 =buttons<*0*> +- - 1 =buttons$random_push_n9b$true<*0*> +.names buttons$random_push_n9b$true<*1*> buttons<*1*> _nad buttons$random_push$raw_nac<*1*> +- - 0 =buttons<*1*> +- - 1 =buttons$random_push_n9b$true<*1*> +.names buttons$random_push_n9b$true<*2*> buttons<*2*> _nad buttons$random_push$raw_nac<*2*> +- - 0 =buttons<*2*> +- - 1 =buttons$random_push_n9b$true<*2*> +# if/else (0 == location ) +.mv buttons$_n85$raw_naf<*0*> 2 ON OFF +.mv buttons$_n85$raw_naf<*1*> 2 ON OFF +.mv buttons$_n85$raw_naf<*2*> 2 ON OFF +.names buttons$_n85_n8a$true<*0*> buttons$random_push$raw_nac<*0*> _n85 buttons$_n85$raw_naf<*0*> +- - 0 =buttons$random_push$raw_nac<*0*> +- - 1 =buttons$_n85_n8a$true<*0*> +.names buttons$_n85_n8a$true<*1*> buttons$random_push$raw_nac<*1*> _n85 buttons$_n85$raw_naf<*1*> +- - 0 =buttons$random_push$raw_nac<*1*> +- - 1 =buttons$_n85_n8a$true<*1*> +.names buttons$_n85_n8a$true<*2*> buttons$random_push$raw_nac<*2*> _n85 buttons$_n85$raw_naf<*2*> +- - 0 =buttons$random_push$raw_nac<*2*> +- - 1 =buttons$_n85_n8a$true<*2*> +.names _nb3<0> +1 +.names _nb3<1> +0 +# 1 == location +.names _nb3<0> location<0> _nb4<0> +.def 0 +0 1 1 +1 0 1 +.names _nb3<1> location<1> _nb4<1> +.def 0 +0 1 1 +1 0 1 +.names _nb4<0> _nb4<1> _nb5 +.def 1 +0 0 0 +.names _nb5 _nb2 +0 1 +1 0 +.names _nb2 _nb6 +- =_nb2 +# buttons [1] = 1 +.mv buttons$_nb2_nb7$true<*0*> 2 ON OFF +.mv buttons$_nb2_nb7$true<*1*> 2 ON OFF +.mv buttons$_nb2_nb7$true<*2*> 2 ON OFF +.mv _nb8 2 ON OFF +.names _nb9<0> +1 +.names _nb9<1> +0 +.names _nba<0> +0 +.names _nba<1> +0 +.names _nba<0> _nb9<0> _nbc<0> +.def 0 +0 1 1 +1 0 1 +.names _nba<1> _nb9<1> _nbc<1> +.def 0 +0 1 1 +1 0 1 +.names _nbc<0> _nbc<1> _nbd +.def 1 +0 0 0 +.names _nbd _nbb +0 1 +1 0 +.names _nb8 buttons$_n85$raw_naf<*0*> _nbb buttons$_nb2_nb7$true<*0*> +- - 0 =buttons$_n85$raw_naf<*0*> +- - 1 =_nb8 +.names _nbe<0> +1 +.names _nbe<1> +0 +.names _nbe<0> _nb9<0> _nc0<0> +.def 0 +0 1 1 +1 0 1 +.names _nbe<1> _nb9<1> _nc0<1> +.def 0 +0 1 1 +1 0 1 +.names _nc0<0> _nc0<1> _nc1 +.def 1 +0 0 0 +.names _nc1 _nbf +0 1 +1 0 +.names _nb8 buttons$_n85$raw_naf<*1*> _nbf buttons$_nb2_nb7$true<*1*> +- - 0 =buttons$_n85$raw_naf<*1*> +- - 1 =_nb8 +.names _nc2<0> +0 +.names _nc2<1> +1 +.names _nc2<0> _nb9<0> _nc4<0> +.def 0 +0 1 1 +1 0 1 +.names _nc2<1> _nb9<1> _nc4<1> +.def 0 +0 1 1 +1 0 1 +.names _nc4<0> _nc4<1> _nc5 +.def 1 +0 0 0 +.names _nc5 _nc3 +0 1 +1 0 +.names _nb8 buttons$_n85$raw_naf<*2*> _nc3 buttons$_nb2_nb7$true<*2*> +- - 0 =buttons$_n85$raw_naf<*2*> +- - 1 =_nb8 +.names _nb8 +OFF +.names random_push<1> _nc7 +.def 1 +0 0 +.names _nc7 _nc6 +- =_nc7 +# buttons [1] = 0 +.mv buttons$random_push_nc8$true<*0*> 2 ON OFF +.mv buttons$random_push_nc8$true<*1*> 2 ON OFF +.mv buttons$random_push_nc8$true<*2*> 2 ON OFF +.mv _nc9 2 ON OFF +.names _nca<0> +1 +.names _nca<1> +0 +.names _ncb<0> +0 +.names _ncb<1> +0 +.names _ncb<0> _nca<0> _ncd<0> +.def 0 +0 1 1 +1 0 1 +.names _ncb<1> _nca<1> _ncd<1> +.def 0 +0 1 1 +1 0 1 +.names _ncd<0> _ncd<1> _nce +.def 1 +0 0 0 +.names _nce _ncc +0 1 +1 0 +.names _nc9 buttons$_n85$raw_naf<*0*> _ncc buttons$random_push_nc8$true<*0*> +- - 0 =buttons$_n85$raw_naf<*0*> +- - 1 =_nc9 +.names _ncf<0> +1 +.names _ncf<1> +0 +.names _ncf<0> _nca<0> _nd1<0> +.def 0 +0 1 1 +1 0 1 +.names _ncf<1> _nca<1> _nd1<1> +.def 0 +0 1 1 +1 0 1 +.names _nd1<0> _nd1<1> _nd2 +.def 1 +0 0 0 +.names _nd2 _nd0 +0 1 +1 0 +.names _nc9 buttons$_n85$raw_naf<*1*> _nd0 buttons$random_push_nc8$true<*1*> +- - 0 =buttons$_n85$raw_naf<*1*> +- - 1 =_nc9 +.names _nd3<0> +0 +.names _nd3<1> +1 +.names _nd3<0> _nca<0> _nd5<0> +.def 0 +0 1 1 +1 0 1 +.names _nd3<1> _nca<1> _nd5<1> +.def 0 +0 1 1 +1 0 1 +.names _nd5<0> _nd5<1> _nd6 +.def 1 +0 0 0 +.names _nd6 _nd4 +0 1 +1 0 +.names _nc9 buttons$_n85$raw_naf<*2*> _nd4 buttons$random_push_nc8$true<*2*> +- - 0 =buttons$_n85$raw_naf<*2*> +- - 1 =_nc9 +.names _nc9 +ON +# if/else (random_push [1]) +.mv buttons$random_push$raw_nd7<*0*> 2 ON OFF +.mv buttons$random_push$raw_nd7<*1*> 2 ON OFF +.mv buttons$random_push$raw_nd7<*2*> 2 ON OFF +.names random_push<1> _nd8 +.def 1 +0 0 +.names buttons$random_push_nc8$true<*0*> buttons$_n85$raw_naf<*0*> _nd8 buttons$random_push$raw_nd7<*0*> +- - 0 =buttons$_n85$raw_naf<*0*> +- - 1 =buttons$random_push_nc8$true<*0*> +.names buttons$random_push_nc8$true<*1*> buttons$_n85$raw_naf<*1*> _nd8 buttons$random_push$raw_nd7<*1*> +- - 0 =buttons$_n85$raw_naf<*1*> +- - 1 =buttons$random_push_nc8$true<*1*> +.names buttons$random_push_nc8$true<*2*> buttons$_n85$raw_naf<*2*> _nd8 buttons$random_push$raw_nd7<*2*> +- - 0 =buttons$_n85$raw_naf<*2*> +- - 1 =buttons$random_push_nc8$true<*2*> +# if/else (1 == location ) +.mv buttons$_nb2$raw_ndc<*0*> 2 ON OFF +.mv buttons$_nb2$raw_ndc<*1*> 2 ON OFF +.mv buttons$_nb2$raw_ndc<*2*> 2 ON OFF +.names buttons$_nb2_nb7$true<*0*> buttons$random_push$raw_nd7<*0*> _nb2 buttons$_nb2$raw_ndc<*0*> +- - 0 =buttons$random_push$raw_nd7<*0*> +- - 1 =buttons$_nb2_nb7$true<*0*> +.names buttons$_nb2_nb7$true<*1*> buttons$random_push$raw_nd7<*1*> _nb2 buttons$_nb2$raw_ndc<*1*> +- - 0 =buttons$random_push$raw_nd7<*1*> +- - 1 =buttons$_nb2_nb7$true<*1*> +.names buttons$_nb2_nb7$true<*2*> buttons$random_push$raw_nd7<*2*> _nb2 buttons$_nb2$raw_ndc<*2*> +- - 0 =buttons$random_push$raw_nd7<*2*> +- - 1 =buttons$_nb2_nb7$true<*2*> +.names _ne1<0> +0 +.names _ne1<1> +1 +# 2 == location +.names _ne1<0> location<0> _ne2<0> +.def 0 +0 1 1 +1 0 1 +.names _ne1<1> location<1> _ne2<1> +.def 0 +0 1 1 +1 0 1 +.names _ne2<0> _ne2<1> _ne3 +.def 1 +0 0 0 +.names _ne3 _ne0 +0 1 +1 0 +.names _ne0 _ne4 +- =_ne0 +# buttons [2] = 1 +.mv buttons$_ne0_ne5$true<*0*> 2 ON OFF +.mv buttons$_ne0_ne5$true<*1*> 2 ON OFF +.mv buttons$_ne0_ne5$true<*2*> 2 ON OFF +.mv _ne6 2 ON OFF +.names _ne7<0> +0 +.names _ne7<1> +1 +.names _ne8<0> +0 +.names _ne8<1> +0 +.names _ne8<0> _ne7<0> _nea<0> +.def 0 +0 1 1 +1 0 1 +.names _ne8<1> _ne7<1> _nea<1> +.def 0 +0 1 1 +1 0 1 +.names _nea<0> _nea<1> _neb +.def 1 +0 0 0 +.names _neb _ne9 +0 1 +1 0 +.names _ne6 buttons$_nb2$raw_ndc<*0*> _ne9 buttons$_ne0_ne5$true<*0*> +- - 0 =buttons$_nb2$raw_ndc<*0*> +- - 1 =_ne6 +.names _nec<0> +1 +.names _nec<1> +0 +.names _nec<0> _ne7<0> _nee<0> +.def 0 +0 1 1 +1 0 1 +.names _nec<1> _ne7<1> _nee<1> +.def 0 +0 1 1 +1 0 1 +.names _nee<0> _nee<1> _nef +.def 1 +0 0 0 +.names _nef _ned +0 1 +1 0 +.names _ne6 buttons$_nb2$raw_ndc<*1*> _ned buttons$_ne0_ne5$true<*1*> +- - 0 =buttons$_nb2$raw_ndc<*1*> +- - 1 =_ne6 +.names _nf0<0> +0 +.names _nf0<1> +1 +.names _nf0<0> _ne7<0> _nf2<0> +.def 0 +0 1 1 +1 0 1 +.names _nf0<1> _ne7<1> _nf2<1> +.def 0 +0 1 1 +1 0 1 +.names _nf2<0> _nf2<1> _nf3 +.def 1 +0 0 0 +.names _nf3 _nf1 +0 1 +1 0 +.names _ne6 buttons$_nb2$raw_ndc<*2*> _nf1 buttons$_ne0_ne5$true<*2*> +- - 0 =buttons$_nb2$raw_ndc<*2*> +- - 1 =_ne6 +.names _ne6 +OFF +.names random_push<2> _nf5 +.def 1 +0 0 +.names _nf5 _nf4 +- =_nf5 +# buttons [2] = 0 +.mv buttons$random_push_nf6$true<*0*> 2 ON OFF +.mv buttons$random_push_nf6$true<*1*> 2 ON OFF +.mv buttons$random_push_nf6$true<*2*> 2 ON OFF +.mv _nf7 2 ON OFF +.names _nf8<0> +0 +.names _nf8<1> +1 +.names _nf9<0> +0 +.names _nf9<1> +0 +.names _nf9<0> _nf8<0> _nfb<0> +.def 0 +0 1 1 +1 0 1 +.names _nf9<1> _nf8<1> _nfb<1> +.def 0 +0 1 1 +1 0 1 +.names _nfb<0> _nfb<1> _nfc +.def 1 +0 0 0 +.names _nfc _nfa +0 1 +1 0 +.names _nf7 buttons$_nb2$raw_ndc<*0*> _nfa buttons$random_push_nf6$true<*0*> +- - 0 =buttons$_nb2$raw_ndc<*0*> +- - 1 =_nf7 +.names _nfd<0> +1 +.names _nfd<1> +0 +.names _nfd<0> _nf8<0> _nff<0> +.def 0 +0 1 1 +1 0 1 +.names _nfd<1> _nf8<1> _nff<1> +.def 0 +0 1 1 +1 0 1 +.names _nff<0> _nff<1> _n100 +.def 1 +0 0 0 +.names _n100 _nfe +0 1 +1 0 +.names _nf7 buttons$_nb2$raw_ndc<*1*> _nfe buttons$random_push_nf6$true<*1*> +- - 0 =buttons$_nb2$raw_ndc<*1*> +- - 1 =_nf7 +.names _n101<0> +0 +.names _n101<1> +1 +.names _n101<0> _nf8<0> _n103<0> +.def 0 +0 1 1 +1 0 1 +.names _n101<1> _nf8<1> _n103<1> +.def 0 +0 1 1 +1 0 1 +.names _n103<0> _n103<1> _n104 +.def 1 +0 0 0 +.names _n104 _n102 +0 1 +1 0 +.names _nf7 buttons$_nb2$raw_ndc<*2*> _n102 buttons$random_push_nf6$true<*2*> +- - 0 =buttons$_nb2$raw_ndc<*2*> +- - 1 =_nf7 +.names _nf7 +ON +# if/else (random_push [2]) +.mv buttons$random_push$raw_n105<*0*> 2 ON OFF +.mv buttons$random_push$raw_n105<*1*> 2 ON OFF +.mv buttons$random_push$raw_n105<*2*> 2 ON OFF +.names random_push<2> _n106 +.def 1 +0 0 +.names buttons$random_push_nf6$true<*0*> buttons$_nb2$raw_ndc<*0*> _n106 buttons$random_push$raw_n105<*0*> +- - 0 =buttons$_nb2$raw_ndc<*0*> +- - 1 =buttons$random_push_nf6$true<*0*> +.names buttons$random_push_nf6$true<*1*> buttons$_nb2$raw_ndc<*1*> _n106 buttons$random_push$raw_n105<*1*> +- - 0 =buttons$_nb2$raw_ndc<*1*> +- - 1 =buttons$random_push_nf6$true<*1*> +.names buttons$random_push_nf6$true<*2*> buttons$_nb2$raw_ndc<*2*> _n106 buttons$random_push$raw_n105<*2*> +- - 0 =buttons$_nb2$raw_ndc<*2*> +- - 1 =buttons$random_push_nf6$true<*2*> +# if/else (2 == location ) +.mv buttons$_ne0$raw_n10a<*0*> 2 ON OFF +.mv buttons$_ne0$raw_n10a<*1*> 2 ON OFF +.mv buttons$_ne0$raw_n10a<*2*> 2 ON OFF +.names buttons$_ne0_ne5$true<*0*> buttons$random_push$raw_n105<*0*> _ne0 buttons$_ne0$raw_n10a<*0*> +- - 0 =buttons$random_push$raw_n105<*0*> +- - 1 =buttons$_ne0_ne5$true<*0*> +.names buttons$_ne0_ne5$true<*1*> buttons$random_push$raw_n105<*1*> _ne0 buttons$_ne0$raw_n10a<*1*> +- - 0 =buttons$random_push$raw_n105<*1*> +- - 1 =buttons$_ne0_ne5$true<*1*> +.names buttons$_ne0_ne5$true<*2*> buttons$random_push$raw_n105<*2*> _ne0 buttons$_ne0$raw_n10a<*2*> +- - 0 =buttons$random_push$raw_n105<*2*> +- - 1 =buttons$_ne0_ne5$true<*2*> +.names stop_next _n10e +- =stop_next +.mv _n110 2 UP DOWN +.names _n110 +UP +# direction == 0 +.names direction _n110 _n10f +.def 0 +- =direction 1 +.names _n10f _n111 +- =_n10f +# buttons [location + 1] = 0 +.mv buttons$_n10f_n112$true<*0*> 2 ON OFF +.mv buttons$_n10f_n112$true<*1*> 2 ON OFF +.mv buttons$_n10f_n112$true<*2*> 2 ON OFF +.names _n113<0> +1 +.names _n113<1> +0 +# location + 1 +.names _n115 +0 +.names location<0> _n113<0> _n115 _n114<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n117 +0 +.names location<0> _n113<0> _n117 _n116 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names location<1> _n113<1> _n116 _n114<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n118 2 ON OFF +.names _n119<0> +0 +.names _n119<1> +0 +.names _n119<0> _n114<0> _n11b<0> +.def 0 +0 1 1 +1 0 1 +.names _n119<1> _n114<1> _n11b<1> +.def 0 +0 1 1 +1 0 1 +.names _n11b<0> _n11b<1> _n11c +.def 1 +0 0 0 +.names _n11c _n11a +0 1 +1 0 +.names _n118 buttons$_ne0$raw_n10a<*0*> _n11a buttons$_n10f_n112$true<*0*> +- - 0 =buttons$_ne0$raw_n10a<*0*> +- - 1 =_n118 +.names _n11d<0> +1 +.names _n11d<1> +0 +.names _n11d<0> _n114<0> _n11f<0> +.def 0 +0 1 1 +1 0 1 +.names _n11d<1> _n114<1> _n11f<1> +.def 0 +0 1 1 +1 0 1 +.names _n11f<0> _n11f<1> _n120 +.def 1 +0 0 0 +.names _n120 _n11e +0 1 +1 0 +.names _n118 buttons$_ne0$raw_n10a<*1*> _n11e buttons$_n10f_n112$true<*1*> +- - 0 =buttons$_ne0$raw_n10a<*1*> +- - 1 =_n118 +.names _n121<0> +0 +.names _n121<1> +1 +.names _n121<0> _n114<0> _n123<0> +.def 0 +0 1 1 +1 0 1 +.names _n121<1> _n114<1> _n123<1> +.def 0 +0 1 1 +1 0 1 +.names _n123<0> _n123<1> _n124 +.def 1 +0 0 0 +.names _n124 _n122 +0 1 +1 0 +.names _n118 buttons$_ne0$raw_n10a<*2*> _n122 buttons$_n10f_n112$true<*2*> +- - 0 =buttons$_ne0$raw_n10a<*2*> +- - 1 =_n118 +.names _n118 +ON +# buttons [location - 1] = 0 +.mv buttons$_n10f_n125$false<*0*> 2 ON OFF +.mv buttons$_n10f_n125$false<*1*> 2 ON OFF +.mv buttons$_n10f_n125$false<*2*> 2 ON OFF +.names _n126<0> +1 +.names _n126<1> +0 +# location - 1 +.names _n128 +0 +.names location<0> _n126<0> _n128 _n127<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n12a +0 +.names location<0> _n126<0> _n12a _n129 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names location<1> _n126<1> _n129 _n127<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n12b 2 ON OFF +.names _n12c<0> +0 +.names _n12c<1> +0 +.names _n12c<0> _n127<0> _n12e<0> +.def 0 +0 1 1 +1 0 1 +.names _n12c<1> _n127<1> _n12e<1> +.def 0 +0 1 1 +1 0 1 +.names _n12e<0> _n12e<1> _n12f +.def 1 +0 0 0 +.names _n12f _n12d +0 1 +1 0 +.names _n12b buttons$_ne0$raw_n10a<*0*> _n12d buttons$_n10f_n125$false<*0*> +- - 0 =buttons$_ne0$raw_n10a<*0*> +- - 1 =_n12b +.names _n130<0> +1 +.names _n130<1> +0 +.names _n130<0> _n127<0> _n132<0> +.def 0 +0 1 1 +1 0 1 +.names _n130<1> _n127<1> _n132<1> +.def 0 +0 1 1 +1 0 1 +.names _n132<0> _n132<1> _n133 +.def 1 +0 0 0 +.names _n133 _n131 +0 1 +1 0 +.names _n12b buttons$_ne0$raw_n10a<*1*> _n131 buttons$_n10f_n125$false<*1*> +- - 0 =buttons$_ne0$raw_n10a<*1*> +- - 1 =_n12b +.names _n134<0> +0 +.names _n134<1> +1 +.names _n134<0> _n127<0> _n136<0> +.def 0 +0 1 1 +1 0 1 +.names _n134<1> _n127<1> _n136<1> +.def 0 +0 1 1 +1 0 1 +.names _n136<0> _n136<1> _n137 +.def 1 +0 0 0 +.names _n137 _n135 +0 1 +1 0 +.names _n12b buttons$_ne0$raw_n10a<*2*> _n135 buttons$_n10f_n125$false<*2*> +- - 0 =buttons$_ne0$raw_n10a<*2*> +- - 1 =_n12b +.names _n12b +ON +# if/else (direction == 0) +.mv buttons$_n10f$raw_n138<*0*> 2 ON OFF +.mv buttons$_n10f$raw_n138<*1*> 2 ON OFF +.mv buttons$_n10f$raw_n138<*2*> 2 ON OFF +.names buttons$_n10f_n112$true<*0*> buttons$_n10f_n125$false<*0*> _n10f buttons$_n10f$raw_n138<*0*> +- - 0 =buttons$_n10f_n125$false<*0*> +- - 1 =buttons$_n10f_n112$true<*0*> +.names buttons$_n10f_n112$true<*1*> buttons$_n10f_n125$false<*1*> _n10f buttons$_n10f$raw_n138<*1*> +- - 0 =buttons$_n10f_n125$false<*1*> +- - 1 =buttons$_n10f_n112$true<*1*> +.names buttons$_n10f_n112$true<*2*> buttons$_n10f_n125$false<*2*> _n10f buttons$_n10f$raw_n138<*2*> +- - 0 =buttons$_n10f_n125$false<*2*> +- - 1 =buttons$_n10f_n112$true<*2*> +# if/else (stop_next ) +.mv buttons$stop_next$raw_n13c<*0*> 2 ON OFF +.mv buttons$stop_next$raw_n13c<*1*> 2 ON OFF +.mv buttons$stop_next$raw_n13c<*2*> 2 ON OFF +.names buttons$_n10f$raw_n138<*0*> buttons$_ne0$raw_n10a<*0*> stop_next buttons$stop_next$raw_n13c<*0*> +- - 0 =buttons$_ne0$raw_n10a<*0*> +- - 1 =buttons$_n10f$raw_n138<*0*> +.names buttons$_n10f$raw_n138<*1*> buttons$_ne0$raw_n10a<*1*> stop_next buttons$stop_next$raw_n13c<*1*> +- - 0 =buttons$_ne0$raw_n10a<*1*> +- - 1 =buttons$_n10f$raw_n138<*1*> +.names buttons$_n10f$raw_n138<*2*> buttons$_ne0$raw_n10a<*2*> stop_next buttons$stop_next$raw_n13c<*2*> +- - 0 =buttons$_ne0$raw_n10a<*2*> +- - 1 =buttons$_n10f$raw_n138<*2*> +.mv _n141 4 OPEN OPENING CLOSED CLOSING +.names _n141 +CLOSED +# door != 2 +.names door _n141 _n140 +.def 1 +- =door 0 +.names _n140 _n142 +- =_n140 +# open_next = 0 +.names open_next$_n140_n143$true +0 +.mv _n145 2 STOPPED MOVING +.names _n145 +MOVING +# movement == 1 +.names movement _n145 _n144 +.def 0 +- =movement 1 +.mv _n147 2 UP DOWN +.names _n147 +UP +# direction == 0 +.names direction _n147 _n146 +.def 0 +- =direction 1 +.names _n149<0> +1 +.names _n149<1> +0 +# location + 1 +.names _n14b +0 +.names location<0> _n149<0> _n14b _n14a<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n14d +0 +.names location<0> _n149<0> _n14d _n14c +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names location<1> _n149<1> _n14c _n14a<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n14e 2 ON OFF +.names buttons<*0*> buttons<*1*> buttons<*2*> _n14a<1> _n14a<0> _n14e +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.mv _n14f 2 ON OFF +.names _n14f +ON +# buttons [location + 1] == 0 +.names _n14e _n14f _n148 +.def 0 +- =_n14e 1 +# direction == 0 && buttons [location + 1] == 0 +.names _n146 _n148 _n150 +.def 0 +1 1 1 +# stop_next || (direction == 0 && buttons [location + 1] == 0) +.names stop_next _n150 _n151 +.def 1 +0 0 0 +.mv _n153 2 UP DOWN +.names _n153 +DOWN +# direction == 1 +.names direction _n153 _n152 +.def 0 +- =direction 1 +.names _n155<0> +1 +.names _n155<1> +0 +# location - 1 +.names _n157 +0 +.names location<0> _n155<0> _n157 _n156<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n159 +0 +.names location<0> _n155<0> _n159 _n158 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names location<1> _n155<1> _n158 _n156<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n15a 2 ON OFF +.names buttons<*0*> buttons<*1*> buttons<*2*> _n156<1> _n156<0> _n15a +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.mv _n15b 2 ON OFF +.names _n15b +ON +# buttons [location - 1] == 0 +.names _n15a _n15b _n154 +.def 0 +- =_n15a 1 +# direction == 1 && buttons [location - 1] == 0 +.names _n152 _n154 _n15c +.def 0 +1 1 1 +# stop_next || (direction == 0 && buttons [location + 1] == 0) || (direction == 1 && buttons [location - 1] == 0) +.names _n151 _n15c _n15d +.def 1 +0 0 0 +# movement == 1 && (stop_next || (direction == 0 && buttons [location + 1] == 0) || (direction == 1 && buttons [location - 1] == 0)) +.names _n144 _n15d _n15e +.def 0 +1 1 1 +.names _n15e _n15f +- =_n15e +# open_next = 1 +.names open_next$_n15e_n160$true +1 +# if/else (movement == 1 && (stop_next || (direction == 0 && buttons [location + 1] == 0) || (direction == 1 && buttons [location - 1] == 0))) +.names open_next$_n15e_n160$true open_next _n15e open_next$_n15e$raw_n163 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (door != 2) +.names open_next$_n140_n143$true open_next$_n15e$raw_n163 _n140 open_next$_n140$raw_n166 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# assign random = $NDset ( 0,1 ) +.names random +0 +1 +.mv _n16e 4 OPEN OPENING CLOSED CLOSING +.names _n16e +CLOSED +.names door _n16e _n16d +.def 0 +- =door 1 +.names _n16d _n16c +1 1 +0 0 +.mv _n170 2 STOPPED MOVING +.names _n170 +STOPPED +# movement == 0 +.names movement _n170 _n16f +.def 0 +- =movement 1 +# open_next && movement == 0 +.names open_next _n16f _n171 +.def 0 +1 1 1 +.names _n171 _n172 +- =_n171 +# door = 1 +.mv door$_n171_n173$true 4 OPEN OPENING CLOSED CLOSING +.names door$_n171_n173$true +OPENING +# if/else (open_next && movement == 0) +.mv door$_n171$raw_n176 4 OPEN OPENING CLOSED CLOSING +.names door$_n171_n173$true door _n171 door$_n171$raw_n176 +- - 0 =door +- - 1 =door$_n171_n173$true +.mv _n179 4 OPEN OPENING CLOSED CLOSING +.names _n179 +OPENING +.names door _n179 _n178 +.def 0 +- =door 1 +.names _n178 _n177 +1 1 +0 0 +.names random _n17a +- =random +# door = 0 +.mv door$random_n17b$true 4 OPEN OPENING CLOSED CLOSING +.names door$random_n17b$true +OPEN +# if/else (random ) +.mv door$random$raw_n17e 4 OPEN OPENING CLOSED CLOSING +.names door$random_n17b$true door random door$random$raw_n17e +- - 0 =door +- - 1 =door$random_n17b$true +.mv _n181 4 OPEN OPENING CLOSED CLOSING +.names _n181 +OPEN +.names door _n181 _n180 +.def 0 +- =door 1 +.names _n180 _n17f +1 1 +0 0 +.names random _n182 +- =random +# door = 3 +.mv door$random_n183$true 4 OPEN OPENING CLOSED CLOSING +.names door$random_n183$true +CLOSING +# if/else (random ) +.mv door$random$raw_n186 4 OPEN OPENING CLOSED CLOSING +.names door$random_n183$true door random door$random$raw_n186 +- - 0 =door +- - 1 =door$random_n183$true +.mv _n189 4 OPEN OPENING CLOSED CLOSING +.names _n189 +CLOSING +.names door _n189 _n188 +.def 0 +- =door 1 +.names _n188 _n187 +1 1 +0 0 +.names random _n18a +- =random +# door = 2 +.mv door$random_n18b$true 4 OPEN OPENING CLOSED CLOSING +.names door$random_n18b$true +CLOSED +# if/else (random ) +.mv door$random$raw_n18e 4 OPEN OPENING CLOSED CLOSING +.names door$random_n18b$true door random door$random$raw_n18e +- - 0 =door +- - 1 =door$random_n18b$true +# case (door ) +.mv door$_n187$raw_n191 4 OPEN OPENING CLOSED CLOSING +.names door$random$raw_n18e door _n187 door$_n187$raw_n191 +- - 0 =door +- - 1 =door$random$raw_n18e +.mv door$_n17f$raw_n192 4 OPEN OPENING CLOSED CLOSING +.names door$random$raw_n186 door$_n187$raw_n191 _n17f door$_n17f$raw_n192 +- - 0 =door$_n187$raw_n191 +- - 1 =door$random$raw_n186 +.mv door$_n177$raw_n196 4 OPEN OPENING CLOSED CLOSING +.names door$random$raw_n17e door$_n17f$raw_n192 _n177 door$_n177$raw_n196 +- - 0 =door$_n17f$raw_n192 +- - 1 =door$random$raw_n17e +.mv door$_n16c$raw_n19a 4 OPEN OPENING CLOSED CLOSING +.names door$_n171$raw_n176 door$_n177$raw_n196 _n16c door$_n16c$raw_n19a +- - 0 =door$_n177$raw_n196 +- - 1 =door$_n171$raw_n176 +# assign start_moving = (continue || button_above && direction == UP ) || (button_below && direction == DOWN ) +.mv _n1a0 2 UP DOWN +.names _n1a0 +UP +# direction == 0 +.names direction _n1a0 _n19f +.def 0 +- =direction 1 +# button_above && direction == 0 +.names button_above _n19f _n1a1 +.def 0 +1 1 1 +# continue || button_above && direction == 0 +.names continue _n1a1 _n1a2 +.def 1 +0 0 0 +.mv _n1a4 2 UP DOWN +.names _n1a4 +DOWN +# direction == 1 +.names direction _n1a4 _n1a3 +.def 0 +- =direction 1 +# button_below && direction == 1 +.names button_below _n1a3 _n1a5 +.def 0 +1 1 1 +# (continue || button_above && direction == 0) || (button_below && direction == 1) +.names _n1a2 _n1a5 _n1a6 +.def 1 +0 0 0 +.names _n1a6 start_moving$raw_n19e +- =_n1a6 +# assign r_stop = $NDset ( 0,1 ) +.names r_stop +0 +1 +# assign stop_moving = r_stop && (movement == MOVING ) +.mv _n1ab 2 STOPPED MOVING +.names _n1ab +MOVING +# movement == 1 +.names movement _n1ab _n1aa +.def 0 +- =movement 1 +# r_stop && (movement == 1) +.names r_stop _n1aa _n1ac +.def 0 +1 1 1 +.names _n1ac stop_moving$raw_n1a9 +- =_n1ac +# assign inc = (stop_moving ) && (direction == UP ) +.mv _n1af 2 UP DOWN +.names _n1af +UP +# direction == 0 +.names direction _n1af _n1ae +.def 0 +- =direction 1 +# (stop_moving ) && (direction == 0) +.names stop_moving _n1ae _n1b0 +.def 0 +1 1 1 +.names _n1b0 inc$raw_n1ad +- =_n1b0 +# assign dec = (stop_moving ) && (direction == DOWN ) +.mv _n1b3 2 UP DOWN +.names _n1b3 +DOWN +# direction == 1 +.names direction _n1b3 _n1b2 +.def 0 +- =direction 1 +# (stop_moving ) && (direction == 1) +.names stop_moving _n1b2 _n1b4 +.def 0 +1 1 1 +.names _n1b4 dec$raw_n1b1 +- =_n1b4 +.mv _n1b6 4 OPEN OPENING CLOSED CLOSING +.names _n1b6 +CLOSED +# door == 2 +.names door _n1b6 _n1b5 +.def 0 +- =door 1 +.names _n1b5 _n1b7 +- =_n1b5 +.mv _n1ba 2 STOPPED MOVING +.names _n1ba +STOPPED +.names movement _n1ba _n1b9 +.def 0 +- =movement 1 +.names _n1b9 _n1b8 +1 1 +0 0 +.mv _n1bc 4 OPEN OPENING CLOSED CLOSING +.names _n1bc +CLOSED +# door == 2 +.names door _n1bc _n1bb +.def 0 +- =door 1 +# door == 2 && start_moving +.names _n1bb start_moving _n1bd +.def 0 +1 1 1 +.names open_next _n1be +0 1 +1 0 +# door == 2 && start_moving && !open_next +.names _n1bd _n1be _n1bf +.def 0 +1 1 1 +.names _n1bf _n1c0 +- =_n1bf +# movement = 1 +.mv movement$_n1bf_n1c1$true 2 STOPPED MOVING +.names movement$_n1bf_n1c1$true +MOVING +# if/else (door == 2 && start_moving && !open_next ) +.mv movement$_n1bf$raw_n1c4 2 STOPPED MOVING +.names movement$_n1bf_n1c1$true movement _n1bf movement$_n1bf$raw_n1c4 +- - 0 =movement +- - 1 =movement$_n1bf_n1c1$true +.mv _n1c7 2 STOPPED MOVING +.names _n1c7 +MOVING +.names movement _n1c7 _n1c6 +.def 0 +- =movement 1 +.names _n1c6 _n1c5 +1 1 +0 0 +.names stop_moving _n1c8 +- =stop_moving +# movement = 0 +.mv movement$stop_moving_n1c9$true 2 STOPPED MOVING +.names movement$stop_moving_n1c9$true +STOPPED +.mv _n1cb 2 UP DOWN +.names _n1cb +UP +# direction == 0 +.names direction _n1cb _n1ca +.def 0 +- =direction 1 +.names _n1ca _n1cc +- =_n1ca +# location = location + 1 +.names _n1ce<0> +1 +.names _n1ce<1> +0 +# location + 1 +.names _n1d0 +0 +.names location<0> _n1ce<0> _n1d0 _n1cf<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n1d2 +0 +.names location<0> _n1ce<0> _n1d2 _n1d1 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names location<1> _n1ce<1> _n1d1 _n1cf<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n1cf<0> location$_n1ca_n1cd$true<0> +- =_n1cf<0> +.names _n1cf<1> location$_n1ca_n1cd$true<1> +- =_n1cf<1> +# if/else (direction == 0) +.names location$_n1ca_n1cd$true<0> location<0> _n1ca location$_n1ca$raw_n1d8<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names location$_n1ca_n1cd$true<1> location<1> _n1ca location$_n1ca$raw_n1d8<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _n1dd 2 UP DOWN +.names _n1dd +DOWN +# direction == 1 +.names direction _n1dd _n1dc +.def 0 +- =direction 1 +.names _n1dc _n1de +- =_n1dc +# location = location - 1 +.names _n1e0<0> +1 +.names _n1e0<1> +0 +# location - 1 +.names _n1e2 +0 +.names location$_n1ca$raw_n1d8<0> _n1e0<0> _n1e2 _n1e1<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n1e4 +0 +.names location$_n1ca$raw_n1d8<0> _n1e0<0> _n1e4 _n1e3 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names location$_n1ca$raw_n1d8<1> _n1e0<1> _n1e3 _n1e1<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n1e1<0> location$_n1dc_n1df$true<0> +- =_n1e1<0> +.names _n1e1<1> location$_n1dc_n1df$true<1> +- =_n1e1<1> +# if/else (direction == 1) +.names location$_n1dc_n1df$true<0> location$_n1ca$raw_n1d8<0> _n1dc location$_n1dc$raw_n1e6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names location$_n1dc_n1df$true<1> location$_n1ca$raw_n1d8<1> _n1dc location$_n1dc$raw_n1e6<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (stop_moving ) +.mv movement$stop_moving$raw_n1f3 2 STOPPED MOVING +.names movement$stop_moving_n1c9$true movement stop_moving movement$stop_moving$raw_n1f3 +- - 0 =movement +- - 1 =movement$stop_moving_n1c9$true +.names location$_n1dc$raw_n1e6<0> location<0> stop_moving location$stop_moving$raw_n1f4<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names location$_n1dc$raw_n1e6<1> location<1> stop_moving location$stop_moving$raw_n1f4<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# case (movement ) +.mv movement$_n1c5$raw_n1fb 2 STOPPED MOVING +.names movement$stop_moving$raw_n1f3 movement _n1c5 movement$_n1c5$raw_n1fb +- - 0 =movement +- - 1 =movement$stop_moving$raw_n1f3 +.names location$stop_moving$raw_n1f4<0> location<0> _n1c5 location$_n1c5$raw_n1fc<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names location$stop_moving$raw_n1f4<1> location<1> _n1c5 location$_n1c5$raw_n1fc<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv movement$_n1b8$raw_n1ff 2 STOPPED MOVING +.names movement$_n1bf$raw_n1c4 movement$_n1c5$raw_n1fb _n1b8 movement$_n1b8$raw_n1ff +- - 0 =movement$_n1c5$raw_n1fb +- - 1 =movement$_n1bf$raw_n1c4 +.names location<0> location$_n1c5$raw_n1fc<0> _n1b8 location$_n1b8$raw_n203<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names location<1> location$_n1c5$raw_n1fc<1> _n1b8 location$_n1b8$raw_n203<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (door == 2) +.mv movement$_n1b5$raw_n20a 2 STOPPED MOVING +.names movement$_n1b8$raw_n1ff movement _n1b5 movement$_n1b5$raw_n20a +- - 0 =movement +- - 1 =movement$_n1b8$raw_n1ff +.names location$_n1b8$raw_n203<0> location<0> _n1b5 location$_n1b5$raw_n20b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names location$_n1b8$raw_n203<1> location<1> _n1b5 location$_n1b5$raw_n20b<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.mv _n210 2 UP DOWN +.names _n210 +UP +.names direction _n210 _n20f +.def 0 +- =direction 1 +.names _n20f _n20e +1 1 +0 0 +.names button_above _n211 +0 1 +1 0 +.names continue _n212 +0 1 +1 0 +# (!button_above ) && !continue +.names _n211 _n212 _n213 +.def 0 +1 1 1 +.names _n213 _n214 +- =_n213 +# direction = 1 +.mv direction$_n213_n215$true 2 UP DOWN +.names direction$_n213_n215$true +DOWN +# if/else ((!button_above ) && !continue ) +.mv direction$_n213$raw_n218 2 UP DOWN +.names direction$_n213_n215$true direction _n213 direction$_n213$raw_n218 +- - 0 =direction +- - 1 =direction$_n213_n215$true +.mv _n21b 2 UP DOWN +.names _n21b +DOWN +.names direction _n21b _n21a +.def 0 +- =direction 1 +.names _n21a _n219 +1 1 +0 0 +.names button_below _n21c +0 1 +1 0 +.names continue _n21d +0 1 +1 0 +# (!button_below ) && !continue +.names _n21c _n21d _n21e +.def 0 +1 1 1 +.names _n21e _n21f +- =_n21e +# direction = 0 +.mv direction$_n21e_n220$true 2 UP DOWN +.names direction$_n21e_n220$true +UP +# if/else ((!button_below ) && !continue ) +.mv direction$_n21e$raw_n223 2 UP DOWN +.names direction$_n21e_n220$true direction _n21e direction$_n21e$raw_n223 +- - 0 =direction +- - 1 =direction$_n21e_n220$true +# case (direction ) +.mv direction$_n219$raw_n226 2 UP DOWN +.names direction$_n21e$raw_n223 direction _n219 direction$_n219$raw_n226 +- - 0 =direction +- - 1 =direction$_n21e$raw_n223 +.mv direction$_n20e$raw_n227 2 UP DOWN +.names direction$_n213$raw_n218 direction$_n219$raw_n226 _n20e direction$_n20e$raw_n227 +- - 0 =direction$_n219$raw_n226 +- - 1 =direction$_n213$raw_n218 +.names _n22c<0> +1 +.names _n22c<1> +1 +.names _n22d<0> +1 +.names _n22d<1> +0 +# 3 - 1 +.names _n22f +0 +.names _n22c<0> _n22d<0> _n22f _n22e<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n231 +0 +.names _n22c<0> _n22d<0> _n231 _n230 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n22c<1> _n22d<1> _n230 _n22e<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# location == 3 - 1 +.names location<0> _n22e<0> _n232<0> +.def 0 +0 1 1 +1 0 1 +.names location<1> _n22e<1> _n232<1> +.def 0 +0 1 1 +1 0 1 +.names _n232<0> _n232<1> _n233 +.def 1 +0 0 0 +.names _n233 _n22b +0 1 +1 0 +.names _n22b _n234 +- =_n22b +# direction = 1 +.mv direction$_n22b_n235$true 2 UP DOWN +.names direction$_n22b_n235$true +DOWN +# if/else (location == 3 - 1) +.mv direction$_n22b$raw_n236 2 UP DOWN +.names direction$_n22b_n235$true direction$_n20e$raw_n227 _n22b direction$_n22b$raw_n236 +- - 0 =direction$_n20e$raw_n227 +- - 1 =direction$_n22b_n235$true +.names _n23b<0> +0 +.names _n23b<1> +0 +# location == 0 +.names location<0> _n23b<0> _n23c<0> +.def 0 +0 1 1 +1 0 1 +.names location<1> _n23b<1> _n23c<1> +.def 0 +0 1 1 +1 0 1 +.names _n23c<0> _n23c<1> _n23d +.def 1 +0 0 0 +.names _n23d _n23a +0 1 +1 0 +.names _n23a _n23e +- =_n23a +# direction = 0 +.mv direction$_n23a_n23f$true 2 UP DOWN +.names direction$_n23a_n23f$true +UP +# if/else (location == 0) +.mv direction$_n23a$raw_n240 2 UP DOWN +.names direction$_n23a_n23f$true direction$_n22b$raw_n236 _n23a direction$_n23a$raw_n240 +- - 0 =direction$_n22b$raw_n236 +- - 1 =direction$_n23a_n23f$true +# conflict arbitrators +.names button_above$raw_n6c button_above +0 0 +1 1 +.names _n1b7 _n1b8 _n1c0 _n1c5 _n1c8 _n244 +.def 0 + 1 1 1 - - 1 + 1 0 - 1 1 1 +.mv _n245 2 STOPPED MOVING +.names _n244 movement$_n1b5$raw_n20a movement _n245 +1 - - =movement$_n1b5$raw_n20a +0 - - =movement +.names _n89 _n99 _nb6 _nc6 _ne4 _nf4 _n10e _n111 _n25b +.def 0 + 1 - - - - - - - 1 + 0 1 - - - - - - 1 + - - 1 - - - - - 1 + - - 0 1 - - - - 1 + - - - - 1 - - - 1 + - - - - 0 1 - - 1 + - - - - - - 1 1 1 + - - - - - - 1 0 1 +.mv _n25c<*0*> 2 ON OFF +.mv _n25c<*1*> 2 ON OFF +.mv _n25c<*2*> 2 ON OFF +.names _n25b buttons$stop_next$raw_n13c<*0*> buttons<*0*> _n25c<*0*> +1 - - =buttons$stop_next$raw_n13c<*0*> +0 - - =buttons<*0*> +.names _n25b buttons$stop_next$raw_n13c<*1*> buttons<*1*> _n25c<*1*> +1 - - =buttons$stop_next$raw_n13c<*1*> +0 - - =buttons<*1*> +.names _n25b buttons$stop_next$raw_n13c<*2*> buttons<*2*> _n25c<*2*> +1 - - =buttons$stop_next$raw_n13c<*2*> +0 - - =buttons<*2*> +.names start_moving$raw_n19e start_moving +0 0 +1 1 +.names _n16c _n172 _n177 _n17a _n17f _n182 _n187 _n18a _n29c +.def 0 + 1 1 - - - - - - 1 + 0 - 1 1 - - - - 1 + 0 - 0 - 1 1 - - 1 + 0 - 0 - 0 - 1 1 1 +.mv _n29d 4 OPEN OPENING CLOSED CLOSING +.names _n29c door$_n16c$raw_n19a door _n29d +1 - - =door$_n16c$raw_n19a +0 - - =door +.names stop_moving$raw_n1a9 stop_moving +0 0 +1 1 +.names _n1b7 _n1b8 _n1c5 _n1c8 _n1cc _n1de _n2b3 +.def 0 + 1 0 1 1 1 - 1 + 1 0 1 1 - 1 1 +.names _n2b3 location$_n1b5$raw_n20b<0> location$_n1b5$raw_n20b<1> location<0> location<1> -> _n2b4<0> _n2b4<1> +1 - - - - =location$_n1b5$raw_n20b<0> =location$_n1b5$raw_n20b<1> +0 - - - - =location<0> =location<1> +.names button_below$raw_n53 button_below +0 0 +1 1 +.names _n20e _n214 _n219 _n21f _n234 _n23e _n2b5 +.def 0 + 1 1 - - - - 1 + 0 - 1 1 - - 1 + - - - - 1 - 1 + - - - - - 1 1 +.mv _n2b6 2 UP DOWN +.names _n2b5 direction$_n23a$raw_n240 direction _n2b6 +1 - - =direction$_n23a$raw_n240 +0 - - =direction +.names _n142 _n15f _n2cc +.def 0 + 1 - 1 + 0 1 1 +.names _n2cc open_next$_n140$raw_n166 open_next _n2cd +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names dec$raw_n1b1 dec +0 0 +1 1 +.names inc$raw_n1ad inc +0 0 +1 1 +# non-blocking assignments +# latches +.r movement$raw_n1a movement +- =movement$raw_n1a +.latch _n245 movement +.r buttons$raw_n1b<*0*> buttons$raw_n2d<*0*> buttons$raw_n3f<*0*> buttons<*0*> +.def ON +OFF - - =buttons$raw_n1b<*0*> +ON OFF - =buttons$raw_n2d<*0*> +ON ON OFF =buttons$raw_n3f<*0*> +.r buttons$raw_n1b<*1*> buttons$raw_n2d<*1*> buttons$raw_n3f<*1*> buttons<*1*> +.def ON +OFF - - =buttons$raw_n1b<*1*> +ON OFF - =buttons$raw_n2d<*1*> +ON ON OFF =buttons$raw_n3f<*1*> +.r buttons$raw_n1b<*2*> buttons$raw_n2d<*2*> buttons$raw_n3f<*2*> buttons<*2*> +.def ON +OFF - - =buttons$raw_n1b<*2*> +ON OFF - =buttons$raw_n2d<*2*> +ON ON OFF =buttons$raw_n3f<*2*> +.latch _n25c<*0*> buttons<*0*> +.latch _n25c<*1*> buttons<*1*> +.latch _n25c<*2*> buttons<*2*> +.r door$raw_n19 door +- =door$raw_n19 +.latch _n29d door +.r location$raw_n17<0> location<0> +.def 0 +1 1 +.r location$raw_n17<1> location<1> +.def 0 +1 1 +.latch _n2b4<0> location<0> +.latch _n2b4<1> location<1> +.r direction$raw_n18 direction +- =direction$raw_n18 +.latch _n2b6 direction +.r open_next$raw_n16 open_next +0 0 +1 1 +.latch _n2cd open_next +# quasi-continuous assignment +.end + + +.model main_control +# I/O ports +.inputs init2<0> init2<1> +.inputs init1<0> init1<1> +.outputs stop_next<1> stop_next<2> +.inputs dec<1> dec<2> +.inputs inc<1> inc<2> +.outputs continue<1> continue<2> + +.mv down_floor_buttons<*0*> 2 ON OFF +.mv down_floor_buttons<*1*> 2 ON OFF +.mv down_floor_buttons<*2*> 2 ON OFF +.mv direction<*1*> 2 UP DOWN +.mv direction<*2*> 2 UP DOWN +.mv up_floor_buttons<*0*> 2 ON OFF +.mv up_floor_buttons<*1*> 2 ON OFF +.mv up_floor_buttons<*2*> 2 ON OFF +# locations [1] = init1 +.names _n2d0<0> +1 +.names _n2d0<1> +0 +.names _n2d1<0> +1 +.names _n2d1<1> +0 +.names _n2d1<0> _n2d0<0> _n2d3<0> +.def 0 +0 1 1 +1 0 1 +.names _n2d1<1> _n2d0<1> _n2d3<1> +.def 0 +0 1 1 +1 0 1 +.names _n2d3<0> _n2d3<1> _n2d4 +.def 1 +0 0 0 +.names _n2d4 _n2d2 +0 1 +1 0 +.names _n2d5<0> +0 +.names _n2d5<1> +0 +.names _n2cf<0> _n2d5<0> _n2d2 locations$raw_n2ce<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2cf<1> _n2d5<1> _n2d2 locations$raw_n2ce<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2d8<0> +0 +.names _n2d8<1> +1 +.names _n2d8<0> _n2d0<0> _n2da<0> +.def 0 +0 1 1 +1 0 1 +.names _n2d8<1> _n2d0<1> _n2da<1> +.def 0 +0 1 1 +1 0 1 +.names _n2da<0> _n2da<1> _n2db +.def 1 +0 0 0 +.names _n2db _n2d9 +0 1 +1 0 +.names _n2dc<0> +0 +.names _n2dc<1> +0 +.names _n2cf<0> _n2dc<0> _n2d9 locations$raw_n2ce<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2cf<1> _n2dc<1> _n2d9 locations$raw_n2ce<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names init1<0> _n2cf<0> +- =init1<0> +.names init1<1> _n2cf<1> +- =init1<1> +# locations [2] = init2 +.names _n2e1<0> +0 +.names _n2e1<1> +1 +.names _n2e2<0> +1 +.names _n2e2<1> +0 +.names _n2e2<0> _n2e1<0> _n2e4<0> +.def 0 +0 1 1 +1 0 1 +.names _n2e2<1> _n2e1<1> _n2e4<1> +.def 0 +0 1 1 +1 0 1 +.names _n2e4<0> _n2e4<1> _n2e5 +.def 1 +0 0 0 +.names _n2e5 _n2e3 +0 1 +1 0 +.names _n2e0<0> locations$raw_n2ce<*1*><0> _n2e3 locations$raw_n2df<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2e0<1> locations$raw_n2ce<*1*><1> _n2e3 locations$raw_n2df<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2e8<0> +0 +.names _n2e8<1> +1 +.names _n2e8<0> _n2e1<0> _n2ea<0> +.def 0 +0 1 1 +1 0 1 +.names _n2e8<1> _n2e1<1> _n2ea<1> +.def 0 +0 1 1 +1 0 1 +.names _n2ea<0> _n2ea<1> _n2eb +.def 1 +0 0 0 +.names _n2eb _n2e9 +0 1 +1 0 +.names _n2e0<0> locations$raw_n2ce<*2*><0> _n2e9 locations$raw_n2df<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n2e0<1> locations$raw_n2ce<*2*><1> _n2e9 locations$raw_n2df<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names init2<0> _n2e0<0> +- =init2<0> +.names init2<1> _n2e0<1> +- =init2<1> +# up_floor_buttons [0] = 1 +.mv up_floor_buttons$raw_n2ee<*0*> 2 ON OFF +.mv up_floor_buttons$raw_n2ee<*1*> 2 ON OFF +.mv up_floor_buttons$raw_n2ee<*2*> 2 ON OFF +.mv _n2ef 2 ON OFF +.names _n2f0<0> +0 +.names _n2f0<1> +0 +.names _n2f1<0> +0 +.names _n2f1<1> +0 +.names _n2f1<0> _n2f0<0> _n2f3<0> +.def 0 +0 1 1 +1 0 1 +.names _n2f1<1> _n2f0<1> _n2f3<1> +.def 0 +0 1 1 +1 0 1 +.names _n2f3<0> _n2f3<1> _n2f4 +.def 1 +0 0 0 +.names _n2f4 _n2f2 +0 1 +1 0 +.mv _n2f5 2 ON OFF +.names _n2f5 +ON +.names _n2ef _n2f5 _n2f2 up_floor_buttons$raw_n2ee<*0*> +- - 0 =_n2f5 +- - 1 =_n2ef +.names _n2f6<0> +1 +.names _n2f6<1> +0 +.names _n2f6<0> _n2f0<0> _n2f8<0> +.def 0 +0 1 1 +1 0 1 +.names _n2f6<1> _n2f0<1> _n2f8<1> +.def 0 +0 1 1 +1 0 1 +.names _n2f8<0> _n2f8<1> _n2f9 +.def 1 +0 0 0 +.names _n2f9 _n2f7 +0 1 +1 0 +.mv _n2fa 2 ON OFF +.names _n2fa +ON +.names _n2ef _n2fa _n2f7 up_floor_buttons$raw_n2ee<*1*> +- - 0 =_n2fa +- - 1 =_n2ef +.names _n2fb<0> +0 +.names _n2fb<1> +1 +.names _n2fb<0> _n2f0<0> _n2fd<0> +.def 0 +0 1 1 +1 0 1 +.names _n2fb<1> _n2f0<1> _n2fd<1> +.def 0 +0 1 1 +1 0 1 +.names _n2fd<0> _n2fd<1> _n2fe +.def 1 +0 0 0 +.names _n2fe _n2fc +0 1 +1 0 +.mv _n2ff 2 ON OFF +.names _n2ff +ON +.names _n2ef _n2ff _n2fc up_floor_buttons$raw_n2ee<*2*> +- - 0 =_n2ff +- - 1 =_n2ef +.names _n2ef +OFF +# up_floor_buttons [1] = 1 +.mv up_floor_buttons$raw_n300<*0*> 2 ON OFF +.mv up_floor_buttons$raw_n300<*1*> 2 ON OFF +.mv up_floor_buttons$raw_n300<*2*> 2 ON OFF +.mv _n301 2 ON OFF +.names _n302<0> +1 +.names _n302<1> +0 +.names _n303<0> +0 +.names _n303<1> +0 +.names _n303<0> _n302<0> _n305<0> +.def 0 +0 1 1 +1 0 1 +.names _n303<1> _n302<1> _n305<1> +.def 0 +0 1 1 +1 0 1 +.names _n305<0> _n305<1> _n306 +.def 1 +0 0 0 +.names _n306 _n304 +0 1 +1 0 +.names _n301 up_floor_buttons$raw_n2ee<*0*> _n304 up_floor_buttons$raw_n300<*0*> +- - 0 =up_floor_buttons$raw_n2ee<*0*> +- - 1 =_n301 +.names _n307<0> +1 +.names _n307<1> +0 +.names _n307<0> _n302<0> _n309<0> +.def 0 +0 1 1 +1 0 1 +.names _n307<1> _n302<1> _n309<1> +.def 0 +0 1 1 +1 0 1 +.names _n309<0> _n309<1> _n30a +.def 1 +0 0 0 +.names _n30a _n308 +0 1 +1 0 +.names _n301 up_floor_buttons$raw_n2ee<*1*> _n308 up_floor_buttons$raw_n300<*1*> +- - 0 =up_floor_buttons$raw_n2ee<*1*> +- - 1 =_n301 +.names _n30b<0> +0 +.names _n30b<1> +1 +.names _n30b<0> _n302<0> _n30d<0> +.def 0 +0 1 1 +1 0 1 +.names _n30b<1> _n302<1> _n30d<1> +.def 0 +0 1 1 +1 0 1 +.names _n30d<0> _n30d<1> _n30e +.def 1 +0 0 0 +.names _n30e _n30c +0 1 +1 0 +.names _n301 up_floor_buttons$raw_n2ee<*2*> _n30c up_floor_buttons$raw_n300<*2*> +- - 0 =up_floor_buttons$raw_n2ee<*2*> +- - 1 =_n301 +.names _n301 +OFF +# up_floor_buttons [2] = 1 +.mv up_floor_buttons$raw_n30f<*0*> 2 ON OFF +.mv up_floor_buttons$raw_n30f<*1*> 2 ON OFF +.mv up_floor_buttons$raw_n30f<*2*> 2 ON OFF +.mv _n310 2 ON OFF +.names _n311<0> +0 +.names _n311<1> +1 +.names _n312<0> +0 +.names _n312<1> +0 +.names _n312<0> _n311<0> _n314<0> +.def 0 +0 1 1 +1 0 1 +.names _n312<1> _n311<1> _n314<1> +.def 0 +0 1 1 +1 0 1 +.names _n314<0> _n314<1> _n315 +.def 1 +0 0 0 +.names _n315 _n313 +0 1 +1 0 +.names _n310 up_floor_buttons$raw_n300<*0*> _n313 up_floor_buttons$raw_n30f<*0*> +- - 0 =up_floor_buttons$raw_n300<*0*> +- - 1 =_n310 +.names _n316<0> +1 +.names _n316<1> +0 +.names _n316<0> _n311<0> _n318<0> +.def 0 +0 1 1 +1 0 1 +.names _n316<1> _n311<1> _n318<1> +.def 0 +0 1 1 +1 0 1 +.names _n318<0> _n318<1> _n319 +.def 1 +0 0 0 +.names _n319 _n317 +0 1 +1 0 +.names _n310 up_floor_buttons$raw_n300<*1*> _n317 up_floor_buttons$raw_n30f<*1*> +- - 0 =up_floor_buttons$raw_n300<*1*> +- - 1 =_n310 +.names _n31a<0> +0 +.names _n31a<1> +1 +.names _n31a<0> _n311<0> _n31c<0> +.def 0 +0 1 1 +1 0 1 +.names _n31a<1> _n311<1> _n31c<1> +.def 0 +0 1 1 +1 0 1 +.names _n31c<0> _n31c<1> _n31d +.def 1 +0 0 0 +.names _n31d _n31b +0 1 +1 0 +.names _n310 up_floor_buttons$raw_n300<*2*> _n31b up_floor_buttons$raw_n30f<*2*> +- - 0 =up_floor_buttons$raw_n300<*2*> +- - 1 =_n310 +.names _n310 +OFF +# down_floor_buttons [0] = 1 +.mv down_floor_buttons$raw_n31e<*0*> 2 ON OFF +.mv down_floor_buttons$raw_n31e<*1*> 2 ON OFF +.mv down_floor_buttons$raw_n31e<*2*> 2 ON OFF +.mv _n31f 2 ON OFF +.names _n320<0> +0 +.names _n320<1> +0 +.names _n321<0> +0 +.names _n321<1> +0 +.names _n321<0> _n320<0> _n323<0> +.def 0 +0 1 1 +1 0 1 +.names _n321<1> _n320<1> _n323<1> +.def 0 +0 1 1 +1 0 1 +.names _n323<0> _n323<1> _n324 +.def 1 +0 0 0 +.names _n324 _n322 +0 1 +1 0 +.mv _n325 2 ON OFF +.names _n325 +ON +.names _n31f _n325 _n322 down_floor_buttons$raw_n31e<*0*> +- - 0 =_n325 +- - 1 =_n31f +.names _n326<0> +1 +.names _n326<1> +0 +.names _n326<0> _n320<0> _n328<0> +.def 0 +0 1 1 +1 0 1 +.names _n326<1> _n320<1> _n328<1> +.def 0 +0 1 1 +1 0 1 +.names _n328<0> _n328<1> _n329 +.def 1 +0 0 0 +.names _n329 _n327 +0 1 +1 0 +.mv _n32a 2 ON OFF +.names _n32a +ON +.names _n31f _n32a _n327 down_floor_buttons$raw_n31e<*1*> +- - 0 =_n32a +- - 1 =_n31f +.names _n32b<0> +0 +.names _n32b<1> +1 +.names _n32b<0> _n320<0> _n32d<0> +.def 0 +0 1 1 +1 0 1 +.names _n32b<1> _n320<1> _n32d<1> +.def 0 +0 1 1 +1 0 1 +.names _n32d<0> _n32d<1> _n32e +.def 1 +0 0 0 +.names _n32e _n32c +0 1 +1 0 +.mv _n32f 2 ON OFF +.names _n32f +ON +.names _n31f _n32f _n32c down_floor_buttons$raw_n31e<*2*> +- - 0 =_n32f +- - 1 =_n31f +.names _n31f +OFF +# down_floor_buttons [1] = 1 +.mv down_floor_buttons$raw_n330<*0*> 2 ON OFF +.mv down_floor_buttons$raw_n330<*1*> 2 ON OFF +.mv down_floor_buttons$raw_n330<*2*> 2 ON OFF +.mv _n331 2 ON OFF +.names _n332<0> +1 +.names _n332<1> +0 +.names _n333<0> +0 +.names _n333<1> +0 +.names _n333<0> _n332<0> _n335<0> +.def 0 +0 1 1 +1 0 1 +.names _n333<1> _n332<1> _n335<1> +.def 0 +0 1 1 +1 0 1 +.names _n335<0> _n335<1> _n336 +.def 1 +0 0 0 +.names _n336 _n334 +0 1 +1 0 +.names _n331 down_floor_buttons$raw_n31e<*0*> _n334 down_floor_buttons$raw_n330<*0*> +- - 0 =down_floor_buttons$raw_n31e<*0*> +- - 1 =_n331 +.names _n337<0> +1 +.names _n337<1> +0 +.names _n337<0> _n332<0> _n339<0> +.def 0 +0 1 1 +1 0 1 +.names _n337<1> _n332<1> _n339<1> +.def 0 +0 1 1 +1 0 1 +.names _n339<0> _n339<1> _n33a +.def 1 +0 0 0 +.names _n33a _n338 +0 1 +1 0 +.names _n331 down_floor_buttons$raw_n31e<*1*> _n338 down_floor_buttons$raw_n330<*1*> +- - 0 =down_floor_buttons$raw_n31e<*1*> +- - 1 =_n331 +.names _n33b<0> +0 +.names _n33b<1> +1 +.names _n33b<0> _n332<0> _n33d<0> +.def 0 +0 1 1 +1 0 1 +.names _n33b<1> _n332<1> _n33d<1> +.def 0 +0 1 1 +1 0 1 +.names _n33d<0> _n33d<1> _n33e +.def 1 +0 0 0 +.names _n33e _n33c +0 1 +1 0 +.names _n331 down_floor_buttons$raw_n31e<*2*> _n33c down_floor_buttons$raw_n330<*2*> +- - 0 =down_floor_buttons$raw_n31e<*2*> +- - 1 =_n331 +.names _n331 +OFF +# down_floor_buttons [2] = 1 +.mv down_floor_buttons$raw_n33f<*0*> 2 ON OFF +.mv down_floor_buttons$raw_n33f<*1*> 2 ON OFF +.mv down_floor_buttons$raw_n33f<*2*> 2 ON OFF +.mv _n340 2 ON OFF +.names _n341<0> +0 +.names _n341<1> +1 +.names _n342<0> +0 +.names _n342<1> +0 +.names _n342<0> _n341<0> _n344<0> +.def 0 +0 1 1 +1 0 1 +.names _n342<1> _n341<1> _n344<1> +.def 0 +0 1 1 +1 0 1 +.names _n344<0> _n344<1> _n345 +.def 1 +0 0 0 +.names _n345 _n343 +0 1 +1 0 +.names _n340 down_floor_buttons$raw_n330<*0*> _n343 down_floor_buttons$raw_n33f<*0*> +- - 0 =down_floor_buttons$raw_n330<*0*> +- - 1 =_n340 +.names _n346<0> +1 +.names _n346<1> +0 +.names _n346<0> _n341<0> _n348<0> +.def 0 +0 1 1 +1 0 1 +.names _n346<1> _n341<1> _n348<1> +.def 0 +0 1 1 +1 0 1 +.names _n348<0> _n348<1> _n349 +.def 1 +0 0 0 +.names _n349 _n347 +0 1 +1 0 +.names _n340 down_floor_buttons$raw_n330<*1*> _n347 down_floor_buttons$raw_n33f<*1*> +- - 0 =down_floor_buttons$raw_n330<*1*> +- - 1 =_n340 +.names _n34a<0> +0 +.names _n34a<1> +1 +.names _n34a<0> _n341<0> _n34c<0> +.def 0 +0 1 1 +1 0 1 +.names _n34a<1> _n341<1> _n34c<1> +.def 0 +0 1 1 +1 0 1 +.names _n34c<0> _n34c<1> _n34d +.def 1 +0 0 0 +.names _n34d _n34b +0 1 +1 0 +.names _n340 down_floor_buttons$raw_n330<*2*> _n34b down_floor_buttons$raw_n33f<*2*> +- - 0 =down_floor_buttons$raw_n330<*2*> +- - 1 =_n340 +.names _n340 +OFF +# direction [1] = 0 +.mv direction$raw_n34e<*1*> 2 UP DOWN +.mv direction$raw_n34e<*2*> 2 UP DOWN +.mv _n34f 2 UP DOWN +.names _n350<0> +1 +.names _n350<1> +0 +.names _n351<0> +1 +.names _n351<1> +0 +.names _n351<0> _n350<0> _n353<0> +.def 0 +0 1 1 +1 0 1 +.names _n351<1> _n350<1> _n353<1> +.def 0 +0 1 1 +1 0 1 +.names _n353<0> _n353<1> _n354 +.def 1 +0 0 0 +.names _n354 _n352 +0 1 +1 0 +.mv _n355 2 UP DOWN +.names _n355 +UP +.names _n34f _n355 _n352 direction$raw_n34e<*1*> +- - 0 =_n355 +- - 1 =_n34f +.names _n356<0> +0 +.names _n356<1> +1 +.names _n356<0> _n350<0> _n358<0> +.def 0 +0 1 1 +1 0 1 +.names _n356<1> _n350<1> _n358<1> +.def 0 +0 1 1 +1 0 1 +.names _n358<0> _n358<1> _n359 +.def 1 +0 0 0 +.names _n359 _n357 +0 1 +1 0 +.mv _n35a 2 UP DOWN +.names _n35a +UP +.names _n34f _n35a _n357 direction$raw_n34e<*2*> +- - 0 =_n35a +- - 1 =_n34f +.names _n34f +UP +# direction [2] = 0 +.mv direction$raw_n35b<*1*> 2 UP DOWN +.mv direction$raw_n35b<*2*> 2 UP DOWN +.mv _n35c 2 UP DOWN +.names _n35d<0> +0 +.names _n35d<1> +1 +.names _n35e<0> +1 +.names _n35e<1> +0 +.names _n35e<0> _n35d<0> _n360<0> +.def 0 +0 1 1 +1 0 1 +.names _n35e<1> _n35d<1> _n360<1> +.def 0 +0 1 1 +1 0 1 +.names _n360<0> _n360<1> _n361 +.def 1 +0 0 0 +.names _n361 _n35f +0 1 +1 0 +.names _n35c direction$raw_n34e<*1*> _n35f direction$raw_n35b<*1*> +- - 0 =direction$raw_n34e<*1*> +- - 1 =_n35c +.names _n362<0> +0 +.names _n362<1> +1 +.names _n362<0> _n35d<0> _n364<0> +.def 0 +0 1 1 +1 0 1 +.names _n362<1> _n35d<1> _n364<1> +.def 0 +0 1 1 +1 0 1 +.names _n364<0> _n364<1> _n365 +.def 1 +0 0 0 +.names _n365 _n363 +0 1 +1 0 +.names _n35c direction$raw_n34e<*2*> _n363 direction$raw_n35b<*2*> +- - 0 =direction$raw_n34e<*2*> +- - 1 =_n35c +.names _n35c +UP +# non-blocking assignments for initial +# assign buttons [0] = up_floor_buttons [0] == ON || down_floor_buttons [0] == ON +.names _n368<0> +0 +.names _n368<1> +0 +.mv _n369 2 ON OFF +.names up_floor_buttons<*0*> up_floor_buttons<*1*> up_floor_buttons<*2*> _n368<1> _n368<0> _n369 +- - - 0 0 =up_floor_buttons<*0*> +- - - 0 1 =up_floor_buttons<*1*> +- - - 1 0 =up_floor_buttons<*2*> +- - - 1 1 ON +.mv _n36a 2 ON OFF +.names _n36a +ON +# up_floor_buttons [0] == 0 +.names _n369 _n36a _n367 +.def 0 +- =_n369 1 +.names _n36c<0> +0 +.names _n36c<1> +0 +.mv _n36d 2 ON OFF +.names down_floor_buttons<*0*> down_floor_buttons<*1*> down_floor_buttons<*2*> _n36c<1> _n36c<0> _n36d +- - - 0 0 =down_floor_buttons<*0*> +- - - 0 1 =down_floor_buttons<*1*> +- - - 1 0 =down_floor_buttons<*2*> +- - - 1 1 ON +.mv _n36e 2 ON OFF +.names _n36e +ON +# down_floor_buttons [0] == 0 +.names _n36d _n36e _n36b +.def 0 +- =_n36d 1 +# up_floor_buttons [0] == 0 || down_floor_buttons [0] == 0 +.names _n367 _n36b _n36f +.def 1 +0 0 0 +.names _n36f buttons$raw_n366<0> +- =_n36f +.names _n370 +0 +# assign buttons [1] = up_floor_buttons [1] == ON || down_floor_buttons [1] == ON +.names _n373<0> +1 +.names _n373<1> +0 +.mv _n374 2 ON OFF +.names up_floor_buttons<*0*> up_floor_buttons<*1*> up_floor_buttons<*2*> _n373<1> _n373<0> _n374 +- - - 0 0 =up_floor_buttons<*0*> +- - - 0 1 =up_floor_buttons<*1*> +- - - 1 0 =up_floor_buttons<*2*> +- - - 1 1 ON +.mv _n375 2 ON OFF +.names _n375 +ON +# up_floor_buttons [1] == 0 +.names _n374 _n375 _n372 +.def 0 +- =_n374 1 +.names _n377<0> +1 +.names _n377<1> +0 +.mv _n378 2 ON OFF +.names down_floor_buttons<*0*> down_floor_buttons<*1*> down_floor_buttons<*2*> _n377<1> _n377<0> _n378 +- - - 0 0 =down_floor_buttons<*0*> +- - - 0 1 =down_floor_buttons<*1*> +- - - 1 0 =down_floor_buttons<*2*> +- - - 1 1 ON +.mv _n379 2 ON OFF +.names _n379 +ON +# down_floor_buttons [1] == 0 +.names _n378 _n379 _n376 +.def 0 +- =_n378 1 +# up_floor_buttons [1] == 0 || down_floor_buttons [1] == 0 +.names _n372 _n376 _n37a +.def 1 +0 0 0 +.names _n37a buttons$raw_n371<1> +- =_n37a +.names _n37b +0 +# assign buttons [2] = up_floor_buttons [2] == ON || down_floor_buttons [2] == ON +.names _n37e<0> +0 +.names _n37e<1> +1 +.mv _n37f 2 ON OFF +.names up_floor_buttons<*0*> up_floor_buttons<*1*> up_floor_buttons<*2*> _n37e<1> _n37e<0> _n37f +- - - 0 0 =up_floor_buttons<*0*> +- - - 0 1 =up_floor_buttons<*1*> +- - - 1 0 =up_floor_buttons<*2*> +- - - 1 1 ON +.mv _n380 2 ON OFF +.names _n380 +ON +# up_floor_buttons [2] == 0 +.names _n37f _n380 _n37d +.def 0 +- =_n37f 1 +.names _n382<0> +0 +.names _n382<1> +1 +.mv _n383 2 ON OFF +.names down_floor_buttons<*0*> down_floor_buttons<*1*> down_floor_buttons<*2*> _n382<1> _n382<0> _n383 +- - - 0 0 =down_floor_buttons<*0*> +- - - 0 1 =down_floor_buttons<*1*> +- - - 1 0 =down_floor_buttons<*2*> +- - - 1 1 ON +.mv _n384 2 ON OFF +.names _n384 +ON +# down_floor_buttons [2] == 0 +.names _n383 _n384 _n381 +.def 0 +- =_n383 1 +# up_floor_buttons [2] == 0 || down_floor_buttons [2] == 0 +.names _n37d _n381 _n385 +.def 1 +0 0 0 +.names _n385 buttons$raw_n37c<2> +- =_n385 +.names _n386 +0 +# assign button_below [1] = ((locations [1] == 2) && (buttons [0] || buttons [1])) || (locations [1] == 1 && buttons [0]) +.names _n389<0> +1 +.names _n389<1> +0 +.names locations<*1*><0> locations<*2*><0> _n389<1> _n389<0> _n38a<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n389<1> _n389<0> _n38a<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n38b<0> +0 +.names _n38b<1> +1 +# locations [1] == 2 +.names _n38a<0> _n38b<0> _n38c<0> +.def 0 +0 1 1 +1 0 1 +.names _n38a<1> _n38b<1> _n38c<1> +.def 0 +0 1 1 +1 0 1 +.names _n38c<0> _n38c<1> _n38d +.def 1 +0 0 0 +.names _n38d _n388 +0 1 +1 0 +# buttons [0] || buttons [1] +.names buttons<0> buttons<1> _n38e<0> +.def 1 +0 0 0 +# (locations [1] == 2) && (buttons [0] || buttons [1]) +.names _n388 _n38e<0> _n38f<0> +.def 0 +1 1 1 +.names _n390 +0 +.names _n392<0> +1 +.names _n392<1> +0 +.names locations<*1*><0> locations<*2*><0> _n392<1> _n392<0> _n393<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n392<1> _n392<0> _n393<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n394<0> +1 +.names _n394<1> +0 +# locations [1] == 1 +.names _n393<0> _n394<0> _n395<0> +.def 0 +0 1 1 +1 0 1 +.names _n393<1> _n394<1> _n395<1> +.def 0 +0 1 1 +1 0 1 +.names _n395<0> _n395<1> _n396 +.def 1 +0 0 0 +.names _n396 _n391 +0 1 +1 0 +# locations [1] == 1 && buttons [0] +.names _n391 buttons<0> _n397<0> +.def 0 +1 1 1 +.names _n398 +0 +# ((locations [1] == 2) && (buttons [0] || buttons [1])) || (locations [1] == 1 && buttons [0]) +.names _n38f<0> _n397<0> _n399<0> +.def 1 +0 0 0 +.names _n399<0> button_below$raw_n387<1> +- =_n399<0> +# assign button_above [1] = ((locations [1] == 0) && (buttons [2] || buttons [1])) || ((locations [1] == 1) && (buttons [2])) +.names _n39c<0> +1 +.names _n39c<1> +0 +.names locations<*1*><0> locations<*2*><0> _n39c<1> _n39c<0> _n39d<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n39c<1> _n39c<0> _n39d<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n39e<0> +0 +.names _n39e<1> +0 +# locations [1] == 0 +.names _n39d<0> _n39e<0> _n39f<0> +.def 0 +0 1 1 +1 0 1 +.names _n39d<1> _n39e<1> _n39f<1> +.def 0 +0 1 1 +1 0 1 +.names _n39f<0> _n39f<1> _n3a0 +.def 1 +0 0 0 +.names _n3a0 _n39b +0 1 +1 0 +# buttons [2] || buttons [1] +.names buttons<2> buttons<1> _n3a1<0> +.def 1 +0 0 0 +# (locations [1] == 0) && (buttons [2] || buttons [1]) +.names _n39b _n3a1<0> _n3a2<0> +.def 0 +1 1 1 +.names _n3a3 +0 +.names _n3a5<0> +1 +.names _n3a5<1> +0 +.names locations<*1*><0> locations<*2*><0> _n3a5<1> _n3a5<0> _n3a6<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n3a5<1> _n3a5<0> _n3a6<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n3a7<0> +1 +.names _n3a7<1> +0 +# locations [1] == 1 +.names _n3a6<0> _n3a7<0> _n3a8<0> +.def 0 +0 1 1 +1 0 1 +.names _n3a6<1> _n3a7<1> _n3a8<1> +.def 0 +0 1 1 +1 0 1 +.names _n3a8<0> _n3a8<1> _n3a9 +.def 1 +0 0 0 +.names _n3a9 _n3a4 +0 1 +1 0 +# (locations [1] == 1) && (buttons [2]) +.names _n3a4 buttons<2> _n3aa<2> +.def 0 +1 1 1 +.names _n3ab +0 +# ((locations [1] == 0) && (buttons [2] || buttons [1])) || ((locations [1] == 1) && (buttons [2])) +.names _n3a2<0> _n3aa<2> _n3ac<0> +.def 1 +0 0 0 +.names _n3ac<0> button_above$raw_n39a<1> +- =_n3ac<0> +# assign button_below [2] = ((locations [2] == 2) && (buttons [0] || buttons [1])) || (locations [2] == 1 && buttons [0]) +.names _n3af<0> +0 +.names _n3af<1> +1 +.names locations<*1*><0> locations<*2*><0> _n3af<1> _n3af<0> _n3b0<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n3af<1> _n3af<0> _n3b0<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n3b1<0> +0 +.names _n3b1<1> +1 +# locations [2] == 2 +.names _n3b0<0> _n3b1<0> _n3b2<0> +.def 0 +0 1 1 +1 0 1 +.names _n3b0<1> _n3b1<1> _n3b2<1> +.def 0 +0 1 1 +1 0 1 +.names _n3b2<0> _n3b2<1> _n3b3 +.def 1 +0 0 0 +.names _n3b3 _n3ae +0 1 +1 0 +# buttons [0] || buttons [1] +.names buttons<0> buttons<1> _n3b4<0> +.def 1 +0 0 0 +# (locations [2] == 2) && (buttons [0] || buttons [1]) +.names _n3ae _n3b4<0> _n3b5<0> +.def 0 +1 1 1 +.names _n3b6 +0 +.names _n3b8<0> +0 +.names _n3b8<1> +1 +.names locations<*1*><0> locations<*2*><0> _n3b8<1> _n3b8<0> _n3b9<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n3b8<1> _n3b8<0> _n3b9<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n3ba<0> +1 +.names _n3ba<1> +0 +# locations [2] == 1 +.names _n3b9<0> _n3ba<0> _n3bb<0> +.def 0 +0 1 1 +1 0 1 +.names _n3b9<1> _n3ba<1> _n3bb<1> +.def 0 +0 1 1 +1 0 1 +.names _n3bb<0> _n3bb<1> _n3bc +.def 1 +0 0 0 +.names _n3bc _n3b7 +0 1 +1 0 +# locations [2] == 1 && buttons [0] +.names _n3b7 buttons<0> _n3bd<0> +.def 0 +1 1 1 +.names _n3be +0 +# ((locations [2] == 2) && (buttons [0] || buttons [1])) || (locations [2] == 1 && buttons [0]) +.names _n3b5<0> _n3bd<0> _n3bf<0> +.def 1 +0 0 0 +.names _n3bf<0> button_below$raw_n3ad<2> +- =_n3bf<0> +# assign button_above [2] = ((locations [2] == 0) && (buttons [2] || buttons [1])) || ((locations [2] == 1) && (buttons [2])) +.names _n3c2<0> +0 +.names _n3c2<1> +1 +.names locations<*1*><0> locations<*2*><0> _n3c2<1> _n3c2<0> _n3c3<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n3c2<1> _n3c2<0> _n3c3<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n3c4<0> +0 +.names _n3c4<1> +0 +# locations [2] == 0 +.names _n3c3<0> _n3c4<0> _n3c5<0> +.def 0 +0 1 1 +1 0 1 +.names _n3c3<1> _n3c4<1> _n3c5<1> +.def 0 +0 1 1 +1 0 1 +.names _n3c5<0> _n3c5<1> _n3c6 +.def 1 +0 0 0 +.names _n3c6 _n3c1 +0 1 +1 0 +# buttons [2] || buttons [1] +.names buttons<2> buttons<1> _n3c7<0> +.def 1 +0 0 0 +# (locations [2] == 0) && (buttons [2] || buttons [1]) +.names _n3c1 _n3c7<0> _n3c8<0> +.def 0 +1 1 1 +.names _n3c9 +0 +.names _n3cb<0> +0 +.names _n3cb<1> +1 +.names locations<*1*><0> locations<*2*><0> _n3cb<1> _n3cb<0> _n3cc<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n3cb<1> _n3cb<0> _n3cc<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n3cd<0> +1 +.names _n3cd<1> +0 +# locations [2] == 1 +.names _n3cc<0> _n3cd<0> _n3ce<0> +.def 0 +0 1 1 +1 0 1 +.names _n3cc<1> _n3cd<1> _n3ce<1> +.def 0 +0 1 1 +1 0 1 +.names _n3ce<0> _n3ce<1> _n3cf +.def 1 +0 0 0 +.names _n3cf _n3ca +0 1 +1 0 +# (locations [2] == 1) && (buttons [2]) +.names _n3ca buttons<2> _n3d0<2> +.def 0 +1 1 1 +.names _n3d1 +0 +# ((locations [2] == 0) && (buttons [2] || buttons [1])) || ((locations [2] == 1) && (buttons [2])) +.names _n3c8<0> _n3d0<2> _n3d2<0> +.def 1 +0 0 0 +.names _n3d2<0> button_above$raw_n3c0<2> +- =_n3d2<0> +# assign continue [1] = button_above [1] && direction [1] == UP || button_below [1] && direction [1] == DOWN +.names _n3d5<0> +1 +.names _n3d5<1> +0 +.mv _n3d6 2 UP DOWN +.names direction<*1*> direction<*2*> _n3d5<1> _n3d5<0> _n3d6 +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n3d7 2 UP DOWN +.names _n3d7 +UP +# direction [1] == 0 +.names _n3d6 _n3d7 _n3d4 +.def 0 +- =_n3d6 1 +# button_above [1] && direction [1] == 0 +.names button_above<1> _n3d4 _n3d8<1> +.def 0 +1 1 1 +.names _n3d9 +0 +.names _n3db<0> +1 +.names _n3db<1> +0 +.mv _n3dc 2 UP DOWN +.names direction<*1*> direction<*2*> _n3db<1> _n3db<0> _n3dc +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n3dd 2 UP DOWN +.names _n3dd +DOWN +# direction [1] == 1 +.names _n3dc _n3dd _n3da +.def 0 +- =_n3dc 1 +# button_below [1] && direction [1] == 1 +.names button_below<1> _n3da _n3de<1> +.def 0 +1 1 1 +.names _n3df +0 +# button_above [1] && direction [1] == 0 || button_below [1] && direction [1] == 1 +.names _n3d8<1> _n3de<1> _n3e0<0> +.def 1 +0 0 0 +.names _n3e0<0> continue$raw_n3d3<1> +- =_n3e0<0> +# assign continue [2] = button_above [2] && direction [2] == UP || button_below [2] && direction [2] == DOWN +.names _n3e3<0> +0 +.names _n3e3<1> +1 +.mv _n3e4 2 UP DOWN +.names direction<*1*> direction<*2*> _n3e3<1> _n3e3<0> _n3e4 +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n3e5 2 UP DOWN +.names _n3e5 +UP +# direction [2] == 0 +.names _n3e4 _n3e5 _n3e2 +.def 0 +- =_n3e4 1 +# button_above [2] && direction [2] == 0 +.names button_above<2> _n3e2 _n3e6<2> +.def 0 +1 1 1 +.names _n3e7 +0 +.names _n3e9<0> +0 +.names _n3e9<1> +1 +.mv _n3ea 2 UP DOWN +.names direction<*1*> direction<*2*> _n3e9<1> _n3e9<0> _n3ea +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n3eb 2 UP DOWN +.names _n3eb +DOWN +# direction [2] == 1 +.names _n3ea _n3eb _n3e8 +.def 0 +- =_n3ea 1 +# button_below [2] && direction [2] == 1 +.names button_below<2> _n3e8 _n3ec<2> +.def 0 +1 1 1 +.names _n3ed +0 +# button_above [2] && direction [2] == 0 || button_below [2] && direction [2] == 1 +.names _n3e6<2> _n3ec<2> _n3ee<0> +.def 1 +0 0 0 +.names _n3ee<0> continue$raw_n3e1<2> +- =_n3ee<0> +# assign stop_next [1] = ((locations [1] != 3 - 1) && (direction [1] == UP )) ? ((up_floor_buttons [locations [1] + 1] == ON ) ? 1 : 0) : (((locations [1] != 0) && (direction [1] == DOWN )) ? ((down_floor_buttons [locations [1] - 1] == ON ) ? 1 : 0) : 0) +.names _n3f1<0> +1 +.names _n3f1<1> +0 +.names locations<*1*><0> locations<*2*><0> _n3f1<1> _n3f1<0> _n3f2<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n3f1<1> _n3f1<0> _n3f2<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n3f3<0> +1 +.names _n3f3<1> +1 +.names _n3f4<0> +1 +.names _n3f4<1> +0 +# 3 - 1 +.names _n3f6 +0 +.names _n3f3<0> _n3f4<0> _n3f6 _n3f5<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n3f8 +0 +.names _n3f3<0> _n3f4<0> _n3f8 _n3f7 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n3f3<1> _n3f4<1> _n3f7 _n3f5<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# locations [1] != 3 - 1 +.names _n3f2<0> _n3f5<0> _n3f9<0> +.def 0 +0 1 1 +1 0 1 +.names _n3f2<1> _n3f5<1> _n3f9<1> +.def 0 +0 1 1 +1 0 1 +.names _n3f9<0> _n3f9<1> _n3fa +.def 1 +0 0 0 +.names _n3fa _n3f0 +- =_n3fa +.names _n3fc<0> +1 +.names _n3fc<1> +0 +.mv _n3fd 2 UP DOWN +.names direction<*1*> direction<*2*> _n3fc<1> _n3fc<0> _n3fd +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n3fe 2 UP DOWN +.names _n3fe +UP +# direction [1] == 0 +.names _n3fd _n3fe _n3fb +.def 0 +- =_n3fd 1 +# (locations [1] != 3 - 1) && (direction [1] == 0) +.names _n3f0 _n3fb _n3ff +.def 0 +1 1 1 +.names _n401<0> +1 +.names _n401<1> +0 +.names locations<*1*><0> locations<*2*><0> _n401<1> _n401<0> _n402<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n401<1> _n401<0> _n402<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n403<0> +1 +.names _n403<1> +0 +# locations [1] + 1 +.names _n405 +0 +.names _n402<0> _n403<0> _n405 _n404<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n407 +0 +.names _n402<0> _n403<0> _n407 _n406 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n402<1> _n403<1> _n406 _n404<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n408 2 ON OFF +.names up_floor_buttons<*0*> up_floor_buttons<*1*> up_floor_buttons<*2*> _n404<1> _n404<0> _n408 +- - - 0 0 =up_floor_buttons<*0*> +- - - 0 1 =up_floor_buttons<*1*> +- - - 1 0 =up_floor_buttons<*2*> +- - - 1 1 ON +.mv _n409 2 ON OFF +.names _n409 +ON +# up_floor_buttons [locations [1] + 1] == 0 +.names _n408 _n409 _n400 +.def 0 +- =_n408 1 +.names _n40a<1> +1 +.names _n40b<1> +0 +# (up_floor_buttons [locations [1] + 1] == 0) ? 1 : 0 +.names _n40a<1> _n40b<1> _n400 _n40c<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n40f<0> +1 +.names _n40f<1> +0 +.names locations<*1*><0> locations<*2*><0> _n40f<1> _n40f<0> _n410<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n40f<1> _n40f<0> _n410<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n411<0> +0 +.names _n411<1> +0 +# locations [1] != 0 +.names _n410<0> _n411<0> _n412<0> +.def 0 +0 1 1 +1 0 1 +.names _n410<1> _n411<1> _n412<1> +.def 0 +0 1 1 +1 0 1 +.names _n412<0> _n412<1> _n413 +.def 1 +0 0 0 +.names _n413 _n40e +- =_n413 +.names _n415<0> +1 +.names _n415<1> +0 +.mv _n416 2 UP DOWN +.names direction<*1*> direction<*2*> _n415<1> _n415<0> _n416 +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n417 2 UP DOWN +.names _n417 +DOWN +# direction [1] == 1 +.names _n416 _n417 _n414 +.def 0 +- =_n416 1 +# (locations [1] != 0) && (direction [1] == 1) +.names _n40e _n414 _n418 +.def 0 +1 1 1 +.names _n41a<0> +1 +.names _n41a<1> +0 +.names locations<*1*><0> locations<*2*><0> _n41a<1> _n41a<0> _n41b<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n41a<1> _n41a<0> _n41b<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n41c<0> +1 +.names _n41c<1> +0 +# locations [1] - 1 +.names _n41e +0 +.names _n41b<0> _n41c<0> _n41e _n41d<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n420 +0 +.names _n41b<0> _n41c<0> _n420 _n41f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n41b<1> _n41c<1> _n41f _n41d<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n421 2 ON OFF +.names down_floor_buttons<*0*> down_floor_buttons<*1*> down_floor_buttons<*2*> _n41d<1> _n41d<0> _n421 +- - - 0 0 =down_floor_buttons<*0*> +- - - 0 1 =down_floor_buttons<*1*> +- - - 1 0 =down_floor_buttons<*2*> +- - - 1 1 ON +.mv _n422 2 ON OFF +.names _n422 +ON +# down_floor_buttons [locations [1] - 1] == 0 +.names _n421 _n422 _n419 +.def 0 +- =_n421 1 +.names _n423<1> +1 +.names _n424<1> +0 +# (down_floor_buttons [locations [1] - 1] == 0) ? 1 : 0 +.names _n423<1> _n424<1> _n419 _n425<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n427<1> +0 +# ((locations [1] != 0) && (direction [1] == 1)) ? ((down_floor_buttons [locations [1] - 1] == 0) ? 1 : 0) : 0 +.names _n425<1> _n427<1> _n418 _n428<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# ((locations [1] != 3 - 1) && (direction [1] == 0)) ? ((up_floor_buttons [locations [1] + 1] == 0) ? 1 : 0) : (((locations [1] != 0) && (direction [1] == 1)) ? ((down_floor_buttons [locations [1] - 1] == 0) ? 1 : 0) : 0) +.names _n40c<1> _n428<1> _n3ff _n42a<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n42a<1> stop_next$raw_n3ef<1> +- =_n42a<1> +# assign stop_next [2] = ((locations [2] != 3 - 1) && (direction [2] == UP )) ? ((up_floor_buttons [locations [2] + 1] == ON ) ? 1 : 0) : (((locations [2] != 0) && (direction [2] == DOWN )) ? ((down_floor_buttons [locations [2] - 1] == ON ) ? 1 : 0) : 0) +.names _n42e<0> +0 +.names _n42e<1> +1 +.names locations<*1*><0> locations<*2*><0> _n42e<1> _n42e<0> _n42f<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n42e<1> _n42e<0> _n42f<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n430<0> +1 +.names _n430<1> +1 +.names _n431<0> +1 +.names _n431<1> +0 +# 3 - 1 +.names _n433 +0 +.names _n430<0> _n431<0> _n433 _n432<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n435 +0 +.names _n430<0> _n431<0> _n435 _n434 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n430<1> _n431<1> _n434 _n432<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# locations [2] != 3 - 1 +.names _n42f<0> _n432<0> _n436<0> +.def 0 +0 1 1 +1 0 1 +.names _n42f<1> _n432<1> _n436<1> +.def 0 +0 1 1 +1 0 1 +.names _n436<0> _n436<1> _n437 +.def 1 +0 0 0 +.names _n437 _n42d +- =_n437 +.names _n439<0> +0 +.names _n439<1> +1 +.mv _n43a 2 UP DOWN +.names direction<*1*> direction<*2*> _n439<1> _n439<0> _n43a +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n43b 2 UP DOWN +.names _n43b +UP +# direction [2] == 0 +.names _n43a _n43b _n438 +.def 0 +- =_n43a 1 +# (locations [2] != 3 - 1) && (direction [2] == 0) +.names _n42d _n438 _n43c +.def 0 +1 1 1 +.names _n43e<0> +0 +.names _n43e<1> +1 +.names locations<*1*><0> locations<*2*><0> _n43e<1> _n43e<0> _n43f<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n43e<1> _n43e<0> _n43f<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n440<0> +1 +.names _n440<1> +0 +# locations [2] + 1 +.names _n442 +0 +.names _n43f<0> _n440<0> _n442 _n441<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n444 +0 +.names _n43f<0> _n440<0> _n444 _n443 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n43f<1> _n440<1> _n443 _n441<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n445 2 ON OFF +.names up_floor_buttons<*0*> up_floor_buttons<*1*> up_floor_buttons<*2*> _n441<1> _n441<0> _n445 +- - - 0 0 =up_floor_buttons<*0*> +- - - 0 1 =up_floor_buttons<*1*> +- - - 1 0 =up_floor_buttons<*2*> +- - - 1 1 ON +.mv _n446 2 ON OFF +.names _n446 +ON +# up_floor_buttons [locations [2] + 1] == 0 +.names _n445 _n446 _n43d +.def 0 +- =_n445 1 +.names _n447<2> +1 +.names _n448<2> +0 +# (up_floor_buttons [locations [2] + 1] == 0) ? 1 : 0 +.names _n447<2> _n448<2> _n43d _n449<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n44c<0> +0 +.names _n44c<1> +1 +.names locations<*1*><0> locations<*2*><0> _n44c<1> _n44c<0> _n44d<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n44c<1> _n44c<0> _n44d<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n44e<0> +0 +.names _n44e<1> +0 +# locations [2] != 0 +.names _n44d<0> _n44e<0> _n44f<0> +.def 0 +0 1 1 +1 0 1 +.names _n44d<1> _n44e<1> _n44f<1> +.def 0 +0 1 1 +1 0 1 +.names _n44f<0> _n44f<1> _n450 +.def 1 +0 0 0 +.names _n450 _n44b +- =_n450 +.names _n452<0> +0 +.names _n452<1> +1 +.mv _n453 2 UP DOWN +.names direction<*1*> direction<*2*> _n452<1> _n452<0> _n453 +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n454 2 UP DOWN +.names _n454 +DOWN +# direction [2] == 1 +.names _n453 _n454 _n451 +.def 0 +- =_n453 1 +# (locations [2] != 0) && (direction [2] == 1) +.names _n44b _n451 _n455 +.def 0 +1 1 1 +.names _n457<0> +0 +.names _n457<1> +1 +.names locations<*1*><0> locations<*2*><0> _n457<1> _n457<0> _n458<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n457<1> _n457<0> _n458<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n459<0> +1 +.names _n459<1> +0 +# locations [2] - 1 +.names _n45b +0 +.names _n458<0> _n459<0> _n45b _n45a<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n45d +0 +.names _n458<0> _n459<0> _n45d _n45c +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n458<1> _n459<1> _n45c _n45a<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n45e 2 ON OFF +.names down_floor_buttons<*0*> down_floor_buttons<*1*> down_floor_buttons<*2*> _n45a<1> _n45a<0> _n45e +- - - 0 0 =down_floor_buttons<*0*> +- - - 0 1 =down_floor_buttons<*1*> +- - - 1 0 =down_floor_buttons<*2*> +- - - 1 1 ON +.mv _n45f 2 ON OFF +.names _n45f +ON +# down_floor_buttons [locations [2] - 1] == 0 +.names _n45e _n45f _n456 +.def 0 +- =_n45e 1 +.names _n460<2> +1 +.names _n461<2> +0 +# (down_floor_buttons [locations [2] - 1] == 0) ? 1 : 0 +.names _n460<2> _n461<2> _n456 _n462<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n464<2> +0 +# ((locations [2] != 0) && (direction [2] == 1)) ? ((down_floor_buttons [locations [2] - 1] == 0) ? 1 : 0) : 0 +.names _n462<2> _n464<2> _n455 _n465<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# ((locations [2] != 3 - 1) && (direction [2] == 0)) ? ((up_floor_buttons [locations [2] + 1] == 0) ? 1 : 0) : (((locations [2] != 0) && (direction [2] == 1)) ? ((down_floor_buttons [locations [2] - 1] == 0) ? 1 : 0) : 0) +.names _n449<2> _n465<2> _n43c _n467<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n467<2> stop_next$raw_n42c<2> +- =_n467<2> +# assign random_up [0] = $NDset ( 0,1 ) +.names -> random_up<0> +0 +1 +# assign random_down [0] = $NDset ( 0,1 ) +.names -> random_down<0> +0 +1 +# assign random_up [1] = $NDset ( 0,1 ) +.names -> random_up<1> +0 +1 +# assign random_down [1] = $NDset ( 0,1 ) +.names -> random_down<1> +0 +1 +# assign random_up [2] = $NDset ( 0,1 ) +.names -> random_up<2> +0 +1 +# assign random_down [2] = $NDset ( 0,1 ) +.names -> random_down<2> +0 +1 +.names random_up<0> _n476 +.def 1 +0 0 +.names _n476 _n475 +- =_n476 +# up_floor_buttons [0] = 0 +.mv up_floor_buttons$random_up_n477$true<*0*> 2 ON OFF +.mv up_floor_buttons$random_up_n477$true<*1*> 2 ON OFF +.mv up_floor_buttons$random_up_n477$true<*2*> 2 ON OFF +.mv _n478 2 ON OFF +.names _n479<0> +0 +.names _n479<1> +0 +.names _n47a<0> +0 +.names _n47a<1> +0 +.names _n47a<0> _n479<0> _n47c<0> +.def 0 +0 1 1 +1 0 1 +.names _n47a<1> _n479<1> _n47c<1> +.def 0 +0 1 1 +1 0 1 +.names _n47c<0> _n47c<1> _n47d +.def 1 +0 0 0 +.names _n47d _n47b +0 1 +1 0 +.names _n478 up_floor_buttons<*0*> _n47b up_floor_buttons$random_up_n477$true<*0*> +- - 0 =up_floor_buttons<*0*> +- - 1 =_n478 +.names _n47e<0> +1 +.names _n47e<1> +0 +.names _n47e<0> _n479<0> _n480<0> +.def 0 +0 1 1 +1 0 1 +.names _n47e<1> _n479<1> _n480<1> +.def 0 +0 1 1 +1 0 1 +.names _n480<0> _n480<1> _n481 +.def 1 +0 0 0 +.names _n481 _n47f +0 1 +1 0 +.names _n478 up_floor_buttons<*1*> _n47f up_floor_buttons$random_up_n477$true<*1*> +- - 0 =up_floor_buttons<*1*> +- - 1 =_n478 +.names _n482<0> +0 +.names _n482<1> +1 +.names _n482<0> _n479<0> _n484<0> +.def 0 +0 1 1 +1 0 1 +.names _n482<1> _n479<1> _n484<1> +.def 0 +0 1 1 +1 0 1 +.names _n484<0> _n484<1> _n485 +.def 1 +0 0 0 +.names _n485 _n483 +0 1 +1 0 +.names _n478 up_floor_buttons<*2*> _n483 up_floor_buttons$random_up_n477$true<*2*> +- - 0 =up_floor_buttons<*2*> +- - 1 =_n478 +.names _n478 +ON +# if/else (random_up [0]) +.mv up_floor_buttons$random_up$raw_n488<*0*> 2 ON OFF +.mv up_floor_buttons$random_up$raw_n488<*1*> 2 ON OFF +.mv up_floor_buttons$random_up$raw_n488<*2*> 2 ON OFF +.names random_up<0> _n489 +.def 1 +0 0 +.names up_floor_buttons$random_up_n477$true<*0*> up_floor_buttons<*0*> _n489 up_floor_buttons$random_up$raw_n488<*0*> +- - 0 =up_floor_buttons<*0*> +- - 1 =up_floor_buttons$random_up_n477$true<*0*> +.names up_floor_buttons$random_up_n477$true<*1*> up_floor_buttons<*1*> _n489 up_floor_buttons$random_up$raw_n488<*1*> +- - 0 =up_floor_buttons<*1*> +- - 1 =up_floor_buttons$random_up_n477$true<*1*> +.names up_floor_buttons$random_up_n477$true<*2*> up_floor_buttons<*2*> _n489 up_floor_buttons$random_up$raw_n488<*2*> +- - 0 =up_floor_buttons<*2*> +- - 1 =up_floor_buttons$random_up_n477$true<*2*> +.names random_down<0> _n48b +.def 1 +0 0 +.names _n48b _n48a +- =_n48b +# down_floor_buttons [0] = 0 +.mv down_floor_buttons$random_down_n48c$true<*0*> 2 ON OFF +.mv down_floor_buttons$random_down_n48c$true<*1*> 2 ON OFF +.mv down_floor_buttons$random_down_n48c$true<*2*> 2 ON OFF +.mv _n48d 2 ON OFF +.names _n48e<0> +0 +.names _n48e<1> +0 +.names _n48f<0> +0 +.names _n48f<1> +0 +.names _n48f<0> _n48e<0> _n491<0> +.def 0 +0 1 1 +1 0 1 +.names _n48f<1> _n48e<1> _n491<1> +.def 0 +0 1 1 +1 0 1 +.names _n491<0> _n491<1> _n492 +.def 1 +0 0 0 +.names _n492 _n490 +0 1 +1 0 +.names _n48d down_floor_buttons<*0*> _n490 down_floor_buttons$random_down_n48c$true<*0*> +- - 0 =down_floor_buttons<*0*> +- - 1 =_n48d +.names _n493<0> +1 +.names _n493<1> +0 +.names _n493<0> _n48e<0> _n495<0> +.def 0 +0 1 1 +1 0 1 +.names _n493<1> _n48e<1> _n495<1> +.def 0 +0 1 1 +1 0 1 +.names _n495<0> _n495<1> _n496 +.def 1 +0 0 0 +.names _n496 _n494 +0 1 +1 0 +.names _n48d down_floor_buttons<*1*> _n494 down_floor_buttons$random_down_n48c$true<*1*> +- - 0 =down_floor_buttons<*1*> +- - 1 =_n48d +.names _n497<0> +0 +.names _n497<1> +1 +.names _n497<0> _n48e<0> _n499<0> +.def 0 +0 1 1 +1 0 1 +.names _n497<1> _n48e<1> _n499<1> +.def 0 +0 1 1 +1 0 1 +.names _n499<0> _n499<1> _n49a +.def 1 +0 0 0 +.names _n49a _n498 +0 1 +1 0 +.names _n48d down_floor_buttons<*2*> _n498 down_floor_buttons$random_down_n48c$true<*2*> +- - 0 =down_floor_buttons<*2*> +- - 1 =_n48d +.names _n48d +ON +# if/else (random_down [0]) +.mv down_floor_buttons$random_down$raw_n49f<*0*> 2 ON OFF +.mv down_floor_buttons$random_down$raw_n49f<*1*> 2 ON OFF +.mv down_floor_buttons$random_down$raw_n49f<*2*> 2 ON OFF +.names random_down<0> _n4a0 +.def 1 +0 0 +.names down_floor_buttons$random_down_n48c$true<*0*> down_floor_buttons<*0*> _n4a0 down_floor_buttons$random_down$raw_n49f<*0*> +- - 0 =down_floor_buttons<*0*> +- - 1 =down_floor_buttons$random_down_n48c$true<*0*> +.names down_floor_buttons$random_down_n48c$true<*1*> down_floor_buttons<*1*> _n4a0 down_floor_buttons$random_down$raw_n49f<*1*> +- - 0 =down_floor_buttons<*1*> +- - 1 =down_floor_buttons$random_down_n48c$true<*1*> +.names down_floor_buttons$random_down_n48c$true<*2*> down_floor_buttons<*2*> _n4a0 down_floor_buttons$random_down$raw_n49f<*2*> +- - 0 =down_floor_buttons<*2*> +- - 1 =down_floor_buttons$random_down_n48c$true<*2*> +.names random_up<1> _n4a4 +.def 1 +0 0 +.names _n4a4 _n4a3 +- =_n4a4 +# up_floor_buttons [1] = 0 +.mv up_floor_buttons$random_up_n4a5$true<*0*> 2 ON OFF +.mv up_floor_buttons$random_up_n4a5$true<*1*> 2 ON OFF +.mv up_floor_buttons$random_up_n4a5$true<*2*> 2 ON OFF +.mv _n4a6 2 ON OFF +.names _n4a7<0> +1 +.names _n4a7<1> +0 +.names _n4a8<0> +0 +.names _n4a8<1> +0 +.names _n4a8<0> _n4a7<0> _n4aa<0> +.def 0 +0 1 1 +1 0 1 +.names _n4a8<1> _n4a7<1> _n4aa<1> +.def 0 +0 1 1 +1 0 1 +.names _n4aa<0> _n4aa<1> _n4ab +.def 1 +0 0 0 +.names _n4ab _n4a9 +0 1 +1 0 +.names _n4a6 up_floor_buttons$random_up$raw_n488<*0*> _n4a9 up_floor_buttons$random_up_n4a5$true<*0*> +- - 0 =up_floor_buttons$random_up$raw_n488<*0*> +- - 1 =_n4a6 +.names _n4ac<0> +1 +.names _n4ac<1> +0 +.names _n4ac<0> _n4a7<0> _n4ae<0> +.def 0 +0 1 1 +1 0 1 +.names _n4ac<1> _n4a7<1> _n4ae<1> +.def 0 +0 1 1 +1 0 1 +.names _n4ae<0> _n4ae<1> _n4af +.def 1 +0 0 0 +.names _n4af _n4ad +0 1 +1 0 +.names _n4a6 up_floor_buttons$random_up$raw_n488<*1*> _n4ad up_floor_buttons$random_up_n4a5$true<*1*> +- - 0 =up_floor_buttons$random_up$raw_n488<*1*> +- - 1 =_n4a6 +.names _n4b0<0> +0 +.names _n4b0<1> +1 +.names _n4b0<0> _n4a7<0> _n4b2<0> +.def 0 +0 1 1 +1 0 1 +.names _n4b0<1> _n4a7<1> _n4b2<1> +.def 0 +0 1 1 +1 0 1 +.names _n4b2<0> _n4b2<1> _n4b3 +.def 1 +0 0 0 +.names _n4b3 _n4b1 +0 1 +1 0 +.names _n4a6 up_floor_buttons$random_up$raw_n488<*2*> _n4b1 up_floor_buttons$random_up_n4a5$true<*2*> +- - 0 =up_floor_buttons$random_up$raw_n488<*2*> +- - 1 =_n4a6 +.names _n4a6 +ON +# if/else (random_up [1]) +.mv up_floor_buttons$random_up$raw_n4b5<*0*> 2 ON OFF +.mv up_floor_buttons$random_up$raw_n4b5<*1*> 2 ON OFF +.mv up_floor_buttons$random_up$raw_n4b5<*2*> 2 ON OFF +.names random_up<1> _n4b6 +.def 1 +0 0 +.names up_floor_buttons$random_up_n4a5$true<*0*> up_floor_buttons$random_up$raw_n488<*0*> _n4b6 up_floor_buttons$random_up$raw_n4b5<*0*> +- - 0 =up_floor_buttons$random_up$raw_n488<*0*> +- - 1 =up_floor_buttons$random_up_n4a5$true<*0*> +.names up_floor_buttons$random_up_n4a5$true<*1*> up_floor_buttons$random_up$raw_n488<*1*> _n4b6 up_floor_buttons$random_up$raw_n4b5<*1*> +- - 0 =up_floor_buttons$random_up$raw_n488<*1*> +- - 1 =up_floor_buttons$random_up_n4a5$true<*1*> +.names up_floor_buttons$random_up_n4a5$true<*2*> up_floor_buttons$random_up$raw_n488<*2*> _n4b6 up_floor_buttons$random_up$raw_n4b5<*2*> +- - 0 =up_floor_buttons$random_up$raw_n488<*2*> +- - 1 =up_floor_buttons$random_up_n4a5$true<*2*> +.names random_down<1> _n4be +.def 1 +0 0 +.names _n4be _n4bd +- =_n4be +# down_floor_buttons [1] = 0 +.mv down_floor_buttons$random_down_n4bf$true<*0*> 2 ON OFF +.mv down_floor_buttons$random_down_n4bf$true<*1*> 2 ON OFF +.mv down_floor_buttons$random_down_n4bf$true<*2*> 2 ON OFF +.mv _n4c0 2 ON OFF +.names _n4c1<0> +1 +.names _n4c1<1> +0 +.names _n4c2<0> +0 +.names _n4c2<1> +0 +.names _n4c2<0> _n4c1<0> _n4c4<0> +.def 0 +0 1 1 +1 0 1 +.names _n4c2<1> _n4c1<1> _n4c4<1> +.def 0 +0 1 1 +1 0 1 +.names _n4c4<0> _n4c4<1> _n4c5 +.def 1 +0 0 0 +.names _n4c5 _n4c3 +0 1 +1 0 +.names _n4c0 down_floor_buttons$random_down$raw_n49f<*0*> _n4c3 down_floor_buttons$random_down_n4bf$true<*0*> +- - 0 =down_floor_buttons$random_down$raw_n49f<*0*> +- - 1 =_n4c0 +.names _n4c6<0> +1 +.names _n4c6<1> +0 +.names _n4c6<0> _n4c1<0> _n4c8<0> +.def 0 +0 1 1 +1 0 1 +.names _n4c6<1> _n4c1<1> _n4c8<1> +.def 0 +0 1 1 +1 0 1 +.names _n4c8<0> _n4c8<1> _n4c9 +.def 1 +0 0 0 +.names _n4c9 _n4c7 +0 1 +1 0 +.names _n4c0 down_floor_buttons$random_down$raw_n49f<*1*> _n4c7 down_floor_buttons$random_down_n4bf$true<*1*> +- - 0 =down_floor_buttons$random_down$raw_n49f<*1*> +- - 1 =_n4c0 +.names _n4ca<0> +0 +.names _n4ca<1> +1 +.names _n4ca<0> _n4c1<0> _n4cc<0> +.def 0 +0 1 1 +1 0 1 +.names _n4ca<1> _n4c1<1> _n4cc<1> +.def 0 +0 1 1 +1 0 1 +.names _n4cc<0> _n4cc<1> _n4cd +.def 1 +0 0 0 +.names _n4cd _n4cb +0 1 +1 0 +.names _n4c0 down_floor_buttons$random_down$raw_n49f<*2*> _n4cb down_floor_buttons$random_down_n4bf$true<*2*> +- - 0 =down_floor_buttons$random_down$raw_n49f<*2*> +- - 1 =_n4c0 +.names _n4c0 +ON +# if/else (random_down [1]) +.mv down_floor_buttons$random_down$raw_n4ce<*0*> 2 ON OFF +.mv down_floor_buttons$random_down$raw_n4ce<*1*> 2 ON OFF +.mv down_floor_buttons$random_down$raw_n4ce<*2*> 2 ON OFF +.names random_down<1> _n4cf +.def 1 +0 0 +.names down_floor_buttons$random_down_n4bf$true<*0*> down_floor_buttons$random_down$raw_n49f<*0*> _n4cf down_floor_buttons$random_down$raw_n4ce<*0*> +- - 0 =down_floor_buttons$random_down$raw_n49f<*0*> +- - 1 =down_floor_buttons$random_down_n4bf$true<*0*> +.names down_floor_buttons$random_down_n4bf$true<*1*> down_floor_buttons$random_down$raw_n49f<*1*> _n4cf down_floor_buttons$random_down$raw_n4ce<*1*> +- - 0 =down_floor_buttons$random_down$raw_n49f<*1*> +- - 1 =down_floor_buttons$random_down_n4bf$true<*1*> +.names down_floor_buttons$random_down_n4bf$true<*2*> down_floor_buttons$random_down$raw_n49f<*2*> _n4cf down_floor_buttons$random_down$raw_n4ce<*2*> +- - 0 =down_floor_buttons$random_down$raw_n49f<*2*> +- - 1 =down_floor_buttons$random_down_n4bf$true<*2*> +.names random_up<2> _n4d8 +.def 1 +0 0 +.names _n4d8 _n4d7 +- =_n4d8 +# up_floor_buttons [2] = 0 +.mv up_floor_buttons$random_up_n4d9$true<*0*> 2 ON OFF +.mv up_floor_buttons$random_up_n4d9$true<*1*> 2 ON OFF +.mv up_floor_buttons$random_up_n4d9$true<*2*> 2 ON OFF +.mv _n4da 2 ON OFF +.names _n4db<0> +0 +.names _n4db<1> +1 +.names _n4dc<0> +0 +.names _n4dc<1> +0 +.names _n4dc<0> _n4db<0> _n4de<0> +.def 0 +0 1 1 +1 0 1 +.names _n4dc<1> _n4db<1> _n4de<1> +.def 0 +0 1 1 +1 0 1 +.names _n4de<0> _n4de<1> _n4df +.def 1 +0 0 0 +.names _n4df _n4dd +0 1 +1 0 +.names _n4da up_floor_buttons$random_up$raw_n4b5<*0*> _n4dd up_floor_buttons$random_up_n4d9$true<*0*> +- - 0 =up_floor_buttons$random_up$raw_n4b5<*0*> +- - 1 =_n4da +.names _n4e0<0> +1 +.names _n4e0<1> +0 +.names _n4e0<0> _n4db<0> _n4e2<0> +.def 0 +0 1 1 +1 0 1 +.names _n4e0<1> _n4db<1> _n4e2<1> +.def 0 +0 1 1 +1 0 1 +.names _n4e2<0> _n4e2<1> _n4e3 +.def 1 +0 0 0 +.names _n4e3 _n4e1 +0 1 +1 0 +.names _n4da up_floor_buttons$random_up$raw_n4b5<*1*> _n4e1 up_floor_buttons$random_up_n4d9$true<*1*> +- - 0 =up_floor_buttons$random_up$raw_n4b5<*1*> +- - 1 =_n4da +.names _n4e4<0> +0 +.names _n4e4<1> +1 +.names _n4e4<0> _n4db<0> _n4e6<0> +.def 0 +0 1 1 +1 0 1 +.names _n4e4<1> _n4db<1> _n4e6<1> +.def 0 +0 1 1 +1 0 1 +.names _n4e6<0> _n4e6<1> _n4e7 +.def 1 +0 0 0 +.names _n4e7 _n4e5 +0 1 +1 0 +.names _n4da up_floor_buttons$random_up$raw_n4b5<*2*> _n4e5 up_floor_buttons$random_up_n4d9$true<*2*> +- - 0 =up_floor_buttons$random_up$raw_n4b5<*2*> +- - 1 =_n4da +.names _n4da +ON +# if/else (random_up [2]) +.mv up_floor_buttons$random_up$raw_n4e9<*0*> 2 ON OFF +.mv up_floor_buttons$random_up$raw_n4e9<*1*> 2 ON OFF +.mv up_floor_buttons$random_up$raw_n4e9<*2*> 2 ON OFF +.names random_up<2> _n4ea +.def 1 +0 0 +.names up_floor_buttons$random_up_n4d9$true<*0*> up_floor_buttons$random_up$raw_n4b5<*0*> _n4ea up_floor_buttons$random_up$raw_n4e9<*0*> +- - 0 =up_floor_buttons$random_up$raw_n4b5<*0*> +- - 1 =up_floor_buttons$random_up_n4d9$true<*0*> +.names up_floor_buttons$random_up_n4d9$true<*1*> up_floor_buttons$random_up$raw_n4b5<*1*> _n4ea up_floor_buttons$random_up$raw_n4e9<*1*> +- - 0 =up_floor_buttons$random_up$raw_n4b5<*1*> +- - 1 =up_floor_buttons$random_up_n4d9$true<*1*> +.names up_floor_buttons$random_up_n4d9$true<*2*> up_floor_buttons$random_up$raw_n4b5<*2*> _n4ea up_floor_buttons$random_up$raw_n4e9<*2*> +- - 0 =up_floor_buttons$random_up$raw_n4b5<*2*> +- - 1 =up_floor_buttons$random_up_n4d9$true<*2*> +.names random_down<2> _n4f2 +.def 1 +0 0 +.names _n4f2 _n4f1 +- =_n4f2 +# down_floor_buttons [2] = 0 +.mv down_floor_buttons$random_down_n4f3$true<*0*> 2 ON OFF +.mv down_floor_buttons$random_down_n4f3$true<*1*> 2 ON OFF +.mv down_floor_buttons$random_down_n4f3$true<*2*> 2 ON OFF +.mv _n4f4 2 ON OFF +.names _n4f5<0> +0 +.names _n4f5<1> +1 +.names _n4f6<0> +0 +.names _n4f6<1> +0 +.names _n4f6<0> _n4f5<0> _n4f8<0> +.def 0 +0 1 1 +1 0 1 +.names _n4f6<1> _n4f5<1> _n4f8<1> +.def 0 +0 1 1 +1 0 1 +.names _n4f8<0> _n4f8<1> _n4f9 +.def 1 +0 0 0 +.names _n4f9 _n4f7 +0 1 +1 0 +.names _n4f4 down_floor_buttons$random_down$raw_n4ce<*0*> _n4f7 down_floor_buttons$random_down_n4f3$true<*0*> +- - 0 =down_floor_buttons$random_down$raw_n4ce<*0*> +- - 1 =_n4f4 +.names _n4fa<0> +1 +.names _n4fa<1> +0 +.names _n4fa<0> _n4f5<0> _n4fc<0> +.def 0 +0 1 1 +1 0 1 +.names _n4fa<1> _n4f5<1> _n4fc<1> +.def 0 +0 1 1 +1 0 1 +.names _n4fc<0> _n4fc<1> _n4fd +.def 1 +0 0 0 +.names _n4fd _n4fb +0 1 +1 0 +.names _n4f4 down_floor_buttons$random_down$raw_n4ce<*1*> _n4fb down_floor_buttons$random_down_n4f3$true<*1*> +- - 0 =down_floor_buttons$random_down$raw_n4ce<*1*> +- - 1 =_n4f4 +.names _n4fe<0> +0 +.names _n4fe<1> +1 +.names _n4fe<0> _n4f5<0> _n500<0> +.def 0 +0 1 1 +1 0 1 +.names _n4fe<1> _n4f5<1> _n500<1> +.def 0 +0 1 1 +1 0 1 +.names _n500<0> _n500<1> _n501 +.def 1 +0 0 0 +.names _n501 _n4ff +0 1 +1 0 +.names _n4f4 down_floor_buttons$random_down$raw_n4ce<*2*> _n4ff down_floor_buttons$random_down_n4f3$true<*2*> +- - 0 =down_floor_buttons$random_down$raw_n4ce<*2*> +- - 1 =_n4f4 +.names _n4f4 +ON +# if/else (random_down [2]) +.mv down_floor_buttons$random_down$raw_n502<*0*> 2 ON OFF +.mv down_floor_buttons$random_down$raw_n502<*1*> 2 ON OFF +.mv down_floor_buttons$random_down$raw_n502<*2*> 2 ON OFF +.names random_down<2> _n503 +.def 1 +0 0 +.names down_floor_buttons$random_down_n4f3$true<*0*> down_floor_buttons$random_down$raw_n4ce<*0*> _n503 down_floor_buttons$random_down$raw_n502<*0*> +- - 0 =down_floor_buttons$random_down$raw_n4ce<*0*> +- - 1 =down_floor_buttons$random_down_n4f3$true<*0*> +.names down_floor_buttons$random_down_n4f3$true<*1*> down_floor_buttons$random_down$raw_n4ce<*1*> _n503 down_floor_buttons$random_down$raw_n502<*1*> +- - 0 =down_floor_buttons$random_down$raw_n4ce<*1*> +- - 1 =down_floor_buttons$random_down_n4f3$true<*1*> +.names down_floor_buttons$random_down_n4f3$true<*2*> down_floor_buttons$random_down$raw_n4ce<*2*> _n503 down_floor_buttons$random_down$raw_n502<*2*> +- - 0 =down_floor_buttons$random_down$raw_n4ce<*2*> +- - 1 =down_floor_buttons$random_down_n4f3$true<*2*> +.names _n50c<0> +1 +.names _n50c<1> +0 +.names locations<*1*><0> locations<*2*><0> _n50c<1> _n50c<0> _n50d<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n50c<1> _n50c<0> _n50d<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n50e<0> +1 +.names _n50e<1> +1 +.names _n50f<0> +1 +.names _n50f<1> +0 +# 3 - 1 +.names _n511 +0 +.names _n50e<0> _n50f<0> _n511 _n510<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n513 +0 +.names _n50e<0> _n50f<0> _n513 _n512 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n50e<1> _n50f<1> _n512 _n510<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# locations [1] != 3 - 1 +.names _n50d<0> _n510<0> _n514<0> +.def 0 +0 1 1 +1 0 1 +.names _n50d<1> _n510<1> _n514<1> +.def 0 +0 1 1 +1 0 1 +.names _n514<0> _n514<1> _n515 +.def 1 +0 0 0 +.names _n515 _n50b +- =_n515 +.names _n517<0> +1 +.names _n517<1> +0 +.mv _n518 2 UP DOWN +.names direction<*1*> direction<*2*> _n517<1> _n517<0> _n518 +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n519 2 UP DOWN +.names _n519 +UP +# direction [1] == 0 +.names _n518 _n519 _n516 +.def 0 +- =_n518 1 +# (locations [1] != 3 - 1) && (direction [1] == 0) +.names _n50b _n516 _n51a +.def 0 +1 1 1 +.names _n51a _n51b +- =_n51a +.names _n51d<0> +1 +.names _n51d<1> +0 +.names locations<*1*><0> locations<*2*><0> _n51d<1> _n51d<0> _n51e<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n51d<1> _n51d<0> _n51e<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n51f<0> +1 +.names _n51f<1> +0 +# locations [1] + 1 +.names _n521 +0 +.names _n51e<0> _n51f<0> _n521 _n520<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n523 +0 +.names _n51e<0> _n51f<0> _n523 _n522 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n51e<1> _n51f<1> _n522 _n520<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n524 2 ON OFF +.names up_floor_buttons$random_up$raw_n4e9<*0*> up_floor_buttons$random_up$raw_n4e9<*1*> up_floor_buttons$random_up$raw_n4e9<*2*> _n520<1> _n520<0> _n524 +- - - 0 0 =up_floor_buttons$random_up$raw_n4e9<*0*> +- - - 0 1 =up_floor_buttons$random_up$raw_n4e9<*1*> +- - - 1 0 =up_floor_buttons$random_up$raw_n4e9<*2*> +- - - 1 1 ON +.mv _n525 2 ON OFF +.names _n525 +ON +# up_floor_buttons [locations [1] + 1] == 0 +.names _n524 _n525 _n51c +.def 0 +- =_n524 1 +.names _n51c _n526 +- =_n51c +# up_floor_buttons [locations [1] + 1] = 1 +.mv up_floor_buttons$_n51c_n527$true<*0*> 2 ON OFF +.mv up_floor_buttons$_n51c_n527$true<*1*> 2 ON OFF +.mv up_floor_buttons$_n51c_n527$true<*2*> 2 ON OFF +.names _n528<0> +1 +.names _n528<1> +0 +.names locations<*1*><0> locations<*2*><0> _n528<1> _n528<0> _n529<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n528<1> _n528<0> _n529<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n52a<0> +1 +.names _n52a<1> +0 +# locations [1] + 1 +.names _n52c +0 +.names _n529<0> _n52a<0> _n52c _n52b<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n52e +0 +.names _n529<0> _n52a<0> _n52e _n52d +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n529<1> _n52a<1> _n52d _n52b<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n52f 2 ON OFF +.names _n530<0> +0 +.names _n530<1> +0 +.names _n530<0> _n52b<0> _n532<0> +.def 0 +0 1 1 +1 0 1 +.names _n530<1> _n52b<1> _n532<1> +.def 0 +0 1 1 +1 0 1 +.names _n532<0> _n532<1> _n533 +.def 1 +0 0 0 +.names _n533 _n531 +0 1 +1 0 +.names _n52f up_floor_buttons$random_up$raw_n4e9<*0*> _n531 up_floor_buttons$_n51c_n527$true<*0*> +- - 0 =up_floor_buttons$random_up$raw_n4e9<*0*> +- - 1 =_n52f +.names _n534<0> +1 +.names _n534<1> +0 +.names _n534<0> _n52b<0> _n536<0> +.def 0 +0 1 1 +1 0 1 +.names _n534<1> _n52b<1> _n536<1> +.def 0 +0 1 1 +1 0 1 +.names _n536<0> _n536<1> _n537 +.def 1 +0 0 0 +.names _n537 _n535 +0 1 +1 0 +.names _n52f up_floor_buttons$random_up$raw_n4e9<*1*> _n535 up_floor_buttons$_n51c_n527$true<*1*> +- - 0 =up_floor_buttons$random_up$raw_n4e9<*1*> +- - 1 =_n52f +.names _n538<0> +0 +.names _n538<1> +1 +.names _n538<0> _n52b<0> _n53a<0> +.def 0 +0 1 1 +1 0 1 +.names _n538<1> _n52b<1> _n53a<1> +.def 0 +0 1 1 +1 0 1 +.names _n53a<0> _n53a<1> _n53b +.def 1 +0 0 0 +.names _n53b _n539 +0 1 +1 0 +.names _n52f up_floor_buttons$random_up$raw_n4e9<*2*> _n539 up_floor_buttons$_n51c_n527$true<*2*> +- - 0 =up_floor_buttons$random_up$raw_n4e9<*2*> +- - 1 =_n52f +.names _n52f +OFF +# if/else (up_floor_buttons [locations [1] + 1] == 0) +.mv up_floor_buttons$_n51c$raw_n53d<*0*> 2 ON OFF +.mv up_floor_buttons$_n51c$raw_n53d<*1*> 2 ON OFF +.mv up_floor_buttons$_n51c$raw_n53d<*2*> 2 ON OFF +.names up_floor_buttons$_n51c_n527$true<*0*> up_floor_buttons$random_up$raw_n4e9<*0*> _n51c up_floor_buttons$_n51c$raw_n53d<*0*> +- - 0 =up_floor_buttons$random_up$raw_n4e9<*0*> +- - 1 =up_floor_buttons$_n51c_n527$true<*0*> +.names up_floor_buttons$_n51c_n527$true<*1*> up_floor_buttons$random_up$raw_n4e9<*1*> _n51c up_floor_buttons$_n51c$raw_n53d<*1*> +- - 0 =up_floor_buttons$random_up$raw_n4e9<*1*> +- - 1 =up_floor_buttons$_n51c_n527$true<*1*> +.names up_floor_buttons$_n51c_n527$true<*2*> up_floor_buttons$random_up$raw_n4e9<*2*> _n51c up_floor_buttons$_n51c$raw_n53d<*2*> +- - 0 =up_floor_buttons$random_up$raw_n4e9<*2*> +- - 1 =up_floor_buttons$_n51c_n527$true<*2*> +# if/else ((locations [1] != 3 - 1) && (direction [1] == 0)) +.mv up_floor_buttons$_n51a$raw_n545<*0*> 2 ON OFF +.mv up_floor_buttons$_n51a$raw_n545<*1*> 2 ON OFF +.mv up_floor_buttons$_n51a$raw_n545<*2*> 2 ON OFF +.names up_floor_buttons$_n51c$raw_n53d<*0*> up_floor_buttons$random_up$raw_n4e9<*0*> _n51a up_floor_buttons$_n51a$raw_n545<*0*> +- - 0 =up_floor_buttons$random_up$raw_n4e9<*0*> +- - 1 =up_floor_buttons$_n51c$raw_n53d<*0*> +.names up_floor_buttons$_n51c$raw_n53d<*1*> up_floor_buttons$random_up$raw_n4e9<*1*> _n51a up_floor_buttons$_n51a$raw_n545<*1*> +- - 0 =up_floor_buttons$random_up$raw_n4e9<*1*> +- - 1 =up_floor_buttons$_n51c$raw_n53d<*1*> +.names up_floor_buttons$_n51c$raw_n53d<*2*> up_floor_buttons$random_up$raw_n4e9<*2*> _n51a up_floor_buttons$_n51a$raw_n545<*2*> +- - 0 =up_floor_buttons$random_up$raw_n4e9<*2*> +- - 1 =up_floor_buttons$_n51c$raw_n53d<*2*> +.names _n54d<0> +1 +.names _n54d<1> +0 +.names locations<*1*><0> locations<*2*><0> _n54d<1> _n54d<0> _n54e<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n54d<1> _n54d<0> _n54e<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n54f<0> +0 +.names _n54f<1> +0 +# locations [1] != 0 +.names _n54e<0> _n54f<0> _n550<0> +.def 0 +0 1 1 +1 0 1 +.names _n54e<1> _n54f<1> _n550<1> +.def 0 +0 1 1 +1 0 1 +.names _n550<0> _n550<1> _n551 +.def 1 +0 0 0 +.names _n551 _n54c +- =_n551 +.names _n553<0> +1 +.names _n553<1> +0 +.mv _n554 2 UP DOWN +.names direction<*1*> direction<*2*> _n553<1> _n553<0> _n554 +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n555 2 UP DOWN +.names _n555 +DOWN +# direction [1] == 1 +.names _n554 _n555 _n552 +.def 0 +- =_n554 1 +# (locations [1] != 0) && (direction [1] == 1) +.names _n54c _n552 _n556 +.def 0 +1 1 1 +.names _n556 _n557 +- =_n556 +.names _n559<0> +1 +.names _n559<1> +0 +.names locations<*1*><0> locations<*2*><0> _n559<1> _n559<0> _n55a<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n559<1> _n559<0> _n55a<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n55b<0> +1 +.names _n55b<1> +0 +# locations [1] - 1 +.names _n55d +0 +.names _n55a<0> _n55b<0> _n55d _n55c<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n55f +0 +.names _n55a<0> _n55b<0> _n55f _n55e +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n55a<1> _n55b<1> _n55e _n55c<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n560 2 ON OFF +.names down_floor_buttons$random_down$raw_n502<*0*> down_floor_buttons$random_down$raw_n502<*1*> down_floor_buttons$random_down$raw_n502<*2*> _n55c<1> _n55c<0> _n560 +- - - 0 0 =down_floor_buttons$random_down$raw_n502<*0*> +- - - 0 1 =down_floor_buttons$random_down$raw_n502<*1*> +- - - 1 0 =down_floor_buttons$random_down$raw_n502<*2*> +- - - 1 1 ON +.mv _n561 2 ON OFF +.names _n561 +ON +# down_floor_buttons [locations [1] - 1] == 0 +.names _n560 _n561 _n558 +.def 0 +- =_n560 1 +.names _n558 _n562 +- =_n558 +# down_floor_buttons [locations [1] - 1] = 1 +.mv down_floor_buttons$_n558_n563$true<*0*> 2 ON OFF +.mv down_floor_buttons$_n558_n563$true<*1*> 2 ON OFF +.mv down_floor_buttons$_n558_n563$true<*2*> 2 ON OFF +.names _n564<0> +1 +.names _n564<1> +0 +.names locations<*1*><0> locations<*2*><0> _n564<1> _n564<0> _n565<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n564<1> _n564<0> _n565<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n566<0> +1 +.names _n566<1> +0 +# locations [1] - 1 +.names _n568 +0 +.names _n565<0> _n566<0> _n568 _n567<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n56a +0 +.names _n565<0> _n566<0> _n56a _n569 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n565<1> _n566<1> _n569 _n567<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n56b 2 ON OFF +.names _n56c<0> +0 +.names _n56c<1> +0 +.names _n56c<0> _n567<0> _n56e<0> +.def 0 +0 1 1 +1 0 1 +.names _n56c<1> _n567<1> _n56e<1> +.def 0 +0 1 1 +1 0 1 +.names _n56e<0> _n56e<1> _n56f +.def 1 +0 0 0 +.names _n56f _n56d +0 1 +1 0 +.names _n56b down_floor_buttons$random_down$raw_n502<*0*> _n56d down_floor_buttons$_n558_n563$true<*0*> +- - 0 =down_floor_buttons$random_down$raw_n502<*0*> +- - 1 =_n56b +.names _n570<0> +1 +.names _n570<1> +0 +.names _n570<0> _n567<0> _n572<0> +.def 0 +0 1 1 +1 0 1 +.names _n570<1> _n567<1> _n572<1> +.def 0 +0 1 1 +1 0 1 +.names _n572<0> _n572<1> _n573 +.def 1 +0 0 0 +.names _n573 _n571 +0 1 +1 0 +.names _n56b down_floor_buttons$random_down$raw_n502<*1*> _n571 down_floor_buttons$_n558_n563$true<*1*> +- - 0 =down_floor_buttons$random_down$raw_n502<*1*> +- - 1 =_n56b +.names _n574<0> +0 +.names _n574<1> +1 +.names _n574<0> _n567<0> _n576<0> +.def 0 +0 1 1 +1 0 1 +.names _n574<1> _n567<1> _n576<1> +.def 0 +0 1 1 +1 0 1 +.names _n576<0> _n576<1> _n577 +.def 1 +0 0 0 +.names _n577 _n575 +0 1 +1 0 +.names _n56b down_floor_buttons$random_down$raw_n502<*2*> _n575 down_floor_buttons$_n558_n563$true<*2*> +- - 0 =down_floor_buttons$random_down$raw_n502<*2*> +- - 1 =_n56b +.names _n56b +OFF +# if/else (down_floor_buttons [locations [1] - 1] == 0) +.mv down_floor_buttons$_n558$raw_n578<*0*> 2 ON OFF +.mv down_floor_buttons$_n558$raw_n578<*1*> 2 ON OFF +.mv down_floor_buttons$_n558$raw_n578<*2*> 2 ON OFF +.names down_floor_buttons$_n558_n563$true<*0*> down_floor_buttons$random_down$raw_n502<*0*> _n558 down_floor_buttons$_n558$raw_n578<*0*> +- - 0 =down_floor_buttons$random_down$raw_n502<*0*> +- - 1 =down_floor_buttons$_n558_n563$true<*0*> +.names down_floor_buttons$_n558_n563$true<*1*> down_floor_buttons$random_down$raw_n502<*1*> _n558 down_floor_buttons$_n558$raw_n578<*1*> +- - 0 =down_floor_buttons$random_down$raw_n502<*1*> +- - 1 =down_floor_buttons$_n558_n563$true<*1*> +.names down_floor_buttons$_n558_n563$true<*2*> down_floor_buttons$random_down$raw_n502<*2*> _n558 down_floor_buttons$_n558$raw_n578<*2*> +- - 0 =down_floor_buttons$random_down$raw_n502<*2*> +- - 1 =down_floor_buttons$_n558_n563$true<*2*> +# if/else ((locations [1] != 0) && (direction [1] == 1)) +.mv down_floor_buttons$_n556$raw_n580<*0*> 2 ON OFF +.mv down_floor_buttons$_n556$raw_n580<*1*> 2 ON OFF +.mv down_floor_buttons$_n556$raw_n580<*2*> 2 ON OFF +.names down_floor_buttons$_n558$raw_n578<*0*> down_floor_buttons$random_down$raw_n502<*0*> _n556 down_floor_buttons$_n556$raw_n580<*0*> +- - 0 =down_floor_buttons$random_down$raw_n502<*0*> +- - 1 =down_floor_buttons$_n558$raw_n578<*0*> +.names down_floor_buttons$_n558$raw_n578<*1*> down_floor_buttons$random_down$raw_n502<*1*> _n556 down_floor_buttons$_n556$raw_n580<*1*> +- - 0 =down_floor_buttons$random_down$raw_n502<*1*> +- - 1 =down_floor_buttons$_n558$raw_n578<*1*> +.names down_floor_buttons$_n558$raw_n578<*2*> down_floor_buttons$random_down$raw_n502<*2*> _n556 down_floor_buttons$_n556$raw_n580<*2*> +- - 0 =down_floor_buttons$random_down$raw_n502<*2*> +- - 1 =down_floor_buttons$_n558$raw_n578<*2*> +.names _n589<0> +0 +.names _n589<1> +1 +.names locations<*1*><0> locations<*2*><0> _n589<1> _n589<0> _n58a<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n589<1> _n589<0> _n58a<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n58b<0> +1 +.names _n58b<1> +1 +.names _n58c<0> +1 +.names _n58c<1> +0 +# 3 - 1 +.names _n58e +0 +.names _n58b<0> _n58c<0> _n58e _n58d<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n590 +0 +.names _n58b<0> _n58c<0> _n590 _n58f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n58b<1> _n58c<1> _n58f _n58d<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# locations [2] != 3 - 1 +.names _n58a<0> _n58d<0> _n591<0> +.def 0 +0 1 1 +1 0 1 +.names _n58a<1> _n58d<1> _n591<1> +.def 0 +0 1 1 +1 0 1 +.names _n591<0> _n591<1> _n592 +.def 1 +0 0 0 +.names _n592 _n588 +- =_n592 +.names _n594<0> +0 +.names _n594<1> +1 +.mv _n595 2 UP DOWN +.names direction<*1*> direction<*2*> _n594<1> _n594<0> _n595 +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n596 2 UP DOWN +.names _n596 +UP +# direction [2] == 0 +.names _n595 _n596 _n593 +.def 0 +- =_n595 1 +# (locations [2] != 3 - 1) && (direction [2] == 0) +.names _n588 _n593 _n597 +.def 0 +1 1 1 +.names _n597 _n598 +- =_n597 +.names _n59a<0> +0 +.names _n59a<1> +1 +.names locations<*1*><0> locations<*2*><0> _n59a<1> _n59a<0> _n59b<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n59a<1> _n59a<0> _n59b<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n59c<0> +1 +.names _n59c<1> +0 +# locations [2] + 1 +.names _n59e +0 +.names _n59b<0> _n59c<0> _n59e _n59d<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n5a0 +0 +.names _n59b<0> _n59c<0> _n5a0 _n59f +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n59b<1> _n59c<1> _n59f _n59d<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n5a1 2 ON OFF +.names up_floor_buttons$_n51a$raw_n545<*0*> up_floor_buttons$_n51a$raw_n545<*1*> up_floor_buttons$_n51a$raw_n545<*2*> _n59d<1> _n59d<0> _n5a1 +- - - 0 0 =up_floor_buttons$_n51a$raw_n545<*0*> +- - - 0 1 =up_floor_buttons$_n51a$raw_n545<*1*> +- - - 1 0 =up_floor_buttons$_n51a$raw_n545<*2*> +- - - 1 1 ON +.mv _n5a2 2 ON OFF +.names _n5a2 +ON +# up_floor_buttons [locations [2] + 1] == 0 +.names _n5a1 _n5a2 _n599 +.def 0 +- =_n5a1 1 +.names _n599 _n5a3 +- =_n599 +# up_floor_buttons [locations [2] + 1] = 1 +.mv up_floor_buttons$_n599_n5a4$true<*0*> 2 ON OFF +.mv up_floor_buttons$_n599_n5a4$true<*1*> 2 ON OFF +.mv up_floor_buttons$_n599_n5a4$true<*2*> 2 ON OFF +.names _n5a5<0> +0 +.names _n5a5<1> +1 +.names locations<*1*><0> locations<*2*><0> _n5a5<1> _n5a5<0> _n5a6<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n5a5<1> _n5a5<0> _n5a6<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n5a7<0> +1 +.names _n5a7<1> +0 +# locations [2] + 1 +.names _n5a9 +0 +.names _n5a6<0> _n5a7<0> _n5a9 _n5a8<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n5ab +0 +.names _n5a6<0> _n5a7<0> _n5ab _n5aa +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n5a6<1> _n5a7<1> _n5aa _n5a8<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n5ac 2 ON OFF +.names _n5ad<0> +0 +.names _n5ad<1> +0 +.names _n5ad<0> _n5a8<0> _n5af<0> +.def 0 +0 1 1 +1 0 1 +.names _n5ad<1> _n5a8<1> _n5af<1> +.def 0 +0 1 1 +1 0 1 +.names _n5af<0> _n5af<1> _n5b0 +.def 1 +0 0 0 +.names _n5b0 _n5ae +0 1 +1 0 +.names _n5ac up_floor_buttons$_n51a$raw_n545<*0*> _n5ae up_floor_buttons$_n599_n5a4$true<*0*> +- - 0 =up_floor_buttons$_n51a$raw_n545<*0*> +- - 1 =_n5ac +.names _n5b1<0> +1 +.names _n5b1<1> +0 +.names _n5b1<0> _n5a8<0> _n5b3<0> +.def 0 +0 1 1 +1 0 1 +.names _n5b1<1> _n5a8<1> _n5b3<1> +.def 0 +0 1 1 +1 0 1 +.names _n5b3<0> _n5b3<1> _n5b4 +.def 1 +0 0 0 +.names _n5b4 _n5b2 +0 1 +1 0 +.names _n5ac up_floor_buttons$_n51a$raw_n545<*1*> _n5b2 up_floor_buttons$_n599_n5a4$true<*1*> +- - 0 =up_floor_buttons$_n51a$raw_n545<*1*> +- - 1 =_n5ac +.names _n5b5<0> +0 +.names _n5b5<1> +1 +.names _n5b5<0> _n5a8<0> _n5b7<0> +.def 0 +0 1 1 +1 0 1 +.names _n5b5<1> _n5a8<1> _n5b7<1> +.def 0 +0 1 1 +1 0 1 +.names _n5b7<0> _n5b7<1> _n5b8 +.def 1 +0 0 0 +.names _n5b8 _n5b6 +0 1 +1 0 +.names _n5ac up_floor_buttons$_n51a$raw_n545<*2*> _n5b6 up_floor_buttons$_n599_n5a4$true<*2*> +- - 0 =up_floor_buttons$_n51a$raw_n545<*2*> +- - 1 =_n5ac +.names _n5ac +OFF +# if/else (up_floor_buttons [locations [2] + 1] == 0) +.mv up_floor_buttons$_n599$raw_n5ba<*0*> 2 ON OFF +.mv up_floor_buttons$_n599$raw_n5ba<*1*> 2 ON OFF +.mv up_floor_buttons$_n599$raw_n5ba<*2*> 2 ON OFF +.names up_floor_buttons$_n599_n5a4$true<*0*> up_floor_buttons$_n51a$raw_n545<*0*> _n599 up_floor_buttons$_n599$raw_n5ba<*0*> +- - 0 =up_floor_buttons$_n51a$raw_n545<*0*> +- - 1 =up_floor_buttons$_n599_n5a4$true<*0*> +.names up_floor_buttons$_n599_n5a4$true<*1*> up_floor_buttons$_n51a$raw_n545<*1*> _n599 up_floor_buttons$_n599$raw_n5ba<*1*> +- - 0 =up_floor_buttons$_n51a$raw_n545<*1*> +- - 1 =up_floor_buttons$_n599_n5a4$true<*1*> +.names up_floor_buttons$_n599_n5a4$true<*2*> up_floor_buttons$_n51a$raw_n545<*2*> _n599 up_floor_buttons$_n599$raw_n5ba<*2*> +- - 0 =up_floor_buttons$_n51a$raw_n545<*2*> +- - 1 =up_floor_buttons$_n599_n5a4$true<*2*> +# if/else ((locations [2] != 3 - 1) && (direction [2] == 0)) +.mv up_floor_buttons$_n597$raw_n5c2<*0*> 2 ON OFF +.mv up_floor_buttons$_n597$raw_n5c2<*1*> 2 ON OFF +.mv up_floor_buttons$_n597$raw_n5c2<*2*> 2 ON OFF +.names up_floor_buttons$_n599$raw_n5ba<*0*> up_floor_buttons$_n51a$raw_n545<*0*> _n597 up_floor_buttons$_n597$raw_n5c2<*0*> +- - 0 =up_floor_buttons$_n51a$raw_n545<*0*> +- - 1 =up_floor_buttons$_n599$raw_n5ba<*0*> +.names up_floor_buttons$_n599$raw_n5ba<*1*> up_floor_buttons$_n51a$raw_n545<*1*> _n597 up_floor_buttons$_n597$raw_n5c2<*1*> +- - 0 =up_floor_buttons$_n51a$raw_n545<*1*> +- - 1 =up_floor_buttons$_n599$raw_n5ba<*1*> +.names up_floor_buttons$_n599$raw_n5ba<*2*> up_floor_buttons$_n51a$raw_n545<*2*> _n597 up_floor_buttons$_n597$raw_n5c2<*2*> +- - 0 =up_floor_buttons$_n51a$raw_n545<*2*> +- - 1 =up_floor_buttons$_n599$raw_n5ba<*2*> +.names _n5ca<0> +0 +.names _n5ca<1> +1 +.names locations<*1*><0> locations<*2*><0> _n5ca<1> _n5ca<0> _n5cb<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n5ca<1> _n5ca<0> _n5cb<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n5cc<0> +0 +.names _n5cc<1> +0 +# locations [2] != 0 +.names _n5cb<0> _n5cc<0> _n5cd<0> +.def 0 +0 1 1 +1 0 1 +.names _n5cb<1> _n5cc<1> _n5cd<1> +.def 0 +0 1 1 +1 0 1 +.names _n5cd<0> _n5cd<1> _n5ce +.def 1 +0 0 0 +.names _n5ce _n5c9 +- =_n5ce +.names _n5d0<0> +0 +.names _n5d0<1> +1 +.mv _n5d1 2 UP DOWN +.names direction<*1*> direction<*2*> _n5d0<1> _n5d0<0> _n5d1 +- - 0 0 UP +- - 0 1 =direction<*1*> +- - 1 0 =direction<*2*> +- - 1 1 UP +.mv _n5d2 2 UP DOWN +.names _n5d2 +DOWN +# direction [2] == 1 +.names _n5d1 _n5d2 _n5cf +.def 0 +- =_n5d1 1 +# (locations [2] != 0) && (direction [2] == 1) +.names _n5c9 _n5cf _n5d3 +.def 0 +1 1 1 +.names _n5d3 _n5d4 +- =_n5d3 +.names _n5d6<0> +0 +.names _n5d6<1> +1 +.names locations<*1*><0> locations<*2*><0> _n5d6<1> _n5d6<0> _n5d7<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n5d6<1> _n5d6<0> _n5d7<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n5d8<0> +1 +.names _n5d8<1> +0 +# locations [2] - 1 +.names _n5da +0 +.names _n5d7<0> _n5d8<0> _n5da _n5d9<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n5dc +0 +.names _n5d7<0> _n5d8<0> _n5dc _n5db +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n5d7<1> _n5d8<1> _n5db _n5d9<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n5dd 2 ON OFF +.names down_floor_buttons$_n556$raw_n580<*0*> down_floor_buttons$_n556$raw_n580<*1*> down_floor_buttons$_n556$raw_n580<*2*> _n5d9<1> _n5d9<0> _n5dd +- - - 0 0 =down_floor_buttons$_n556$raw_n580<*0*> +- - - 0 1 =down_floor_buttons$_n556$raw_n580<*1*> +- - - 1 0 =down_floor_buttons$_n556$raw_n580<*2*> +- - - 1 1 ON +.mv _n5de 2 ON OFF +.names _n5de +ON +# down_floor_buttons [locations [2] - 1] == 0 +.names _n5dd _n5de _n5d5 +.def 0 +- =_n5dd 1 +.names _n5d5 _n5df +- =_n5d5 +# down_floor_buttons [locations [2] - 1] = 1 +.mv down_floor_buttons$_n5d5_n5e0$true<*0*> 2 ON OFF +.mv down_floor_buttons$_n5d5_n5e0$true<*1*> 2 ON OFF +.mv down_floor_buttons$_n5d5_n5e0$true<*2*> 2 ON OFF +.names _n5e1<0> +0 +.names _n5e1<1> +1 +.names locations<*1*><0> locations<*2*><0> _n5e1<1> _n5e1<0> _n5e2<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n5e1<1> _n5e1<0> _n5e2<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n5e3<0> +1 +.names _n5e3<1> +0 +# locations [2] - 1 +.names _n5e5 +0 +.names _n5e2<0> _n5e3<0> _n5e5 _n5e4<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n5e7 +0 +.names _n5e2<0> _n5e3<0> _n5e7 _n5e6 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n5e2<1> _n5e3<1> _n5e6 _n5e4<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.mv _n5e8 2 ON OFF +.names _n5e9<0> +0 +.names _n5e9<1> +0 +.names _n5e9<0> _n5e4<0> _n5eb<0> +.def 0 +0 1 1 +1 0 1 +.names _n5e9<1> _n5e4<1> _n5eb<1> +.def 0 +0 1 1 +1 0 1 +.names _n5eb<0> _n5eb<1> _n5ec +.def 1 +0 0 0 +.names _n5ec _n5ea +0 1 +1 0 +.names _n5e8 down_floor_buttons$_n556$raw_n580<*0*> _n5ea down_floor_buttons$_n5d5_n5e0$true<*0*> +- - 0 =down_floor_buttons$_n556$raw_n580<*0*> +- - 1 =_n5e8 +.names _n5ed<0> +1 +.names _n5ed<1> +0 +.names _n5ed<0> _n5e4<0> _n5ef<0> +.def 0 +0 1 1 +1 0 1 +.names _n5ed<1> _n5e4<1> _n5ef<1> +.def 0 +0 1 1 +1 0 1 +.names _n5ef<0> _n5ef<1> _n5f0 +.def 1 +0 0 0 +.names _n5f0 _n5ee +0 1 +1 0 +.names _n5e8 down_floor_buttons$_n556$raw_n580<*1*> _n5ee down_floor_buttons$_n5d5_n5e0$true<*1*> +- - 0 =down_floor_buttons$_n556$raw_n580<*1*> +- - 1 =_n5e8 +.names _n5f1<0> +0 +.names _n5f1<1> +1 +.names _n5f1<0> _n5e4<0> _n5f3<0> +.def 0 +0 1 1 +1 0 1 +.names _n5f1<1> _n5e4<1> _n5f3<1> +.def 0 +0 1 1 +1 0 1 +.names _n5f3<0> _n5f3<1> _n5f4 +.def 1 +0 0 0 +.names _n5f4 _n5f2 +0 1 +1 0 +.names _n5e8 down_floor_buttons$_n556$raw_n580<*2*> _n5f2 down_floor_buttons$_n5d5_n5e0$true<*2*> +- - 0 =down_floor_buttons$_n556$raw_n580<*2*> +- - 1 =_n5e8 +.names _n5e8 +OFF +# if/else (down_floor_buttons [locations [2] - 1] == 0) +.mv down_floor_buttons$_n5d5$raw_n5f5<*0*> 2 ON OFF +.mv down_floor_buttons$_n5d5$raw_n5f5<*1*> 2 ON OFF +.mv down_floor_buttons$_n5d5$raw_n5f5<*2*> 2 ON OFF +.names down_floor_buttons$_n5d5_n5e0$true<*0*> down_floor_buttons$_n556$raw_n580<*0*> _n5d5 down_floor_buttons$_n5d5$raw_n5f5<*0*> +- - 0 =down_floor_buttons$_n556$raw_n580<*0*> +- - 1 =down_floor_buttons$_n5d5_n5e0$true<*0*> +.names down_floor_buttons$_n5d5_n5e0$true<*1*> down_floor_buttons$_n556$raw_n580<*1*> _n5d5 down_floor_buttons$_n5d5$raw_n5f5<*1*> +- - 0 =down_floor_buttons$_n556$raw_n580<*1*> +- - 1 =down_floor_buttons$_n5d5_n5e0$true<*1*> +.names down_floor_buttons$_n5d5_n5e0$true<*2*> down_floor_buttons$_n556$raw_n580<*2*> _n5d5 down_floor_buttons$_n5d5$raw_n5f5<*2*> +- - 0 =down_floor_buttons$_n556$raw_n580<*2*> +- - 1 =down_floor_buttons$_n5d5_n5e0$true<*2*> +# if/else ((locations [2] != 0) && (direction [2] == 1)) +.mv down_floor_buttons$_n5d3$raw_n5fd<*0*> 2 ON OFF +.mv down_floor_buttons$_n5d3$raw_n5fd<*1*> 2 ON OFF +.mv down_floor_buttons$_n5d3$raw_n5fd<*2*> 2 ON OFF +.names down_floor_buttons$_n5d5$raw_n5f5<*0*> down_floor_buttons$_n556$raw_n580<*0*> _n5d3 down_floor_buttons$_n5d3$raw_n5fd<*0*> +- - 0 =down_floor_buttons$_n556$raw_n580<*0*> +- - 1 =down_floor_buttons$_n5d5$raw_n5f5<*0*> +.names down_floor_buttons$_n5d5$raw_n5f5<*1*> down_floor_buttons$_n556$raw_n580<*1*> _n5d3 down_floor_buttons$_n5d3$raw_n5fd<*1*> +- - 0 =down_floor_buttons$_n556$raw_n580<*1*> +- - 1 =down_floor_buttons$_n5d5$raw_n5f5<*1*> +.names down_floor_buttons$_n5d5$raw_n5f5<*2*> down_floor_buttons$_n556$raw_n580<*2*> _n5d3 down_floor_buttons$_n5d3$raw_n5fd<*2*> +- - 0 =down_floor_buttons$_n556$raw_n580<*2*> +- - 1 =down_floor_buttons$_n5d5$raw_n5f5<*2*> +.names _n606<0> +1 +.names _n606<1> +0 +.names locations<*1*><0> locations<*2*><0> _n606<1> _n606<0> _n607<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n606<1> _n606<0> _n607<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n608<0> +1 +.names _n608<1> +1 +.names _n609<0> +1 +.names _n609<1> +0 +# 3 - 1 +.names _n60b +0 +.names _n608<0> _n609<0> _n60b _n60a<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n60d +0 +.names _n608<0> _n609<0> _n60d _n60c +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n608<1> _n609<1> _n60c _n60a<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# locations [1] == 3 - 1 +.names _n607<0> _n60a<0> _n60e<0> +.def 0 +0 1 1 +1 0 1 +.names _n607<1> _n60a<1> _n60e<1> +.def 0 +0 1 1 +1 0 1 +.names _n60e<0> _n60e<1> _n60f +.def 1 +0 0 0 +.names _n60f _n605 +0 1 +1 0 +.names _n605 _n610 +- =_n605 +# direction [1] = 1 +.mv direction$_n605_n611$true<*1*> 2 UP DOWN +.mv direction$_n605_n611$true<*2*> 2 UP DOWN +.mv _n612 2 UP DOWN +.names _n613<0> +1 +.names _n613<1> +0 +.names _n614<0> +1 +.names _n614<1> +0 +.names _n614<0> _n613<0> _n616<0> +.def 0 +0 1 1 +1 0 1 +.names _n614<1> _n613<1> _n616<1> +.def 0 +0 1 1 +1 0 1 +.names _n616<0> _n616<1> _n617 +.def 1 +0 0 0 +.names _n617 _n615 +0 1 +1 0 +.names _n612 direction<*1*> _n615 direction$_n605_n611$true<*1*> +- - 0 =direction<*1*> +- - 1 =_n612 +.names _n618<0> +0 +.names _n618<1> +1 +.names _n618<0> _n613<0> _n61a<0> +.def 0 +0 1 1 +1 0 1 +.names _n618<1> _n613<1> _n61a<1> +.def 0 +0 1 1 +1 0 1 +.names _n61a<0> _n61a<1> _n61b +.def 1 +0 0 0 +.names _n61b _n619 +0 1 +1 0 +.names _n612 direction<*2*> _n619 direction$_n605_n611$true<*2*> +- - 0 =direction<*2*> +- - 1 =_n612 +.names _n612 +DOWN +# if/else (locations [1] == 3 - 1) +.mv direction$_n605$raw_n61e<*1*> 2 UP DOWN +.mv direction$_n605$raw_n61e<*2*> 2 UP DOWN +.names direction$_n605_n611$true<*1*> direction<*1*> _n605 direction$_n605$raw_n61e<*1*> +- - 0 =direction<*1*> +- - 1 =direction$_n605_n611$true<*1*> +.names direction$_n605_n611$true<*2*> direction<*2*> _n605 direction$_n605$raw_n61e<*2*> +- - 0 =direction<*2*> +- - 1 =direction$_n605_n611$true<*2*> +.names _n620<0> +1 +.names _n620<1> +0 +.names locations<*1*><0> locations<*2*><0> _n620<1> _n620<0> _n621<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n620<1> _n620<0> _n621<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n622<0> +0 +.names _n622<1> +0 +# locations [1] == 0 +.names _n621<0> _n622<0> _n623<0> +.def 0 +0 1 1 +1 0 1 +.names _n621<1> _n622<1> _n623<1> +.def 0 +0 1 1 +1 0 1 +.names _n623<0> _n623<1> _n624 +.def 1 +0 0 0 +.names _n624 _n61f +0 1 +1 0 +.names _n61f _n625 +- =_n61f +# direction [1] = 0 +.mv direction$_n61f_n626$true<*1*> 2 UP DOWN +.mv direction$_n61f_n626$true<*2*> 2 UP DOWN +.mv _n627 2 UP DOWN +.names _n628<0> +1 +.names _n628<1> +0 +.names _n629<0> +1 +.names _n629<1> +0 +.names _n629<0> _n628<0> _n62b<0> +.def 0 +0 1 1 +1 0 1 +.names _n629<1> _n628<1> _n62b<1> +.def 0 +0 1 1 +1 0 1 +.names _n62b<0> _n62b<1> _n62c +.def 1 +0 0 0 +.names _n62c _n62a +0 1 +1 0 +.names _n627 direction$_n605$raw_n61e<*1*> _n62a direction$_n61f_n626$true<*1*> +- - 0 =direction$_n605$raw_n61e<*1*> +- - 1 =_n627 +.names _n62d<0> +0 +.names _n62d<1> +1 +.names _n62d<0> _n628<0> _n62f<0> +.def 0 +0 1 1 +1 0 1 +.names _n62d<1> _n628<1> _n62f<1> +.def 0 +0 1 1 +1 0 1 +.names _n62f<0> _n62f<1> _n630 +.def 1 +0 0 0 +.names _n630 _n62e +0 1 +1 0 +.names _n627 direction$_n605$raw_n61e<*2*> _n62e direction$_n61f_n626$true<*2*> +- - 0 =direction$_n605$raw_n61e<*2*> +- - 1 =_n627 +.names _n627 +UP +# if/else (locations [1] == 0) +.mv direction$_n61f$raw_n631<*1*> 2 UP DOWN +.mv direction$_n61f$raw_n631<*2*> 2 UP DOWN +.names direction$_n61f_n626$true<*1*> direction$_n605$raw_n61e<*1*> _n61f direction$_n61f$raw_n631<*1*> +- - 0 =direction$_n605$raw_n61e<*1*> +- - 1 =direction$_n61f_n626$true<*1*> +.names direction$_n61f_n626$true<*2*> direction$_n605$raw_n61e<*2*> _n61f direction$_n61f$raw_n631<*2*> +- - 0 =direction$_n605$raw_n61e<*2*> +- - 1 =direction$_n61f_n626$true<*2*> +.names inc<1> _n636 +.def 1 +0 0 +.names _n636 _n635 +- =_n636 +# locations [1] = locations [1] + 1 +.names _n639<0> +1 +.names _n639<1> +0 +.names _n63a<0> +1 +.names _n63a<1> +0 +.names _n63a<0> _n639<0> _n63c<0> +.def 0 +0 1 1 +1 0 1 +.names _n63a<1> _n639<1> _n63c<1> +.def 0 +0 1 1 +1 0 1 +.names _n63c<0> _n63c<1> _n63d +.def 1 +0 0 0 +.names _n63d _n63b +0 1 +1 0 +.names _n638<0> locations<*1*><0> _n63b locations$inc_n637$true<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n638<1> locations<*1*><1> _n63b locations$inc_n637$true<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n640<0> +0 +.names _n640<1> +1 +.names _n640<0> _n639<0> _n642<0> +.def 0 +0 1 1 +1 0 1 +.names _n640<1> _n639<1> _n642<1> +.def 0 +0 1 1 +1 0 1 +.names _n642<0> _n642<1> _n643 +.def 1 +0 0 0 +.names _n643 _n641 +0 1 +1 0 +.names _n638<0> locations<*2*><0> _n641 locations$inc_n637$true<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n638<1> locations<*2*><1> _n641 locations$inc_n637$true<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n646<0> +1 +.names _n646<1> +0 +.names locations<*1*><0> locations<*2*><0> _n646<1> _n646<0> _n647<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations<*1*><1> locations<*2*><1> _n646<1> _n646<0> _n647<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n648<0> +1 +.names _n648<1> +0 +# locations [1] + 1 +.names _n64a +0 +.names _n647<0> _n648<0> _n64a _n649<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n64c +0 +.names _n647<0> _n648<0> _n64c _n64b +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n647<1> _n648<1> _n64b _n649<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n649<0> _n638<0> +- =_n649<0> +.names _n649<1> _n638<1> +- =_n649<1> +# direction [1] = 0 +.mv direction$inc_n64d$true<*1*> 2 UP DOWN +.mv direction$inc_n64d$true<*2*> 2 UP DOWN +.mv _n64e 2 UP DOWN +.names _n64f<0> +1 +.names _n64f<1> +0 +.names _n650<0> +1 +.names _n650<1> +0 +.names _n650<0> _n64f<0> _n652<0> +.def 0 +0 1 1 +1 0 1 +.names _n650<1> _n64f<1> _n652<1> +.def 0 +0 1 1 +1 0 1 +.names _n652<0> _n652<1> _n653 +.def 1 +0 0 0 +.names _n653 _n651 +0 1 +1 0 +.names _n64e direction$_n61f$raw_n631<*1*> _n651 direction$inc_n64d$true<*1*> +- - 0 =direction$_n61f$raw_n631<*1*> +- - 1 =_n64e +.names _n654<0> +0 +.names _n654<1> +1 +.names _n654<0> _n64f<0> _n656<0> +.def 0 +0 1 1 +1 0 1 +.names _n654<1> _n64f<1> _n656<1> +.def 0 +0 1 1 +1 0 1 +.names _n656<0> _n656<1> _n657 +.def 1 +0 0 0 +.names _n657 _n655 +0 1 +1 0 +.names _n64e direction$_n61f$raw_n631<*2*> _n655 direction$inc_n64d$true<*2*> +- - 0 =direction$_n61f$raw_n631<*2*> +- - 1 =_n64e +.names _n64e +UP +# if/else (inc [1]) +.mv direction$inc$raw_n658<*1*> 2 UP DOWN +.mv direction$inc$raw_n658<*2*> 2 UP DOWN +.names inc<1> _n659 +.def 1 +0 0 +.names direction$inc_n64d$true<*1*> direction$_n61f$raw_n631<*1*> _n659 direction$inc$raw_n658<*1*> +- - 0 =direction$_n61f$raw_n631<*1*> +- - 1 =direction$inc_n64d$true<*1*> +.names direction$inc_n64d$true<*2*> direction$_n61f$raw_n631<*2*> _n659 direction$inc$raw_n658<*2*> +- - 0 =direction$_n61f$raw_n631<*2*> +- - 1 =direction$inc_n64d$true<*2*> +.names inc<1> _n65f +.def 1 +0 0 +.names locations$inc_n637$true<*1*><0> locations<*1*><0> _n65f locations$inc$raw_n65e<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$inc_n637$true<*1*><1> locations<*1*><1> _n65f locations$inc$raw_n65e<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$inc_n637$true<*2*><0> locations<*2*><0> _n65f locations$inc$raw_n65e<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$inc_n637$true<*2*><1> locations<*2*><1> _n65f locations$inc$raw_n65e<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names dec<1> _n666 +.def 1 +0 0 +.names _n666 _n665 +- =_n666 +# locations [1] = locations [1] - 1 +.names _n669<0> +1 +.names _n669<1> +0 +.names _n66a<0> +1 +.names _n66a<1> +0 +.names _n66a<0> _n669<0> _n66c<0> +.def 0 +0 1 1 +1 0 1 +.names _n66a<1> _n669<1> _n66c<1> +.def 0 +0 1 1 +1 0 1 +.names _n66c<0> _n66c<1> _n66d +.def 1 +0 0 0 +.names _n66d _n66b +0 1 +1 0 +.names _n668<0> locations$inc$raw_n65e<*1*><0> _n66b locations$dec_n667$true<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n668<1> locations$inc$raw_n65e<*1*><1> _n66b locations$dec_n667$true<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n670<0> +0 +.names _n670<1> +1 +.names _n670<0> _n669<0> _n672<0> +.def 0 +0 1 1 +1 0 1 +.names _n670<1> _n669<1> _n672<1> +.def 0 +0 1 1 +1 0 1 +.names _n672<0> _n672<1> _n673 +.def 1 +0 0 0 +.names _n673 _n671 +0 1 +1 0 +.names _n668<0> locations$inc$raw_n65e<*2*><0> _n671 locations$dec_n667$true<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n668<1> locations$inc$raw_n65e<*2*><1> _n671 locations$dec_n667$true<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n676<0> +1 +.names _n676<1> +0 +.names locations$inc$raw_n65e<*1*><0> locations$inc$raw_n65e<*2*><0> _n676<1> _n676<0> _n677<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations$inc$raw_n65e<*1*><1> locations$inc$raw_n65e<*2*><1> _n676<1> _n676<0> _n677<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n678<0> +1 +.names _n678<1> +0 +# locations [1] - 1 +.names _n67a +0 +.names _n677<0> _n678<0> _n67a _n679<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n67c +0 +.names _n677<0> _n678<0> _n67c _n67b +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n677<1> _n678<1> _n67b _n679<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n679<0> _n668<0> +- =_n679<0> +.names _n679<1> _n668<1> +- =_n679<1> +# direction [1] = 1 +.mv direction$dec_n67d$true<*1*> 2 UP DOWN +.mv direction$dec_n67d$true<*2*> 2 UP DOWN +.mv _n67e 2 UP DOWN +.names _n67f<0> +1 +.names _n67f<1> +0 +.names _n680<0> +1 +.names _n680<1> +0 +.names _n680<0> _n67f<0> _n682<0> +.def 0 +0 1 1 +1 0 1 +.names _n680<1> _n67f<1> _n682<1> +.def 0 +0 1 1 +1 0 1 +.names _n682<0> _n682<1> _n683 +.def 1 +0 0 0 +.names _n683 _n681 +0 1 +1 0 +.names _n67e direction$inc$raw_n658<*1*> _n681 direction$dec_n67d$true<*1*> +- - 0 =direction$inc$raw_n658<*1*> +- - 1 =_n67e +.names _n684<0> +0 +.names _n684<1> +1 +.names _n684<0> _n67f<0> _n686<0> +.def 0 +0 1 1 +1 0 1 +.names _n684<1> _n67f<1> _n686<1> +.def 0 +0 1 1 +1 0 1 +.names _n686<0> _n686<1> _n687 +.def 1 +0 0 0 +.names _n687 _n685 +0 1 +1 0 +.names _n67e direction$inc$raw_n658<*2*> _n685 direction$dec_n67d$true<*2*> +- - 0 =direction$inc$raw_n658<*2*> +- - 1 =_n67e +.names _n67e +DOWN +# if/else (dec [1]) +.mv direction$dec$raw_n688<*1*> 2 UP DOWN +.mv direction$dec$raw_n688<*2*> 2 UP DOWN +.names dec<1> _n689 +.def 1 +0 0 +.names direction$dec_n67d$true<*1*> direction$inc$raw_n658<*1*> _n689 direction$dec$raw_n688<*1*> +- - 0 =direction$inc$raw_n658<*1*> +- - 1 =direction$dec_n67d$true<*1*> +.names direction$dec_n67d$true<*2*> direction$inc$raw_n658<*2*> _n689 direction$dec$raw_n688<*2*> +- - 0 =direction$inc$raw_n658<*2*> +- - 1 =direction$dec_n67d$true<*2*> +.names dec<1> _n68b +.def 1 +0 0 +.names locations$dec_n667$true<*1*><0> locations$inc$raw_n65e<*1*><0> _n68b locations$dec$raw_n68a<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$dec_n667$true<*1*><1> locations$inc$raw_n65e<*1*><1> _n68b locations$dec$raw_n68a<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$dec_n667$true<*2*><0> locations$inc$raw_n65e<*2*><0> _n68b locations$dec$raw_n68a<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$dec_n667$true<*2*><1> locations$inc$raw_n65e<*2*><1> _n68b locations$dec$raw_n68a<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n697<0> +0 +.names _n697<1> +1 +.names locations$dec$raw_n68a<*1*><0> locations$dec$raw_n68a<*2*><0> _n697<1> _n697<0> _n698<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations$dec$raw_n68a<*1*><1> locations$dec$raw_n68a<*2*><1> _n697<1> _n697<0> _n698<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n699<0> +1 +.names _n699<1> +1 +.names _n69a<0> +1 +.names _n69a<1> +0 +# 3 - 1 +.names _n69c +0 +.names _n699<0> _n69a<0> _n69c _n69b<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n69e +0 +.names _n699<0> _n69a<0> _n69e _n69d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n699<1> _n69a<1> _n69d _n69b<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# locations [2] == 3 - 1 +.names _n698<0> _n69b<0> _n69f<0> +.def 0 +0 1 1 +1 0 1 +.names _n698<1> _n69b<1> _n69f<1> +.def 0 +0 1 1 +1 0 1 +.names _n69f<0> _n69f<1> _n6a0 +.def 1 +0 0 0 +.names _n6a0 _n696 +0 1 +1 0 +.names _n696 _n6a1 +- =_n696 +# direction [2] = 1 +.mv direction$_n696_n6a2$true<*1*> 2 UP DOWN +.mv direction$_n696_n6a2$true<*2*> 2 UP DOWN +.mv _n6a3 2 UP DOWN +.names _n6a4<0> +0 +.names _n6a4<1> +1 +.names _n6a5<0> +1 +.names _n6a5<1> +0 +.names _n6a5<0> _n6a4<0> _n6a7<0> +.def 0 +0 1 1 +1 0 1 +.names _n6a5<1> _n6a4<1> _n6a7<1> +.def 0 +0 1 1 +1 0 1 +.names _n6a7<0> _n6a7<1> _n6a8 +.def 1 +0 0 0 +.names _n6a8 _n6a6 +0 1 +1 0 +.names _n6a3 direction$dec$raw_n688<*1*> _n6a6 direction$_n696_n6a2$true<*1*> +- - 0 =direction$dec$raw_n688<*1*> +- - 1 =_n6a3 +.names _n6a9<0> +0 +.names _n6a9<1> +1 +.names _n6a9<0> _n6a4<0> _n6ab<0> +.def 0 +0 1 1 +1 0 1 +.names _n6a9<1> _n6a4<1> _n6ab<1> +.def 0 +0 1 1 +1 0 1 +.names _n6ab<0> _n6ab<1> _n6ac +.def 1 +0 0 0 +.names _n6ac _n6aa +0 1 +1 0 +.names _n6a3 direction$dec$raw_n688<*2*> _n6aa direction$_n696_n6a2$true<*2*> +- - 0 =direction$dec$raw_n688<*2*> +- - 1 =_n6a3 +.names _n6a3 +DOWN +# if/else (locations [2] == 3 - 1) +.mv direction$_n696$raw_n6ad<*1*> 2 UP DOWN +.mv direction$_n696$raw_n6ad<*2*> 2 UP DOWN +.names direction$_n696_n6a2$true<*1*> direction$dec$raw_n688<*1*> _n696 direction$_n696$raw_n6ad<*1*> +- - 0 =direction$dec$raw_n688<*1*> +- - 1 =direction$_n696_n6a2$true<*1*> +.names direction$_n696_n6a2$true<*2*> direction$dec$raw_n688<*2*> _n696 direction$_n696$raw_n6ad<*2*> +- - 0 =direction$dec$raw_n688<*2*> +- - 1 =direction$_n696_n6a2$true<*2*> +.names _n6b6<0> +0 +.names _n6b6<1> +1 +.names locations$dec$raw_n68a<*1*><0> locations$dec$raw_n68a<*2*><0> _n6b6<1> _n6b6<0> _n6b7<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations$dec$raw_n68a<*1*><1> locations$dec$raw_n68a<*2*><1> _n6b6<1> _n6b6<0> _n6b7<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n6b8<0> +0 +.names _n6b8<1> +0 +# locations [2] == 0 +.names _n6b7<0> _n6b8<0> _n6b9<0> +.def 0 +0 1 1 +1 0 1 +.names _n6b7<1> _n6b8<1> _n6b9<1> +.def 0 +0 1 1 +1 0 1 +.names _n6b9<0> _n6b9<1> _n6ba +.def 1 +0 0 0 +.names _n6ba _n6b5 +0 1 +1 0 +.names _n6b5 _n6bb +- =_n6b5 +# direction [2] = 0 +.mv direction$_n6b5_n6bc$true<*1*> 2 UP DOWN +.mv direction$_n6b5_n6bc$true<*2*> 2 UP DOWN +.mv _n6bd 2 UP DOWN +.names _n6be<0> +0 +.names _n6be<1> +1 +.names _n6bf<0> +1 +.names _n6bf<1> +0 +.names _n6bf<0> _n6be<0> _n6c1<0> +.def 0 +0 1 1 +1 0 1 +.names _n6bf<1> _n6be<1> _n6c1<1> +.def 0 +0 1 1 +1 0 1 +.names _n6c1<0> _n6c1<1> _n6c2 +.def 1 +0 0 0 +.names _n6c2 _n6c0 +0 1 +1 0 +.names _n6bd direction$_n696$raw_n6ad<*1*> _n6c0 direction$_n6b5_n6bc$true<*1*> +- - 0 =direction$_n696$raw_n6ad<*1*> +- - 1 =_n6bd +.names _n6c3<0> +0 +.names _n6c3<1> +1 +.names _n6c3<0> _n6be<0> _n6c5<0> +.def 0 +0 1 1 +1 0 1 +.names _n6c3<1> _n6be<1> _n6c5<1> +.def 0 +0 1 1 +1 0 1 +.names _n6c5<0> _n6c5<1> _n6c6 +.def 1 +0 0 0 +.names _n6c6 _n6c4 +0 1 +1 0 +.names _n6bd direction$_n696$raw_n6ad<*2*> _n6c4 direction$_n6b5_n6bc$true<*2*> +- - 0 =direction$_n696$raw_n6ad<*2*> +- - 1 =_n6bd +.names _n6bd +UP +# if/else (locations [2] == 0) +.mv direction$_n6b5$raw_n6c7<*1*> 2 UP DOWN +.mv direction$_n6b5$raw_n6c7<*2*> 2 UP DOWN +.names direction$_n6b5_n6bc$true<*1*> direction$_n696$raw_n6ad<*1*> _n6b5 direction$_n6b5$raw_n6c7<*1*> +- - 0 =direction$_n696$raw_n6ad<*1*> +- - 1 =direction$_n6b5_n6bc$true<*1*> +.names direction$_n6b5_n6bc$true<*2*> direction$_n696$raw_n6ad<*2*> _n6b5 direction$_n6b5$raw_n6c7<*2*> +- - 0 =direction$_n696$raw_n6ad<*2*> +- - 1 =direction$_n6b5_n6bc$true<*2*> +.names inc<2> _n6d0 +.def 1 +0 0 +.names _n6d0 _n6cf +- =_n6d0 +# locations [2] = locations [2] + 1 +.names _n6d3<0> +0 +.names _n6d3<1> +1 +.names _n6d4<0> +1 +.names _n6d4<1> +0 +.names _n6d4<0> _n6d3<0> _n6d6<0> +.def 0 +0 1 1 +1 0 1 +.names _n6d4<1> _n6d3<1> _n6d6<1> +.def 0 +0 1 1 +1 0 1 +.names _n6d6<0> _n6d6<1> _n6d7 +.def 1 +0 0 0 +.names _n6d7 _n6d5 +0 1 +1 0 +.names _n6d2<0> locations$dec$raw_n68a<*1*><0> _n6d5 locations$inc_n6d1$true<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n6d2<1> locations$dec$raw_n68a<*1*><1> _n6d5 locations$inc_n6d1$true<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n6da<0> +0 +.names _n6da<1> +1 +.names _n6da<0> _n6d3<0> _n6dc<0> +.def 0 +0 1 1 +1 0 1 +.names _n6da<1> _n6d3<1> _n6dc<1> +.def 0 +0 1 1 +1 0 1 +.names _n6dc<0> _n6dc<1> _n6dd +.def 1 +0 0 0 +.names _n6dd _n6db +0 1 +1 0 +.names _n6d2<0> locations$dec$raw_n68a<*2*><0> _n6db locations$inc_n6d1$true<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n6d2<1> locations$dec$raw_n68a<*2*><1> _n6db locations$inc_n6d1$true<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n6e0<0> +0 +.names _n6e0<1> +1 +.names locations$dec$raw_n68a<*1*><0> locations$dec$raw_n68a<*2*><0> _n6e0<1> _n6e0<0> _n6e1<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations$dec$raw_n68a<*1*><1> locations$dec$raw_n68a<*2*><1> _n6e0<1> _n6e0<0> _n6e1<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n6e2<0> +1 +.names _n6e2<1> +0 +# locations [2] + 1 +.names _n6e4 +0 +.names _n6e1<0> _n6e2<0> _n6e4 _n6e3<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n6e6 +0 +.names _n6e1<0> _n6e2<0> _n6e6 _n6e5 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n6e1<1> _n6e2<1> _n6e5 _n6e3<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n6e3<0> _n6d2<0> +- =_n6e3<0> +.names _n6e3<1> _n6d2<1> +- =_n6e3<1> +# direction [2] = 0 +.mv direction$inc_n6e7$true<*1*> 2 UP DOWN +.mv direction$inc_n6e7$true<*2*> 2 UP DOWN +.mv _n6e8 2 UP DOWN +.names _n6e9<0> +0 +.names _n6e9<1> +1 +.names _n6ea<0> +1 +.names _n6ea<1> +0 +.names _n6ea<0> _n6e9<0> _n6ec<0> +.def 0 +0 1 1 +1 0 1 +.names _n6ea<1> _n6e9<1> _n6ec<1> +.def 0 +0 1 1 +1 0 1 +.names _n6ec<0> _n6ec<1> _n6ed +.def 1 +0 0 0 +.names _n6ed _n6eb +0 1 +1 0 +.names _n6e8 direction$_n6b5$raw_n6c7<*1*> _n6eb direction$inc_n6e7$true<*1*> +- - 0 =direction$_n6b5$raw_n6c7<*1*> +- - 1 =_n6e8 +.names _n6ee<0> +0 +.names _n6ee<1> +1 +.names _n6ee<0> _n6e9<0> _n6f0<0> +.def 0 +0 1 1 +1 0 1 +.names _n6ee<1> _n6e9<1> _n6f0<1> +.def 0 +0 1 1 +1 0 1 +.names _n6f0<0> _n6f0<1> _n6f1 +.def 1 +0 0 0 +.names _n6f1 _n6ef +0 1 +1 0 +.names _n6e8 direction$_n6b5$raw_n6c7<*2*> _n6ef direction$inc_n6e7$true<*2*> +- - 0 =direction$_n6b5$raw_n6c7<*2*> +- - 1 =_n6e8 +.names _n6e8 +UP +# if/else (inc [2]) +.mv direction$inc$raw_n6f2<*1*> 2 UP DOWN +.mv direction$inc$raw_n6f2<*2*> 2 UP DOWN +.names inc<2> _n6f3 +.def 1 +0 0 +.names direction$inc_n6e7$true<*1*> direction$_n6b5$raw_n6c7<*1*> _n6f3 direction$inc$raw_n6f2<*1*> +- - 0 =direction$_n6b5$raw_n6c7<*1*> +- - 1 =direction$inc_n6e7$true<*1*> +.names direction$inc_n6e7$true<*2*> direction$_n6b5$raw_n6c7<*2*> _n6f3 direction$inc$raw_n6f2<*2*> +- - 0 =direction$_n6b5$raw_n6c7<*2*> +- - 1 =direction$inc_n6e7$true<*2*> +.names inc<2> _n6f5 +.def 1 +0 0 +.names locations$inc_n6d1$true<*1*><0> locations$dec$raw_n68a<*1*><0> _n6f5 locations$inc$raw_n6f4<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$inc_n6d1$true<*1*><1> locations$dec$raw_n68a<*1*><1> _n6f5 locations$inc$raw_n6f4<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$inc_n6d1$true<*2*><0> locations$dec$raw_n68a<*2*><0> _n6f5 locations$inc$raw_n6f4<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$inc_n6d1$true<*2*><1> locations$dec$raw_n68a<*2*><1> _n6f5 locations$inc$raw_n6f4<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names dec<2> _n701 +.def 1 +0 0 +.names _n701 _n700 +- =_n701 +# locations [2] = locations [2] - 1 +.names _n704<0> +0 +.names _n704<1> +1 +.names _n705<0> +1 +.names _n705<1> +0 +.names _n705<0> _n704<0> _n707<0> +.def 0 +0 1 1 +1 0 1 +.names _n705<1> _n704<1> _n707<1> +.def 0 +0 1 1 +1 0 1 +.names _n707<0> _n707<1> _n708 +.def 1 +0 0 0 +.names _n708 _n706 +0 1 +1 0 +.names _n703<0> locations$inc$raw_n6f4<*1*><0> _n706 locations$dec_n702$true<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n703<1> locations$inc$raw_n6f4<*1*><1> _n706 locations$dec_n702$true<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n70b<0> +0 +.names _n70b<1> +1 +.names _n70b<0> _n704<0> _n70d<0> +.def 0 +0 1 1 +1 0 1 +.names _n70b<1> _n704<1> _n70d<1> +.def 0 +0 1 1 +1 0 1 +.names _n70d<0> _n70d<1> _n70e +.def 1 +0 0 0 +.names _n70e _n70c +0 1 +1 0 +.names _n703<0> locations$inc$raw_n6f4<*2*><0> _n70c locations$dec_n702$true<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n703<1> locations$inc$raw_n6f4<*2*><1> _n70c locations$dec_n702$true<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n711<0> +0 +.names _n711<1> +1 +.names locations$inc$raw_n6f4<*1*><0> locations$inc$raw_n6f4<*2*><0> _n711<1> _n711<0> _n712<0> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names locations$inc$raw_n6f4<*1*><1> locations$inc$raw_n6f4<*2*><1> _n711<1> _n711<0> _n712<1> +- - 0 0 0 +- - 0 0 0 +0 - 0 1 0 +1 - 0 1 1 +- 0 1 0 0 +- 1 1 0 1 +- - 1 1 0 +- - 1 1 0 +.names _n713<0> +1 +.names _n713<1> +0 +# locations [2] - 1 +.names _n715 +0 +.names _n712<0> _n713<0> _n715 _n714<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n717 +0 +.names _n712<0> _n713<0> _n717 _n716 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n712<1> _n713<1> _n716 _n714<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n714<0> _n703<0> +- =_n714<0> +.names _n714<1> _n703<1> +- =_n714<1> +# direction [2] = 1 +.mv direction$dec_n718$true<*1*> 2 UP DOWN +.mv direction$dec_n718$true<*2*> 2 UP DOWN +.mv _n719 2 UP DOWN +.names _n71a<0> +0 +.names _n71a<1> +1 +.names _n71b<0> +1 +.names _n71b<1> +0 +.names _n71b<0> _n71a<0> _n71d<0> +.def 0 +0 1 1 +1 0 1 +.names _n71b<1> _n71a<1> _n71d<1> +.def 0 +0 1 1 +1 0 1 +.names _n71d<0> _n71d<1> _n71e +.def 1 +0 0 0 +.names _n71e _n71c +0 1 +1 0 +.names _n719 direction$inc$raw_n6f2<*1*> _n71c direction$dec_n718$true<*1*> +- - 0 =direction$inc$raw_n6f2<*1*> +- - 1 =_n719 +.names _n71f<0> +0 +.names _n71f<1> +1 +.names _n71f<0> _n71a<0> _n721<0> +.def 0 +0 1 1 +1 0 1 +.names _n71f<1> _n71a<1> _n721<1> +.def 0 +0 1 1 +1 0 1 +.names _n721<0> _n721<1> _n722 +.def 1 +0 0 0 +.names _n722 _n720 +0 1 +1 0 +.names _n719 direction$inc$raw_n6f2<*2*> _n720 direction$dec_n718$true<*2*> +- - 0 =direction$inc$raw_n6f2<*2*> +- - 1 =_n719 +.names _n719 +DOWN +# if/else (dec [2]) +.mv direction$dec$raw_n723<*1*> 2 UP DOWN +.mv direction$dec$raw_n723<*2*> 2 UP DOWN +.names dec<2> _n724 +.def 1 +0 0 +.names direction$dec_n718$true<*1*> direction$inc$raw_n6f2<*1*> _n724 direction$dec$raw_n723<*1*> +- - 0 =direction$inc$raw_n6f2<*1*> +- - 1 =direction$dec_n718$true<*1*> +.names direction$dec_n718$true<*2*> direction$inc$raw_n6f2<*2*> _n724 direction$dec$raw_n723<*2*> +- - 0 =direction$inc$raw_n6f2<*2*> +- - 1 =direction$dec_n718$true<*2*> +.names dec<2> _n726 +.def 1 +0 0 +.names locations$dec_n702$true<*1*><0> locations$inc$raw_n6f4<*1*><0> _n726 locations$dec$raw_n725<*1*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$dec_n702$true<*1*><1> locations$inc$raw_n6f4<*1*><1> _n726 locations$dec$raw_n725<*1*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$dec_n702$true<*2*><0> locations$inc$raw_n6f4<*2*><0> _n726 locations$dec$raw_n725<*2*><0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names locations$dec_n702$true<*2*><1> locations$inc$raw_n6f4<*2*><1> _n726 locations$dec$raw_n725<*2*><1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names button_above$raw_n39a<1> button_above<1> +- =button_above$raw_n39a<1> +.names button_above$raw_n3c0<2> button_above<2> +- =button_above$raw_n3c0<2> +.names _n48a _n4bd _n4f1 _n557 _n562 _n5d4 _n5df _n731 +.def 0 + 1 - - - - - - 1 + - 1 - - - - - 1 + - - 1 - - - - 1 + - - - 1 1 - - 1 + - - - - - 1 1 1 +.mv _n732<*0*> 2 ON OFF +.mv _n732<*1*> 2 ON OFF +.mv _n732<*2*> 2 ON OFF +.names _n731 down_floor_buttons$_n5d3$raw_n5fd<*0*> down_floor_buttons<*0*> _n732<*0*> +1 - - =down_floor_buttons$_n5d3$raw_n5fd<*0*> +0 - - =down_floor_buttons<*0*> +.names _n731 down_floor_buttons$_n5d3$raw_n5fd<*1*> down_floor_buttons<*1*> _n732<*1*> +1 - - =down_floor_buttons$_n5d3$raw_n5fd<*1*> +0 - - =down_floor_buttons<*1*> +.names _n731 down_floor_buttons$_n5d3$raw_n5fd<*2*> down_floor_buttons<*2*> _n732<*2*> +1 - - =down_floor_buttons$_n5d3$raw_n5fd<*2*> +0 - - =down_floor_buttons<*2*> +.names buttons$raw_n366<0> buttons<0> +- =buttons$raw_n366<0> +.names buttons$raw_n371<1> buttons<1> +- =buttons$raw_n371<1> +.names buttons$raw_n37c<2> buttons<2> +- =buttons$raw_n37c<2> +.names _n610 _n625 _n635 _n665 _n6a1 _n6bb _n6cf _n700 _n784 +.def 0 + 1 - - - - - - - 1 + - 1 - - - - - - 1 + - - 1 - - - - - 1 + - - - 1 - - - - 1 + - - - - 1 - - - 1 + - - - - - 1 - - 1 + - - - - - - 1 - 1 + - - - - - - - 1 1 +.mv _n785<*1*> 2 UP DOWN +.mv _n785<*2*> 2 UP DOWN +.names _n784 direction$dec$raw_n723<*1*> direction<*1*> _n785<*1*> +1 - - =direction$dec$raw_n723<*1*> +0 - - =direction<*1*> +.names _n784 direction$dec$raw_n723<*2*> direction<*2*> _n785<*2*> +1 - - =direction$dec$raw_n723<*2*> +0 - - =direction<*2*> +.names button_below$raw_n387<1> button_below<1> +- =button_below$raw_n387<1> +.names button_below$raw_n3ad<2> button_below<2> +- =button_below$raw_n3ad<2> +.names _n475 _n4a3 _n4d7 _n51b _n526 _n598 _n5a3 _n7bc +.def 0 + 1 - - - - - - 1 + - 1 - - - - - 1 + - - 1 - - - - 1 + - - - 1 1 - - 1 + - - - - - 1 1 1 +.mv _n7bd<*0*> 2 ON OFF +.mv _n7bd<*1*> 2 ON OFF +.mv _n7bd<*2*> 2 ON OFF +.names _n7bc up_floor_buttons$_n597$raw_n5c2<*0*> up_floor_buttons<*0*> _n7bd<*0*> +1 - - =up_floor_buttons$_n597$raw_n5c2<*0*> +0 - - =up_floor_buttons<*0*> +.names _n7bc up_floor_buttons$_n597$raw_n5c2<*1*> up_floor_buttons<*1*> _n7bd<*1*> +1 - - =up_floor_buttons$_n597$raw_n5c2<*1*> +0 - - =up_floor_buttons<*1*> +.names _n7bc up_floor_buttons$_n597$raw_n5c2<*2*> up_floor_buttons<*2*> _n7bd<*2*> +1 - - =up_floor_buttons$_n597$raw_n5c2<*2*> +0 - - =up_floor_buttons<*2*> +.names stop_next$raw_n3ef<1> stop_next<1> +- =stop_next$raw_n3ef<1> +.names stop_next$raw_n42c<2> stop_next<2> +- =stop_next$raw_n42c<2> +.names _n635 _n665 _n6cf _n700 _n80f +.def 0 + 1 - - - 1 + - 1 - - 1 + - - 1 - 1 + - - - 1 1 +.names _n80f locations$dec$raw_n725<*1*><0> locations$dec$raw_n725<*1*><1> locations<*1*><0> locations<*1*><1> -> _n810<*1*><0> _n810<*1*><1> +1 - - - - =locations$dec$raw_n725<*1*><0> =locations$dec$raw_n725<*1*><1> +0 - - - - =locations<*1*><0> =locations<*1*><1> +.names _n80f locations$dec$raw_n725<*2*><0> locations$dec$raw_n725<*2*><1> locations<*2*><0> locations<*2*><1> -> _n810<*2*><0> _n810<*2*><1> +1 - - - - =locations$dec$raw_n725<*2*><0> =locations$dec$raw_n725<*2*><1> +0 - - - - =locations<*2*><0> =locations<*2*><1> +.names continue$raw_n3d3<1> continue<1> +- =continue$raw_n3d3<1> +.names continue$raw_n3e1<2> continue<2> +- =continue$raw_n3e1<2> +# non-blocking assignments +# latches +.r down_floor_buttons$raw_n33f<*0*> down_floor_buttons<*0*> +.def ON +OFF =down_floor_buttons$raw_n33f<*0*> +.r down_floor_buttons$raw_n33f<*1*> down_floor_buttons<*1*> +.def ON +OFF =down_floor_buttons$raw_n33f<*1*> +.r down_floor_buttons$raw_n33f<*2*> down_floor_buttons<*2*> +.def ON +OFF =down_floor_buttons$raw_n33f<*2*> +.latch _n732<*0*> down_floor_buttons<*0*> +.latch _n732<*1*> down_floor_buttons<*1*> +.latch _n732<*2*> down_floor_buttons<*2*> +.r up_floor_buttons$raw_n30f<*0*> up_floor_buttons<*0*> +.def ON +OFF =up_floor_buttons$raw_n30f<*0*> +.r up_floor_buttons$raw_n30f<*1*> up_floor_buttons<*1*> +.def ON +OFF =up_floor_buttons$raw_n30f<*1*> +.r up_floor_buttons$raw_n30f<*2*> up_floor_buttons<*2*> +.def ON +OFF =up_floor_buttons$raw_n30f<*2*> +.latch _n7bd<*0*> up_floor_buttons<*0*> +.latch _n7bd<*1*> up_floor_buttons<*1*> +.latch _n7bd<*2*> up_floor_buttons<*2*> +.r direction$raw_n35b<*1*> direction<*1*> +.def UP +DOWN =direction$raw_n35b<*1*> +.r direction$raw_n35b<*2*> direction<*2*> +.def UP +DOWN =direction$raw_n35b<*2*> +.latch _n785<*1*> direction<*1*> +.latch _n785<*2*> direction<*2*> +.r locations$raw_n2df<*1*><0> locations<*1*><0> +.def 0 +1 1 +.r locations$raw_n2df<*2*><0> locations<*2*><0> +.def 0 +1 1 +.r locations$raw_n2df<*1*><1> locations<*1*><1> +.def 0 +1 1 +.r locations$raw_n2df<*2*><1> locations<*2*><1> +.def 0 +1 1 +.latch _n810<*1*><0> locations<*1*><0> +.latch _n810<*2*><0> locations<*2*><0> +.latch _n810<*1*><1> locations<*1*><1> +.latch _n810<*2*><1> locations<*2*><1> +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/elevator/elevator.v =================================================================== --- vis_dev/vis-2.1/examples/elevator/elevator.v (revision 11) +++ vis_dev/vis-2.1/examples/elevator/elevator.v (revision 11) @@ -0,0 +1,262 @@ +`define elev 2 +`define floor 3 +`define width 2 +typedef enum {UP,DOWN} dir; +typedef enum {STOPPED,MOVING} mov; +typedef enum {OPEN,OPENING,CLOSED,CLOSING} dr; +typedef enum {ON,OFF} onoff; + +//*********************************************** +module main(clk); +input clk; +wire[1:`elev] stop_next; +wire[1:`elev] inc; +wire[1:`elev] dec; +wire[1:`elev] continue; +wire[0:`width-1] init1, init2, init11, init22; + +assign init11=$ND(0,1,2,3); +assign init22=$ND(0,1,2,3); +assign init1 = init11==3?2:init11; +assign init2 = init22==3?2:init22; + +elevator e1(clk,stop_next[1],inc[1],dec[1],continue[1],init1); +elevator e2(clk,stop_next[2],inc[2],dec[2],continue[2],init2); +main_control main_control(clk,inc,dec,stop_next,continue,init1,init2); +endmodule +//*********************************************** + +//************************************************ +module main_control(clk,inc,dec,stop_next,continue,init1,init2); +input clk,inc,dec,init1,init2; +output stop_next,continue; +wire[1:`elev] inc; +wire[1:`elev] continue; +wire[1:`elev] dec; +wire[1:`elev] stop_next; +reg [0:`width-1] locations[1:`elev]; +onoff reg up_floor_buttons[0:`floor-1]; +onoff reg down_floor_buttons[0:`floor-1]; +wire[0:`floor-1] random_up; +wire[0:`width-1] init1,init2; +wire[0:`floor-1] random_down; +wire[0:`floor-1] buttons; +wire[1:`elev] button_above,button_below; +dir reg direction[1:`elev]; +initial begin + locations[1]=init1; + locations[2]=init2; + up_floor_buttons[0]=OFF; + up_floor_buttons[1]=OFF; + up_floor_buttons[2]=OFF; + down_floor_buttons[0]=OFF; + down_floor_buttons[1]=OFF; + down_floor_buttons[2]=OFF; + direction[1]=UP; + direction[2]=UP; +end + +//compute if elevator should continue in same direction. We skip the next floor assuming +// that the stop_next computation will take care of this. +assign buttons[0] = up_floor_buttons[0]==ON || down_floor_buttons[0]==ON; +assign buttons[1] = up_floor_buttons[1]==ON || down_floor_buttons[1]==ON; +assign buttons[2] = up_floor_buttons[2]==ON || down_floor_buttons[2]==ON; +assign button_below[1] = + ((locations[1]==2)&&(buttons[0]||buttons[1])) + || (locations[1]==1 && buttons[0]); +assign button_above[1] = ((locations[1]==0)&&(buttons[2]||buttons[1])) + || ((locations[1]==1)&&(buttons[2])); +assign button_below[2] = + ((locations[2]==2)&&(buttons[0]||buttons[1])) + || (locations[2]==1 && buttons[0]); +assign button_above[2] = ((locations[2]==0)&&(buttons[2]||buttons[1])) + || ((locations[2]==1)&&(buttons[2])); +assign continue[1] = button_above[1] && direction[1]==UP || button_below[1] && direction[1]==DOWN; +assign continue[2] = button_above[2] && direction[2]==UP || button_below[2] && direction[2]==DOWN; + +//schedule the next pickup + assign stop_next[1]=((locations[1] != `floor-1)&&(direction[1]==UP))? + ((up_floor_buttons[locations[1]+1]==ON)?1:0): + (((locations[1] != 0)&&(direction[1]==DOWN))? + ((down_floor_buttons[locations[1]-1]==ON)?1:0):0); + assign stop_next[2]=((locations[2] != `floor-1)&&(direction[2]==UP))? + ((up_floor_buttons[locations[2]+1]==ON)?1:0): + (((locations[2] != 0)&&(direction[2]==DOWN))? + ((down_floor_buttons[locations[2]-1]==ON)?1:0):0); + assign random_up[0] = $ND(0,1); + assign random_down[0] = $ND(0,1); + assign random_up[1] = $ND(0,1); + assign random_down[1] = $ND(0,1); + assign random_up[2] = $ND(0,1); + assign random_down[2] = $ND(0,1); + + +always@(posedge clk) begin +// randomly push floor buttons +for (i=0;i<=`floor-1;i=i+1)begin + if (random_up[i]) up_floor_buttons[i]=ON; + if (random_down[i]) down_floor_buttons[i]=ON; +end + +//turn off scheduled floor buttons. +// it is important to turn these off after the random pushes, since we +// want the scheduled buttons to be OFF even though they may have been +// randomly pushed. +for (i=1;i<=`elev;i=i+1) begin + if ((locations[i] != `floor-1)&& (direction[i] == UP)) begin + if (up_floor_buttons[locations[i]+1]==ON) begin + up_floor_buttons[locations[i]+1] = OFF; + end + end + if ((locations[i] != 0)&& (direction[i] == DOWN)) begin + if (down_floor_buttons[locations[i]-1]==ON) begin + down_floor_buttons[locations[i]-1] = OFF; + end + end +end +end + +//keep track of locations and directions +always@(posedge clk) begin +for (i=1;i<=`elev;i=i+1) begin + if (locations[i]==`floor-1) direction[i] = DOWN; + if (locations[i]==0) direction[i]=UP; + if(inc[i]) begin + locations[i]=locations[i]+1; + direction[i]=UP; + end + if(dec[i]) begin + locations[i]=locations[i]-1; + direction[i]=DOWN; + end +end +end + +endmodule +//*********************************************** + +//*********************************************** +module elevator(clk,stop_next,inc,dec,continue,init); +input clk,stop_next,continue,init; +output inc,dec; +onoff reg buttons[0:`floor-1]; +wire [0:`width-1] init; +reg[0:`width-1] location; +dir reg direction; +mov reg movement; +dr reg door; +reg open_next; +wire button_above, button_below; + +//initial begin +initial open_next = 0; +initial location = init; +initial direction = UP; +initial door = OPEN; +initial movement = STOPPED; +initial buttons[0]=OFF; +initial buttons[1]=OFF; +initial buttons[2]=OFF; +//end + +wire[0:`floor-1] random_push; +wire button_above,button_below; +assign random_push = $ND(0,1,2,3,4,5,6,7); +assign button_below = + ((location==2)&&(buttons[1]==ON||buttons[0]==ON)) || + ((location==1)&&buttons[0]==ON); +assign button_above = ((location==0)&&(buttons[2]==ON|| + buttons[1]==ON)) || + ((location==1)&&(buttons[2]==ON)); + +//****************************** +always@(posedge clk) begin +// randomly push buttons. +// But when door is open turn button off for that floor. +for (i=0;i<=`floor-1;i=i+1) begin + if (i == location) buttons[i]=OFF; + else if (random_push[i]) buttons[i]=ON; +end + +// record a request to stop at the next floor +// it is important that this happens last since we want to +// insure that the stop_next request is always recorded by +// pushing the button. +if(stop_next) begin + if (direction==UP) buttons[location+1]=ON; + else buttons[location-1]=ON; + end +end +//******************************* + +//******************************* +always@(posedge clk) begin +//schedule the door to open at the next floor +if(door != CLOSED) open_next=0; +else if (movement==MOVING&&(stop_next||(direction == UP&&buttons[location+1]==ON)|| + (direction == DOWN&&buttons[location-1]==ON))) + open_next=1; +end +//******************************* + +wire random; +assign random = $ND(0,1); + +//******************************* +always@(posedge clk) begin +//Door operation: open the door if button[location] is on. +//Random pause between different states. + case (door) + CLOSED: if (open_next&&movement==STOPPED) + door=OPENING; + OPENING: if (random) door = OPEN; + OPEN: if (random) door = CLOSING; + CLOSING: if (random) door = CLOSED; + endcase +end +//******************************* + +// Move to next floor. Increase or decrease location when arrived. +// Signal to main control (through inc or dec) that have arrived at next floor. +wire stop_moving; +wire start_moving; +wire r_stop; +assign start_moving = (continue || button_above&&direction==UP) || + (button_below && direction == DOWN); +assign r_stop = $ND(0,1); +assign stop_moving = r_stop&&(movement == MOVING); +assign inc = (stop_moving)&&(direction == UP); +assign dec = (stop_moving)&&(direction == DOWN); +//******************************* +always@(posedge clk) begin +if (door == CLOSED) begin + case (movement) + STOPPED: if (door==CLOSED&&start_moving&&!open_next) + movement=MOVING; + MOVING: if (stop_moving) begin + movement=STOPPED; + if (direction == UP) location = location+1; + if (direction == DOWN) location = location-1; + end + endcase + end +end +//******************************* + +// Determine direction of movement + +//******************************* +always@(posedge clk) begin + case (direction) + UP: if((!button_above)&&!continue) + direction = DOWN; + DOWN: if((!button_below)&&!continue) + direction = UP; + endcase + if(location==`floor-1) direction=DOWN; + if(location==0) direction=UP; + end +//******************************* + +endmodule +//*********************************************** Index: vis_dev/vis-2.1/examples/elevator/emodel-simp.blif =================================================================== --- vis_dev/vis-2.1/examples/elevator/emodel-simp.blif (revision 11) +++ vis_dev/vis-2.1/examples/elevator/emodel-simp.blif (revision 11) @@ -0,0 +1,107 @@ +.model elevator +.inputs init<0>0 init<1>0 location<0>0 location<1>0 buttons<*0*>0 \ +buttons<*1*>0 buttons<*2*>0 stop_next0 direction0 door0 door1 movement0 \ +open_next0 continue0 [0]0 [1]0 [2]0 [3]0 [4]0 +.outputs open_next$raw_n160 location$raw_n17<0>0 location$raw_n17<1>0 \ +direction$raw_n180 door$raw_n190 door$raw_n191 movement$raw_n1a0 \ +buttons$raw_n1b<*0*>0 buttons$raw_n1b<*1*>0 buttons$raw_n1b<*2*>0 \ +buttons$raw_n2d<*0*>0 buttons$raw_n2d<*1*>0 buttons$raw_n2d<*2*>0 \ +buttons$raw_n3f<*0*>0 buttons$raw_n3f<*1*>0 buttons$raw_n3f<*2*>0 _n2450 \ +_n25c<*0*>0 _n25c<*1*>0 _n25c<*2*>0 _n29d0 _n29d1 _n2b4<0>0 _n2b4<1>0 _n2b60 \ +_n2cd0 dec0 inc0 +.names open_next$raw_n160 +.names direction$raw_n180 +.names door$raw_n190 +.names door$raw_n191 +.names movement$raw_n1a0 +.names buttons$raw_n1b<*0*>0 + 1 +.names buttons$raw_n1b<*1*>0 +.names buttons$raw_n1b<*2*>0 +.names buttons$raw_n2d<*0*>0 +.names buttons$raw_n2d<*1*>0 + 1 +.names buttons$raw_n2d<*2*>0 +.names buttons$raw_n3f<*0*>0 +.names buttons$raw_n3f<*1*>0 +.names buttons$raw_n3f<*2*>0 + 1 +.names buttons<*0*>0 buttons<*1*>0 buttons<*2*>0 direction0 door0 door1 \ +movement0 open_next0 continue0 _n2b60 [4]0 inc0 dec0 _n2450 +----1-1------ 1 +-----01------ 1 +------1---0-- 1 +----01001---- 1 +-0-001-0-0-0- 1 +--0001-0-0-0- 1 +0--101-0-1--0 1 +-0-101-0-1--0 1 +.names location<0>0 location<1>0 buttons<*0*>0 stop_next0 direction0 [0]0 \ +_n25c<*0*>0 +00---- 1 +0-1--0 1 +--10-0 1 +-11-10 1 +-01-00 1 +.names location<0>0 location<1>0 buttons<*1*>0 stop_next0 direction0 [1]0 \ +_n25c<*1*>0 +10---- 1 +1-1--0 1 +--10-0 1 +-01-10 1 +-11-00 1 +.names location<0>0 location<1>0 buttons<*2*>0 stop_next0 direction0 [2]0 \ +_n25c<*2*>0 +01---- 1 +0-1--0 1 +--10-0 1 +-01-10 1 +-11-00 1 +.names door0 door1 _n29d1 [3]0 _n29d0 +-01- 1 +-10- 1 +1--0 1 +.names door0 door1 movement0 open_next0 [3]0 _n29d1 +11--- 1 +-11-- 1 +-1-0- 1 +00--1 1 +.names location<0>0 door0 door1 movement0 [4]0 inc0 dec0 _n2b4<0>0 +11----- 1 +1-0---- 1 +1----00 1 +00111-- 1 +.names location<0>0 location<1>0 door0 door1 inc0 dec0 _n2b4<1>0 +-11--- 1 +-1-0-- 1 +11--0- 1 +01---0 1 +10011- 1 +0001-1 1 +.names location<0>0 location<1>0 buttons<*0*>0 buttons<*2*>0 direction0 \ +continue0 _n2b60 +01---- 1 +1---11 1 +100-1- 1 +11--00 1 +1--100 1 +.names location<0>0 location<1>0 buttons<*0*>0 buttons<*1*>0 buttons<*2*>0 \ +stop_next0 direction0 door0 door1 movement0 open_next0 _n2cd0 +-------01-1 1 +-----1-011- 1 +0--0---011- 1 +00----1011- 1 +-00---1011- 1 +01----0011- 1 +-10---0011- 1 +11--0-1011- 1 +10--0-0011- 1 +.names direction0 movement0 [4]0 inc0 +011 1 +.names direction0 movement0 [4]0 dec0 +111 1 +.names init<0>0 location$raw_n17<0>0 +1 1 +.names init<1>0 location$raw_n17<1>0 +1 1 +.end Index: vis_dev/vis-2.1/examples/elevator/emodel.blif =================================================================== --- vis_dev/vis-2.1/examples/elevator/emodel.blif (revision 11) +++ vis_dev/vis-2.1/examples/elevator/emodel.blif (revision 11) @@ -0,0 +1,1814 @@ +.model elevator +.inputs init<0>0 init<1>0 location<0>0 location<1>0 buttons<*0*>0 buttons<*1*>0 buttons<*2*>0 stop_next0 direction0 door0 door1 movement0 open_next0 continue0 +.outputs _n2450 _n25c<*0*>0 _n25c<*1*>0 _n25c<*2*>0 _n29d0 _n29d1 _n2b4<0>0 _n2b4<1>0 _n2b60 _n2cd0 dec0 inc0 +.outputs movement$raw_n1a0 +.outputs buttons$raw_n1b<*2*>0 +.outputs buttons$raw_n2d<*2*>0 +.outputs buttons$raw_n3f<*2*>0 +.outputs buttons$raw_n1b<*0*>0 +.outputs buttons$raw_n2d<*0*>0 +.outputs buttons$raw_n3f<*0*>0 +.outputs door$raw_n190 +.outputs door$raw_n191 +.outputs location$raw_n17<0>0 +.outputs buttons$raw_n1b<*1*>0 +.outputs buttons$raw_n2d<*1*>0 +.outputs buttons$raw_n3f<*1*>0 +.outputs direction$raw_n180 +.outputs open_next$raw_n160 +.outputs location$raw_n17<1>0 +.names open_next$raw_n160 +0 +.names init<0>0 location$raw_n17<0>0 +1 1 +.names init<1>0 location$raw_n17<1>0 +1 1 +.names direction$raw_n180 +0 +.names door$raw_n191 +0 +.names door$raw_n190 +0 +.names movement$raw_n1a0 +0 +.names _n1d<0>0 +0 +.names _n1d<1>0 +0 +.names _n1e<0>0 +0 +.names _n1e<1>0 +0 +.names _n1e<0>0 _n1d<0>0 _n20<0>0 +01 1 +10 1 +.names _n1e<1>0 _n1d<1>0 _n20<1>0 +01 1 +10 1 +.names _n210_b _n210 +0 1 +.names _n20<0>0 _n20<1>0 _n210_b +00 1 +.names _n210 _n1f0 +0 1 +.names _n220 +0 +.names _n1c0 _n220 _n1f0 buttons$raw_n1b<*0*>0 +-10 1 +1-1 1 +.names _n23<0>0 +1 +.names _n23<1>0 +0 +.names _n23<0>0 _n1d<0>0 _n25<0>0 +01 1 +10 1 +.names _n23<1>0 _n1d<1>0 _n25<1>0 +01 1 +10 1 +.names _n260_b _n260 +0 1 +.names _n25<0>0 _n25<1>0 _n260_b +00 1 +.names _n260 _n240 +0 1 +.names _n270 +0 +.names _n1c0 _n270 _n240 buttons$raw_n1b<*1*>0 +-10 1 +1-1 1 +.names _n28<0>0 +0 +.names _n28<1>0 +1 +.names _n28<0>0 _n1d<0>0 _n2a<0>0 +01 1 +10 1 +.names _n28<1>0 _n1d<1>0 _n2a<1>0 +01 1 +10 1 +.names _n2b0_b _n2b0 +0 1 +.names _n2a<0>0 _n2a<1>0 _n2b0_b +00 1 +.names _n2b0 _n290 +0 1 +.names _n2c0 +0 +.names _n1c0 _n2c0 _n290 buttons$raw_n1b<*2*>0 +-10 1 +1-1 1 +.names _n1c0 +1 +.names _n2f<0>0 +1 +.names _n2f<1>0 +0 +.names _n30<0>0 +0 +.names _n30<1>0 +0 +.names _n30<0>0 _n2f<0>0 _n32<0>0 +01 1 +10 1 +.names _n30<1>0 _n2f<1>0 _n32<1>0 +01 1 +10 1 +.names _n330_b _n330 +0 1 +.names _n32<0>0 _n32<1>0 _n330_b +00 1 +.names _n330 _n310 +0 1 +.names _n340 +0 +.names _n2e0 _n340 _n310 buttons$raw_n2d<*0*>0 +-10 1 +1-1 1 +.names _n35<0>0 +1 +.names _n35<1>0 +0 +.names _n35<0>0 _n2f<0>0 _n37<0>0 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direction$_n213_n215$true0 direction0 _n2130 direction$_n213$raw_n2180 +-10 1 +1-1 1 +.names _n21b0 +1 +.names direction0 _n21b0 _n21a0 +00 1 +11 1 +.names _n21a0 _n2190 +1 1 +.names button_below0 _n21c0 +0 1 +.names continue0 _n21d0 +0 1 +.names _n21c0 _n21d0 _n21e0 +11 1 +.names _n21e0 _n21f0 +1 1 +.names direction$_n21e_n220$true0 +0 +.names direction$_n21e_n220$true0 direction0 _n21e0 direction$_n21e$raw_n2230 +-10 1 +1-1 1 +.names direction$_n21e$raw_n2230 direction0 _n2190 direction$_n219$raw_n2260 +-10 1 +1-1 1 +.names direction$_n213$raw_n2180 direction$_n219$raw_n2260 _n20e0 direction$_n20e$raw_n2270 +-10 1 +1-1 1 +.names _n22c<0>0 +1 +.names _n22c<1>0 +1 +.names _n22d<0>0 +1 +.names _n22d<1>0 +0 +.names _n22f0 +0 +.names _n22c<0>0 _n22d<0>0 _n22f0 _n22e<0>0 +001 1 +010 1 +100 1 +111 1 +.names _n2310 +0 +.names _n22c<0>0 _n22d<0>0 _n2310 _n2300 +001 1 +010 1 +011 1 +111 1 +.names _n22c<1>0 _n22d<1>0 _n2300 _n22e<1>0 +001 1 +010 1 +100 1 +111 1 +.names location<0>0 _n22e<0>0 _n232<0>0 +01 1 +10 1 +.names location<1>0 _n22e<1>0 _n232<1>0 +01 1 +10 1 +.names _n2330_b _n2330 +0 1 +.names _n232<0>0 _n232<1>0 _n2330_b +00 1 +.names _n2330 _n22b0 +0 1 +.names _n22b0 _n2340 +1 1 +.names direction$_n22b_n235$true0 +1 +.names direction$_n22b_n235$true0 direction$_n20e$raw_n2270 _n22b0 direction$_n22b$raw_n2360 +-10 1 +1-1 1 +.names _n23b<0>0 +0 +.names _n23b<1>0 +0 +.names location<0>0 _n23b<0>0 _n23c<0>0 +01 1 +10 1 +.names location<1>0 _n23b<1>0 _n23c<1>0 +01 1 +10 1 +.names _n23d0_b _n23d0 +0 1 +.names _n23c<0>0 _n23c<1>0 _n23d0_b +00 1 +.names _n23d0 _n23a0 +0 1 +.names _n23a0 _n23e0 +1 1 +.names direction$_n23a_n23f$true0 +0 +.names direction$_n23a_n23f$true0 direction$_n22b$raw_n2360 _n23a0 direction$_n23a$raw_n2400 +-10 1 +1-1 1 +.names button_above$raw_n6c0 button_above0 +1 1 +.names _n1b70 _n1b80 _n1c00 _n1c50 _n1c80 _n2440 +111-- 1 +10-11 1 +.names _n2440 movement$_n1b5$raw_n20a0 movement0 _n2450 +11- 1 +0-1 1 +.names _n890 _n990 _nb60 _nc60 _ne40 _nf40 _n10e0 _n1110 _n25b0 +1------- 1 +01------ 1 +--1----- 1 +--01---- 1 +----1--- 1 +----01-- 1 +------11 1 +------10 1 +.names _n25b0 buttons$stop_next$raw_n13c<*0*>0 buttons<*0*>0 _n25c<*0*>0 +11- 1 +0-1 1 +.names _n25b0 buttons$stop_next$raw_n13c<*1*>0 buttons<*1*>0 _n25c<*1*>0 +11- 1 +0-1 1 +.names _n25b0 buttons$stop_next$raw_n13c<*2*>0 buttons<*2*>0 _n25c<*2*>0 +11- 1 +0-1 1 +.names start_moving$raw_n19e0 start_moving0 +1 1 +.names _n16c0 _n1720 _n1770 _n17a0 _n17f0 _n1820 _n1870 _n18a0 _n29c0 +11------ 1 +0-11---- 1 +0-0-11-- 1 +0-0-0-11 1 +.names _n29c0 door$_n16c$raw_n19a0 door$_n16c$raw_n19a1 door0 door1 _n29d0 +110-- 1 +111-- 1 +0--10 1 +0--11 1 +.names _n29c0 door$_n16c$raw_n19a0 door$_n16c$raw_n19a1 door0 door1 _n29d1 +101-- 1 +111-- 1 +0--01 1 +0--11 1 +.names stop_moving$raw_n1a90 stop_moving0 +1 1 +.names _n1b70 _n1b80 _n1c50 _n1c80 _n1cc0 _n1de0 _n2b30 +10111- 1 +1011-1 1 +.names _n2b30 location$_n1b5$raw_n20b<0>0 location$_n1b5$raw_n20b<1>0 location<0>0 location<1>0 _n2b4<0>0 +11--- 1 +0--1- 1 +.names _n2b30 location$_n1b5$raw_n20b<0>0 location$_n1b5$raw_n20b<1>0 location<0>0 location<1>0 _n2b4<1>0 +1-1-- 1 +0---1 1 +.names button_below$raw_n530 button_below0 +1 1 +.names _n20e0 _n2140 _n2190 _n21f0 _n2340 _n23e0 _n2b50 +11---- 1 +0-11-- 1 +----1- 1 +-----1 1 +.names _n2b50 direction$_n23a$raw_n2400 direction0 _n2b60 +11- 1 +0-1 1 +.names _n1420 _n15f0 _n2cc0 +1- 1 +01 1 +.names _n2cc0 open_next$_n140$raw_n1660 open_next0 _n2cd0 +11- 1 +0-1 1 +.names dec$raw_n1b10 dec0 +1 1 +.names inc$raw_n1ad0 inc0 +1 1 +.exdc +.end Index: vis_dev/vis-2.1/examples/elevator/emodel.ctl =================================================================== --- vis_dev/vis-2.1/examples/elevator/emodel.ctl (revision 11) +++ vis_dev/vis-2.1/examples/elevator/emodel.ctl (revision 11) @@ -0,0 +1,2 @@ +AG(movement=MOVING -> door=CLOSED); +AG(buttons<*0*>=ON -> AF((door=OPEN) * location<0>=0 * location<1>=0)); Index: vis_dev/vis-2.1/examples/elevator/emodel.fair =================================================================== --- vis_dev/vis-2.1/examples/elevator/emodel.fair (revision 11) +++ vis_dev/vis-2.1/examples/elevator/emodel.fair (revision 11) @@ -0,0 +1,4 @@ +!(door=OPENING); +!(door=OPEN); +!(door=CLOSING); +!(movement=MOVING); Index: vis_dev/vis-2.1/examples/elevator/emodel.inv =================================================================== --- vis_dev/vis-2.1/examples/elevator/emodel.inv (revision 11) +++ vis_dev/vis-2.1/examples/elevator/emodel.inv (revision 11) @@ -0,0 +1,1 @@ +movement=MOVING -> door=CLOSED; Index: vis_dev/vis-2.1/examples/elevator/emodel.mv =================================================================== --- vis_dev/vis-2.1/examples/elevator/emodel.mv (revision 11) +++ vis_dev/vis-2.1/examples/elevator/emodel.mv (revision 11) @@ -0,0 +1,2062 @@ +.model elevator +.root e1 +.inputs init<0> init<1> stop_next continue +.outputs dec inc +.mv door$_n16c$raw_n19a 4 OPEN OPENING CLOSED CLOSING +.mv _n4b 2 ON OFF +.mv buttons$raw_n3f<*1*> 2 ON OFF +.mv buttons$_n85$raw_naf<*2*> 2 ON OFF +.mv _n25c<*2*> 2 ON OFF +.mv _n179 4 OPEN OPENING CLOSED CLOSING +.mv buttons$_nb2$raw_ndc<*2*> 2 ON OFF +.mv _n16e 4 OPEN OPENING CLOSED CLOSING +.mv _n50 2 ON OFF +.mv buttons$_ne0$raw_n10a<*2*> 2 ON OFF +.mv buttons$_n85_n8a$true<*1*> 2 ON OFF +.mv direction$_n213_n215$true 2 UP DOWN +.mv buttons$_n10f$raw_n138<*2*> 2 ON OFF +.mv direction$_n22b$raw_n236 2 UP DOWN +.mv buttons$raw_n1b<*0*> 2 ON OFF +.mv movement$raw_n1a 2 STOPPED MOVING +.mv movement 2 STOPPED MOVING +.mv _nb8 2 ON OFF +.mv _n8b 2 ON OFF +.mv buttons$random_push$raw_n105<*1*> 2 ON OFF +.mv _n12b 2 ON OFF +.mv direction$_n21e_n220$true 2 UP DOWN +.mv _n1dd 2 UP DOWN +.mv direction$_n20e$raw_n227 2 UP DOWN +.mv movement$_n1c5$raw_n1fb 2 STOPPED MOVING +.mv buttons$raw_n2d<*1*> 2 ON OFF +.mv _n21b 2 UP DOWN +.mv buttons$random_push_nf6$true<*2*> 2 ON OFF +.mv buttons$random_push$raw_nd7<*2*> 2 ON OFF +.mv buttons$_nb2_nb7$true<*1*> 2 ON OFF +.mv buttons$_ne0_ne5$true<*1*> 2 ON OFF +.mv buttons$random_push$raw_nac<*1*> 2 ON OFF +.mv movement$_n1bf$raw_n1c4 2 STOPPED MOVING +.mv _n181 4 OPEN OPENING CLOSED CLOSING +.mv direction$_n23a_n23f$true 2 UP DOWN +.mv movement$_n1b5$raw_n20a 2 STOPPED MOVING +.mv _n3e 2 ON OFF +.mv _n1a0 2 UP DOWN +.mv door$raw_n19 4 OPEN OPENING CLOSED CLOSING +.mv buttons$random_push_nc8$true<*2*> 2 ON OFF +.mv _n1a4 2 UP DOWN +.mv _nf7 2 ON OFF +.mv _n46 2 ON OFF +.mv buttons$raw_n3f<*0*> 2 ON OFF +.mv direction$_n219$raw_n226 2 UP DOWN +.mv _n189 4 OPEN OPENING CLOSED CLOSING +.mv buttons$_n85$raw_naf<*1*> 2 ON OFF +.mv _n25c<*1*> 2 ON OFF +.mv _n40 2 ON OFF +.mv movement$stop_moving$raw_n1f3 2 STOPPED MOVING +.mv buttons$_ne0$raw_n10a<*1*> 2 ON OFF +.mv buttons$_n85_n8a$true<*2*> 2 ON OFF +.mv door$_n17f$raw_n192 4 OPEN OPENING CLOSED CLOSING +.mv direction$_n22b_n235$true 2 UP DOWN +.mv _n141 4 OPEN OPENING CLOSED CLOSING +.mv buttons$stop_next$raw_n13c<*2*> 2 ON OFF +.mv buttons$raw_n1b<*1*> 2 ON OFF +.mv _n145 2 STOPPED MOVING +.mv _n147 2 UP DOWN +.mv buttons$random_push_n9b$true<*2*> 2 ON OFF +.mv _n82 2 ON OFF +.mv buttons$random_push$raw_n105<*2*> 2 ON OFF +.mv _n81 2 ON OFF +.mv buttons$raw_n2d<*2*> 2 ON OFF +.mv direction 2 UP DOWN +.mv buttons$_nb2_nb7$true<*2*> 2 ON OFF +.mv buttons$_ne0_ne5$true<*0*> 2 ON OFF +.mv direction$_n23a$raw_n240 2 UP DOWN +.mv movement$_n1b8$raw_n1ff 2 STOPPED MOVING +.mv buttons$_n10f_n112$true<*0*> 2 ON OFF +.mv door$random$raw_n18e 4 OPEN OPENING CLOSED CLOSING +.mv buttons$random_push$raw_nac<*2*> 2 ON OFF +.mv _n2e 2 ON OFF +.mv _n2c 2 ON OFF +.mv _n39 2 ON OFF +.mv _n1b3 2 UP DOWN +.mv buttons$random_push_nc8$true<*1*> 2 ON OFF +.mv buttons$_n10f_n125$false<*2*> 2 ON OFF +.mv buttons<*0*> 2 ON OFF +.mv _ne6 2 ON OFF +.mv _n1b6 4 OPEN OPENING CLOSED CLOSING +.mv _n34 2 ON OFF +.mv _n1ab 2 STOPPED MOVING +.mv door$random_n183$true 4 OPEN OPENING CLOSED CLOSING +.mv door$random_n17b$true 4 OPEN OPENING CLOSED CLOSING +.mv buttons$_n85$raw_naf<*0*> 2 ON OFF +.mv _n25c<*0*> 2 ON OFF +.mv _n1af 2 UP DOWN +.mv door$random_n18b$true 4 OPEN OPENING CLOSED CLOSING +.mv buttons$_ne0$raw_n10a<*0*> 2 ON OFF +.mv movement$stop_moving_n1c9$true 2 STOPPED MOVING +.mv _n153 2 UP DOWN +.mv door$_n187$raw_n191 4 OPEN OPENING CLOSED CLOSING +.mv buttons$_nb2$raw_ndc<*0*> 2 ON OFF +.mv buttons$raw_n1b<*2*> 2 ON OFF +.mv _n78 2 ON OFF +.mv buttons$stop_next$raw_n13c<*1*> 2 ON OFF +.mv _n77 2 ON OFF +.mv _n245 2 STOPPED MOVING +.mv _n74 2 ON OFF +.mv _n73 2 ON OFF +.mv buttons$_n10f$raw_n138<*0*> 2 ON OFF +.mv door$_n171_n173$true 4 OPEN OPENING CLOSED CLOSING +.mv _n14e 2 ON OFF +.mv _n14f 2 ON OFF +.mv buttons$random_push_n9b$true<*1*> 2 ON OFF +.mv door$_n177$raw_n196 4 OPEN OPENING CLOSED CLOSING +.mv door$random$raw_n17e 4 OPEN OPENING CLOSED CLOSING +.mv buttons$_n10f_n112$true<*1*> 2 ON OFF +.mv _n110 2 UP DOWN +.mv _n1c 2 ON OFF +.mv _n27 2 ON OFF +.mv door$random$raw_n186 4 OPEN OPENING CLOSED CLOSING +.mv buttons$random_push_nc8$true<*0*> 2 ON OFF +.mv _n1c7 2 STOPPED MOVING +.mv _n1ba 2 STOPPED MOVING +.mv buttons$random_push_nf6$true<*0*> 2 ON OFF +.mv buttons$random_push$raw_nd7<*0*> 2 ON OFF +.mv buttons<*1*> 2 ON OFF +.mv _n22 2 ON OFF +.mv buttons$_n10f_n125$false<*1*> 2 ON OFF +.mv _n2b6 2 UP DOWN +.mv _n1bc 4 OPEN OPENING CLOSED CLOSING +.mv _n118 2 ON OFF +.mv direction$raw_n18 2 UP DOWN +.mv _n5f 2 ON OFF +.mv buttons$raw_n3f<*2*> 2 ON OFF +.mv _n5e 2 ON OFF +.mv door$_n171$raw_n176 4 OPEN OPENING CLOSED CLOSING +.mv _n69 2 ON OFF +.mv _n5b 2 ON OFF +.mv _n68 2 ON OFF +.mv _n5a 2 ON OFF +.mv _n15a 2 ON OFF +.mv buttons$_nb2$raw_ndc<*1*> 2 ON OFF +.mv _n15b 2 ON OFF +.mv buttons$stop_next$raw_n13c<*0*> 2 ON OFF +.mv buttons$_n85_n8a$true<*0*> 2 ON OFF +.mv direction$_n213$raw_n218 2 UP DOWN +.mv buttons$_n10f$raw_n138<*1*> 2 ON OFF +.mv buttons$random_push_n9b$true<*0*> 2 ON OFF +.mv movement$_n1bf_n1c1$true 2 STOPPED MOVING +.mv direction$_n21e$raw_n223 2 UP DOWN +.mv _nc9 2 ON OFF +.mv _n210 2 UP DOWN +.mv buttons$_n10f_n112$true<*2*> 2 ON OFF +.mv _n9c 2 ON OFF +.mv buttons$random_push$raw_n105<*0*> 2 ON OFF +.mv _n1cb 2 UP DOWN +.mv buttons$raw_n2d<*0*> 2 ON OFF +.mv _n29d 4 OPEN OPENING CLOSED CLOSING +.mv buttons$random_push$raw_nd7<*1*> 2 ON OFF +.mv buttons$random_push_nf6$true<*1*> 2 ON OFF +.mv buttons$_nb2_nb7$true<*0*> 2 ON OFF +.mv buttons<*2*> 2 ON OFF +.mv buttons$_n10f_n125$false<*0*> 2 ON OFF +.mv buttons$_ne0_ne5$true<*2*> 2 ON OFF +.mv buttons$random_push$raw_nac<*0*> 2 ON OFF +.mv door 4 OPEN OPENING CLOSED CLOSING +.mv _n170 2 STOPPED MOVING +.latch _n245 movement +.reset movement$raw_n1a ->movement +- =movement$raw_n1a +.latch _n25c<*2*> buttons<*2*> +.reset buttons$raw_n1b<*2*> buttons$raw_n2d<*2*> buttons$raw_n3f<*2*> ->buttons<*2*> +.default ON +OFF - - =buttons$raw_n1b<*2*> +ON OFF - =buttons$raw_n2d<*2*> +ON ON OFF =buttons$raw_n3f<*2*> +.latch _n25c<*0*> buttons<*0*> +.reset buttons$raw_n1b<*0*> buttons$raw_n2d<*0*> buttons$raw_n3f<*0*> ->buttons<*0*> +.default ON +OFF - - =buttons$raw_n1b<*0*> +ON OFF - =buttons$raw_n2d<*0*> +ON ON OFF =buttons$raw_n3f<*0*> +.latch _n29d door +.reset door$raw_n19 ->door +- =door$raw_n19 +.latch _n2b4<0> location<0> +.reset location$raw_n17<0> ->location<0> +.default 0 +1 1 +.latch _n2b6 direction +.reset direction$raw_n18 ->direction +- =direction$raw_n18 +.latch _n25c<*1*> buttons<*1*> +.reset buttons$raw_n1b<*1*> buttons$raw_n2d<*1*> buttons$raw_n3f<*1*> ->buttons<*1*> +.default ON +OFF - - =buttons$raw_n1b<*1*> +ON OFF - =buttons$raw_n2d<*1*> +ON ON OFF =buttons$raw_n3f<*1*> +.latch _n2cd open_next +.reset open_next$raw_n16 ->open_next +0 0 +1 1 +.latch _n2b4<1> location<1> +.reset location$raw_n17<1> ->location<1> +.default 0 +1 1 +.table ->open_next$raw_n16 +0 +.table init<0> ->location$raw_n17<0> +- =init<0> +.table init<1> ->location$raw_n17<1> +- =init<1> +.table ->direction$raw_n18 +UP +.table ->door$raw_n19 +OPEN +.table ->movement$raw_n1a +STOPPED +.table ->_n1d<0> +0 +.table ->_n1d<1> +0 +.table ->_n1e<0> +0 +.table ->_n1e<1> +0 +.table _n1e<0> _n1d<0> ->_n20<0> +.default 0 +0 1 1 +1 0 1 +.table _n1e<1> _n1d<1> ->_n20<1> +.default 0 +0 1 1 +1 0 1 +.table _n20<0> _n20<1> ->_n21 +.default 1 +0 0 0 +.table _n21 ->_n1f +0 1 +1 0 +.table ->_n22 +ON +.table _n1c _n22 _n1f ->buttons$raw_n1b<*0*> +- - 0 =_n22 +- - 1 =_n1c +.table ->_n23<0> +1 +.table ->_n23<1> +0 +.table _n23<0> _n1d<0> ->_n25<0> +.default 0 +0 1 1 +1 0 1 +.table _n23<1> _n1d<1> ->_n25<1> +.default 0 +0 1 1 +1 0 1 +.table _n25<0> _n25<1> ->_n26 +.default 1 +0 0 0 +.table _n26 ->_n24 +0 1 +1 0 +.table ->_n27 +ON +.table _n1c _n27 _n24 ->buttons$raw_n1b<*1*> +- - 0 =_n27 +- - 1 =_n1c +.table ->_n28<0> +0 +.table ->_n28<1> +1 +.table _n28<0> _n1d<0> ->_n2a<0> +.default 0 +0 1 1 +1 0 1 +.table _n28<1> _n1d<1> ->_n2a<1> +.default 0 +0 1 1 +1 0 1 +.table _n2a<0> _n2a<1> ->_n2b +.default 1 +0 0 0 +.table _n2b ->_n29 +0 1 +1 0 +.table ->_n2c +ON +.table _n1c _n2c _n29 ->buttons$raw_n1b<*2*> +- - 0 =_n2c +- - 1 =_n1c +.table ->_n1c +OFF +.table ->_n2f<0> +1 +.table ->_n2f<1> +0 +.table ->_n30<0> +0 +.table ->_n30<1> +0 +.table _n30<0> _n2f<0> ->_n32<0> +.default 0 +0 1 1 +1 0 1 +.table _n30<1> _n2f<1> ->_n32<1> +.default 0 +0 1 1 +1 0 1 +.table _n32<0> _n32<1> ->_n33 +.default 1 +0 0 0 +.table _n33 ->_n31 +0 1 +1 0 +.table ->_n34 +ON +.table _n2e _n34 _n31 ->buttons$raw_n2d<*0*> +- - 0 =_n34 +- - 1 =_n2e +.table ->_n35<0> +1 +.table ->_n35<1> +0 +.table _n35<0> _n2f<0> ->_n37<0> +.default 0 +0 1 1 +1 0 1 +.table _n35<1> _n2f<1> ->_n37<1> +.default 0 +0 1 1 +1 0 1 +.table _n37<0> _n37<1> ->_n38 +.default 1 +0 0 0 +.table _n38 ->_n36 +0 1 +1 0 +.table ->_n39 +ON +.table _n2e _n39 _n36 ->buttons$raw_n2d<*1*> +- - 0 =_n39 +- - 1 =_n2e +.table ->_n3a<0> +0 +.table ->_n3a<1> +1 +.table _n3a<0> _n2f<0> ->_n3c<0> +.default 0 +0 1 1 +1 0 1 +.table _n3a<1> _n2f<1> ->_n3c<1> +.default 0 +0 1 1 +1 0 1 +.table _n3c<0> _n3c<1> ->_n3d +.default 1 +0 0 0 +.table _n3d ->_n3b +0 1 +1 0 +.table ->_n3e +ON +.table _n2e _n3e _n3b ->buttons$raw_n2d<*2*> +- - 0 =_n3e +- - 1 =_n2e +.table ->_n2e +OFF +.table ->_n41<0> +0 +.table ->_n41<1> +1 +.table ->_n42<0> +0 +.table ->_n42<1> +0 +.table _n42<0> _n41<0> ->_n44<0> +.default 0 +0 1 1 +1 0 1 +.table _n42<1> _n41<1> ->_n44<1> +.default 0 +0 1 1 +1 0 1 +.table _n44<0> _n44<1> ->_n45 +.default 1 +0 0 0 +.table _n45 ->_n43 +0 1 +1 0 +.table ->_n46 +ON +.table _n40 _n46 _n43 ->buttons$raw_n3f<*0*> +- - 0 =_n46 +- - 1 =_n40 +.table ->_n47<0> +1 +.table ->_n47<1> +0 +.table _n47<0> _n41<0> ->_n49<0> +.default 0 +0 1 1 +1 0 1 +.table _n47<1> _n41<1> ->_n49<1> +.default 0 +0 1 1 +1 0 1 +.table _n49<0> _n49<1> ->_n4a +.default 1 +0 0 0 +.table _n4a ->_n48 +0 1 +1 0 +.table ->_n4b +ON +.table _n40 _n4b _n48 ->buttons$raw_n3f<*1*> +- - 0 =_n4b +- - 1 =_n40 +.table ->_n4c<0> +0 +.table ->_n4c<1> +1 +.table _n4c<0> _n41<0> ->_n4e<0> +.default 0 +0 1 1 +1 0 1 +.table _n4c<1> _n41<1> ->_n4e<1> +.default 0 +0 1 1 +1 0 1 +.table _n4e<0> _n4e<1> ->_n4f +.default 1 +0 0 0 +.table _n4f ->_n4d +0 1 +1 0 +.table ->_n50 +ON +.table _n40 _n50 _n4d ->buttons$raw_n3f<*2*> +- - 0 =_n50 +- - 1 =_n40 +.table ->_n40 +OFF +.table ->random_push<0> random_push<1> random_push<2> +0 0 0 +1 0 0 +0 1 0 +1 1 0 +0 0 1 +1 0 1 +0 1 1 +1 1 1 +.table ->_n55<0> +0 +.table ->_n55<1> +1 +.table location<0> _n55<0> ->_n56<0> +.default 0 +0 1 1 +1 0 1 +.table location<1> _n55<1> ->_n56<1> +.default 0 +0 1 1 +1 0 1 +.table _n56<0> _n56<1> ->_n57 +.default 1 +0 0 0 +.table _n57 ->_n54 +0 1 +1 0 +.table ->_n59<0> +1 +.table ->_n59<1> +0 +.table buttons<*0*> buttons<*1*> buttons<*2*> _n59<1> _n59<0> ->_n5a +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.table ->_n5b +ON +.table _n5a _n5b ->_n58 +.default 0 +- =_n5a 1 +.table ->_n5d<0> +0 +.table ->_n5d<1> +0 +.table buttons<*0*> buttons<*1*> buttons<*2*> _n5d<1> _n5d<0> ->_n5e +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.table ->_n5f +ON +.table _n5e _n5f ->_n5c +.default 0 +- =_n5e 1 +.table _n58 _n5c ->_n60 +.default 1 +0 0 0 +.table _n54 _n60 ->_n61 +.default 0 +1 1 1 +.table ->_n63<0> +1 +.table ->_n63<1> +0 +.table location<0> _n63<0> ->_n64<0> +.default 0 +0 1 1 +1 0 1 +.table location<1> _n63<1> ->_n64<1> +.default 0 +0 1 1 +1 0 1 +.table _n64<0> _n64<1> ->_n65 +.default 1 +0 0 0 +.table _n65 ->_n62 +0 1 +1 0 +.table ->_n67<0> +0 +.table ->_n67<1> +0 +.table buttons<*0*> buttons<*1*> buttons<*2*> _n67<1> _n67<0> ->_n68 +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.table ->_n69 +ON +.table _n68 _n69 ->_n66 +.default 0 +- =_n68 1 +.table _n62 _n66 ->_n6a +.default 0 +1 1 1 +.table _n61 _n6a ->_n6b +.default 1 +0 0 0 +.table _n6b ->button_below$raw_n53 +- =_n6b +.table ->_n6e<0> +0 +.table ->_n6e<1> +0 +.table location<0> _n6e<0> ->_n6f<0> +.default 0 +0 1 1 +1 0 1 +.table location<1> _n6e<1> ->_n6f<1> +.default 0 +0 1 1 +1 0 1 +.table _n6f<0> _n6f<1> ->_n70 +.default 1 +0 0 0 +.table _n70 ->_n6d +0 1 +1 0 +.table ->_n72<0> +0 +.table ->_n72<1> +1 +.table buttons<*0*> buttons<*1*> buttons<*2*> _n72<1> _n72<0> ->_n73 +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.table ->_n74 +ON +.table _n73 _n74 ->_n71 +.default 0 +- =_n73 1 +.table ->_n76<0> +1 +.table ->_n76<1> +0 +.table buttons<*0*> buttons<*1*> buttons<*2*> _n76<1> _n76<0> ->_n77 +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.table ->_n78 +ON +.table _n77 _n78 ->_n75 +.default 0 +- =_n77 1 +.table _n71 _n75 ->_n79 +.default 1 +0 0 0 +.table _n6d _n79 ->_n7a +.default 0 +1 1 1 +.table ->_n7c<0> +1 +.table ->_n7c<1> +0 +.table location<0> _n7c<0> ->_n7d<0> +.default 0 +0 1 1 +1 0 1 +.table location<1> _n7c<1> ->_n7d<1> +.default 0 +0 1 1 +1 0 1 +.table _n7d<0> _n7d<1> ->_n7e +.default 1 +0 0 0 +.table _n7e ->_n7b +0 1 +1 0 +.table ->_n80<0> +0 +.table ->_n80<1> +1 +.table buttons<*0*> buttons<*1*> buttons<*2*> _n80<1> _n80<0> ->_n81 +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.table ->_n82 +ON +.table _n81 _n82 ->_n7f +.default 0 +- =_n81 1 +.table _n7b _n7f ->_n83 +.default 0 +1 1 1 +.table _n7a _n83 ->_n84 +.default 1 +0 0 0 +.table _n84 ->button_above$raw_n6c +- =_n84 +.table ->_n86<0> +0 +.table ->_n86<1> +0 +.table _n86<0> location<0> ->_n87<0> +.default 0 +0 1 1 +1 0 1 +.table _n86<1> location<1> ->_n87<1> +.default 0 +0 1 1 +1 0 1 +.table _n87<0> _n87<1> ->_n88 +.default 1 +0 0 0 +.table _n88 ->_n85 +0 1 +1 0 +.table _n85 ->_n89 +- =_n85 +.table ->_n8c<0> +0 +.table ->_n8c<1> +0 +.table ->_n8d<0> +0 +.table ->_n8d<1> +0 +.table _n8d<0> _n8c<0> ->_n8f<0> +.default 0 +0 1 1 +1 0 1 +.table _n8d<1> _n8c<1> ->_n8f<1> +.default 0 +0 1 1 +1 0 1 +.table _n8f<0> _n8f<1> ->_n90 +.default 1 +0 0 0 +.table _n90 ->_n8e +0 1 +1 0 +.table _n8b buttons<*0*> _n8e ->buttons$_n85_n8a$true<*0*> +- - 0 =buttons<*0*> +- - 1 =_n8b +.table ->_n91<0> +1 +.table ->_n91<1> +0 +.table _n91<0> _n8c<0> ->_n93<0> +.default 0 +0 1 1 +1 0 1 +.table _n91<1> _n8c<1> ->_n93<1> +.default 0 +0 1 1 +1 0 1 +.table _n93<0> _n93<1> ->_n94 +.default 1 +0 0 0 +.table _n94 ->_n92 +0 1 +1 0 +.table _n8b buttons<*1*> _n92 ->buttons$_n85_n8a$true<*1*> +- - 0 =buttons<*1*> +- - 1 =_n8b +.table ->_n95<0> +0 +.table ->_n95<1> +1 +.table _n95<0> _n8c<0> ->_n97<0> +.default 0 +0 1 1 +1 0 1 +.table _n95<1> _n8c<1> ->_n97<1> +.default 0 +0 1 1 +1 0 1 +.table _n97<0> _n97<1> ->_n98 +.default 1 +0 0 0 +.table _n98 ->_n96 +0 1 +1 0 +.table _n8b buttons<*2*> _n96 ->buttons$_n85_n8a$true<*2*> +- - 0 =buttons<*2*> +- - 1 =_n8b +.table ->_n8b +OFF +.table random_push<0> ->_n9a +.default 1 +0 0 +.table _n9a ->_n99 +- =_n9a +.table ->_n9d<0> +0 +.table ->_n9d<1> +0 +.table ->_n9e<0> +0 +.table ->_n9e<1> +0 +.table _n9e<0> _n9d<0> ->_na0<0> +.default 0 +0 1 1 +1 0 1 +.table _n9e<1> _n9d<1> ->_na0<1> +.default 0 +0 1 1 +1 0 1 +.table _na0<0> _na0<1> ->_na1 +.default 1 +0 0 0 +.table _na1 ->_n9f +0 1 +1 0 +.table _n9c buttons<*0*> _n9f ->buttons$random_push_n9b$true<*0*> +- - 0 =buttons<*0*> +- - 1 =_n9c +.table ->_na2<0> +1 +.table ->_na2<1> +0 +.table _na2<0> _n9d<0> ->_na4<0> +.default 0 +0 1 1 +1 0 1 +.table _na2<1> _n9d<1> ->_na4<1> +.default 0 +0 1 1 +1 0 1 +.table _na4<0> _na4<1> ->_na5 +.default 1 +0 0 0 +.table _na5 ->_na3 +0 1 +1 0 +.table _n9c buttons<*1*> _na3 ->buttons$random_push_n9b$true<*1*> +- - 0 =buttons<*1*> +- - 1 =_n9c +.table ->_na6<0> +0 +.table ->_na6<1> +1 +.table _na6<0> _n9d<0> ->_na8<0> +.default 0 +0 1 1 +1 0 1 +.table _na6<1> _n9d<1> ->_na8<1> +.default 0 +0 1 1 +1 0 1 +.table _na8<0> _na8<1> ->_na9 +.default 1 +0 0 0 +.table _na9 ->_na7 +0 1 +1 0 +.table _n9c buttons<*2*> _na7 ->buttons$random_push_n9b$true<*2*> +- - 0 =buttons<*2*> +- - 1 =_n9c +.table ->_n9c +ON +.table random_push<0> ->_nad +.default 1 +0 0 +.table buttons$random_push_n9b$true<*0*> buttons<*0*> _nad ->buttons$random_push$raw_nac<*0*> +- - 0 =buttons<*0*> +- - 1 =buttons$random_push_n9b$true<*0*> +.table buttons$random_push_n9b$true<*1*> buttons<*1*> _nad ->buttons$random_push$raw_nac<*1*> +- - 0 =buttons<*1*> +- - 1 =buttons$random_push_n9b$true<*1*> +.table buttons$random_push_n9b$true<*2*> buttons<*2*> _nad ->buttons$random_push$raw_nac<*2*> +- - 0 =buttons<*2*> +- - 1 =buttons$random_push_n9b$true<*2*> +.table buttons$_n85_n8a$true<*0*> buttons$random_push$raw_nac<*0*> _n85 ->buttons$_n85$raw_naf<*0*> +- - 0 =buttons$random_push$raw_nac<*0*> +- - 1 =buttons$_n85_n8a$true<*0*> +.table buttons$_n85_n8a$true<*1*> buttons$random_push$raw_nac<*1*> _n85 ->buttons$_n85$raw_naf<*1*> +- - 0 =buttons$random_push$raw_nac<*1*> +- - 1 =buttons$_n85_n8a$true<*1*> +.table buttons$_n85_n8a$true<*2*> buttons$random_push$raw_nac<*2*> _n85 ->buttons$_n85$raw_naf<*2*> +- - 0 =buttons$random_push$raw_nac<*2*> +- - 1 =buttons$_n85_n8a$true<*2*> +.table ->_nb3<0> +1 +.table ->_nb3<1> +0 +.table _nb3<0> location<0> ->_nb4<0> +.default 0 +0 1 1 +1 0 1 +.table _nb3<1> location<1> ->_nb4<1> +.default 0 +0 1 1 +1 0 1 +.table _nb4<0> _nb4<1> ->_nb5 +.default 1 +0 0 0 +.table _nb5 ->_nb2 +0 1 +1 0 +.table _nb2 ->_nb6 +- =_nb2 +.table ->_nb9<0> +1 +.table ->_nb9<1> +0 +.table ->_nba<0> +0 +.table ->_nba<1> +0 +.table _nba<0> _nb9<0> ->_nbc<0> +.default 0 +0 1 1 +1 0 1 +.table _nba<1> _nb9<1> ->_nbc<1> +.default 0 +0 1 1 +1 0 1 +.table _nbc<0> _nbc<1> ->_nbd +.default 1 +0 0 0 +.table _nbd ->_nbb +0 1 +1 0 +.table _nb8 buttons$_n85$raw_naf<*0*> _nbb ->buttons$_nb2_nb7$true<*0*> +- - 0 =buttons$_n85$raw_naf<*0*> +- - 1 =_nb8 +.table ->_nbe<0> +1 +.table ->_nbe<1> +0 +.table _nbe<0> _nb9<0> ->_nc0<0> +.default 0 +0 1 1 +1 0 1 +.table _nbe<1> _nb9<1> ->_nc0<1> +.default 0 +0 1 1 +1 0 1 +.table _nc0<0> _nc0<1> ->_nc1 +.default 1 +0 0 0 +.table _nc1 ->_nbf +0 1 +1 0 +.table _nb8 buttons$_n85$raw_naf<*1*> _nbf ->buttons$_nb2_nb7$true<*1*> +- - 0 =buttons$_n85$raw_naf<*1*> +- - 1 =_nb8 +.table ->_nc2<0> +0 +.table ->_nc2<1> +1 +.table _nc2<0> _nb9<0> ->_nc4<0> +.default 0 +0 1 1 +1 0 1 +.table _nc2<1> _nb9<1> ->_nc4<1> +.default 0 +0 1 1 +1 0 1 +.table _nc4<0> _nc4<1> ->_nc5 +.default 1 +0 0 0 +.table _nc5 ->_nc3 +0 1 +1 0 +.table _nb8 buttons$_n85$raw_naf<*2*> _nc3 ->buttons$_nb2_nb7$true<*2*> +- - 0 =buttons$_n85$raw_naf<*2*> +- - 1 =_nb8 +.table ->_nb8 +OFF +.table random_push<1> ->_nc7 +.default 1 +0 0 +.table _nc7 ->_nc6 +- =_nc7 +.table ->_nca<0> +1 +.table ->_nca<1> +0 +.table ->_ncb<0> +0 +.table ->_ncb<1> +0 +.table _ncb<0> _nca<0> ->_ncd<0> +.default 0 +0 1 1 +1 0 1 +.table _ncb<1> _nca<1> ->_ncd<1> +.default 0 +0 1 1 +1 0 1 +.table _ncd<0> _ncd<1> ->_nce +.default 1 +0 0 0 +.table _nce ->_ncc +0 1 +1 0 +.table _nc9 buttons$_n85$raw_naf<*0*> _ncc ->buttons$random_push_nc8$true<*0*> +- - 0 =buttons$_n85$raw_naf<*0*> +- - 1 =_nc9 +.table ->_ncf<0> +1 +.table ->_ncf<1> +0 +.table _ncf<0> _nca<0> ->_nd1<0> +.default 0 +0 1 1 +1 0 1 +.table _ncf<1> _nca<1> ->_nd1<1> +.default 0 +0 1 1 +1 0 1 +.table _nd1<0> _nd1<1> ->_nd2 +.default 1 +0 0 0 +.table _nd2 ->_nd0 +0 1 +1 0 +.table _nc9 buttons$_n85$raw_naf<*1*> _nd0 ->buttons$random_push_nc8$true<*1*> +- - 0 =buttons$_n85$raw_naf<*1*> +- - 1 =_nc9 +.table ->_nd3<0> +0 +.table ->_nd3<1> +1 +.table _nd3<0> _nca<0> ->_nd5<0> +.default 0 +0 1 1 +1 0 1 +.table _nd3<1> _nca<1> ->_nd5<1> +.default 0 +0 1 1 +1 0 1 +.table _nd5<0> _nd5<1> ->_nd6 +.default 1 +0 0 0 +.table _nd6 ->_nd4 +0 1 +1 0 +.table _nc9 buttons$_n85$raw_naf<*2*> _nd4 ->buttons$random_push_nc8$true<*2*> +- - 0 =buttons$_n85$raw_naf<*2*> +- - 1 =_nc9 +.table ->_nc9 +ON +.table random_push<1> ->_nd8 +.default 1 +0 0 +.table buttons$random_push_nc8$true<*0*> buttons$_n85$raw_naf<*0*> _nd8 ->buttons$random_push$raw_nd7<*0*> +- - 0 =buttons$_n85$raw_naf<*0*> +- - 1 =buttons$random_push_nc8$true<*0*> +.table buttons$random_push_nc8$true<*1*> buttons$_n85$raw_naf<*1*> _nd8 ->buttons$random_push$raw_nd7<*1*> +- - 0 =buttons$_n85$raw_naf<*1*> +- - 1 =buttons$random_push_nc8$true<*1*> +.table buttons$random_push_nc8$true<*2*> buttons$_n85$raw_naf<*2*> _nd8 ->buttons$random_push$raw_nd7<*2*> +- - 0 =buttons$_n85$raw_naf<*2*> +- - 1 =buttons$random_push_nc8$true<*2*> +.table buttons$_nb2_nb7$true<*0*> buttons$random_push$raw_nd7<*0*> _nb2 ->buttons$_nb2$raw_ndc<*0*> +- - 0 =buttons$random_push$raw_nd7<*0*> +- - 1 =buttons$_nb2_nb7$true<*0*> +.table buttons$_nb2_nb7$true<*1*> buttons$random_push$raw_nd7<*1*> _nb2 ->buttons$_nb2$raw_ndc<*1*> +- - 0 =buttons$random_push$raw_nd7<*1*> +- - 1 =buttons$_nb2_nb7$true<*1*> +.table buttons$_nb2_nb7$true<*2*> buttons$random_push$raw_nd7<*2*> _nb2 ->buttons$_nb2$raw_ndc<*2*> +- - 0 =buttons$random_push$raw_nd7<*2*> +- - 1 =buttons$_nb2_nb7$true<*2*> +.table ->_ne1<0> +0 +.table ->_ne1<1> +1 +.table _ne1<0> location<0> ->_ne2<0> +.default 0 +0 1 1 +1 0 1 +.table _ne1<1> location<1> ->_ne2<1> +.default 0 +0 1 1 +1 0 1 +.table _ne2<0> _ne2<1> ->_ne3 +.default 1 +0 0 0 +.table _ne3 ->_ne0 +0 1 +1 0 +.table _ne0 ->_ne4 +- =_ne0 +.table ->_ne7<0> +0 +.table ->_ne7<1> +1 +.table ->_ne8<0> +0 +.table ->_ne8<1> +0 +.table _ne8<0> _ne7<0> ->_nea<0> +.default 0 +0 1 1 +1 0 1 +.table _ne8<1> _ne7<1> ->_nea<1> +.default 0 +0 1 1 +1 0 1 +.table _nea<0> _nea<1> ->_neb +.default 1 +0 0 0 +.table _neb ->_ne9 +0 1 +1 0 +.table _ne6 buttons$_nb2$raw_ndc<*0*> _ne9 ->buttons$_ne0_ne5$true<*0*> +- - 0 =buttons$_nb2$raw_ndc<*0*> +- - 1 =_ne6 +.table ->_nec<0> +1 +.table ->_nec<1> +0 +.table _nec<0> _ne7<0> ->_nee<0> +.default 0 +0 1 1 +1 0 1 +.table _nec<1> _ne7<1> ->_nee<1> +.default 0 +0 1 1 +1 0 1 +.table _nee<0> _nee<1> ->_nef +.default 1 +0 0 0 +.table _nef ->_ned +0 1 +1 0 +.table _ne6 buttons$_nb2$raw_ndc<*1*> _ned ->buttons$_ne0_ne5$true<*1*> +- - 0 =buttons$_nb2$raw_ndc<*1*> +- - 1 =_ne6 +.table ->_nf0<0> +0 +.table ->_nf0<1> +1 +.table _nf0<0> _ne7<0> ->_nf2<0> +.default 0 +0 1 1 +1 0 1 +.table _nf0<1> _ne7<1> ->_nf2<1> +.default 0 +0 1 1 +1 0 1 +.table _nf2<0> _nf2<1> ->_nf3 +.default 1 +0 0 0 +.table _nf3 ->_nf1 +0 1 +1 0 +.table _ne6 buttons$_nb2$raw_ndc<*2*> _nf1 ->buttons$_ne0_ne5$true<*2*> +- - 0 =buttons$_nb2$raw_ndc<*2*> +- - 1 =_ne6 +.table ->_ne6 +OFF +.table random_push<2> ->_nf5 +.default 1 +0 0 +.table _nf5 ->_nf4 +- =_nf5 +.table ->_nf8<0> +0 +.table ->_nf8<1> +1 +.table ->_nf9<0> +0 +.table ->_nf9<1> +0 +.table _nf9<0> _nf8<0> ->_nfb<0> +.default 0 +0 1 1 +1 0 1 +.table _nf9<1> _nf8<1> ->_nfb<1> +.default 0 +0 1 1 +1 0 1 +.table _nfb<0> _nfb<1> ->_nfc +.default 1 +0 0 0 +.table _nfc ->_nfa +0 1 +1 0 +.table _nf7 buttons$_nb2$raw_ndc<*0*> _nfa ->buttons$random_push_nf6$true<*0*> +- - 0 =buttons$_nb2$raw_ndc<*0*> +- - 1 =_nf7 +.table ->_nfd<0> +1 +.table ->_nfd<1> +0 +.table _nfd<0> _nf8<0> ->_nff<0> +.default 0 +0 1 1 +1 0 1 +.table _nfd<1> _nf8<1> ->_nff<1> +.default 0 +0 1 1 +1 0 1 +.table _nff<0> _nff<1> ->_n100 +.default 1 +0 0 0 +.table _n100 ->_nfe +0 1 +1 0 +.table _nf7 buttons$_nb2$raw_ndc<*1*> _nfe ->buttons$random_push_nf6$true<*1*> +- - 0 =buttons$_nb2$raw_ndc<*1*> +- - 1 =_nf7 +.table ->_n101<0> +0 +.table ->_n101<1> +1 +.table _n101<0> _nf8<0> ->_n103<0> +.default 0 +0 1 1 +1 0 1 +.table _n101<1> _nf8<1> ->_n103<1> +.default 0 +0 1 1 +1 0 1 +.table _n103<0> _n103<1> ->_n104 +.default 1 +0 0 0 +.table _n104 ->_n102 +0 1 +1 0 +.table _nf7 buttons$_nb2$raw_ndc<*2*> _n102 ->buttons$random_push_nf6$true<*2*> +- - 0 =buttons$_nb2$raw_ndc<*2*> +- - 1 =_nf7 +.table ->_nf7 +ON +.table random_push<2> ->_n106 +.default 1 +0 0 +.table buttons$random_push_nf6$true<*0*> buttons$_nb2$raw_ndc<*0*> _n106 ->buttons$random_push$raw_n105<*0*> +- - 0 =buttons$_nb2$raw_ndc<*0*> +- - 1 =buttons$random_push_nf6$true<*0*> +.table buttons$random_push_nf6$true<*1*> buttons$_nb2$raw_ndc<*1*> _n106 ->buttons$random_push$raw_n105<*1*> +- - 0 =buttons$_nb2$raw_ndc<*1*> +- - 1 =buttons$random_push_nf6$true<*1*> +.table buttons$random_push_nf6$true<*2*> buttons$_nb2$raw_ndc<*2*> _n106 ->buttons$random_push$raw_n105<*2*> +- - 0 =buttons$_nb2$raw_ndc<*2*> +- - 1 =buttons$random_push_nf6$true<*2*> +.table buttons$_ne0_ne5$true<*0*> buttons$random_push$raw_n105<*0*> _ne0 ->buttons$_ne0$raw_n10a<*0*> +- - 0 =buttons$random_push$raw_n105<*0*> +- - 1 =buttons$_ne0_ne5$true<*0*> +.table buttons$_ne0_ne5$true<*1*> buttons$random_push$raw_n105<*1*> _ne0 ->buttons$_ne0$raw_n10a<*1*> +- - 0 =buttons$random_push$raw_n105<*1*> +- - 1 =buttons$_ne0_ne5$true<*1*> +.table buttons$_ne0_ne5$true<*2*> buttons$random_push$raw_n105<*2*> _ne0 ->buttons$_ne0$raw_n10a<*2*> +- - 0 =buttons$random_push$raw_n105<*2*> +- - 1 =buttons$_ne0_ne5$true<*2*> +.table stop_next ->_n10e +- =stop_next +.table ->_n110 +UP +.table direction _n110 ->_n10f +.default 0 +- =direction 1 +.table _n10f ->_n111 +- =_n10f +.table ->_n113<0> +1 +.table ->_n113<1> +0 +.table ->_n115 +0 +.table location<0> _n113<0> _n115 ->_n114<0> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table ->_n117 +0 +.table location<0> _n113<0> _n117 ->_n116 +.default 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.table location<1> _n113<1> _n116 ->_n114<1> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table ->_n119<0> +0 +.table ->_n119<1> +0 +.table _n119<0> _n114<0> ->_n11b<0> +.default 0 +0 1 1 +1 0 1 +.table _n119<1> _n114<1> ->_n11b<1> +.default 0 +0 1 1 +1 0 1 +.table _n11b<0> _n11b<1> ->_n11c +.default 1 +0 0 0 +.table _n11c ->_n11a +0 1 +1 0 +.table _n118 buttons$_ne0$raw_n10a<*0*> _n11a ->buttons$_n10f_n112$true<*0*> +- - 0 =buttons$_ne0$raw_n10a<*0*> +- - 1 =_n118 +.table ->_n11d<0> +1 +.table ->_n11d<1> +0 +.table _n11d<0> _n114<0> ->_n11f<0> +.default 0 +0 1 1 +1 0 1 +.table _n11d<1> _n114<1> ->_n11f<1> +.default 0 +0 1 1 +1 0 1 +.table _n11f<0> _n11f<1> ->_n120 +.default 1 +0 0 0 +.table _n120 ->_n11e +0 1 +1 0 +.table _n118 buttons$_ne0$raw_n10a<*1*> _n11e ->buttons$_n10f_n112$true<*1*> +- - 0 =buttons$_ne0$raw_n10a<*1*> +- - 1 =_n118 +.table ->_n121<0> +0 +.table ->_n121<1> +1 +.table _n121<0> _n114<0> ->_n123<0> +.default 0 +0 1 1 +1 0 1 +.table _n121<1> _n114<1> ->_n123<1> +.default 0 +0 1 1 +1 0 1 +.table _n123<0> _n123<1> ->_n124 +.default 1 +0 0 0 +.table _n124 ->_n122 +0 1 +1 0 +.table _n118 buttons$_ne0$raw_n10a<*2*> _n122 ->buttons$_n10f_n112$true<*2*> +- - 0 =buttons$_ne0$raw_n10a<*2*> +- - 1 =_n118 +.table ->_n118 +ON +.table ->_n126<0> +1 +.table ->_n126<1> +0 +.table ->_n128 +0 +.table location<0> _n126<0> _n128 ->_n127<0> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table ->_n12a +0 +.table location<0> _n126<0> _n12a ->_n129 +.default 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.table location<1> _n126<1> _n129 ->_n127<1> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table ->_n12c<0> +0 +.table ->_n12c<1> +0 +.table _n12c<0> _n127<0> ->_n12e<0> +.default 0 +0 1 1 +1 0 1 +.table _n12c<1> _n127<1> ->_n12e<1> +.default 0 +0 1 1 +1 0 1 +.table _n12e<0> _n12e<1> ->_n12f +.default 1 +0 0 0 +.table _n12f ->_n12d +0 1 +1 0 +.table _n12b buttons$_ne0$raw_n10a<*0*> _n12d ->buttons$_n10f_n125$false<*0*> +- - 0 =buttons$_ne0$raw_n10a<*0*> +- - 1 =_n12b +.table ->_n130<0> +1 +.table ->_n130<1> +0 +.table _n130<0> _n127<0> ->_n132<0> +.default 0 +0 1 1 +1 0 1 +.table _n130<1> _n127<1> ->_n132<1> +.default 0 +0 1 1 +1 0 1 +.table _n132<0> _n132<1> ->_n133 +.default 1 +0 0 0 +.table _n133 ->_n131 +0 1 +1 0 +.table _n12b buttons$_ne0$raw_n10a<*1*> _n131 ->buttons$_n10f_n125$false<*1*> +- - 0 =buttons$_ne0$raw_n10a<*1*> +- - 1 =_n12b +.table ->_n134<0> +0 +.table ->_n134<1> +1 +.table _n134<0> _n127<0> ->_n136<0> +.default 0 +0 1 1 +1 0 1 +.table _n134<1> _n127<1> ->_n136<1> +.default 0 +0 1 1 +1 0 1 +.table _n136<0> _n136<1> ->_n137 +.default 1 +0 0 0 +.table _n137 ->_n135 +0 1 +1 0 +.table _n12b buttons$_ne0$raw_n10a<*2*> _n135 ->buttons$_n10f_n125$false<*2*> +- - 0 =buttons$_ne0$raw_n10a<*2*> +- - 1 =_n12b +.table ->_n12b +ON +.table buttons$_n10f_n112$true<*0*> buttons$_n10f_n125$false<*0*> _n10f ->buttons$_n10f$raw_n138<*0*> +- - 0 =buttons$_n10f_n125$false<*0*> +- - 1 =buttons$_n10f_n112$true<*0*> +.table buttons$_n10f_n112$true<*1*> buttons$_n10f_n125$false<*1*> _n10f ->buttons$_n10f$raw_n138<*1*> +- - 0 =buttons$_n10f_n125$false<*1*> +- - 1 =buttons$_n10f_n112$true<*1*> +.table buttons$_n10f_n112$true<*2*> buttons$_n10f_n125$false<*2*> _n10f ->buttons$_n10f$raw_n138<*2*> +- - 0 =buttons$_n10f_n125$false<*2*> +- - 1 =buttons$_n10f_n112$true<*2*> +.table buttons$_n10f$raw_n138<*0*> buttons$_ne0$raw_n10a<*0*> stop_next ->buttons$stop_next$raw_n13c<*0*> +- - 0 =buttons$_ne0$raw_n10a<*0*> +- - 1 =buttons$_n10f$raw_n138<*0*> +.table buttons$_n10f$raw_n138<*1*> buttons$_ne0$raw_n10a<*1*> stop_next ->buttons$stop_next$raw_n13c<*1*> +- - 0 =buttons$_ne0$raw_n10a<*1*> +- - 1 =buttons$_n10f$raw_n138<*1*> +.table buttons$_n10f$raw_n138<*2*> buttons$_ne0$raw_n10a<*2*> stop_next ->buttons$stop_next$raw_n13c<*2*> +- - 0 =buttons$_ne0$raw_n10a<*2*> +- - 1 =buttons$_n10f$raw_n138<*2*> +.table ->_n141 +CLOSED +.table door _n141 ->_n140 +.default 1 +- =door 0 +.table _n140 ->_n142 +- =_n140 +.table ->open_next$_n140_n143$true +0 +.table ->_n145 +MOVING +.table movement _n145 ->_n144 +.default 0 +- =movement 1 +.table ->_n147 +UP +.table direction _n147 ->_n146 +.default 0 +- =direction 1 +.table ->_n149<0> +1 +.table ->_n149<1> +0 +.table ->_n14b +0 +.table location<0> _n149<0> _n14b ->_n14a<0> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table ->_n14d +0 +.table location<0> _n149<0> _n14d ->_n14c +.default 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.table location<1> _n149<1> _n14c ->_n14a<1> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table buttons<*0*> buttons<*1*> buttons<*2*> _n14a<1> _n14a<0> ->_n14e +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.table ->_n14f +ON +.table _n14e _n14f ->_n148 +.default 0 +- =_n14e 1 +.table _n146 _n148 ->_n150 +.default 0 +1 1 1 +.table stop_next _n150 ->_n151 +.default 1 +0 0 0 +.table ->_n153 +DOWN +.table direction _n153 ->_n152 +.default 0 +- =direction 1 +.table ->_n155<0> +1 +.table ->_n155<1> +0 +.table ->_n157 +0 +.table location<0> _n155<0> _n157 ->_n156<0> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table ->_n159 +0 +.table location<0> _n155<0> _n159 ->_n158 +.default 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.table location<1> _n155<1> _n158 ->_n156<1> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table buttons<*0*> buttons<*1*> buttons<*2*> _n156<1> _n156<0> ->_n15a +- - - 0 0 =buttons<*0*> +- - - 0 1 =buttons<*1*> +- - - 1 0 =buttons<*2*> +- - - 1 1 ON +.table ->_n15b +ON +.table _n15a _n15b ->_n154 +.default 0 +- =_n15a 1 +.table _n152 _n154 ->_n15c +.default 0 +1 1 1 +.table _n151 _n15c ->_n15d +.default 1 +0 0 0 +.table _n144 _n15d ->_n15e +.default 0 +1 1 1 +.table _n15e ->_n15f +- =_n15e +.table ->open_next$_n15e_n160$true +1 +.table open_next$_n15e_n160$true open_next _n15e ->open_next$_n15e$raw_n163 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table open_next$_n140_n143$true open_next$_n15e$raw_n163 _n140 ->open_next$_n140$raw_n166 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table ->random +0 +1 +.table ->_n16e +CLOSED +.table door _n16e ->_n16d +.default 0 +- =door 1 +.table _n16d ->_n16c +1 1 +0 0 +.table ->_n170 +STOPPED +.table movement _n170 ->_n16f +.default 0 +- =movement 1 +.table open_next _n16f ->_n171 +.default 0 +1 1 1 +.table _n171 ->_n172 +- =_n171 +.table ->door$_n171_n173$true +OPENING +.table door$_n171_n173$true door _n171 ->door$_n171$raw_n176 +- - 0 =door +- - 1 =door$_n171_n173$true +.table ->_n179 +OPENING +.table door _n179 ->_n178 +.default 0 +- =door 1 +.table _n178 ->_n177 +1 1 +0 0 +.table random ->_n17a +- =random +.table ->door$random_n17b$true +OPEN +.table door$random_n17b$true door random ->door$random$raw_n17e +- - 0 =door +- - 1 =door$random_n17b$true +.table ->_n181 +OPEN +.table door _n181 ->_n180 +.default 0 +- =door 1 +.table _n180 ->_n17f +1 1 +0 0 +.table random ->_n182 +- =random +.table ->door$random_n183$true +CLOSING +.table door$random_n183$true door random ->door$random$raw_n186 +- - 0 =door +- - 1 =door$random_n183$true +.table ->_n189 +CLOSING +.table door _n189 ->_n188 +.default 0 +- =door 1 +.table _n188 ->_n187 +1 1 +0 0 +.table random ->_n18a +- =random +.table ->door$random_n18b$true +CLOSED +.table door$random_n18b$true door random ->door$random$raw_n18e +- - 0 =door +- - 1 =door$random_n18b$true +.table door$random$raw_n18e door _n187 ->door$_n187$raw_n191 +- - 0 =door +- - 1 =door$random$raw_n18e +.table door$random$raw_n186 door$_n187$raw_n191 _n17f ->door$_n17f$raw_n192 +- - 0 =door$_n187$raw_n191 +- - 1 =door$random$raw_n186 +.table door$random$raw_n17e door$_n17f$raw_n192 _n177 ->door$_n177$raw_n196 +- - 0 =door$_n17f$raw_n192 +- - 1 =door$random$raw_n17e +.table door$_n171$raw_n176 door$_n177$raw_n196 _n16c ->door$_n16c$raw_n19a +- - 0 =door$_n177$raw_n196 +- - 1 =door$_n171$raw_n176 +.table ->_n1a0 +UP +.table direction _n1a0 ->_n19f +.default 0 +- =direction 1 +.table button_above _n19f ->_n1a1 +.default 0 +1 1 1 +.table continue _n1a1 ->_n1a2 +.default 1 +0 0 0 +.table ->_n1a4 +DOWN +.table direction _n1a4 ->_n1a3 +.default 0 +- =direction 1 +.table button_below _n1a3 ->_n1a5 +.default 0 +1 1 1 +.table _n1a2 _n1a5 ->_n1a6 +.default 1 +0 0 0 +.table _n1a6 ->start_moving$raw_n19e +- =_n1a6 +.table ->r_stop +0 +1 +.table ->_n1ab +MOVING +.table movement _n1ab ->_n1aa +.default 0 +- =movement 1 +.table r_stop _n1aa ->_n1ac +.default 0 +1 1 1 +.table _n1ac ->stop_moving$raw_n1a9 +- =_n1ac +.table ->_n1af +UP +.table direction _n1af ->_n1ae +.default 0 +- =direction 1 +.table stop_moving _n1ae ->_n1b0 +.default 0 +1 1 1 +.table _n1b0 ->inc$raw_n1ad +- =_n1b0 +.table ->_n1b3 +DOWN +.table direction _n1b3 ->_n1b2 +.default 0 +- =direction 1 +.table stop_moving _n1b2 ->_n1b4 +.default 0 +1 1 1 +.table _n1b4 ->dec$raw_n1b1 +- =_n1b4 +.table ->_n1b6 +CLOSED +.table door _n1b6 ->_n1b5 +.default 0 +- =door 1 +.table _n1b5 ->_n1b7 +- =_n1b5 +.table ->_n1ba +STOPPED +.table movement _n1ba ->_n1b9 +.default 0 +- =movement 1 +.table _n1b9 ->_n1b8 +1 1 +0 0 +.table ->_n1bc +CLOSED +.table door _n1bc ->_n1bb +.default 0 +- =door 1 +.table _n1bb start_moving ->_n1bd +.default 0 +1 1 1 +.table open_next ->_n1be +0 1 +1 0 +.table _n1bd _n1be ->_n1bf +.default 0 +1 1 1 +.table _n1bf ->_n1c0 +- =_n1bf +.table ->movement$_n1bf_n1c1$true +MOVING +.table movement$_n1bf_n1c1$true movement _n1bf ->movement$_n1bf$raw_n1c4 +- - 0 =movement +- - 1 =movement$_n1bf_n1c1$true +.table ->_n1c7 +MOVING +.table movement _n1c7 ->_n1c6 +.default 0 +- =movement 1 +.table _n1c6 ->_n1c5 +1 1 +0 0 +.table stop_moving ->_n1c8 +- =stop_moving +.table ->movement$stop_moving_n1c9$true +STOPPED +.table ->_n1cb +UP +.table direction _n1cb ->_n1ca +.default 0 +- =direction 1 +.table _n1ca ->_n1cc +- =_n1ca +.table ->_n1ce<0> +1 +.table ->_n1ce<1> +0 +.table ->_n1d0 +0 +.table location<0> _n1ce<0> _n1d0 ->_n1cf<0> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table ->_n1d2 +0 +.table location<0> _n1ce<0> _n1d2 ->_n1d1 +.default 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.table location<1> _n1ce<1> _n1d1 ->_n1cf<1> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table _n1cf<0> ->location$_n1ca_n1cd$true<0> +- =_n1cf<0> +.table _n1cf<1> ->location$_n1ca_n1cd$true<1> +- =_n1cf<1> +.table location$_n1ca_n1cd$true<0> location<0> _n1ca ->location$_n1ca$raw_n1d8<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table location$_n1ca_n1cd$true<1> location<1> _n1ca ->location$_n1ca$raw_n1d8<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table ->_n1dd +DOWN +.table direction _n1dd ->_n1dc +.default 0 +- =direction 1 +.table _n1dc ->_n1de +- =_n1dc +.table ->_n1e0<0> +1 +.table ->_n1e0<1> +0 +.table ->_n1e2 +0 +.table location$_n1ca$raw_n1d8<0> _n1e0<0> _n1e2 ->_n1e1<0> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table ->_n1e4 +0 +.table location$_n1ca$raw_n1d8<0> _n1e0<0> _n1e4 ->_n1e3 +.default 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.table location$_n1ca$raw_n1d8<1> _n1e0<1> _n1e3 ->_n1e1<1> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table _n1e1<0> ->location$_n1dc_n1df$true<0> +- =_n1e1<0> +.table _n1e1<1> ->location$_n1dc_n1df$true<1> +- =_n1e1<1> +.table location$_n1dc_n1df$true<0> location$_n1ca$raw_n1d8<0> _n1dc ->location$_n1dc$raw_n1e6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table location$_n1dc_n1df$true<1> location$_n1ca$raw_n1d8<1> _n1dc ->location$_n1dc$raw_n1e6<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table movement$stop_moving_n1c9$true movement stop_moving ->movement$stop_moving$raw_n1f3 +- - 0 =movement +- - 1 =movement$stop_moving_n1c9$true +.table location$_n1dc$raw_n1e6<0> location<0> stop_moving ->location$stop_moving$raw_n1f4<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table location$_n1dc$raw_n1e6<1> location<1> stop_moving ->location$stop_moving$raw_n1f4<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table movement$stop_moving$raw_n1f3 movement _n1c5 ->movement$_n1c5$raw_n1fb +- - 0 =movement +- - 1 =movement$stop_moving$raw_n1f3 +.table location$stop_moving$raw_n1f4<0> location<0> _n1c5 ->location$_n1c5$raw_n1fc<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table location$stop_moving$raw_n1f4<1> location<1> _n1c5 ->location$_n1c5$raw_n1fc<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table movement$_n1bf$raw_n1c4 movement$_n1c5$raw_n1fb _n1b8 ->movement$_n1b8$raw_n1ff +- - 0 =movement$_n1c5$raw_n1fb +- - 1 =movement$_n1bf$raw_n1c4 +.table location<0> location$_n1c5$raw_n1fc<0> _n1b8 ->location$_n1b8$raw_n203<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table location<1> location$_n1c5$raw_n1fc<1> _n1b8 ->location$_n1b8$raw_n203<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table movement$_n1b8$raw_n1ff movement _n1b5 ->movement$_n1b5$raw_n20a +- - 0 =movement +- - 1 =movement$_n1b8$raw_n1ff +.table location$_n1b8$raw_n203<0> location<0> _n1b5 ->location$_n1b5$raw_n20b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table location$_n1b8$raw_n203<1> location<1> _n1b5 ->location$_n1b5$raw_n20b<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.table ->_n210 +UP +.table direction _n210 ->_n20f +.default 0 +- =direction 1 +.table _n20f ->_n20e +1 1 +0 0 +.table button_above ->_n211 +0 1 +1 0 +.table continue ->_n212 +0 1 +1 0 +.table _n211 _n212 ->_n213 +.default 0 +1 1 1 +.table _n213 ->_n214 +- =_n213 +.table ->direction$_n213_n215$true +DOWN +.table direction$_n213_n215$true direction _n213 ->direction$_n213$raw_n218 +- - 0 =direction +- - 1 =direction$_n213_n215$true +.table ->_n21b +DOWN +.table direction _n21b ->_n21a +.default 0 +- =direction 1 +.table _n21a ->_n219 +1 1 +0 0 +.table button_below ->_n21c +0 1 +1 0 +.table continue ->_n21d +0 1 +1 0 +.table _n21c _n21d ->_n21e +.default 0 +1 1 1 +.table _n21e ->_n21f +- =_n21e +.table ->direction$_n21e_n220$true +UP +.table direction$_n21e_n220$true direction _n21e ->direction$_n21e$raw_n223 +- - 0 =direction +- - 1 =direction$_n21e_n220$true +.table direction$_n21e$raw_n223 direction _n219 ->direction$_n219$raw_n226 +- - 0 =direction +- - 1 =direction$_n21e$raw_n223 +.table direction$_n213$raw_n218 direction$_n219$raw_n226 _n20e ->direction$_n20e$raw_n227 +- - 0 =direction$_n219$raw_n226 +- - 1 =direction$_n213$raw_n218 +.table ->_n22c<0> +1 +.table ->_n22c<1> +1 +.table ->_n22d<0> +1 +.table ->_n22d<1> +0 +.table ->_n22f +0 +.table _n22c<0> _n22d<0> _n22f ->_n22e<0> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table ->_n231 +0 +.table _n22c<0> _n22d<0> _n231 ->_n230 +.default 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.table _n22c<1> _n22d<1> _n230 ->_n22e<1> +.default 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.table location<0> _n22e<0> ->_n232<0> +.default 0 +0 1 1 +1 0 1 +.table location<1> _n22e<1> ->_n232<1> +.default 0 +0 1 1 +1 0 1 +.table _n232<0> _n232<1> ->_n233 +.default 1 +0 0 0 +.table _n233 ->_n22b +0 1 +1 0 +.table _n22b ->_n234 +- =_n22b +.table ->direction$_n22b_n235$true +DOWN +.table direction$_n22b_n235$true direction$_n20e$raw_n227 _n22b ->direction$_n22b$raw_n236 +- - 0 =direction$_n20e$raw_n227 +- - 1 =direction$_n22b_n235$true +.table ->_n23b<0> +0 +.table ->_n23b<1> +0 +.table location<0> _n23b<0> ->_n23c<0> +.default 0 +0 1 1 +1 0 1 +.table location<1> _n23b<1> ->_n23c<1> +.default 0 +0 1 1 +1 0 1 +.table _n23c<0> _n23c<1> ->_n23d +.default 1 +0 0 0 +.table _n23d ->_n23a +0 1 +1 0 +.table _n23a ->_n23e +- =_n23a +.table ->direction$_n23a_n23f$true +UP +.table direction$_n23a_n23f$true direction$_n22b$raw_n236 _n23a ->direction$_n23a$raw_n240 +- - 0 =direction$_n22b$raw_n236 +- - 1 =direction$_n23a_n23f$true +.table button_above$raw_n6c ->button_above +0 0 +1 1 +.table _n1b7 _n1b8 _n1c0 _n1c5 _n1c8 ->_n244 +.default 0 +1 1 1 - - 1 +1 0 - 1 1 1 +.table _n244 movement$_n1b5$raw_n20a movement ->_n245 +1 - - =movement$_n1b5$raw_n20a +0 - - =movement +.table _n89 _n99 _nb6 _nc6 _ne4 _nf4 _n10e _n111 ->_n25b +.default 0 +1 - - - - - - - 1 +0 1 - - - - - - 1 +- - 1 - - - - - 1 +- - 0 1 - - - - 1 +- - - - 1 - - - 1 +- - - - 0 1 - - 1 +- - - - - - 1 1 1 +- - - - - - 1 0 1 +.table _n25b buttons$stop_next$raw_n13c<*0*> buttons<*0*> ->_n25c<*0*> +1 - - =buttons$stop_next$raw_n13c<*0*> +0 - - =buttons<*0*> +.table _n25b buttons$stop_next$raw_n13c<*1*> buttons<*1*> ->_n25c<*1*> +1 - - =buttons$stop_next$raw_n13c<*1*> +0 - - =buttons<*1*> +.table _n25b buttons$stop_next$raw_n13c<*2*> buttons<*2*> ->_n25c<*2*> +1 - - =buttons$stop_next$raw_n13c<*2*> +0 - - =buttons<*2*> +.table start_moving$raw_n19e ->start_moving +0 0 +1 1 +.table _n16c _n172 _n177 _n17a _n17f _n182 _n187 _n18a ->_n29c +.default 0 +1 1 - - - - - - 1 +0 - 1 1 - - - - 1 +0 - 0 - 1 1 - - 1 +0 - 0 - 0 - 1 1 1 +.table _n29c door$_n16c$raw_n19a door ->_n29d +1 - - =door$_n16c$raw_n19a +0 - - =door +.table stop_moving$raw_n1a9 ->stop_moving +0 0 +1 1 +.table _n1b7 _n1b8 _n1c5 _n1c8 _n1cc _n1de ->_n2b3 +.default 0 +1 0 1 1 1 - 1 +1 0 1 1 - 1 1 +.table _n2b3 location$_n1b5$raw_n20b<0> location$_n1b5$raw_n20b<1> location<0> location<1> ->_n2b4<0> _n2b4<1> +1 - - - - =location$_n1b5$raw_n20b<0> =location$_n1b5$raw_n20b<1> +0 - - - - =location<0> =location<1> +.table button_below$raw_n53 ->button_below +0 0 +1 1 +.table _n20e _n214 _n219 _n21f _n234 _n23e ->_n2b5 +.default 0 +1 1 - - - - 1 +0 - 1 1 - - 1 +- - - - 1 - 1 +- - - - - 1 1 +.table _n2b5 direction$_n23a$raw_n240 direction ->_n2b6 +1 - - =direction$_n23a$raw_n240 +0 - - =direction +.table _n142 _n15f ->_n2cc +.default 0 +1 - 1 +0 1 1 +.table _n2cc open_next$_n140$raw_n166 open_next ->_n2cd +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.table dec$raw_n1b1 ->dec +0 0 +1 1 +.table inc$raw_n1ad ->inc +0 0 +1 1 +.end Index: vis_dev/vis-2.1/examples/elevator/order =================================================================== --- vis_dev/vis-2.1/examples/elevator/order (revision 11) +++ vis_dev/vis-2.1/examples/elevator/order (revision 11) @@ -0,0 +1,85 @@ +# vis release 1.2 (compiled 19-Feb-97 at 7:27 PM) +# network name: main +# generated: Wed Feb 19 19:49:23 1997 +# +# name type mddId vals levs +init22<1> pseudo-input 1 2 (0) +init22<0> pseudo-input 2 2 (1) +init11<1> pseudo-input 3 2 (2) +init11<0> pseudo-input 4 2 (3) +e1.door latch 7 4 (4, 5) +e1.door$NS shadow 8 4 (6, 7) +e1.movement latch 16 2 (8) +e1.movement$NS shadow 17 2 (9) +e1.r_stop pseudo-input 24 2 (10) +e1.open_next$NS shadow 6 2 (11) +e1.open_next latch 5 2 (12) +e1.random pseudo-input 9 2 (13) +e2.door latch 33 4 (14, 16) +e2.door$NS shadow 34 4 (15, 17) +e2.movement latch 14 2 (18) +e2.movement$NS shadow 15 2 (19) +e2.r_stop pseudo-input 13 2 (20) +e1.location<0> latch 20 2 (21) +e1.location<0>$NS shadow 21 2 (22) +e1.buttons<*1*>$NS shadow 11 2 (23) +e1.buttons<*1*> latch 10 2 (24) +e1.location<1> latch 18 2 (25) +e1.location<1>$NS shadow 19 2 (26) +e1.direction latch 22 2 (27) +e1.direction$NS shadow 23 2 (28) +e2.open_next latch 31 2 (29) +e2.open_next$NS shadow 32 2 (30) +e2.random pseudo-input 0 2 (31) +e2.location<0> latch 48 2 (32) +e2.location<0>$NS shadow 49 2 (33) +e2.location<1> latch 46 2 (34) +e2.location<1>$NS shadow 47 2 (35) +e2.direction latch 35 2 (36) +e2.direction$NS shadow 36 2 (37) +e2.random_push<0> pseudo-input 45 2 (38) +e2.buttons<*0*>$NS shadow 44 2 (39) +e2.buttons<*0*> latch 43 2 (40) +e2.random_push<2> pseudo-input 37 2 (41) +e2.buttons<*2*>$NS shadow 40 2 (42) +e2.buttons<*2*> latch 39 2 (43) +e2.random_push<1> pseudo-input 38 2 (44) +e2.buttons<*1*>$NS shadow 42 2 (45) +e2.buttons<*1*> latch 41 2 (46) +e1.random_push<0> pseudo-input 30 2 (47) +e1.buttons<*0*>$NS shadow 29 2 (48) +e1.buttons<*0*> latch 28 2 (49) +e1.random_push<2> pseudo-input 27 2 (50) +e1.buttons<*2*>$NS shadow 26 2 (51) +e1.buttons<*2*> latch 25 2 (52) +main_control.locations<*2*><0>$NS shadow 59 2 (53) +main_control.locations<*2*><0> latch 58 2 (54) +main_control.locations<*2*><1> latch 54 2 (55) +main_control.locations<*2*><1>$NS shadow 55 2 (56) +main_control.direction<*2*> latch 50 2 (57) +main_control.direction<*2*>$NS shadow 51 2 (58) +main_control.random_up<1> pseudo-input 63 2 (59) +main_control.random_down<1> pseudo-input 65 2 (60) +e1.random_push<1> pseudo-input 12 2 (61) +main_control.direction<*1*>$NS shadow 53 2 (62) +main_control.direction<*1*> latch 52 2 (63) +main_control.locations<*1*><1> latch 56 2 (64) +main_control.locations<*1*><1>$NS shadow 57 2 (65) +main_control.random_down<0> pseudo-input 72 2 (66) +main_control.random_up<0> pseudo-input 79 2 (67) +main_control.locations<*1*><0>$NS shadow 61 2 (68) +main_control.locations<*1*><0> latch 60 2 (69) +main_control.random_up<2> pseudo-input 62 2 (70) +main_control.random_down<2> pseudo-input 64 2 (71) +main_control.down_floor_buttons<*1*> latch 68 2 (72) +main_control.down_floor_buttons<*1*>$NS shadow 69 2 (73) +main_control.down_floor_buttons<*0*>$NS shadow 71 2 (74) +main_control.down_floor_buttons<*0*> latch 70 2 (75) +main_control.down_floor_buttons<*2*> latch 66 2 (76) +main_control.down_floor_buttons<*2*>$NS shadow 67 2 (77) +main_control.up_floor_buttons<*2*> latch 73 2 (78) +main_control.up_floor_buttons<*2*>$NS shadow 74 2 (79) +main_control.up_floor_buttons<*1*> latch 75 2 (80) +main_control.up_floor_buttons<*1*>$NS shadow 76 2 (81) +main_control.up_floor_buttons<*0*>$NS shadow 78 2 (82) +main_control.up_floor_buttons<*0*> latch 77 2 (83) Index: vis_dev/vis-2.1/examples/exampleS/affalse =================================================================== --- vis_dev/vis-2.1/examples/exampleS/affalse (revision 11) +++ vis_dev/vis-2.1/examples/exampleS/affalse (revision 11) @@ -0,0 +1,1 @@ +AF FALSE; Index: vis_dev/vis-2.1/examples/exampleS/agtrue =================================================================== --- vis_dev/vis-2.1/examples/exampleS/agtrue (revision 11) +++ vis_dev/vis-2.1/examples/exampleS/agtrue (revision 11) @@ -0,0 +1,2 @@ +AG(TRUE); +#AG( (.s.exit1=0) + (.s.exit1=1) ); Index: vis_dev/vis-2.1/examples/exampleS/check_result =================================================================== --- vis_dev/vis-2.1/examples/exampleS/check_result (revision 11) +++ vis_dev/vis-2.1/examples/exampleS/check_result (revision 11) @@ -0,0 +1,6 @@ +FSM depth = 10 +reachable states = 21 +# LE: language is not empty +# MC: formula failed --- AF(FALSE) +# LE: language is not empty +# MC: formula passed --- AG(TRUE) Index: vis_dev/vis-2.1/examples/exampleS/check_script =================================================================== --- vis_dev/vis-2.1/examples/exampleS/check_script (revision 11) +++ vis_dev/vis-2.1/examples/exampleS/check_script (revision 11) @@ -0,0 +1,12 @@ +read_blif_mv exampleS.mv +init_verify +compute_reach -v 1 +print_fairness +lang_empty -d 0 +model_check -d 0 affalse +read_fairness exampleS.fair +print_fairness +lang_empty -d 0 +model_check -d 0 agtrue +time +quit -s Index: vis_dev/vis-2.1/examples/exampleS/exampleS.fair =================================================================== --- vis_dev/vis-2.1/examples/exampleS/exampleS.fair (revision 11) +++ vis_dev/vis-2.1/examples/exampleS/exampleS.fair (revision 11) @@ -0,0 +1,12 @@ +#.model resource +#.state st2 = m_st:U +#.state st3 = r_st:I +#.negfair +#.subsets {st2} +#.subsets {st3} +#.endfair +#.endmodel +## TESLA ver 0.2 +# assertion 0: req implies (req until grant) then (use until release) +!(m_st=D); +!(r_st=I); Index: vis_dev/vis-2.1/examples/exampleS/exampleS.mv =================================================================== --- vis_dev/vis-2.1/examples/exampleS/exampleS.mv (revision 11) +++ vis_dev/vis-2.1/examples/exampleS/exampleS.mv (revision 11) @@ -0,0 +1,1143 @@ +# vl2mv exampleS.v +# version: 0.2 +# date: 11:15:09 12/11/95 (PST) +.model resource +# I/O ports + +.mv r_st 2 I B +.mv r_m_st 4 R G U D +.mv m_st 4 R G U D +.mv r_r_st 2 I B +.subckt a0 a0 req=req grant=grant use=use release=release +# assign req = (m_st == R ) +.mv _n2 4 R G U D +.names _n2 +R +# m_st == 0 +.names m_st _n2 _n1 +.def 0 +- =m_st 1 +.names _n1 req$raw_n0 +- =_n1 +# assign use = (m_st == U ) +.mv _n5 4 R G U D +.names _n5 +U +# m_st == 2 +.names m_st _n5 _n4 +.def 0 +- =m_st 1 +.names _n4 use$raw_n3 +- =_n4 +# assign release = (m_st == D ) +.mv _n8 4 R G U D +.names _n8 +D +# m_st == 3 +.names m_st _n8 _n7 +.def 0 +- =m_st 1 +.names _n7 release$raw_n6 +- =_n7 +# m_st = 0 +.mv m_st$raw_n9 4 R G U D +.names m_st$raw_n9 +R +# non-blocking assignments for initial +# assign r_m_st = $NDset ( 2,3 ) +.names r_m_st +U +D +.mv _ne 4 R G U D +.names _ne +R +.names m_st _ne _nd +.def 0 +- =m_st 1 +.names _nd _nc +1 1 +0 0 +.names grant _nf +- =grant +# m_st = 1 +.mv m_st$grant_n10$true 4 R G U D +.names m_st$grant_n10$true +G +# if/else (grant ) +.mv m_st$grant$raw_n13 4 R G U D +.names m_st$grant_n10$true m_st grant m_st$grant$raw_n13 +- - 0 =m_st +- - 1 =m_st$grant_n10$true +.mv _n16 4 R G U D +.names _n16 +G +.names m_st _n16 _n15 +.def 0 +- =m_st 1 +.names _n15 _n14 +1 1 +0 0 +# m_st = 2 +.mv m_st$_n14_n17$true 4 R G U D +.names m_st$_n14_n17$true +U +.mv _n1a 4 R G U D +.names _n1a +U +.names m_st _n1a _n19 +.def 0 +- =m_st 1 +.names _n19 _n18 +1 1 +0 0 +# m_st = r_m_st +.mv m_st$_n18_n1b$true 4 R G U D +.names r_m_st m_st$_n18_n1b$true +- =r_m_st +.mv _n1e 4 R G U D +.names _n1e +D +.names m_st _n1e _n1d +.def 0 +- =m_st 1 +.names _n1d _n1c +1 1 +0 0 +# m_st = 0 +.mv m_st$_n1c_n1f$true 4 R G U D +.names m_st$_n1c_n1f$true +R +# case (m_st ) +.mv m_st$_n1c$raw_n22 4 R G U D +.names m_st$_n1c_n1f$true m_st _n1c m_st$_n1c$raw_n22 +- - 0 =m_st +- - 1 =m_st$_n1c_n1f$true +.mv m_st$_n18$raw_n23 4 R G U D +.names m_st$_n18_n1b$true m_st$_n1c$raw_n22 _n18 m_st$_n18$raw_n23 +- - 0 =m_st$_n1c$raw_n22 +- - 1 =m_st$_n18_n1b$true +.mv m_st$_n14$raw_n27 4 R G U D +.names m_st$_n14_n17$true m_st$_n18$raw_n23 _n14 m_st$_n14$raw_n27 +- - 0 =m_st$_n18$raw_n23 +- - 1 =m_st$_n14_n17$true +.mv m_st$_nc$raw_n2b 4 R G U D +.names m_st$grant$raw_n13 m_st$_n14$raw_n27 _nc m_st$_nc$raw_n2b +- - 0 =m_st$_n14$raw_n27 +- - 1 =m_st$grant$raw_n13 +# r_st = 0 +.mv r_st$raw_n2f 2 I B +.names r_st$raw_n2f +I +# non-blocking assignments for initial +# assign grant = (r_st == B ) +.mv _n32 2 I B +.names _n32 +B +# r_st == 1 +.names r_st _n32 _n31 +.def 0 +- =r_st 1 +.names _n31 grant$raw_n30 +- =_n31 +# assign r_r_st = $NDset ( 1,0 ) +.names r_r_st +B +I +.mv _n37 2 I B +.names _n37 +I +.names r_st _n37 _n36 +.def 0 +- =r_st 1 +.names _n36 _n35 +1 1 +0 0 +.names req _n38 +- =req +# r_st = r_r_st +.mv r_st$req_n39$true 2 I B +.names r_r_st r_st$req_n39$true +- =r_r_st +# r_st = 0 +.mv r_st$req_n3a$false 2 I B +.names r_st$req_n3a$false +I +# if/else (req ) +.mv r_st$req$raw_n3c 2 I B +.names r_st$req_n39$true r_st$req_n3a$false req r_st$req$raw_n3c +- - 0 =r_st$req_n3a$false +- - 1 =r_st$req_n39$true +.mv _n41 2 I B +.names _n41 +B +.names r_st _n41 _n40 +.def 0 +- =r_st 1 +.names _n40 _n3f +1 1 +0 0 +.names release _n42 +- =release +# r_st = 0 +.mv r_st$release_n43$true 2 I B +.names r_st$release_n43$true +I +# if/else (release ) +.mv r_st$release$raw_n46 2 I B +.names r_st$release_n43$true r_st release r_st$release$raw_n46 +- - 0 =r_st +- - 1 =r_st$release_n43$true +# case (r_st ) +.mv r_st$_n3f$raw_n49 2 I B +.names r_st$release$raw_n46 r_st _n3f r_st$_n3f$raw_n49 +- - 0 =r_st +- - 1 =r_st$release$raw_n46 +.mv r_st$_n35$raw_n4a 2 I B +.names r_st$req$raw_n3c r_st$_n3f$raw_n49 _n35 r_st$_n35$raw_n4a +- - 0 =r_st$_n3f$raw_n49 +- - 1 =r_st$req$raw_n3c +# conflict arbitrators +.names _n35 _n38 _n3f _n42 _n4e +.def 0 + 1 1 - - 1 + 1 0 - - 1 + 0 - 1 1 1 +.mv _n4f 2 I B +.names _n4e r_st$_n35$raw_n4a r_st _n4f +1 - - =r_st$_n35$raw_n4a +0 - - =r_st +.names release$raw_n6 release +0 0 +1 1 +.names req$raw_n0 req +0 0 +1 1 +.names use$raw_n3 use +0 0 +1 1 +.names _nc _nf _n14 _n18 _n1c _n5a +.def 0 + 1 1 - - - 1 + 0 - 1 - - 1 + 0 - 0 1 - 1 + 0 - 0 0 1 1 +.mv _n5b 4 R G U D +.names _n5a m_st$_nc$raw_n2b m_st _n5b +1 - - =m_st$_nc$raw_n2b +0 - - =m_st +.names grant$raw_n30 grant +0 0 +1 1 +# non-blocking assignments +# latches +.r r_st$raw_n2f r_st +- =r_st$raw_n2f +.latch _n4f r_st +.r m_st$raw_n9 m_st +- =m_st$raw_n9 +.latch _n5b m_st +# quasi-continuous assignment +.end + + +.model a0 +# I/O ports +.inputs release +.inputs req +.inputs use +.inputs grant + +# assign e0 = 1 +.names e0$raw_n66 +1 +# assign r0 = s3 || f0 +# s3 || f0 +.names s3 f0 _n68 +.def 1 +0 0 0 +.names _n68 r0$raw_n67 +- =_n68 +# assign trigger = s0 +.names s0 trigger$raw_n69 +- =s0 +.subckt a0_seq0 a0_seq0 e=e0 r=r0 s=s0 f=f0 req=req +# assign e3 = trigger +.names trigger e3$raw_n6a +- =trigger +# assign r3 = 0 +.names r3$raw_n6b +0 +.subckt a0_seq3 a0_seq3 e=e3 r=r3 s=s3 f=f3 req=req grant=grant use=use release=release +# conflict arbitrators +.names r3$raw_n6b r3 +0 0 +1 1 +.names trigger$raw_n69 trigger +0 0 +1 1 +.names e0$raw_n66 e0 +0 0 +1 1 +.names e3$raw_n6a e3 +0 0 +1 1 +.names r0$raw_n67 r0 +0 0 +1 1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model a0_seq0 +# I/O ports +.inputs e +.outputs f +.inputs req +.inputs r +.outputs s + +.mv st 4 S D X T +# st = 0 +.mv st$raw_n6c 4 S D X T +.names st$raw_n6c +S +# non-blocking assignments for initial +# assign s = (((st == S ) && e && (req ))) +.mv _n6f 4 S D X T +.names _n6f +S +# st == 0 +.names st _n6f _n6e +.def 0 +- =st 1 +# (st == 0) && e +.names _n6e e _n70 +.def 0 +1 1 1 +# (st == 0) && e && (req ) +.names _n70 req _n71 +.def 0 +1 1 1 +.names _n71 s$raw_n6d +- =_n71 +# assign f = (((st == S ) && e && !(req )) || (st == T )) +.mv _n74 4 S D X T +.names _n74 +S +# st == 0 +.names st _n74 _n73 +.def 0 +- =st 1 +# (st == 0) && e +.names _n73 e _n75 +.def 0 +1 1 1 +.names req _n76 +0 1 +1 0 +# (st == 0) && e && !(req ) +.names _n75 _n76 _n77 +.def 0 +1 1 1 +.mv _n79 4 S D X T +.names _n79 +T +# st == 3 +.names st _n79 _n78 +.def 0 +- =st 1 +# ((st == 0) && e && !(req )) || (st == 3) +.names _n77 _n78 _n7a +.def 1 +0 0 0 +.names _n7a f$raw_n72 +- =_n7a +.mv _n7d 4 S D X T +.names _n7d +S +.names st _n7d _n7c +.def 0 +- =st 1 +.names _n7c _n7b +1 1 +0 0 +# e && (req ) +.names e req _n7e +.def 0 +1 1 1 +.names _n7e _n7f +- =_n7e +# st = 0 +.mv st$_n7e_n80$true 4 S D X T +.names st$_n7e_n80$true +S +.names req _n81 +0 1 +1 0 +# e && !(req ) +.names e _n81 _n82 +.def 0 +1 1 1 +.names _n82 _n83 +- =_n82 +# st = 3 +.mv st$_n82_n84$true 4 S D X T +.names st$_n82_n84$true +T +# if/else (e && !(req )) +.mv st$_n82$raw_n87 4 S D X T +.names st$_n82_n84$true st _n82 st$_n82$raw_n87 +- - 0 =st +- - 1 =st$_n82_n84$true +# if/else (e && (req )) +.mv st$_n7e$raw_n89 4 S D X T +.names st$_n7e_n80$true st$_n82$raw_n87 _n7e st$_n7e$raw_n89 +- - 0 =st$_n82$raw_n87 +- - 1 =st$_n7e_n80$true +.names r _n8c +- =r +# st = 0 +.mv st$r_n8d$true 4 S D X T +.names st$r_n8d$true +S +# if/else (r ) +.mv st$r$raw_n90 4 S D X T +.names st$r_n8d$true st r st$r$raw_n90 +- - 0 =st +- - 1 =st$r_n8d$true +# case (st ) +.mv st$_n7b$raw_n92 4 S D X T +.names st$_n7e$raw_n89 st$r$raw_n90 _n7b st$_n7b$raw_n92 +- - 0 =st$r$raw_n90 +- - 1 =st$_n7e$raw_n89 +# conflict arbitrators +.names f$raw_n72 f +0 0 +1 1 +.names s$raw_n6d s +0 0 +1 1 +.names _n7b _n7f _n83 _n8c _n95 +.def 0 + 1 1 - - 1 + 1 0 1 - 1 + 0 - - 1 1 +.mv _n96 4 S D X T +.names _n95 st$_n7b$raw_n92 st _n96 +1 - - =st$_n7b$raw_n92 +0 - - =st +# non-blocking assignments +# latches +.r st$raw_n6c st +- =st$raw_n6c +.latch _n96 st +# quasi-continuous assignment +.end + + +.model a0_seq3 +# I/O ports +.inputs release +.inputs e +.outputs f +.inputs req +.inputs r +.outputs s +.inputs use +.inputs grant + +.subckt a0_seq1 a0_seq1 e=e1 r=r1 s=s1 f=f1 req=req grant=grant +.subckt a0_seq2 a0_seq2 e=e2 r=r2 s=s2 f=f2 use=use release=release +# assign r1 = r +.names r r1$raw_n99 +- =r +# assign r2 = r +.names r r2$raw_n9a +- =r +.subckt then then e=s1 r=r s=e2 +# assign s = s2 +.names s2 s$raw_n9b +- =s2 +# assign f = f1 || f2 +# f1 || f2 +.names f1 f2 _n9d +.def 1 +0 0 0 +.names _n9d f$raw_n9c +- =_n9d +# assign e1 = e +.names e e1$raw_n9e +- =e +# conflict arbitrators +.names r1$raw_n99 r1 +0 0 +1 1 +.names r2$raw_n9a r2 +0 0 +1 1 +.names f$raw_n9c f +0 0 +1 1 +.names s$raw_n9b s +0 0 +1 1 +.names e1$raw_n9e e1 +0 0 +1 1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model a0_seq1 +# I/O ports +.inputs e +.outputs f +.inputs req +.inputs r +.outputs s +.inputs grant + +.mv st 4 S D X T +# st = 0 +.mv st$raw_n9f 4 S D X T +.names st$raw_n9f +S +# non-blocking assignments for initial +# assign s = (((st == S ) && e && (grant )) || ((st == X ) && (!r ) && (grant ))) +.mv _na2 4 S D X T +.names _na2 +S +# st == 0 +.names st _na2 _na1 +.def 0 +- =st 1 +# (st == 0) && e +.names _na1 e _na3 +.def 0 +1 1 1 +# (st == 0) && e && (grant ) +.names _na3 grant _na4 +.def 0 +1 1 1 +.mv _na6 4 S D X T +.names _na6 +X +# st == 2 +.names st _na6 _na5 +.def 0 +- =st 1 +.names r _na7 +0 1 +1 0 +# (st == 2) && (!r ) +.names _na5 _na7 _na8 +.def 0 +1 1 1 +# (st == 2) && (!r ) && (grant ) +.names _na8 grant _na9 +.def 0 +1 1 1 +# ((st == 0) && e && (grant )) || ((st == 2) && (!r ) && (grant )) +.names _na4 _na9 _naa +.def 1 +0 0 0 +.names _naa s$raw_na0 +- =_naa +# assign f = (((st == S ) && e && !(req ) && !(grant )) || ((st == X ) && !(req ) && !(grant )) || (st == T )) +.mv _nad 4 S D X T +.names _nad +S +# st == 0 +.names st _nad _nac +.def 0 +- =st 1 +# (st == 0) && e +.names _nac e _nae +.def 0 +1 1 1 +.names req _naf +0 1 +1 0 +# (st == 0) && e && !(req ) +.names _nae _naf _nb0 +.def 0 +1 1 1 +.names grant _nb1 +0 1 +1 0 +# (st == 0) && e && !(req ) && !(grant ) +.names _nb0 _nb1 _nb2 +.def 0 +1 1 1 +.mv _nb4 4 S D X T +.names _nb4 +X +# st == 2 +.names st _nb4 _nb3 +.def 0 +- =st 1 +.names req _nb5 +0 1 +1 0 +# (st == 2) && !(req ) +.names _nb3 _nb5 _nb6 +.def 0 +1 1 1 +.names grant _nb7 +0 1 +1 0 +# (st == 2) && !(req ) && !(grant ) +.names _nb6 _nb7 _nb8 +.def 0 +1 1 1 +# ((st == 0) && e && !(req ) && !(grant )) || ((st == 2) && !(req ) && !(grant )) +.names _nb2 _nb8 _nb9 +.def 1 +0 0 0 +.mv _nbb 4 S D X T +.names _nbb +T +# st == 3 +.names st _nbb _nba +.def 0 +- =st 1 +# ((st == 0) && e && !(req ) && !(grant )) || ((st == 2) && !(req ) && !(grant )) || (st == 3) +.names _nb9 _nba _nbc +.def 1 +0 0 0 +.names _nbc f$raw_nab +- =_nbc +.mv _nbf 4 S D X T +.names _nbf +S +.names st _nbf _nbe +.def 0 +- =st 1 +.names _nbe _nbd +1 1 +0 0 +# e && (grant ) +.names e grant _nc0 +.def 0 +1 1 1 +.names _nc0 _nc1 +- =_nc0 +# st = 0 +.mv st$_nc0_nc2$true 4 S D X T +.names st$_nc0_nc2$true +S +# e && (req ) +.names e req _nc3 +.def 0 +1 1 1 +.names _nc3 _nc4 +- =_nc3 +# st = 2 +.mv st$_nc3_nc5$true 4 S D X T +.names st$_nc3_nc5$true +X +.names req _nc6 +0 1 +1 0 +# e && !(req ) +.names e _nc6 _nc7 +.def 0 +1 1 1 +.names grant _nc8 +0 1 +1 0 +# e && !(req ) && !(grant ) +.names _nc7 _nc8 _nc9 +.def 0 +1 1 1 +.names _nc9 _nca +- =_nc9 +# st = 3 +.mv st$_nc9_ncb$true 4 S D X T +.names st$_nc9_ncb$true +T +# if/else (e && !(req ) && !(grant )) +.mv st$_nc9$raw_nce 4 S D X T +.names st$_nc9_ncb$true st _nc9 st$_nc9$raw_nce +- - 0 =st +- - 1 =st$_nc9_ncb$true +# if/else (e && (req )) +.mv st$_nc3$raw_nd0 4 S D X T +.names st$_nc3_nc5$true st$_nc9$raw_nce _nc3 st$_nc3$raw_nd0 +- - 0 =st$_nc9$raw_nce +- - 1 =st$_nc3_nc5$true +# if/else (e && (grant )) +.mv st$_nc0$raw_nd4 4 S D X T +.names st$_nc0_nc2$true st$_nc3$raw_nd0 _nc0 st$_nc0$raw_nd4 +- - 0 =st$_nc3$raw_nd0 +- - 1 =st$_nc0_nc2$true +.mv _nd9 4 S D X T +.names _nd9 +X +.names st _nd9 _nd8 +.def 0 +- =st 1 +.names _nd8 _nd7 +1 1 +0 0 +# r || (grant ) +.names r grant _nda +.def 1 +0 0 0 +.names _nda _ndb +- =_nda +# st = 0 +.mv st$_nda_ndc$true 4 S D X T +.names st$_nda_ndc$true +S +.names req _ndd +0 1 +1 0 +.names grant _nde +0 1 +1 0 +# !(req ) && !(grant ) +.names _ndd _nde _ndf +.def 0 +1 1 1 +.names _ndf _ne0 +- =_ndf +# st = 3 +.mv st$_ndf_ne1$true 4 S D X T +.names st$_ndf_ne1$true +T +# if/else (!(req ) && !(grant )) +.mv st$_ndf$raw_ne4 4 S D X T +.names st$_ndf_ne1$true st _ndf st$_ndf$raw_ne4 +- - 0 =st +- - 1 =st$_ndf_ne1$true +# if/else (r || (grant )) +.mv st$_nda$raw_ne6 4 S D X T +.names st$_nda_ndc$true st$_ndf$raw_ne4 _nda st$_nda$raw_ne6 +- - 0 =st$_ndf$raw_ne4 +- - 1 =st$_nda_ndc$true +.names r _ne9 +- =r +# st = 0 +.mv st$r_nea$true 4 S D X T +.names st$r_nea$true +S +# if/else (r ) +.mv st$r$raw_ned 4 S D X T +.names st$r_nea$true st r st$r$raw_ned +- - 0 =st +- - 1 =st$r_nea$true +# case (st ) +.mv st$_nd7$raw_nef 4 S D X T +.names st$_nda$raw_ne6 st$r$raw_ned _nd7 st$_nd7$raw_nef +- - 0 =st$r$raw_ned +- - 1 =st$_nda$raw_ne6 +.mv st$_nbd$raw_nf3 4 S D X T +.names st$_nc0$raw_nd4 st$_nd7$raw_nef _nbd st$_nbd$raw_nf3 +- - 0 =st$_nd7$raw_nef +- - 1 =st$_nc0$raw_nd4 +# conflict arbitrators +.names f$raw_nab f +0 0 +1 1 +.names s$raw_na0 s +0 0 +1 1 +.names _nbd _nc1 _nc4 _nca _nd7 _ndb _ne0 _ne9 _nf6 +.def 0 + 1 1 - - - - - - 1 + 1 0 1 - - - - - 1 + 1 0 0 1 - - - - 1 + 0 - - - 1 1 - - 1 + 0 - - - 1 0 1 - 1 + 0 - - - 0 - - 1 1 +.mv _nf7 4 S D X T +.names _nf6 st$_nbd$raw_nf3 st _nf7 +1 - - =st$_nbd$raw_nf3 +0 - - =st +# non-blocking assignments +# latches +.r st$raw_n9f st +- =st$raw_n9f +.latch _nf7 st +# quasi-continuous assignment +.end + + +.model a0_seq2 +# I/O ports +.inputs release +.inputs e +.outputs f +.inputs r +.outputs s +.inputs use + +.mv st 4 S D X T +# st = 0 +.mv st$raw_nfa 4 S D X T +.names st$raw_nfa +S +# non-blocking assignments for initial +# assign s = (((st == S ) && e && (release )) || ((st == X ) && (!r ) && (release ))) +.mv _nfd 4 S D X T +.names _nfd +S +# st == 0 +.names st _nfd _nfc +.def 0 +- =st 1 +# (st == 0) && e +.names _nfc e _nfe +.def 0 +1 1 1 +# (st == 0) && e && (release ) +.names _nfe release _nff +.def 0 +1 1 1 +.mv _n101 4 S D X T +.names _n101 +X +# st == 2 +.names st _n101 _n100 +.def 0 +- =st 1 +.names r _n102 +0 1 +1 0 +# (st == 2) && (!r ) +.names _n100 _n102 _n103 +.def 0 +1 1 1 +# (st == 2) && (!r ) && (release ) +.names _n103 release _n104 +.def 0 +1 1 1 +# ((st == 0) && e && (release )) || ((st == 2) && (!r ) && (release )) +.names _nff _n104 _n105 +.def 1 +0 0 0 +.names _n105 s$raw_nfb +- =_n105 +# assign f = (((st == S ) && e && !(use ) && !(release )) || ((st == X ) && !(use ) && !(release )) || (st == T )) +.mv _n108 4 S D X T +.names _n108 +S +# st == 0 +.names st _n108 _n107 +.def 0 +- =st 1 +# (st == 0) && e +.names _n107 e _n109 +.def 0 +1 1 1 +.names use _n10a +0 1 +1 0 +# (st == 0) && e && !(use ) +.names _n109 _n10a _n10b +.def 0 +1 1 1 +.names release _n10c +0 1 +1 0 +# (st == 0) && e && !(use ) && !(release ) +.names _n10b _n10c _n10d +.def 0 +1 1 1 +.mv _n10f 4 S D X T +.names _n10f +X +# st == 2 +.names st _n10f _n10e +.def 0 +- =st 1 +.names use _n110 +0 1 +1 0 +# (st == 2) && !(use ) +.names _n10e _n110 _n111 +.def 0 +1 1 1 +.names release _n112 +0 1 +1 0 +# (st == 2) && !(use ) && !(release ) +.names _n111 _n112 _n113 +.def 0 +1 1 1 +# ((st == 0) && e && !(use ) && !(release )) || ((st == 2) && !(use ) && !(release )) +.names _n10d _n113 _n114 +.def 1 +0 0 0 +.mv _n116 4 S D X T +.names _n116 +T +# st == 3 +.names st _n116 _n115 +.def 0 +- =st 1 +# ((st == 0) && e && !(use ) && !(release )) || ((st == 2) && !(use ) && !(release )) || (st == 3) +.names _n114 _n115 _n117 +.def 1 +0 0 0 +.names _n117 f$raw_n106 +- =_n117 +.mv _n11a 4 S D X T +.names _n11a +S +.names st _n11a _n119 +.def 0 +- =st 1 +.names _n119 _n118 +1 1 +0 0 +# e && (release ) +.names e release _n11b +.def 0 +1 1 1 +.names _n11b _n11c +- =_n11b +# st = 0 +.mv st$_n11b_n11d$true 4 S D X T +.names st$_n11b_n11d$true +S +# e && (use ) +.names e use _n11e +.def 0 +1 1 1 +.names _n11e _n11f +- =_n11e +# st = 2 +.mv st$_n11e_n120$true 4 S D X T +.names st$_n11e_n120$true +X +.names use _n121 +0 1 +1 0 +# e && !(use ) +.names e _n121 _n122 +.def 0 +1 1 1 +.names release _n123 +0 1 +1 0 +# e && !(use ) && !(release ) +.names _n122 _n123 _n124 +.def 0 +1 1 1 +.names _n124 _n125 +- =_n124 +# st = 3 +.mv st$_n124_n126$true 4 S D X T +.names st$_n124_n126$true +T +# if/else (e && !(use ) && !(release )) +.mv st$_n124$raw_n129 4 S D X T +.names st$_n124_n126$true st _n124 st$_n124$raw_n129 +- - 0 =st +- - 1 =st$_n124_n126$true +# if/else (e && (use )) +.mv st$_n11e$raw_n12b 4 S D X T +.names st$_n11e_n120$true st$_n124$raw_n129 _n11e st$_n11e$raw_n12b +- - 0 =st$_n124$raw_n129 +- - 1 =st$_n11e_n120$true +# if/else (e && (release )) +.mv st$_n11b$raw_n12f 4 S D X T +.names st$_n11b_n11d$true st$_n11e$raw_n12b _n11b st$_n11b$raw_n12f +- - 0 =st$_n11e$raw_n12b +- - 1 =st$_n11b_n11d$true +.mv _n134 4 S D X T +.names _n134 +X +.names st _n134 _n133 +.def 0 +- =st 1 +.names _n133 _n132 +1 1 +0 0 +# r || (release ) +.names r release _n135 +.def 1 +0 0 0 +.names _n135 _n136 +- =_n135 +# st = 0 +.mv st$_n135_n137$true 4 S D X T +.names st$_n135_n137$true +S +.names use _n138 +0 1 +1 0 +.names release _n139 +0 1 +1 0 +# !(use ) && !(release ) +.names _n138 _n139 _n13a +.def 0 +1 1 1 +.names _n13a _n13b +- =_n13a +# st = 3 +.mv st$_n13a_n13c$true 4 S D X T +.names st$_n13a_n13c$true +T +# if/else (!(use ) && !(release )) +.mv st$_n13a$raw_n13f 4 S D X T +.names st$_n13a_n13c$true st _n13a st$_n13a$raw_n13f +- - 0 =st +- - 1 =st$_n13a_n13c$true +# if/else (r || (release )) +.mv st$_n135$raw_n141 4 S D X T +.names st$_n135_n137$true st$_n13a$raw_n13f _n135 st$_n135$raw_n141 +- - 0 =st$_n13a$raw_n13f +- - 1 =st$_n135_n137$true +.names r _n144 +- =r +# st = 0 +.mv st$r_n145$true 4 S D X T +.names st$r_n145$true +S +# if/else (r ) +.mv st$r$raw_n148 4 S D X T +.names st$r_n145$true st r st$r$raw_n148 +- - 0 =st +- - 1 =st$r_n145$true +# case (st ) +.mv st$_n132$raw_n14a 4 S D X T +.names st$_n135$raw_n141 st$r$raw_n148 _n132 st$_n132$raw_n14a +- - 0 =st$r$raw_n148 +- - 1 =st$_n135$raw_n141 +.mv st$_n118$raw_n14e 4 S D X T +.names st$_n11b$raw_n12f st$_n132$raw_n14a _n118 st$_n118$raw_n14e +- - 0 =st$_n132$raw_n14a +- - 1 =st$_n11b$raw_n12f +# conflict arbitrators +.names f$raw_n106 f +0 0 +1 1 +.names s$raw_nfb s +0 0 +1 1 +.names _n118 _n11c _n11f _n125 _n132 _n136 _n13b _n144 _n151 +.def 0 + 1 1 - - - - - - 1 + 1 0 1 - - - - - 1 + 1 0 0 1 - - - - 1 + 0 - - - 1 1 - - 1 + 0 - - - 1 0 1 - 1 + 0 - - - 0 - - 1 1 +.mv _n152 4 S D X T +.names _n151 st$_n118$raw_n14e st _n152 +1 - - =st$_n118$raw_n14e +0 - - =st +# non-blocking assignments +# latches +.r st$raw_nfa st +- =st$raw_nfa +.latch _n152 st +# quasi-continuous assignment +.end + + +.model then +# I/O ports +.inputs e +.inputs r +.outputs s + +.mv st 4 S D X T +# st = 0 +.mv st$raw_n155 4 S D X T +.names st$raw_n155 +S +# non-blocking assignments for initial +# assign s = (st == D ) +.mv _n158 4 S D X T +.names _n158 +D +# st == 1 +.names st _n158 _n157 +.def 0 +- =st 1 +.names _n157 s$raw_n156 +- =_n157 +.mv _n15b 4 S D X T +.names _n15b +S +.names st _n15b _n15a +.def 0 +- =st 1 +.names _n15a _n159 +1 1 +0 0 +.names e _n15c +- =e +# st = 2 +.mv st$e_n15d$true 4 S D X T +.names st$e_n15d$true +X +# if/else (e ) +.mv st$e$raw_n160 4 S D X T +.names st$e_n15d$true st e st$e$raw_n160 +- - 0 =st +- - 1 =st$e_n15d$true +.mv _n163 4 S D X T +.names _n163 +X +.names st _n163 _n162 +.def 0 +- =st 1 +.names _n162 _n161 +1 1 +0 0 +# st = 1 +.mv st$_n161_n164$true 4 S D X T +.names st$_n161_n164$true +D +.names r _n165 +- =r +# st = 0 +.mv st$r_n166$true 4 S D X T +.names st$r_n166$true +S +# if/else (r ) +.mv st$r$raw_n169 4 S D X T +.names st$r_n166$true st r st$r$raw_n169 +- - 0 =st +- - 1 =st$r_n166$true +# case (st ) +.mv st$_n161$raw_n16b 4 S D X T +.names st$_n161_n164$true st$r$raw_n169 _n161 st$_n161$raw_n16b +- - 0 =st$r$raw_n169 +- - 1 =st$_n161_n164$true +.mv st$_n159$raw_n16f 4 S D X T +.names st$e$raw_n160 st$_n161$raw_n16b _n159 st$_n159$raw_n16f +- - 0 =st$_n161$raw_n16b +- - 1 =st$e$raw_n160 +# conflict arbitrators +.names s$raw_n156 s +0 0 +1 1 +.names _n159 _n15c _n161 _n165 _n172 +.def 0 + 1 1 - - 1 + 0 - 1 - 1 + 0 - 0 1 1 +.mv _n173 4 S D X T +.names _n172 st$_n159$raw_n16f st _n173 +1 - - =st$_n159$raw_n16f +0 - - =st +# non-blocking assignments +# latches +.r st$raw_n155 st +- =st$raw_n155 +.latch _n173 st +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/exampleS/exampleS.v =================================================================== --- vis_dev/vis-2.1/examples/exampleS/exampleS.v (revision 11) +++ vis_dev/vis-2.1/examples/exampleS/exampleS.v (revision 11) @@ -0,0 +1,171 @@ +typedef enum { R, G, U, D } m_state; +typedef enum { I, B } r_state; + +module resource(clk); +input clk; +wire req, grant, use, release; + +/* INSTANTIATION 0: assert req implies (req until grant) then (use until release) +*/ + a0 a0(clk, req, grant, use, release); + + +// RESOURCE REQUESTOR + +assign req = (m_st == R); +assign use = (m_st == U); +assign release = (m_st == D); +m_state reg m_st; +m_state wire r_m_st; +initial m_st = R; + +assign r_m_st = $ND(U,D); + +always @(posedge clk) begin + case (m_st) + R: if (grant) m_st = G; + G: m_st = U; + U: begin + m_st = r_m_st; + end + D: m_st = R; + endcase; +end + +// RESOURCE GRANTER + +r_state reg r_st; +r_state wire r_r_st; +initial r_st = I; + +assign grant = (r_st == B); +assign r_r_st = $ND(B,I); + +always @(posedge clk) begin + case (r_st) + I: begin + if (req) r_st = r_r_st; + else r_st = I; + end + B: if (release) r_st = I; + endcase; +end +endmodule + + +/* TESLA ver 0.2: Sequence Detection FSMS: */ + +typedef enum { S, D, X, T } state; + +/* DEFINITION 0: assert req implies (req until grant) then (use until release) +*/ +module a0(clk, req, grant, use, release); +input clk, req, grant, use, release; +wire clk, trigger, failure, e0, r0, s0, f0, e3, r3, s3, f3, req, grant, use, release; + assign e0 = 1; + assign r0 = s3 || f0; + assign trigger = s0; + a0_seq0 a0_seq0(clk, e0, r0, s0, f0, req); + assign e3 = trigger; + assign r3 = 0; + a0_seq3 a0_seq3(clk, e3, r3, s3, f3, req, grant, use, release); +endmodule + +module a0_seq0(clk, e, r, s, f, req); +input clk, e, r, req; +output s, f; +//AP + state reg st; + initial st = S; + assign s = (((st == S) && e && (req))); + assign f = (((st == S) && e && ! (req)) || (st == T)); + always @(posedge clk) begin + case (st) + S: begin + if (e && (req)) st = S; + else if (e && !(req)) st = T; + end + default: if (r) st = S; + endcase; + end +endmodule + +module a0_seq3(clk, e, r, s, f, req, grant, use, release); +input clk, e, r, req, grant, use, release; +output s, f; +// THEN +wire e1, r1, s1, f1, e2, r2, s2, f2, req, grant, use, release; + a0_seq1 a0_seq1(clk, e1, r1, s1, f1, req, grant); + a0_seq2 a0_seq2(clk, e2, r2, s2, f2, use, release); + assign r1 = r; + assign r2 = r; + then then(clk, s1, r, e2); + assign s = s2; + assign f = f1 || f2; + assign e1 = e; +endmodule + +module then(clk, e, r, s); +input clk, e, r; +output s; +//THEN_DEF + state reg st; + initial st = S; + assign s = (st == D); + always @(posedge clk) begin + case (st) + S: if (e) st = X; + X: st = D; + default: if (r) st = S; + endcase; + end +endmodule + +module a0_seq1(clk, e, r, s, f, req, grant); +input clk, e, r, req, grant; +output s, f; +//UNTIL + state reg st; + initial st = S; + assign s = (((st == S) && e && (grant)) || ((st == X) && (! r) && (grant))); + assign f = (((st == S) && e && ! (req) && !(grant)) || ((st == X) && !(req) && !(grant)) || (st == T)); + always @(posedge clk) begin + case (st) + S: begin + if (e && (grant)) st = S; + else if (e && (req)) st = X; + else if(e && !(req) && !(grant)) st = T; + end + X: begin + if (r || (grant)) st = S; + else if (!(req) && !(grant)) st = T; + end + default: if (r) st = S; + endcase; + end +endmodule + +module a0_seq2(clk, e, r, s, f, use, release); +input clk, e, r, use, release; +output s, f; +//UNTIL + state reg st; + initial st = S; + assign s = (((st == S) && e && (release)) || ((st == X) && (! r) && (release))); + assign f = (((st == S) && e && ! (use) && !(release)) || ((st == X) && !(use) && !(release)) || (st == T)); + always @(posedge clk) begin + case (st) + S: begin + if (e && (release)) st = S; + else if (e && (use)) st = X; + else if(e && !(use) && !(release)) st = T; + end + X: begin + if (r || (release)) st = S; + else if (!(use) && !(release)) st = T; + end + default: if (r) st = S; + endcase; + end +endmodule + Index: vis_dev/vis-2.1/examples/fpmpy/README =================================================================== --- vis_dev/vis-2.1/examples/fpmpy/README (revision 11) +++ vis_dev/vis-2.1/examples/fpmpy/README (revision 11) @@ -0,0 +1,21 @@ +$Id: README,v 1.1 1997/03/01 18:54:43 fabio Exp $ + +This directory contains a simple floating point multiplier, +not exactly IEEE 754-compliant, but largely inspired to the standard. + +The significand uses the hidden bit and is between 1 (included) and 2 +(excluded). +The exponent uses the excess (2**(n-1) - 1) representation. For single +precision, this is excess 127. +The smallest exponent (0) is used for the represenation of 0. Denormals +are not supported. +The largest exponent is used for infinities and NaNs. Infinities use +the smallest possible significand (all zeroes). Everything else is deemed +a NaN. No distinction is made between signalling and non-signalling NaNs. +When the multiplier generates a NaN, it uses the all-one significand. +One multiplication takes three clock cycles and it is not pipelined. + +The CTL formulae check for several properties of the result and +demonstrate the use of vector variables and macros. + +Author: Fabio Somenzi Index: vis_dev/vis-2.1/examples/fpmpy/check_result =================================================================== --- vis_dev/vis-2.1/examples/fpmpy/check_result (revision 11) +++ vis_dev/vis-2.1/examples/fpmpy/check_result (revision 11) @@ -0,0 +1,10 @@ +# INV: formula passed --- (((!((FPM.state<1>=0 * FPM.state<0>=0)) * ((((x<6>=0 * x<5>=0) * x<4>=0) * x<3>=0) -> ((x<2>=0 * x<1>=0) * x<0>=0))) * ((((y<6>=0 * y<5>=0) * y<4>=0) * y<3>=0) -> ((y<2>=0 * y<1>=0) * y<0>=0))) -> ((((z<6>=0 * z<5>=0) * z<4>=0) * z<3>=0) -> ((z<2>=0 * z<1>=0) * z<0>=0))) +# INV: formula failed --- ((!((FPM.state<1>=0 * FPM.state<0>=0)) * !((y<7>=1 ^ x<7>=0))) -> z<7>=1) +# MC: formula passed --- AG(((((start=1 * (FPM.state<1>=0 * FPM.state<0>=0)) * ((((y<6>=0 * y<5>=0) * y<4>=0) * y<3>=0) -> ((y<2>=0 * y<1>=0) * y<0>=0))) * ((((x<6>=0 * x<5>=0) * x<4>=0) * x<3>=0) -> ((x<2>=0 * x<1>=0) * x<0>=0))) -> AX(AX(AX(((((z<6>=0 * z<5>=0) * z<4>=0) * z<3>=0) -> ((z<2>=0 * z<1>=0) * z<0>=0))))))) +# MC: formula failed --- AG((((start=1 * (FPM.state<1>=0 * FPM.state<0>=0)) * !((y<7>=1 ^ x<7>=0))) -> AX(AX(AX(z<7>=1))))) +# MC: formula passed --- AG((((start=1 * (FPM.state<1>=0 * FPM.state<0>=0)) * (y<7>=1 ^ x<7>=0)) -> AX(AX(AX(z<7>=0))))) +# MC: formula passed --- AG((((start=1 * (FPM.state<1>=0 * FPM.state<0>=0)) * (((((y<6>=1 * y<5>=1) * y<4>=1) * y<3>=1) * !(((y<2>=0 * y<1>=0) * y<0>=0))) + ((((x<6>=1 * x<5>=1) * x<4>=1) * x<3>=1) * !(((x<2>=0 * x<1>=0) * x<0>=0))))) -> AX(AX(AX(((((z<6>=1 * z<5>=1) * z<4>=1) * z<3>=1) * !(((z<2>=0 * z<1>=0) * z<0>=0)))))))) +# MC: formula failed --- AG(((((start=1 * (FPM.state<1>=0 * FPM.state<0>=0)) * ((((((y<6>=0 * y<5>=0) * y<4>=0) * y<3>=0) * y<2>=0) * y<1>=0) * y<0>=0)) * !(((((x<6>=1 * x<5>=1) * x<4>=1) * x<3>=1) * !(((x<2>=0 * x<1>=0) * x<0>=0))))) -> AX(AX(AX(((((((z<6>=0 * z<5>=0) * z<4>=0) * z<3>=0) * z<2>=0) * z<1>=0) * z<0>=0)))))) +# MC: formula failed --- AG(((((start=1 * (FPM.state<1>=0 * FPM.state<0>=0)) * ((((((x<6>=0 * x<5>=0) * x<4>=0) * x<3>=0) * x<2>=0) * x<1>=0) * x<0>=0)) * !(((((y<6>=1 * y<5>=1) * y<4>=1) * y<3>=1) * !(((y<2>=0 * y<1>=0) * y<0>=0))))) -> AX(AX(AX(((((((z<6>=0 * z<5>=0) * z<4>=0) * z<3>=0) * z<2>=0) * z<1>=0) * z<0>=0)))))) +# MC: formula passed --- AG((((((start=1 * (FPM.state<1>=0 * FPM.state<0>=0)) * ((((((y<6>=1 * y<5>=1) * y<4>=1) * y<3>=1) * y<2>=0) * y<1>=0) * y<0>=0)) * !(((((x<6>=1 * x<5>=1) * x<4>=1) * x<3>=1) * !(((x<2>=0 * x<1>=0) * x<0>=0))))) * !((((x<6>=0 * x<5>=0) * x<4>=0) * x<3>=0))) -> AX(AX(AX(((((((z<6>=1 * z<5>=1) * z<4>=1) * z<3>=1) * z<2>=0) * z<1>=0) * z<0>=0)))))) +# MC: formula passed --- AG((((((start=1 * (FPM.state<1>=0 * FPM.state<0>=0)) * ((((((x<6>=1 * x<5>=1) * x<4>=1) * x<3>=1) * x<2>=0) * x<1>=0) * x<0>=0)) * !(((((y<6>=1 * y<5>=1) * y<4>=1) * y<3>=1) * !(((y<2>=0 * y<1>=0) * y<0>=0))))) * !((((y<6>=0 * y<5>=0) * y<4>=0) * y<3>=0))) -> AX(AX(AX(((((((z<6>=1 * z<5>=1) * z<4>=1) * z<3>=1) * z<2>=0) * z<1>=0) * z<0>=0)))))) Index: vis_dev/vis-2.1/examples/fpmpy/check_script =================================================================== --- vis_dev/vis-2.1/examples/fpmpy/check_script (revision 11) +++ vis_dev/vis-2.1/examples/fpmpy/check_script (revision 11) @@ -0,0 +1,8 @@ +read_blif_mv fpmpy.mv +flatten_hierarchy +static_order +dynamic_var_ordering -e sift +build_partition_mdds +check_invariant -A 1 fpmpy.inv +model_check fpmpy.ctl +quit -s Index: vis_dev/vis-2.1/examples/fpmpy/fpmpy.ctl =================================================================== --- vis_dev/vis-2.1/examples/fpmpy/fpmpy.ctl (revision 11) +++ vis_dev/vis-2.1/examples/fpmpy/fpmpy.ctl (revision 11) @@ -0,0 +1,42 @@ +# Define common subformulae. +\define START (start=1 * FPM.state[1:0]=0) +\define Validx (x[6:3]=0 -> x[2:0]=0) +\define Validy (y[6:3]=0 -> y[2:0]=0) +\define Validz (z[6:3]=0 -> z[2:0]=0) +\define NaNx (x[6:3]=b1111 * !(x[2:0]=0)) +\define NaNy (y[6:3]=b1111 * !(y[2:0]=0)) +\define NaNz (z[6:3]=b1111 * !(z[2:0]=0)) +\define Infx x[6:0]=b1111000 +\define Infy y[6:0]=b1111000 +\define Infz z[6:0]=b1111000 + +#PASS: Legal operands cannot produce illegal results. The only illegal +# operands in our case are the denormals. + +AG((\START * \Validy * \Validx) -> AX:3(\Validz)); + +#FAIL: If the sign bits are different the result is negative. +# This formula fails because one operand may be NaN. + +AG((\START * !(y[7]==x[7])) -> AX:3(z[7]=1)); + +#PASS: If the sign bits are the same the result is positive. + +AG((\START * y[7]==x[7]) -> AX:3(z[7]=0)); + +#PASS: If one of the operands is NaN the result is NaN. + +AG((\START * (\NaNy + \NaNx)) -> AX:3(\NaNz)); + +#FAIL: If one of the operands is zero and the other operand is +# not NaN the result is zero. +# These properties should fail, because infinity * zero = NaN. + +AG((\START * y[6:0]=0 * !\NaNx) -> AX:3(z[6:0]=0)); +AG((\START * x[6:0]=0 * !\NaNy) -> AX:3(z[6:0]=0)); + +#PASS: If one of the operands is infinite and the other operand is +# neither NaN nor zero the result is infinite. + +AG((\START * \Infy * !\NaNx * !(x[6:3]=0)) -> AX:3(\Infz)); +AG((\START * \Infx * !\NaNy * !(y[6:3]=0)) -> AX:3(\Infz)); Index: vis_dev/vis-2.1/examples/fpmpy/fpmpy.inv =================================================================== --- vis_dev/vis-2.1/examples/fpmpy/fpmpy.inv (revision 11) +++ vis_dev/vis-2.1/examples/fpmpy/fpmpy.inv (revision 11) @@ -0,0 +1,22 @@ +# Define common subformulae. +\define START (start=1 * FPM.state[1:0]=0) +\define BUSY !(FPM.state[1:0]=0) +\define Validx (x[6:3]=0 -> x[2:0]=0) +\define Validy (y[6:3]=0 -> y[2:0]=0) +\define Validz (z[6:3]=0 -> z[2:0]=0) +\define NaNx (x[6:3]=b1111 * !(x[2:0]=0)) +\define NaNy (y[6:3]=b1111 * !(y[2:0]=0)) +\define NaNz (z[6:3]=b1111 * !(z[2:0]=0)) +\define Infx x[6:0]=b1111000 +\define Infy y[6:0]=b1111000 +\define Infz z[6:0]=b1111000 + +#PASS: Legal operands cannot produce illegal results. The only illegal +# operands in our case are the denormals. + +(\BUSY * \Validx * \Validy) -> \Validz; + +#FAIL: If the sign bits are different the result is negative. +# This formula fails because one operand may be NaN. + +(\BUSY * !(y[7]==x[7])) -> z[7]=1; Index: vis_dev/vis-2.1/examples/fpmpy/fpmpy.mv =================================================================== --- vis_dev/vis-2.1/examples/fpmpy/fpmpy.mv (revision 11) +++ vis_dev/vis-2.1/examples/fpmpy/fpmpy.mv (revision 11) @@ -0,0 +1,3393 @@ +# /sda4/tools/Vis1.2/vl2mv/i686/bin/vl2mv fpmpy.v +# version: 0.2 +# date: 20:12:08 02/25/97 (MST) +.model fvFPMult +# I/O ports +.inputs i<0> i<1> i<2> i<3> i<4> i<5> i<6> i<7> +.inputs j<0> j<1> j<2> j<3> j<4> j<5> j<6> j<7> +.subckt IEEEfpMult FPM start=start x<0>=x<0> x<1>=x<1> x<2>=x<2> x<3>=x<3> x<4>=x<4> x<5>=x<5> x<6>=x<6> x<7>=x<7> y<0>=y<0> y<1>=y<1> y<2>=y<2> y<3>=y<3> y<4>=y<4> y<5>=y<5> y<6>=y<6> y<7>=y<7> z<0>=z<0> z<1>=z<1> z<2>=z<2> z<3>=z<3> z<4>=z<4> z<5>=z<5> z<6>=z<6> z<7>=z<7> +# x = i +.names i<0> x$raw_n0<0> +- =i<0> +.names i<1> x$raw_n0<1> +- =i<1> +.names i<2> x$raw_n0<2> +- =i<2> +.names i<3> x$raw_n0<3> +- =i<3> +.names i<4> x$raw_n0<4> +- =i<4> +.names i<5> x$raw_n0<5> +- =i<5> +.names i<6> x$raw_n0<6> +- =i<6> +.names i<7> x$raw_n0<7> +- =i<7> +# y = j +.names j<0> y$raw_n1<0> +- =j<0> +.names j<1> y$raw_n1<1> +- =j<1> +.names j<2> y$raw_n1<2> +- =j<2> +.names j<3> y$raw_n1<3> +- =j<3> +.names j<4> y$raw_n1<4> +- =j<4> +.names j<5> y$raw_n1<5> +- =j<5> +.names j<6> y$raw_n1<6> +- =j<6> +.names j<7> y$raw_n1<7> +- =j<7> +# conflict arbitrators +.names _n2 +.def 0 + 1 +.names _n2 y$raw_n1<0> y$raw_n1<1> y$raw_n1<2> y$raw_n1<3> y$raw_n1<4> y$raw_n1<5> y$raw_n1<6> y$raw_n1<7> -> _n3<0> _n3<1> _n3<2> _n3<3> _n3<4> _n3<5> _n3<6> _n3<7> +.def 0 0 0 0 0 0 0 0 +1 - - - - - - - - =y$raw_n1<0> =y$raw_n1<1> =y$raw_n1<2> =y$raw_n1<3> =y$raw_n1<4> =y$raw_n1<5> =y$raw_n1<6> =y$raw_n1<7> +.names start _n4 +0 0 +1 1 +.names _n5 +.def 0 + 1 +.names _n5 x$raw_n0<0> x$raw_n0<1> x$raw_n0<2> x$raw_n0<3> x$raw_n0<4> x$raw_n0<5> x$raw_n0<6> x$raw_n0<7> -> _n6<0> _n6<1> _n6<2> _n6<3> _n6<4> _n6<5> _n6<6> _n6<7> +.def 0 0 0 0 0 0 0 0 +1 - - - - - - - - =x$raw_n0<0> =x$raw_n0<1> =x$raw_n0<2> =x$raw_n0<3> =x$raw_n0<4> =x$raw_n0<5> =x$raw_n0<6> =x$raw_n0<7> +# non-blocking assignments +# latches +.r y<0> +- +.r y<1> +- +.r y<2> +- +.r y<3> +- +.r y<4> +- +.r y<5> +- +.r y<6> +- +.r y<7> +- +.latch _n3<0> y<0> +.latch _n3<1> y<1> +.latch _n3<2> y<2> +.latch _n3<3> y<3> +.latch _n3<4> y<4> +.latch _n3<5> y<5> +.latch _n3<6> y<6> +.latch _n3<7> y<7> +.r start +0 +1 +.latch _n4 start +.r x<0> +- +.r x<1> +- +.r x<2> +- +.r x<3> +- +.r x<4> +- +.r x<5> +- +.r x<6> +- +.r x<7> +- +.latch _n6<0> x<0> +.latch _n6<1> x<1> +.latch _n6<2> x<2> +.latch _n6<3> x<3> +.latch _n6<4> x<4> +.latch _n6<5> x<5> +.latch _n6<6> x<6> +.latch _n6<7> x<7> +# quasi-continuous assignment +.end + + +.model IEEEfpMult +# I/O ports +.inputs y<0> y<1> y<2> y<3> y<4> y<5> y<6> y<7> +.outputs z<0> z<1> z<2> z<3> z<4> z<5> z<6> z<7> +.inputs start +.inputs x<0> x<1> x<2> x<3> x<4> x<5> x<6> x<7> +.subckt intMult im x<0>=xMant<0> x<1>=xMant<1> x<2>=xMant<2> x<3>=xMant<3> y<0>=yMant<0> y<1>=yMant<1> y<2>=yMant<2> y<3>=yMant<3> z<0>=combZ<0> z<1>=combZ<1> z<2>=combZ<2> z<3>=combZ<3> z<4>=combZ<4> z<5>=combZ<5> z<6>=combZ<6> z<7>=combZ<7> +# xSign = 0 +.names xSign$raw_n7 +0 +# xExp = 0 +.names xExp$raw_n8<0> +0 +.names xExp$raw_n8<1> +0 +.names xExp$raw_n8<2> +0 +.names xExp$raw_n8<3> +0 +# xMant = 0 +.names xMant$raw_n9<0> +0 +.names xMant$raw_n9<1> +0 +.names xMant$raw_n9<2> +0 +.names xMant$raw_n9<3> +0 +# ySign = 0 +.names ySign$raw_na +0 +# yExp = 0 +.names yExp$raw_nb<0> +0 +.names yExp$raw_nb<1> +0 +.names yExp$raw_nb<2> +0 +.names yExp$raw_nb<3> +0 +# yMant = 0 +.names yMant$raw_nc<0> +0 +.names yMant$raw_nc<1> +0 +.names yMant$raw_nc<2> +0 +.names yMant$raw_nc<3> +0 +# signProd = 0 +.names signProd$raw_nd +0 +# expProd = 0 +.names expProd$raw_ne<0> +0 +.names expProd$raw_ne<1> +0 +.names expProd$raw_ne<2> +0 +.names expProd$raw_ne<3> +0 +.names expProd$raw_ne<4> +0 +.names expProd$raw_ne<5> +0 +# mantProd = 0 +.names mantProd$raw_nf<0> +0 +.names mantProd$raw_nf<1> +0 +.names mantProd$raw_nf<2> +0 +.names mantProd$raw_nf<3> +0 +.names mantProd$raw_nf<4> +0 +.names mantProd$raw_nf<5> +0 +.names mantProd$raw_nf<6> +0 +.names mantProd$raw_nf<7> +0 +# z = 0 +.names z$raw_n10<0> +0 +.names z$raw_n10<1> +0 +.names z$raw_n10<2> +0 +.names z$raw_n10<3> +0 +.names z$raw_n10<4> +0 +.names z$raw_n10<5> +0 +.names z$raw_n10<6> +0 +.names z$raw_n10<7> +0 +# state = 0 +.names state$raw_n11<0> +0 +.names state$raw_n11<1> +0 +# non-blocking assignments for initial +.names _n14<0> +0 +.names _n14<1> +0 +.names state<0> _n14<0> _n15<0> +.def 0 +0 1 1 +1 0 1 +.names state<1> _n14<1> _n15<1> +.def 0 +0 1 1 +1 0 1 +.names _n15<0> _n15<1> _n16 +.def 1 +0 0 0 +.names _n16 _n13 +0 1 +1 0 +.names _n13 _n12 +1 1 +0 0 +.names start _n17 +- =start +# xSign = x [3 + 4] +.names x<7> xSign$start_n18$true +- =x<7> +# xExp = x [3 + 4 - 1 : 3] +.names x<3> xExp$start_n19$true<0> +- =x<3> +.names x<4> xExp$start_n19$true<1> +- =x<4> +.names x<5> xExp$start_n19$true<2> +- =x<5> +.names x<6> xExp$start_n19$true<3> +- =x<6> +# xMant = {'b1, x [3 - 1 : 0]} +.names x<0> _n1b<0> +- =x<0> +.names x<1> _n1b<1> +- =x<1> +.names x<2> _n1b<2> +- =x<2> +.names _n1c +1 +.names _n1c _n1b<3> +- =_n1c +.names _n1d +0 +.names _n1b<0> xMant$start_n1a$true<0> +- =_n1b<0> +.names _n1b<1> xMant$start_n1a$true<1> +- =_n1b<1> +.names _n1b<2> xMant$start_n1a$true<2> +- =_n1b<2> +.names _n1b<3> xMant$start_n1a$true<3> +- =_n1b<3> +# ySign = y [3 + 4] +.names y<7> ySign$start_n1e$true +- =y<7> +# yExp = y [3 + 4 - 1 : 3] +.names y<3> yExp$start_n1f$true<0> +- =y<3> +.names y<4> yExp$start_n1f$true<1> +- =y<4> +.names y<5> yExp$start_n1f$true<2> +- =y<5> +.names y<6> yExp$start_n1f$true<3> +- =y<6> +# yMant = {'b1, y [3 - 1 : 0]} +.names y<0> _n21<0> +- =y<0> +.names y<1> _n21<1> +- =y<1> +.names y<2> _n21<2> +- =y<2> +.names _n22 +1 +.names _n22 _n21<3> +- =_n22 +.names _n23 +0 +.names _n21<0> yMant$start_n20$true<0> +- =_n21<0> +.names _n21<1> yMant$start_n20$true<1> +- =_n21<1> +.names _n21<2> yMant$start_n20$true<2> +- =_n21<2> +.names _n21<3> yMant$start_n20$true<3> +- =_n21<3> +# state = 1 +.names state$start_n24$true<0> +1 +.names state$start_n24$true<1> +0 +# if/else (start ) +.names yMant$start_n20$true<0> yMant<0> start yMant$start$raw_n33<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yMant$start_n20$true<1> yMant<1> start yMant$start$raw_n33<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yMant$start_n20$true<2> yMant<2> start yMant$start$raw_n33<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yMant$start_n20$true<3> yMant<3> start yMant$start$raw_n33<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yExp$start_n1f$true<0> yExp<0> start yExp$start$raw_n38<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yExp$start_n1f$true<1> yExp<1> start yExp$start$raw_n38<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yExp$start_n1f$true<2> yExp<2> start yExp$start$raw_n38<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yExp$start_n1f$true<3> yExp<3> start yExp$start$raw_n38<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names ySign$start_n1e$true ySign start ySign$start$raw_n3d +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xExp$start_n19$true<0> xExp<0> start xExp$start$raw_n3f<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xExp$start_n19$true<1> xExp<1> start xExp$start$raw_n3f<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xExp$start_n19$true<2> xExp<2> start xExp$start$raw_n3f<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xExp$start_n19$true<3> xExp<3> start xExp$start$raw_n3f<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xSign$start_n18$true xSign start xSign$start$raw_n44 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state$start_n24$true<0> state<0> start state$start$raw_n46<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state$start_n24$true<1> state<1> start state$start$raw_n46<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xMant$start_n1a$true<0> xMant<0> start xMant$start$raw_n49<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xMant$start_n1a$true<1> xMant<1> start xMant$start$raw_n49<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xMant$start_n1a$true<2> xMant<2> start xMant$start$raw_n49<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xMant$start_n1a$true<3> xMant<3> start xMant$start$raw_n49<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n50<0> +1 +.names _n50<1> +0 +.names state<0> _n50<0> _n51<0> +.def 0 +0 1 1 +1 0 1 +.names state<1> _n50<1> _n51<1> +.def 0 +0 1 1 +1 0 1 +.names _n51<0> _n51<1> _n52 +.def 1 +0 0 0 +.names _n52 _n4f +0 1 +1 0 +.names _n4f _n4e +1 1 +0 0 +# mantProd = combZ +.names combZ<0> mantProd$_n4e_n53$true<0> +- =combZ<0> +.names combZ<1> mantProd$_n4e_n53$true<1> +- =combZ<1> +.names combZ<2> mantProd$_n4e_n53$true<2> +- =combZ<2> +.names combZ<3> mantProd$_n4e_n53$true<3> +- =combZ<3> +.names combZ<4> mantProd$_n4e_n53$true<4> +- =combZ<4> +.names combZ<5> mantProd$_n4e_n53$true<5> +- =combZ<5> +.names combZ<6> mantProd$_n4e_n53$true<6> +- =combZ<6> +.names combZ<7> mantProd$_n4e_n53$true<7> +- =combZ<7> +.subckt Zero _n55 Zero<0>=_n54<0> aExp<0>=xExp<0> aExp<1>=xExp<1> aExp<2>=xExp<2> aExp<3>=xExp<3> aMant<0>=xMant<0> aMant<1>=xMant<1> aMant<2>=xMant<2> +.subckt Zero _n57 Zero<0>=_n56<0> aExp<0>=yExp<0> aExp<1>=yExp<1> aExp<2>=yExp<2> aExp<3>=yExp<3> aMant<0>=yMant<0> aMant<1>=yMant<1> aMant<2>=yMant<2> +# Zero (xExp ,xMant ) || Zero (yExp ,yMant ) +.names _n54<0> _n56<0> _n58<0> +.def 1 +0 0 0 +.names _n58<0> _n5a +.def 1 +0 0 +.names _n5a _n59 +- =_n5a +# expProd = 0 +.names expProd$_n58_n5b$true<0> +0 +.names expProd$_n58_n5b$true<1> +0 +.names expProd$_n58_n5b$true<2> +0 +.names expProd$_n58_n5b$true<3> +0 +.names expProd$_n58_n5b$true<4> +0 +.names expProd$_n58_n5b$true<5> +0 +# expProd = xExp + yExp - {'b1} +# xExp + yExp +.names _n5e +0 +.names xExp<0> yExp<0> _n5e _n5d<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n60 +0 +.names xExp<0> yExp<0> _n60 _n5f +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names xExp<1> yExp<1> _n5f _n5d<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names xExp<1> yExp<1> _n5f _n61 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names xExp<2> yExp<2> _n61 _n5d<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names xExp<2> yExp<2> _n61 _n62 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names xExp<3> yExp<3> _n62 _n5d<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names xExp<3> yExp<3> _n62 _n63 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n63 _n5d<4> +1 1 +0 0 +.names _n65 +1 +.names _n65 _n64<0> +- =_n65 +.names _n66 +0 +.names _n67 +1 +.names _n67 _n64<1> +- =_n67 +.names _n68 +0 +.names _n69 +1 +.names _n69 _n64<2> +- =_n69 +.names _n6a +0 +# xExp + yExp - {'b1} +.names _n6c +0 +.names _n5d<0> _n64<0> _n6c _n6b<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n6e +0 +.names _n5d<0> _n64<0> _n6e _n6d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n5d<1> _n64<1> _n6d _n6b<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n5d<1> _n64<1> _n6d _n6f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n5d<2> _n64<2> _n6f _n6b<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n5d<2> _n64<2> _n6f _n70 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n70 _n6b<3> +1 1 +0 0 +.names _n6b<4> +0 +.names _n6b<5> +0 +.names _n6b<0> expProd$_n58_n5c$false<0> +- =_n6b<0> +.names _n6b<1> expProd$_n58_n5c$false<1> +- =_n6b<1> +.names _n6b<2> expProd$_n58_n5c$false<2> +- =_n6b<2> +.names _n6b<3> expProd$_n58_n5c$false<3> +- =_n6b<3> +.names _n6b<4> expProd$_n58_n5c$false<4> +- =_n6b<4> +.names _n6b<5> expProd$_n58_n5c$false<5> +- =_n6b<5> +# if/else (Zero (xExp ,xMant ) || Zero (yExp ,yMant ) ) +.names _n58<0> _n75 +.def 1 +0 0 +.names expProd$_n58_n5b$true<0> expProd$_n58_n5c$false<0> _n75 expProd$_n58$raw_n74<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd$_n58_n5b$true<1> expProd$_n58_n5c$false<1> _n75 expProd$_n58$raw_n74<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd$_n58_n5b$true<2> expProd$_n58_n5c$false<2> _n75 expProd$_n58$raw_n74<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd$_n58_n5b$true<3> expProd$_n58_n5c$false<3> _n75 expProd$_n58$raw_n74<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd$_n58_n5b$true<4> expProd$_n58_n5c$false<4> _n75 expProd$_n58$raw_n74<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd$_n58_n5b$true<5> expProd$_n58_n5c$false<5> _n75 expProd$_n58$raw_n74<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# signProd = xSign ^ ySign +# xSign ^ ySign +.names xSign ySign _n81 +.def 0 +0 1 1 +1 0 1 +.names _n81 signProd$_n4e_n80$true +- =_n81 +# state = 2 +.names state$_n4e_n82$true<0> +0 +.names state$_n4e_n82$true<1> +1 +.names _n85<0> +0 +.names _n85<1> +1 +.names state<0> _n85<0> _n86<0> +.def 0 +0 1 1 +1 0 1 +.names state<1> _n85<1> _n86<1> +.def 0 +0 1 1 +1 0 1 +.names _n86<0> _n86<1> _n87 +.def 1 +0 0 0 +.names _n87 _n84 +0 1 +1 0 +.names _n84 _n83 +1 1 +0 0 +.subckt NaN _n89 NaN<0>=_n88<0> aExp<0>=xExp<0> aExp<1>=xExp<1> aExp<2>=xExp<2> aExp<3>=xExp<3> aMant<0>=xMant<0> aMant<1>=xMant<1> aMant<2>=xMant<2> +.subckt NaN _n8b NaN<0>=_n8a<0> aExp<0>=yExp<0> aExp<1>=yExp<1> aExp<2>=yExp<2> aExp<3>=yExp<3> aMant<0>=yMant<0> aMant<1>=yMant<1> aMant<2>=yMant<2> +# NaN (xExp ,xMant ) || NaN (yExp ,yMant ) +.names _n88<0> _n8a<0> _n8c<0> +.def 1 +0 0 0 +.subckt Infinity _n8e Infinity<0>=_n8d<0> aExp<0>=xExp<0> aExp<1>=xExp<1> aExp<2>=xExp<2> aExp<3>=xExp<3> aMant<0>=xMant<0> aMant<1>=xMant<1> aMant<2>=xMant<2> +.subckt Zero _n90 Zero<0>=_n8f<0> aExp<0>=yExp<0> aExp<1>=yExp<1> aExp<2>=yExp<2> aExp<3>=yExp<3> aMant<0>=yMant<0> aMant<1>=yMant<1> aMant<2>=yMant<2> +# Infinity (xExp ,xMant ) && Zero (yExp ,yMant ) +.names _n8d<0> _n8f<0> _n91<0> +.def 0 +1 1 1 +# NaN (xExp ,xMant ) || NaN (yExp ,yMant ) || Infinity (xExp ,xMant ) && Zero (yExp ,yMant ) +.names _n8c<0> _n91<0> _n92<0> +.def 1 +0 0 0 +.subckt Zero _n94 Zero<0>=_n93<0> aExp<0>=xExp<0> aExp<1>=xExp<1> aExp<2>=xExp<2> aExp<3>=xExp<3> aMant<0>=xMant<0> aMant<1>=xMant<1> aMant<2>=xMant<2> +.subckt Infinity _n96 Infinity<0>=_n95<0> aExp<0>=yExp<0> aExp<1>=yExp<1> aExp<2>=yExp<2> aExp<3>=yExp<3> aMant<0>=yMant<0> aMant<1>=yMant<1> aMant<2>=yMant<2> +# Zero (xExp ,xMant ) && Infinity (yExp ,yMant ) +.names _n93<0> _n95<0> _n97<0> +.def 0 +1 1 1 +# NaN (xExp ,xMant ) || NaN (yExp ,yMant ) || Infinity (xExp ,xMant ) && Zero (yExp ,yMant ) || Zero (xExp ,xMant ) && Infinity (yExp ,yMant ) +.names _n92<0> _n97<0> _n98<0> +.def 1 +0 0 0 +.names _n98<0> _n9a +.def 1 +0 0 +.names _n9a _n99 +- =_n9a +# z = {'b0, {'b1}, {'b1}} +.names _n9e +1 +.names _n9e _n9d<0> +- =_n9e +.names _n9f +0 +.names _na0 +1 +.names _na0 _n9d<1> +- =_na0 +.names _na1 +0 +.names _na2 +1 +.names _na2 _n9d<2> +- =_na2 +.names _na3 +0 +.names _n9d<0> _n9c<0> +- =_n9d<0> +.names _n9d<1> _n9c<1> +- =_n9d<1> +.names _n9d<2> _n9c<2> +- =_n9d<2> +.names _na5 +1 +.names _na5 _na4<0> +- =_na5 +.names _na6 +0 +.names _na7 +1 +.names _na7 _na4<1> +- =_na7 +.names _na8 +0 +.names _na9 +1 +.names _na9 _na4<2> +- =_na9 +.names _naa +0 +.names _nab +1 +.names _nab _na4<3> +- =_nab +.names _nac +0 +.names _na4<0> _n9c<3> +- =_na4<0> +.names _na4<1> _n9c<4> +- =_na4<1> +.names _na4<2> _n9c<5> +- =_na4<2> +.names _na4<3> _n9c<6> +- =_na4<3> +.names _nad +0 +.names _nad _n9c<7> +- =_nad +.names _nae +0 +.names _n9c<0> z$_n98_n9b$true<0> +- =_n9c<0> +.names _n9c<1> z$_n98_n9b$true<1> +- =_n9c<1> +.names _n9c<2> z$_n98_n9b$true<2> +- =_n9c<2> +.names _n9c<3> z$_n98_n9b$true<3> +- =_n9c<3> +.names _n9c<4> z$_n98_n9b$true<4> +- =_n9c<4> +.names _n9c<5> z$_n98_n9b$true<5> +- =_n9c<5> +.names _n9c<6> z$_n98_n9b$true<6> +- =_n9c<6> +.names _n9c<7> z$_n98_n9b$true<7> +- =_n9c<7> +.subckt Infinity _nb0 Infinity<0>=_naf<0> aExp<0>=xExp<0> aExp<1>=xExp<1> aExp<2>=xExp<2> aExp<3>=xExp<3> aMant<0>=xMant<0> aMant<1>=xMant<1> aMant<2>=xMant<2> +.subckt Infinity _nb2 Infinity<0>=_nb1<0> aExp<0>=yExp<0> aExp<1>=yExp<1> aExp<2>=yExp<2> aExp<3>=yExp<3> aMant<0>=yMant<0> aMant<1>=yMant<1> aMant<2>=yMant<2> +# Infinity (xExp ,xMant ) || Infinity (yExp ,yMant ) +.names _naf<0> _nb1<0> _nb3<0> +.def 1 +0 0 0 +.names _nb3<0> _nb5 +.def 1 +0 0 +.names _nb5 _nb4 +- =_nb5 +# z = {signProd , {'b1}, {'b0}} +.names _nb9 +0 +.names _nb9 _nb8<0> +- =_nb9 +.names _nba +0 +.names _nbb +0 +.names _nbb _nb8<1> +- =_nbb +.names _nbc +0 +.names _nbd +0 +.names _nbd _nb8<2> +- =_nbd +.names _nbe +0 +.names _nb8<0> _nb7<0> +- =_nb8<0> +.names _nb8<1> _nb7<1> +- =_nb8<1> +.names _nb8<2> _nb7<2> +- =_nb8<2> +.names _nc0 +1 +.names _nc0 _nbf<0> +- =_nc0 +.names _nc1 +0 +.names _nc2 +1 +.names _nc2 _nbf<1> +- =_nc2 +.names _nc3 +0 +.names _nc4 +1 +.names _nc4 _nbf<2> +- =_nc4 +.names _nc5 +0 +.names _nc6 +1 +.names _nc6 _nbf<3> +- =_nc6 +.names _nc7 +0 +.names _nbf<0> _nb7<3> +- =_nbf<0> +.names _nbf<1> _nb7<4> +- =_nbf<1> +.names _nbf<2> _nb7<5> +- =_nbf<2> +.names _nbf<3> _nb7<6> +- =_nbf<3> +.names signProd _nb7<7> +- =signProd +.names _nc8 +0 +.names _nb7<0> z$_nb3_nb6$true<0> +- =_nb7<0> +.names _nb7<1> z$_nb3_nb6$true<1> +- =_nb7<1> +.names _nb7<2> z$_nb3_nb6$true<2> +- =_nb7<2> +.names _nb7<3> z$_nb3_nb6$true<3> +- =_nb7<3> +.names _nb7<4> z$_nb3_nb6$true<4> +- =_nb7<4> +.names _nb7<5> z$_nb3_nb6$true<5> +- =_nb7<5> +.names _nb7<6> z$_nb3_nb6$true<6> +- =_nb7<6> +.names _nb7<7> z$_nb3_nb6$true<7> +- =_nb7<7> +.names _nca<0> +0 +.names _nca<1> +0 +.names _nca<2> +0 +.names _nca<3> +0 +.names _nca<4> +0 +.names _nca<5> +0 +# scaledExp == 0 +.names scaledExp<0> _nca<0> _ncb<0> +.def 0 +0 1 1 +1 0 1 +.names scaledExp<1> _nca<1> _ncb<1> +.def 0 +0 1 1 +1 0 1 +.names scaledExp<2> _nca<2> _ncb<2> +.def 0 +0 1 1 +1 0 1 +.names scaledExp<3> _nca<3> _ncb<3> +.def 0 +0 1 1 +1 0 1 +.names scaledExp<4> _nca<4> _ncb<4> +.def 0 +0 1 1 +1 0 1 +.names scaledExp<5> _nca<5> _ncb<5> +.def 0 +0 1 1 +1 0 1 +.names _ncb<0> _ncb<1> _ncb<2> _ncb<3> _ncb<4> _ncb<5> _ncc +.def 1 +0 0 0 0 0 0 0 +.names _ncc _nc9 +0 1 +1 0 +# scaledExp [4 + 1] || scaledExp == 0 +.names scaledExp<5> _nc9 _ncd<5> +.def 1 +0 0 0 +.names _nce +0 +.names _ncd<5> _nd0 +.def 1 +0 0 +.names _nd0 _ncf +- =_nd0 +# z = {signProd , {'b0}} +.names _nd4 +0 +.names _nd4 _nd3<0> +- =_nd4 +.names _nd5 +0 +.names _nd6 +0 +.names _nd6 _nd3<1> +- =_nd6 +.names _nd7 +0 +.names _nd8 +0 +.names _nd8 _nd3<2> +- =_nd8 +.names _nd9 +0 +.names _nda +0 +.names _nda _nd3<3> +- =_nda +.names _ndb +0 +.names _ndc +0 +.names _ndc _nd3<4> +- =_ndc +.names _ndd +0 +.names _nde +0 +.names _nde _nd3<5> +- =_nde +.names _ndf +0 +.names _ne0 +0 +.names _ne0 _nd3<6> +- =_ne0 +.names _ne1 +0 +.names _nd3<0> _nd2<0> +- =_nd3<0> +.names _nd3<1> _nd2<1> +- =_nd3<1> +.names _nd3<2> _nd2<2> +- =_nd3<2> +.names _nd3<3> _nd2<3> +- =_nd3<3> +.names _nd3<4> _nd2<4> +- =_nd3<4> +.names _nd3<5> _nd2<5> +- =_nd3<5> +.names _nd3<6> _nd2<6> +- =_nd3<6> +.names signProd _nd2<7> +- =signProd +.names _ne2 +0 +.names _nd2<0> z$_ncd_nd1$true<0> +- =_nd2<0> +.names _nd2<1> z$_ncd_nd1$true<1> +- =_nd2<1> +.names _nd2<2> z$_ncd_nd1$true<2> +- =_nd2<2> +.names _nd2<3> z$_ncd_nd1$true<3> +- =_nd2<3> +.names _nd2<4> z$_ncd_nd1$true<4> +- =_nd2<4> +.names _nd2<5> z$_ncd_nd1$true<5> +- =_nd2<5> +.names _nd2<6> z$_ncd_nd1$true<6> +- =_nd2<6> +.names _nd2<7> z$_ncd_nd1$true<7> +- =_nd2<7> +.names _ne4 +1 +.names _ne4 _ne3<0> +- =_ne4 +.names _ne5 +0 +.names _ne6 +1 +.names _ne6 _ne3<1> +- =_ne6 +.names _ne7 +0 +.names _ne8 +1 +.names _ne8 _ne3<2> +- =_ne8 +.names _ne9 +0 +.names _nea +1 +.names _nea _ne3<3> +- =_nea +.names _neb +0 +# scaledExp >= {'b1} +.names _nee +0 +.names scaledExp<0> _ne3<0> _nee _ned<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _nf0 +0 +.names scaledExp<0> _ne3<0> _nf0 _nef +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names scaledExp<1> _ne3<1> _nef _ned<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names scaledExp<1> _ne3<1> _nef _nf1 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names scaledExp<2> _ne3<2> _nf1 _ned<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names scaledExp<2> _ne3<2> _nf1 _nf2 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names scaledExp<3> _ne3<3> _nf2 _ned<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names scaledExp<3> _ne3<3> _nf2 _nf3 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _nf4 +0 +.names scaledExp<4> _nf4 _nf3 _ned<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names scaledExp<4> _nf4 _nf3 _nf5 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _nf6 +0 +.names scaledExp<5> _nf6 _nf5 _ned<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names scaledExp<5> _nf6 _nf5 _nf7 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _ned<0> _ned<1> _ned<2> _ned<3> _ned<4> _ned<5> _nf8 +.def 1 +0 0 0 0 0 0 0 +.names _nf7 _nf8 _nf9 +.def 0 +1 1 1 +.names _nf9 _nec +0 1 +1 0 +.names _nec _nfa +- =_nec +# z = {signProd , {'b1}, {'b0}} +.names _nfe +0 +.names _nfe _nfd<0> +- =_nfe +.names _nff +0 +.names _n100 +0 +.names _n100 _nfd<1> +- =_n100 +.names _n101 +0 +.names _n102 +0 +.names _n102 _nfd<2> +- =_n102 +.names _n103 +0 +.names _nfd<0> _nfc<0> +- =_nfd<0> +.names _nfd<1> _nfc<1> +- =_nfd<1> +.names _nfd<2> _nfc<2> +- =_nfd<2> +.names _n105 +1 +.names _n105 _n104<0> +- =_n105 +.names _n106 +0 +.names _n107 +1 +.names _n107 _n104<1> +- =_n107 +.names _n108 +0 +.names _n109 +1 +.names _n109 _n104<2> +- =_n109 +.names _n10a +0 +.names _n10b +1 +.names _n10b _n104<3> +- =_n10b +.names _n10c +0 +.names _n104<0> _nfc<3> +- =_n104<0> +.names _n104<1> _nfc<4> +- =_n104<1> +.names _n104<2> _nfc<5> +- =_n104<2> +.names _n104<3> _nfc<6> +- =_n104<3> +.names signProd _nfc<7> +- =signProd +.names _n10d +0 +.names _nfc<0> z$_nec_nfb$true<0> +- =_nfc<0> +.names _nfc<1> z$_nec_nfb$true<1> +- =_nfc<1> +.names _nfc<2> z$_nec_nfb$true<2> +- =_nfc<2> +.names _nfc<3> z$_nec_nfb$true<3> +- =_nfc<3> +.names _nfc<4> z$_nec_nfb$true<4> +- =_nfc<4> +.names _nfc<5> z$_nec_nfb$true<5> +- =_nfc<5> +.names _nfc<6> z$_nec_nfb$true<6> +- =_nfc<6> +.names _nfc<7> z$_nec_nfb$true<7> +- =_nfc<7> +# z = {signProd , scaledExp [4 - 1 : 0], scaledMant } +.names scaledMant<0> _n10f<0> +- =scaledMant<0> +.names scaledMant<1> _n10f<1> +- =scaledMant<1> +.names scaledMant<2> _n10f<2> +- =scaledMant<2> +.names scaledExp<0> _n10f<3> +- =scaledExp<0> +.names scaledExp<1> _n10f<4> +- =scaledExp<1> +.names scaledExp<2> _n10f<5> +- =scaledExp<2> +.names scaledExp<3> _n10f<6> +- =scaledExp<3> +.names signProd _n10f<7> +- =signProd +.names _n110 +0 +.names _n10f<0> z$_nec_n10e$false<0> +- =_n10f<0> +.names _n10f<1> z$_nec_n10e$false<1> +- =_n10f<1> +.names _n10f<2> z$_nec_n10e$false<2> +- =_n10f<2> +.names _n10f<3> z$_nec_n10e$false<3> +- =_n10f<3> +.names _n10f<4> z$_nec_n10e$false<4> +- =_n10f<4> +.names _n10f<5> z$_nec_n10e$false<5> +- =_n10f<5> +.names _n10f<6> z$_nec_n10e$false<6> +- =_n10f<6> +.names _n10f<7> z$_nec_n10e$false<7> +- =_n10f<7> +# if/else (scaledExp >= {'b1}) +.names z$_nec_nfb$true<0> z$_nec_n10e$false<0> _nec z$_nec$raw_n112<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nec_nfb$true<1> z$_nec_n10e$false<1> _nec z$_nec$raw_n112<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nec_nfb$true<2> z$_nec_n10e$false<2> _nec z$_nec$raw_n112<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nec_nfb$true<3> z$_nec_n10e$false<3> _nec z$_nec$raw_n112<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nec_nfb$true<4> z$_nec_n10e$false<4> _nec z$_nec$raw_n112<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nec_nfb$true<5> z$_nec_n10e$false<5> _nec z$_nec$raw_n112<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nec_nfb$true<6> z$_nec_n10e$false<6> _nec z$_nec$raw_n112<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nec_nfb$true<7> z$_nec_n10e$false<7> _nec z$_nec$raw_n112<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (scaledExp [4 + 1] || scaledExp == 0) +.names _ncd<5> _n11f +.def 1 +0 0 +.names z$_ncd_nd1$true<0> z$_nec$raw_n112<0> _n11f z$_ncd$raw_n11e<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_ncd_nd1$true<1> z$_nec$raw_n112<1> _n11f z$_ncd$raw_n11e<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_ncd_nd1$true<2> z$_nec$raw_n112<2> _n11f z$_ncd$raw_n11e<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_ncd_nd1$true<3> z$_nec$raw_n112<3> _n11f z$_ncd$raw_n11e<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_ncd_nd1$true<4> z$_nec$raw_n112<4> _n11f z$_ncd$raw_n11e<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_ncd_nd1$true<5> z$_nec$raw_n112<5> _n11f z$_ncd$raw_n11e<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_ncd_nd1$true<6> z$_nec$raw_n112<6> _n11f z$_ncd$raw_n11e<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_ncd_nd1$true<7> z$_nec$raw_n112<7> _n11f z$_ncd$raw_n11e<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (Infinity (xExp ,xMant ) || Infinity (yExp ,yMant ) ) +.names _nb3<0> _n12c +.def 1 +0 0 +.names z$_nb3_nb6$true<0> z$_ncd$raw_n11e<0> _n12c z$_nb3$raw_n12b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nb3_nb6$true<1> z$_ncd$raw_n11e<1> _n12c z$_nb3$raw_n12b<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nb3_nb6$true<2> z$_ncd$raw_n11e<2> _n12c z$_nb3$raw_n12b<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nb3_nb6$true<3> z$_ncd$raw_n11e<3> _n12c z$_nb3$raw_n12b<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nb3_nb6$true<4> z$_ncd$raw_n11e<4> _n12c z$_nb3$raw_n12b<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nb3_nb6$true<5> z$_ncd$raw_n11e<5> _n12c z$_nb3$raw_n12b<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nb3_nb6$true<6> z$_ncd$raw_n11e<6> _n12c z$_nb3$raw_n12b<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_nb3_nb6$true<7> z$_ncd$raw_n11e<7> _n12c z$_nb3$raw_n12b<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (NaN (xExp ,xMant ) || NaN (yExp ,yMant ) || Infinity (xExp ,xMant ) && Zero (yExp ,yMant ) || Zero (xExp ,xMant ) && Infinity (yExp ,yMant ) ) +.names _n98<0> _n139 +.def 1 +0 0 +.names z$_n98_n9b$true<0> z$_nb3$raw_n12b<0> _n139 z$_n98$raw_n138<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98_n9b$true<1> z$_nb3$raw_n12b<1> _n139 z$_n98$raw_n138<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98_n9b$true<2> z$_nb3$raw_n12b<2> _n139 z$_n98$raw_n138<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98_n9b$true<3> z$_nb3$raw_n12b<3> _n139 z$_n98$raw_n138<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98_n9b$true<4> z$_nb3$raw_n12b<4> _n139 z$_n98$raw_n138<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98_n9b$true<5> z$_nb3$raw_n12b<5> _n139 z$_n98$raw_n138<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98_n9b$true<6> z$_nb3$raw_n12b<6> _n139 z$_n98$raw_n138<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98_n9b$true<7> z$_nb3$raw_n12b<7> _n139 z$_n98$raw_n138<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# state = 0 +.names state$_n83_n144$true<0> +0 +.names state$_n83_n144$true<1> +0 +# case (state ) +.names z$_n98$raw_n138<0> z<0> _n83 z$_n83$raw_n149<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98$raw_n138<1> z<1> _n83 z$_n83$raw_n149<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98$raw_n138<2> z<2> _n83 z$_n83$raw_n149<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98$raw_n138<3> z<3> _n83 z$_n83$raw_n149<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98$raw_n138<4> z<4> _n83 z$_n83$raw_n149<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98$raw_n138<5> z<5> _n83 z$_n83$raw_n149<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98$raw_n138<6> z<6> _n83 z$_n83$raw_n149<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z$_n98$raw_n138<7> z<7> _n83 z$_n83$raw_n149<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state$_n83_n144$true<0> state<0> _n83 state$_n83$raw_n152<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state$_n83_n144$true<1> state<1> _n83 state$_n83$raw_n152<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state$_n4e_n82$true<0> state$_n83$raw_n152<0> _n4e state$_n4e$raw_n157<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state$_n4e_n82$true<1> state$_n83$raw_n152<1> _n4e state$_n4e$raw_n157<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names signProd$_n4e_n80$true signProd _n4e signProd$_n4e$raw_n15f +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd$_n4e_n53$true<0> mantProd<0> _n4e mantProd$_n4e$raw_n161<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd$_n4e_n53$true<1> mantProd<1> _n4e mantProd$_n4e$raw_n161<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd$_n4e_n53$true<2> mantProd<2> _n4e mantProd$_n4e$raw_n161<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd$_n4e_n53$true<3> mantProd<3> _n4e mantProd$_n4e$raw_n161<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd$_n4e_n53$true<4> mantProd<4> _n4e mantProd$_n4e$raw_n161<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd$_n4e_n53$true<5> mantProd<5> _n4e mantProd$_n4e$raw_n161<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd$_n4e_n53$true<6> mantProd<6> _n4e mantProd$_n4e$raw_n161<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd$_n4e_n53$true<7> mantProd<7> _n4e mantProd$_n4e$raw_n161<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd$_n58$raw_n74<0> expProd<0> _n4e expProd$_n4e$raw_n16b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd$_n58$raw_n74<1> expProd<1> _n4e expProd$_n4e$raw_n16b<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd$_n58$raw_n74<2> expProd<2> _n4e expProd$_n4e$raw_n16b<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd$_n58$raw_n74<3> expProd<3> _n4e expProd$_n4e$raw_n16b<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd$_n58$raw_n74<4> expProd<4> _n4e expProd$_n4e$raw_n16b<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd$_n58$raw_n74<5> expProd<5> _n4e expProd$_n4e$raw_n16b<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<0> z$_n83$raw_n149<0> _n4e z$_n4e$raw_n172<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<1> z$_n83$raw_n149<1> _n4e z$_n4e$raw_n172<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<2> z$_n83$raw_n149<2> _n4e z$_n4e$raw_n172<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<3> z$_n83$raw_n149<3> _n4e z$_n4e$raw_n172<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<4> z$_n83$raw_n149<4> _n4e z$_n4e$raw_n172<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<5> z$_n83$raw_n149<5> _n4e z$_n4e$raw_n172<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<6> z$_n83$raw_n149<6> _n4e z$_n4e$raw_n172<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<7> z$_n83$raw_n149<7> _n4e z$_n4e$raw_n172<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state$start$raw_n46<0> state$_n4e$raw_n157<0> _n12 state$_n12$raw_n182<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names state$start$raw_n46<1> state$_n4e$raw_n157<1> _n12 state$_n12$raw_n182<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yMant$start$raw_n33<0> yMant<0> _n12 yMant$_n12$raw_n18c<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yMant$start$raw_n33<1> yMant<1> _n12 yMant$_n12$raw_n18c<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yMant$start$raw_n33<2> yMant<2> _n12 yMant$_n12$raw_n18c<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yMant$start$raw_n33<3> yMant<3> _n12 yMant$_n12$raw_n18c<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names ySign$start$raw_n3d ySign _n12 ySign$_n12$raw_n191 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yExp$start$raw_n38<0> yExp<0> _n12 yExp$_n12$raw_n193<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yExp$start$raw_n38<1> yExp<1> _n12 yExp$_n12$raw_n193<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yExp$start$raw_n38<2> yExp<2> _n12 yExp$_n12$raw_n193<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names yExp$start$raw_n38<3> yExp<3> _n12 yExp$_n12$raw_n193<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xExp$start$raw_n3f<0> xExp<0> _n12 xExp$_n12$raw_n198<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xExp$start$raw_n3f<1> xExp<1> _n12 xExp$_n12$raw_n198<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xExp$start$raw_n3f<2> xExp<2> _n12 xExp$_n12$raw_n198<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xExp$start$raw_n3f<3> xExp<3> _n12 xExp$_n12$raw_n198<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xSign$start$raw_n44 xSign _n12 xSign$_n12$raw_n19d +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xMant$start$raw_n49<0> xMant<0> _n12 xMant$_n12$raw_n19f<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xMant$start$raw_n49<1> xMant<1> _n12 xMant$_n12$raw_n19f<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xMant$start$raw_n49<2> xMant<2> _n12 xMant$_n12$raw_n19f<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names xMant$start$raw_n49<3> xMant<3> _n12 xMant$_n12$raw_n19f<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names signProd signProd$_n4e$raw_n15f _n12 signProd$_n12$raw_n1a5 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<0> z$_n4e$raw_n172<0> _n12 z$_n12$raw_n1a7<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<1> z$_n4e$raw_n172<1> _n12 z$_n12$raw_n1a7<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<2> z$_n4e$raw_n172<2> _n12 z$_n12$raw_n1a7<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<3> z$_n4e$raw_n172<3> _n12 z$_n12$raw_n1a7<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<4> z$_n4e$raw_n172<4> _n12 z$_n12$raw_n1a7<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<5> z$_n4e$raw_n172<5> _n12 z$_n12$raw_n1a7<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<6> z$_n4e$raw_n172<6> _n12 z$_n12$raw_n1a7<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names z<7> z$_n4e$raw_n172<7> _n12 z$_n12$raw_n1a7<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd<0> mantProd$_n4e$raw_n161<0> _n12 mantProd$_n12$raw_n1b0<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd<1> mantProd$_n4e$raw_n161<1> _n12 mantProd$_n12$raw_n1b0<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd<2> mantProd$_n4e$raw_n161<2> _n12 mantProd$_n12$raw_n1b0<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd<3> mantProd$_n4e$raw_n161<3> _n12 mantProd$_n12$raw_n1b0<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd<4> mantProd$_n4e$raw_n161<4> _n12 mantProd$_n12$raw_n1b0<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd<5> mantProd$_n4e$raw_n161<5> _n12 mantProd$_n12$raw_n1b0<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd<6> mantProd$_n4e$raw_n161<6> _n12 mantProd$_n12$raw_n1b0<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names mantProd<7> mantProd$_n4e$raw_n161<7> _n12 mantProd$_n12$raw_n1b0<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd<0> expProd$_n4e$raw_n16b<0> _n12 expProd$_n12$raw_n1ba<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd<1> expProd$_n4e$raw_n16b<1> _n12 expProd$_n12$raw_n1ba<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd<2> expProd$_n4e$raw_n16b<2> _n12 expProd$_n12$raw_n1ba<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd<3> expProd$_n4e$raw_n16b<3> _n12 expProd$_n12$raw_n1ba<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd<4> expProd$_n4e$raw_n16b<4> _n12 expProd$_n12$raw_n1ba<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names expProd<5> expProd$_n4e$raw_n16b<5> _n12 expProd$_n12$raw_n1ba<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# assign msb = mantProd [2 * 3 + 1] +.names mantProd<7> msb$raw_n1c1 +- =mantProd<7> +# assign lsb = mantProd [3 + 1] +.names mantProd<4> lsb$raw_n1c2 +- =mantProd<4> +# assign guard = mantProd [3] +.names mantProd<3> guard$raw_n1c3 +- =mantProd<3> +# assign round = mantProd [3 - 1] +.names mantProd<2> round$raw_n1c4 +- =mantProd<2> +# assign sticky = |mantProd [3 - 2 : 0] +.names mantProd<0> mantProd<1> _n1c8 +.def 1 +0 0 0 +.names _n1c8 _n1c6 +- =_n1c8 +.names _n1c6 sticky$raw_n1c5 +- =_n1c6 +# assign preMant = msb ? mantProd [2 * 3 + 1 : 3] + {{'b0}, guard & (round | sticky | lsb ), 'b0} : mantProd [2 * 3 + 1 : 3] + {{'b0}, round & (sticky | guard )} +.names _n1cb +0 +.names _n1cb _n1ca<0> +- =_n1cb +.names _n1cc +0 +# round | sticky +.names round sticky _n1cd +.def 1 +0 0 0 +# round | sticky | lsb +.names _n1cd lsb _n1ce +.def 1 +0 0 0 +# guard & (round | sticky | lsb ) +.names guard _n1ce _n1cf +.def 0 +1 1 1 +.names _n1cf _n1ca<1> +- =_n1cf +.names _n1d0 +0 +.names _n1d2 +0 +.names _n1d2 _n1d1<0> +- =_n1d2 +.names _n1d3 +0 +.names _n1d4 +0 +.names _n1d4 _n1d1<1> +- =_n1d4 +.names _n1d5 +0 +.names _n1d6 +0 +.names _n1d6 _n1d1<2> +- =_n1d6 +.names _n1d7 +0 +.names _n1d1<0> _n1ca<2> +- =_n1d1<0> +.names _n1d1<1> _n1ca<3> +- =_n1d1<1> +.names _n1d1<2> _n1ca<4> +- =_n1d1<2> +# mantProd [2 * 3 + 1 : 3] + {{'b0}, guard & (round | sticky | lsb ), 'b0} +.names _n1d9 +0 +.names mantProd<3> _n1ca<0> _n1d9 _n1d8<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n1db +0 +.names mantProd<3> _n1ca<0> _n1db _n1da +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names mantProd<4> _n1ca<1> _n1da _n1d8<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names mantProd<4> _n1ca<1> _n1da _n1dc +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names mantProd<5> _n1ca<2> _n1dc _n1d8<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names mantProd<5> _n1ca<2> _n1dc _n1dd +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names mantProd<6> _n1ca<3> _n1dd _n1d8<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names mantProd<6> _n1ca<3> _n1dd _n1de +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names mantProd<7> _n1ca<4> _n1de _n1d8<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# sticky | guard +.names sticky guard _n1e0 +.def 1 +0 0 0 +# round & (sticky | guard ) +.names round _n1e0 _n1e1 +.def 0 +1 1 1 +.names _n1e1 _n1df<0> +- =_n1e1 +.names _n1e2 +0 +.names _n1e4 +0 +.names _n1e4 _n1e3<0> +- =_n1e4 +.names _n1e5 +0 +.names _n1e6 +0 +.names _n1e6 _n1e3<1> +- =_n1e6 +.names _n1e7 +0 +.names _n1e8 +0 +.names _n1e8 _n1e3<2> +- =_n1e8 +.names _n1e9 +0 +.names _n1ea +0 +.names _n1ea _n1e3<3> +- =_n1ea +.names _n1eb +0 +.names _n1e3<0> _n1df<1> +- =_n1e3<0> +.names _n1e3<1> _n1df<2> +- =_n1e3<1> +.names _n1e3<2> _n1df<3> +- =_n1e3<2> +.names _n1e3<3> _n1df<4> +- =_n1e3<3> +# mantProd [2 * 3 + 1 : 3] + {{'b0}, round & (sticky | guard )} +.names _n1ed +0 +.names mantProd<3> _n1df<0> _n1ed _n1ec<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n1ef +0 +.names mantProd<3> _n1df<0> _n1ef _n1ee +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names mantProd<4> _n1df<1> _n1ee _n1ec<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names mantProd<4> _n1df<1> _n1ee _n1f0 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names mantProd<5> _n1df<2> _n1f0 _n1ec<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names mantProd<5> _n1df<2> _n1f0 _n1f1 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names mantProd<6> _n1df<3> _n1f1 _n1ec<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names mantProd<6> _n1df<3> _n1f1 _n1f2 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names mantProd<7> _n1df<4> _n1f2 _n1ec<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# msb ? mantProd [2 * 3 + 1 : 3] + {{'b0}, guard & (round | sticky | lsb ), 'b0} : mantProd [2 * 3 + 1 : 3] + {{'b0}, round & (sticky | guard )} +.names _n1d8<0> _n1ec<0> msb _n1f3<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1d8<1> _n1ec<1> msb _n1f3<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1d8<2> _n1ec<2> msb _n1f3<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1d8<3> _n1ec<3> msb _n1f3<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1d8<4> _n1ec<4> msb _n1f3<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1f3<0> preMant$raw_n1c9<0> +- =_n1f3<0> +.names _n1f3<1> preMant$raw_n1c9<1> +- =_n1f3<1> +.names _n1f3<2> preMant$raw_n1c9<2> +- =_n1f3<2> +.names _n1f3<3> preMant$raw_n1c9<3> +- =_n1f3<3> +.names _n1f3<4> preMant$raw_n1c9<4> +- =_n1f3<4> +# assign scaledExp = preMant [3 + 1] ? expProd + 1 : expProd +.names _n1fa<0> +1 +.names _n1fa<1> +0 +.names _n1fa<2> +0 +.names _n1fa<3> +0 +.names _n1fa<4> +0 +.names _n1fa<5> +0 +# expProd + 1 +.names _n1fc +0 +.names expProd<0> _n1fa<0> _n1fc _n1fb<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n1fe +0 +.names expProd<0> _n1fa<0> _n1fe _n1fd +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names expProd<1> _n1fa<1> _n1fd _n1fb<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names expProd<1> _n1fa<1> _n1fd _n1ff +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names expProd<2> _n1fa<2> _n1ff _n1fb<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names expProd<2> _n1fa<2> _n1ff _n200 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names expProd<3> _n1fa<3> _n200 _n1fb<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names expProd<3> _n1fa<3> _n200 _n201 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names expProd<4> _n1fa<4> _n201 _n1fb<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names expProd<4> _n1fa<4> _n201 _n202 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names expProd<5> _n1fa<5> _n202 _n1fb<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# preMant [3 + 1] ? expProd + 1 : expProd +.names preMant<4> _n204 +.def 1 +0 0 +.names _n1fb<0> expProd<0> _n204 _n203<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1fb<1> expProd<1> _n204 _n203<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1fb<2> expProd<2> _n204 _n203<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1fb<3> expProd<3> _n204 _n203<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1fb<4> expProd<4> _n204 _n203<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n1fb<5> expProd<5> _n204 _n203<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n203<0> scaledExp$raw_n1f9<0> +- =_n203<0> +.names _n203<1> scaledExp$raw_n1f9<1> +- =_n203<1> +.names _n203<2> scaledExp$raw_n1f9<2> +- =_n203<2> +.names _n203<3> scaledExp$raw_n1f9<3> +- =_n203<3> +.names _n203<4> scaledExp$raw_n1f9<4> +- =_n203<4> +.names _n203<5> scaledExp$raw_n1f9<5> +- =_n203<5> +# assign scaledMant = preMant [3 + 1] ? preMant [3 : 1] : preMant [3 - 1 : 0] +# preMant [3 + 1] ? preMant [3 : 1] : preMant [3 - 1 : 0] +.names preMant<4> _n20d +.def 1 +0 0 +.names preMant<1> preMant<0> _n20d _n20c<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names preMant<2> preMant<1> _n20d _n20c<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names preMant<3> preMant<2> _n20d _n20c<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20c<0> scaledMant$raw_n20b<0> +- =_n20c<0> +.names _n20c<1> scaledMant$raw_n20b<1> +- =_n20c<1> +.names _n20c<2> scaledMant$raw_n20b<2> +- =_n20c<2> +# conflict arbitrators +.names sticky$raw_n1c5 sticky +0 0 +1 1 +.names _n12 _n4e _n211 +.def 0 + 0 1 1 +.names _n211 signProd$_n12$raw_n1a5 signProd _n212 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n12 _n4e _n213 +.def 0 + 0 1 1 +.names _n213 mantProd$_n12$raw_n1b0<0> mantProd$_n12$raw_n1b0<1> mantProd$_n12$raw_n1b0<2> mantProd$_n12$raw_n1b0<3> mantProd$_n12$raw_n1b0<4> mantProd$_n12$raw_n1b0<5> mantProd$_n12$raw_n1b0<6> mantProd$_n12$raw_n1b0<7> mantProd<0> mantProd<1> mantProd<2> mantProd<3> mantProd<4> mantProd<5> mantProd<6> mantProd<7> -> _n214<0> _n214<1> _n214<2> _n214<3> _n214<4> _n214<5> _n214<6> _n214<7> +1 - - - - - - - - - - - - - - - - =mantProd$_n12$raw_n1b0<0> =mantProd$_n12$raw_n1b0<1> =mantProd$_n12$raw_n1b0<2> =mantProd$_n12$raw_n1b0<3> =mantProd$_n12$raw_n1b0<4> =mantProd$_n12$raw_n1b0<5> =mantProd$_n12$raw_n1b0<6> =mantProd$_n12$raw_n1b0<7> +0 - - - - - - - - - - - - - - - - =mantProd<0> =mantProd<1> =mantProd<2> =mantProd<3> =mantProd<4> =mantProd<5> =mantProd<6> =mantProd<7> +.names _n12 _n17 _n215 +.def 0 + 1 1 1 +.names _n215 yMant$_n12$raw_n18c<0> yMant$_n12$raw_n18c<1> yMant$_n12$raw_n18c<2> yMant$_n12$raw_n18c<3> yMant<0> yMant<1> yMant<2> yMant<3> -> _n216<0> _n216<1> _n216<2> _n216<3> +1 - - - - - - - - =yMant$_n12$raw_n18c<0> =yMant$_n12$raw_n18c<1> =yMant$_n12$raw_n18c<2> =yMant$_n12$raw_n18c<3> +0 - - - - - - - - =yMant<0> =yMant<1> =yMant<2> =yMant<3> +.names _n12 _n4e _n83 _n99 _nb4 _ncf _nfa _n217 +.def 0 + 0 0 1 1 - - - 1 + 0 0 1 0 1 - - 1 + 0 0 1 0 0 1 - 1 + 0 0 1 0 0 0 1 1 + 0 0 1 0 0 0 0 1 +.names _n217 z$_n12$raw_n1a7<0> z$_n12$raw_n1a7<1> z$_n12$raw_n1a7<2> z$_n12$raw_n1a7<3> z$_n12$raw_n1a7<4> z$_n12$raw_n1a7<5> z$_n12$raw_n1a7<6> z$_n12$raw_n1a7<7> z<0> z<1> z<2> z<3> z<4> z<5> z<6> z<7> -> _n218<0> _n218<1> _n218<2> _n218<3> _n218<4> _n218<5> _n218<6> _n218<7> +1 - - - - - - - - - - - - - - - - =z$_n12$raw_n1a7<0> =z$_n12$raw_n1a7<1> =z$_n12$raw_n1a7<2> =z$_n12$raw_n1a7<3> =z$_n12$raw_n1a7<4> =z$_n12$raw_n1a7<5> =z$_n12$raw_n1a7<6> =z$_n12$raw_n1a7<7> +0 - - - - - - - - - - - - - - - - =z<0> =z<1> =z<2> =z<3> =z<4> =z<5> =z<6> =z<7> +.names lsb$raw_n1c2 lsb +0 0 +1 1 +.names scaledMant$raw_n20b<0> scaledMant<0> +- =scaledMant$raw_n20b<0> +.names scaledMant$raw_n20b<1> scaledMant<1> +- =scaledMant$raw_n20b<1> +.names scaledMant$raw_n20b<2> scaledMant<2> +- =scaledMant$raw_n20b<2> +.names _n12 _n17 _n219 +.def 0 + 1 1 1 +.names _n219 yExp$_n12$raw_n193<0> yExp$_n12$raw_n193<1> yExp$_n12$raw_n193<2> yExp$_n12$raw_n193<3> yExp<0> yExp<1> yExp<2> yExp<3> -> _n21a<0> _n21a<1> _n21a<2> _n21a<3> +1 - - - - - - - - =yExp$_n12$raw_n193<0> =yExp$_n12$raw_n193<1> =yExp$_n12$raw_n193<2> =yExp$_n12$raw_n193<3> +0 - - - - - - - - =yExp<0> =yExp<1> =yExp<2> =yExp<3> +.names _n12 _n17 _n21b +.def 0 + 1 1 1 +.names _n21b ySign$_n12$raw_n191 ySign _n21c +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names _n12 _n17 _n21d +.def 0 + 1 1 1 +.names _n21d xExp$_n12$raw_n198<0> xExp$_n12$raw_n198<1> xExp$_n12$raw_n198<2> xExp$_n12$raw_n198<3> xExp<0> xExp<1> xExp<2> xExp<3> -> _n21e<0> _n21e<1> _n21e<2> _n21e<3> +1 - - - - - - - - =xExp$_n12$raw_n198<0> =xExp$_n12$raw_n198<1> =xExp$_n12$raw_n198<2> =xExp$_n12$raw_n198<3> +0 - - - - - - - - =xExp<0> =xExp<1> =xExp<2> =xExp<3> +.names preMant$raw_n1c9<0> preMant<0> +- =preMant$raw_n1c9<0> +.names preMant$raw_n1c9<1> preMant<1> +- =preMant$raw_n1c9<1> +.names preMant$raw_n1c9<2> preMant<2> +- =preMant$raw_n1c9<2> +.names preMant$raw_n1c9<3> preMant<3> +- =preMant$raw_n1c9<3> +.names preMant$raw_n1c9<4> preMant<4> +- =preMant$raw_n1c9<4> +.names msb$raw_n1c1 msb +0 0 +1 1 +.names _n12 _n17 _n21f +.def 0 + 1 1 1 +.names _n21f xSign$_n12$raw_n19d xSign _n220 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names round$raw_n1c4 round +0 0 +1 1 +.names _n12 _n17 _n4e _n83 _n221 +.def 0 + 1 1 - - 1 + 0 - 1 - 1 + 0 - 0 1 1 +.names _n221 state$_n12$raw_n182<0> state$_n12$raw_n182<1> state<0> state<1> -> _n222<0> _n222<1> +1 - - - - =state$_n12$raw_n182<0> =state$_n12$raw_n182<1> +0 - - - - =state<0> =state<1> +.names _n12 _n17 _n223 +.def 0 + 1 1 1 +.names _n223 xMant$_n12$raw_n19f<0> xMant$_n12$raw_n19f<1> xMant$_n12$raw_n19f<2> xMant$_n12$raw_n19f<3> xMant<0> xMant<1> xMant<2> xMant<3> -> _n224<0> _n224<1> _n224<2> _n224<3> +1 - - - - - - - - =xMant$_n12$raw_n19f<0> =xMant$_n12$raw_n19f<1> =xMant$_n12$raw_n19f<2> =xMant$_n12$raw_n19f<3> +0 - - - - - - - - =xMant<0> =xMant<1> =xMant<2> =xMant<3> +.names scaledExp$raw_n1f9<0> scaledExp<0> +- =scaledExp$raw_n1f9<0> +.names scaledExp$raw_n1f9<1> scaledExp<1> +- =scaledExp$raw_n1f9<1> +.names scaledExp$raw_n1f9<2> scaledExp<2> +- =scaledExp$raw_n1f9<2> +.names scaledExp$raw_n1f9<3> scaledExp<3> +- =scaledExp$raw_n1f9<3> +.names scaledExp$raw_n1f9<4> scaledExp<4> +- =scaledExp$raw_n1f9<4> +.names scaledExp$raw_n1f9<5> scaledExp<5> +- =scaledExp$raw_n1f9<5> +.names guard$raw_n1c3 guard +0 0 +1 1 +.names _n12 _n4e _n59 _n225 +.def 0 + 0 1 1 1 + 0 1 0 1 +.names _n225 expProd$_n12$raw_n1ba<0> expProd$_n12$raw_n1ba<1> expProd$_n12$raw_n1ba<2> expProd$_n12$raw_n1ba<3> expProd$_n12$raw_n1ba<4> expProd$_n12$raw_n1ba<5> expProd<0> expProd<1> expProd<2> expProd<3> expProd<4> expProd<5> -> _n226<0> _n226<1> _n226<2> _n226<3> _n226<4> _n226<5> +1 - - - - - - - - - - - - =expProd$_n12$raw_n1ba<0> =expProd$_n12$raw_n1ba<1> =expProd$_n12$raw_n1ba<2> =expProd$_n12$raw_n1ba<3> =expProd$_n12$raw_n1ba<4> =expProd$_n12$raw_n1ba<5> +0 - - - - - - - - - - - - =expProd<0> =expProd<1> =expProd<2> =expProd<3> =expProd<4> =expProd<5> +# non-blocking assignments +# latches +.r signProd$raw_nd signProd +0 0 +1 1 +.latch _n212 signProd +.r z$raw_n10<0> z<0> +.def 0 +1 1 +.r z$raw_n10<1> z<1> +.def 0 +1 1 +.r z$raw_n10<2> z<2> +.def 0 +1 1 +.r z$raw_n10<3> z<3> +.def 0 +1 1 +.r z$raw_n10<4> z<4> +.def 0 +1 1 +.r z$raw_n10<5> z<5> +.def 0 +1 1 +.r z$raw_n10<6> z<6> +.def 0 +1 1 +.r z$raw_n10<7> z<7> +.def 0 +1 1 +.latch _n218<0> z<0> +.latch _n218<1> z<1> +.latch _n218<2> z<2> +.latch _n218<3> z<3> +.latch _n218<4> z<4> +.latch _n218<5> z<5> +.latch _n218<6> z<6> +.latch _n218<7> z<7> +.r yMant$raw_nc<0> yMant<0> +.def 0 +1 1 +.r yMant$raw_nc<1> yMant<1> +.def 0 +1 1 +.r yMant$raw_nc<2> yMant<2> +.def 0 +1 1 +.r yMant$raw_nc<3> yMant<3> +.def 0 +1 1 +.latch _n216<0> yMant<0> +.latch _n216<1> yMant<1> +.latch _n216<2> yMant<2> +.latch _n216<3> yMant<3> +.r mantProd$raw_nf<0> mantProd<0> +.def 0 +1 1 +.r mantProd$raw_nf<1> mantProd<1> +.def 0 +1 1 +.r mantProd$raw_nf<2> mantProd<2> +.def 0 +1 1 +.r mantProd$raw_nf<3> mantProd<3> +.def 0 +1 1 +.r mantProd$raw_nf<4> mantProd<4> +.def 0 +1 1 +.r mantProd$raw_nf<5> mantProd<5> +.def 0 +1 1 +.r mantProd$raw_nf<6> mantProd<6> +.def 0 +1 1 +.r mantProd$raw_nf<7> mantProd<7> +.def 0 +1 1 +.latch _n214<0> mantProd<0> +.latch _n214<1> mantProd<1> +.latch _n214<2> mantProd<2> +.latch _n214<3> mantProd<3> +.latch _n214<4> mantProd<4> +.latch _n214<5> mantProd<5> +.latch _n214<6> mantProd<6> +.latch _n214<7> mantProd<7> +.r ySign$raw_na ySign +0 0 +1 1 +.latch _n21c ySign +.r yExp$raw_nb<0> yExp<0> +.def 0 +1 1 +.r yExp$raw_nb<1> yExp<1> +.def 0 +1 1 +.r yExp$raw_nb<2> yExp<2> +.def 0 +1 1 +.r yExp$raw_nb<3> yExp<3> +.def 0 +1 1 +.latch _n21a<0> yExp<0> +.latch _n21a<1> yExp<1> +.latch _n21a<2> yExp<2> +.latch _n21a<3> yExp<3> +.r xExp$raw_n8<0> xExp<0> +.def 0 +1 1 +.r xExp$raw_n8<1> xExp<1> +.def 0 +1 1 +.r xExp$raw_n8<2> xExp<2> +.def 0 +1 1 +.r xExp$raw_n8<3> xExp<3> +.def 0 +1 1 +.latch _n21e<0> xExp<0> +.latch _n21e<1> xExp<1> +.latch _n21e<2> xExp<2> +.latch _n21e<3> xExp<3> +.r xSign$raw_n7 xSign +0 0 +1 1 +.latch _n220 xSign +.r xMant$raw_n9<0> xMant<0> +.def 0 +1 1 +.r xMant$raw_n9<1> xMant<1> +.def 0 +1 1 +.r xMant$raw_n9<2> xMant<2> +.def 0 +1 1 +.r xMant$raw_n9<3> xMant<3> +.def 0 +1 1 +.latch _n224<0> xMant<0> +.latch _n224<1> xMant<1> +.latch _n224<2> xMant<2> +.latch _n224<3> xMant<3> +.r state$raw_n11<0> state<0> +.def 0 +1 1 +.r state$raw_n11<1> state<1> +.def 0 +1 1 +.latch _n222<0> state<0> +.latch _n222<1> state<1> +.r expProd$raw_ne<0> expProd<0> +.def 0 +1 1 +.r expProd$raw_ne<1> expProd<1> +.def 0 +1 1 +.r expProd$raw_ne<2> expProd<2> +.def 0 +1 1 +.r expProd$raw_ne<3> expProd<3> +.def 0 +1 1 +.r expProd$raw_ne<4> expProd<4> +.def 0 +1 1 +.r expProd$raw_ne<5> expProd<5> +.def 0 +1 1 +.latch _n226<0> expProd<0> +.latch _n226<1> expProd<1> +.latch _n226<2> expProd<2> +.latch _n226<3> expProd<3> +.latch _n226<4> expProd<4> +.latch _n226<5> expProd<5> +# quasi-continuous assignment +.end + + +.model NaN +# I/O ports +.inputs aMant<0> aMant<1> aMant<2> +.outputs NaN<0> +.inputs aExp<0> aExp<1> aExp<2> aExp<3> +.names _n229 +1 +.names _n229 _n228<0> +- =_n229 +.names _n22a +0 +.names _n22b +1 +.names _n22b _n228<1> +- =_n22b +.names _n22c +0 +.names _n22d +1 +.names _n22d _n228<2> +- =_n22d +.names _n22e +0 +.names _n22f +1 +.names _n22f _n228<3> +- =_n22f +.names _n230 +0 +# aExp == {'b1} +.names aExp<0> _n228<0> _n231<0> +.def 0 +0 1 1 +1 0 1 +.names aExp<1> _n228<1> _n231<1> +.def 0 +0 1 1 +1 0 1 +.names aExp<2> _n228<2> _n231<2> +.def 0 +0 1 1 +1 0 1 +.names aExp<3> _n228<3> _n231<3> +.def 0 +0 1 1 +1 0 1 +.names _n231<0> _n231<1> _n231<2> _n231<3> _n232 +.def 1 +0 0 0 0 0 +.names _n232 _n227 +0 1 +1 0 +.names _n234<0> +0 +.names _n234<1> +0 +.names _n234<2> +0 +# aMant != 0 +.names aMant<0> _n234<0> _n235<0> +.def 0 +0 1 1 +1 0 1 +.names aMant<1> _n234<1> _n235<1> +.def 0 +0 1 1 +1 0 1 +.names aMant<2> _n234<2> _n235<2> +.def 0 +0 1 1 +1 0 1 +.names _n235<0> _n235<1> _n235<2> _n236 +.def 1 +0 0 0 0 +.names _n236 _n233 +- =_n236 +# aExp == {'b1} && aMant != 0 +.names _n227 _n233 _n237 +.def 0 +1 1 1 +.names _n237 _n238 +- =_n237 +# NaN = 1 +.names NaN$_n237_n239$true<0> +1 +# NaN = 0 +.names NaN$_n237_n23a$false<0> +0 +# if/else (aExp == {'b1} && aMant != 0) +.names NaN$_n237_n239$true<0> NaN$_n237_n23a$false<0> _n237 NaN$_n237$raw_n23c<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names NaN$_n237$raw_n23c<0> NaN<0> +- =NaN$_n237$raw_n23c<0> +.end + + +.model Infinity +# I/O ports +.inputs aMant<0> aMant<1> aMant<2> +.outputs Infinity<0> +.inputs aExp<0> aExp<1> aExp<2> aExp<3> +.names _n242 +1 +.names _n242 _n241<0> +- =_n242 +.names _n243 +0 +.names _n244 +1 +.names _n244 _n241<1> +- =_n244 +.names _n245 +0 +.names _n246 +1 +.names _n246 _n241<2> +- =_n246 +.names _n247 +0 +.names _n248 +1 +.names _n248 _n241<3> +- =_n248 +.names _n249 +0 +# aExp == {'b1} +.names aExp<0> _n241<0> _n24a<0> +.def 0 +0 1 1 +1 0 1 +.names aExp<1> _n241<1> _n24a<1> +.def 0 +0 1 1 +1 0 1 +.names aExp<2> _n241<2> _n24a<2> +.def 0 +0 1 1 +1 0 1 +.names aExp<3> _n241<3> _n24a<3> +.def 0 +0 1 1 +1 0 1 +.names _n24a<0> _n24a<1> _n24a<2> _n24a<3> _n24b +.def 1 +0 0 0 0 0 +.names _n24b _n240 +0 1 +1 0 +.names _n24d<0> +0 +.names _n24d<1> +0 +.names _n24d<2> +0 +# aMant == 0 +.names aMant<0> _n24d<0> _n24e<0> +.def 0 +0 1 1 +1 0 1 +.names aMant<1> _n24d<1> _n24e<1> +.def 0 +0 1 1 +1 0 1 +.names aMant<2> _n24d<2> _n24e<2> +.def 0 +0 1 1 +1 0 1 +.names _n24e<0> _n24e<1> _n24e<2> _n24f +.def 1 +0 0 0 0 +.names _n24f _n24c +0 1 +1 0 +# aExp == {'b1} && aMant == 0 +.names _n240 _n24c _n250 +.def 0 +1 1 1 +.names _n250 _n251 +- =_n250 +# Infinity = 1 +.names Infinity$_n250_n252$true<0> +1 +# Infinity = 0 +.names Infinity$_n250_n253$false<0> +0 +# if/else (aExp == {'b1} && aMant == 0) +.names Infinity$_n250_n252$true<0> Infinity$_n250_n253$false<0> _n250 Infinity$_n250$raw_n255<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names Infinity$_n250$raw_n255<0> Infinity<0> +- =Infinity$_n250$raw_n255<0> +.end + + +.model Zero +# I/O ports +.inputs aMant<0> aMant<1> aMant<2> +.inputs aExp<0> aExp<1> aExp<2> aExp<3> +.outputs Zero<0> +.names _n25a<0> +0 +.names _n25a<1> +0 +.names _n25a<2> +0 +.names _n25a<3> +0 +# aExp == 0 +.names aExp<0> _n25a<0> _n25b<0> +.def 0 +0 1 1 +1 0 1 +.names aExp<1> _n25a<1> _n25b<1> +.def 0 +0 1 1 +1 0 1 +.names aExp<2> _n25a<2> _n25b<2> +.def 0 +0 1 1 +1 0 1 +.names aExp<3> _n25a<3> _n25b<3> +.def 0 +0 1 1 +1 0 1 +.names _n25b<0> _n25b<1> _n25b<2> _n25b<3> _n25c +.def 1 +0 0 0 0 0 +.names _n25c _n259 +0 1 +1 0 +.names _n25e<0> +0 +.names _n25e<1> +0 +.names _n25e<2> +0 +# aMant == 0 +.names aMant<0> _n25e<0> _n25f<0> +.def 0 +0 1 1 +1 0 1 +.names aMant<1> _n25e<1> _n25f<1> +.def 0 +0 1 1 +1 0 1 +.names aMant<2> _n25e<2> _n25f<2> +.def 0 +0 1 1 +1 0 1 +.names _n25f<0> _n25f<1> _n25f<2> _n260 +.def 1 +0 0 0 0 +.names _n260 _n25d +0 1 +1 0 +# aExp == 0 && aMant == 0 +.names _n259 _n25d _n261 +.def 0 +1 1 1 +.names _n261 _n262 +- =_n261 +# Zero = 1 +.names Zero$_n261_n263$true<0> +1 +# Zero = 0 +.names Zero$_n261_n264$false<0> +0 +# if/else (aExp == 0 && aMant == 0) +.names Zero$_n261_n263$true<0> Zero$_n261_n264$false<0> _n261 Zero$_n261$raw_n266<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names Zero$_n261$raw_n266<0> Zero<0> +- =Zero$_n261$raw_n266<0> +.end + + +.model intMult +# I/O ports +.inputs y<0> y<1> y<2> y<3> +.outputs z<0> z<1> z<2> z<3> z<4> z<5> z<6> z<7> +.inputs x<0> x<1> x<2> x<3> +# assign int0 = {y [0]} & x +.names y<0> _n26b<0> +- =y<0> +.names y<0> _n26b<1> +- =y<0> +.names y<0> _n26b<2> +- =y<0> +.names y<0> _n26b<3> +- =y<0> +# {y [0]} & x +.names _n26b<0> x<0> _n26c<0> +.def 0 +1 1 1 +.names _n26b<1> x<1> _n26c<1> +.def 0 +1 1 1 +.names _n26b<2> x<2> _n26c<2> +.def 0 +1 1 1 +.names _n26b<3> x<3> _n26c<3> +.def 0 +1 1 1 +.names _n26c<0> int0$raw_n26a<0> +- =_n26c<0> +.names _n26c<1> int0$raw_n26a<1> +- =_n26c<1> +.names _n26c<2> int0$raw_n26a<2> +- =_n26c<2> +.names _n26c<3> int0$raw_n26a<3> +- =_n26c<3> +# assign int1 = int0 + {{y [1]} & x , {'b0}} +.names _n270 +0 +.names _n270 _n26f<0> +- =_n270 +.names _n271 +0 +.names _n26f<0> _n26e<0> +- =_n26f<0> +.names y<1> _n272<0> +- =y<1> +.names y<1> _n272<1> +- =y<1> +.names y<1> _n272<2> +- =y<1> +.names y<1> _n272<3> +- =y<1> +# {y [1]} & x +.names _n272<0> x<0> _n273<0> +.def 0 +1 1 1 +.names _n272<1> x<1> _n273<1> +.def 0 +1 1 1 +.names _n272<2> x<2> _n273<2> +.def 0 +1 1 1 +.names _n272<3> x<3> _n273<3> +.def 0 +1 1 1 +.names _n273<0> _n26e<1> +- =_n273<0> +.names _n273<1> _n26e<2> +- =_n273<1> +.names _n273<2> _n26e<3> +- =_n273<2> +.names _n273<3> _n26e<4> +- =_n273<3> +# int0 + {{y [1]} & x , {'b0}} +.names _n275 +0 +.names int0<0> _n26e<0> _n275 _n274<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n277 +0 +.names int0<0> _n26e<0> _n277 _n276 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int0<1> _n26e<1> _n276 _n274<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int0<1> _n26e<1> _n276 _n278 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int0<2> _n26e<2> _n278 _n274<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int0<2> _n26e<2> _n278 _n279 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int0<3> _n26e<3> _n279 _n274<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int0<3> _n26e<3> _n279 _n27a +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n27a _n274<4> +1 1 +0 0 +.names _n274<5> +0 +.names _n274<0> int1$raw_n26d<0> +- =_n274<0> +.names _n274<1> int1$raw_n26d<1> +- =_n274<1> +.names _n274<2> int1$raw_n26d<2> +- =_n274<2> +.names _n274<3> int1$raw_n26d<3> +- =_n274<3> +.names _n274<4> int1$raw_n26d<4> +- =_n274<4> +.names _n274<5> int1$raw_n26d<5> +- =_n274<5> +# assign int2 = int1 + {{y [2]} & x , {'b0}} +.names _n27e +0 +.names _n27e _n27d<0> +- =_n27e +.names _n27f +0 +.names _n280 +0 +.names _n280 _n27d<1> +- =_n280 +.names _n281 +0 +.names _n27d<0> _n27c<0> +- =_n27d<0> +.names _n27d<1> _n27c<1> +- =_n27d<1> +.names y<2> _n282<0> +- =y<2> +.names y<2> _n282<1> +- =y<2> +.names y<2> _n282<2> +- =y<2> +.names y<2> _n282<3> +- =y<2> +# {y [2]} & x +.names _n282<0> x<0> _n283<0> +.def 0 +1 1 1 +.names _n282<1> x<1> _n283<1> +.def 0 +1 1 1 +.names _n282<2> x<2> _n283<2> +.def 0 +1 1 1 +.names _n282<3> x<3> _n283<3> +.def 0 +1 1 1 +.names _n283<0> _n27c<2> +- =_n283<0> +.names _n283<1> _n27c<3> +- =_n283<1> +.names _n283<2> _n27c<4> +- =_n283<2> +.names _n283<3> _n27c<5> +- =_n283<3> +# int1 + {{y [2]} & x , {'b0}} +.names _n285 +0 +.names int1<0> _n27c<0> _n285 _n284<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n287 +0 +.names int1<0> _n27c<0> _n287 _n286 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int1<1> _n27c<1> _n286 _n284<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int1<1> _n27c<1> _n286 _n288 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int1<2> _n27c<2> _n288 _n284<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int1<2> _n27c<2> _n288 _n289 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int1<3> _n27c<3> _n289 _n284<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int1<3> _n27c<3> _n289 _n28a +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int1<4> _n27c<4> _n28a _n284<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int1<4> _n27c<4> _n28a _n28b +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int1<5> _n27c<5> _n28b _n284<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int1<5> _n27c<5> _n28b _n28c +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n28c _n284<6> +1 1 +0 0 +.names _n284<0> int2$raw_n27b<0> +- =_n284<0> +.names _n284<1> int2$raw_n27b<1> +- =_n284<1> +.names _n284<2> int2$raw_n27b<2> +- =_n284<2> +.names _n284<3> int2$raw_n27b<3> +- =_n284<3> +.names _n284<4> int2$raw_n27b<4> +- =_n284<4> +.names _n284<5> int2$raw_n27b<5> +- =_n284<5> +.names _n284<6> int2$raw_n27b<6> +- =_n284<6> +# assign int3 = int2 + {{y [3]} & x , {'b0}} +.names _n290 +0 +.names _n290 _n28f<0> +- =_n290 +.names _n291 +0 +.names _n292 +0 +.names _n292 _n28f<1> +- =_n292 +.names _n293 +0 +.names _n294 +0 +.names _n294 _n28f<2> +- =_n294 +.names _n295 +0 +.names _n28f<0> _n28e<0> +- =_n28f<0> +.names _n28f<1> _n28e<1> +- =_n28f<1> +.names _n28f<2> _n28e<2> +- =_n28f<2> +.names y<3> _n296<0> +- =y<3> +.names y<3> _n296<1> +- =y<3> +.names y<3> _n296<2> +- =y<3> +.names y<3> _n296<3> +- =y<3> +# {y [3]} & x +.names _n296<0> x<0> _n297<0> +.def 0 +1 1 1 +.names _n296<1> x<1> _n297<1> +.def 0 +1 1 1 +.names _n296<2> x<2> _n297<2> +.def 0 +1 1 1 +.names _n296<3> x<3> _n297<3> +.def 0 +1 1 1 +.names _n297<0> _n28e<3> +- =_n297<0> +.names _n297<1> _n28e<4> +- =_n297<1> +.names _n297<2> _n28e<5> +- =_n297<2> +.names _n297<3> _n28e<6> +- =_n297<3> +# int2 + {{y [3]} & x , {'b0}} +.names _n299 +0 +.names int2<0> _n28e<0> _n299 _n298<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n29b +0 +.names int2<0> _n28e<0> _n29b _n29a +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int2<1> _n28e<1> _n29a _n298<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int2<1> _n28e<1> _n29a _n29c +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int2<2> _n28e<2> _n29c _n298<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int2<2> _n28e<2> _n29c _n29d +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int2<3> _n28e<3> _n29d _n298<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int2<3> _n28e<3> _n29d _n29e +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int2<4> _n28e<4> _n29e _n298<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int2<4> _n28e<4> _n29e _n29f +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int2<5> _n28e<5> _n29f _n298<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int2<5> _n28e<5> _n29f _n2a0 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names int2<6> _n28e<6> _n2a0 _n298<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names int2<6> _n28e<6> _n2a0 _n2a1 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n2a1 _n298<7> +1 1 +0 0 +.names _n298<0> int3$raw_n28d<0> +- =_n298<0> +.names _n298<1> int3$raw_n28d<1> +- =_n298<1> +.names _n298<2> int3$raw_n28d<2> +- =_n298<2> +.names _n298<3> int3$raw_n28d<3> +- =_n298<3> +.names _n298<4> int3$raw_n28d<4> +- =_n298<4> +.names _n298<5> int3$raw_n28d<5> +- =_n298<5> +.names _n298<6> int3$raw_n28d<6> +- =_n298<6> +.names _n298<7> int3$raw_n28d<7> +- =_n298<7> +# assign z = int3 +.names int3<0> z$raw_n2a2<0> +- =int3<0> +.names int3<1> z$raw_n2a2<1> +- =int3<1> +.names int3<2> z$raw_n2a2<2> +- =int3<2> +.names int3<3> z$raw_n2a2<3> +- =int3<3> +.names int3<4> z$raw_n2a2<4> +- =int3<4> +.names int3<5> z$raw_n2a2<5> +- =int3<5> +.names int3<6> z$raw_n2a2<6> +- =int3<6> +.names int3<7> z$raw_n2a2<7> +- =int3<7> +# conflict arbitrators +.names z$raw_n2a2<0> z<0> +- =z$raw_n2a2<0> +.names z$raw_n2a2<1> z<1> +- =z$raw_n2a2<1> +.names z$raw_n2a2<2> z<2> +- =z$raw_n2a2<2> +.names z$raw_n2a2<3> z<3> +- =z$raw_n2a2<3> +.names z$raw_n2a2<4> z<4> +- =z$raw_n2a2<4> +.names z$raw_n2a2<5> z<5> +- =z$raw_n2a2<5> +.names z$raw_n2a2<6> z<6> +- =z$raw_n2a2<6> +.names z$raw_n2a2<7> z<7> +- =z$raw_n2a2<7> +.names int0$raw_n26a<0> int0<0> +- =int0$raw_n26a<0> +.names int0$raw_n26a<1> int0<1> +- =int0$raw_n26a<1> +.names int0$raw_n26a<2> int0<2> +- =int0$raw_n26a<2> +.names int0$raw_n26a<3> int0<3> +- =int0$raw_n26a<3> +.names int1$raw_n26d<0> int1<0> +- =int1$raw_n26d<0> +.names int1$raw_n26d<1> int1<1> +- =int1$raw_n26d<1> +.names int1$raw_n26d<2> int1<2> +- =int1$raw_n26d<2> +.names int1$raw_n26d<3> int1<3> +- =int1$raw_n26d<3> +.names int1$raw_n26d<4> int1<4> +- =int1$raw_n26d<4> +.names int1$raw_n26d<5> int1<5> +- =int1$raw_n26d<5> +.names int2$raw_n27b<0> int2<0> +- =int2$raw_n27b<0> +.names int2$raw_n27b<1> int2<1> +- =int2$raw_n27b<1> +.names int2$raw_n27b<2> int2<2> +- =int2$raw_n27b<2> +.names int2$raw_n27b<3> int2<3> +- =int2$raw_n27b<3> +.names int2$raw_n27b<4> int2<4> +- =int2$raw_n27b<4> +.names int2$raw_n27b<5> int2<5> +- =int2$raw_n27b<5> +.names int2$raw_n27b<6> int2<6> +- =int2$raw_n27b<6> +.names int3$raw_n28d<0> int3<0> +- =int3$raw_n28d<0> +.names int3$raw_n28d<1> int3<1> +- =int3$raw_n28d<1> +.names int3$raw_n28d<2> int3<2> +- =int3$raw_n28d<2> +.names int3$raw_n28d<3> int3<3> +- =int3$raw_n28d<3> +.names int3$raw_n28d<4> int3<4> +- =int3$raw_n28d<4> +.names int3$raw_n28d<5> int3<5> +- =int3$raw_n28d<5> +.names int3$raw_n28d<6> int3<6> +- =int3$raw_n28d<6> +.names int3$raw_n28d<7> int3<7> +- =int3$raw_n28d<7> +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/fpmpy/fpmpy.v =================================================================== --- vis_dev/vis-2.1/examples/fpmpy/fpmpy.v (revision 11) +++ vis_dev/vis-2.1/examples/fpmpy/fpmpy.v (revision 11) @@ -0,0 +1,211 @@ +// VIS testbench for a sequential floating point multiplier. +// The purpose of this testbench is exclusively to latch the inputs, so +// that CTL properties may refer to them. +// +// Author: Fabio Somenzi +// +module fvFPMult(clock,i,j); + parameter MBITS = 3; // size of significand minus hidden bit + parameter EBITS = 4; // size of exponent + input clock; // global clock + input [MBITS+EBITS:0] i; // multiplicand + input [MBITS+EBITS:0] j; // multiplier + reg [MBITS+EBITS:0] x; // multiplicand + reg [MBITS+EBITS:0] y; // multiplier + wire [MBITS+EBITS:0] z; // output register + reg start; // starts multiplier + + IEEEfpMult #(MBITS,EBITS) FPM (clock,start,x,y,z); + + always @ (posedge clock) begin + x = i; + y = j; + end // always @ (posedge clock) + +endmodule // fvFPMult + +// Floating point multiplier. +// Not exactly IEEE 754-compliant, but largely inspired to the standard. +// +// The significand uses the hidden bit and is between 1 (included) and 2 +// (excluded). +// The exponent uses the excess (2**(n-1) - 1) representation. For single +// precision, this is excess 127. +// The smallest exponent (0) is used for the represenation of 0. Denormals +// are not supported. +// The largest exponent is used for infinities and NaNs. Infinities use +// the smallest possible significand (all zeroes). Everything else is deemed +// a NaN. No distinction is made between signalling and non-signalling NaNs. +// When the multiplier generates a NaN, it uses the all-one significand. +// One multiplication takes three clock cycles and it is not pipelined. +// +// Author: Fabio Somenzi +// +module IEEEfpMult(clock,start,x,y,z); + parameter MBITS = 3; // size of significand minus hidden bit + parameter EBITS = 4; // size of exponent + input clock; + input start; + input [MBITS+EBITS:0] x, y; + output [MBITS+EBITS:0] z; + + reg [MBITS+EBITS:0] z; + reg xSign; // unpacked x with hidden bit exposed + reg [EBITS-1:0] xExp; + reg [MBITS:0] xMant; + reg ySign; // unpacked y with hidden bit exposed + reg [EBITS-1:0] yExp; + reg [MBITS:0] yMant; + reg [1:0] state; // idle, computing, postprocessing + reg signProd; // components of the product + reg [EBITS+1:0] expProd; // before rounding and normalization + reg [2*MBITS+1:0] mantProd; + wire msb; + wire lsb; + wire guard; + wire round; + wire sticky; + wire [MBITS+1:0] preMant; + wire [EBITS+1:0] scaledExp; + wire [MBITS-1:0] scaledMant; + wire [2*MBITS+1:0] combZ; + + intMult im(xMant, yMant, combZ); + + function NaN; + input [EBITS-1:0] aExp; + input [MBITS-1:0] aMant; + begin: isNaN + if (aExp == {EBITS{1'b1}} && aMant != 0) + NaN = 1; + else + NaN = 0; + end // block: isNaN + endfunction // NaN + + function Zero; + input [EBITS-1:0] aExp; + input [MBITS-1:0] aMant; + begin: isZero + if (aExp == 0 && aMant == 0) + Zero = 1; + else + Zero = 0; + end // block: isZero + endfunction // Zero + + function Infinity; + input [EBITS-1:0] aExp; + input [MBITS-1:0] aMant; + begin: isInfinity + if (aExp == {EBITS{1'b1}} && aMant == 0) + Infinity = 1; + else + Infinity = 0; + end // block: isInfinity + endfunction // Infinity + + parameter + idle = 2'd0, + computing = 2'd1, + postprocessing = 2'd2; + + initial begin + xSign = 0; + xExp = 0; + xMant = 0; + ySign = 0; + yExp = 0; + yMant = 0; + signProd = 0; + expProd = 0; + mantProd = 0; + z = 0; + state = idle; + end + + always @ (posedge clock) begin + case (state) + idle: + begin + if (start) begin // unpack operands + xSign = x[MBITS+EBITS]; + xExp = x[MBITS+EBITS-1:MBITS]; + xMant = {1'b1,x[MBITS-1:0]}; + ySign = y[MBITS+EBITS]; + yExp = y[MBITS+EBITS-1:MBITS]; + yMant = {1'b1,y[MBITS-1:0]}; + state = computing; + end // if (start) + end // case: idle + computing: + begin + mantProd = combZ; + if (Zero(xExp,xMant) || Zero(yExp,yMant)) + expProd = 0; + else + expProd = xExp + yExp - {EBITS-1{1'b1}}; + signProd = xSign ^ ySign; + state = postprocessing; + end // case: computing + postprocessing: + begin + if (NaN(xExp,xMant) || NaN(yExp,yMant) || + Infinity(xExp,xMant) && Zero(yExp,yMant) || + Zero(xExp,xMant) && Infinity(yExp,yMant)) + z = {1'b0,{EBITS{1'b1}},{MBITS{1'b1}}}; // NaN + else if (Infinity(xExp,xMant) || Infinity(yExp,yMant)) + z = {signProd,{EBITS{1'b1}},{MBITS{1'b0}}}; // +/- Infinity + else + // check for underflow and overflow + if (scaledExp[EBITS+1] || scaledExp == 0) + z = {signProd,{MBITS+EBITS{1'b0}}}; // signed zero + else if (scaledExp >= {EBITS{1'b1}}) // overflow + z = {signProd,{EBITS{1'b1}},{MBITS{1'b0}}}; // +/- Infinity + else + z = {signProd,scaledExp[EBITS-1:0],scaledMant}; + state = idle; + end // case: postprocessing + endcase // case (state) + end // always @ (posedge clock) + + // Combinational logic for rounding and normalization + assign msb = mantProd[2*MBITS+1]; // MSB of the product + assign lsb = mantProd[MBITS+1]; // LSB of the result + assign guard = mantProd[MBITS]; // guard bit + assign round = mantProd[MBITS-1]; // round bit + assign sticky = | mantProd[MBITS-2:0]; // sticky bit + // round to nearest even + assign preMant = msb ? + mantProd[2*MBITS+1:MBITS] + + {{MBITS{1'b0}}, guard & (round | sticky | lsb), 1'b0} + : + mantProd[2*MBITS+1:MBITS] + + {{MBITS+1{1'b0}}, round & (sticky | guard)}; + // normalize + assign scaledExp = preMant[MBITS+1] ? + expProd + 1 : + expProd; + assign scaledMant = preMant[MBITS+1] ? + preMant[MBITS:1] : + preMant[MBITS-1:0]; + +endmodule // IEEEfpMult + +module intMult(x,y,z); + input [3:0] x, y; + output [7:0] z; + + wire [3:0] int0; + wire [5:0] int1; + wire [6:0] int2; + wire [7:0] int3; + + assign int0 = {4{y[0]}} & x; + assign int1 = int0 + {{4{y[1]}} & x, {1{1'b0}}}; + assign int2 = int1 + {{4{y[2]}} & x, {2{1'b0}}}; + assign int3 = int2 + {{4{y[3]}} & x, {3{1'b0}}}; + + assign z = int3; + +endmodule // intMult Index: vis_dev/vis-2.1/examples/fpmpy/result =================================================================== --- vis_dev/vis-2.1/examples/fpmpy/result (revision 11) +++ vis_dev/vis-2.1/examples/fpmpy/result (revision 11) @@ -0,0 +1,1 @@ +/bin/sh: ../../vis: not found Index: vis_dev/vis-2.1/examples/gcd/check_result =================================================================== --- vis_dev/vis-2.1/examples/gcd/check_result (revision 11) +++ vis_dev/vis-2.1/examples/gcd/check_result (revision 11) @@ -0,0 +1,2 @@ +# MC: formula passed --- (start=1 -> AX(AX(AF(busy=0)))) +# MC: formula passed --- AX(AX(AF(busy=0))) Index: vis_dev/vis-2.1/examples/gcd/check_script =================================================================== --- vis_dev/vis-2.1/examples/gcd/check_script (revision 11) +++ vis_dev/vis-2.1/examples/gcd/check_script (revision 11) @@ -0,0 +1,4 @@ +read_blif_mv gcd.mv +flatten_hierarchy +static_order -s input_and_latch gcd.ord +build_partition_mdds Index: vis_dev/vis-2.1/examples/gcd/check_script2 =================================================================== --- vis_dev/vis-2.1/examples/gcd/check_script2 (revision 11) +++ vis_dev/vis-2.1/examples/gcd/check_script2 (revision 11) @@ -0,0 +1,7 @@ +read_blif_mv gcd2.mv +flatten_hierarchy +static_order -s input_and_latch gcd2.ord +build_partition_mdds +read_fairness fair.ctl +robustness -v 1 -s 1 -E +quit -s Index: vis_dev/vis-2.1/examples/gcd/check_script21 =================================================================== --- vis_dev/vis-2.1/examples/gcd/check_script21 (revision 11) +++ vis_dev/vis-2.1/examples/gcd/check_script21 (revision 11) @@ -0,0 +1,6 @@ +read_blif_mv gcd2.mv +init_verify +compute_reach -v 1 -s 1 +dynamic_var_ordering -f sift +write_order gcd2.ord + Index: vis_dev/vis-2.1/examples/gcd/check_script3 =================================================================== --- vis_dev/vis-2.1/examples/gcd/check_script3 (revision 11) +++ vis_dev/vis-2.1/examples/gcd/check_script3 (revision 11) @@ -0,0 +1,7 @@ +read_blif_mv gcd3.mv +flatten_hierarchy +static_order -s input_and_latch gcd3.ord +build_partition_mdds +read_fairness fair.ctl +robustness -v 1 -s 1 -E +quit -s Index: vis_dev/vis-2.1/examples/gcd/check_script31 =================================================================== --- vis_dev/vis-2.1/examples/gcd/check_script31 (revision 11) +++ vis_dev/vis-2.1/examples/gcd/check_script31 (revision 11) @@ -0,0 +1,6 @@ +read_blif_mv gcd3.mv +init_verify +compute_reach -v 1 -s 1 +dynamic_var_ordering -f sift +write_order gcd3.ord + Index: vis_dev/vis-2.1/examples/gcd/fair.ctl =================================================================== --- vis_dev/vis-2.1/examples/gcd/fair.ctl (revision 11) +++ vis_dev/vis-2.1/examples/gcd/fair.ctl (revision 11) @@ -0,0 +1,1 @@ +(start=1); Index: vis_dev/vis-2.1/examples/gcd/forbiden.ctl =================================================================== --- vis_dev/vis-2.1/examples/gcd/forbiden.ctl (revision 11) +++ vis_dev/vis-2.1/examples/gcd/forbiden.ctl (revision 11) @@ -0,0 +1,1 @@ +(FALSE); Index: vis_dev/vis-2.1/examples/gcd/gcd.ctl =================================================================== --- vis_dev/vis-2.1/examples/gcd/gcd.ctl (revision 11) +++ vis_dev/vis-2.1/examples/gcd/gcd.ctl (revision 11) @@ -0,0 +1,1 @@ +(AF(AG !((g.x<0> = 0) + (g.y<0> = 0)))); Index: vis_dev/vis-2.1/examples/gcd/gcd.hint =================================================================== --- vis_dev/vis-2.1/examples/gcd/gcd.hint (revision 11) +++ vis_dev/vis-2.1/examples/gcd/gcd.hint (revision 11) @@ -0,0 +1,8 @@ +g.x[7:1] = 0 * g.y[7:1] = 0; +g.x[7:2] = 0 * g.y[7:2] = 0; +g.x[7:3] = 0 * g.y[7:3] = 0; +g.x[7:4] = 0 * g.y[7:4] = 0; +g.x[7:5] = 0 * g.y[7:5] = 0; +g.x[7:6] = 0 * g.y[7:6] = 0; +g.x[7] = 0 * g.y[7] = 0; + Index: vis_dev/vis-2.1/examples/gcd/gcd.mv =================================================================== --- vis_dev/vis-2.1/examples/gcd/gcd.mv (revision 11) +++ vis_dev/vis-2.1/examples/gcd/gcd.mv (revision 11) @@ -0,0 +1,2636 @@ +# ../../../vl2mv-2.1/vl2mv gcd.v +# version: 1.4 +# date: 13:45:54 11/18/2008 (CET) +.model testGcd +# I/O ports +.inputs y<0> y<1> y<2> y<3> y<4> y<5> y<6> y<7> +.inputs s +.inputs x<0> x<1> x<2> x<3> x<4> x<5> x<6> x<7> +.subckt gcd g start=start a<0>=a<0> a<1>=a<1> a<2>=a<2> a<3>=a<3> a<4>=a<4> a<5>=a<5> a<6>=a<6> a<7>=a<7> b<0>=b<0> b<1>=b<1> b<2>=b<2> b<3>=b<3> b<4>=b<4> b<5>=b<5> b<6>=b<6> b<7>=b<7> busy=busy o<0>=o<0> o<1>=o<1> o<2>=o<2> o<3>=o<3> o<4>=o<4> o<5>=o<5> o<6>=o<6> o<7>=o<7> +# a = 0 +.names a$raw_n0<0> +0 +.names a$raw_n0<1> +0 +.names a$raw_n0<2> +0 +.names a$raw_n0<3> +0 +.names a$raw_n0<4> +0 +.names a$raw_n0<5> +0 +.names a$raw_n0<6> +0 +.names a$raw_n0<7> +0 +# b = 0 +.names b$raw_n1<0> +0 +.names b$raw_n1<1> +0 +.names b$raw_n1<2> +0 +.names b$raw_n1<3> +0 +.names b$raw_n1<4> +0 +.names b$raw_n1<5> +0 +.names b$raw_n1<6> +0 +.names b$raw_n1<7> +0 +# start = 0 +.names start$raw_n2 +0 +# non-blocking assignments for initial +# a = x +.names x<0> a$raw_n3<0> +- =x<0> +.names x<1> a$raw_n3<1> +- =x<1> +.names x<2> a$raw_n3<2> +- =x<2> +.names x<3> a$raw_n3<3> +- =x<3> +.names x<4> a$raw_n3<4> +- =x<4> +.names x<5> a$raw_n3<5> +- =x<5> +.names x<6> a$raw_n3<6> +- =x<6> +.names x<7> a$raw_n3<7> +- =x<7> +# b = y +.names y<0> b$raw_n4<0> +- =y<0> +.names y<1> b$raw_n4<1> +- =y<1> +.names y<2> b$raw_n4<2> +- =y<2> +.names y<3> b$raw_n4<3> +- =y<3> +.names y<4> b$raw_n4<4> +- =y<4> +.names y<5> b$raw_n4<5> +- =y<5> +.names y<6> b$raw_n4<6> +- =y<6> +.names y<7> b$raw_n4<7> +- =y<7> +# start = s +.names s start$raw_n5 +- =s +# conflict arbitrators +.names _n6 +.def 0 + 1 +.names _n6 start$raw_n5 _n7 +.def 0 +1 0 0 +1 1 1 +.names _n8 +.def 0 + 1 +.names _n8 a$raw_n3<0> a$raw_n3<1> a$raw_n3<2> a$raw_n3<3> a$raw_n3<4> a$raw_n3<5> a$raw_n3<6> a$raw_n3<7> -> _n9<0> _n9<1> _n9<2> _n9<3> _n9<4> _n9<5> _n9<6> _n9<7> +.def 0 0 0 0 0 0 0 0 +1 - - - - - - - - =a$raw_n3<0> =a$raw_n3<1> =a$raw_n3<2> =a$raw_n3<3> =a$raw_n3<4> =a$raw_n3<5> =a$raw_n3<6> =a$raw_n3<7> +.names _na +.def 0 + 1 +.names _na b$raw_n4<0> b$raw_n4<1> b$raw_n4<2> b$raw_n4<3> b$raw_n4<4> b$raw_n4<5> b$raw_n4<6> b$raw_n4<7> -> _nb<0> _nb<1> _nb<2> _nb<3> _nb<4> _nb<5> _nb<6> _nb<7> +.def 0 0 0 0 0 0 0 0 +1 - - - - - - - - =b$raw_n4<0> =b$raw_n4<1> =b$raw_n4<2> =b$raw_n4<3> =b$raw_n4<4> =b$raw_n4<5> =b$raw_n4<6> =b$raw_n4<7> +# non-blocking assignments +# latches +.r a$raw_n0<0> a<0> +.def 0 +1 1 +.r a$raw_n0<1> a<1> +.def 0 +1 1 +.r a$raw_n0<2> a<2> +.def 0 +1 1 +.r a$raw_n0<3> a<3> +.def 0 +1 1 +.r a$raw_n0<4> a<4> +.def 0 +1 1 +.r a$raw_n0<5> a<5> +.def 0 +1 1 +.r a$raw_n0<6> a<6> +.def 0 +1 1 +.r a$raw_n0<7> a<7> +.def 0 +1 1 +.latch _n9<0> a<0> +.latch _n9<1> a<1> +.latch _n9<2> a<2> +.latch _n9<3> a<3> +.latch _n9<4> a<4> +.latch _n9<5> a<5> +.latch _n9<6> a<6> +.latch _n9<7> a<7> +.r start$raw_n2 start +0 0 +1 1 +.latch _n7 start +.r b$raw_n1<0> b<0> +.def 0 +1 1 +.r b$raw_n1<1> b<1> +.def 0 +1 1 +.r b$raw_n1<2> b<2> +.def 0 +1 1 +.r b$raw_n1<3> b<3> +.def 0 +1 1 +.r b$raw_n1<4> b<4> +.def 0 +1 1 +.r b$raw_n1<5> b<5> +.def 0 +1 1 +.r b$raw_n1<6> b<6> +.def 0 +1 1 +.r b$raw_n1<7> b<7> +.def 0 +1 1 +.latch _nb<0> b<0> +.latch _nb<1> b<1> +.latch _nb<2> b<2> +.latch _nb<3> b<3> +.latch _nb<4> b<4> +.latch _nb<5> b<5> +.latch _nb<6> b<6> +.latch _nb<7> b<7> +# quasi-continuous assignment +.end + + +.model gcd +# I/O ports +.outputs o<0> o<1> o<2> o<3> o<4> o<5> o<6> o<7> +.outputs busy +.inputs a<0> a<1> a<2> a<3> a<4> a<5> a<6> a<7> +.inputs start +.inputs b<0> b<1> b<2> b<3> b<4> b<5> b<6> b<7> +# assign xy_lsb [1] = select (x ,lsb ) +.subckt select _ne select<0>=_nd<0> z<0>=x<0> z<1>=x<1> z<2>=x<2> z<3>=x<3> z<4>=x<4> z<5>=x<5> z<6>=x<6> z<7>=x<7> lsb<0>=lsb<0> lsb<1>=lsb<1> lsb<2>=lsb<2> +.names _nd<0> xy_lsb$raw_nc<1> +- =_nd<0> +# assign xy_lsb [0] = select (y ,lsb ) +.subckt select _n11 select<0>=_n10<0> z<0>=y<0> z<1>=y<1> z<2>=y<2> z<3>=y<3> z<4>=y<4> z<5>=y<5> z<6>=y<6> z<7>=y<7> lsb<0>=lsb<0> lsb<1>=lsb<1> lsb<2>=lsb<2> +.names _n10<0> xy_lsb$raw_nf<0> +- =_n10<0> +# assign diff = x < y ? y - x : x - y +# x < y +.names _n15 +0 +.names x<0> y<0> _n15 _n14<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n17 +0 +.names x<0> y<0> _n17 _n16 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _n16 _n14<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _n16 _n18 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _n18 _n14<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _n18 _n19 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _n19 _n14<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _n19 _n1a +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _n1a _n14<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _n1a _n1b +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _n1b _n14<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _n1b _n1c +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _n1c _n14<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _n1c _n1d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _n1d _n14<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<7> y<7> _n1d _n1e +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n14<0> _n14<1> _n14<2> _n14<3> _n14<4> _n14<5> _n14<6> _n14<7> _n1f +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n1e _n1f _n13 +.def 0 +1 1 1 +# y - x +.names _n21 +0 +.names y<0> x<0> _n21 _n20<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n23 +0 +.names y<0> x<0> _n23 _n22 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<1> x<1> _n22 _n20<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<1> x<1> _n22 _n24 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<2> x<2> _n24 _n20<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<2> x<2> _n24 _n25 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<3> x<3> _n25 _n20<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<3> x<3> _n25 _n26 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<4> x<4> _n26 _n20<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<4> x<4> _n26 _n27 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<5> x<5> _n27 _n20<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<5> x<5> _n27 _n28 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<6> x<6> _n28 _n20<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<6> x<6> _n28 _n29 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<7> x<7> _n29 _n20<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# x - y +.names _n2b +0 +.names x<0> y<0> _n2b _n2a<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n2d +0 +.names x<0> y<0> _n2d _n2c +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _n2c _n2a<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _n2c _n2e +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _n2e _n2a<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _n2e _n2f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _n2f _n2a<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _n2f _n30 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _n30 _n2a<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _n30 _n31 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _n31 _n2a<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _n31 _n32 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _n32 _n2a<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _n32 _n33 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _n33 _n2a<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# x < y ? y - x : x - y +.names _n20<0> _n2a<0> _n13 _n34<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<1> _n2a<1> _n13 _n34<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<2> _n2a<2> _n13 _n34<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<3> _n2a<3> _n13 _n34<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<4> _n2a<4> _n13 _n34<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<5> _n2a<5> _n13 _n34<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<6> _n2a<6> _n13 _n34<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<7> _n2a<7> _n13 _n34<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n34<0> diff$raw_n12<0> +- =_n34<0> +.names _n34<1> diff$raw_n12<1> +- =_n34<1> +.names _n34<2> diff$raw_n12<2> +- =_n34<2> +.names _n34<3> diff$raw_n12<3> +- =_n34<3> +.names _n34<4> diff$raw_n12<4> +- =_n34<4> +.names _n34<5> diff$raw_n12<5> +- =_n34<5> +.names _n34<6> diff$raw_n12<6> +- =_n34<6> +.names _n34<7> diff$raw_n12<7> +- =_n34<7> +# assign done = ((x == y ) | (x == 0) | (y == 0)) & busy +# x == y +.names x<0> y<0> _n3f<0> +.def 0 +0 1 1 +1 0 1 +.names x<1> y<1> _n3f<1> +.def 0 +0 1 1 +1 0 1 +.names x<2> y<2> _n3f<2> +.def 0 +0 1 1 +1 0 1 +.names x<3> y<3> _n3f<3> +.def 0 +0 1 1 +1 0 1 +.names x<4> y<4> _n3f<4> +.def 0 +0 1 1 +1 0 1 +.names x<5> y<5> _n3f<5> +.def 0 +0 1 1 +1 0 1 +.names x<6> y<6> _n3f<6> +.def 0 +0 1 1 +1 0 1 +.names x<7> y<7> _n3f<7> +.def 0 +0 1 1 +1 0 1 +.names _n3f<0> _n3f<1> _n3f<2> _n3f<3> _n3f<4> _n3f<5> _n3f<6> _n3f<7> _n40 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n40 _n3e +0 1 +1 0 +.names _n42<0> +0 +.names _n42<1> +0 +.names _n42<2> +0 +.names _n42<3> +0 +.names _n42<4> +0 +.names _n42<5> +0 +.names _n42<6> +0 +.names _n42<7> +0 +# x == 0 +.names x<0> _n42<0> _n43<0> +.def 0 +0 1 1 +1 0 1 +.names x<1> _n42<1> _n43<1> +.def 0 +0 1 1 +1 0 1 +.names x<2> _n42<2> _n43<2> +.def 0 +0 1 1 +1 0 1 +.names x<3> _n42<3> _n43<3> +.def 0 +0 1 1 +1 0 1 +.names x<4> _n42<4> _n43<4> +.def 0 +0 1 1 +1 0 1 +.names x<5> _n42<5> _n43<5> +.def 0 +0 1 1 +1 0 1 +.names x<6> _n42<6> _n43<6> +.def 0 +0 1 1 +1 0 1 +.names x<7> _n42<7> _n43<7> +.def 0 +0 1 1 +1 0 1 +.names _n43<0> _n43<1> _n43<2> _n43<3> _n43<4> _n43<5> _n43<6> _n43<7> _n44 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n44 _n41 +0 1 +1 0 +# (x == y ) | (x == 0) +.names _n3e _n41 _n45 +.def 1 +0 0 0 +.names _n47<0> +0 +.names _n47<1> +0 +.names _n47<2> +0 +.names _n47<3> +0 +.names _n47<4> +0 +.names _n47<5> +0 +.names _n47<6> +0 +.names _n47<7> +0 +# y == 0 +.names y<0> _n47<0> _n48<0> +.def 0 +0 1 1 +1 0 1 +.names y<1> _n47<1> _n48<1> +.def 0 +0 1 1 +1 0 1 +.names y<2> _n47<2> _n48<2> +.def 0 +0 1 1 +1 0 1 +.names y<3> _n47<3> _n48<3> +.def 0 +0 1 1 +1 0 1 +.names y<4> _n47<4> _n48<4> +.def 0 +0 1 1 +1 0 1 +.names y<5> _n47<5> _n48<5> +.def 0 +0 1 1 +1 0 1 +.names y<6> _n47<6> _n48<6> +.def 0 +0 1 1 +1 0 1 +.names y<7> _n47<7> _n48<7> +.def 0 +0 1 1 +1 0 1 +.names _n48<0> _n48<1> _n48<2> _n48<3> _n48<4> _n48<5> _n48<6> _n48<7> _n49 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n49 _n46 +0 1 +1 0 +# (x == y ) | (x == 0) | (y == 0) +.names _n45 _n46 _n4a +.def 1 +0 0 0 +# ((x == y ) | (x == 0) | (y == 0)) & busy +.names _n4a busy _n4b +.def 0 +1 1 1 +.names _n4b done$raw_n3d +- =_n4b +# assign load = start & ~busy +.names busy _n4d +0 1 +1 0 +# start & ~busy +.names start _n4d _n4e +.def 0 +1 1 1 +.names _n4e load$raw_n4c +- =_n4e +# busy = 0 +.names busy$raw_n4f +0 +# x = 0 +.names x$raw_n50<0> +0 +.names x$raw_n50<1> +0 +.names x$raw_n50<2> +0 +.names x$raw_n50<3> +0 +.names x$raw_n50<4> +0 +.names x$raw_n50<5> +0 +.names x$raw_n50<6> +0 +.names x$raw_n50<7> +0 +# y = 0 +.names y$raw_n51<0> +0 +.names y$raw_n51<1> +0 +.names y$raw_n51<2> +0 +.names y$raw_n51<3> +0 +.names y$raw_n51<4> +0 +.names y$raw_n51<5> +0 +.names y$raw_n51<6> +0 +.names y$raw_n51<7> +0 +# o = 0 +.names o$raw_n52<0> +0 +.names o$raw_n52<1> +0 +.names o$raw_n52<2> +0 +.names o$raw_n52<3> +0 +.names o$raw_n52<4> +0 +.names o$raw_n52<5> +0 +.names o$raw_n52<6> +0 +.names o$raw_n52<7> +0 +# lsb = 0 +.names lsb$raw_n53<0> +0 +.names lsb$raw_n53<1> +0 +.names lsb$raw_n53<2> +0 +# non-blocking assignments for initial +.names load _n54 +- =load +# x = a +.names a<0> x$load_n55$true<0> +- =a<0> +.names a<1> x$load_n55$true<1> +- =a<1> +.names a<2> x$load_n55$true<2> +- =a<2> +.names a<3> x$load_n55$true<3> +- =a<3> +.names a<4> x$load_n55$true<4> +- =a<4> +.names a<5> x$load_n55$true<5> +- =a<5> +.names a<6> x$load_n55$true<6> +- =a<6> +.names a<7> x$load_n55$true<7> +- =a<7> +# y = b +.names b<0> y$load_n56$true<0> +- =b<0> +.names b<1> y$load_n56$true<1> +- =b<1> +.names b<2> y$load_n56$true<2> +- =b<2> +.names b<3> y$load_n56$true<3> +- =b<3> +.names b<4> y$load_n56$true<4> +- =b<4> +.names b<5> y$load_n56$true<5> +- =b<5> +.names b<6> y$load_n56$true<6> +- =b<6> +.names b<7> y$load_n56$true<7> +- =b<7> +# lsb = 0 +.names lsb$load_n57$true<0> +0 +.names lsb$load_n57$true<1> +0 +.names lsb$load_n57$true<2> +0 +.names done _n58 +0 1 +1 0 +# busy & ~done +.names busy _n58 _n59 +.def 0 +1 1 1 +.names _n59 _n5a +- =_n59 +.names _n5d<0> +0 +.names _n5d<1> +0 +.names xy_lsb<0> _n5d<0> _n5e<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _n5d<1> _n5e<1> +.def 0 +0 1 1 +1 0 1 +.names _n5e<0> _n5e<1> _n5f +.def 1 +0 0 0 +.names _n5f _n5c +0 1 +1 0 +.names _n5c _n5b +1 1 +0 0 +# lsb = lsb + 1 +.names _n61<0> +1 +.names _n61<1> +0 +.names _n61<2> +0 +# lsb + 1 +.names _n63 +0 +.names lsb<0> _n61<0> _n63 _n62<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n65 +0 +.names lsb<0> _n61<0> _n65 _n64 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names lsb<1> _n61<1> _n64 _n62<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names lsb<1> _n61<1> _n64 _n66 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names lsb<2> _n61<2> _n66 _n62<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n62<0> lsb$_n5b_n60$true<0> +- =_n62<0> +.names _n62<1> lsb$_n5b_n60$true<1> +- =_n62<1> +.names _n62<2> lsb$_n5b_n60$true<2> +- =_n62<2> +.names _n69<0> +1 +.names _n69<1> +0 +.names xy_lsb<0> _n69<0> _n6a<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _n69<1> _n6a<1> +.def 0 +0 1 1 +1 0 1 +.names _n6a<0> _n6a<1> _n6b +.def 1 +0 0 0 +.names _n6b _n68 +0 1 +1 0 +.names _n68 _n67 +1 1 +0 0 +# x [8 - 2 : 0] = x [8 - 1 : 1] +.names x<1> x$_n67_n6c$true<0> +- =x<1> +.names x<2> x$_n67_n6c$true<1> +- =x<2> +.names x<3> x$_n67_n6c$true<2> +- =x<3> +.names x<4> x$_n67_n6c$true<3> +- =x<4> +.names x<5> x$_n67_n6c$true<4> +- =x<5> +.names x<6> x$_n67_n6c$true<5> +- =x<6> +.names x<7> x$_n67_n6c$true<6> +- =x<7> +.names x<7> x$_n67_n6c$true<7> +- =x<7> +# x [8 - 1] = 0 +.names x$_n67_n6d$true<7> +0 +.names x$_n67_n6c$true<0> x$_n67_n6d$true<0> +- =x$_n67_n6c$true<0> +.names x$_n67_n6c$true<1> x$_n67_n6d$true<1> +- =x$_n67_n6c$true<1> +.names x$_n67_n6c$true<2> x$_n67_n6d$true<2> +- =x$_n67_n6c$true<2> +.names x$_n67_n6c$true<3> x$_n67_n6d$true<3> +- =x$_n67_n6c$true<3> +.names x$_n67_n6c$true<4> x$_n67_n6d$true<4> +- =x$_n67_n6c$true<4> +.names x$_n67_n6c$true<5> x$_n67_n6d$true<5> +- =x$_n67_n6c$true<5> +.names x$_n67_n6c$true<6> x$_n67_n6d$true<6> +- =x$_n67_n6c$true<6> +.names _n70<0> +0 +.names _n70<1> +1 +.names xy_lsb<0> _n70<0> _n71<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _n70<1> _n71<1> +.def 0 +0 1 1 +1 0 1 +.names _n71<0> _n71<1> _n72 +.def 1 +0 0 0 +.names _n72 _n6f +0 1 +1 0 +.names _n6f _n6e +1 1 +0 0 +# y [8 - 2 : 0] = y [8 - 1 : 1] +.names y<1> y$_n6e_n73$true<0> +- =y<1> +.names y<2> y$_n6e_n73$true<1> +- =y<2> +.names y<3> y$_n6e_n73$true<2> +- =y<3> +.names y<4> y$_n6e_n73$true<3> +- =y<4> +.names y<5> y$_n6e_n73$true<4> +- =y<5> +.names y<6> y$_n6e_n73$true<5> +- =y<6> +.names y<7> y$_n6e_n73$true<6> +- =y<7> +.names y<7> y$_n6e_n73$true<7> +- =y<7> +# y [8 - 1] = 0 +.names y$_n6e_n74$true<7> +0 +.names y$_n6e_n73$true<0> y$_n6e_n74$true<0> +- =y$_n6e_n73$true<0> +.names y$_n6e_n73$true<1> y$_n6e_n74$true<1> +- =y$_n6e_n73$true<1> +.names y$_n6e_n73$true<2> y$_n6e_n74$true<2> +- =y$_n6e_n73$true<2> +.names y$_n6e_n73$true<3> y$_n6e_n74$true<3> +- =y$_n6e_n73$true<3> +.names y$_n6e_n73$true<4> y$_n6e_n74$true<4> +- =y$_n6e_n73$true<4> +.names y$_n6e_n73$true<5> y$_n6e_n74$true<5> +- =y$_n6e_n73$true<5> +.names y$_n6e_n73$true<6> y$_n6e_n74$true<6> +- =y$_n6e_n73$true<6> +.names _n77<0> +1 +.names _n77<1> +1 +.names xy_lsb<0> _n77<0> _n78<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _n77<1> _n78<1> +.def 0 +0 1 1 +1 0 1 +.names _n78<0> _n78<1> _n79 +.def 1 +0 0 0 +.names _n79 _n76 +0 1 +1 0 +.names _n76 _n75 +1 1 +0 0 +# x < y +.names _n7c +0 +.names x<0> y<0> _n7c _n7b<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n7e +0 +.names x<0> y<0> _n7e _n7d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _n7d _n7b<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _n7d _n7f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _n7f _n7b<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _n7f _n80 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _n80 _n7b<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _n80 _n81 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _n81 _n7b<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _n81 _n82 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _n82 _n7b<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _n82 _n83 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _n83 _n7b<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _n83 _n84 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _n84 _n7b<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<7> y<7> _n84 _n85 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n7b<0> _n7b<1> _n7b<2> _n7b<3> _n7b<4> _n7b<5> _n7b<6> _n7b<7> _n86 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n85 _n86 _n7a +.def 0 +1 1 1 +.names _n7a _n87 +- =_n7a +# y [8 - 2 : 0] = diff [8 - 1 : 1] +.names diff<1> y$_n7a_n88$true<0> +- =diff<1> +.names diff<2> y$_n7a_n88$true<1> +- =diff<2> +.names diff<3> y$_n7a_n88$true<2> +- =diff<3> +.names diff<4> y$_n7a_n88$true<3> +- =diff<4> +.names diff<5> y$_n7a_n88$true<4> +- =diff<5> +.names diff<6> y$_n7a_n88$true<5> +- =diff<6> +.names diff<7> y$_n7a_n88$true<6> +- =diff<7> +.names y<7> y$_n7a_n88$true<7> +- =y<7> +# y [8 - 1] = 0 +.names y$_n7a_n89$true<7> +0 +.names y$_n7a_n88$true<0> y$_n7a_n89$true<0> +- =y$_n7a_n88$true<0> +.names y$_n7a_n88$true<1> y$_n7a_n89$true<1> +- =y$_n7a_n88$true<1> +.names y$_n7a_n88$true<2> y$_n7a_n89$true<2> +- =y$_n7a_n88$true<2> +.names y$_n7a_n88$true<3> y$_n7a_n89$true<3> +- =y$_n7a_n88$true<3> +.names y$_n7a_n88$true<4> y$_n7a_n89$true<4> +- =y$_n7a_n88$true<4> +.names y$_n7a_n88$true<5> y$_n7a_n89$true<5> +- =y$_n7a_n88$true<5> +.names y$_n7a_n88$true<6> y$_n7a_n89$true<6> +- =y$_n7a_n88$true<6> +# x [8 - 2 : 0] = diff [8 - 1 : 1] +.names diff<1> x$_n7a_n8a$false<0> +- =diff<1> +.names diff<2> x$_n7a_n8a$false<1> +- =diff<2> +.names diff<3> x$_n7a_n8a$false<2> +- =diff<3> +.names diff<4> x$_n7a_n8a$false<3> +- =diff<4> +.names diff<5> x$_n7a_n8a$false<4> +- =diff<5> +.names diff<6> x$_n7a_n8a$false<5> +- =diff<6> +.names diff<7> x$_n7a_n8a$false<6> +- =diff<7> +.names x<7> x$_n7a_n8a$false<7> +- =x<7> +# x [8 - 1] = 0 +.names x$_n7a_n8b$false<7> +0 +.names x$_n7a_n8a$false<0> x$_n7a_n8b$false<0> +- =x$_n7a_n8a$false<0> +.names x$_n7a_n8a$false<1> x$_n7a_n8b$false<1> +- =x$_n7a_n8a$false<1> +.names x$_n7a_n8a$false<2> x$_n7a_n8b$false<2> +- =x$_n7a_n8a$false<2> +.names x$_n7a_n8a$false<3> x$_n7a_n8b$false<3> +- =x$_n7a_n8a$false<3> +.names x$_n7a_n8a$false<4> x$_n7a_n8b$false<4> +- =x$_n7a_n8a$false<4> +.names x$_n7a_n8a$false<5> x$_n7a_n8b$false<5> +- =x$_n7a_n8a$false<5> +.names x$_n7a_n8a$false<6> x$_n7a_n8b$false<6> +- =x$_n7a_n8a$false<6> +# if/else (x < y ) +.names y$_n7a_n89$true<0> y<0> _n7a y$_n7a$raw_n8e<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a_n89$true<1> y<1> _n7a y$_n7a$raw_n8e<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a_n89$true<2> y<2> _n7a y$_n7a$raw_n8e<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a_n89$true<3> y<3> _n7a y$_n7a$raw_n8e<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a_n89$true<4> y<4> _n7a y$_n7a$raw_n8e<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a_n89$true<5> y<5> _n7a y$_n7a$raw_n8e<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a_n89$true<6> y<6> _n7a y$_n7a$raw_n8e<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a_n89$true<7> y<7> _n7a y$_n7a$raw_n8e<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<0> x$_n7a_n8b$false<0> _n7a x$_n7a$raw_n97<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> x$_n7a_n8b$false<1> _n7a x$_n7a$raw_n97<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> x$_n7a_n8b$false<2> _n7a x$_n7a$raw_n97<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> x$_n7a_n8b$false<3> _n7a x$_n7a$raw_n97<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> x$_n7a_n8b$false<4> _n7a x$_n7a$raw_n97<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> x$_n7a_n8b$false<5> _n7a x$_n7a$raw_n97<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> x$_n7a_n8b$false<6> _n7a x$_n7a$raw_n97<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> x$_n7a_n8b$false<7> _n7a x$_n7a$raw_n97<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# case (xy_lsb ) +.names y$_n7a$raw_n8e<0> y<0> _n75 y$_n75$raw_na4<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a$raw_n8e<1> y<1> _n75 y$_n75$raw_na4<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a$raw_n8e<2> y<2> _n75 y$_n75$raw_na4<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a$raw_n8e<3> y<3> _n75 y$_n75$raw_na4<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a$raw_n8e<4> y<4> _n75 y$_n75$raw_na4<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a$raw_n8e<5> y<5> _n75 y$_n75$raw_na4<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a$raw_n8e<6> y<6> _n75 y$_n75$raw_na4<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7a$raw_n8e<7> y<7> _n75 y$_n75$raw_na4<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n7a$raw_n97<0> x<0> _n75 x$_n75$raw_nad<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n7a$raw_n97<1> x<1> _n75 x$_n75$raw_nad<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n7a$raw_n97<2> x<2> _n75 x$_n75$raw_nad<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n7a$raw_n97<3> x<3> _n75 x$_n75$raw_nad<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n7a$raw_n97<4> x<4> _n75 x$_n75$raw_nad<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n7a$raw_n97<5> x<5> _n75 x$_n75$raw_nad<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n7a$raw_n97<6> x<6> _n75 x$_n75$raw_nad<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n7a$raw_n97<7> x<7> _n75 x$_n75$raw_nad<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n6e_n74$true<0> y$_n75$raw_na4<0> _n6e y$_n6e$raw_nb6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n6e_n74$true<1> y$_n75$raw_na4<1> _n6e y$_n6e$raw_nb6<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n6e_n74$true<2> y$_n75$raw_na4<2> _n6e y$_n6e$raw_nb6<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n6e_n74$true<3> y$_n75$raw_na4<3> _n6e y$_n6e$raw_nb6<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n6e_n74$true<4> y$_n75$raw_na4<4> _n6e y$_n6e$raw_nb6<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n6e_n74$true<5> y$_n75$raw_na4<5> _n6e y$_n6e$raw_nb6<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n6e_n74$true<6> y$_n75$raw_na4<6> _n6e y$_n6e$raw_nb6<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n6e_n74$true<7> y$_n75$raw_na4<7> _n6e y$_n6e$raw_nb6<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<0> x$_n75$raw_nad<0> _n6e x$_n6e$raw_nc2<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> x$_n75$raw_nad<1> _n6e x$_n6e$raw_nc2<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> x$_n75$raw_nad<2> _n6e x$_n6e$raw_nc2<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> x$_n75$raw_nad<3> _n6e x$_n6e$raw_nc2<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> x$_n75$raw_nad<4> _n6e x$_n6e$raw_nc2<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> x$_n75$raw_nad<5> _n6e x$_n6e$raw_nc2<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> x$_n75$raw_nad<6> _n6e x$_n6e$raw_nc2<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> x$_n75$raw_nad<7> _n6e x$_n6e$raw_nc2<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n67_n6d$true<0> x$_n6e$raw_nc2<0> _n67 x$_n67$raw_ncb<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n67_n6d$true<1> x$_n6e$raw_nc2<1> _n67 x$_n67$raw_ncb<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n67_n6d$true<2> x$_n6e$raw_nc2<2> _n67 x$_n67$raw_ncb<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n67_n6d$true<3> x$_n6e$raw_nc2<3> _n67 x$_n67$raw_ncb<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n67_n6d$true<4> x$_n6e$raw_nc2<4> _n67 x$_n67$raw_ncb<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n67_n6d$true<5> x$_n6e$raw_nc2<5> _n67 x$_n67$raw_ncb<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n67_n6d$true<6> x$_n6e$raw_nc2<6> _n67 x$_n67$raw_ncb<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n67_n6d$true<7> x$_n6e$raw_nc2<7> _n67 x$_n67$raw_ncb<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<0> y$_n6e$raw_nb6<0> _n67 y$_n67$raw_nd6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<1> y$_n6e$raw_nb6<1> _n67 y$_n67$raw_nd6<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<2> y$_n6e$raw_nb6<2> _n67 y$_n67$raw_nd6<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<3> y$_n6e$raw_nb6<3> _n67 y$_n67$raw_nd6<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<4> y$_n6e$raw_nb6<4> _n67 y$_n67$raw_nd6<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<5> y$_n6e$raw_nb6<5> _n67 y$_n67$raw_nd6<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<6> y$_n6e$raw_nb6<6> _n67 y$_n67$raw_nd6<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<7> y$_n6e$raw_nb6<7> _n67 y$_n67$raw_nd6<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n5b_n60$true<0> lsb<0> _n5b lsb$_n5b$raw_ne2<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n5b_n60$true<1> lsb<1> _n5b lsb$_n5b$raw_ne2<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n5b_n60$true<2> lsb<2> _n5b lsb$_n5b$raw_ne2<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<0> y$_n67$raw_nd6<0> _n5b y$_n5b$raw_ne6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<1> y$_n67$raw_nd6<1> _n5b y$_n5b$raw_ne6<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<2> y$_n67$raw_nd6<2> _n5b y$_n5b$raw_ne6<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<3> y$_n67$raw_nd6<3> _n5b y$_n5b$raw_ne6<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<4> y$_n67$raw_nd6<4> _n5b y$_n5b$raw_ne6<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<5> y$_n67$raw_nd6<5> _n5b y$_n5b$raw_ne6<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<6> y$_n67$raw_nd6<6> _n5b y$_n5b$raw_ne6<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<7> y$_n67$raw_nd6<7> _n5b y$_n5b$raw_ne6<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<0> x$_n67$raw_ncb<0> _n5b x$_n5b$raw_nef<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> x$_n67$raw_ncb<1> _n5b x$_n5b$raw_nef<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> x$_n67$raw_ncb<2> _n5b x$_n5b$raw_nef<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> x$_n67$raw_ncb<3> _n5b x$_n5b$raw_nef<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> x$_n67$raw_ncb<4> _n5b x$_n5b$raw_nef<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> x$_n67$raw_ncb<5> _n5b x$_n5b$raw_nef<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> x$_n67$raw_ncb<6> _n5b x$_n5b$raw_nef<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> x$_n67$raw_ncb<7> _n5b x$_n5b$raw_nef<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names done _nf8 +- =done +# o = (x < y ) ? x : y +# x < y +.names _nfc +0 +.names x<0> y<0> _nfc _nfb<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _nfe +0 +.names x<0> y<0> _nfe _nfd +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _nfd _nfb<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _nfd _nff +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _nff _nfb<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _nff _n100 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _n100 _nfb<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _n100 _n101 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _n101 _nfb<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _n101 _n102 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _n102 _nfb<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _n102 _n103 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _n103 _nfb<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _n103 _n104 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _n104 _nfb<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<7> y<7> _n104 _n105 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _nfb<0> _nfb<1> _nfb<2> _nfb<3> _nfb<4> _nfb<5> _nfb<6> _nfb<7> _n106 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n105 _n106 _nfa +.def 0 +1 1 1 +# (x < y ) ? x : y +.names x<0> y<0> _nfa _n107<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> y<1> _nfa _n107<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> y<2> _nfa _n107<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> y<3> _nfa _n107<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> y<4> _nfa _n107<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> y<5> _nfa _n107<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> y<6> _nfa _n107<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> y<7> _nfa _n107<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n107<0> o$done_nf9$true<0> +- =_n107<0> +.names _n107<1> o$done_nf9$true<1> +- =_n107<1> +.names _n107<2> o$done_nf9$true<2> +- =_n107<2> +.names _n107<3> o$done_nf9$true<3> +- =_n107<3> +.names _n107<4> o$done_nf9$true<4> +- =_n107<4> +.names _n107<5> o$done_nf9$true<5> +- =_n107<5> +.names _n107<6> o$done_nf9$true<6> +- =_n107<6> +.names _n107<7> o$done_nf9$true<7> +- =_n107<7> +# if/else (done ) +.names o$done_nf9$true<0> o<0> done o$done$raw_n112<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_nf9$true<1> o<1> done o$done$raw_n112<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_nf9$true<2> o<2> done o$done$raw_n112<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_nf9$true<3> o<3> done o$done$raw_n112<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_nf9$true<4> o<4> done o$done$raw_n112<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_nf9$true<5> o<5> done o$done$raw_n112<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_nf9$true<6> o<6> done o$done$raw_n112<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_nf9$true<7> o<7> done o$done$raw_n112<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (busy & ~done ) +.names y$_n5b$raw_ne6<0> y<0> _n59 y$_n59$raw_n121<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_ne6<1> y<1> _n59 y$_n59$raw_n121<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_ne6<2> y<2> _n59 y$_n59$raw_n121<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_ne6<3> y<3> _n59 y$_n59$raw_n121<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_ne6<4> y<4> _n59 y$_n59$raw_n121<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_ne6<5> y<5> _n59 y$_n59$raw_n121<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_ne6<6> y<6> _n59 y$_n59$raw_n121<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_ne6<7> y<7> _n59 y$_n59$raw_n121<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n5b$raw_ne2<0> lsb<0> _n59 lsb$_n59$raw_n12a<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n5b$raw_ne2<1> lsb<1> _n59 lsb$_n59$raw_n12a<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n5b$raw_ne2<2> lsb<2> _n59 lsb$_n59$raw_n12a<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nef<0> x<0> _n59 x$_n59$raw_n12e<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nef<1> x<1> _n59 x$_n59$raw_n12e<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nef<2> x<2> _n59 x$_n59$raw_n12e<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nef<3> x<3> _n59 x$_n59$raw_n12e<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nef<4> x<4> _n59 x$_n59$raw_n12e<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nef<5> x<5> _n59 x$_n59$raw_n12e<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nef<6> x<6> _n59 x$_n59$raw_n12e<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nef<7> x<7> _n59 x$_n59$raw_n12e<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<0> o$done$raw_n112<0> _n59 o$_n59$raw_n137<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<1> o$done$raw_n112<1> _n59 o$_n59$raw_n137<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<2> o$done$raw_n112<2> _n59 o$_n59$raw_n137<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<3> o$done$raw_n112<3> _n59 o$_n59$raw_n137<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<4> o$done$raw_n112<4> _n59 o$_n59$raw_n137<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<5> o$done$raw_n112<5> _n59 o$_n59$raw_n137<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<6> o$done$raw_n112<6> _n59 o$_n59$raw_n137<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<7> o$done$raw_n112<7> _n59 o$_n59$raw_n137<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (load ) +.names y$load_n56$true<0> y$_n59$raw_n121<0> load y$load$raw_n143<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<1> y$_n59$raw_n121<1> load y$load$raw_n143<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<2> y$_n59$raw_n121<2> load y$load$raw_n143<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<3> y$_n59$raw_n121<3> load y$load$raw_n143<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<4> y$_n59$raw_n121<4> load y$load$raw_n143<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<5> y$_n59$raw_n121<5> load y$load$raw_n143<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<6> y$_n59$raw_n121<6> load y$load$raw_n143<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<7> y$_n59$raw_n121<7> load y$load$raw_n143<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$load_n57$true<0> lsb$_n59$raw_n12a<0> load lsb$load$raw_n14c<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$load_n57$true<1> lsb$_n59$raw_n12a<1> load lsb$load$raw_n14c<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$load_n57$true<2> lsb$_n59$raw_n12a<2> load lsb$load$raw_n14c<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<0> x$_n59$raw_n12e<0> load x$load$raw_n150<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<1> x$_n59$raw_n12e<1> load x$load$raw_n150<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<2> x$_n59$raw_n12e<2> load x$load$raw_n150<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<3> x$_n59$raw_n12e<3> load x$load$raw_n150<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<4> x$_n59$raw_n12e<4> load x$load$raw_n150<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<5> x$_n59$raw_n12e<5> load x$load$raw_n150<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<6> x$_n59$raw_n12e<6> load x$load$raw_n150<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<7> x$_n59$raw_n12e<7> load x$load$raw_n150<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<0> o$_n59$raw_n137<0> load o$load$raw_n15d<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<1> o$_n59$raw_n137<1> load o$load$raw_n15d<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<2> o$_n59$raw_n137<2> load o$load$raw_n15d<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<3> o$_n59$raw_n137<3> load o$load$raw_n15d<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<4> o$_n59$raw_n137<4> load o$load$raw_n15d<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<5> o$_n59$raw_n137<5> load o$load$raw_n15d<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<6> o$_n59$raw_n137<6> load o$load$raw_n15d<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<7> o$_n59$raw_n137<7> load o$load$raw_n15d<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names busy _n168 +0 1 +1 0 +.names _n168 _n169 +- =_n168 +.names start _n16a +- =start +# busy = 1 +.names busy$start_n16b$true +1 +# if/else (start ) +.names busy$start_n16b$true busy start busy$start$raw_n16e +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names done _n170 +- =done +# busy = 0 +.names busy$done_n171$true +0 +# if/else (done ) +.names busy$done_n171$true busy done busy$done$raw_n174 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (~busy ) +.names busy$start$raw_n16e busy$done$raw_n174 _n168 busy$_n168$raw_n177 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names _n54 _n5a _n5b _n67 _n6e _n75 _n87 _n17b +.def 0 + 1 - - - - - - 1 + 0 1 0 0 1 - - 1 + 0 1 0 0 1 - - 1 + 0 1 0 0 0 1 1 1 + 0 1 0 0 0 1 1 1 +.names _n17b y$load$raw_n143<0> y$load$raw_n143<1> y$load$raw_n143<2> y$load$raw_n143<3> y$load$raw_n143<4> y$load$raw_n143<5> y$load$raw_n143<6> y$load$raw_n143<7> y<0> y<1> y<2> y<3> y<4> y<5> y<6> y<7> -> _n17c<0> _n17c<1> _n17c<2> _n17c<3> _n17c<4> _n17c<5> _n17c<6> _n17c<7> +1 - - - - - - - - - - - - - - - - =y$load$raw_n143<0> =y$load$raw_n143<1> =y$load$raw_n143<2> =y$load$raw_n143<3> =y$load$raw_n143<4> =y$load$raw_n143<5> =y$load$raw_n143<6> =y$load$raw_n143<7> +0 - - - - - - - - - - - - - - - - =y<0> =y<1> =y<2> =y<3> =y<4> =y<5> =y<6> =y<7> +.names _n54 _n5a _nf8 _n17d +.def 0 + 0 0 1 1 +.names _n17d o$load$raw_n15d<0> o$load$raw_n15d<1> o$load$raw_n15d<2> o$load$raw_n15d<3> o$load$raw_n15d<4> o$load$raw_n15d<5> o$load$raw_n15d<6> o$load$raw_n15d<7> o<0> o<1> o<2> o<3> o<4> o<5> o<6> o<7> -> _n17e<0> _n17e<1> _n17e<2> _n17e<3> _n17e<4> _n17e<5> _n17e<6> _n17e<7> +1 - - - - - - - - - - - - - - - - =o$load$raw_n15d<0> =o$load$raw_n15d<1> =o$load$raw_n15d<2> =o$load$raw_n15d<3> =o$load$raw_n15d<4> =o$load$raw_n15d<5> =o$load$raw_n15d<6> =o$load$raw_n15d<7> +0 - - - - - - - - - - - - - - - - =o<0> =o<1> =o<2> =o<3> =o<4> =o<5> =o<6> =o<7> +.names load$raw_n4c load +0 0 +1 1 +.names _n54 _n5a _n5b _n17f +.def 0 + 1 - - 1 + 0 1 1 1 +.names _n17f lsb$load$raw_n14c<0> lsb$load$raw_n14c<1> lsb$load$raw_n14c<2> lsb<0> lsb<1> lsb<2> -> _n180<0> _n180<1> _n180<2> +1 - - - - - - =lsb$load$raw_n14c<0> =lsb$load$raw_n14c<1> =lsb$load$raw_n14c<2> +0 - - - - - - =lsb<0> =lsb<1> =lsb<2> +.names _n169 _n16a _n170 _n181 +.def 0 + 1 1 - 1 + 0 - 1 1 +.names _n181 busy$_n168$raw_n177 busy _n182 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names xy_lsb$raw_nf<0> xy_lsb<0> +- =xy_lsb$raw_nf<0> +.names xy_lsb$raw_nc<1> xy_lsb<1> +- =xy_lsb$raw_nc<1> +.names done$raw_n3d done +0 0 +1 1 +.names diff$raw_n12<0> diff<0> +- =diff$raw_n12<0> +.names diff$raw_n12<1> diff<1> +- =diff$raw_n12<1> +.names diff$raw_n12<2> diff<2> +- =diff$raw_n12<2> +.names diff$raw_n12<3> diff<3> +- =diff$raw_n12<3> +.names diff$raw_n12<4> diff<4> +- =diff$raw_n12<4> +.names diff$raw_n12<5> diff<5> +- =diff$raw_n12<5> +.names diff$raw_n12<6> diff<6> +- =diff$raw_n12<6> +.names diff$raw_n12<7> diff<7> +- =diff$raw_n12<7> +.names _n54 _n5a _n5b _n67 _n6e _n75 _n87 _n183 +.def 0 + 1 - - - - - - 1 + 0 1 0 1 - - - 1 + 0 1 0 1 - - - 1 + 0 1 0 0 0 1 0 1 + 0 1 0 0 0 1 0 1 +.names _n183 x$load$raw_n150<0> x$load$raw_n150<1> x$load$raw_n150<2> x$load$raw_n150<3> x$load$raw_n150<4> x$load$raw_n150<5> x$load$raw_n150<6> x$load$raw_n150<7> x<0> x<1> x<2> x<3> x<4> x<5> x<6> x<7> -> _n184<0> _n184<1> _n184<2> _n184<3> _n184<4> _n184<5> _n184<6> _n184<7> +1 - - - - - - - - - - - - - - - - =x$load$raw_n150<0> =x$load$raw_n150<1> =x$load$raw_n150<2> =x$load$raw_n150<3> =x$load$raw_n150<4> =x$load$raw_n150<5> =x$load$raw_n150<6> =x$load$raw_n150<7> +0 - - - - - - - - - - - - - - - - =x<0> =x<1> =x<2> =x<3> =x<4> =x<5> =x<6> =x<7> +# non-blocking assignments +# latches +.r y$raw_n51<0> y<0> +.def 0 +1 1 +.r y$raw_n51<1> y<1> +.def 0 +1 1 +.r y$raw_n51<2> y<2> +.def 0 +1 1 +.r y$raw_n51<3> y<3> +.def 0 +1 1 +.r y$raw_n51<4> y<4> +.def 0 +1 1 +.r y$raw_n51<5> y<5> +.def 0 +1 1 +.r y$raw_n51<6> y<6> +.def 0 +1 1 +.r y$raw_n51<7> y<7> +.def 0 +1 1 +.latch _n17c<0> y<0> +.latch _n17c<1> y<1> +.latch _n17c<2> y<2> +.latch _n17c<3> y<3> +.latch _n17c<4> y<4> +.latch _n17c<5> y<5> +.latch _n17c<6> y<6> +.latch _n17c<7> y<7> +.r o$raw_n52<0> o<0> +.def 0 +1 1 +.r o$raw_n52<1> o<1> +.def 0 +1 1 +.r o$raw_n52<2> o<2> +.def 0 +1 1 +.r o$raw_n52<3> o<3> +.def 0 +1 1 +.r o$raw_n52<4> o<4> +.def 0 +1 1 +.r o$raw_n52<5> o<5> +.def 0 +1 1 +.r o$raw_n52<6> o<6> +.def 0 +1 1 +.r o$raw_n52<7> o<7> +.def 0 +1 1 +.latch _n17e<0> o<0> +.latch _n17e<1> o<1> +.latch _n17e<2> o<2> +.latch _n17e<3> o<3> +.latch _n17e<4> o<4> +.latch _n17e<5> o<5> +.latch _n17e<6> o<6> +.latch _n17e<7> o<7> +.r busy$raw_n4f busy +0 0 +1 1 +.latch _n182 busy +.r lsb$raw_n53<0> lsb<0> +.def 0 +1 1 +.r lsb$raw_n53<1> lsb<1> +.def 0 +1 1 +.r lsb$raw_n53<2> lsb<2> +.def 0 +1 1 +.latch _n180<0> lsb<0> +.latch _n180<1> lsb<1> +.latch _n180<2> lsb<2> +.r x$raw_n50<0> x<0> +.def 0 +1 1 +.r x$raw_n50<1> x<1> +.def 0 +1 1 +.r x$raw_n50<2> x<2> +.def 0 +1 1 +.r x$raw_n50<3> x<3> +.def 0 +1 1 +.r x$raw_n50<4> x<4> +.def 0 +1 1 +.r x$raw_n50<5> x<5> +.def 0 +1 1 +.r x$raw_n50<6> x<6> +.def 0 +1 1 +.r x$raw_n50<7> x<7> +.def 0 +1 1 +.latch _n184<0> x<0> +.latch _n184<1> x<1> +.latch _n184<2> x<2> +.latch _n184<3> x<3> +.latch _n184<4> x<4> +.latch _n184<5> x<5> +.latch _n184<6> x<6> +.latch _n184<7> x<7> +# quasi-continuous assignment +.end + + +.model select +# I/O ports +.inputs z<0> z<1> z<2> z<3> z<4> z<5> z<6> z<7> +.inputs lsb<0> lsb<1> lsb<2> +.outputs select<0> +.names _n186<0> +0 +.names _n186<1> +0 +.names _n186<2> +0 +# lsb == 'b000 +.names lsb<0> _n186<0> _n187<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n186<1> _n187<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n186<2> _n187<2> +.def 0 +0 1 1 +1 0 1 +.names _n187<0> _n187<1> _n187<2> _n188 +.def 1 +0 0 0 0 +.names _n188 _n185 +0 1 +1 0 +.names _n185 _n189 +- =_n185 +# select = z [0] +.names z<0> select$_n185_n18a$true<0> +- =z<0> +.names _n18c<0> +1 +.names _n18c<1> +0 +.names _n18c<2> +0 +# lsb == 'b001 +.names lsb<0> _n18c<0> _n18d<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n18c<1> _n18d<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n18c<2> _n18d<2> +.def 0 +0 1 1 +1 0 1 +.names _n18d<0> _n18d<1> _n18d<2> _n18e +.def 1 +0 0 0 0 +.names _n18e _n18b +0 1 +1 0 +.names _n18b _n18f +- =_n18b +# select = z [1] +.names z<1> select$_n18b_n190$true<0> +- =z<1> +.names _n192<0> +0 +.names _n192<1> +1 +.names _n192<2> +0 +# lsb == 'b010 +.names lsb<0> _n192<0> _n193<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n192<1> _n193<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n192<2> _n193<2> +.def 0 +0 1 1 +1 0 1 +.names _n193<0> _n193<1> _n193<2> _n194 +.def 1 +0 0 0 0 +.names _n194 _n191 +0 1 +1 0 +.names _n191 _n195 +- =_n191 +# select = z [2] +.names z<2> select$_n191_n196$true<0> +- =z<2> +.names _n198<0> +1 +.names _n198<1> +1 +.names _n198<2> +0 +# lsb == 'b011 +.names lsb<0> _n198<0> _n199<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n198<1> _n199<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n198<2> _n199<2> +.def 0 +0 1 1 +1 0 1 +.names _n199<0> _n199<1> _n199<2> _n19a +.def 1 +0 0 0 0 +.names _n19a _n197 +0 1 +1 0 +.names _n197 _n19b +- =_n197 +# select = z [3] +.names z<3> select$_n197_n19c$true<0> +- =z<3> +.names _n19e<0> +0 +.names _n19e<1> +0 +.names _n19e<2> +1 +# lsb == 'b100 +.names lsb<0> _n19e<0> _n19f<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n19e<1> _n19f<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n19e<2> _n19f<2> +.def 0 +0 1 1 +1 0 1 +.names _n19f<0> _n19f<1> _n19f<2> _n1a0 +.def 1 +0 0 0 0 +.names _n1a0 _n19d +0 1 +1 0 +.names _n19d _n1a1 +- =_n19d +# select = z [4] +.names z<4> select$_n19d_n1a2$true<0> +- =z<4> +.names _n1a4<0> +1 +.names _n1a4<1> +0 +.names _n1a4<2> +1 +# lsb == 'b101 +.names lsb<0> _n1a4<0> _n1a5<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1a4<1> _n1a5<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1a4<2> _n1a5<2> +.def 0 +0 1 1 +1 0 1 +.names _n1a5<0> _n1a5<1> _n1a5<2> _n1a6 +.def 1 +0 0 0 0 +.names _n1a6 _n1a3 +0 1 +1 0 +.names _n1a3 _n1a7 +- =_n1a3 +# select = z [5] +.names z<5> select$_n1a3_n1a8$true<0> +- =z<5> +.names _n1aa<0> +0 +.names _n1aa<1> +1 +.names _n1aa<2> +1 +# lsb == 'b110 +.names lsb<0> _n1aa<0> _n1ab<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1aa<1> _n1ab<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1aa<2> _n1ab<2> +.def 0 +0 1 1 +1 0 1 +.names _n1ab<0> _n1ab<1> _n1ab<2> _n1ac +.def 1 +0 0 0 0 +.names _n1ac _n1a9 +0 1 +1 0 +.names _n1a9 _n1ad +- =_n1a9 +# select = z [6] +.names z<6> select$_n1a9_n1ae$true<0> +- =z<6> +# select = z [7] +.names z<7> select$_n1a9_n1af$false<0> +- =z<7> +# if/else (lsb == 'b110) +.names select$_n1a9_n1ae$true<0> select$_n1a9_n1af$false<0> _n1a9 select$_n1a9$raw_n1b1<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b101) +.names select$_n1a3_n1a8$true<0> select$_n1a9$raw_n1b1<0> _n1a3 select$_n1a3$raw_n1b6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b100) +.names select$_n19d_n1a2$true<0> select$_n1a3$raw_n1b6<0> _n19d select$_n19d$raw_n1bb<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b011) +.names select$_n197_n19c$true<0> select$_n19d$raw_n1bb<0> _n197 select$_n197$raw_n1c0<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b010) +.names select$_n191_n196$true<0> select$_n197$raw_n1c0<0> _n191 select$_n191$raw_n1c5<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b001) +.names select$_n18b_n190$true<0> select$_n191$raw_n1c5<0> _n18b select$_n18b$raw_n1ca<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b000) +.names select$_n185_n18a$true<0> select$_n18b$raw_n1ca<0> _n185 select$_n185$raw_n1cf<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names select$_n185$raw_n1cf<0> select<0> +- =select$_n185$raw_n1cf<0> +.end + + Index: vis_dev/vis-2.1/examples/gcd/gcd.ord =================================================================== --- vis_dev/vis-2.1/examples/gcd/gcd.ord (revision 11) +++ vis_dev/vis-2.1/examples/gcd/gcd.ord (revision 11) @@ -0,0 +1,112 @@ +# vis release 1.3 (compiled 1-Jan-99 at 7:01 AM) +# network name: testGcd +# generated: Sat Jan 2 00:17:06 1999 +# +# name type mddId vals levs +y<7> primary-input 0 2 (0) +s primary-input 16 2 (1) +x<1> primary-input 14 2 (2) +x<3> primary-input 12 2 (3) +x<4> primary-input 11 2 (4) +x<5> primary-input 10 2 (5) +y<6> primary-input 1 2 (6) +y<5> primary-input 2 2 (7) +y<4> primary-input 3 2 (8) +y<3> primary-input 4 2 (9) +y<2> primary-input 5 2 (10) +y<0> primary-input 7 2 (11) +x<7> primary-input 8 2 (12) +x<2> primary-input 13 2 (13) +x<0> primary-input 15 2 (14) +o<0>$NS shadow 90 2 (19) +o<0> latch 89 2 (20) +o<1>$NS shadow 88 2 (21) +o<1> latch 87 2 (22) +o<7>$NS shadow 76 2 (23) +o<7> latch 75 2 (24) +o<6>$NS shadow 78 2 (25) +o<6> latch 77 2 (26) +o<5>$NS shadow 80 2 (27) +o<5> latch 79 2 (28) +o<4>$NS shadow 82 2 (29) +o<4> latch 81 2 (30) +o<3>$NS shadow 84 2 (31) +o<3> latch 83 2 (32) +o<2>$NS shadow 86 2 (33) +o<2> latch 85 2 (34) +b<1>$NS shadow 120 2 (37) +b<1> latch 119 2 (38) +g.x<6>$NS shadow 56 2 (43) +g.x<6> latch 55 2 (44) +g.y<6>$NS shadow 24 2 (45) +g.y<6> latch 23 2 (46) +g.x<5>$NS shadow 60 2 (47) +g.x<5> latch 59 2 (48) +g.y<5>$NS shadow 32 2 (49) +g.y<5> latch 31 2 (50) +g.lsb<1>$NS shadow 20 2 (51) +g.lsb<1> latch 19 2 (52) +g.x<4>$NS shadow 62 2 (53) +g.x<4> latch 61 2 (54) +g.y<4>$NS shadow 36 2 (55) +g.y<4> latch 35 2 (56) +g.lsb<2>$NS shadow 22 2 (57) +g.lsb<2> latch 21 2 (58) +g.y<7>$NS shadow 28 2 (59) +g.y<7> latch 27 2 (60) +a<6>$NS shadow 94 2 (61) +a<6> latch 93 2 (62) +x<6> primary-input 9 2 (63) +a<5>$NS shadow 96 2 (64) +a<5> latch 95 2 (65) +a<7> latch 91 2 (66) +a<7>$NS shadow 92 2 (67) +g.x<7> latch 57 2 (68) +g.x<7>$NS shadow 58 2 (69) +g.lsb<0>$NS shadow 18 2 (74) +g.lsb<0> latch 17 2 (75) +g.x<3>$NS shadow 64 2 (76) +g.x<3> latch 63 2 (77) +g.y<3>$NS shadow 40 2 (78) +g.y<3> latch 39 2 (79) +g.x<2>$NS shadow 66 2 (84) +g.x<2> latch 65 2 (85) +g.y<2>$NS shadow 44 2 (86) +g.y<2> latch 43 2 (87) +busy$NS shadow 72 2 (88) +busy latch 71 2 (89) +start latch 73 2 (90) +start$NS shadow 74 2 (91) +a<4>$NS shadow 98 2 (92) +a<4> latch 97 2 (93) +a<2>$NS shadow 102 2 (94) +a<2> latch 101 2 (95) +g.x<1>$NS shadow 68 2 (96) +g.x<1> latch 67 2 (97) +g.y<1>$NS shadow 48 2 (98) +g.y<1> latch 47 2 (99) +g.y<0>$NS shadow 52 2 (100) +g.y<0> latch 51 2 (101) +y<1> primary-input 6 2 (102) +a<3>$NS shadow 100 2 (103) +a<3> latch 99 2 (104) +a<1>$NS shadow 104 2 (105) +a<1> latch 103 2 (106) +g.x<0>$NS shadow 70 2 (107) +g.x<0> latch 69 2 (108) +a<0>$NS shadow 106 2 (109) +a<0> latch 105 2 (110) +b<0>$NS shadow 122 2 (111) +b<0> latch 121 2 (112) +b<2>$NS shadow 118 2 (113) +b<2> latch 117 2 (114) +b<3> latch 115 2 (115) +b<3>$NS shadow 116 2 (116) +b<4> latch 113 2 (117) +b<4>$NS shadow 114 2 (118) +b<5> latch 111 2 (119) +b<5>$NS shadow 112 2 (120) +b<6> latch 109 2 (121) +b<6>$NS shadow 110 2 (122) +b<7>$NS shadow 108 2 (123) +b<7> latch 107 2 (124) Index: vis_dev/vis-2.1/examples/gcd/gcd.v =================================================================== --- vis_dev/vis-2.1/examples/gcd/gcd.v (revision 11) +++ vis_dev/vis-2.1/examples/gcd/gcd.v (revision 11) @@ -0,0 +1,148 @@ +// Testbench for the gcd circuit. +module testGcd(clock,x,y,s); + parameter N = 8; + parameter logN = 3; + input clock; + input [N-1:0] x,y; + input s; + reg [N-1:0] a,b; + reg start; + wire busy; + wire [N-1:0] o; + + // Unit under test. + gcd #(N,logN) g(clock,start,a,b,busy,o); + + initial begin + a = 0; + b = 0; + start = 0; + end + + always @ (posedge clock) begin + a = x; + b = y; + start = s; + end // always @ (posedge clock) + +endmodule // testGcd + +// GCD circuit for unsigned N-bit numbers +// a[0], b[0], and o[0] are the least significant bits +// +// Author: Fabio Somenzi +module gcd(clock,start,a,b,busy,o); + parameter N = 8; + parameter logN = 3; + input clock; + input start; + input [N-1:0] a; + input [N-1:0] b; + output busy; + output [N-1:0] o; + + reg [logN-1:0] lsb; + reg [N-1:0] x; + reg [N-1:0] y; + wire done; + wire load; + reg busy; + reg [N-1:0] o; + + wire [1:0] xy_lsb; + wire [N-1:0] diff; + + function select; + input [N-1:0] z; + input [logN-1:0] lsb; + begin: _select + if (lsb == 3'd0) + select = z[0]; + else if (lsb == 3'd1) + select = z[1]; + else if (lsb == 3'd2) + select = z[2]; + else if (lsb == 3'd3) + select = z[3]; + else if (lsb == 3'd4) + select = z[4]; + else if (lsb == 3'd5) + select = z[5]; + else if (lsb == 3'd6) + select = z[6]; + else + select = z[7]; + end // block: _select + endfunction // select + + assign xy_lsb[1] = select(x,lsb); + assign xy_lsb[0] = select(y,lsb); + assign diff = x < y ? y - x : x - y; + assign done = ((x == y) | (x == 0) | (y == 0)) & busy; + assign load = start & ~busy; + + initial begin + busy = 0; + x = 0; + y = 0; + o = 0; + lsb = 0; + end // initial begin + + // Data path. + always @(posedge clock) begin + if (load) begin + x = a; + y = b; + lsb = 0; + end // if (load) + else if (busy & ~done) begin + case (xy_lsb) + 2'b00: + + lsb = lsb + 1; + + 2'b01: + begin + x[N-2:0] = x[N-1:1]; + x[N-1] = 0; + end + 2'b10: + begin + y[N-2:0] = y[N-1:1]; + y[N-1] = 0; + end + 2'b11: begin + if (x < y) begin + y[N-2:0] = diff[N-1:1]; + y[N-1] = 0; + end // if (x < y) + else begin + x[N-2:0] = diff[N-1:1]; + x[N-1] = 0; + end // else: !if(x < y) + end // case: 2b'11 + endcase // case (xy_lsb) + end // if (~done) + else if (done) begin + o = (x < y) ? x : y; + end // else: !if(~done) + end // always @ (posedge clock) + + + + // Controller. + always @(posedge clock) begin + if (~busy) begin + if (start) begin + busy = 1; + end // if (start) + end // if (~busy) + else begin + if (done) begin + busy = 0; + end + end // else: !if(~busy) + end // always @ (posedge clock) + +endmodule // gcd Index: vis_dev/vis-2.1/examples/gcd/gcd2.mv =================================================================== --- vis_dev/vis-2.1/examples/gcd/gcd2.mv (revision 11) +++ vis_dev/vis-2.1/examples/gcd/gcd2.mv (revision 11) @@ -0,0 +1,2710 @@ +# ../../../vl2mv-2.1/vl2mv gcd2.v +# version: 1.4 +# date: 13:49:11 11/18/2008 (CET) +.model testGcd +# I/O ports +.inputs y<0> y<1> y<2> y<3> y<4> y<5> y<6> y<7> +.inputs s +.inputs x<0> x<1> x<2> x<3> x<4> x<5> x<6> x<7> +.subckt gcd g start=start a<0>=a<0> a<1>=a<1> a<2>=a<2> a<3>=a<3> a<4>=a<4> a<5>=a<5> a<6>=a<6> a<7>=a<7> b<0>=b<0> b<1>=b<1> b<2>=b<2> b<3>=b<3> b<4>=b<4> b<5>=b<5> b<6>=b<6> b<7>=b<7> busy=busy o<0>=o<0> o<1>=o<1> o<2>=o<2> o<3>=o<3> o<4>=o<4> o<5>=o<5> o<6>=o<6> o<7>=o<7> +# a = 0 +.names a$raw_n0<0> +0 +.names a$raw_n0<1> +0 +.names a$raw_n0<2> +0 +.names a$raw_n0<3> +0 +.names a$raw_n0<4> +0 +.names a$raw_n0<5> +0 +.names a$raw_n0<6> +0 +.names a$raw_n0<7> +0 +# b = 0 +.names b$raw_n1<0> +0 +.names b$raw_n1<1> +0 +.names b$raw_n1<2> +0 +.names b$raw_n1<3> +0 +.names b$raw_n1<4> +0 +.names b$raw_n1<5> +0 +.names b$raw_n1<6> +0 +.names b$raw_n1<7> +0 +# start = 0 +.names start$raw_n2 +0 +# non-blocking assignments for initial +# a = x +.names x<0> a$raw_n3<0> +- =x<0> +.names x<1> a$raw_n3<1> +- =x<1> +.names x<2> a$raw_n3<2> +- =x<2> +.names x<3> a$raw_n3<3> +- =x<3> +.names x<4> a$raw_n3<4> +- =x<4> +.names x<5> a$raw_n3<5> +- =x<5> +.names x<6> a$raw_n3<6> +- =x<6> +.names x<7> a$raw_n3<7> +- =x<7> +# b = y +.names y<0> b$raw_n4<0> +- =y<0> +.names y<1> b$raw_n4<1> +- =y<1> +.names y<2> b$raw_n4<2> +- =y<2> +.names y<3> b$raw_n4<3> +- =y<3> +.names y<4> b$raw_n4<4> +- =y<4> +.names y<5> b$raw_n4<5> +- =y<5> +.names y<6> b$raw_n4<6> +- =y<6> +.names y<7> b$raw_n4<7> +- =y<7> +# start = s +.names s start$raw_n5 +- =s +# conflict arbitrators +.names _n6 +.def 0 + 1 +.names _n6 start$raw_n5 _n7 +.def 0 +1 0 0 +1 1 1 +.names _n8 +.def 0 + 1 +.names _n8 a$raw_n3<0> a$raw_n3<1> a$raw_n3<2> a$raw_n3<3> a$raw_n3<4> a$raw_n3<5> a$raw_n3<6> a$raw_n3<7> -> _n9<0> _n9<1> _n9<2> _n9<3> _n9<4> _n9<5> _n9<6> _n9<7> +.def 0 0 0 0 0 0 0 0 +1 - - - - - - - - =a$raw_n3<0> =a$raw_n3<1> =a$raw_n3<2> =a$raw_n3<3> =a$raw_n3<4> =a$raw_n3<5> =a$raw_n3<6> =a$raw_n3<7> +.names _na +.def 0 + 1 +.names _na b$raw_n4<0> b$raw_n4<1> b$raw_n4<2> b$raw_n4<3> b$raw_n4<4> b$raw_n4<5> b$raw_n4<6> b$raw_n4<7> -> _nb<0> _nb<1> _nb<2> _nb<3> _nb<4> _nb<5> _nb<6> _nb<7> +.def 0 0 0 0 0 0 0 0 +1 - - - - - - - - =b$raw_n4<0> =b$raw_n4<1> =b$raw_n4<2> =b$raw_n4<3> =b$raw_n4<4> =b$raw_n4<5> =b$raw_n4<6> =b$raw_n4<7> +# non-blocking assignments +# latches +.r a$raw_n0<0> a<0> +.def 0 +1 1 +.r a$raw_n0<1> a<1> +.def 0 +1 1 +.r a$raw_n0<2> a<2> +.def 0 +1 1 +.r a$raw_n0<3> a<3> +.def 0 +1 1 +.r a$raw_n0<4> a<4> +.def 0 +1 1 +.r a$raw_n0<5> a<5> +.def 0 +1 1 +.r a$raw_n0<6> a<6> +.def 0 +1 1 +.r a$raw_n0<7> a<7> +.def 0 +1 1 +.latch _n9<0> a<0> +.latch _n9<1> a<1> +.latch _n9<2> a<2> +.latch _n9<3> a<3> +.latch _n9<4> a<4> +.latch _n9<5> a<5> +.latch _n9<6> a<6> +.latch _n9<7> a<7> +.r start$raw_n2 start +0 0 +1 1 +.latch _n7 start +.r b$raw_n1<0> b<0> +.def 0 +1 1 +.r b$raw_n1<1> b<1> +.def 0 +1 1 +.r b$raw_n1<2> b<2> +.def 0 +1 1 +.r b$raw_n1<3> b<3> +.def 0 +1 1 +.r b$raw_n1<4> b<4> +.def 0 +1 1 +.r b$raw_n1<5> b<5> +.def 0 +1 1 +.r b$raw_n1<6> b<6> +.def 0 +1 1 +.r b$raw_n1<7> b<7> +.def 0 +1 1 +.latch _nb<0> b<0> +.latch _nb<1> b<1> +.latch _nb<2> b<2> +.latch _nb<3> b<3> +.latch _nb<4> b<4> +.latch _nb<5> b<5> +.latch _nb<6> b<6> +.latch _nb<7> b<7> +# quasi-continuous assignment +.end + + +.model gcd +# I/O ports +.outputs o<0> o<1> o<2> o<3> o<4> o<5> o<6> o<7> +.outputs busy +.inputs a<0> a<1> a<2> a<3> a<4> a<5> a<6> a<7> +.inputs start +.inputs b<0> b<1> b<2> b<3> b<4> b<5> b<6> b<7> +# assign xy_lsb [1] = select (x ,lsb ) +.subckt select _ne select<0>=_nd<0> z<0>=x<0> z<1>=x<1> z<2>=x<2> z<3>=x<3> z<4>=x<4> z<5>=x<5> z<6>=x<6> z<7>=x<7> lsb<0>=lsb<0> lsb<1>=lsb<1> lsb<2>=lsb<2> +.names _nd<0> xy_lsb$raw_nc<1> +- =_nd<0> +# assign xy_lsb [0] = select (y ,lsb ) +.subckt select _n11 select<0>=_n10<0> z<0>=y<0> z<1>=y<1> z<2>=y<2> z<3>=y<3> z<4>=y<4> z<5>=y<5> z<6>=y<6> z<7>=y<7> lsb<0>=lsb<0> lsb<1>=lsb<1> lsb<2>=lsb<2> +.names _n10<0> xy_lsb$raw_nf<0> +- =_n10<0> +# assign diff = x < y ? y - x : x - y +# x < y +.names _n15 +0 +.names x<0> y<0> _n15 _n14<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n17 +0 +.names x<0> y<0> _n17 _n16 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _n16 _n14<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _n16 _n18 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _n18 _n14<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _n18 _n19 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _n19 _n14<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _n19 _n1a +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _n1a _n14<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _n1a _n1b +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _n1b _n14<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _n1b _n1c +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _n1c _n14<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _n1c _n1d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _n1d _n14<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<7> y<7> _n1d _n1e +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n14<0> _n14<1> _n14<2> _n14<3> _n14<4> _n14<5> _n14<6> _n14<7> _n1f +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n1e _n1f _n13 +.def 0 +1 1 1 +# y - x +.names _n21 +0 +.names y<0> x<0> _n21 _n20<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n23 +0 +.names y<0> x<0> _n23 _n22 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<1> x<1> _n22 _n20<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<1> x<1> _n22 _n24 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<2> x<2> _n24 _n20<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<2> x<2> _n24 _n25 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<3> x<3> _n25 _n20<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<3> x<3> _n25 _n26 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<4> x<4> _n26 _n20<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<4> x<4> _n26 _n27 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<5> x<5> _n27 _n20<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<5> x<5> _n27 _n28 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<6> x<6> _n28 _n20<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<6> x<6> _n28 _n29 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<7> x<7> _n29 _n20<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# x - y +.names _n2b +0 +.names x<0> y<0> _n2b _n2a<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n2d +0 +.names x<0> y<0> _n2d _n2c +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _n2c _n2a<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _n2c _n2e +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _n2e _n2a<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _n2e _n2f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _n2f _n2a<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _n2f _n30 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _n30 _n2a<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _n30 _n31 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _n31 _n2a<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _n31 _n32 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _n32 _n2a<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _n32 _n33 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _n33 _n2a<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# x < y ? y - x : x - y +.names _n20<0> _n2a<0> _n13 _n34<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<1> _n2a<1> _n13 _n34<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<2> _n2a<2> _n13 _n34<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<3> _n2a<3> _n13 _n34<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<4> _n2a<4> _n13 _n34<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<5> _n2a<5> _n13 _n34<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<6> _n2a<6> _n13 _n34<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<7> _n2a<7> _n13 _n34<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n34<0> diff$raw_n12<0> +- =_n34<0> +.names _n34<1> diff$raw_n12<1> +- =_n34<1> +.names _n34<2> diff$raw_n12<2> +- =_n34<2> +.names _n34<3> diff$raw_n12<3> +- =_n34<3> +.names _n34<4> diff$raw_n12<4> +- =_n34<4> +.names _n34<5> diff$raw_n12<5> +- =_n34<5> +.names _n34<6> diff$raw_n12<6> +- =_n34<6> +.names _n34<7> diff$raw_n12<7> +- =_n34<7> +# assign done = ((x == y ) | (x == 0) | (y == 0)) & busy +# x == y +.names x<0> y<0> _n3f<0> +.def 0 +0 1 1 +1 0 1 +.names x<1> y<1> _n3f<1> +.def 0 +0 1 1 +1 0 1 +.names x<2> y<2> _n3f<2> +.def 0 +0 1 1 +1 0 1 +.names x<3> y<3> _n3f<3> +.def 0 +0 1 1 +1 0 1 +.names x<4> y<4> _n3f<4> +.def 0 +0 1 1 +1 0 1 +.names x<5> y<5> _n3f<5> +.def 0 +0 1 1 +1 0 1 +.names x<6> y<6> _n3f<6> +.def 0 +0 1 1 +1 0 1 +.names x<7> y<7> _n3f<7> +.def 0 +0 1 1 +1 0 1 +.names _n3f<0> _n3f<1> _n3f<2> _n3f<3> _n3f<4> _n3f<5> _n3f<6> _n3f<7> _n40 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n40 _n3e +0 1 +1 0 +.names _n42<0> +0 +.names _n42<1> +0 +.names _n42<2> +0 +.names _n42<3> +0 +.names _n42<4> +0 +.names _n42<5> +0 +.names _n42<6> +0 +.names _n42<7> +0 +# x == 0 +.names x<0> _n42<0> _n43<0> +.def 0 +0 1 1 +1 0 1 +.names x<1> _n42<1> _n43<1> +.def 0 +0 1 1 +1 0 1 +.names x<2> _n42<2> _n43<2> +.def 0 +0 1 1 +1 0 1 +.names x<3> _n42<3> _n43<3> +.def 0 +0 1 1 +1 0 1 +.names x<4> _n42<4> _n43<4> +.def 0 +0 1 1 +1 0 1 +.names x<5> _n42<5> _n43<5> +.def 0 +0 1 1 +1 0 1 +.names x<6> _n42<6> _n43<6> +.def 0 +0 1 1 +1 0 1 +.names x<7> _n42<7> _n43<7> +.def 0 +0 1 1 +1 0 1 +.names _n43<0> _n43<1> _n43<2> _n43<3> _n43<4> _n43<5> _n43<6> _n43<7> _n44 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n44 _n41 +0 1 +1 0 +# (x == y ) | (x == 0) +.names _n3e _n41 _n45 +.def 1 +0 0 0 +.names _n47<0> +0 +.names _n47<1> +0 +.names _n47<2> +0 +.names _n47<3> +0 +.names _n47<4> +0 +.names _n47<5> +0 +.names _n47<6> +0 +.names _n47<7> +0 +# y == 0 +.names y<0> _n47<0> _n48<0> +.def 0 +0 1 1 +1 0 1 +.names y<1> _n47<1> _n48<1> +.def 0 +0 1 1 +1 0 1 +.names y<2> _n47<2> _n48<2> +.def 0 +0 1 1 +1 0 1 +.names y<3> _n47<3> _n48<3> +.def 0 +0 1 1 +1 0 1 +.names y<4> _n47<4> _n48<4> +.def 0 +0 1 1 +1 0 1 +.names y<5> _n47<5> _n48<5> +.def 0 +0 1 1 +1 0 1 +.names y<6> _n47<6> _n48<6> +.def 0 +0 1 1 +1 0 1 +.names y<7> _n47<7> _n48<7> +.def 0 +0 1 1 +1 0 1 +.names _n48<0> _n48<1> _n48<2> _n48<3> _n48<4> _n48<5> _n48<6> _n48<7> _n49 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n49 _n46 +0 1 +1 0 +# (x == y ) | (x == 0) | (y == 0) +.names _n45 _n46 _n4a +.def 1 +0 0 0 +# ((x == y ) | (x == 0) | (y == 0)) & busy +.names _n4a busy _n4b +.def 0 +1 1 1 +.names _n4b done$raw_n3d +- =_n4b +# assign load = start & ~busy +.names busy _n4d +0 1 +1 0 +# start & ~busy +.names start _n4d _n4e +.def 0 +1 1 1 +.names _n4e load$raw_n4c +- =_n4e +# busy = 0 +.names busy$raw_n4f +0 +# x = 0 +.names x$raw_n50<0> +0 +.names x$raw_n50<1> +0 +.names x$raw_n50<2> +0 +.names x$raw_n50<3> +0 +.names x$raw_n50<4> +0 +.names x$raw_n50<5> +0 +.names x$raw_n50<6> +0 +.names x$raw_n50<7> +0 +# y = 0 +.names y$raw_n51<0> +0 +.names y$raw_n51<1> +0 +.names y$raw_n51<2> +0 +.names y$raw_n51<3> +0 +.names y$raw_n51<4> +0 +.names y$raw_n51<5> +0 +.names y$raw_n51<6> +0 +.names y$raw_n51<7> +0 +# o = 0 +.names o$raw_n52<0> +0 +.names o$raw_n52<1> +0 +.names o$raw_n52<2> +0 +.names o$raw_n52<3> +0 +.names o$raw_n52<4> +0 +.names o$raw_n52<5> +0 +.names o$raw_n52<6> +0 +.names o$raw_n52<7> +0 +# lsb = 0 +.names lsb$raw_n53<0> +0 +.names lsb$raw_n53<1> +0 +.names lsb$raw_n53<2> +0 +# non-blocking assignments for initial +.names load _n54 +- =load +# x = a +.names a<0> x$load_n55$true<0> +- =a<0> +.names a<1> x$load_n55$true<1> +- =a<1> +.names a<2> x$load_n55$true<2> +- =a<2> +.names a<3> x$load_n55$true<3> +- =a<3> +.names a<4> x$load_n55$true<4> +- =a<4> +.names a<5> x$load_n55$true<5> +- =a<5> +.names a<6> x$load_n55$true<6> +- =a<6> +.names a<7> x$load_n55$true<7> +- =a<7> +# y = b +.names b<0> y$load_n56$true<0> +- =b<0> +.names b<1> y$load_n56$true<1> +- =b<1> +.names b<2> y$load_n56$true<2> +- =b<2> +.names b<3> y$load_n56$true<3> +- =b<3> +.names b<4> y$load_n56$true<4> +- =b<4> +.names b<5> y$load_n56$true<5> +- =b<5> +.names b<6> y$load_n56$true<6> +- =b<6> +.names b<7> y$load_n56$true<7> +- =b<7> +# lsb = 0 +.names lsb$load_n57$true<0> +0 +.names lsb$load_n57$true<1> +0 +.names lsb$load_n57$true<2> +0 +.names done _n58 +0 1 +1 0 +# busy & ~done +.names busy _n58 _n59 +.def 0 +1 1 1 +.names _n59 _n5a +- =_n59 +.names _n5d<0> +0 +.names _n5d<1> +0 +.names xy_lsb<0> _n5d<0> _n5e<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _n5d<1> _n5e<1> +.def 0 +0 1 1 +1 0 1 +.names _n5e<0> _n5e<1> _n5f +.def 1 +0 0 0 +.names _n5f _n5c +0 1 +1 0 +.names _n5c _n5b +1 1 +0 0 +.names _n60<0> +1 +.names _n60<1> +1 +.names _n60<2> +1 +# lsb < 7 +.names _n63 +0 +.names lsb<0> _n60<0> _n63 _n62<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n65 +0 +.names lsb<0> _n60<0> _n65 _n64 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names lsb<1> _n60<1> _n64 _n62<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names lsb<1> _n60<1> _n64 _n66 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names lsb<2> _n60<2> _n66 _n62<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names lsb<2> _n60<2> _n66 _n67 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n62<0> _n62<1> _n62<2> _n68 +.def 1 +0 0 0 0 +.names _n67 _n68 _n61 +.def 0 +1 1 1 +.names _n61 _n69 +- =_n61 +# lsb = lsb + 1 +.names _n6b<0> +1 +.names _n6b<1> +0 +.names _n6b<2> +0 +# lsb + 1 +.names _n6d +0 +.names lsb<0> _n6b<0> _n6d _n6c<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n6f +0 +.names lsb<0> _n6b<0> _n6f _n6e +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names lsb<1> _n6b<1> _n6e _n6c<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names lsb<1> _n6b<1> _n6e _n70 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names lsb<2> _n6b<2> _n70 _n6c<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n6c<0> lsb$_n61_n6a$true<0> +- =_n6c<0> +.names _n6c<1> lsb$_n61_n6a$true<1> +- =_n6c<1> +.names _n6c<2> lsb$_n61_n6a$true<2> +- =_n6c<2> +# if/else (lsb < 7) +.names lsb$_n61_n6a$true<0> lsb<0> _n61 lsb$_n61$raw_n73<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n61_n6a$true<1> lsb<1> _n61 lsb$_n61$raw_n73<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n61_n6a$true<2> lsb<2> _n61 lsb$_n61$raw_n73<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n79<0> +1 +.names _n79<1> +0 +.names xy_lsb<0> _n79<0> _n7a<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _n79<1> _n7a<1> +.def 0 +0 1 1 +1 0 1 +.names _n7a<0> _n7a<1> _n7b +.def 1 +0 0 0 +.names _n7b _n78 +0 1 +1 0 +.names _n78 _n77 +1 1 +0 0 +# x [8 - 2 : 0] = x [8 - 1 : 1] +.names x<1> x$_n77_n7c$true<0> +- =x<1> +.names x<2> x$_n77_n7c$true<1> +- =x<2> +.names x<3> x$_n77_n7c$true<2> +- =x<3> +.names x<4> x$_n77_n7c$true<3> +- =x<4> +.names x<5> x$_n77_n7c$true<4> +- =x<5> +.names x<6> x$_n77_n7c$true<5> +- =x<6> +.names x<7> x$_n77_n7c$true<6> +- =x<7> +.names x<7> x$_n77_n7c$true<7> +- =x<7> +# x [8 - 1] = 0 +.names x$_n77_n7d$true<7> +0 +.names x$_n77_n7c$true<0> x$_n77_n7d$true<0> +- =x$_n77_n7c$true<0> +.names x$_n77_n7c$true<1> x$_n77_n7d$true<1> +- =x$_n77_n7c$true<1> +.names x$_n77_n7c$true<2> x$_n77_n7d$true<2> +- =x$_n77_n7c$true<2> +.names x$_n77_n7c$true<3> x$_n77_n7d$true<3> +- =x$_n77_n7c$true<3> +.names x$_n77_n7c$true<4> x$_n77_n7d$true<4> +- =x$_n77_n7c$true<4> +.names x$_n77_n7c$true<5> x$_n77_n7d$true<5> +- =x$_n77_n7c$true<5> +.names x$_n77_n7c$true<6> x$_n77_n7d$true<6> +- =x$_n77_n7c$true<6> +.names _n80<0> +0 +.names _n80<1> +1 +.names xy_lsb<0> _n80<0> _n81<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _n80<1> _n81<1> +.def 0 +0 1 1 +1 0 1 +.names _n81<0> _n81<1> _n82 +.def 1 +0 0 0 +.names _n82 _n7f +0 1 +1 0 +.names _n7f _n7e +1 1 +0 0 +# y [8 - 2 : 0] = y [8 - 1 : 1] +.names y<1> y$_n7e_n83$true<0> +- =y<1> +.names y<2> y$_n7e_n83$true<1> +- =y<2> +.names y<3> y$_n7e_n83$true<2> +- =y<3> +.names y<4> y$_n7e_n83$true<3> +- =y<4> +.names y<5> y$_n7e_n83$true<4> +- =y<5> +.names y<6> y$_n7e_n83$true<5> +- =y<6> +.names y<7> y$_n7e_n83$true<6> +- =y<7> +.names y<7> y$_n7e_n83$true<7> +- =y<7> +# y [8 - 1] = 0 +.names y$_n7e_n84$true<7> +0 +.names y$_n7e_n83$true<0> y$_n7e_n84$true<0> +- =y$_n7e_n83$true<0> +.names y$_n7e_n83$true<1> y$_n7e_n84$true<1> +- =y$_n7e_n83$true<1> +.names y$_n7e_n83$true<2> y$_n7e_n84$true<2> +- =y$_n7e_n83$true<2> +.names y$_n7e_n83$true<3> y$_n7e_n84$true<3> +- =y$_n7e_n83$true<3> +.names y$_n7e_n83$true<4> y$_n7e_n84$true<4> +- =y$_n7e_n83$true<4> +.names y$_n7e_n83$true<5> y$_n7e_n84$true<5> +- =y$_n7e_n83$true<5> +.names y$_n7e_n83$true<6> y$_n7e_n84$true<6> +- =y$_n7e_n83$true<6> +.names _n87<0> +1 +.names _n87<1> +1 +.names xy_lsb<0> _n87<0> _n88<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _n87<1> _n88<1> +.def 0 +0 1 1 +1 0 1 +.names _n88<0> _n88<1> _n89 +.def 1 +0 0 0 +.names _n89 _n86 +0 1 +1 0 +.names _n86 _n85 +1 1 +0 0 +# x < y +.names _n8c +0 +.names x<0> y<0> _n8c _n8b<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n8e +0 +.names x<0> y<0> _n8e _n8d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _n8d _n8b<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _n8d _n8f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _n8f _n8b<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _n8f _n90 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _n90 _n8b<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _n90 _n91 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _n91 _n8b<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _n91 _n92 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _n92 _n8b<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _n92 _n93 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _n93 _n8b<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _n93 _n94 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _n94 _n8b<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<7> y<7> _n94 _n95 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n8b<0> _n8b<1> _n8b<2> _n8b<3> _n8b<4> _n8b<5> _n8b<6> _n8b<7> _n96 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n95 _n96 _n8a +.def 0 +1 1 1 +.names _n8a _n97 +- =_n8a +# y [8 - 2 : 0] = diff [8 - 1 : 1] +.names diff<1> y$_n8a_n98$true<0> +- =diff<1> +.names diff<2> y$_n8a_n98$true<1> +- =diff<2> +.names diff<3> y$_n8a_n98$true<2> +- =diff<3> +.names diff<4> y$_n8a_n98$true<3> +- =diff<4> +.names diff<5> y$_n8a_n98$true<4> +- =diff<5> +.names diff<6> y$_n8a_n98$true<5> +- =diff<6> +.names diff<7> y$_n8a_n98$true<6> +- =diff<7> +.names y<7> y$_n8a_n98$true<7> +- =y<7> +# y [8 - 1] = 0 +.names y$_n8a_n99$true<7> +0 +.names y$_n8a_n98$true<0> y$_n8a_n99$true<0> +- =y$_n8a_n98$true<0> +.names y$_n8a_n98$true<1> y$_n8a_n99$true<1> +- =y$_n8a_n98$true<1> +.names y$_n8a_n98$true<2> y$_n8a_n99$true<2> +- =y$_n8a_n98$true<2> +.names y$_n8a_n98$true<3> y$_n8a_n99$true<3> +- =y$_n8a_n98$true<3> +.names y$_n8a_n98$true<4> y$_n8a_n99$true<4> +- =y$_n8a_n98$true<4> +.names y$_n8a_n98$true<5> y$_n8a_n99$true<5> +- =y$_n8a_n98$true<5> +.names y$_n8a_n98$true<6> y$_n8a_n99$true<6> +- =y$_n8a_n98$true<6> +# x [8 - 2 : 0] = diff [8 - 1 : 1] +.names diff<1> x$_n8a_n9a$false<0> +- =diff<1> +.names diff<2> x$_n8a_n9a$false<1> +- =diff<2> +.names diff<3> x$_n8a_n9a$false<2> +- =diff<3> +.names diff<4> x$_n8a_n9a$false<3> +- =diff<4> +.names diff<5> x$_n8a_n9a$false<4> +- =diff<5> +.names diff<6> x$_n8a_n9a$false<5> +- =diff<6> +.names diff<7> x$_n8a_n9a$false<6> +- =diff<7> +.names x<7> x$_n8a_n9a$false<7> +- =x<7> +# x [8 - 1] = 0 +.names x$_n8a_n9b$false<7> +0 +.names x$_n8a_n9a$false<0> x$_n8a_n9b$false<0> +- =x$_n8a_n9a$false<0> +.names x$_n8a_n9a$false<1> x$_n8a_n9b$false<1> +- =x$_n8a_n9a$false<1> +.names x$_n8a_n9a$false<2> x$_n8a_n9b$false<2> +- =x$_n8a_n9a$false<2> +.names x$_n8a_n9a$false<3> x$_n8a_n9b$false<3> +- =x$_n8a_n9a$false<3> +.names x$_n8a_n9a$false<4> x$_n8a_n9b$false<4> +- =x$_n8a_n9a$false<4> +.names x$_n8a_n9a$false<5> x$_n8a_n9b$false<5> +- =x$_n8a_n9a$false<5> +.names x$_n8a_n9a$false<6> x$_n8a_n9b$false<6> +- =x$_n8a_n9a$false<6> +# if/else (x < y ) +.names y$_n8a_n99$true<0> y<0> _n8a y$_n8a$raw_n9e<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a_n99$true<1> y<1> _n8a y$_n8a$raw_n9e<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a_n99$true<2> y<2> _n8a y$_n8a$raw_n9e<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a_n99$true<3> y<3> _n8a y$_n8a$raw_n9e<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a_n99$true<4> y<4> _n8a y$_n8a$raw_n9e<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a_n99$true<5> y<5> _n8a y$_n8a$raw_n9e<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a_n99$true<6> y<6> _n8a y$_n8a$raw_n9e<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a_n99$true<7> y<7> _n8a y$_n8a$raw_n9e<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<0> x$_n8a_n9b$false<0> _n8a x$_n8a$raw_na7<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> x$_n8a_n9b$false<1> _n8a x$_n8a$raw_na7<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> x$_n8a_n9b$false<2> _n8a x$_n8a$raw_na7<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> x$_n8a_n9b$false<3> _n8a x$_n8a$raw_na7<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> x$_n8a_n9b$false<4> _n8a x$_n8a$raw_na7<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> x$_n8a_n9b$false<5> _n8a x$_n8a$raw_na7<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> x$_n8a_n9b$false<6> _n8a x$_n8a$raw_na7<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> x$_n8a_n9b$false<7> _n8a x$_n8a$raw_na7<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# case (xy_lsb ) +.names y$_n8a$raw_n9e<0> y<0> _n85 y$_n85$raw_nb4<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a$raw_n9e<1> y<1> _n85 y$_n85$raw_nb4<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a$raw_n9e<2> y<2> _n85 y$_n85$raw_nb4<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a$raw_n9e<3> y<3> _n85 y$_n85$raw_nb4<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a$raw_n9e<4> y<4> _n85 y$_n85$raw_nb4<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a$raw_n9e<5> y<5> _n85 y$_n85$raw_nb4<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a$raw_n9e<6> y<6> _n85 y$_n85$raw_nb4<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n8a$raw_n9e<7> y<7> _n85 y$_n85$raw_nb4<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n8a$raw_na7<0> x<0> _n85 x$_n85$raw_nbd<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n8a$raw_na7<1> x<1> _n85 x$_n85$raw_nbd<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n8a$raw_na7<2> x<2> _n85 x$_n85$raw_nbd<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n8a$raw_na7<3> x<3> _n85 x$_n85$raw_nbd<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n8a$raw_na7<4> x<4> _n85 x$_n85$raw_nbd<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n8a$raw_na7<5> x<5> _n85 x$_n85$raw_nbd<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n8a$raw_na7<6> x<6> _n85 x$_n85$raw_nbd<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n8a$raw_na7<7> x<7> _n85 x$_n85$raw_nbd<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7e_n84$true<0> y$_n85$raw_nb4<0> _n7e y$_n7e$raw_nc6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7e_n84$true<1> y$_n85$raw_nb4<1> _n7e y$_n7e$raw_nc6<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7e_n84$true<2> y$_n85$raw_nb4<2> _n7e y$_n7e$raw_nc6<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7e_n84$true<3> y$_n85$raw_nb4<3> _n7e y$_n7e$raw_nc6<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7e_n84$true<4> y$_n85$raw_nb4<4> _n7e y$_n7e$raw_nc6<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7e_n84$true<5> y$_n85$raw_nb4<5> _n7e y$_n7e$raw_nc6<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7e_n84$true<6> y$_n85$raw_nb4<6> _n7e y$_n7e$raw_nc6<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n7e_n84$true<7> y$_n85$raw_nb4<7> _n7e y$_n7e$raw_nc6<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<0> x$_n85$raw_nbd<0> _n7e x$_n7e$raw_nd2<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> x$_n85$raw_nbd<1> _n7e x$_n7e$raw_nd2<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> x$_n85$raw_nbd<2> _n7e x$_n7e$raw_nd2<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> x$_n85$raw_nbd<3> _n7e x$_n7e$raw_nd2<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> x$_n85$raw_nbd<4> _n7e x$_n7e$raw_nd2<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> x$_n85$raw_nbd<5> _n7e x$_n7e$raw_nd2<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> x$_n85$raw_nbd<6> _n7e x$_n7e$raw_nd2<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> x$_n85$raw_nbd<7> _n7e x$_n7e$raw_nd2<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n77_n7d$true<0> x$_n7e$raw_nd2<0> _n77 x$_n77$raw_ndb<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n77_n7d$true<1> x$_n7e$raw_nd2<1> _n77 x$_n77$raw_ndb<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n77_n7d$true<2> x$_n7e$raw_nd2<2> _n77 x$_n77$raw_ndb<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n77_n7d$true<3> x$_n7e$raw_nd2<3> _n77 x$_n77$raw_ndb<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n77_n7d$true<4> x$_n7e$raw_nd2<4> _n77 x$_n77$raw_ndb<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n77_n7d$true<5> x$_n7e$raw_nd2<5> _n77 x$_n77$raw_ndb<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n77_n7d$true<6> x$_n7e$raw_nd2<6> _n77 x$_n77$raw_ndb<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n77_n7d$true<7> x$_n7e$raw_nd2<7> _n77 x$_n77$raw_ndb<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<0> y$_n7e$raw_nc6<0> _n77 y$_n77$raw_ne6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<1> y$_n7e$raw_nc6<1> _n77 y$_n77$raw_ne6<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<2> y$_n7e$raw_nc6<2> _n77 y$_n77$raw_ne6<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<3> y$_n7e$raw_nc6<3> _n77 y$_n77$raw_ne6<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<4> y$_n7e$raw_nc6<4> _n77 y$_n77$raw_ne6<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<5> y$_n7e$raw_nc6<5> _n77 y$_n77$raw_ne6<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<6> y$_n7e$raw_nc6<6> _n77 y$_n77$raw_ne6<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<7> y$_n7e$raw_nc6<7> _n77 y$_n77$raw_ne6<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n61$raw_n73<0> lsb<0> _n5b lsb$_n5b$raw_nf2<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n61$raw_n73<1> lsb<1> _n5b lsb$_n5b$raw_nf2<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n61$raw_n73<2> lsb<2> _n5b lsb$_n5b$raw_nf2<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<0> y$_n77$raw_ne6<0> _n5b y$_n5b$raw_nf6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<1> y$_n77$raw_ne6<1> _n5b y$_n5b$raw_nf6<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<2> y$_n77$raw_ne6<2> _n5b y$_n5b$raw_nf6<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<3> y$_n77$raw_ne6<3> _n5b y$_n5b$raw_nf6<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<4> y$_n77$raw_ne6<4> _n5b y$_n5b$raw_nf6<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<5> y$_n77$raw_ne6<5> _n5b y$_n5b$raw_nf6<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<6> y$_n77$raw_ne6<6> _n5b y$_n5b$raw_nf6<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<7> y$_n77$raw_ne6<7> _n5b y$_n5b$raw_nf6<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<0> x$_n77$raw_ndb<0> _n5b x$_n5b$raw_nff<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> x$_n77$raw_ndb<1> _n5b x$_n5b$raw_nff<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> x$_n77$raw_ndb<2> _n5b x$_n5b$raw_nff<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> x$_n77$raw_ndb<3> _n5b x$_n5b$raw_nff<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> x$_n77$raw_ndb<4> _n5b x$_n5b$raw_nff<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> x$_n77$raw_ndb<5> _n5b x$_n5b$raw_nff<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> x$_n77$raw_ndb<6> _n5b x$_n5b$raw_nff<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> x$_n77$raw_ndb<7> _n5b x$_n5b$raw_nff<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names done _n108 +- =done +# o = (x < y ) ? x : y +# x < y +.names _n10c +0 +.names x<0> y<0> _n10c _n10b<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n10e +0 +.names x<0> y<0> _n10e _n10d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _n10d _n10b<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _n10d _n10f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _n10f _n10b<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _n10f _n110 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _n110 _n10b<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _n110 _n111 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _n111 _n10b<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _n111 _n112 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _n112 _n10b<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _n112 _n113 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _n113 _n10b<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _n113 _n114 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _n114 _n10b<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<7> y<7> _n114 _n115 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n10b<0> _n10b<1> _n10b<2> _n10b<3> _n10b<4> _n10b<5> _n10b<6> _n10b<7> _n116 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n115 _n116 _n10a +.def 0 +1 1 1 +# (x < y ) ? x : y +.names x<0> y<0> _n10a _n117<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> y<1> _n10a _n117<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> y<2> _n10a _n117<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> y<3> _n10a _n117<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> y<4> _n10a _n117<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> y<5> _n10a _n117<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> y<6> _n10a _n117<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> y<7> _n10a _n117<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n117<0> o$done_n109$true<0> +- =_n117<0> +.names _n117<1> o$done_n109$true<1> +- =_n117<1> +.names _n117<2> o$done_n109$true<2> +- =_n117<2> +.names _n117<3> o$done_n109$true<3> +- =_n117<3> +.names _n117<4> o$done_n109$true<4> +- =_n117<4> +.names _n117<5> o$done_n109$true<5> +- =_n117<5> +.names _n117<6> o$done_n109$true<6> +- =_n117<6> +.names _n117<7> o$done_n109$true<7> +- =_n117<7> +# if/else (done ) +.names o$done_n109$true<0> o<0> done o$done$raw_n122<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n109$true<1> o<1> done o$done$raw_n122<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n109$true<2> o<2> done o$done$raw_n122<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n109$true<3> o<3> done o$done$raw_n122<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n109$true<4> o<4> done o$done$raw_n122<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n109$true<5> o<5> done o$done$raw_n122<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n109$true<6> o<6> done o$done$raw_n122<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n109$true<7> o<7> done o$done$raw_n122<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (busy & ~done ) +.names y$_n5b$raw_nf6<0> y<0> _n59 y$_n59$raw_n131<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_nf6<1> y<1> _n59 y$_n59$raw_n131<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_nf6<2> y<2> _n59 y$_n59$raw_n131<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_nf6<3> y<3> _n59 y$_n59$raw_n131<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_nf6<4> y<4> _n59 y$_n59$raw_n131<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_nf6<5> y<5> _n59 y$_n59$raw_n131<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_nf6<6> y<6> _n59 y$_n59$raw_n131<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n5b$raw_nf6<7> y<7> _n59 y$_n59$raw_n131<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n5b$raw_nf2<0> lsb<0> _n59 lsb$_n59$raw_n13a<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n5b$raw_nf2<1> lsb<1> _n59 lsb$_n59$raw_n13a<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n5b$raw_nf2<2> lsb<2> _n59 lsb$_n59$raw_n13a<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nff<0> x<0> _n59 x$_n59$raw_n13e<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nff<1> x<1> _n59 x$_n59$raw_n13e<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nff<2> x<2> _n59 x$_n59$raw_n13e<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nff<3> x<3> _n59 x$_n59$raw_n13e<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nff<4> x<4> _n59 x$_n59$raw_n13e<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nff<5> x<5> _n59 x$_n59$raw_n13e<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nff<6> x<6> _n59 x$_n59$raw_n13e<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n5b$raw_nff<7> x<7> _n59 x$_n59$raw_n13e<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<0> o$done$raw_n122<0> _n59 o$_n59$raw_n147<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<1> o$done$raw_n122<1> _n59 o$_n59$raw_n147<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<2> o$done$raw_n122<2> _n59 o$_n59$raw_n147<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<3> o$done$raw_n122<3> _n59 o$_n59$raw_n147<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<4> o$done$raw_n122<4> _n59 o$_n59$raw_n147<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<5> o$done$raw_n122<5> _n59 o$_n59$raw_n147<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<6> o$done$raw_n122<6> _n59 o$_n59$raw_n147<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<7> o$done$raw_n122<7> _n59 o$_n59$raw_n147<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (load ) +.names y$load_n56$true<0> y$_n59$raw_n131<0> load y$load$raw_n153<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<1> y$_n59$raw_n131<1> load y$load$raw_n153<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<2> y$_n59$raw_n131<2> load y$load$raw_n153<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<3> y$_n59$raw_n131<3> load y$load$raw_n153<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<4> y$_n59$raw_n131<4> load y$load$raw_n153<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<5> y$_n59$raw_n131<5> load y$load$raw_n153<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<6> y$_n59$raw_n131<6> load y$load$raw_n153<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n56$true<7> y$_n59$raw_n131<7> load y$load$raw_n153<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$load_n57$true<0> lsb$_n59$raw_n13a<0> load lsb$load$raw_n15c<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$load_n57$true<1> lsb$_n59$raw_n13a<1> load lsb$load$raw_n15c<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$load_n57$true<2> lsb$_n59$raw_n13a<2> load lsb$load$raw_n15c<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<0> x$_n59$raw_n13e<0> load x$load$raw_n160<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<1> x$_n59$raw_n13e<1> load x$load$raw_n160<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<2> x$_n59$raw_n13e<2> load x$load$raw_n160<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<3> x$_n59$raw_n13e<3> load x$load$raw_n160<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<4> x$_n59$raw_n13e<4> load x$load$raw_n160<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<5> x$_n59$raw_n13e<5> load x$load$raw_n160<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<6> x$_n59$raw_n13e<6> load x$load$raw_n160<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n55$true<7> x$_n59$raw_n13e<7> load x$load$raw_n160<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<0> o$_n59$raw_n147<0> load o$load$raw_n16d<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<1> o$_n59$raw_n147<1> load o$load$raw_n16d<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<2> o$_n59$raw_n147<2> load o$load$raw_n16d<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<3> o$_n59$raw_n147<3> load o$load$raw_n16d<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<4> o$_n59$raw_n147<4> load o$load$raw_n16d<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<5> o$_n59$raw_n147<5> load o$load$raw_n16d<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<6> o$_n59$raw_n147<6> load o$load$raw_n16d<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<7> o$_n59$raw_n147<7> load o$load$raw_n16d<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names busy _n178 +0 1 +1 0 +.names _n178 _n179 +- =_n178 +.names start _n17a +- =start +# busy = 1 +.names busy$start_n17b$true +1 +# if/else (start ) +.names busy$start_n17b$true busy start busy$start$raw_n17e +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names done _n180 +- =done +# busy = 0 +.names busy$done_n181$true +0 +# if/else (done ) +.names busy$done_n181$true busy done busy$done$raw_n184 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (~busy ) +.names busy$start$raw_n17e busy$done$raw_n184 _n178 busy$_n178$raw_n187 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names _n54 _n5a _n5b _n77 _n7e _n85 _n97 _n18b +.def 0 + 1 - - - - - - 1 + 0 1 0 0 1 - - 1 + 0 1 0 0 1 - - 1 + 0 1 0 0 0 1 1 1 + 0 1 0 0 0 1 1 1 +.names _n18b y$load$raw_n153<0> y$load$raw_n153<1> y$load$raw_n153<2> y$load$raw_n153<3> y$load$raw_n153<4> y$load$raw_n153<5> y$load$raw_n153<6> y$load$raw_n153<7> y<0> y<1> y<2> y<3> y<4> y<5> y<6> y<7> -> _n18c<0> _n18c<1> _n18c<2> _n18c<3> _n18c<4> _n18c<5> _n18c<6> _n18c<7> +1 - - - - - - - - - - - - - - - - =y$load$raw_n153<0> =y$load$raw_n153<1> =y$load$raw_n153<2> =y$load$raw_n153<3> =y$load$raw_n153<4> =y$load$raw_n153<5> =y$load$raw_n153<6> =y$load$raw_n153<7> +0 - - - - - - - - - - - - - - - - =y<0> =y<1> =y<2> =y<3> =y<4> =y<5> =y<6> =y<7> +.names _n54 _n5a _n108 _n18d +.def 0 + 0 0 1 1 +.names _n18d o$load$raw_n16d<0> o$load$raw_n16d<1> o$load$raw_n16d<2> o$load$raw_n16d<3> o$load$raw_n16d<4> o$load$raw_n16d<5> o$load$raw_n16d<6> o$load$raw_n16d<7> o<0> o<1> o<2> o<3> o<4> o<5> o<6> o<7> -> _n18e<0> _n18e<1> _n18e<2> _n18e<3> _n18e<4> _n18e<5> _n18e<6> _n18e<7> +1 - - - - - - - - - - - - - - - - =o$load$raw_n16d<0> =o$load$raw_n16d<1> =o$load$raw_n16d<2> =o$load$raw_n16d<3> =o$load$raw_n16d<4> =o$load$raw_n16d<5> =o$load$raw_n16d<6> =o$load$raw_n16d<7> +0 - - - - - - - - - - - - - - - - =o<0> =o<1> =o<2> =o<3> =o<4> =o<5> =o<6> =o<7> +.names load$raw_n4c load +0 0 +1 1 +.names _n54 _n5a _n5b _n69 _n18f +.def 0 + 1 - - - 1 + 0 1 1 1 1 +.names _n18f lsb$load$raw_n15c<0> lsb$load$raw_n15c<1> lsb$load$raw_n15c<2> lsb<0> lsb<1> lsb<2> -> _n190<0> _n190<1> _n190<2> +1 - - - - - - =lsb$load$raw_n15c<0> =lsb$load$raw_n15c<1> =lsb$load$raw_n15c<2> +0 - - - - - - =lsb<0> =lsb<1> =lsb<2> +.names _n179 _n17a _n180 _n191 +.def 0 + 1 1 - 1 + 0 - 1 1 +.names _n191 busy$_n178$raw_n187 busy _n192 +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names xy_lsb$raw_nf<0> xy_lsb<0> +- =xy_lsb$raw_nf<0> +.names xy_lsb$raw_nc<1> xy_lsb<1> +- =xy_lsb$raw_nc<1> +.names done$raw_n3d done +0 0 +1 1 +.names diff$raw_n12<0> diff<0> +- =diff$raw_n12<0> +.names diff$raw_n12<1> diff<1> +- =diff$raw_n12<1> +.names diff$raw_n12<2> diff<2> +- =diff$raw_n12<2> +.names diff$raw_n12<3> diff<3> +- =diff$raw_n12<3> +.names diff$raw_n12<4> diff<4> +- =diff$raw_n12<4> +.names diff$raw_n12<5> diff<5> +- =diff$raw_n12<5> +.names diff$raw_n12<6> diff<6> +- =diff$raw_n12<6> +.names diff$raw_n12<7> diff<7> +- =diff$raw_n12<7> +.names _n54 _n5a _n5b _n77 _n7e _n85 _n97 _n193 +.def 0 + 1 - - - - - - 1 + 0 1 0 1 - - - 1 + 0 1 0 1 - - - 1 + 0 1 0 0 0 1 0 1 + 0 1 0 0 0 1 0 1 +.names _n193 x$load$raw_n160<0> x$load$raw_n160<1> x$load$raw_n160<2> x$load$raw_n160<3> x$load$raw_n160<4> x$load$raw_n160<5> x$load$raw_n160<6> x$load$raw_n160<7> x<0> x<1> x<2> x<3> x<4> x<5> x<6> x<7> -> _n194<0> _n194<1> _n194<2> _n194<3> _n194<4> _n194<5> _n194<6> _n194<7> +1 - - - - - - - - - - - - - - - - =x$load$raw_n160<0> =x$load$raw_n160<1> =x$load$raw_n160<2> =x$load$raw_n160<3> =x$load$raw_n160<4> =x$load$raw_n160<5> =x$load$raw_n160<6> =x$load$raw_n160<7> +0 - - - - - - - - - - - - - - - - =x<0> =x<1> =x<2> =x<3> =x<4> =x<5> =x<6> =x<7> +# non-blocking assignments +# latches +.r y$raw_n51<0> y<0> +.def 0 +1 1 +.r y$raw_n51<1> y<1> +.def 0 +1 1 +.r y$raw_n51<2> y<2> +.def 0 +1 1 +.r y$raw_n51<3> y<3> +.def 0 +1 1 +.r y$raw_n51<4> y<4> +.def 0 +1 1 +.r y$raw_n51<5> y<5> +.def 0 +1 1 +.r y$raw_n51<6> y<6> +.def 0 +1 1 +.r y$raw_n51<7> y<7> +.def 0 +1 1 +.latch _n18c<0> y<0> +.latch _n18c<1> y<1> +.latch _n18c<2> y<2> +.latch _n18c<3> y<3> +.latch _n18c<4> y<4> +.latch _n18c<5> y<5> +.latch _n18c<6> y<6> +.latch _n18c<7> y<7> +.r o$raw_n52<0> o<0> +.def 0 +1 1 +.r o$raw_n52<1> o<1> +.def 0 +1 1 +.r o$raw_n52<2> o<2> +.def 0 +1 1 +.r o$raw_n52<3> o<3> +.def 0 +1 1 +.r o$raw_n52<4> o<4> +.def 0 +1 1 +.r o$raw_n52<5> o<5> +.def 0 +1 1 +.r o$raw_n52<6> o<6> +.def 0 +1 1 +.r o$raw_n52<7> o<7> +.def 0 +1 1 +.latch _n18e<0> o<0> +.latch _n18e<1> o<1> +.latch _n18e<2> o<2> +.latch _n18e<3> o<3> +.latch _n18e<4> o<4> +.latch _n18e<5> o<5> +.latch _n18e<6> o<6> +.latch _n18e<7> o<7> +.r busy$raw_n4f busy +0 0 +1 1 +.latch _n192 busy +.r lsb$raw_n53<0> lsb<0> +.def 0 +1 1 +.r lsb$raw_n53<1> lsb<1> +.def 0 +1 1 +.r lsb$raw_n53<2> lsb<2> +.def 0 +1 1 +.latch _n190<0> lsb<0> +.latch _n190<1> lsb<1> +.latch _n190<2> lsb<2> +.r x$raw_n50<0> x<0> +.def 0 +1 1 +.r x$raw_n50<1> x<1> +.def 0 +1 1 +.r x$raw_n50<2> x<2> +.def 0 +1 1 +.r x$raw_n50<3> x<3> +.def 0 +1 1 +.r x$raw_n50<4> x<4> +.def 0 +1 1 +.r x$raw_n50<5> x<5> +.def 0 +1 1 +.r x$raw_n50<6> x<6> +.def 0 +1 1 +.r x$raw_n50<7> x<7> +.def 0 +1 1 +.latch _n194<0> x<0> +.latch _n194<1> x<1> +.latch _n194<2> x<2> +.latch _n194<3> x<3> +.latch _n194<4> x<4> +.latch _n194<5> x<5> +.latch _n194<6> x<6> +.latch _n194<7> x<7> +# quasi-continuous assignment +.end + + +.model select +# I/O ports +.inputs z<0> z<1> z<2> z<3> z<4> z<5> z<6> z<7> +.inputs lsb<0> lsb<1> lsb<2> +.outputs select<0> +.names _n196<0> +0 +.names _n196<1> +0 +.names _n196<2> +0 +# lsb == 'b000 +.names lsb<0> _n196<0> _n197<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n196<1> _n197<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n196<2> _n197<2> +.def 0 +0 1 1 +1 0 1 +.names _n197<0> _n197<1> _n197<2> _n198 +.def 1 +0 0 0 0 +.names _n198 _n195 +0 1 +1 0 +.names _n195 _n199 +- =_n195 +# select = z [0] +.names z<0> select$_n195_n19a$true<0> +- =z<0> +.names _n19c<0> +1 +.names _n19c<1> +0 +.names _n19c<2> +0 +# lsb == 'b001 +.names lsb<0> _n19c<0> _n19d<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n19c<1> _n19d<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n19c<2> _n19d<2> +.def 0 +0 1 1 +1 0 1 +.names _n19d<0> _n19d<1> _n19d<2> _n19e +.def 1 +0 0 0 0 +.names _n19e _n19b +0 1 +1 0 +.names _n19b _n19f +- =_n19b +# select = z [1] +.names z<1> select$_n19b_n1a0$true<0> +- =z<1> +.names _n1a2<0> +0 +.names _n1a2<1> +1 +.names _n1a2<2> +0 +# lsb == 'b010 +.names lsb<0> _n1a2<0> _n1a3<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1a2<1> _n1a3<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1a2<2> _n1a3<2> +.def 0 +0 1 1 +1 0 1 +.names _n1a3<0> _n1a3<1> _n1a3<2> _n1a4 +.def 1 +0 0 0 0 +.names _n1a4 _n1a1 +0 1 +1 0 +.names _n1a1 _n1a5 +- =_n1a1 +# select = z [2] +.names z<2> select$_n1a1_n1a6$true<0> +- =z<2> +.names _n1a8<0> +1 +.names _n1a8<1> +1 +.names _n1a8<2> +0 +# lsb == 'b011 +.names lsb<0> _n1a8<0> _n1a9<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1a8<1> _n1a9<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1a8<2> _n1a9<2> +.def 0 +0 1 1 +1 0 1 +.names _n1a9<0> _n1a9<1> _n1a9<2> _n1aa +.def 1 +0 0 0 0 +.names _n1aa _n1a7 +0 1 +1 0 +.names _n1a7 _n1ab +- =_n1a7 +# select = z [3] +.names z<3> select$_n1a7_n1ac$true<0> +- =z<3> +.names _n1ae<0> +0 +.names _n1ae<1> +0 +.names _n1ae<2> +1 +# lsb == 'b100 +.names lsb<0> _n1ae<0> _n1af<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1ae<1> _n1af<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1ae<2> _n1af<2> +.def 0 +0 1 1 +1 0 1 +.names _n1af<0> _n1af<1> _n1af<2> _n1b0 +.def 1 +0 0 0 0 +.names _n1b0 _n1ad +0 1 +1 0 +.names _n1ad _n1b1 +- =_n1ad +# select = z [4] +.names z<4> select$_n1ad_n1b2$true<0> +- =z<4> +.names _n1b4<0> +1 +.names _n1b4<1> +0 +.names _n1b4<2> +1 +# lsb == 'b101 +.names lsb<0> _n1b4<0> _n1b5<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1b4<1> _n1b5<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1b4<2> _n1b5<2> +.def 0 +0 1 1 +1 0 1 +.names _n1b5<0> _n1b5<1> _n1b5<2> _n1b6 +.def 1 +0 0 0 0 +.names _n1b6 _n1b3 +0 1 +1 0 +.names _n1b3 _n1b7 +- =_n1b3 +# select = z [5] +.names z<5> select$_n1b3_n1b8$true<0> +- =z<5> +.names _n1ba<0> +0 +.names _n1ba<1> +1 +.names _n1ba<2> +1 +# lsb == 'b110 +.names lsb<0> _n1ba<0> _n1bb<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1ba<1> _n1bb<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1ba<2> _n1bb<2> +.def 0 +0 1 1 +1 0 1 +.names _n1bb<0> _n1bb<1> _n1bb<2> _n1bc +.def 1 +0 0 0 0 +.names _n1bc _n1b9 +0 1 +1 0 +.names _n1b9 _n1bd +- =_n1b9 +# select = z [6] +.names z<6> select$_n1b9_n1be$true<0> +- =z<6> +# select = z [7] +.names z<7> select$_n1b9_n1bf$false<0> +- =z<7> +# if/else (lsb == 'b110) +.names select$_n1b9_n1be$true<0> select$_n1b9_n1bf$false<0> _n1b9 select$_n1b9$raw_n1c1<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b101) +.names select$_n1b3_n1b8$true<0> select$_n1b9$raw_n1c1<0> _n1b3 select$_n1b3$raw_n1c6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b100) +.names select$_n1ad_n1b2$true<0> select$_n1b3$raw_n1c6<0> _n1ad select$_n1ad$raw_n1cb<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b011) +.names select$_n1a7_n1ac$true<0> select$_n1ad$raw_n1cb<0> _n1a7 select$_n1a7$raw_n1d0<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b010) +.names select$_n1a1_n1a6$true<0> select$_n1a7$raw_n1d0<0> _n1a1 select$_n1a1$raw_n1d5<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b001) +.names select$_n19b_n1a0$true<0> select$_n1a1$raw_n1d5<0> _n19b select$_n19b$raw_n1da<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b000) +.names select$_n195_n19a$true<0> select$_n19b$raw_n1da<0> _n195 select$_n195$raw_n1df<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names select$_n195$raw_n1df<0> select<0> +- =select$_n195$raw_n1df<0> +.end + + Index: vis_dev/vis-2.1/examples/gcd/gcd2.ord =================================================================== --- vis_dev/vis-2.1/examples/gcd/gcd2.ord (revision 11) +++ vis_dev/vis-2.1/examples/gcd/gcd2.ord (revision 11) @@ -0,0 +1,112 @@ +# vis release 2.1 (compiled 17-Nov-08 at 8:20 PM) +# network name: testGcd +# generated: Tue Nov 18 11:45:34 2008 +# +# name type mddId vals levs +x<3> primary-input 12 2 (0) +x<2> primary-input 13 2 (1) +x<4> primary-input 11 2 (2) +x<1> primary-input 14 2 (3) +x<6> primary-input 9 2 (4) +x<5> primary-input 10 2 (5) +x<7> primary-input 8 2 (6) +y<5> primary-input 2 2 (7) +y<0> primary-input 7 2 (8) +x<0> primary-input 15 2 (9) +y<2> primary-input 5 2 (10) +y<3> primary-input 4 2 (11) +y<4> primary-input 3 2 (12) +y<6> primary-input 1 2 (13) +y<1> primary-input 6 2 (14) +y<7> primary-input 0 2 (15) +s primary-input 16 2 (16) +busy$NS shadow 56 2 (17) +busy latch 55 2 (18) +o<6> latch 59 2 (19) +o<6>$NS shadow 60 2 (20) +g.x<6>$NS shadow 40 2 (21) +g.x<6> latch 39 2 (22) +a<6>$NS shadow 78 2 (23) +a<6> latch 77 2 (24) +start$NS shadow 74 2 (25) +start latch 73 2 (26) +b<0>$NS shadow 106 2 (27) +b<0> latch 105 2 (28) +a<4>$NS shadow 82 2 (29) +a<4> latch 81 2 (30) +a<2>$NS shadow 86 2 (31) +a<2> latch 85 2 (32) +a<0>$NS shadow 90 2 (33) +a<0> latch 89 2 (34) +b<7>$NS shadow 92 2 (35) +b<7> latch 91 2 (36) +b<6>$NS shadow 94 2 (37) +b<6> latch 93 2 (38) +b<5>$NS shadow 96 2 (39) +b<5> latch 95 2 (40) +b<4>$NS shadow 98 2 (41) +b<4> latch 97 2 (42) +a<7>$NS shadow 76 2 (43) +a<7> latch 75 2 (44) +b<3>$NS shadow 100 2 (45) +b<3> latch 99 2 (46) +b<1>$NS shadow 104 2 (47) +b<1> latch 103 2 (48) +b<2>$NS shadow 102 2 (49) +b<2> latch 101 2 (50) +a<5>$NS shadow 80 2 (51) +a<5> latch 79 2 (52) +a<1>$NS shadow 88 2 (53) +a<1> latch 87 2 (54) +a<3>$NS shadow 84 2 (55) +a<3> latch 83 2 (56) +g.y<6>$NS shadow 24 2 (57) +g.y<6> latch 23 2 (58) +g.x<7>$NS shadow 42 2 (59) +g.x<7> latch 41 2 (60) +g.y<7>$NS shadow 26 2 (61) +g.y<7> latch 25 2 (62) +o<7> latch 57 2 (63) +o<7>$NS shadow 58 2 (64) +g.lsb<2>$NS shadow 22 2 (65) +g.lsb<2> latch 21 2 (66) +g.lsb<1> latch 19 2 (67) +g.lsb<1>$NS shadow 20 2 (68) +o<5> latch 61 2 (69) +o<5>$NS shadow 62 2 (70) +g.y<5>$NS shadow 28 2 (71) +g.y<5> latch 27 2 (72) +g.x<5>$NS shadow 44 2 (73) +g.x<5> latch 43 2 (74) +o<4> latch 63 2 (75) +o<4>$NS shadow 64 2 (76) +g.x<4>$NS shadow 46 2 (77) +g.x<4> latch 45 2 (78) +g.y<4>$NS shadow 30 2 (79) +g.y<4> latch 29 2 (80) +g.lsb<0>$NS shadow 18 2 (81) +g.lsb<0> latch 17 2 (82) +o<3> latch 65 2 (83) +o<3>$NS shadow 66 2 (84) +g.y<3>$NS shadow 32 2 (85) +g.y<3> latch 31 2 (86) +g.x<3> latch 47 2 (87) +g.x<3>$NS shadow 48 2 (88) +o<2> latch 67 2 (89) +o<2>$NS shadow 68 2 (90) +g.x<2> latch 49 2 (91) +g.x<2>$NS shadow 50 2 (92) +g.y<2>$NS shadow 34 2 (93) +g.y<2> latch 33 2 (94) +g.y<1>$NS shadow 36 2 (95) +g.y<1> latch 35 2 (96) +g.x<1> latch 51 2 (97) +g.x<1>$NS shadow 52 2 (98) +g.x<0> latch 53 2 (99) +g.x<0>$NS shadow 54 2 (100) +g.y<0>$NS shadow 38 2 (101) +g.y<0> latch 37 2 (102) +o<0> latch 71 2 (103) +o<0>$NS shadow 72 2 (104) +o<1> latch 69 2 (105) +o<1>$NS shadow 70 2 (106) Index: vis_dev/vis-2.1/examples/gcd/gcd2.v =================================================================== --- vis_dev/vis-2.1/examples/gcd/gcd2.v (revision 11) +++ vis_dev/vis-2.1/examples/gcd/gcd2.v (revision 11) @@ -0,0 +1,148 @@ +// Testbench for the gcd circuit. +module testGcd(clock,x,y,s); + parameter N = 8; + parameter logN = 3; + input clock; + input [N-1:0] x,y; + input s; + reg [N-1:0] a,b; + reg start; + wire busy; + wire [N-1:0] o; + + // Unit under test. + gcd #(N,logN) g(clock,start,a,b,busy,o); + + initial begin + a = 0; + b = 0; + start = 0; + end + + always @ (posedge clock) begin + a = x; + b = y; + start = s; + end // always @ (posedge clock) + +endmodule // testGcd + +// GCD circuit for unsigned N-bit numbers +// a[0], b[0], and o[0] are the least significant bits +// +// Author: Fabio Somenzi +module gcd(clock,start,a,b,busy,o); + parameter N = 8; + parameter logN = 3; + input clock; + input start; + input [N-1:0] a; + input [N-1:0] b; + output busy; + output [N-1:0] o; + + reg [logN-1:0] lsb; + reg [N-1:0] x; + reg [N-1:0] y; + wire done; + wire load; + reg busy; + reg [N-1:0] o; + + wire [1:0] xy_lsb; + wire [N-1:0] diff; + + function select; + input [N-1:0] z; + input [logN-1:0] lsb; + begin: _select + if (lsb == 3'd0) + select = z[0]; + else if (lsb == 3'd1) + select = z[1]; + else if (lsb == 3'd2) + select = z[2]; + else if (lsb == 3'd3) + select = z[3]; + else if (lsb == 3'd4) + select = z[4]; + else if (lsb == 3'd5) + select = z[5]; + else if (lsb == 3'd6) + select = z[6]; + else + select = z[7]; + end // block: _select + endfunction // select + + assign xy_lsb[1] = select(x,lsb); + assign xy_lsb[0] = select(y,lsb); + assign diff = x < y ? y - x : x - y; + assign done = ((x == y) | (x == 0) | (y == 0)) & busy; + assign load = start & ~busy; + + initial begin + busy = 0; + x = 0; + y = 0; + o = 0; + lsb = 0; + end // initial begin + + // Data path. + always @(posedge clock) begin + if (load) begin + x = a; + y = b; + lsb = 0; + end // if (load) + else if (busy & ~done) begin + case (xy_lsb) + 2'b00: + if (lsb<7) begin + lsb = lsb + 1; + end + 2'b01: + begin + x[N-2:0] = x[N-1:1]; + x[N-1] = 0; + end + 2'b10: + begin + y[N-2:0] = y[N-1:1]; + y[N-1] = 0; + end + 2'b11: begin + if (x < y) begin + y[N-2:0] = diff[N-1:1]; + y[N-1] = 0; + end // if (x < y) + else begin + x[N-2:0] = diff[N-1:1]; + x[N-1] = 0; + end // else: !if(x < y) + end // case: 2b'11 + endcase // case (xy_lsb) + end // if (~done) + else if (done) begin + o = (x < y) ? x : y; + end // else: !if(~done) + end // always @ (posedge clock) + + + + // Controller. + always @(posedge clock) begin + if (~busy) begin + if (start) begin + busy = 1; + end // if (start) + end // if (~busy) + else begin + if (done) begin + busy = 0; + end + end // else: !if(~busy) + end // always @ (posedge clock) + +endmodule // gcd Index: vis_dev/vis-2.1/examples/gcd/gcd3.mv =================================================================== --- vis_dev/vis-2.1/examples/gcd/gcd3.mv (revision 11) +++ vis_dev/vis-2.1/examples/gcd/gcd3.mv (revision 11) @@ -0,0 +1,2936 @@ +# ../../../vl2mv-2.1/vl2mv gcd3.v +# version: 1.4 +# date: 13:20:40 11/18/2008 (CET) +.model testGcd +# I/O ports +.inputs y<0> y<1> y<2> y<3> y<4> y<5> y<6> y<7> +.inputs s +.inputs x<0> x<1> x<2> x<3> x<4> x<5> x<6> x<7> +.subckt gcd g start=start a<0>=a<0> a<1>=a<1> a<2>=a<2> a<3>=a<3> a<4>=a<4> a<5>=a<5> a<6>=a<6> a<7>=a<7> b<0>=b<0> b<1>=b<1> b<2>=b<2> b<3>=b<3> b<4>=b<4> b<5>=b<5> b<6>=b<6> b<7>=b<7> busy=busy o<0>=o<0> o<1>=o<1> o<2>=o<2> o<3>=o<3> o<4>=o<4> o<5>=o<5> o<6>=o<6> o<7>=o<7> +# a = 0 +.names a$raw_n0<0> +0 +.names a$raw_n0<1> +0 +.names a$raw_n0<2> +0 +.names a$raw_n0<3> +0 +.names a$raw_n0<4> +0 +.names a$raw_n0<5> +0 +.names a$raw_n0<6> +0 +.names a$raw_n0<7> +0 +# b = 0 +.names b$raw_n1<0> +0 +.names b$raw_n1<1> +0 +.names b$raw_n1<2> +0 +.names b$raw_n1<3> +0 +.names b$raw_n1<4> +0 +.names b$raw_n1<5> +0 +.names b$raw_n1<6> +0 +.names b$raw_n1<7> +0 +# start = 0 +.names start$raw_n2 +0 +# non-blocking assignments for initial +# a = x +.names x<0> a$raw_n3<0> +- =x<0> +.names x<1> a$raw_n3<1> +- =x<1> +.names x<2> a$raw_n3<2> +- =x<2> +.names x<3> a$raw_n3<3> +- =x<3> +.names x<4> a$raw_n3<4> +- =x<4> +.names x<5> a$raw_n3<5> +- =x<5> +.names x<6> a$raw_n3<6> +- =x<6> +.names x<7> a$raw_n3<7> +- =x<7> +# b = y +.names y<0> b$raw_n4<0> +- =y<0> +.names y<1> b$raw_n4<1> +- =y<1> +.names y<2> b$raw_n4<2> +- =y<2> +.names y<3> b$raw_n4<3> +- =y<3> +.names y<4> b$raw_n4<4> +- =y<4> +.names y<5> b$raw_n4<5> +- =y<5> +.names y<6> b$raw_n4<6> +- =y<6> +.names y<7> b$raw_n4<7> +- =y<7> +# start = s +.names s start$raw_n5 +- =s +# conflict arbitrators +.names _n6 +.def 0 + 1 +.names _n6 start$raw_n5 _n7 +.def 0 +1 0 0 +1 1 1 +.names _n8 +.def 0 + 1 +.names _n8 a$raw_n3<0> a$raw_n3<1> a$raw_n3<2> a$raw_n3<3> a$raw_n3<4> a$raw_n3<5> a$raw_n3<6> a$raw_n3<7> -> _n9<0> _n9<1> _n9<2> _n9<3> _n9<4> _n9<5> _n9<6> _n9<7> +.def 0 0 0 0 0 0 0 0 +1 - - - - - - - - =a$raw_n3<0> =a$raw_n3<1> =a$raw_n3<2> =a$raw_n3<3> =a$raw_n3<4> =a$raw_n3<5> =a$raw_n3<6> =a$raw_n3<7> +.names _na +.def 0 + 1 +.names _na b$raw_n4<0> b$raw_n4<1> b$raw_n4<2> b$raw_n4<3> b$raw_n4<4> b$raw_n4<5> b$raw_n4<6> b$raw_n4<7> -> _nb<0> _nb<1> _nb<2> _nb<3> _nb<4> _nb<5> _nb<6> _nb<7> +.def 0 0 0 0 0 0 0 0 +1 - - - - - - - - =b$raw_n4<0> =b$raw_n4<1> =b$raw_n4<2> =b$raw_n4<3> =b$raw_n4<4> =b$raw_n4<5> =b$raw_n4<6> =b$raw_n4<7> +# non-blocking assignments +# latches +.r a$raw_n0<0> a<0> +.def 0 +1 1 +.r a$raw_n0<1> a<1> +.def 0 +1 1 +.r a$raw_n0<2> a<2> +.def 0 +1 1 +.r a$raw_n0<3> a<3> +.def 0 +1 1 +.r a$raw_n0<4> a<4> +.def 0 +1 1 +.r a$raw_n0<5> a<5> +.def 0 +1 1 +.r a$raw_n0<6> a<6> +.def 0 +1 1 +.r a$raw_n0<7> a<7> +.def 0 +1 1 +.latch _n9<0> a<0> +.latch _n9<1> a<1> +.latch _n9<2> a<2> +.latch _n9<3> a<3> +.latch _n9<4> a<4> +.latch _n9<5> a<5> +.latch _n9<6> a<6> +.latch _n9<7> a<7> +.r start$raw_n2 start +0 0 +1 1 +.latch _n7 start +.r b$raw_n1<0> b<0> +.def 0 +1 1 +.r b$raw_n1<1> b<1> +.def 0 +1 1 +.r b$raw_n1<2> b<2> +.def 0 +1 1 +.r b$raw_n1<3> b<3> +.def 0 +1 1 +.r b$raw_n1<4> b<4> +.def 0 +1 1 +.r b$raw_n1<5> b<5> +.def 0 +1 1 +.r b$raw_n1<6> b<6> +.def 0 +1 1 +.r b$raw_n1<7> b<7> +.def 0 +1 1 +.latch _nb<0> b<0> +.latch _nb<1> b<1> +.latch _nb<2> b<2> +.latch _nb<3> b<3> +.latch _nb<4> b<4> +.latch _nb<5> b<5> +.latch _nb<6> b<6> +.latch _nb<7> b<7> +# quasi-continuous assignment +.end + + +.model gcd +# I/O ports +.outputs o<0> o<1> o<2> o<3> o<4> o<5> o<6> o<7> +.outputs busy +.inputs a<0> a<1> a<2> a<3> a<4> a<5> a<6> a<7> +.inputs start +.inputs b<0> b<1> b<2> b<3> b<4> b<5> b<6> b<7> +# assign xy_lsb [1] = select (x ,lsb ) +.subckt select _ne select<0>=_nd<0> z<0>=x<0> z<1>=x<1> z<2>=x<2> z<3>=x<3> z<4>=x<4> z<5>=x<5> z<6>=x<6> z<7>=x<7> lsb<0>=lsb<0> lsb<1>=lsb<1> lsb<2>=lsb<2> +.names _nd<0> xy_lsb$raw_nc<1> +- =_nd<0> +# assign xy_lsb [0] = select (y ,lsb ) +.subckt select _n11 select<0>=_n10<0> z<0>=y<0> z<1>=y<1> z<2>=y<2> z<3>=y<3> z<4>=y<4> z<5>=y<5> z<6>=y<6> z<7>=y<7> lsb<0>=lsb<0> lsb<1>=lsb<1> lsb<2>=lsb<2> +.names _n10<0> xy_lsb$raw_nf<0> +- =_n10<0> +# assign diff = x < y ? y - x : x - y +# x < y +.names _n15 +0 +.names x<0> y<0> _n15 _n14<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n17 +0 +.names x<0> y<0> _n17 _n16 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _n16 _n14<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _n16 _n18 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _n18 _n14<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _n18 _n19 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _n19 _n14<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _n19 _n1a +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _n1a _n14<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _n1a _n1b +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _n1b _n14<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _n1b _n1c +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _n1c _n14<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _n1c _n1d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _n1d _n14<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<7> y<7> _n1d _n1e +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n14<0> _n14<1> _n14<2> _n14<3> _n14<4> _n14<5> _n14<6> _n14<7> _n1f +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n1e _n1f _n13 +.def 0 +1 1 1 +# y - x +.names _n21 +0 +.names y<0> x<0> _n21 _n20<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n23 +0 +.names y<0> x<0> _n23 _n22 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<1> x<1> _n22 _n20<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<1> x<1> _n22 _n24 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<2> x<2> _n24 _n20<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<2> x<2> _n24 _n25 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<3> x<3> _n25 _n20<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<3> x<3> _n25 _n26 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<4> x<4> _n26 _n20<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<4> x<4> _n26 _n27 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<5> x<5> _n27 _n20<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<5> x<5> _n27 _n28 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<6> x<6> _n28 _n20<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names y<6> x<6> _n28 _n29 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names y<7> x<7> _n29 _n20<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# x - y +.names _n2b +0 +.names x<0> y<0> _n2b _n2a<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n2d +0 +.names x<0> y<0> _n2d _n2c +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _n2c _n2a<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _n2c _n2e +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _n2e _n2a<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _n2e _n2f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _n2f _n2a<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _n2f _n30 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _n30 _n2a<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _n30 _n31 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _n31 _n2a<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _n31 _n32 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _n32 _n2a<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _n32 _n33 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _n33 _n2a<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# x < y ? y - x : x - y +.names _n20<0> _n2a<0> _n13 _n34<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<1> _n2a<1> _n13 _n34<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<2> _n2a<2> _n13 _n34<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<3> _n2a<3> _n13 _n34<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<4> _n2a<4> _n13 _n34<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<5> _n2a<5> _n13 _n34<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<6> _n2a<6> _n13 _n34<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n20<7> _n2a<7> _n13 _n34<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n34<0> diff$raw_n12<0> +- =_n34<0> +.names _n34<1> diff$raw_n12<1> +- =_n34<1> +.names _n34<2> diff$raw_n12<2> +- =_n34<2> +.names _n34<3> diff$raw_n12<3> +- =_n34<3> +.names _n34<4> diff$raw_n12<4> +- =_n34<4> +.names _n34<5> diff$raw_n12<5> +- =_n34<5> +.names _n34<6> diff$raw_n12<6> +- =_n34<6> +.names _n34<7> diff$raw_n12<7> +- =_n34<7> +# assign done = ((x == y ) | (x == 0) | (y == 0) | (cpt > 13)) & busy +# x == y +.names x<0> y<0> _n3f<0> +.def 0 +0 1 1 +1 0 1 +.names x<1> y<1> _n3f<1> +.def 0 +0 1 1 +1 0 1 +.names x<2> y<2> _n3f<2> +.def 0 +0 1 1 +1 0 1 +.names x<3> y<3> _n3f<3> +.def 0 +0 1 1 +1 0 1 +.names x<4> y<4> _n3f<4> +.def 0 +0 1 1 +1 0 1 +.names x<5> y<5> _n3f<5> +.def 0 +0 1 1 +1 0 1 +.names x<6> y<6> _n3f<6> +.def 0 +0 1 1 +1 0 1 +.names x<7> y<7> _n3f<7> +.def 0 +0 1 1 +1 0 1 +.names _n3f<0> _n3f<1> _n3f<2> _n3f<3> _n3f<4> _n3f<5> _n3f<6> _n3f<7> _n40 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n40 _n3e +0 1 +1 0 +.names _n42<0> +0 +.names _n42<1> +0 +.names _n42<2> +0 +.names _n42<3> +0 +.names _n42<4> +0 +.names _n42<5> +0 +.names _n42<6> +0 +.names _n42<7> +0 +# x == 0 +.names x<0> _n42<0> _n43<0> +.def 0 +0 1 1 +1 0 1 +.names x<1> _n42<1> _n43<1> +.def 0 +0 1 1 +1 0 1 +.names x<2> _n42<2> _n43<2> +.def 0 +0 1 1 +1 0 1 +.names x<3> _n42<3> _n43<3> +.def 0 +0 1 1 +1 0 1 +.names x<4> _n42<4> _n43<4> +.def 0 +0 1 1 +1 0 1 +.names x<5> _n42<5> _n43<5> +.def 0 +0 1 1 +1 0 1 +.names x<6> _n42<6> _n43<6> +.def 0 +0 1 1 +1 0 1 +.names x<7> _n42<7> _n43<7> +.def 0 +0 1 1 +1 0 1 +.names _n43<0> _n43<1> _n43<2> _n43<3> _n43<4> _n43<5> _n43<6> _n43<7> _n44 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n44 _n41 +0 1 +1 0 +# (x == y ) | (x == 0) +.names _n3e _n41 _n45 +.def 1 +0 0 0 +.names _n47<0> +0 +.names _n47<1> +0 +.names _n47<2> +0 +.names _n47<3> +0 +.names _n47<4> +0 +.names _n47<5> +0 +.names _n47<6> +0 +.names _n47<7> +0 +# y == 0 +.names y<0> _n47<0> _n48<0> +.def 0 +0 1 1 +1 0 1 +.names y<1> _n47<1> _n48<1> +.def 0 +0 1 1 +1 0 1 +.names y<2> _n47<2> _n48<2> +.def 0 +0 1 1 +1 0 1 +.names y<3> _n47<3> _n48<3> +.def 0 +0 1 1 +1 0 1 +.names y<4> _n47<4> _n48<4> +.def 0 +0 1 1 +1 0 1 +.names y<5> _n47<5> _n48<5> +.def 0 +0 1 1 +1 0 1 +.names y<6> _n47<6> _n48<6> +.def 0 +0 1 1 +1 0 1 +.names y<7> _n47<7> _n48<7> +.def 0 +0 1 1 +1 0 1 +.names _n48<0> _n48<1> _n48<2> _n48<3> _n48<4> _n48<5> _n48<6> _n48<7> _n49 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n49 _n46 +0 1 +1 0 +# (x == y ) | (x == 0) | (y == 0) +.names _n45 _n46 _n4a +.def 1 +0 0 0 +.names _n4b<0> +1 +.names _n4b<1> +0 +.names _n4b<2> +1 +.names _n4b<3> +1 +# cpt > 13 +.names _n4e +0 +.names cpt<0> _n4b<0> _n4e _n4d<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n50 +0 +.names cpt<0> _n4b<0> _n50 _n4f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names cpt<1> _n4b<1> _n4f _n4d<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names cpt<1> _n4b<1> _n4f _n51 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names cpt<2> _n4b<2> _n51 _n4d<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names cpt<2> _n4b<2> _n51 _n52 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names cpt<3> _n4b<3> _n52 _n4d<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names cpt<3> _n4b<3> _n52 _n53 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n4d<0> _n4d<1> _n4d<2> _n4d<3> _n54 +.def 0 +0 0 0 0 1 +.names _n53 _n54 _n55 +.def 1 +0 0 0 +.names _n55 _n4c +0 1 +1 0 +# (x == y ) | (x == 0) | (y == 0) | (cpt > 13) +.names _n4a _n4c _n56 +.def 1 +0 0 0 +# ((x == y ) | (x == 0) | (y == 0) | (cpt > 13)) & busy +.names _n56 busy _n57 +.def 0 +1 1 1 +.names _n57 done$raw_n3d +- =_n57 +# assign load = start & ~busy +.names busy _n59 +0 1 +1 0 +# start & ~busy +.names start _n59 _n5a +.def 0 +1 1 1 +.names _n5a load$raw_n58 +- =_n5a +# busy = 0 +.names busy$raw_n5b +0 +# x = 0 +.names x$raw_n5c<0> +0 +.names x$raw_n5c<1> +0 +.names x$raw_n5c<2> +0 +.names x$raw_n5c<3> +0 +.names x$raw_n5c<4> +0 +.names x$raw_n5c<5> +0 +.names x$raw_n5c<6> +0 +.names x$raw_n5c<7> +0 +# y = 0 +.names y$raw_n5d<0> +0 +.names y$raw_n5d<1> +0 +.names y$raw_n5d<2> +0 +.names y$raw_n5d<3> +0 +.names y$raw_n5d<4> +0 +.names y$raw_n5d<5> +0 +.names y$raw_n5d<6> +0 +.names y$raw_n5d<7> +0 +# o = 0 +.names o$raw_n5e<0> +0 +.names o$raw_n5e<1> +0 +.names o$raw_n5e<2> +0 +.names o$raw_n5e<3> +0 +.names o$raw_n5e<4> +0 +.names o$raw_n5e<5> +0 +.names o$raw_n5e<6> +0 +.names o$raw_n5e<7> +0 +# lsb = 0 +.names lsb$raw_n5f<0> +0 +.names lsb$raw_n5f<1> +0 +.names lsb$raw_n5f<2> +0 +# cpt = 0 +.names cpt$raw_n60<0> +0 +.names cpt$raw_n60<1> +0 +.names cpt$raw_n60<2> +0 +.names cpt$raw_n60<3> +0 +# non-blocking assignments for initial +.names load _n61 +- =load +# x = a +.names a<0> x$load_n62$true<0> +- =a<0> +.names a<1> x$load_n62$true<1> +- =a<1> +.names a<2> x$load_n62$true<2> +- =a<2> +.names a<3> x$load_n62$true<3> +- =a<3> +.names a<4> x$load_n62$true<4> +- =a<4> +.names a<5> x$load_n62$true<5> +- =a<5> +.names a<6> x$load_n62$true<6> +- =a<6> +.names a<7> x$load_n62$true<7> +- =a<7> +# y = b +.names b<0> y$load_n63$true<0> +- =b<0> +.names b<1> y$load_n63$true<1> +- =b<1> +.names b<2> y$load_n63$true<2> +- =b<2> +.names b<3> y$load_n63$true<3> +- =b<3> +.names b<4> y$load_n63$true<4> +- =b<4> +.names b<5> y$load_n63$true<5> +- =b<5> +.names b<6> y$load_n63$true<6> +- =b<6> +.names b<7> y$load_n63$true<7> +- =b<7> +# lsb = 0 +.names lsb$load_n64$true<0> +0 +.names lsb$load_n64$true<1> +0 +.names lsb$load_n64$true<2> +0 +# cpt = 0 +.names cpt$load_n65$true<0> +0 +.names cpt$load_n65$true<1> +0 +.names cpt$load_n65$true<2> +0 +.names cpt$load_n65$true<3> +0 +.names done _n66 +0 1 +1 0 +# busy & ~done +.names busy _n66 _n67 +.def 0 +1 1 1 +.names _n67 _n68 +- =_n67 +# cpt = cpt + 1 +.names _n6a<0> +1 +.names _n6a<1> +0 +.names _n6a<2> +0 +.names _n6a<3> +0 +# cpt + 1 +.names _n6c +0 +.names cpt<0> _n6a<0> _n6c _n6b<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n6e +0 +.names cpt<0> _n6a<0> _n6e _n6d +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names cpt<1> _n6a<1> _n6d _n6b<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names cpt<1> _n6a<1> _n6d _n6f +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names cpt<2> _n6a<2> _n6f _n6b<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names cpt<2> _n6a<2> _n6f _n70 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names cpt<3> _n6a<3> _n70 _n6b<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n6b<0> cpt$_n67_n69$true<0> +- =_n6b<0> +.names _n6b<1> cpt$_n67_n69$true<1> +- =_n6b<1> +.names _n6b<2> cpt$_n67_n69$true<2> +- =_n6b<2> +.names _n6b<3> cpt$_n67_n69$true<3> +- =_n6b<3> +.names _n73<0> +0 +.names _n73<1> +0 +.names xy_lsb<0> _n73<0> _n74<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _n73<1> _n74<1> +.def 0 +0 1 1 +1 0 1 +.names _n74<0> _n74<1> _n75 +.def 1 +0 0 0 +.names _n75 _n72 +0 1 +1 0 +.names _n72 _n71 +1 1 +0 0 +.names _n76<0> +1 +.names _n76<1> +1 +.names _n76<2> +1 +# lsb < 7 +.names _n79 +0 +.names lsb<0> _n76<0> _n79 _n78<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n7b +0 +.names lsb<0> _n76<0> _n7b _n7a +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names lsb<1> _n76<1> _n7a _n78<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names lsb<1> _n76<1> _n7a _n7c +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names lsb<2> _n76<2> _n7c _n78<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names lsb<2> _n76<2> _n7c _n7d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n78<0> _n78<1> _n78<2> _n7e +.def 1 +0 0 0 0 +.names _n7d _n7e _n77 +.def 0 +1 1 1 +.names _n77 _n7f +- =_n77 +# lsb = lsb + 1 +.names _n81<0> +1 +.names _n81<1> +0 +.names _n81<2> +0 +# lsb + 1 +.names _n83 +0 +.names lsb<0> _n81<0> _n83 _n82<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n85 +0 +.names lsb<0> _n81<0> _n85 _n84 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names lsb<1> _n81<1> _n84 _n82<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names lsb<1> _n81<1> _n84 _n86 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names lsb<2> _n81<2> _n86 _n82<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n82<0> lsb$_n77_n80$true<0> +- =_n82<0> +.names _n82<1> lsb$_n77_n80$true<1> +- =_n82<1> +.names _n82<2> lsb$_n77_n80$true<2> +- =_n82<2> +# if/else (lsb < 7) +.names lsb$_n77_n80$true<0> lsb<0> _n77 lsb$_n77$raw_n8b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n77_n80$true<1> lsb<1> _n77 lsb$_n77$raw_n8b<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n77_n80$true<2> lsb<2> _n77 lsb$_n77$raw_n8b<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n93<0> +1 +.names _n93<1> +0 +.names xy_lsb<0> _n93<0> _n94<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _n93<1> _n94<1> +.def 0 +0 1 1 +1 0 1 +.names _n94<0> _n94<1> _n95 +.def 1 +0 0 0 +.names _n95 _n92 +0 1 +1 0 +.names _n92 _n91 +1 1 +0 0 +# x [8 - 2 : 0] = x [8 - 1 : 1] +.names x<1> x$_n91_n96$true<0> +- =x<1> +.names x<2> x$_n91_n96$true<1> +- =x<2> +.names x<3> x$_n91_n96$true<2> +- =x<3> +.names x<4> x$_n91_n96$true<3> +- =x<4> +.names x<5> x$_n91_n96$true<4> +- =x<5> +.names x<6> x$_n91_n96$true<5> +- =x<6> +.names x<7> x$_n91_n96$true<6> +- =x<7> +.names x<7> x$_n91_n96$true<7> +- =x<7> +# x [8 - 1] = 0 +.names x$_n91_n97$true<7> +0 +.names x$_n91_n96$true<0> x$_n91_n97$true<0> +- =x$_n91_n96$true<0> +.names x$_n91_n96$true<1> x$_n91_n97$true<1> +- =x$_n91_n96$true<1> +.names x$_n91_n96$true<2> x$_n91_n97$true<2> +- =x$_n91_n96$true<2> +.names x$_n91_n96$true<3> x$_n91_n97$true<3> +- =x$_n91_n96$true<3> +.names x$_n91_n96$true<4> x$_n91_n97$true<4> +- =x$_n91_n96$true<4> +.names x$_n91_n96$true<5> x$_n91_n97$true<5> +- =x$_n91_n96$true<5> +.names x$_n91_n96$true<6> x$_n91_n97$true<6> +- =x$_n91_n96$true<6> +.names _n9a<0> +0 +.names _n9a<1> +1 +.names xy_lsb<0> _n9a<0> _n9b<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _n9a<1> _n9b<1> +.def 0 +0 1 1 +1 0 1 +.names _n9b<0> _n9b<1> _n9c +.def 1 +0 0 0 +.names _n9c _n99 +0 1 +1 0 +.names _n99 _n98 +1 1 +0 0 +# y [8 - 2 : 0] = y [8 - 1 : 1] +.names y<1> y$_n98_n9d$true<0> +- =y<1> +.names y<2> y$_n98_n9d$true<1> +- =y<2> +.names y<3> y$_n98_n9d$true<2> +- =y<3> +.names y<4> y$_n98_n9d$true<3> +- =y<4> +.names y<5> y$_n98_n9d$true<4> +- =y<5> +.names y<6> y$_n98_n9d$true<5> +- =y<6> +.names y<7> y$_n98_n9d$true<6> +- =y<7> +.names y<7> y$_n98_n9d$true<7> +- =y<7> +# y [8 - 1] = 0 +.names y$_n98_n9e$true<7> +0 +.names y$_n98_n9d$true<0> y$_n98_n9e$true<0> +- =y$_n98_n9d$true<0> +.names y$_n98_n9d$true<1> y$_n98_n9e$true<1> +- =y$_n98_n9d$true<1> +.names y$_n98_n9d$true<2> y$_n98_n9e$true<2> +- =y$_n98_n9d$true<2> +.names y$_n98_n9d$true<3> y$_n98_n9e$true<3> +- =y$_n98_n9d$true<3> +.names y$_n98_n9d$true<4> y$_n98_n9e$true<4> +- =y$_n98_n9d$true<4> +.names y$_n98_n9d$true<5> y$_n98_n9e$true<5> +- =y$_n98_n9d$true<5> +.names y$_n98_n9d$true<6> y$_n98_n9e$true<6> +- =y$_n98_n9d$true<6> +.names _na1<0> +1 +.names _na1<1> +1 +.names xy_lsb<0> _na1<0> _na2<0> +.def 0 +0 1 1 +1 0 1 +.names xy_lsb<1> _na1<1> _na2<1> +.def 0 +0 1 1 +1 0 1 +.names _na2<0> _na2<1> _na3 +.def 1 +0 0 0 +.names _na3 _na0 +0 1 +1 0 +.names _na0 _n9f +1 1 +0 0 +# x < y +.names _na6 +0 +.names x<0> y<0> _na6 _na5<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _na8 +0 +.names x<0> y<0> _na8 _na7 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _na7 _na5<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _na7 _na9 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _na9 _na5<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _na9 _naa +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _naa _na5<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _naa _nab +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _nab _na5<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _nab _nac +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _nac _na5<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _nac _nad +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _nad _na5<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _nad _nae +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _nae _na5<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<7> y<7> _nae _naf +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _na5<0> _na5<1> _na5<2> _na5<3> _na5<4> _na5<5> _na5<6> _na5<7> _nb0 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _naf _nb0 _na4 +.def 0 +1 1 1 +.names _na4 _nb1 +- =_na4 +# y [8 - 2 : 0] = diff [8 - 1 : 1] +.names diff<1> y$_na4_nb2$true<0> +- =diff<1> +.names diff<2> y$_na4_nb2$true<1> +- =diff<2> +.names diff<3> y$_na4_nb2$true<2> +- =diff<3> +.names diff<4> y$_na4_nb2$true<3> +- =diff<4> +.names diff<5> y$_na4_nb2$true<4> +- =diff<5> +.names diff<6> y$_na4_nb2$true<5> +- =diff<6> +.names diff<7> y$_na4_nb2$true<6> +- =diff<7> +.names y<7> y$_na4_nb2$true<7> +- =y<7> +# y [8 - 1] = 0 +.names y$_na4_nb3$true<7> +0 +.names y$_na4_nb2$true<0> y$_na4_nb3$true<0> +- =y$_na4_nb2$true<0> +.names y$_na4_nb2$true<1> y$_na4_nb3$true<1> +- =y$_na4_nb2$true<1> +.names y$_na4_nb2$true<2> y$_na4_nb3$true<2> +- =y$_na4_nb2$true<2> +.names y$_na4_nb2$true<3> y$_na4_nb3$true<3> +- =y$_na4_nb2$true<3> +.names y$_na4_nb2$true<4> y$_na4_nb3$true<4> +- =y$_na4_nb2$true<4> +.names y$_na4_nb2$true<5> y$_na4_nb3$true<5> +- =y$_na4_nb2$true<5> +.names y$_na4_nb2$true<6> y$_na4_nb3$true<6> +- =y$_na4_nb2$true<6> +# x [8 - 2 : 0] = diff [8 - 1 : 1] +.names diff<1> x$_na4_nb4$false<0> +- =diff<1> +.names diff<2> x$_na4_nb4$false<1> +- =diff<2> +.names diff<3> x$_na4_nb4$false<2> +- =diff<3> +.names diff<4> x$_na4_nb4$false<3> +- =diff<4> +.names diff<5> x$_na4_nb4$false<4> +- =diff<5> +.names diff<6> x$_na4_nb4$false<5> +- =diff<6> +.names diff<7> x$_na4_nb4$false<6> +- =diff<7> +.names x<7> x$_na4_nb4$false<7> +- =x<7> +# x [8 - 1] = 0 +.names x$_na4_nb5$false<7> +0 +.names x$_na4_nb4$false<0> x$_na4_nb5$false<0> +- =x$_na4_nb4$false<0> +.names x$_na4_nb4$false<1> x$_na4_nb5$false<1> +- =x$_na4_nb4$false<1> +.names x$_na4_nb4$false<2> x$_na4_nb5$false<2> +- =x$_na4_nb4$false<2> +.names x$_na4_nb4$false<3> x$_na4_nb5$false<3> +- =x$_na4_nb4$false<3> +.names x$_na4_nb4$false<4> x$_na4_nb5$false<4> +- =x$_na4_nb4$false<4> +.names x$_na4_nb4$false<5> x$_na4_nb5$false<5> +- =x$_na4_nb4$false<5> +.names x$_na4_nb4$false<6> x$_na4_nb5$false<6> +- =x$_na4_nb4$false<6> +# if/else (x < y ) +.names y$_na4_nb3$true<0> y<0> _na4 y$_na4$raw_nba<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4_nb3$true<1> y<1> _na4 y$_na4$raw_nba<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4_nb3$true<2> y<2> _na4 y$_na4$raw_nba<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4_nb3$true<3> y<3> _na4 y$_na4$raw_nba<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4_nb3$true<4> y<4> _na4 y$_na4$raw_nba<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4_nb3$true<5> y<5> _na4 y$_na4$raw_nba<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4_nb3$true<6> y<6> _na4 y$_na4$raw_nba<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4_nb3$true<7> y<7> _na4 y$_na4$raw_nba<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<0> x$_na4_nb5$false<0> _na4 x$_na4$raw_nc5<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> x$_na4_nb5$false<1> _na4 x$_na4$raw_nc5<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> x$_na4_nb5$false<2> _na4 x$_na4$raw_nc5<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> x$_na4_nb5$false<3> _na4 x$_na4$raw_nc5<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> x$_na4_nb5$false<4> _na4 x$_na4$raw_nc5<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> x$_na4_nb5$false<5> _na4 x$_na4$raw_nc5<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> x$_na4_nb5$false<6> _na4 x$_na4$raw_nc5<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> x$_na4_nb5$false<7> _na4 x$_na4$raw_nc5<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# case (xy_lsb ) +.names y$_na4$raw_nba<0> y<0> _n9f y$_n9f$raw_nd4<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4$raw_nba<1> y<1> _n9f y$_n9f$raw_nd4<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4$raw_nba<2> y<2> _n9f y$_n9f$raw_nd4<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4$raw_nba<3> y<3> _n9f y$_n9f$raw_nd4<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4$raw_nba<4> y<4> _n9f y$_n9f$raw_nd4<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4$raw_nba<5> y<5> _n9f y$_n9f$raw_nd4<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4$raw_nba<6> y<6> _n9f y$_n9f$raw_nd4<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_na4$raw_nba<7> y<7> _n9f y$_n9f$raw_nd4<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_na4$raw_nc5<0> x<0> _n9f x$_n9f$raw_nde<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_na4$raw_nc5<1> x<1> _n9f x$_n9f$raw_nde<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_na4$raw_nc5<2> x<2> _n9f x$_n9f$raw_nde<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_na4$raw_nc5<3> x<3> _n9f x$_n9f$raw_nde<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_na4$raw_nc5<4> x<4> _n9f x$_n9f$raw_nde<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_na4$raw_nc5<5> x<5> _n9f x$_n9f$raw_nde<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_na4$raw_nc5<6> x<6> _n9f x$_n9f$raw_nde<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_na4$raw_nc5<7> x<7> _n9f x$_n9f$raw_nde<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n98_n9e$true<0> y$_n9f$raw_nd4<0> _n98 y$_n98$raw_ne8<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n98_n9e$true<1> y$_n9f$raw_nd4<1> _n98 y$_n98$raw_ne8<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n98_n9e$true<2> y$_n9f$raw_nd4<2> _n98 y$_n98$raw_ne8<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n98_n9e$true<3> y$_n9f$raw_nd4<3> _n98 y$_n98$raw_ne8<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n98_n9e$true<4> y$_n9f$raw_nd4<4> _n98 y$_n98$raw_ne8<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n98_n9e$true<5> y$_n9f$raw_nd4<5> _n98 y$_n98$raw_ne8<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n98_n9e$true<6> y$_n9f$raw_nd4<6> _n98 y$_n98$raw_ne8<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n98_n9e$true<7> y$_n9f$raw_nd4<7> _n98 y$_n98$raw_ne8<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<0> x$_n9f$raw_nde<0> _n98 x$_n98$raw_nf8<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> x$_n9f$raw_nde<1> _n98 x$_n98$raw_nf8<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> x$_n9f$raw_nde<2> _n98 x$_n98$raw_nf8<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> x$_n9f$raw_nde<3> _n98 x$_n98$raw_nf8<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> x$_n9f$raw_nde<4> _n98 x$_n98$raw_nf8<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> x$_n9f$raw_nde<5> _n98 x$_n98$raw_nf8<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> x$_n9f$raw_nde<6> _n98 x$_n98$raw_nf8<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> x$_n9f$raw_nde<7> _n98 x$_n98$raw_nf8<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n91_n97$true<0> x$_n98$raw_nf8<0> _n91 x$_n91$raw_n102<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n91_n97$true<1> x$_n98$raw_nf8<1> _n91 x$_n91$raw_n102<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n91_n97$true<2> x$_n98$raw_nf8<2> _n91 x$_n91$raw_n102<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n91_n97$true<3> x$_n98$raw_nf8<3> _n91 x$_n91$raw_n102<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n91_n97$true<4> x$_n98$raw_nf8<4> _n91 x$_n91$raw_n102<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n91_n97$true<5> x$_n98$raw_nf8<5> _n91 x$_n91$raw_n102<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n91_n97$true<6> x$_n98$raw_nf8<6> _n91 x$_n91$raw_n102<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n91_n97$true<7> x$_n98$raw_nf8<7> _n91 x$_n91$raw_n102<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<0> y$_n98$raw_ne8<0> _n91 y$_n91$raw_n10f<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<1> y$_n98$raw_ne8<1> _n91 y$_n91$raw_n10f<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<2> y$_n98$raw_ne8<2> _n91 y$_n91$raw_n10f<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<3> y$_n98$raw_ne8<3> _n91 y$_n91$raw_n10f<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<4> y$_n98$raw_ne8<4> _n91 y$_n91$raw_n10f<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<5> y$_n98$raw_ne8<5> _n91 y$_n91$raw_n10f<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<6> y$_n98$raw_ne8<6> _n91 y$_n91$raw_n10f<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<7> y$_n98$raw_ne8<7> _n91 y$_n91$raw_n10f<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n77$raw_n8b<0> lsb<0> _n71 lsb$_n71$raw_n11e<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n77$raw_n8b<1> lsb<1> _n71 lsb$_n71$raw_n11e<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n77$raw_n8b<2> lsb<2> _n71 lsb$_n71$raw_n11e<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<0> y$_n91$raw_n10f<0> _n71 y$_n71$raw_n123<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<1> y$_n91$raw_n10f<1> _n71 y$_n71$raw_n123<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<2> y$_n91$raw_n10f<2> _n71 y$_n71$raw_n123<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<3> y$_n91$raw_n10f<3> _n71 y$_n71$raw_n123<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<4> y$_n91$raw_n10f<4> _n71 y$_n71$raw_n123<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<5> y$_n91$raw_n10f<5> _n71 y$_n71$raw_n123<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<6> y$_n91$raw_n10f<6> _n71 y$_n71$raw_n123<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y<7> y$_n91$raw_n10f<7> _n71 y$_n71$raw_n123<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<0> x$_n91$raw_n102<0> _n71 x$_n71$raw_n12d<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> x$_n91$raw_n102<1> _n71 x$_n71$raw_n12d<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> x$_n91$raw_n102<2> _n71 x$_n71$raw_n12d<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> x$_n91$raw_n102<3> _n71 x$_n71$raw_n12d<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> x$_n91$raw_n102<4> _n71 x$_n71$raw_n12d<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> x$_n91$raw_n102<5> _n71 x$_n71$raw_n12d<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> x$_n91$raw_n102<6> _n71 x$_n71$raw_n12d<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> x$_n91$raw_n102<7> _n71 x$_n71$raw_n12d<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names done _n136 +- =done +# o = (x < y ) ? x : y +# x < y +.names _n13a +0 +.names x<0> y<0> _n13a _n139<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n13c +0 +.names x<0> y<0> _n13c _n13b +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<1> y<1> _n13b _n139<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<1> y<1> _n13b _n13d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<2> y<2> _n13d _n139<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<2> y<2> _n13d _n13e +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<3> y<3> _n13e _n139<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<3> y<3> _n13e _n13f +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<4> y<4> _n13f _n139<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<4> y<4> _n13f _n140 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<5> y<5> _n140 _n139<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<5> y<5> _n140 _n141 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<6> y<6> _n141 _n139<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<6> y<6> _n141 _n142 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names x<7> y<7> _n142 _n139<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names x<7> y<7> _n142 _n143 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n139<0> _n139<1> _n139<2> _n139<3> _n139<4> _n139<5> _n139<6> _n139<7> _n144 +.def 1 +0 0 0 0 0 0 0 0 0 +.names _n143 _n144 _n138 +.def 0 +1 1 1 +# (x < y ) ? x : y +.names x<0> y<0> _n138 _n145<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<1> y<1> _n138 _n145<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<2> y<2> _n138 _n145<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<3> y<3> _n138 _n145<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<4> y<4> _n138 _n145<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<5> y<5> _n138 _n145<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<6> y<6> _n138 _n145<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x<7> y<7> _n138 _n145<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n145<0> o$done_n137$true<0> +- =_n145<0> +.names _n145<1> o$done_n137$true<1> +- =_n145<1> +.names _n145<2> o$done_n137$true<2> +- =_n145<2> +.names _n145<3> o$done_n137$true<3> +- =_n145<3> +.names _n145<4> o$done_n137$true<4> +- =_n145<4> +.names _n145<5> o$done_n137$true<5> +- =_n145<5> +.names _n145<6> o$done_n137$true<6> +- =_n145<6> +.names _n145<7> o$done_n137$true<7> +- =_n145<7> +# if/else (done ) +.names o$done_n137$true<0> o<0> done o$done$raw_n150<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n137$true<1> o<1> done o$done$raw_n150<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n137$true<2> o<2> done o$done$raw_n150<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n137$true<3> o<3> done o$done$raw_n150<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n137$true<4> o<4> done o$done$raw_n150<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n137$true<5> o<5> done o$done$raw_n150<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n137$true<6> o<6> done o$done$raw_n150<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o$done_n137$true<7> o<7> done o$done$raw_n150<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (busy & ~done ) +.names y$_n71$raw_n123<0> y<0> _n67 y$_n67$raw_n161<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n71$raw_n123<1> y<1> _n67 y$_n67$raw_n161<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n71$raw_n123<2> y<2> _n67 y$_n67$raw_n161<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n71$raw_n123<3> y<3> _n67 y$_n67$raw_n161<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n71$raw_n123<4> y<4> _n67 y$_n67$raw_n161<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n71$raw_n123<5> y<5> _n67 y$_n67$raw_n161<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n71$raw_n123<6> y<6> _n67 y$_n67$raw_n161<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$_n71$raw_n123<7> y<7> _n67 y$_n67$raw_n161<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n71$raw_n11e<0> lsb<0> _n67 lsb$_n67$raw_n16a<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n71$raw_n11e<1> lsb<1> _n67 lsb$_n67$raw_n16a<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$_n71$raw_n11e<2> lsb<2> _n67 lsb$_n67$raw_n16a<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cpt$_n67_n69$true<0> cpt<0> _n67 cpt$_n67$raw_n16e<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cpt$_n67_n69$true<1> cpt<1> _n67 cpt$_n67$raw_n16e<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cpt$_n67_n69$true<2> cpt<2> _n67 cpt$_n67$raw_n16e<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cpt$_n67_n69$true<3> cpt<3> _n67 cpt$_n67$raw_n16e<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n71$raw_n12d<0> x<0> _n67 x$_n67$raw_n173<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n71$raw_n12d<1> x<1> _n67 x$_n67$raw_n173<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n71$raw_n12d<2> x<2> _n67 x$_n67$raw_n173<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n71$raw_n12d<3> x<3> _n67 x$_n67$raw_n173<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n71$raw_n12d<4> x<4> _n67 x$_n67$raw_n173<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n71$raw_n12d<5> x<5> _n67 x$_n67$raw_n173<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n71$raw_n12d<6> x<6> _n67 x$_n67$raw_n173<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$_n71$raw_n12d<7> x<7> _n67 x$_n67$raw_n173<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<0> o$done$raw_n150<0> _n67 o$_n67$raw_n17c<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<1> o$done$raw_n150<1> _n67 o$_n67$raw_n17c<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<2> o$done$raw_n150<2> _n67 o$_n67$raw_n17c<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<3> o$done$raw_n150<3> _n67 o$_n67$raw_n17c<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<4> o$done$raw_n150<4> _n67 o$_n67$raw_n17c<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<5> o$done$raw_n150<5> _n67 o$_n67$raw_n17c<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<6> o$done$raw_n150<6> _n67 o$_n67$raw_n17c<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<7> o$done$raw_n150<7> _n67 o$_n67$raw_n17c<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (load ) +.names y$load_n63$true<0> y$_n67$raw_n161<0> load y$load$raw_n189<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n63$true<1> y$_n67$raw_n161<1> load y$load$raw_n189<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n63$true<2> y$_n67$raw_n161<2> load y$load$raw_n189<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n63$true<3> y$_n67$raw_n161<3> load y$load$raw_n189<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n63$true<4> y$_n67$raw_n161<4> load y$load$raw_n189<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n63$true<5> y$_n67$raw_n161<5> load y$load$raw_n189<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n63$true<6> y$_n67$raw_n161<6> load y$load$raw_n189<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names y$load_n63$true<7> y$_n67$raw_n161<7> load y$load$raw_n189<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$load_n64$true<0> lsb$_n67$raw_n16a<0> load lsb$load$raw_n192<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$load_n64$true<1> lsb$_n67$raw_n16a<1> load lsb$load$raw_n192<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names lsb$load_n64$true<2> lsb$_n67$raw_n16a<2> load lsb$load$raw_n192<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cpt$load_n65$true<0> cpt$_n67$raw_n16e<0> load cpt$load$raw_n196<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cpt$load_n65$true<1> cpt$_n67$raw_n16e<1> load cpt$load$raw_n196<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cpt$load_n65$true<2> cpt$_n67$raw_n16e<2> load cpt$load$raw_n196<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names cpt$load_n65$true<3> cpt$_n67$raw_n16e<3> load cpt$load$raw_n196<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n62$true<0> x$_n67$raw_n173<0> load x$load$raw_n19b<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n62$true<1> x$_n67$raw_n173<1> load x$load$raw_n19b<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n62$true<2> x$_n67$raw_n173<2> load x$load$raw_n19b<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n62$true<3> x$_n67$raw_n173<3> load x$load$raw_n19b<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n62$true<4> x$_n67$raw_n173<4> load x$load$raw_n19b<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n62$true<5> x$_n67$raw_n173<5> load x$load$raw_n19b<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n62$true<6> x$_n67$raw_n173<6> load x$load$raw_n19b<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names x$load_n62$true<7> x$_n67$raw_n173<7> load x$load$raw_n19b<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<0> o$_n67$raw_n17c<0> load o$load$raw_n1a9<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<1> o$_n67$raw_n17c<1> load o$load$raw_n1a9<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<2> o$_n67$raw_n17c<2> load o$load$raw_n1a9<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<3> o$_n67$raw_n17c<3> load o$load$raw_n1a9<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<4> o$_n67$raw_n17c<4> load o$load$raw_n1a9<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<5> o$_n67$raw_n17c<5> load o$load$raw_n1a9<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<6> o$_n67$raw_n17c<6> load o$load$raw_n1a9<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names o<7> o$_n67$raw_n17c<7> load o$load$raw_n1a9<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names busy _n1b5 +0 1 +1 0 +.names _n1b5 _n1b6 +- =_n1b5 +.names start _n1b7 +- =start +# busy = 1 +.names busy$start_n1b8$true +1 +# if/else (start ) +.names busy$start_n1b8$true busy start busy$start$raw_n1bb +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names done _n1bd +- =done +# busy = 0 +.names busy$done_n1be$true +0 +# if/else (done ) +.names busy$done_n1be$true busy done busy$done$raw_n1c1 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (~busy ) +.names busy$start$raw_n1bb busy$done$raw_n1c1 _n1b5 busy$_n1b5$raw_n1c4 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names _n61 _n68 _n71 _n91 _n98 _n9f _nb1 _n1c8 +.def 0 + 1 - - - - - - 1 + 0 1 0 0 1 - - 1 + 0 1 0 0 1 - - 1 + 0 1 0 0 0 1 1 1 + 0 1 0 0 0 1 1 1 +.names _n1c8 y$load$raw_n189<0> y$load$raw_n189<1> y$load$raw_n189<2> y$load$raw_n189<3> y$load$raw_n189<4> y$load$raw_n189<5> y$load$raw_n189<6> y$load$raw_n189<7> y<0> y<1> y<2> y<3> y<4> y<5> y<6> y<7> -> _n1c9<0> _n1c9<1> _n1c9<2> _n1c9<3> _n1c9<4> _n1c9<5> _n1c9<6> _n1c9<7> +1 - - - - - - - - - - - - - - - - =y$load$raw_n189<0> =y$load$raw_n189<1> =y$load$raw_n189<2> =y$load$raw_n189<3> =y$load$raw_n189<4> =y$load$raw_n189<5> =y$load$raw_n189<6> =y$load$raw_n189<7> +0 - - - - - - - - - - - - - - - - =y<0> =y<1> =y<2> =y<3> =y<4> =y<5> =y<6> =y<7> +.names _n61 _n68 _n136 _n1ca +.def 0 + 0 0 1 1 +.names _n1ca o$load$raw_n1a9<0> o$load$raw_n1a9<1> o$load$raw_n1a9<2> o$load$raw_n1a9<3> o$load$raw_n1a9<4> o$load$raw_n1a9<5> o$load$raw_n1a9<6> o$load$raw_n1a9<7> o<0> o<1> o<2> o<3> o<4> o<5> o<6> o<7> -> _n1cb<0> _n1cb<1> _n1cb<2> _n1cb<3> _n1cb<4> _n1cb<5> _n1cb<6> _n1cb<7> +1 - - - - - - - - - - - - - - - - =o$load$raw_n1a9<0> =o$load$raw_n1a9<1> =o$load$raw_n1a9<2> =o$load$raw_n1a9<3> =o$load$raw_n1a9<4> =o$load$raw_n1a9<5> =o$load$raw_n1a9<6> =o$load$raw_n1a9<7> +0 - - - - - - - - - - - - - - - - =o<0> =o<1> =o<2> =o<3> =o<4> =o<5> =o<6> =o<7> +.names load$raw_n58 load +0 0 +1 1 +.names _n61 _n68 _n71 _n7f _n1cc +.def 0 + 1 - - - 1 + 0 1 1 1 1 +.names _n1cc lsb$load$raw_n192<0> lsb$load$raw_n192<1> lsb$load$raw_n192<2> lsb<0> lsb<1> lsb<2> -> _n1cd<0> _n1cd<1> _n1cd<2> +1 - - - - - - =lsb$load$raw_n192<0> =lsb$load$raw_n192<1> =lsb$load$raw_n192<2> +0 - - - - - - =lsb<0> =lsb<1> =lsb<2> +.names _n1b6 _n1b7 _n1bd _n1ce +.def 0 + 1 1 - 1 + 0 - 1 1 +.names _n1ce busy$_n1b5$raw_n1c4 busy _n1cf +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names xy_lsb$raw_nf<0> xy_lsb<0> +- =xy_lsb$raw_nf<0> +.names xy_lsb$raw_nc<1> xy_lsb<1> +- =xy_lsb$raw_nc<1> +.names done$raw_n3d done +0 0 +1 1 +.names diff$raw_n12<0> diff<0> +- =diff$raw_n12<0> +.names diff$raw_n12<1> diff<1> +- =diff$raw_n12<1> +.names diff$raw_n12<2> diff<2> +- =diff$raw_n12<2> +.names diff$raw_n12<3> diff<3> +- =diff$raw_n12<3> +.names diff$raw_n12<4> diff<4> +- =diff$raw_n12<4> +.names diff$raw_n12<5> diff<5> +- =diff$raw_n12<5> +.names diff$raw_n12<6> diff<6> +- =diff$raw_n12<6> +.names diff$raw_n12<7> diff<7> +- =diff$raw_n12<7> +.names _n61 _n68 _n1d0 +.def 0 + 1 - 1 + 0 1 1 +.names _n1d0 cpt$load$raw_n196<0> cpt$load$raw_n196<1> cpt$load$raw_n196<2> cpt$load$raw_n196<3> cpt<0> cpt<1> cpt<2> cpt<3> -> _n1d1<0> _n1d1<1> _n1d1<2> _n1d1<3> +1 - - - - - - - - =cpt$load$raw_n196<0> =cpt$load$raw_n196<1> =cpt$load$raw_n196<2> =cpt$load$raw_n196<3> +0 - - - - - - - - =cpt<0> =cpt<1> =cpt<2> =cpt<3> +.names _n61 _n68 _n71 _n91 _n98 _n9f _nb1 _n1d2 +.def 0 + 1 - - - - - - 1 + 0 1 0 1 - - - 1 + 0 1 0 1 - - - 1 + 0 1 0 0 0 1 0 1 + 0 1 0 0 0 1 0 1 +.names _n1d2 x$load$raw_n19b<0> x$load$raw_n19b<1> x$load$raw_n19b<2> x$load$raw_n19b<3> x$load$raw_n19b<4> x$load$raw_n19b<5> x$load$raw_n19b<6> x$load$raw_n19b<7> x<0> x<1> x<2> x<3> x<4> x<5> x<6> x<7> -> _n1d3<0> _n1d3<1> _n1d3<2> _n1d3<3> _n1d3<4> _n1d3<5> _n1d3<6> _n1d3<7> +1 - - - - - - - - - - - - - - - - =x$load$raw_n19b<0> =x$load$raw_n19b<1> =x$load$raw_n19b<2> =x$load$raw_n19b<3> =x$load$raw_n19b<4> =x$load$raw_n19b<5> =x$load$raw_n19b<6> =x$load$raw_n19b<7> +0 - - - - - - - - - - - - - - - - =x<0> =x<1> =x<2> =x<3> =x<4> =x<5> =x<6> =x<7> +# non-blocking assignments +# latches +.r y$raw_n5d<0> y<0> +.def 0 +1 1 +.r y$raw_n5d<1> y<1> +.def 0 +1 1 +.r y$raw_n5d<2> y<2> +.def 0 +1 1 +.r y$raw_n5d<3> y<3> +.def 0 +1 1 +.r y$raw_n5d<4> y<4> +.def 0 +1 1 +.r y$raw_n5d<5> y<5> +.def 0 +1 1 +.r y$raw_n5d<6> y<6> +.def 0 +1 1 +.r y$raw_n5d<7> y<7> +.def 0 +1 1 +.latch _n1c9<0> y<0> +.latch _n1c9<1> y<1> +.latch _n1c9<2> y<2> +.latch _n1c9<3> y<3> +.latch _n1c9<4> y<4> +.latch _n1c9<5> y<5> +.latch _n1c9<6> y<6> +.latch _n1c9<7> y<7> +.r o$raw_n5e<0> o<0> +.def 0 +1 1 +.r o$raw_n5e<1> o<1> +.def 0 +1 1 +.r o$raw_n5e<2> o<2> +.def 0 +1 1 +.r o$raw_n5e<3> o<3> +.def 0 +1 1 +.r o$raw_n5e<4> o<4> +.def 0 +1 1 +.r o$raw_n5e<5> o<5> +.def 0 +1 1 +.r o$raw_n5e<6> o<6> +.def 0 +1 1 +.r o$raw_n5e<7> o<7> +.def 0 +1 1 +.latch _n1cb<0> o<0> +.latch _n1cb<1> o<1> +.latch _n1cb<2> o<2> +.latch _n1cb<3> o<3> +.latch _n1cb<4> o<4> +.latch _n1cb<5> o<5> +.latch _n1cb<6> o<6> +.latch _n1cb<7> o<7> +.r busy$raw_n5b busy +0 0 +1 1 +.latch _n1cf busy +.r lsb$raw_n5f<0> lsb<0> +.def 0 +1 1 +.r lsb$raw_n5f<1> lsb<1> +.def 0 +1 1 +.r lsb$raw_n5f<2> lsb<2> +.def 0 +1 1 +.latch _n1cd<0> lsb<0> +.latch _n1cd<1> lsb<1> +.latch _n1cd<2> lsb<2> +.r cpt$raw_n60<0> cpt<0> +.def 0 +1 1 +.r cpt$raw_n60<1> cpt<1> +.def 0 +1 1 +.r cpt$raw_n60<2> cpt<2> +.def 0 +1 1 +.r cpt$raw_n60<3> cpt<3> +.def 0 +1 1 +.latch _n1d1<0> cpt<0> +.latch _n1d1<1> cpt<1> +.latch _n1d1<2> cpt<2> +.latch _n1d1<3> cpt<3> +.r x$raw_n5c<0> x<0> +.def 0 +1 1 +.r x$raw_n5c<1> x<1> +.def 0 +1 1 +.r x$raw_n5c<2> x<2> +.def 0 +1 1 +.r x$raw_n5c<3> x<3> +.def 0 +1 1 +.r x$raw_n5c<4> x<4> +.def 0 +1 1 +.r x$raw_n5c<5> x<5> +.def 0 +1 1 +.r x$raw_n5c<6> x<6> +.def 0 +1 1 +.r x$raw_n5c<7> x<7> +.def 0 +1 1 +.latch _n1d3<0> x<0> +.latch _n1d3<1> x<1> +.latch _n1d3<2> x<2> +.latch _n1d3<3> x<3> +.latch _n1d3<4> x<4> +.latch _n1d3<5> x<5> +.latch _n1d3<6> x<6> +.latch _n1d3<7> x<7> +# quasi-continuous assignment +.end + + +.model select +# I/O ports +.inputs z<0> z<1> z<2> z<3> z<4> z<5> z<6> z<7> +.inputs lsb<0> lsb<1> lsb<2> +.outputs select<0> +.names _n1d5<0> +0 +.names _n1d5<1> +0 +.names _n1d5<2> +0 +# lsb == 'b000 +.names lsb<0> _n1d5<0> _n1d6<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1d5<1> _n1d6<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1d5<2> _n1d6<2> +.def 0 +0 1 1 +1 0 1 +.names _n1d6<0> _n1d6<1> _n1d6<2> _n1d7 +.def 1 +0 0 0 0 +.names _n1d7 _n1d4 +0 1 +1 0 +.names _n1d4 _n1d8 +- =_n1d4 +# select = z [0] +.names z<0> select$_n1d4_n1d9$true<0> +- =z<0> +.names _n1db<0> +1 +.names _n1db<1> +0 +.names _n1db<2> +0 +# lsb == 'b001 +.names lsb<0> _n1db<0> _n1dc<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1db<1> _n1dc<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1db<2> _n1dc<2> +.def 0 +0 1 1 +1 0 1 +.names _n1dc<0> _n1dc<1> _n1dc<2> _n1dd +.def 1 +0 0 0 0 +.names _n1dd _n1da +0 1 +1 0 +.names _n1da _n1de +- =_n1da +# select = z [1] +.names z<1> select$_n1da_n1df$true<0> +- =z<1> +.names _n1e1<0> +0 +.names _n1e1<1> +1 +.names _n1e1<2> +0 +# lsb == 'b010 +.names lsb<0> _n1e1<0> _n1e2<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1e1<1> _n1e2<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1e1<2> _n1e2<2> +.def 0 +0 1 1 +1 0 1 +.names _n1e2<0> _n1e2<1> _n1e2<2> _n1e3 +.def 1 +0 0 0 0 +.names _n1e3 _n1e0 +0 1 +1 0 +.names _n1e0 _n1e4 +- =_n1e0 +# select = z [2] +.names z<2> select$_n1e0_n1e5$true<0> +- =z<2> +.names _n1e7<0> +1 +.names _n1e7<1> +1 +.names _n1e7<2> +0 +# lsb == 'b011 +.names lsb<0> _n1e7<0> _n1e8<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1e7<1> _n1e8<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1e7<2> _n1e8<2> +.def 0 +0 1 1 +1 0 1 +.names _n1e8<0> _n1e8<1> _n1e8<2> _n1e9 +.def 1 +0 0 0 0 +.names _n1e9 _n1e6 +0 1 +1 0 +.names _n1e6 _n1ea +- =_n1e6 +# select = z [3] +.names z<3> select$_n1e6_n1eb$true<0> +- =z<3> +.names _n1ed<0> +0 +.names _n1ed<1> +0 +.names _n1ed<2> +1 +# lsb == 'b100 +.names lsb<0> _n1ed<0> _n1ee<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1ed<1> _n1ee<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1ed<2> _n1ee<2> +.def 0 +0 1 1 +1 0 1 +.names _n1ee<0> _n1ee<1> _n1ee<2> _n1ef +.def 1 +0 0 0 0 +.names _n1ef _n1ec +0 1 +1 0 +.names _n1ec _n1f0 +- =_n1ec +# select = z [4] +.names z<4> select$_n1ec_n1f1$true<0> +- =z<4> +.names _n1f3<0> +1 +.names _n1f3<1> +0 +.names _n1f3<2> +1 +# lsb == 'b101 +.names lsb<0> _n1f3<0> _n1f4<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1f3<1> _n1f4<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1f3<2> _n1f4<2> +.def 0 +0 1 1 +1 0 1 +.names _n1f4<0> _n1f4<1> _n1f4<2> _n1f5 +.def 1 +0 0 0 0 +.names _n1f5 _n1f2 +0 1 +1 0 +.names _n1f2 _n1f6 +- =_n1f2 +# select = z [5] +.names z<5> select$_n1f2_n1f7$true<0> +- =z<5> +.names _n1f9<0> +0 +.names _n1f9<1> +1 +.names _n1f9<2> +1 +# lsb == 'b110 +.names lsb<0> _n1f9<0> _n1fa<0> +.def 0 +0 1 1 +1 0 1 +.names lsb<1> _n1f9<1> _n1fa<1> +.def 0 +0 1 1 +1 0 1 +.names lsb<2> _n1f9<2> _n1fa<2> +.def 0 +0 1 1 +1 0 1 +.names _n1fa<0> _n1fa<1> _n1fa<2> _n1fb +.def 1 +0 0 0 0 +.names _n1fb _n1f8 +0 1 +1 0 +.names _n1f8 _n1fc +- =_n1f8 +# select = z [6] +.names z<6> select$_n1f8_n1fd$true<0> +- =z<6> +# select = z [7] +.names z<7> select$_n1f8_n1fe$false<0> +- =z<7> +# if/else (lsb == 'b110) +.names select$_n1f8_n1fd$true<0> select$_n1f8_n1fe$false<0> _n1f8 select$_n1f8$raw_n200<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b101) +.names select$_n1f2_n1f7$true<0> select$_n1f8$raw_n200<0> _n1f2 select$_n1f2$raw_n205<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b100) +.names select$_n1ec_n1f1$true<0> select$_n1f2$raw_n205<0> _n1ec select$_n1ec$raw_n20a<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b011) +.names select$_n1e6_n1eb$true<0> select$_n1ec$raw_n20a<0> _n1e6 select$_n1e6$raw_n20f<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b010) +.names select$_n1e0_n1e5$true<0> select$_n1e6$raw_n20f<0> _n1e0 select$_n1e0$raw_n214<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b001) +.names select$_n1da_n1df$true<0> select$_n1e0$raw_n214<0> _n1da select$_n1da$raw_n219<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (lsb == 'b000) +.names select$_n1d4_n1d9$true<0> select$_n1da$raw_n219<0> _n1d4 select$_n1d4$raw_n21e<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names select$_n1d4$raw_n21e<0> select<0> +- =select$_n1d4$raw_n21e<0> +.end + + Index: vis_dev/vis-2.1/examples/gcd/gcd3.ord =================================================================== --- vis_dev/vis-2.1/examples/gcd/gcd3.ord (revision 11) +++ vis_dev/vis-2.1/examples/gcd/gcd3.ord (revision 11) @@ -0,0 +1,120 @@ +# vis release 2.1 (compiled 17-Nov-08 at 8:20 PM) +# network name: testGcd +# generated: Tue Nov 18 11:33:18 2008 +# +# name type mddId vals levs +x<5> primary-input 10 2 (0) +x<6> primary-input 9 2 (1) +x<4> primary-input 11 2 (2) +x<7> primary-input 8 2 (3) +x<2> primary-input 13 2 (4) +x<3> primary-input 12 2 (5) +x<1> primary-input 14 2 (6) +y<3> primary-input 4 2 (7) +x<0> primary-input 15 2 (8) +y<0> primary-input 7 2 (9) +y<1> primary-input 6 2 (10) +y<6> primary-input 1 2 (11) +y<5> primary-input 2 2 (12) +y<2> primary-input 5 2 (13) +y<4> primary-input 3 2 (14) +y<7> primary-input 0 2 (15) +s primary-input 16 2 (16) +busy$NS shadow 66 2 (17) +busy latch 65 2 (18) +o<6> latch 69 2 (19) +o<6>$NS shadow 70 2 (20) +o<7> latch 67 2 (21) +o<7>$NS shadow 68 2 (22) +start$NS shadow 82 2 (23) +start latch 81 2 (24) +b<0>$NS shadow 114 2 (25) +b<0> latch 113 2 (26) +a<6>$NS shadow 86 2 (27) +a<6> latch 85 2 (28) +a<4>$NS shadow 90 2 (29) +a<4> latch 89 2 (30) +b<7>$NS shadow 100 2 (31) +b<7> latch 99 2 (32) +b<6>$NS shadow 102 2 (33) +b<6> latch 101 2 (34) +b<5>$NS shadow 104 2 (35) +b<5> latch 103 2 (36) +b<4>$NS shadow 106 2 (37) +b<4> latch 105 2 (38) +b<3>$NS shadow 108 2 (39) +b<3> latch 107 2 (40) +a<7>$NS shadow 84 2 (41) +a<7> latch 83 2 (42) +b<1>$NS shadow 112 2 (43) +b<1> latch 111 2 (44) +b<2>$NS shadow 110 2 (45) +b<2> latch 109 2 (46) +a<5>$NS shadow 88 2 (47) +a<5> latch 87 2 (48) +a<1>$NS shadow 96 2 (49) +a<1> latch 95 2 (50) +a<3>$NS shadow 92 2 (51) +a<3> latch 91 2 (52) +g.x<6>$NS shadow 42 2 (53) +g.x<6> latch 41 2 (54) +g.x<7>$NS shadow 44 2 (55) +g.x<7> latch 43 2 (56) +g.y<7>$NS shadow 26 2 (57) +g.y<7> latch 25 2 (58) +g.y<6>$NS shadow 24 2 (59) +g.y<6> latch 23 2 (60) +g.lsb<2>$NS shadow 22 2 (61) +g.lsb<2> latch 21 2 (62) +o<5> latch 71 2 (63) +o<5>$NS shadow 72 2 (64) +g.lsb<1> latch 19 2 (65) +g.lsb<1>$NS shadow 20 2 (66) +g.y<5>$NS shadow 30 2 (67) +g.y<5> latch 29 2 (68) +g.x<5>$NS shadow 46 2 (69) +g.x<5> latch 45 2 (70) +o<4> latch 73 2 (71) +o<4>$NS shadow 74 2 (72) +g.x<4>$NS shadow 48 2 (73) +g.x<4> latch 47 2 (74) +g.y<4>$NS shadow 32 2 (75) +g.y<4> latch 31 2 (76) +o<3> latch 75 2 (77) +o<3>$NS shadow 76 2 (78) +g.lsb<0>$NS shadow 18 2 (79) +g.lsb<0> latch 17 2 (80) +g.y<3>$NS shadow 34 2 (81) +g.y<3> latch 33 2 (82) +g.x<3> latch 49 2 (83) +g.x<3>$NS shadow 50 2 (84) +a<2>$NS shadow 94 2 (85) +a<2> latch 93 2 (86) +o<2> latch 77 2 (87) +o<2>$NS shadow 78 2 (88) +g.x<2> latch 51 2 (89) +g.x<2>$NS shadow 52 2 (90) +g.y<2>$NS shadow 36 2 (91) +g.y<2> latch 35 2 (92) +o<1> latch 79 2 (93) +o<1>$NS shadow 80 2 (94) +g.y<1>$NS shadow 38 2 (95) +g.y<1> latch 37 2 (96) +g.x<1> latch 53 2 (97) +g.x<1>$NS shadow 54 2 (98) +a<0>$NS shadow 98 2 (99) +a<0> latch 97 2 (100) +g.x<0> latch 55 2 (101) +g.x<0>$NS shadow 56 2 (102) +g.y<0>$NS shadow 40 2 (103) +g.y<0> latch 39 2 (104) +o<0>$NS shadow 28 2 (105) +o<0> latch 27 2 (106) +g.cpt<3>$NS shadow 64 2 (107) +g.cpt<3> latch 63 2 (108) +g.cpt<0> latch 57 2 (109) +g.cpt<0>$NS shadow 58 2 (110) +g.cpt<2> latch 61 2 (111) +g.cpt<2>$NS shadow 62 2 (112) +g.cpt<1>$NS shadow 60 2 (113) +g.cpt<1> latch 59 2 (114) Index: vis_dev/vis-2.1/examples/gcd/gcd3.v =================================================================== --- vis_dev/vis-2.1/examples/gcd/gcd3.v (revision 11) +++ vis_dev/vis-2.1/examples/gcd/gcd3.v (revision 11) @@ -0,0 +1,151 @@ +// Testbench for the gcd circuit. +module testGcd(clock,x,y,s); + parameter N = 8; + parameter logN = 3; + input clock; + input [N-1:0] x,y; + input s; + reg [N-1:0] a,b; + reg start; + wire busy; + wire [N-1:0] o; + + // Unit under test. + gcd #(N,logN) g(clock,start,a,b,busy,o); + + initial begin + a = 0; + b = 0; + start = 0; + end + + always @ (posedge clock) begin + a = x; + b = y; + start = s; + end // always @ (posedge clock) + +endmodule // testGcd + +// GCD circuit for unsigned N-bit numbers +// a[0], b[0], and o[0] are the least significant bits +// +// Author: Fabio Somenzi +module gcd(clock,start,a,b,busy,o); + parameter N = 8; + parameter logN = 3; + input clock; + input start; + input [N-1:0] a; + input [N-1:0] b; + output busy; + output [N-1:0] o; + + reg [logN-1:0] lsb; + reg [N-1:0] x; + reg [N-1:0] y; + wire done; + wire load; + reg busy; + reg [N-1:0] o; + reg [logN:0] cpt; + wire [1:0] xy_lsb; + wire [N-1:0] diff; + + function select; + input [N-1:0] z; + input [logN-1:0] lsb; + begin: _select + if (lsb == 3'd0) + select = z[0]; + else if (lsb == 3'd1) + select = z[1]; + else if (lsb == 3'd2) + select = z[2]; + else if (lsb == 3'd3) + select = z[3]; + else if (lsb == 3'd4) + select = z[4]; + else if (lsb == 3'd5) + select = z[5]; + else if (lsb == 3'd6) + select = z[6]; + else + select = z[7]; + end // block: _select + endfunction // select + + assign xy_lsb[1] = select(x,lsb); + assign xy_lsb[0] = select(y,lsb); + assign diff = x < y ? y - x : x - y; + assign done = ((x == y) | (x == 0) | (y == 0) | (cpt > 13)) & busy; + assign load = start & ~busy; + + initial begin + busy = 0; + x = 0; + y = 0; + o = 0; + lsb = 0; + cpt=0; + end // initial begin + + // Data path. + always @(posedge clock) begin + if (load) begin + x = a; + y = b; + lsb = 0; + cpt=0; + end // if (load) + else if (busy & ~done) begin + cpt = cpt+1 ; + case (xy_lsb) + 2'b00: + if (lsb<7) begin + lsb = lsb + 1; + end + 2'b01: + begin + x[N-2:0] = x[N-1:1]; + x[N-1] = 0; + end + 2'b10: + begin + y[N-2:0] = y[N-1:1]; + y[N-1] = 0; + end + 2'b11: begin + if (x < y) begin + y[N-2:0] = diff[N-1:1]; + y[N-1] = 0; + end // if (x < y) + else begin + x[N-2:0] = diff[N-1:1]; + x[N-1] = 0; + end // else: !if(x < y) + end // case: 2b'11 + endcase // case (xy_lsb) + end // if (~done) + else if (done) begin + o = (x < y) ? x : y; + end // else: !if(~done) + end // always @ (posedge clock) + + + + // Controller. + always @(posedge clock) begin + if (~busy) begin + if (start) begin + busy = 1; + end // if (start) + end // if (~busy) + else begin + if (done) begin + busy = 0; + end + end // else: !if(~busy) + end // always @ (posedge clock) + +endmodule // gcd Index: vis_dev/vis-2.1/examples/gcd/protected.reg =================================================================== --- vis_dev/vis-2.1/examples/gcd/protected.reg (revision 11) +++ vis_dev/vis-2.1/examples/gcd/protected.reg (revision 11) @@ -0,0 +1,1 @@ +g.lsb* Index: vis_dev/vis-2.1/examples/gcd/protected3.reg =================================================================== --- vis_dev/vis-2.1/examples/gcd/protected3.reg (revision 11) +++ vis_dev/vis-2.1/examples/gcd/protected3.reg (revision 11) @@ -0,0 +1,1 @@ +g.cpt* Index: vis_dev/vis-2.1/examples/gcd/required.ctl =================================================================== --- vis_dev/vis-2.1/examples/gcd/required.ctl (revision 11) +++ vis_dev/vis-2.1/examples/gcd/required.ctl (revision 11) @@ -0,0 +1,1 @@ +(TRUE); Index: vis_dev/vis-2.1/examples/gigamax/README =================================================================== --- vis_dev/vis-2.1/examples/gigamax/README (revision 11) +++ vis_dev/vis-2.1/examples/gigamax/README (revision 11) @@ -0,0 +1,8 @@ +Gigamax multiprocessor (Translated from gigamax.smv of SMV) + +gigamax.v + gigamax verilog source +gigamax.ctl + gigamax ctl formulas +gigamax.mv + blif-mv for gigamax, target code of vl2mv from gigamax.v Index: vis_dev/vis-2.1/examples/gigamax/affalse =================================================================== --- vis_dev/vis-2.1/examples/gigamax/affalse (revision 11) +++ vis_dev/vis-2.1/examples/gigamax/affalse (revision 11) @@ -0,0 +1,1 @@ +AF FALSE; Index: vis_dev/vis-2.1/examples/gigamax/agtrue =================================================================== --- vis_dev/vis-2.1/examples/gigamax/agtrue (revision 11) +++ vis_dev/vis-2.1/examples/gigamax/agtrue (revision 11) @@ -0,0 +1,2 @@ +AG(TRUE); +#AG( (.s.exit1=0) + (.s.exit1=1) ); Index: vis_dev/vis-2.1/examples/gigamax/check_result =================================================================== --- vis_dev/vis-2.1/examples/gigamax/check_result (revision 11) +++ vis_dev/vis-2.1/examples/gigamax/check_result (revision 11) @@ -0,0 +1,13 @@ +FSM depth = 7 +reachable states = 122 +# LE: language is not empty +# MC: formula failed --- AF(FALSE) +# MC: formula passed --- AG(EF(p0.Cdevice.readable=1)) +# MC: formula passed --- AG(EF(p0.Cdevice.writable=1)) +# MC: formula passed --- AG(EF(p1.Cdevice.readable=1)) +# MC: formula passed --- AG(EF(p1.Cdevice.writable=1)) +# MC: formula passed --- AG(EF(p2.Cdevice.readable=1)) +# MC: formula passed --- AG(EF(p2.Cdevice.writable=1)) +# MC: formula passed --- AG((p0.Cdevice.writable=0 + p1.Cdevice.writable=0)) +# MC: formula passed --- AG((p1.Cdevice.writable=0 + p2.Cdevice.writable=0)) +# MC: formula passed --- AG((p0.Cdevice.writable=0 + p2.Cdevice.writable=0)) Index: vis_dev/vis-2.1/examples/gigamax/check_script =================================================================== --- vis_dev/vis-2.1/examples/gigamax/check_script (revision 11) +++ vis_dev/vis-2.1/examples/gigamax/check_script (revision 11) @@ -0,0 +1,9 @@ +read_blif_mv gigamax.mv +init_verify +compute_reach -v 1 +print_fairness +lang_empty -d 0 +model_check -d 0 affalse +model_check -d 0 gigamax.ctl +time +quit -s Index: vis_dev/vis-2.1/examples/gigamax/gigamax.ctl =================================================================== --- vis_dev/vis-2.1/examples/gigamax/gigamax.ctl (revision 11) +++ vis_dev/vis-2.1/examples/gigamax/gigamax.ctl (revision 11) @@ -0,0 +1,9 @@ +AG EF (p0.Cdevice.readable=1) ; +AG EF (p0.Cdevice.writable=1) ; +AG EF (p1.Cdevice.readable=1) ; +AG EF (p1.Cdevice.writable=1) ; +AG EF (p2.Cdevice.readable=1) ; +AG EF (p2.Cdevice.writable=1) ; +AG ((p0.Cdevice.writable=0) + (p1.Cdevice.writable=0)) ; +AG ((p1.Cdevice.writable=0) + (p2.Cdevice.writable=0)) ; +AG ((p0.Cdevice.writable=0) + (p2.Cdevice.writable=0)) ; Index: vis_dev/vis-2.1/examples/gigamax/gigamax.mv =================================================================== --- vis_dev/vis-2.1/examples/gigamax/gigamax.mv (revision 11) +++ vis_dev/vis-2.1/examples/gigamax/gigamax.mv (revision 11) @@ -0,0 +1,1396 @@ +# vl2mv gigamax.v +# version: 0.2 +# date: 11:15:57 12/11/95 (PST) +.model main +# I/O ports + +.mv p2_cmd 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv m_cmd 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv p0_cmd 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv nond_CMD 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv CMD 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv p1_cmd 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.subckt processor p0 CMD=CMD master=p0_master REPLY_OWNED=REPLY_OWNED REPLY_WAITING=REPLY_WAITING REPLY_STALL=REPLY_STALL cmd=p0_cmd reply_owned=p0_reply_owned reply_waiting=p0_reply_waiting reply_stall=p0_reply_stall +.subckt processor p1 CMD=CMD master=p1_master REPLY_OWNED=REPLY_OWNED REPLY_WAITING=REPLY_WAITING REPLY_STALL=REPLY_STALL cmd=p1_cmd reply_owned=p1_reply_owned reply_waiting=p1_reply_waiting reply_stall=p1_reply_stall +.subckt processor p2 CMD=CMD master=p2_master REPLY_OWNED=REPLY_OWNED REPLY_WAITING=REPLY_WAITING REPLY_STALL=REPLY_STALL cmd=p2_cmd reply_owned=p2_reply_owned reply_waiting=p2_reply_waiting reply_stall=p2_reply_stall +.subckt memory m CMD=CMD master=m_master REPLY_OWNED=REPLY_OWNED REPLY_WAITING=REPLY_WAITING REPLY_STALL=REPLY_STALL cmd=m_cmd reply_owned=m_reply_owned reply_waiting=m_reply_waiting reply_stall=m_reply_stall +# assign REPLY_OWNED = p0_reply_owned | p1_reply_owned | p2_reply_owned +# p0_reply_owned | p1_reply_owned +.names p0_reply_owned p1_reply_owned _n1 +.def 1 +0 0 0 +# p0_reply_owned | p1_reply_owned | p2_reply_owned +.names _n1 p2_reply_owned _n2 +.def 1 +0 0 0 +.names _n2 REPLY_OWNED$raw_n0 +- =_n2 +# assign REPLY_WAITING = p0_reply_waiting | p1_reply_waiting | p2_reply_waiting +# p0_reply_waiting | p1_reply_waiting +.names p0_reply_waiting p1_reply_waiting _n4 +.def 1 +0 0 0 +# p0_reply_waiting | p1_reply_waiting | p2_reply_waiting +.names _n4 p2_reply_waiting _n5 +.def 1 +0 0 0 +.names _n5 REPLY_WAITING$raw_n3 +- =_n5 +# assign REPLY_STALL = p0_reply_stall | p1_reply_stall | p2_reply_stall | m_reply_stall +# p0_reply_stall | p1_reply_stall +.names p0_reply_stall p1_reply_stall _n7 +.def 1 +0 0 0 +# p0_reply_stall | p1_reply_stall | p2_reply_stall +.names _n7 p2_reply_stall _n8 +.def 1 +0 0 0 +# p0_reply_stall | p1_reply_stall | p2_reply_stall | m_reply_stall +.names _n8 m_reply_stall _n9 +.def 1 +0 0 0 +.names _n9 REPLY_STALL$raw_n6 +- =_n9 +# assign CMD = (p1_cmd == 0 && p2_cmd == 0 && m_cmd == 0) ? p0_cmd : (p0_cmd == 0 && p2_cmd == 0 && m_cmd == 0) ? p1_cmd : (p0_cmd == 0 && p1_cmd == 0 && m_cmd == 0) ? p2_cmd : (p0_cmd == 0 && p1_cmd == 0 && p2_cmd == 0) ? m_cmd : nond_CMD +.mv CMD$raw_na 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv _nc 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _nc +idle +# p1_cmd == 0 +.names p1_cmd _nc _nb +.def 0 +- =p1_cmd 1 +.mv _ne 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _ne +idle +# p2_cmd == 0 +.names p2_cmd _ne _nd +.def 0 +- =p2_cmd 1 +# p1_cmd == 0 && p2_cmd == 0 +.names _nb _nd _nf +.def 0 +1 1 1 +.mv _n11 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n11 +idle +# m_cmd == 0 +.names m_cmd _n11 _n10 +.def 0 +- =m_cmd 1 +# p1_cmd == 0 && p2_cmd == 0 && m_cmd == 0 +.names _nf _n10 _n12 +.def 0 +1 1 1 +.mv _n14 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n14 +idle +# p0_cmd == 0 +.names p0_cmd _n14 _n13 +.def 0 +- =p0_cmd 1 +.mv _n16 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n16 +idle +# p2_cmd == 0 +.names p2_cmd _n16 _n15 +.def 0 +- =p2_cmd 1 +# p0_cmd == 0 && p2_cmd == 0 +.names _n13 _n15 _n17 +.def 0 +1 1 1 +.mv _n19 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n19 +idle +# m_cmd == 0 +.names m_cmd _n19 _n18 +.def 0 +- =m_cmd 1 +# p0_cmd == 0 && p2_cmd == 0 && m_cmd == 0 +.names _n17 _n18 _n1a +.def 0 +1 1 1 +.mv _n1c 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n1c +idle +# p0_cmd == 0 +.names p0_cmd _n1c _n1b +.def 0 +- =p0_cmd 1 +.mv _n1e 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n1e +idle +# p1_cmd == 0 +.names p1_cmd _n1e _n1d +.def 0 +- =p1_cmd 1 +# p0_cmd == 0 && p1_cmd == 0 +.names _n1b _n1d _n1f +.def 0 +1 1 1 +.mv _n21 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n21 +idle +# m_cmd == 0 +.names m_cmd _n21 _n20 +.def 0 +- =m_cmd 1 +# p0_cmd == 0 && p1_cmd == 0 && m_cmd == 0 +.names _n1f _n20 _n22 +.def 0 +1 1 1 +.mv _n24 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n24 +idle +# p0_cmd == 0 +.names p0_cmd _n24 _n23 +.def 0 +- =p0_cmd 1 +.mv _n26 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n26 +idle +# p1_cmd == 0 +.names p1_cmd _n26 _n25 +.def 0 +- =p1_cmd 1 +# p0_cmd == 0 && p1_cmd == 0 +.names _n23 _n25 _n27 +.def 0 +1 1 1 +.mv _n29 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n29 +idle +# p2_cmd == 0 +.names p2_cmd _n29 _n28 +.def 0 +- =p2_cmd 1 +# p0_cmd == 0 && p1_cmd == 0 && p2_cmd == 0 +.names _n27 _n28 _n2a +.def 0 +1 1 1 +# (p0_cmd == 0 && p1_cmd == 0 && p2_cmd == 0) ? m_cmd : nond_CMD +.mv _n2b 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names m_cmd nond_CMD _n2a _n2b +- - 0 =nond_CMD +- - 1 =m_cmd +# (p0_cmd == 0 && p1_cmd == 0 && m_cmd == 0) ? p2_cmd : (p0_cmd == 0 && p1_cmd == 0 && p2_cmd == 0) ? m_cmd : nond_CMD +.mv _n2c 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names p2_cmd _n2b _n22 _n2c +- - 0 =_n2b +- - 1 =p2_cmd +# (p0_cmd == 0 && p2_cmd == 0 && m_cmd == 0) ? p1_cmd : (p0_cmd == 0 && p1_cmd == 0 && m_cmd == 0) ? p2_cmd : (p0_cmd == 0 && p1_cmd == 0 && p2_cmd == 0) ? m_cmd : nond_CMD +.mv _n2d 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names p1_cmd _n2c _n1a _n2d +- - 0 =_n2c +- - 1 =p1_cmd +# (p1_cmd == 0 && p2_cmd == 0 && m_cmd == 0) ? p0_cmd : (p0_cmd == 0 && p2_cmd == 0 && m_cmd == 0) ? p1_cmd : (p0_cmd == 0 && p1_cmd == 0 && m_cmd == 0) ? p2_cmd : (p0_cmd == 0 && p1_cmd == 0 && p2_cmd == 0) ? m_cmd : nond_CMD +.mv _n2e 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names p0_cmd _n2d _n12 _n2e +- - 0 =_n2d +- - 1 =p0_cmd +.names _n2e CMD$raw_na +- =_n2e +# assign p0_master = nond0_master +.names nond0_master p0_master$raw_n2f +- =nond0_master +# assign p1_master = (p0_master ) ? 0 : nond1_master +.names _n31 +0 +# (p0_master ) ? 0 : nond1_master +.names _n31 nond1_master p0_master _n32 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n32 p1_master$raw_n30 +- =_n32 +# assign p2_master = (p0_master || p1_master ) ? 0 : nond2_master +# p0_master || p1_master +.names p0_master p1_master _n35 +.def 1 +0 0 0 +.names _n36 +0 +# (p0_master || p1_master ) ? 0 : nond2_master +.names _n36 nond2_master _n35 _n37 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n37 p2_master$raw_n34 +- =_n37 +# assign m_master = ((p0_master || p1_master ) || p2_master ) ? 0 : nondm_master +# p0_master || p1_master +.names p0_master p1_master _n3a +.def 1 +0 0 0 +# (p0_master || p1_master ) || p2_master +.names _n3a p2_master _n3b +.def 1 +0 0 0 +.names _n3c +0 +# ((p0_master || p1_master ) || p2_master ) ? 0 : nondm_master +.names _n3c nondm_master _n3b _n3d +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n3d m_master$raw_n39 +- =_n3d +# assign nond0_master = $NDset ( 0,1 ) +.names nond0_master +0 +1 +# assign nond1_master = $NDset ( 0,1 ) +.names nond1_master +0 +1 +# assign nond2_master = $NDset ( 0,1 ) +.names nond2_master +0 +1 +# assign nondm_master = $NDset ( 0,1 ) +.names nondm_master +0 +1 +# assign nond_CMD = $NDset ( 0,1,2,3,4,5,6,7,8 ) +.names nond_CMD +idle +read_shared +read_owned +write_invalid +write_shared +write_resp_invalid +write_resp_shared +invalidate +response +# conflict arbitrators +.names REPLY_OWNED$raw_n0 REPLY_OWNED +0 0 +1 1 +.names m_master$raw_n39 m_master +0 0 +1 1 +.names REPLY_WAITING$raw_n3 REPLY_WAITING +0 0 +1 1 +.names p1_master$raw_n30 p1_master +0 0 +1 1 +.names p2_master$raw_n34 p2_master +0 0 +1 1 +.names REPLY_STALL$raw_n6 REPLY_STALL +0 0 +1 1 +.names CMD$raw_na CMD +- =CMD$raw_na +.names p0_master$raw_n2f p0_master +0 0 +1 1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model processor +# I/O ports +.inputs REPLY_OWNED +.outputs reply_waiting +.inputs REPLY_WAITING +.inputs master +.outputs reply_owned +.outputs reply_stall +.outputs cmd +.inputs REPLY_STALL +.inputs CMD + +.mv snoop 3 invalid shared owned +.mv cmd 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv CMD 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv state 3 invalid shared owned +.mv nond_cmd 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.subckt bus_device Bdevice CMD=CMD master=master REPLY_STALL=REPLY_STALL REPLY_WAITING=REPLY_WAITING waiting=waiting reply_waiting=reply_waiting abort=abort +.subckt cache_device Cdevice CMD=CMD master=master abort=abort waiting=waiting state=state snoop=snoop reply_owned=reply_owned readable=readable writable=writable +# assign cmd = (master && state == invalid ) ? nond_cmd : (master && state == shared ) ? 2 : (master && state == owned && snoop == owned ) ? 5 : (master && state == owned && snoop == shared ) ? 6 : (master && state == owned && snoop == invalid ) ? 3 : 0 +.mv cmd$raw_n49 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv _n4b 3 invalid shared owned +.names _n4b +invalid +# state == 0 +.names state _n4b _n4a +.def 0 +- =state 1 +# master && state == 0 +.names master _n4a _n4c +.def 0 +1 1 1 +.mv _n4e 3 invalid shared owned +.names _n4e +shared +# state == 1 +.names state _n4e _n4d +.def 0 +- =state 1 +# master && state == 1 +.names master _n4d _n4f +.def 0 +1 1 1 +.mv _n51 3 invalid shared owned +.names _n51 +owned +# state == 2 +.names state _n51 _n50 +.def 0 +- =state 1 +# master && state == 2 +.names master _n50 _n52 +.def 0 +1 1 1 +.mv _n54 3 invalid shared owned +.names _n54 +owned +# snoop == 2 +.names snoop _n54 _n53 +.def 0 +- =snoop 1 +# master && state == 2 && snoop == 2 +.names _n52 _n53 _n55 +.def 0 +1 1 1 +.mv _n57 3 invalid shared owned +.names _n57 +owned +# state == 2 +.names state _n57 _n56 +.def 0 +- =state 1 +# master && state == 2 +.names master _n56 _n58 +.def 0 +1 1 1 +.mv _n5a 3 invalid shared owned +.names _n5a +shared +# snoop == 1 +.names snoop _n5a _n59 +.def 0 +- =snoop 1 +# master && state == 2 && snoop == 1 +.names _n58 _n59 _n5b +.def 0 +1 1 1 +.mv _n5d 3 invalid shared owned +.names _n5d +owned +# state == 2 +.names state _n5d _n5c +.def 0 +- =state 1 +# master && state == 2 +.names master _n5c _n5e +.def 0 +1 1 1 +.mv _n60 3 invalid shared owned +.names _n60 +invalid +# snoop == 0 +.names snoop _n60 _n5f +.def 0 +- =snoop 1 +# master && state == 2 && snoop == 0 +.names _n5e _n5f _n61 +.def 0 +1 1 1 +.mv _n62 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n62 +write_invalid +.mv _n63 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n63 +idle +# (master && state == 2 && snoop == 0) ? 3 : 0 +.mv _n64 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n62 _n63 _n61 _n64 +- - 0 =_n63 +- - 1 =_n62 +.mv _n65 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n65 +write_resp_shared +# (master && state == 2 && snoop == 1) ? 6 : (master && state == 2 && snoop == 0) ? 3 : 0 +.mv _n66 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n65 _n64 _n5b _n66 +- - 0 =_n64 +- - 1 =_n65 +.mv _n67 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n67 +write_resp_invalid +# (master && state == 2 && snoop == 2) ? 5 : (master && state == 2 && snoop == 1) ? 6 : (master && state == 2 && snoop == 0) ? 3 : 0 +.mv _n68 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n67 _n66 _n55 _n68 +- - 0 =_n66 +- - 1 =_n67 +.mv _n69 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n69 +read_owned +# (master && state == 1) ? 2 : (master && state == 2 && snoop == 2) ? 5 : (master && state == 2 && snoop == 1) ? 6 : (master && state == 2 && snoop == 0) ? 3 : 0 +.mv _n6a 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n69 _n68 _n4f _n6a +- - 0 =_n68 +- - 1 =_n69 +# (master && state == 0) ? nond_cmd : (master && state == 1) ? 2 : (master && state == 2 && snoop == 2) ? 5 : (master && state == 2 && snoop == 1) ? 6 : (master && state == 2 && snoop == 0) ? 3 : 0 +.mv _n6b 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names nond_cmd _n6a _n4c _n6b +- - 0 =_n6a +- - 1 =nond_cmd +.names _n6b cmd$raw_n49 +- =_n6b +# assign nond_cmd = $NDset ( 1,2 ) +.names nond_cmd +read_shared +read_owned +# assign reply_stall = $NDset ( 0,1 ) +.names reply_stall +0 +1 +# conflict arbitrators +.names cmd$raw_n49 cmd +- =cmd$raw_n49 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model memory +# I/O ports +.inputs REPLY_OWNED +.outputs reply_waiting +.inputs REPLY_WAITING +.inputs master +.outputs reply_owned +.outputs reply_stall +.outputs cmd +.inputs REPLY_STALL +.inputs CMD + +.mv cmd 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv CMD 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv nond_cmd 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +# assign reply_owned = 0 +.names reply_owned$raw_n70 +0 +# assign reply_waiting = 0 +.names reply_waiting$raw_n71 +0 +# assign abort = REPLY_STALL || (CMD == read_shared || CMD == read_owned ) && REPLY_WAITING || (CMD == read_shared || CMD == read_owned ) && REPLY_OWNED +.mv _n74 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n74 +read_shared +# CMD == 1 +.names CMD _n74 _n73 +.def 0 +- =CMD 1 +.mv _n76 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n76 +read_owned +# CMD == 2 +.names CMD _n76 _n75 +.def 0 +- =CMD 1 +# CMD == 1 || CMD == 2 +.names _n73 _n75 _n77 +.def 1 +0 0 0 +# (CMD == 1 || CMD == 2) && REPLY_WAITING +.names _n77 REPLY_WAITING _n78 +.def 0 +1 1 1 +# REPLY_STALL || (CMD == 1 || CMD == 2) && REPLY_WAITING +.names REPLY_STALL _n78 _n79 +.def 1 +0 0 0 +.mv _n7b 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n7b +read_shared +# CMD == 1 +.names CMD _n7b _n7a +.def 0 +- =CMD 1 +.mv _n7d 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n7d +read_owned +# CMD == 2 +.names CMD _n7d _n7c +.def 0 +- =CMD 1 +# CMD == 1 || CMD == 2 +.names _n7a _n7c _n7e +.def 1 +0 0 0 +# (CMD == 1 || CMD == 2) && REPLY_OWNED +.names _n7e REPLY_OWNED _n7f +.def 0 +1 1 1 +# REPLY_STALL || (CMD == 1 || CMD == 2) && REPLY_WAITING || (CMD == 1 || CMD == 2) && REPLY_OWNED +.names _n79 _n7f _n80 +.def 1 +0 0 0 +.names _n80 abort$raw_n72 +- =_n80 +# assign cmd = (master && busy ) ? nond_cmd : 0 +.mv cmd$raw_n81 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +# master && busy +.names master busy _n82 +.def 0 +1 1 1 +.mv _n83 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n83 +idle +# (master && busy ) ? nond_cmd : 0 +.mv _n84 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names nond_cmd _n83 _n82 _n84 +- - 0 =_n83 +- - 1 =nond_cmd +.names _n84 cmd$raw_n81 +- =_n84 +# assign reply_stall = (busy && (CMD == read_shared || CMD == read_owned || CMD == write_invalid || CMD == write_shared || CMD == write_resp_invalid || CMD == write_resp_shared )) ? 1 : nond_reply_stall +.mv _n87 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n87 +read_shared +# CMD == 1 +.names CMD _n87 _n86 +.def 0 +- =CMD 1 +.mv _n89 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n89 +read_owned +# CMD == 2 +.names CMD _n89 _n88 +.def 0 +- =CMD 1 +# CMD == 1 || CMD == 2 +.names _n86 _n88 _n8a +.def 1 +0 0 0 +.mv _n8c 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n8c +write_invalid +# CMD == 3 +.names CMD _n8c _n8b +.def 0 +- =CMD 1 +# CMD == 1 || CMD == 2 || CMD == 3 +.names _n8a _n8b _n8d +.def 1 +0 0 0 +.mv _n8f 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n8f +write_shared +# CMD == 4 +.names CMD _n8f _n8e +.def 0 +- =CMD 1 +# CMD == 1 || CMD == 2 || CMD == 3 || CMD == 4 +.names _n8d _n8e _n90 +.def 1 +0 0 0 +.mv _n92 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n92 +write_resp_invalid +# CMD == 5 +.names CMD _n92 _n91 +.def 0 +- =CMD 1 +# CMD == 1 || CMD == 2 || CMD == 3 || CMD == 4 || CMD == 5 +.names _n90 _n91 _n93 +.def 1 +0 0 0 +.mv _n95 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n95 +write_resp_shared +# CMD == 6 +.names CMD _n95 _n94 +.def 0 +- =CMD 1 +# CMD == 1 || CMD == 2 || CMD == 3 || CMD == 4 || CMD == 5 || CMD == 6 +.names _n93 _n94 _n96 +.def 1 +0 0 0 +# busy && (CMD == 1 || CMD == 2 || CMD == 3 || CMD == 4 || CMD == 5 || CMD == 6) +.names busy _n96 _n97 +.def 0 +1 1 1 +.names _n98 +1 +# (busy && (CMD == 1 || CMD == 2 || CMD == 3 || CMD == 4 || CMD == 5 || CMD == 6)) ? 1 : nond_reply_stall +.names _n98 nond_reply_stall _n97 _n99 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n99 reply_stall$raw_n85 +- =_n99 +# assign nond_reply_stall = $NDset ( 0,1 ) +.names nond_reply_stall +0 +1 +# assign nond_cmd = $NDset ( 8,0 ) +.names nond_cmd +response +idle +# busy = 0 +.names busy$raw_n9f +0 +# non-blocking assignments for initial +.names abort _na0 +- =abort +# busy = busy +.names busy busy$abort_na1$true +- =busy +.mv _na3 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _na3 +response +# CMD == 8 +.names CMD _na3 _na2 +.def 0 +- =CMD 1 +# master && CMD == 8 +.names master _na2 _na4 +.def 0 +1 1 1 +.names _na4 _na5 +- =_na4 +# busy = 0 +.names busy$_na4_na6$true +0 +.names master _na7 +0 1 +1 0 +.mv _na9 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _na9 +read_owned +# CMD == 2 +.names CMD _na9 _na8 +.def 0 +- =CMD 1 +# !master && CMD == 2 +.names _na7 _na8 _naa +.def 0 +1 1 1 +.mv _nac 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _nac +read_shared +# CMD == 1 +.names CMD _nac _nab +.def 0 +- =CMD 1 +# !master && CMD == 2 || CMD == 1 +.names _naa _nab _nad +.def 1 +0 0 0 +.names _nad _nae +- =_nad +# busy = 1 +.names busy$_nad_naf$true +1 +# if/else (!master && CMD == 2 || CMD == 1) +.names busy$_nad_naf$true busy _nad busy$_nad$raw_nb2 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (master && CMD == 8) +.names busy$_na4_na6$true busy$_nad$raw_nb2 _na4 busy$_na4$raw_nb5 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (abort ) +.names busy$abort_na1$true busy$_na4$raw_nb5 abort busy$abort$raw_nba +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names _na0 _na5 _nae _nbe +.def 0 + 1 - - 1 + 0 1 - 1 + 0 0 1 1 +.names _nbe busy$abort$raw_nba busy _nbf +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +.names reply_waiting$raw_n71 reply_waiting +0 0 +1 1 +.names abort$raw_n72 abort +0 0 +1 1 +.names reply_owned$raw_n70 reply_owned +0 0 +1 1 +.names reply_stall$raw_n85 reply_stall +0 0 +1 1 +.names cmd$raw_n81 cmd +- =cmd$raw_n81 +# non-blocking assignments +# latches +.r busy$raw_n9f busy +0 0 +1 1 +.latch _nbf busy +# quasi-continuous assignment +.end + + +.model cache_device +# I/O ports +.outputs writable +.outputs readable +.outputs snoop +.inputs master +.outputs reply_owned +.inputs abort +.inputs CMD +.outputs state +.inputs waiting + +.mv snoop 3 invalid shared owned +.mv nond_state 3 invalid shared owned +.mv nond_snoop 3 invalid shared owned +.mv CMD 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.mv state 3 invalid shared owned +# assign readable = ((state == shared ) || (state == owned )) && !waiting +.mv _nc2 3 invalid shared owned +.names _nc2 +shared +# state == 1 +.names state _nc2 _nc1 +.def 0 +- =state 1 +.mv _nc4 3 invalid shared owned +.names _nc4 +owned +# state == 2 +.names state _nc4 _nc3 +.def 0 +- =state 1 +# (state == 1) || (state == 2) +.names _nc1 _nc3 _nc5 +.def 1 +0 0 0 +.names waiting _nc6 +0 1 +1 0 +# ((state == 1) || (state == 2)) && !waiting +.names _nc5 _nc6 _nc7 +.def 0 +1 1 1 +.names _nc7 readable$raw_nc0 +- =_nc7 +# assign writable = (state == owned ) && (!waiting ) +.mv _nca 3 invalid shared owned +.names _nca +owned +# state == 2 +.names state _nca _nc9 +.def 0 +- =state 1 +.names waiting _ncb +0 1 +1 0 +# (state == 2) && (!waiting ) +.names _nc9 _ncb _ncc +.def 0 +1 1 1 +.names _ncc writable$raw_nc8 +- =_ncc +# assign reply_owned = (!master ) && (state == owned ) +.names master _nce +0 1 +1 0 +.mv _nd0 3 invalid shared owned +.names _nd0 +owned +# state == 2 +.names state _nd0 _ncf +.def 0 +- =state 1 +# (!master ) && (state == 2) +.names _nce _ncf _nd1 +.def 0 +1 1 1 +.names _nd1 reply_owned$raw_ncd +- =_nd1 +# assign nond_snoop = $NDset ( 1,2 ) +.names nond_snoop +shared +owned +# assign nond_state = $NDset ( 1,0 ) +.names nond_state +shared +invalid +# state = 0 +.mv state$raw_nd6 3 invalid shared owned +.names state$raw_nd6 +invalid +# non-blocking assignments for initial +# snoop = 0 +.mv snoop$raw_nd7 3 invalid shared owned +.names snoop$raw_nd7 +invalid +# non-blocking assignments for initial +.names abort _nd8 +- =abort +# snoop = snoop +.mv snoop$abort_nd9$true 3 invalid shared owned +.names snoop snoop$abort_nd9$true +- =snoop +.names master _nda +0 1 +1 0 +.mv _ndc 3 invalid shared owned +.names _ndc +owned +# state == 2 +.names state _ndc _ndb +.def 0 +- =state 1 +# !master && state == 2 +.names _nda _ndb _ndd +.def 0 +1 1 1 +.mv _ndf 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _ndf +read_shared +# CMD == 1 +.names CMD _ndf _nde +.def 0 +- =CMD 1 +# !master && state == 2 && CMD == 1 +.names _ndd _nde _ne0 +.def 0 +1 1 1 +.names _ne0 _ne1 +- =_ne0 +# snoop = nond_snoop +.mv snoop$_ne0_ne2$true 3 invalid shared owned +.names nond_snoop snoop$_ne0_ne2$true +- =nond_snoop +.mv _ne4 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _ne4 +write_resp_invalid +# CMD == 5 +.names CMD _ne4 _ne3 +.def 0 +- =CMD 1 +# master && CMD == 5 +.names master _ne3 _ne5 +.def 0 +1 1 1 +.names _ne5 _ne6 +- =_ne5 +# snoop = 0 +.mv snoop$_ne5_ne7$true 3 invalid shared owned +.names snoop$_ne5_ne7$true +invalid +.mv _ne9 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _ne9 +write_resp_shared +# CMD == 6 +.names CMD _ne9 _ne8 +.def 0 +- =CMD 1 +# master && CMD == 6 +.names master _ne8 _nea +.def 0 +1 1 1 +.names _nea _neb +- =_nea +# snoop = 0 +.mv snoop$_nea_nec$true 3 invalid shared owned +.names snoop$_nea_nec$true +invalid +# if/else (master && CMD == 6) +.mv snoop$_nea$raw_nef 3 invalid shared owned +.names snoop$_nea_nec$true snoop _nea snoop$_nea$raw_nef +- - 0 =snoop +- - 1 =snoop$_nea_nec$true +# if/else (master && CMD == 5) +.mv snoop$_ne5$raw_nf1 3 invalid shared owned +.names snoop$_ne5_ne7$true snoop$_nea$raw_nef _ne5 snoop$_ne5$raw_nf1 +- - 0 =snoop$_nea$raw_nef +- - 1 =snoop$_ne5_ne7$true +# if/else (!master && state == 2 && CMD == 1) +.mv snoop$_ne0$raw_nf5 3 invalid shared owned +.names snoop$_ne0_ne2$true snoop$_ne5$raw_nf1 _ne0 snoop$_ne0$raw_nf5 +- - 0 =snoop$_ne5$raw_nf1 +- - 1 =snoop$_ne0_ne2$true +# if/else (abort ) +.mv snoop$abort$raw_nf9 3 invalid shared owned +.names snoop$abort_nd9$true snoop$_ne0$raw_nf5 abort snoop$abort$raw_nf9 +- - 0 =snoop$_ne0$raw_nf5 +- - 1 =snoop$abort_nd9$true +.names abort _nfc +- =abort +# state = state +.mv state$abort_nfd$true 3 invalid shared owned +.names state state$abort_nfd$true +- =state +.names _nff +1 +# master == 1 +.names master _nff _n100 +.def 0 +0 1 1 +1 0 1 +.names _n100 _nfe +0 1 +1 0 +.names _nfe _n102 +- =_nfe +.mv _n105 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n105 +read_shared +.names CMD _n105 _n104 +.def 0 +- =CMD 1 +.names _n104 _n103 +1 1 +0 0 +# state = 1 +.mv state$_n103_n106$true 3 invalid shared owned +.names state$_n103_n106$true +shared +.mv _n109 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n109 +read_owned +.names CMD _n109 _n108 +.def 0 +- =CMD 1 +.names _n108 _n107 +1 1 +0 0 +# state = 2 +.mv state$_n107_n10a$true 3 invalid shared owned +.names state$_n107_n10a$true +owned +.mv _n10d 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n10d +write_invalid +.names CMD _n10d _n10c +.def 0 +- =CMD 1 +.names _n10c _n10b +1 1 +0 0 +# state = 0 +.mv state$_n10b_n10e$true 3 invalid shared owned +.names state$_n10b_n10e$true +invalid +.mv _n111 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n111 +write_resp_invalid +.names CMD _n111 _n110 +.def 0 +- =CMD 1 +.names _n110 _n10f +1 1 +0 0 +# state = 0 +.mv state$_n10f_n112$true 3 invalid shared owned +.names state$_n10f_n112$true +invalid +.mv _n115 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n115 +write_shared +.names CMD _n115 _n114 +.def 0 +- =CMD 1 +.names _n114 _n113 +1 1 +0 0 +# state = 1 +.mv state$_n113_n116$true 3 invalid shared owned +.names state$_n113_n116$true +shared +.mv _n119 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n119 +write_resp_shared +.names CMD _n119 _n118 +.def 0 +- =CMD 1 +.names _n118 _n117 +1 1 +0 0 +# state = 1 +.mv state$_n117_n11a$true 3 invalid shared owned +.names state$_n117_n11a$true +shared +# case (CMD ) +.mv state$_n117$raw_n120 3 invalid shared owned +.names state$_n117_n11a$true state _n117 state$_n117$raw_n120 +- - 0 =state +- - 1 =state$_n117_n11a$true +.mv state$_n113$raw_n123 3 invalid shared owned +.names state$_n113_n116$true state$_n117$raw_n120 _n113 state$_n113$raw_n123 +- - 0 =state$_n117$raw_n120 +- - 1 =state$_n113_n116$true +.mv state$_n10f$raw_n12b 3 invalid shared owned +.names state$_n10f_n112$true state$_n113$raw_n123 _n10f state$_n10f$raw_n12b +- - 0 =state$_n113$raw_n123 +- - 1 =state$_n10f_n112$true +.mv state$_n10b$raw_n133 3 invalid shared owned +.names state$_n10b_n10e$true state$_n10f$raw_n12b _n10b state$_n10b$raw_n133 +- - 0 =state$_n10f$raw_n12b +- - 1 =state$_n10b_n10e$true +.mv state$_n107$raw_n13b 3 invalid shared owned +.names state$_n107_n10a$true state$_n10b$raw_n133 _n107 state$_n107$raw_n13b +- - 0 =state$_n10b$raw_n133 +- - 1 =state$_n107_n10a$true +.mv state$_n103$raw_n143 3 invalid shared owned +.names state$_n103_n106$true state$_n107$raw_n13b _n103 state$_n103$raw_n143 +- - 0 =state$_n107$raw_n13b +- - 1 =state$_n103_n106$true +.names master _n14a +0 1 +1 0 +.mv _n14c 3 invalid shared owned +.names _n14c +shared +# state == 1 +.names state _n14c _n14b +.def 0 +- =state 1 +# !master && state == 1 +.names _n14a _n14b _n14d +.def 0 +1 1 1 +.mv _n14f 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n14f +read_owned +# CMD == 2 +.names CMD _n14f _n14e +.def 0 +- =CMD 1 +.mv _n151 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n151 +invalidate +# CMD == 7 +.names CMD _n151 _n150 +.def 0 +- =CMD 1 +# CMD == 2 || CMD == 7 +.names _n14e _n150 _n152 +.def 1 +0 0 0 +# !master && state == 1 && (CMD == 2 || CMD == 7) +.names _n14d _n152 _n153 +.def 0 +1 1 1 +.names _n153 _n154 +- =_n153 +# state = 0 +.mv state$_n153_n155$true 3 invalid shared owned +.names state$_n153_n155$true +invalid +.mv _n157 3 invalid shared owned +.names _n157 +shared +# state == 1 +.names state _n157 _n156 +.def 0 +- =state 1 +.names _n156 _n158 +- =_n156 +# state = nond_state +.mv state$_n156_n159$true 3 invalid shared owned +.names nond_state state$_n156_n159$true +- =nond_state +# if/else (state == 1) +.mv state$_n156$raw_n15f 3 invalid shared owned +.names state$_n156_n159$true state _n156 state$_n156$raw_n15f +- - 0 =state +- - 1 =state$_n156_n159$true +# if/else (!master && state == 1 && (CMD == 2 || CMD == 7)) +.mv state$_n153$raw_n164 3 invalid shared owned +.names state$_n153_n155$true state$_n156$raw_n15f _n153 state$_n153$raw_n164 +- - 0 =state$_n156$raw_n15f +- - 1 =state$_n153_n155$true +# if/else (master == 1) +.mv state$_nfe$raw_n16c 3 invalid shared owned +.names state$_n103$raw_n143 state$_n153$raw_n164 _nfe state$_nfe$raw_n16c +- - 0 =state$_n153$raw_n164 +- - 1 =state$_n103$raw_n143 +# if/else (abort ) +.mv state$abort$raw_n174 3 invalid shared owned +.names state$abort_nfd$true state$_nfe$raw_n16c abort state$abort$raw_n174 +- - 0 =state$_nfe$raw_n16c +- - 1 =state$abort_nfd$true +# conflict arbitrators +.names writable$raw_nc8 writable +0 0 +1 1 +.names readable$raw_nc0 readable +0 0 +1 1 +.names _nd8 _ne1 _ne6 _neb _n179 +.def 0 + 1 - - - 1 + 0 1 - - 1 + 0 0 1 - 1 + 0 0 0 1 1 +.mv _n17a 3 invalid shared owned +.names _n179 snoop$abort$raw_nf9 snoop _n17a +1 - - =snoop$abort$raw_nf9 +0 - - =snoop +.names reply_owned$raw_ncd reply_owned +0 0 +1 1 +.names _nfc _n102 _n103 _n107 _n10b _n10f _n113 _n117 _n154 _n158 _n187 +.def 0 + 1 - - - - - - - - - 1 + 0 1 1 - - - - - - - 1 + 0 1 0 1 - - - - - - 1 + 0 1 0 0 1 - - - - - 1 + 0 1 0 0 0 1 - - - - 1 + 0 1 0 0 0 0 1 - - - 1 + 0 1 0 0 0 0 0 1 - - 1 + 0 0 - - - - - - 1 - 1 + 0 0 - - - - - - 0 1 1 +.mv _n188 3 invalid shared owned +.names _n187 state$abort$raw_n174 state _n188 +1 - - =state$abort$raw_n174 +0 - - =state +# non-blocking assignments +# latches +.r snoop$raw_nd7 snoop +- =snoop$raw_nd7 +.latch _n17a snoop +.r state$raw_nd6 state +- =state$raw_nd6 +.latch _n188 state +# quasi-continuous assignment +.end + + +.model bus_device +# I/O ports +.outputs reply_waiting +.inputs REPLY_WAITING +.inputs master +.outputs abort +.inputs REPLY_STALL +.inputs CMD +.outputs waiting + +.mv CMD 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +# assign reply_waiting = !master && waiting +.names master _n196 +0 1 +1 0 +# !master && waiting +.names _n196 waiting _n197 +.def 0 +1 1 1 +.names _n197 reply_waiting$raw_n195 +- =_n197 +# assign abort = REPLY_STALL || ((CMD == read_shared || CMD == read_owned ) && REPLY_WAITING ) +.mv _n19a 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n19a +read_shared +# CMD == 1 +.names CMD _n19a _n199 +.def 0 +- =CMD 1 +.mv _n19c 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n19c +read_owned +# CMD == 2 +.names CMD _n19c _n19b +.def 0 +- =CMD 1 +# CMD == 1 || CMD == 2 +.names _n199 _n19b _n19d +.def 1 +0 0 0 +# (CMD == 1 || CMD == 2) && REPLY_WAITING +.names _n19d REPLY_WAITING _n19e +.def 0 +1 1 1 +# REPLY_STALL || ((CMD == 1 || CMD == 2) && REPLY_WAITING ) +.names REPLY_STALL _n19e _n19f +.def 1 +0 0 0 +.names _n19f abort$raw_n198 +- =_n19f +# waiting = 0 +.names waiting$raw_n1a0 +0 +# non-blocking assignments for initial +.names abort _n1a1 +- =abort +# waiting = waiting +.names waiting waiting$abort_n1a2$true +- =waiting +.mv _n1a4 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n1a4 +read_shared +# CMD == 1 +.names CMD _n1a4 _n1a3 +.def 0 +- =CMD 1 +# master && CMD == 1 +.names master _n1a3 _n1a5 +.def 0 +1 1 1 +.names _n1a5 _n1a6 +- =_n1a5 +# waiting = 1 +.names waiting$_n1a5_n1a7$true +1 +.mv _n1a9 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n1a9 +read_owned +# CMD == 2 +.names CMD _n1a9 _n1a8 +.def 0 +- =CMD 1 +# master && CMD == 2 +.names master _n1a8 _n1aa +.def 0 +1 1 1 +.names _n1aa _n1ab +- =_n1aa +# waiting = 1 +.names waiting$_n1aa_n1ac$true +1 +.names master _n1ad +0 1 +1 0 +.mv _n1af 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n1af +response +# CMD == 8 +.names CMD _n1af _n1ae +.def 0 +- =CMD 1 +# !master && CMD == 8 +.names _n1ad _n1ae _n1b0 +.def 0 +1 1 1 +.names _n1b0 _n1b1 +- =_n1b0 +# waiting = 0 +.names waiting$_n1b0_n1b2$true +0 +.names master _n1b3 +0 1 +1 0 +.mv _n1b5 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n1b5 +write_resp_invalid +# CMD == 5 +.names CMD _n1b5 _n1b4 +.def 0 +- =CMD 1 +# !master && CMD == 5 +.names _n1b3 _n1b4 _n1b6 +.def 0 +1 1 1 +.names _n1b6 _n1b7 +- =_n1b6 +# waiting = 0 +.names waiting$_n1b6_n1b8$true +0 +.names master _n1b9 +0 1 +1 0 +.mv _n1bb 9 idle read_shared read_owned write_invalid write_shared write_resp_invalid write_resp_shared invalidate response +.names _n1bb +write_resp_shared +# CMD == 6 +.names CMD _n1bb _n1ba +.def 0 +- =CMD 1 +# !master && CMD == 6 +.names _n1b9 _n1ba _n1bc +.def 0 +1 1 1 +.names _n1bc _n1bd +- =_n1bc +# waiting = 0 +.names waiting$_n1bc_n1be$true +0 +# if/else (!master && CMD == 6) +.names waiting$_n1bc_n1be$true waiting _n1bc waiting$_n1bc$raw_n1c1 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (!master && CMD == 5) +.names waiting$_n1b6_n1b8$true waiting$_n1bc$raw_n1c1 _n1b6 waiting$_n1b6$raw_n1c4 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (!master && CMD == 8) +.names waiting$_n1b0_n1b2$true waiting$_n1b6$raw_n1c4 _n1b0 waiting$_n1b0$raw_n1c9 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (master && CMD == 2) +.names waiting$_n1aa_n1ac$true waiting$_n1b0$raw_n1c9 _n1aa waiting$_n1aa$raw_n1ce +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (master && CMD == 1) +.names waiting$_n1a5_n1a7$true waiting$_n1aa$raw_n1ce _n1a5 waiting$_n1a5$raw_n1d3 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (abort ) +.names waiting$abort_n1a2$true waiting$_n1a5$raw_n1d3 abort waiting$abort$raw_n1d8 +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names reply_waiting$raw_n195 reply_waiting +0 0 +1 1 +.names abort$raw_n198 abort +0 0 +1 1 +.names _n1a1 _n1a6 _n1ab _n1b1 _n1b7 _n1bd _n1dc +.def 0 + 1 - - - - - 1 + 0 1 - - - - 1 + 0 0 1 - - - 1 + 0 0 0 1 - - 1 + 0 0 0 0 1 - 1 + 0 0 0 0 0 1 1 +.names _n1dc waiting$abort$raw_n1d8 waiting _n1dd +1 0 - 0 +1 1 - 1 +0 - 0 0 +0 - 1 1 +# non-blocking assignments +# latches +.r waiting$raw_n1a0 waiting +0 0 +1 1 +.latch _n1dd waiting +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/gigamax/gigamax.v =================================================================== --- vis_dev/vis-2.1/examples/gigamax/gigamax.v (revision 11) +++ vis_dev/vis-2.1/examples/gigamax/gigamax.v (revision 11) @@ -0,0 +1,259 @@ +/* + * gigamax.v + * + * author: Szu-Tsung Cheng (stcheng@ic.berkeley.edu) + * date: 7/26/93 + * + * A verilog program using symbolic extension of vl2mv for + * gigamax multiprocessor distributed, shared memory architecture + * + * from the example of gigamax.smv example in SMV system by + * K. L. McMillan, et. al. + */ + +typedef enum { idle, read_shared, read_owned, write_invalid, write_shared, + write_resp_invalid, write_resp_shared, invalidate, response } + command; +typedef enum { invalid, shared, owned } status; +typedef enum {r0,r1,r2,r3,r4,r5,r6,r7,r8} nine; + + +module main (clk); + +input clk; + +command wire CMD; +wire REPLY_OWNED, REPLY_WAITING, REPLY_STALL; +command wire p0_cmd, p1_cmd, p2_cmd, m_cmd; +wire p0_master, p0_reply_owned, p0_reply_waiting, p0_reply_stall, + p1_master, p1_reply_owned, p1_reply_waiting, p1_reply_stall, + p2_master, p2_reply_owned, p2_reply_waiting, p2_reply_stall, + m_master, m_reply_owned, m_reply_waiting, m_reply_stall; +command wire nond_CMD; +wire nond0_master; +wire nond1_master; +wire nond2_master; +wire nondm_master; + +processor p0(clk, CMD, p0_master, REPLY_OWNED, REPLY_WAITING, REPLY_STALL, + p0_cmd, p0_reply_owned, p0_reply_waiting, p0_reply_stall); +processor p1(clk, CMD, p1_master, REPLY_OWNED, REPLY_WAITING, REPLY_STALL, + p1_cmd, p1_reply_owned, p1_reply_waiting, p1_reply_stall); +processor p2(clk, CMD, p2_master, REPLY_OWNED, REPLY_WAITING, REPLY_STALL, + p2_cmd, p2_reply_owned, p2_reply_waiting, p2_reply_stall); +memory m(clk, CMD, m_master, REPLY_OWNED, REPLY_WAITING, REPLY_STALL, + m_cmd, m_reply_owned, m_reply_waiting, m_reply_stall); + +assign REPLY_OWNED = p0_reply_owned | p1_reply_owned | p2_reply_owned, + REPLY_WAITING = p0_reply_waiting | p1_reply_waiting | p2_reply_waiting, + REPLY_STALL = p0_reply_stall | p1_reply_stall | p2_reply_stall | + m_reply_stall; + +assign CMD = (p1_cmd==idle && p2_cmd==idle && m_cmd==idle) ? p0_cmd : + (p0_cmd==idle && p2_cmd==idle && m_cmd==idle) ? p1_cmd : + (p0_cmd==idle && p1_cmd==idle && m_cmd==idle) ? p2_cmd : + (p0_cmd==idle && p1_cmd==idle && p2_cmd==idle) ? m_cmd : nond_CMD; + +assign p0_master = nond0_master; +assign p1_master = (p0_master) ? 0 : nond1_master; +assign p2_master = (p0_master || p1_master) ? 0 : nond2_master; +assign m_master = ( (p0_master || p1_master) || p2_master) ? 0 : nondm_master; + +assign nond0_master = $ND(0,1); +assign nond1_master = $ND(0,1); +assign nond2_master = $ND(0,1); +assign nondm_master = $ND(0,1); + +assign nond_CMD = $ND(idle, read_shared, read_owned, write_invalid, + write_shared, write_resp_invalid, write_resp_shared, invalidate, response); + +endmodule + + + +module cache_device (clk, CMD, master, abort, waiting, state,snoop, reply_owned, + readable, writable); +input clk; +input CMD; +input master; +input abort; +input waiting; +output state; +output snoop; +output reply_owned; +output readable, writable; + +command wire CMD; +wire master; +wire abort; +wire waiting; +status reg state, snoop; +wire readable, writable, reply_owned; + +status wire nond_snoop; +status wire nond_state; + +assign readable = ((state == shared) || (state == owned)) && !waiting; +assign writable = (state == owned) && (!waiting); +assign reply_owned = (!master) && (state == owned); +assign nond_snoop = $ND(shared,owned); +assign nond_state = $ND(shared,invalid); + +initial begin state = invalid; end +initial begin snoop = invalid; end + +always @(posedge clk) begin + + if (abort) begin snoop = snoop; end + else if (!master && state==owned && CMD==read_shared) begin snoop = nond_snoop; end + else if (master && CMD == write_resp_invalid) begin snoop = invalid; end + else if (master && CMD == write_resp_shared) begin snoop = invalid; end + + if (abort) begin state = state; end + else if (master == 1) + begin + case (CMD) + read_shared: begin state = shared; end + read_owned: begin state = owned; end + write_invalid: begin state = invalid; end + write_resp_invalid: begin state = invalid; end + write_shared:begin state = shared; end + write_resp_shared:begin state = shared; end + endcase + end + else if (!master && state == shared && + (CMD == read_owned || CMD == invalidate)) + begin + state = invalid; + end + else if (state == shared) + begin + state = nond_state; + end +end + +endmodule + + + +module bus_device(clk, CMD, master, REPLY_STALL, REPLY_WAITING, + waiting, reply_waiting, abort); +input clk; +input CMD; +input master; +input REPLY_STALL; +input REPLY_WAITING; +output waiting; +output reply_waiting; +output abort; + +command wire CMD; +wire master; +wire REPLY_STALL, REPLY_WAITING; +reg waiting; +wire reply_waiting; +wire abort; + +wire reply_waiting, abort; + +assign reply_waiting = !master && waiting; +assign abort = REPLY_STALL || + ((CMD == read_shared || CMD == read_owned) && REPLY_WAITING); + +initial waiting = 0; +always @(posedge clk) begin + if (abort) begin waiting = waiting; end + else if (master && CMD == read_shared) begin waiting = 1; end + else if (master && CMD == read_owned) begin waiting = 1; end + else if (!master && CMD == response) begin waiting = 0; end + else if (!master && CMD == write_resp_invalid) begin waiting = 0; end + else if (!master && CMD == write_resp_shared) begin waiting = 0; end +end + +endmodule + + + +module processor(clk, CMD, master, REPLY_OWNED, REPLY_WAITING, REPLY_STALL, + cmd, reply_owned, reply_waiting, reply_stall); +input clk; +input CMD; +input master; +input REPLY_OWNED, REPLY_WAITING, REPLY_STALL; +output cmd; +output reply_owned; +output reply_waiting; +output reply_stall; + +command wire CMD; +wire master; +wire REPLY_OWNED, REPLY_WAITING, REPLY_STALL; +command wire cmd; +wire reply_owned, reply_waiting, reply_stall; + +command wire nond_cmd; +wire abort, waiting; +status wire state, snoop; +wire readable, writable; + +bus_device Bdevice(clk, CMD, master, REPLY_STALL, REPLY_WAITING, + waiting, reply_waiting, abort); +cache_device Cdevice(clk, CMD, master, abort, waiting, state,snoop, reply_owned, + readable, writable); + +assign cmd = (master && state==invalid) ? nond_cmd : + (master && state==shared) ? read_owned : + (master && state==owned && snoop==owned) ? write_resp_invalid : + (master && state==owned && snoop==shared) ? write_resp_shared : + (master && state==owned && snoop==invalid) ? write_invalid : idle; + +assign nond_cmd = $ND(read_shared,read_owned); +assign reply_stall = $ND(0,1); +endmodule + + + +module memory (clk, CMD, master, REPLY_OWNED, REPLY_WAITING, REPLY_STALL, + cmd, reply_owned, reply_waiting, reply_stall); +input clk; +input CMD; +input master; +input REPLY_OWNED, REPLY_WAITING, REPLY_STALL; +output cmd; +output reply_owned, reply_waiting, reply_stall; + +command wire CMD; +wire master; +wire REPLY_OWNED, REPLY_WAITING, REPLY_STALL; +command wire cmd; +wire reply_owned, reply_waiting, reply_stall; + +wire abort; +reg busy; +command wire nond_cmd; +wire nond_reply_stall; + +assign reply_owned = 0; +assign reply_waiting = 0; +assign abort = REPLY_STALL || + (CMD == read_shared || CMD == read_owned) && REPLY_WAITING || + (CMD == read_shared || CMD == read_owned) && REPLY_OWNED; + +assign cmd = (master && busy) ? nond_cmd : idle; +assign reply_stall = (busy && (CMD == read_shared || CMD == read_owned || + CMD == write_invalid || CMD == write_shared || + CMD == write_resp_invalid || CMD == write_resp_shared)) ? + 1 : nond_reply_stall; + +assign nond_reply_stall = $ND(0,1); +assign nond_cmd = $ND(response,idle); + +initial busy = 0; + +always @(posedge clk) begin + if (abort) begin busy = busy; end + else if (master && CMD == response)begin busy = 0; end + else if (!master && CMD == read_owned || CMD == read_shared)begin busy = 1; end +end + +endmodule Index: vis_dev/vis-2.1/examples/minmax/README =================================================================== --- vis_dev/vis-2.1/examples/minmax/README (revision 11) +++ vis_dev/vis-2.1/examples/minmax/README (revision 11) @@ -0,0 +1,10 @@ +$Id: README,v 1.1 1997/03/02 02:03:36 fabio Exp $ + +MinMax circuit. Translated into Verilog from the LDS description in +"Verification of Sequential Machines Using Boolean Functional Vectors" +by Coudert, Berthet, and Madre. + +The VIS script computes the reachable states and check the reachability +of a reset state from the other reachable states. + +Author: Fabio Somenzi Index: vis_dev/vis-2.1/examples/minmax/check_result =================================================================== --- vis_dev/vis-2.1/examples/minmax/check_result (revision 11) +++ vis_dev/vis-2.1/examples/minmax/check_result (revision 11) @@ -0,0 +1,3 @@ +BMC: formula failed +BMC: formula failed +BMC: formula failed Index: vis_dev/vis-2.1/examples/minmax/check_script =================================================================== --- vis_dev/vis-2.1/examples/minmax/check_script (revision 11) +++ vis_dev/vis-2.1/examples/minmax/check_script (revision 11) @@ -0,0 +1,6 @@ +read_blif_mv minMax30.mv +flatten_hierarchy +build_partition_maigs +bounded_model_check -s1 -k5 -v1 minMax.ltl +time +quit -s Index: vis_dev/vis-2.1/examples/minmax/minMax.ltl =================================================================== --- vis_dev/vis-2.1/examples/minmax/minMax.ltl (revision 11) +++ vis_dev/vis-2.1/examples/minmax/minMax.ltl (revision 11) @@ -0,0 +1,15 @@ +#FAIL: a specified reset state must eventually be reached from every state. +# This formula fails in spite of the fairness conditions. +G(F(min[8:0]=b111111111 * last[8:0]=0 * max[8:0]=0)); + +#PASS: The non-reset states reachable in one clock cycle from the reset +# states have min == last == max. +G(min[8:0]=b111111111 * max[8:0]=b000000000 -> + X(min[8:0]=b111111111 * max[8:0]=b000000000 + + min[8:0] == last[8:0] * last[8:0] == max[8:0])); + +#PASS: The non-reset states reachable in two clock cycles from the reset +# states have either min == last or last == max. +G(min[8:0]=b111111111 * max[8:0]=b000000000 -> + X:2(min[8:0]=b111111111 * max[8:0]=b000000000 + + min[8:0] == last[8:0] + last[8:0] == max[8:0])); Index: vis_dev/vis-2.1/examples/minmax/minMax.v =================================================================== --- vis_dev/vis-2.1/examples/minmax/minMax.v (revision 11) +++ vis_dev/vis-2.1/examples/minmax/minMax.v (revision 11) @@ -0,0 +1,58 @@ +// MinMax circuit. Translated into Verilog from the LDS description in +// "Verification of Sequential Machines Using Boolean Functional Vectors" +// by Coudert, Berthet, and Madre. +// +// Author: Fabio Somenzi + +module minMax (clock,clear,enable,reset,in,out); + parameter MSB = 29; // index of the MSB + input clock; + input clear; + input enable; + input reset; + input [MSB:0] in; + output [MSB:0] out; + + reg [MSB:0] min; + reg [MSB:0] last; + reg [MSB:0] max; + + wire [MSB:0] sup; + wire [MSB:0] inf; + wire [MSB:0] avg; + wire aux; + + initial begin + min = {MSB+1{1'b1}}; // fill min with all ones. + max = 0; + last = {MSB+1{1'bx}}; + end + + // Next state logic. + assign {avg,aux} = {1'b0,sup} + {1'b0,inf}; // average of min and max + assign sup = (in > max) ? in : max; // unsigned comparison + assign inf = (in < min) ? in : min; + + always @ (posedge clock) begin + if (clear) begin + last = 0; max = 0; min = {MSB+1{1'b1}}; + end else begin + if (!enable) begin + max = 0; min = {MSB+1{1'b1}}; + end else begin + last = in; + if (reset) begin + max = 0; min = {MSB+1{1'b1}}; + end else begin + max = sup; min = inf; + end + end + end + end + + // Output logic. + assign out = clear ? 0 : + !enable ? last : + reset ? in : avg; + +endmodule // minMax Index: vis_dev/vis-2.1/examples/minmax/minMax30.ctl =================================================================== --- vis_dev/vis-2.1/examples/minmax/minMax30.ctl (revision 11) +++ vis_dev/vis-2.1/examples/minmax/minMax30.ctl (revision 11) @@ -0,0 +1,4 @@ +#PASS: a specified reset state can eventually be reached from every +# reachable state. + +AG(EF(min[29:0]=b111111111111111111111111111111 * last[29:0]=0 * max[29:0]=0)); Index: vis_dev/vis-2.1/examples/minmax/minMax30.mv =================================================================== --- vis_dev/vis-2.1/examples/minmax/minMax30.mv (revision 11) +++ vis_dev/vis-2.1/examples/minmax/minMax30.mv (revision 11) @@ -0,0 +1,6015 @@ +# /sda4/tools/Vis1.2/vl2mv/i686/bin/vl2mv -O -o minMax30.mv minMax.v +# version: 0.2 +# date: 18:53:31 03/01/97 (MST) +.model minMax +# I/O ports +.inputs clear +.outputs out<0> out<1> out<2> out<3> out<4> out<5> out<6> out<7> out<8> out<9> out<10> out<11> out<12> out<13> out<14> out<15> out<16> out<17> out<18> out<19> out<20> out<21> out<22> out<23> out<24> out<25> out<26> out<27> out<28> out<29> +.inputs reset +.inputs enable +.inputs in<0> in<1> in<2> in<3> in<4> in<5> in<6> in<7> in<8> in<9> in<10> in<11> in<12> in<13> in<14> in<15> in<16> in<17> in<18> in<19> in<20> in<21> in<22> in<23> in<24> in<25> in<26> in<27> in<28> in<29> +# min = {'b1} +.names _n2 +1 +.names _n2 _n1<0> +- =_n2 +.names _n3 +0 +.names _n4 +1 +.names _n4 _n1<1> +- =_n4 +.names _n5 +0 +.names _n6 +1 +.names _n6 _n1<2> +- =_n6 +.names _n7 +0 +.names _n8 +1 +.names _n8 _n1<3> +- =_n8 +.names _n9 +0 +.names _na +1 +.names _na _n1<4> +- =_na +.names _nb +0 +.names _nc +1 +.names _nc _n1<5> +- =_nc +.names _nd +0 +.names _ne +1 +.names _ne _n1<6> +- =_ne +.names _nf +0 +.names _n10 +1 +.names _n10 _n1<7> +- =_n10 +.names _n11 +0 +.names _n12 +1 +.names _n12 _n1<8> +- =_n12 +.names _n13 +0 +.names _n14 +1 +.names _n14 _n1<9> +- =_n14 +.names _n15 +0 +.names _n16 +1 +.names _n16 _n1<10> +- =_n16 +.names _n17 +0 +.names _n18 +1 +.names _n18 _n1<11> +- =_n18 +.names _n19 +0 +.names _n1a +1 +.names _n1a _n1<12> +- =_n1a +.names _n1b +0 +.names _n1c +1 +.names _n1c _n1<13> +- =_n1c +.names _n1d +0 +.names _n1e +1 +.names _n1e _n1<14> +- =_n1e +.names _n1f +0 +.names _n20 +1 +.names _n20 _n1<15> +- =_n20 +.names _n21 +0 +.names _n22 +1 +.names _n22 _n1<16> +- =_n22 +.names _n23 +0 +.names _n24 +1 +.names _n24 _n1<17> +- =_n24 +.names _n25 +0 +.names _n26 +1 +.names _n26 _n1<18> +- =_n26 +.names _n27 +0 +.names _n28 +1 +.names _n28 _n1<19> +- =_n28 +.names _n29 +0 +.names _n2a +1 +.names _n2a _n1<20> +- =_n2a +.names _n2b +0 +.names _n2c +1 +.names _n2c _n1<21> +- =_n2c +.names _n2d +0 +.names _n2e +1 +.names _n2e _n1<22> +- =_n2e +.names _n2f +0 +.names _n30 +1 +.names _n30 _n1<23> +- =_n30 +.names _n31 +0 +.names _n32 +1 +.names _n32 _n1<24> +- =_n32 +.names _n33 +0 +.names _n34 +1 +.names _n34 _n1<25> +- =_n34 +.names _n35 +0 +.names _n36 +1 +.names _n36 _n1<26> +- =_n36 +.names _n37 +0 +.names _n38 +1 +.names _n38 _n1<27> +- =_n38 +.names _n39 +0 +.names _n3a +1 +.names _n3a _n1<28> +- =_n3a +.names _n3b +0 +.names _n3c +1 +.names _n3c _n1<29> +- =_n3c +.names _n3d +0 +.names _n1<0> min$raw_n0<0> +- =_n1<0> +.names _n1<1> min$raw_n0<1> +- =_n1<1> +.names _n1<2> min$raw_n0<2> +- =_n1<2> +.names _n1<3> min$raw_n0<3> +- =_n1<3> +.names _n1<4> min$raw_n0<4> +- =_n1<4> +.names _n1<5> min$raw_n0<5> +- =_n1<5> +.names _n1<6> min$raw_n0<6> +- =_n1<6> +.names _n1<7> min$raw_n0<7> +- =_n1<7> +.names _n1<8> min$raw_n0<8> +- =_n1<8> +.names _n1<9> min$raw_n0<9> +- =_n1<9> +.names _n1<10> min$raw_n0<10> +- =_n1<10> +.names _n1<11> min$raw_n0<11> +- =_n1<11> +.names _n1<12> min$raw_n0<12> +- =_n1<12> +.names _n1<13> min$raw_n0<13> +- =_n1<13> +.names _n1<14> min$raw_n0<14> +- =_n1<14> +.names _n1<15> min$raw_n0<15> +- =_n1<15> +.names _n1<16> min$raw_n0<16> +- =_n1<16> +.names _n1<17> min$raw_n0<17> +- =_n1<17> +.names _n1<18> min$raw_n0<18> +- =_n1<18> +.names _n1<19> min$raw_n0<19> +- =_n1<19> +.names _n1<20> min$raw_n0<20> +- =_n1<20> +.names _n1<21> min$raw_n0<21> +- =_n1<21> +.names _n1<22> min$raw_n0<22> +- =_n1<22> +.names _n1<23> min$raw_n0<23> +- =_n1<23> +.names _n1<24> min$raw_n0<24> +- =_n1<24> +.names _n1<25> min$raw_n0<25> +- =_n1<25> +.names _n1<26> min$raw_n0<26> +- =_n1<26> +.names _n1<27> min$raw_n0<27> +- =_n1<27> +.names _n1<28> min$raw_n0<28> +- =_n1<28> +.names _n1<29> min$raw_n0<29> +- =_n1<29> +# max = 0 +.names max$raw_n3e<0> +0 +.names max$raw_n3e<1> +0 +.names max$raw_n3e<2> +0 +.names max$raw_n3e<3> +0 +.names max$raw_n3e<4> +0 +.names max$raw_n3e<5> +0 +.names max$raw_n3e<6> +0 +.names max$raw_n3e<7> +0 +.names max$raw_n3e<8> +0 +.names max$raw_n3e<9> +0 +.names max$raw_n3e<10> +0 +.names max$raw_n3e<11> +0 +.names max$raw_n3e<12> +0 +.names max$raw_n3e<13> +0 +.names max$raw_n3e<14> +0 +.names max$raw_n3e<15> +0 +.names max$raw_n3e<16> +0 +.names max$raw_n3e<17> +0 +.names max$raw_n3e<18> +0 +.names max$raw_n3e<19> +0 +.names max$raw_n3e<20> +0 +.names max$raw_n3e<21> +0 +.names max$raw_n3e<22> +0 +.names max$raw_n3e<23> +0 +.names max$raw_n3e<24> +0 +.names max$raw_n3e<25> +0 +.names max$raw_n3e<26> +0 +.names max$raw_n3e<27> +0 +.names max$raw_n3e<28> +0 +.names max$raw_n3e<29> +0 +# last = {'bx} +.names _n41 +0 +.names _n41 _n40<0> +- =_n41 +.names _n42 +0 +.names _n43 +0 +.names _n43 _n40<1> +- =_n43 +.names _n44 +0 +.names _n45 +0 +.names _n45 _n40<2> +- =_n45 +.names _n46 +0 +.names _n47 +0 +.names _n47 _n40<3> +- =_n47 +.names _n48 +0 +.names _n49 +0 +.names _n49 _n40<4> +- =_n49 +.names _n4a +0 +.names _n4b +0 +.names _n4b _n40<5> +- =_n4b +.names _n4c +0 +.names _n4d +0 +.names _n4d _n40<6> +- =_n4d +.names _n4e +0 +.names _n4f +0 +.names _n4f _n40<7> +- =_n4f +.names _n50 +0 +.names _n51 +0 +.names _n51 _n40<8> +- =_n51 +.names _n52 +0 +.names _n53 +0 +.names _n53 _n40<9> +- =_n53 +.names _n54 +0 +.names _n55 +0 +.names _n55 _n40<10> +- =_n55 +.names _n56 +0 +.names _n57 +0 +.names _n57 _n40<11> +- =_n57 +.names _n58 +0 +.names _n59 +0 +.names _n59 _n40<12> +- =_n59 +.names _n5a +0 +.names _n5b +0 +.names _n5b _n40<13> +- =_n5b +.names _n5c +0 +.names _n5d +0 +.names _n5d _n40<14> +- =_n5d +.names _n5e +0 +.names _n5f +0 +.names _n5f _n40<15> +- =_n5f +.names _n60 +0 +.names _n61 +0 +.names _n61 _n40<16> +- =_n61 +.names _n62 +0 +.names _n63 +0 +.names _n63 _n40<17> +- =_n63 +.names _n64 +0 +.names _n65 +0 +.names _n65 _n40<18> +- =_n65 +.names _n66 +0 +.names _n67 +0 +.names _n67 _n40<19> +- =_n67 +.names _n68 +0 +.names _n69 +0 +.names _n69 _n40<20> +- =_n69 +.names _n6a +0 +.names _n6b +0 +.names _n6b _n40<21> +- =_n6b +.names _n6c +0 +.names _n6d +0 +.names _n6d _n40<22> +- =_n6d +.names _n6e +0 +.names _n6f +0 +.names _n6f _n40<23> +- =_n6f +.names _n70 +0 +.names _n71 +0 +.names _n71 _n40<24> +- =_n71 +.names _n72 +0 +.names _n73 +0 +.names _n73 _n40<25> +- =_n73 +.names _n74 +0 +.names _n75 +0 +.names _n75 _n40<26> +- =_n75 +.names _n76 +0 +.names _n77 +0 +.names _n77 _n40<27> +- =_n77 +.names _n78 +0 +.names _n79 +0 +.names _n79 _n40<28> +- =_n79 +.names _n7a +0 +.names _n7b +0 +.names _n7b _n40<29> +- =_n7b +.names _n7c +0 +.names _n40<0> last$raw_n3f<0> +- =_n40<0> +.names _n40<1> last$raw_n3f<1> +- =_n40<1> +.names _n40<2> last$raw_n3f<2> +- =_n40<2> +.names _n40<3> last$raw_n3f<3> +- =_n40<3> +.names _n40<4> last$raw_n3f<4> +- =_n40<4> +.names _n40<5> last$raw_n3f<5> +- =_n40<5> +.names _n40<6> last$raw_n3f<6> +- =_n40<6> +.names _n40<7> last$raw_n3f<7> +- =_n40<7> +.names _n40<8> last$raw_n3f<8> +- =_n40<8> +.names _n40<9> last$raw_n3f<9> +- =_n40<9> +.names _n40<10> last$raw_n3f<10> +- =_n40<10> +.names _n40<11> last$raw_n3f<11> +- =_n40<11> +.names _n40<12> last$raw_n3f<12> +- =_n40<12> +.names _n40<13> last$raw_n3f<13> +- =_n40<13> +.names _n40<14> last$raw_n3f<14> +- =_n40<14> +.names _n40<15> last$raw_n3f<15> +- =_n40<15> +.names _n40<16> last$raw_n3f<16> +- =_n40<16> +.names _n40<17> last$raw_n3f<17> +- =_n40<17> +.names _n40<18> last$raw_n3f<18> +- =_n40<18> +.names _n40<19> last$raw_n3f<19> +- =_n40<19> +.names _n40<20> last$raw_n3f<20> +- =_n40<20> +.names _n40<21> last$raw_n3f<21> +- =_n40<21> +.names _n40<22> last$raw_n3f<22> +- =_n40<22> +.names _n40<23> last$raw_n3f<23> +- =_n40<23> +.names _n40<24> last$raw_n3f<24> +- =_n40<24> +.names _n40<25> last$raw_n3f<25> +- =_n40<25> +.names _n40<26> last$raw_n3f<26> +- =_n40<26> +.names _n40<27> last$raw_n3f<27> +- =_n40<27> +.names _n40<28> last$raw_n3f<28> +- =_n40<28> +.names _n40<29> last$raw_n3f<29> +- =_n40<29> +# non-blocking assignments for initial +# assign {avg , aux } = {'b0, sup } + {'b0, inf } +.names sup<0> _n80<0> +- =sup<0> +.names sup<1> _n80<1> +- =sup<1> +.names sup<2> _n80<2> +- =sup<2> +.names sup<3> _n80<3> +- =sup<3> +.names sup<4> _n80<4> +- =sup<4> +.names sup<5> _n80<5> +- =sup<5> +.names sup<6> _n80<6> +- =sup<6> +.names sup<7> _n80<7> +- =sup<7> +.names sup<8> _n80<8> +- =sup<8> +.names sup<9> _n80<9> +- =sup<9> +.names sup<10> _n80<10> +- =sup<10> +.names sup<11> _n80<11> +- =sup<11> +.names sup<12> _n80<12> +- =sup<12> +.names sup<13> _n80<13> +- =sup<13> +.names sup<14> _n80<14> +- =sup<14> +.names sup<15> _n80<15> +- =sup<15> +.names sup<16> _n80<16> +- =sup<16> +.names sup<17> _n80<17> +- =sup<17> +.names sup<18> _n80<18> +- =sup<18> +.names sup<19> _n80<19> +- =sup<19> +.names sup<20> _n80<20> +- =sup<20> +.names sup<21> _n80<21> +- =sup<21> +.names sup<22> _n80<22> +- =sup<22> +.names sup<23> _n80<23> +- =sup<23> +.names sup<24> _n80<24> +- =sup<24> +.names sup<25> _n80<25> +- =sup<25> +.names sup<26> _n80<26> +- =sup<26> +.names sup<27> _n80<27> +- =sup<27> +.names sup<28> _n80<28> +- =sup<28> +.names sup<29> _n80<29> +- =sup<29> +.names _n81 +0 +.names _n81 _n80<30> +- =_n81 +.names _n82 +0 +.names inf<0> _n83<0> +- =inf<0> +.names inf<1> _n83<1> +- =inf<1> +.names inf<2> _n83<2> +- =inf<2> +.names inf<3> _n83<3> +- =inf<3> +.names inf<4> _n83<4> +- =inf<4> +.names inf<5> _n83<5> +- =inf<5> +.names inf<6> _n83<6> +- =inf<6> +.names inf<7> _n83<7> +- =inf<7> +.names inf<8> _n83<8> +- =inf<8> +.names inf<9> _n83<9> +- =inf<9> +.names inf<10> _n83<10> +- =inf<10> +.names inf<11> _n83<11> +- =inf<11> +.names inf<12> _n83<12> +- =inf<12> +.names inf<13> _n83<13> +- =inf<13> +.names inf<14> _n83<14> +- =inf<14> +.names inf<15> _n83<15> +- =inf<15> +.names inf<16> _n83<16> +- =inf<16> +.names inf<17> _n83<17> +- =inf<17> +.names inf<18> _n83<18> +- =inf<18> +.names inf<19> _n83<19> +- =inf<19> +.names inf<20> _n83<20> +- =inf<20> +.names inf<21> _n83<21> +- =inf<21> +.names inf<22> _n83<22> +- =inf<22> +.names inf<23> _n83<23> +- =inf<23> +.names inf<24> _n83<24> +- =inf<24> +.names inf<25> _n83<25> +- =inf<25> +.names inf<26> _n83<26> +- =inf<26> +.names inf<27> _n83<27> +- =inf<27> +.names inf<28> _n83<28> +- =inf<28> +.names inf<29> _n83<29> +- =inf<29> +.names _n84 +0 +.names _n84 _n83<30> +- =_n84 +.names _n85 +0 +# {'b0, sup } + {'b0, inf } +.names _n87 +0 +.names _n80<0> _n83<0> _n87 _n86<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n89 +0 +.names _n80<0> _n83<0> _n89 _n88 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<1> _n83<1> _n88 _n86<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<1> _n83<1> _n88 _n8a +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<2> _n83<2> _n8a _n86<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<2> _n83<2> _n8a _n8b +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<3> _n83<3> _n8b _n86<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<3> _n83<3> _n8b _n8c +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<4> _n83<4> _n8c _n86<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<4> _n83<4> _n8c _n8d +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<5> _n83<5> _n8d _n86<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<5> _n83<5> _n8d _n8e +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<6> _n83<6> _n8e _n86<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<6> _n83<6> _n8e _n8f +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<7> _n83<7> _n8f _n86<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<7> _n83<7> _n8f _n90 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<8> _n83<8> _n90 _n86<8> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<8> _n83<8> _n90 _n91 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<9> _n83<9> _n91 _n86<9> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<9> _n83<9> _n91 _n92 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<10> _n83<10> _n92 _n86<10> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<10> _n83<10> _n92 _n93 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<11> _n83<11> _n93 _n86<11> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<11> _n83<11> _n93 _n94 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<12> _n83<12> _n94 _n86<12> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<12> _n83<12> _n94 _n95 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<13> _n83<13> _n95 _n86<13> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<13> _n83<13> _n95 _n96 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<14> _n83<14> _n96 _n86<14> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<14> _n83<14> _n96 _n97 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<15> _n83<15> _n97 _n86<15> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<15> _n83<15> _n97 _n98 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<16> _n83<16> _n98 _n86<16> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<16> _n83<16> _n98 _n99 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<17> _n83<17> _n99 _n86<17> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<17> _n83<17> _n99 _n9a +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<18> _n83<18> _n9a _n86<18> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<18> _n83<18> _n9a _n9b +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<19> _n83<19> _n9b _n86<19> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<19> _n83<19> _n9b _n9c +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<20> _n83<20> _n9c _n86<20> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<20> _n83<20> _n9c _n9d +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<21> _n83<21> _n9d _n86<21> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<21> _n83<21> _n9d _n9e +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<22> _n83<22> _n9e _n86<22> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<22> _n83<22> _n9e _n9f +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<23> _n83<23> _n9f _n86<23> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<23> _n83<23> _n9f _na0 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<24> _n83<24> _na0 _n86<24> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<24> _n83<24> _na0 _na1 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<25> _n83<25> _na1 _n86<25> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<25> _n83<25> _na1 _na2 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<26> _n83<26> _na2 _n86<26> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<26> _n83<26> _na2 _na3 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<27> _n83<27> _na3 _n86<27> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<27> _n83<27> _na3 _na4 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<28> _n83<28> _na4 _n86<28> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<28> _n83<28> _na4 _na5 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<29> _n83<29> _na5 _n86<29> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n80<29> _n83<29> _na5 _na6 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n80<30> _n83<30> _na6 _n86<30> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n86<0> _n7f<0> +- =_n86<0> +.names _n86<1> _n7f<1> +- =_n86<1> +.names _n86<2> _n7f<2> +- =_n86<2> +.names _n86<3> _n7f<3> +- =_n86<3> +.names _n86<4> _n7f<4> +- =_n86<4> +.names _n86<5> _n7f<5> +- =_n86<5> +.names _n86<6> _n7f<6> +- =_n86<6> +.names _n86<7> _n7f<7> +- =_n86<7> +.names _n86<8> _n7f<8> +- =_n86<8> +.names _n86<9> _n7f<9> +- =_n86<9> +.names _n86<10> _n7f<10> +- =_n86<10> +.names _n86<11> _n7f<11> +- =_n86<11> +.names _n86<12> _n7f<12> +- =_n86<12> +.names _n86<13> _n7f<13> +- =_n86<13> +.names _n86<14> _n7f<14> +- =_n86<14> +.names _n86<15> _n7f<15> +- =_n86<15> +.names _n86<16> _n7f<16> +- =_n86<16> +.names _n86<17> _n7f<17> +- =_n86<17> +.names _n86<18> _n7f<18> +- =_n86<18> +.names _n86<19> _n7f<19> +- =_n86<19> +.names _n86<20> _n7f<20> +- =_n86<20> +.names _n86<21> _n7f<21> +- =_n86<21> +.names _n86<22> _n7f<22> +- =_n86<22> +.names _n86<23> _n7f<23> +- =_n86<23> +.names _n86<24> _n7f<24> +- =_n86<24> +.names _n86<25> _n7f<25> +- =_n86<25> +.names _n86<26> _n7f<26> +- =_n86<26> +.names _n86<27> _n7f<27> +- =_n86<27> +.names _n86<28> _n7f<28> +- =_n86<28> +.names _n86<29> _n7f<29> +- =_n86<29> +.names _n86<30> _n7f<30> +- =_n86<30> +.names _n7f<0> aux$raw_n7e +- =_n7f<0> +.names _n7f<1> avg$raw_n7d<0> +- =_n7f<1> +.names _n7f<2> avg$raw_n7d<1> +- =_n7f<2> +.names _n7f<3> avg$raw_n7d<2> +- =_n7f<3> +.names _n7f<4> avg$raw_n7d<3> +- =_n7f<4> +.names _n7f<5> avg$raw_n7d<4> +- =_n7f<5> +.names _n7f<6> avg$raw_n7d<5> +- =_n7f<6> +.names _n7f<7> avg$raw_n7d<6> +- =_n7f<7> +.names _n7f<8> avg$raw_n7d<7> +- =_n7f<8> +.names _n7f<9> avg$raw_n7d<8> +- =_n7f<9> +.names _n7f<10> avg$raw_n7d<9> +- =_n7f<10> +.names _n7f<11> avg$raw_n7d<10> +- =_n7f<11> +.names _n7f<12> avg$raw_n7d<11> +- =_n7f<12> +.names _n7f<13> avg$raw_n7d<12> +- =_n7f<13> +.names _n7f<14> avg$raw_n7d<13> +- =_n7f<14> +.names _n7f<15> avg$raw_n7d<14> +- =_n7f<15> +.names _n7f<16> avg$raw_n7d<15> +- =_n7f<16> +.names _n7f<17> avg$raw_n7d<16> +- =_n7f<17> +.names _n7f<18> avg$raw_n7d<17> +- =_n7f<18> +.names _n7f<19> avg$raw_n7d<18> +- =_n7f<19> +.names _n7f<20> avg$raw_n7d<19> +- =_n7f<20> +.names _n7f<21> avg$raw_n7d<20> +- =_n7f<21> +.names _n7f<22> avg$raw_n7d<21> +- =_n7f<22> +.names _n7f<23> avg$raw_n7d<22> +- =_n7f<23> +.names _n7f<24> avg$raw_n7d<23> +- =_n7f<24> +.names _n7f<25> avg$raw_n7d<24> +- =_n7f<25> +.names _n7f<26> avg$raw_n7d<25> +- =_n7f<26> +.names _n7f<27> avg$raw_n7d<26> +- =_n7f<27> +.names _n7f<28> avg$raw_n7d<27> +- =_n7f<28> +.names _n7f<29> avg$raw_n7d<28> +- =_n7f<29> +.names _n7f<30> avg$raw_n7d<29> +- =_n7f<30> +# assign sup = (in > max ) ? in : max +# in > max +.names _naa +0 +.names in<0> max<0> _naa _na9<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _nac +0 +.names in<0> max<0> _nac _nab +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<1> max<1> _nab _na9<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<1> max<1> _nab _nad +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<2> max<2> _nad _na9<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<2> max<2> _nad _nae +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<3> max<3> _nae _na9<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<3> max<3> _nae _naf +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<4> max<4> _naf _na9<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<4> max<4> _naf _nb0 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<5> max<5> _nb0 _na9<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<5> max<5> _nb0 _nb1 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<6> max<6> _nb1 _na9<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<6> max<6> _nb1 _nb2 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<7> max<7> _nb2 _na9<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<7> max<7> _nb2 _nb3 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<8> max<8> _nb3 _na9<8> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<8> max<8> _nb3 _nb4 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<9> max<9> _nb4 _na9<9> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<9> max<9> _nb4 _nb5 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<10> max<10> _nb5 _na9<10> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<10> max<10> _nb5 _nb6 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<11> max<11> _nb6 _na9<11> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<11> max<11> _nb6 _nb7 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<12> max<12> _nb7 _na9<12> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<12> max<12> _nb7 _nb8 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<13> max<13> _nb8 _na9<13> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<13> max<13> _nb8 _nb9 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<14> max<14> _nb9 _na9<14> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<14> max<14> _nb9 _nba +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<15> max<15> _nba _na9<15> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<15> max<15> _nba _nbb +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<16> max<16> _nbb _na9<16> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<16> max<16> _nbb _nbc +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<17> max<17> _nbc _na9<17> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<17> max<17> _nbc _nbd +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<18> max<18> _nbd _na9<18> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<18> max<18> _nbd _nbe +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<19> max<19> _nbe _na9<19> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<19> max<19> _nbe _nbf +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<20> max<20> _nbf _na9<20> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<20> max<20> _nbf _nc0 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<21> max<21> _nc0 _na9<21> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<21> max<21> _nc0 _nc1 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<22> max<22> _nc1 _na9<22> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<22> max<22> _nc1 _nc2 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<23> max<23> _nc2 _na9<23> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<23> max<23> _nc2 _nc3 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<24> max<24> _nc3 _na9<24> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<24> max<24> _nc3 _nc4 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<25> max<25> _nc4 _na9<25> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<25> max<25> _nc4 _nc5 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<26> max<26> _nc5 _na9<26> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<26> max<26> _nc5 _nc6 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<27> max<27> _nc6 _na9<27> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<27> max<27> _nc6 _nc7 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<28> max<28> _nc7 _na9<28> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<28> max<28> _nc7 _nc8 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<29> max<29> _nc8 _na9<29> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<29> max<29> _nc8 _nc9 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _na9<0> _na9<1> _na9<2> _na9<3> _na9<4> _na9<5> _na9<6> _na9<7> _na9<8> _na9<9> _na9<10> _na9<11> _na9<12> _na9<13> _na9<14> _na9<15> _na9<16> _na9<17> _na9<18> _na9<19> _na9<20> _na9<21> _na9<22> _na9<23> _na9<24> _na9<25> _na9<26> _na9<27> _na9<28> _na9<29> _nca +.def 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +.names _nc9 _nca _ncb +.def 1 +0 0 0 +.names _ncb _na8 +0 1 +1 0 +# (in > max ) ? in : max +.names in<0> max<0> _na8 _ncc<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<1> max<1> _na8 _ncc<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<2> max<2> _na8 _ncc<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<3> max<3> _na8 _ncc<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<4> max<4> _na8 _ncc<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<5> max<5> _na8 _ncc<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<6> max<6> _na8 _ncc<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<7> max<7> _na8 _ncc<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<8> max<8> _na8 _ncc<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<9> max<9> _na8 _ncc<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<10> max<10> _na8 _ncc<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<11> max<11> _na8 _ncc<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<12> max<12> _na8 _ncc<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<13> max<13> _na8 _ncc<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<14> max<14> _na8 _ncc<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<15> max<15> _na8 _ncc<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<16> max<16> _na8 _ncc<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<17> max<17> _na8 _ncc<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<18> max<18> _na8 _ncc<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<19> max<19> _na8 _ncc<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<20> max<20> _na8 _ncc<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<21> max<21> _na8 _ncc<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<22> max<22> _na8 _ncc<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<23> max<23> _na8 _ncc<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<24> max<24> _na8 _ncc<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<25> max<25> _na8 _ncc<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<26> max<26> _na8 _ncc<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<27> max<27> _na8 _ncc<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<28> max<28> _na8 _ncc<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<29> max<29> _na8 _ncc<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _ncc<0> sup$raw_na7<0> +- =_ncc<0> +.names _ncc<1> sup$raw_na7<1> +- =_ncc<1> +.names _ncc<2> sup$raw_na7<2> +- =_ncc<2> +.names _ncc<3> sup$raw_na7<3> +- =_ncc<3> +.names _ncc<4> sup$raw_na7<4> +- =_ncc<4> +.names _ncc<5> sup$raw_na7<5> +- =_ncc<5> +.names _ncc<6> sup$raw_na7<6> +- =_ncc<6> +.names _ncc<7> sup$raw_na7<7> +- =_ncc<7> +.names _ncc<8> sup$raw_na7<8> +- =_ncc<8> +.names _ncc<9> sup$raw_na7<9> +- =_ncc<9> +.names _ncc<10> sup$raw_na7<10> +- =_ncc<10> +.names _ncc<11> sup$raw_na7<11> +- =_ncc<11> +.names _ncc<12> sup$raw_na7<12> +- =_ncc<12> +.names _ncc<13> sup$raw_na7<13> +- =_ncc<13> +.names _ncc<14> sup$raw_na7<14> +- =_ncc<14> +.names _ncc<15> sup$raw_na7<15> +- =_ncc<15> +.names _ncc<16> sup$raw_na7<16> +- =_ncc<16> +.names _ncc<17> sup$raw_na7<17> +- =_ncc<17> +.names _ncc<18> sup$raw_na7<18> +- =_ncc<18> +.names _ncc<19> sup$raw_na7<19> +- =_ncc<19> +.names _ncc<20> sup$raw_na7<20> +- =_ncc<20> +.names _ncc<21> sup$raw_na7<21> +- =_ncc<21> +.names _ncc<22> sup$raw_na7<22> +- =_ncc<22> +.names _ncc<23> sup$raw_na7<23> +- =_ncc<23> +.names _ncc<24> sup$raw_na7<24> +- =_ncc<24> +.names _ncc<25> sup$raw_na7<25> +- =_ncc<25> +.names _ncc<26> sup$raw_na7<26> +- =_ncc<26> +.names _ncc<27> sup$raw_na7<27> +- =_ncc<27> +.names _ncc<28> sup$raw_na7<28> +- =_ncc<28> +.names _ncc<29> sup$raw_na7<29> +- =_ncc<29> +# assign inf = (in < min ) ? in : min +# in < min +.names _nee +0 +.names in<0> min<0> _nee _ned<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _nf0 +0 +.names in<0> min<0> _nf0 _nef +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<1> min<1> _nef _ned<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<1> min<1> _nef _nf1 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<2> min<2> _nf1 _ned<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<2> min<2> _nf1 _nf2 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<3> min<3> _nf2 _ned<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<3> min<3> _nf2 _nf3 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<4> min<4> _nf3 _ned<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<4> min<4> _nf3 _nf4 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<5> min<5> _nf4 _ned<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<5> min<5> _nf4 _nf5 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<6> min<6> _nf5 _ned<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<6> min<6> _nf5 _nf6 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<7> min<7> _nf6 _ned<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<7> min<7> _nf6 _nf7 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<8> min<8> _nf7 _ned<8> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<8> min<8> _nf7 _nf8 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<9> min<9> _nf8 _ned<9> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<9> min<9> _nf8 _nf9 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<10> min<10> _nf9 _ned<10> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<10> min<10> _nf9 _nfa +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<11> min<11> _nfa _ned<11> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<11> min<11> _nfa _nfb +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<12> min<12> _nfb _ned<12> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<12> min<12> _nfb _nfc +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<13> min<13> _nfc _ned<13> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<13> min<13> _nfc _nfd +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<14> min<14> _nfd _ned<14> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<14> min<14> _nfd _nfe +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<15> min<15> _nfe _ned<15> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<15> min<15> _nfe _nff +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<16> min<16> _nff _ned<16> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<16> min<16> _nff _n100 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<17> min<17> _n100 _ned<17> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<17> min<17> _n100 _n101 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<18> min<18> _n101 _ned<18> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<18> min<18> _n101 _n102 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<19> min<19> _n102 _ned<19> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<19> min<19> _n102 _n103 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<20> min<20> _n103 _ned<20> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<20> min<20> _n103 _n104 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<21> min<21> _n104 _ned<21> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<21> min<21> _n104 _n105 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<22> min<22> _n105 _ned<22> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<22> min<22> _n105 _n106 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<23> min<23> _n106 _ned<23> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<23> min<23> _n106 _n107 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<24> min<24> _n107 _ned<24> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<24> min<24> _n107 _n108 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<25> min<25> _n108 _ned<25> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<25> min<25> _n108 _n109 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<26> min<26> _n109 _ned<26> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<26> min<26> _n109 _n10a +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<27> min<27> _n10a _ned<27> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<27> min<27> _n10a _n10b +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<28> min<28> _n10b _ned<28> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<28> min<28> _n10b _n10c +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names in<29> min<29> _n10c _ned<29> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names in<29> min<29> _n10c _n10d +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _ned<0> _ned<1> _ned<2> _ned<3> _ned<4> _ned<5> _ned<6> _ned<7> _ned<8> _ned<9> _ned<10> _ned<11> _ned<12> _ned<13> _ned<14> _ned<15> _ned<16> _ned<17> _ned<18> _ned<19> _ned<20> _ned<21> _ned<22> _ned<23> _ned<24> _ned<25> _ned<26> _ned<27> _ned<28> _ned<29> _n10e +.def 1 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +.names _n10d _n10e _nec +.def 0 +1 1 1 +# (in < min ) ? in : min +.names in<0> min<0> _nec _n10f<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<1> min<1> _nec _n10f<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<2> min<2> _nec _n10f<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<3> min<3> _nec _n10f<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<4> min<4> _nec _n10f<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<5> min<5> _nec _n10f<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<6> min<6> _nec _n10f<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<7> min<7> _nec _n10f<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<8> min<8> _nec _n10f<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<9> min<9> _nec _n10f<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<10> min<10> _nec _n10f<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<11> min<11> _nec _n10f<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<12> min<12> _nec _n10f<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<13> min<13> _nec _n10f<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<14> min<14> _nec _n10f<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<15> min<15> _nec _n10f<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<16> min<16> _nec _n10f<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<17> min<17> _nec _n10f<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<18> min<18> _nec _n10f<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<19> min<19> _nec _n10f<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<20> min<20> _nec _n10f<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<21> min<21> _nec _n10f<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<22> min<22> _nec _n10f<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<23> min<23> _nec _n10f<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<24> min<24> _nec _n10f<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<25> min<25> _nec _n10f<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<26> min<26> _nec _n10f<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<27> min<27> _nec _n10f<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<28> min<28> _nec _n10f<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<29> min<29> _nec _n10f<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n10f<0> inf$raw_neb<0> +- =_n10f<0> +.names _n10f<1> inf$raw_neb<1> +- =_n10f<1> +.names _n10f<2> inf$raw_neb<2> +- =_n10f<2> +.names _n10f<3> inf$raw_neb<3> +- =_n10f<3> +.names _n10f<4> inf$raw_neb<4> +- =_n10f<4> +.names _n10f<5> inf$raw_neb<5> +- =_n10f<5> +.names _n10f<6> inf$raw_neb<6> +- =_n10f<6> +.names _n10f<7> inf$raw_neb<7> +- =_n10f<7> +.names _n10f<8> inf$raw_neb<8> +- =_n10f<8> +.names _n10f<9> inf$raw_neb<9> +- =_n10f<9> +.names _n10f<10> inf$raw_neb<10> +- =_n10f<10> +.names _n10f<11> inf$raw_neb<11> +- =_n10f<11> +.names _n10f<12> inf$raw_neb<12> +- =_n10f<12> +.names _n10f<13> inf$raw_neb<13> +- =_n10f<13> +.names _n10f<14> inf$raw_neb<14> +- =_n10f<14> +.names _n10f<15> inf$raw_neb<15> +- =_n10f<15> +.names _n10f<16> inf$raw_neb<16> +- =_n10f<16> +.names _n10f<17> inf$raw_neb<17> +- =_n10f<17> +.names _n10f<18> inf$raw_neb<18> +- =_n10f<18> +.names _n10f<19> inf$raw_neb<19> +- =_n10f<19> +.names _n10f<20> inf$raw_neb<20> +- =_n10f<20> +.names _n10f<21> inf$raw_neb<21> +- =_n10f<21> +.names _n10f<22> inf$raw_neb<22> +- =_n10f<22> +.names _n10f<23> inf$raw_neb<23> +- =_n10f<23> +.names _n10f<24> inf$raw_neb<24> +- =_n10f<24> +.names _n10f<25> inf$raw_neb<25> +- =_n10f<25> +.names _n10f<26> inf$raw_neb<26> +- =_n10f<26> +.names _n10f<27> inf$raw_neb<27> +- =_n10f<27> +.names _n10f<28> inf$raw_neb<28> +- =_n10f<28> +.names _n10f<29> inf$raw_neb<29> +- =_n10f<29> +.names clear _n12e +- =clear +# last = 0 +.names last$clear_n12f$true<0> +0 +.names last$clear_n12f$true<1> +0 +.names last$clear_n12f$true<2> +0 +.names last$clear_n12f$true<3> +0 +.names last$clear_n12f$true<4> +0 +.names last$clear_n12f$true<5> +0 +.names last$clear_n12f$true<6> +0 +.names last$clear_n12f$true<7> +0 +.names last$clear_n12f$true<8> +0 +.names last$clear_n12f$true<9> +0 +.names last$clear_n12f$true<10> +0 +.names last$clear_n12f$true<11> +0 +.names last$clear_n12f$true<12> +0 +.names last$clear_n12f$true<13> +0 +.names last$clear_n12f$true<14> +0 +.names last$clear_n12f$true<15> +0 +.names last$clear_n12f$true<16> +0 +.names last$clear_n12f$true<17> +0 +.names last$clear_n12f$true<18> +0 +.names last$clear_n12f$true<19> +0 +.names last$clear_n12f$true<20> +0 +.names last$clear_n12f$true<21> +0 +.names last$clear_n12f$true<22> +0 +.names last$clear_n12f$true<23> +0 +.names last$clear_n12f$true<24> +0 +.names last$clear_n12f$true<25> +0 +.names last$clear_n12f$true<26> +0 +.names last$clear_n12f$true<27> +0 +.names last$clear_n12f$true<28> +0 +.names last$clear_n12f$true<29> +0 +# max = 0 +.names max$clear_n130$true<0> +0 +.names max$clear_n130$true<1> +0 +.names max$clear_n130$true<2> +0 +.names max$clear_n130$true<3> +0 +.names max$clear_n130$true<4> +0 +.names max$clear_n130$true<5> +0 +.names max$clear_n130$true<6> +0 +.names max$clear_n130$true<7> +0 +.names max$clear_n130$true<8> +0 +.names max$clear_n130$true<9> +0 +.names max$clear_n130$true<10> +0 +.names max$clear_n130$true<11> +0 +.names max$clear_n130$true<12> +0 +.names max$clear_n130$true<13> +0 +.names max$clear_n130$true<14> +0 +.names max$clear_n130$true<15> +0 +.names max$clear_n130$true<16> +0 +.names max$clear_n130$true<17> +0 +.names max$clear_n130$true<18> +0 +.names max$clear_n130$true<19> +0 +.names max$clear_n130$true<20> +0 +.names max$clear_n130$true<21> +0 +.names max$clear_n130$true<22> +0 +.names max$clear_n130$true<23> +0 +.names max$clear_n130$true<24> +0 +.names max$clear_n130$true<25> +0 +.names max$clear_n130$true<26> +0 +.names max$clear_n130$true<27> +0 +.names max$clear_n130$true<28> +0 +.names max$clear_n130$true<29> +0 +# min = {'b1} +.names _n133 +1 +.names _n133 _n132<0> +- =_n133 +.names _n134 +0 +.names _n135 +1 +.names _n135 _n132<1> +- =_n135 +.names _n136 +0 +.names _n137 +1 +.names _n137 _n132<2> +- =_n137 +.names _n138 +0 +.names _n139 +1 +.names _n139 _n132<3> +- =_n139 +.names _n13a +0 +.names _n13b +1 +.names _n13b _n132<4> +- =_n13b +.names _n13c +0 +.names _n13d +1 +.names _n13d _n132<5> +- =_n13d +.names _n13e +0 +.names _n13f +1 +.names _n13f _n132<6> +- =_n13f +.names _n140 +0 +.names _n141 +1 +.names _n141 _n132<7> +- =_n141 +.names _n142 +0 +.names _n143 +1 +.names _n143 _n132<8> +- =_n143 +.names _n144 +0 +.names _n145 +1 +.names _n145 _n132<9> +- =_n145 +.names _n146 +0 +.names _n147 +1 +.names _n147 _n132<10> +- =_n147 +.names _n148 +0 +.names _n149 +1 +.names _n149 _n132<11> +- =_n149 +.names _n14a +0 +.names _n14b +1 +.names _n14b _n132<12> +- =_n14b +.names _n14c +0 +.names _n14d +1 +.names _n14d _n132<13> +- =_n14d +.names _n14e +0 +.names _n14f +1 +.names _n14f _n132<14> +- =_n14f +.names _n150 +0 +.names _n151 +1 +.names _n151 _n132<15> +- =_n151 +.names _n152 +0 +.names _n153 +1 +.names _n153 _n132<16> +- =_n153 +.names _n154 +0 +.names _n155 +1 +.names _n155 _n132<17> +- =_n155 +.names _n156 +0 +.names _n157 +1 +.names _n157 _n132<18> +- =_n157 +.names _n158 +0 +.names _n159 +1 +.names _n159 _n132<19> +- =_n159 +.names _n15a +0 +.names _n15b +1 +.names _n15b _n132<20> +- =_n15b +.names _n15c +0 +.names _n15d +1 +.names _n15d _n132<21> +- =_n15d +.names _n15e +0 +.names _n15f +1 +.names _n15f _n132<22> +- =_n15f +.names _n160 +0 +.names _n161 +1 +.names _n161 _n132<23> +- =_n161 +.names _n162 +0 +.names _n163 +1 +.names _n163 _n132<24> +- =_n163 +.names _n164 +0 +.names _n165 +1 +.names _n165 _n132<25> +- =_n165 +.names _n166 +0 +.names _n167 +1 +.names _n167 _n132<26> +- =_n167 +.names _n168 +0 +.names _n169 +1 +.names _n169 _n132<27> +- =_n169 +.names _n16a +0 +.names _n16b +1 +.names _n16b _n132<28> +- =_n16b +.names _n16c +0 +.names _n16d +1 +.names _n16d _n132<29> +- =_n16d +.names _n16e +0 +.names _n132<0> min$clear_n131$true<0> +- =_n132<0> +.names _n132<1> min$clear_n131$true<1> +- =_n132<1> +.names _n132<2> min$clear_n131$true<2> +- =_n132<2> +.names _n132<3> min$clear_n131$true<3> +- =_n132<3> +.names _n132<4> min$clear_n131$true<4> +- =_n132<4> +.names _n132<5> min$clear_n131$true<5> +- =_n132<5> +.names _n132<6> min$clear_n131$true<6> +- =_n132<6> +.names _n132<7> min$clear_n131$true<7> +- =_n132<7> +.names _n132<8> min$clear_n131$true<8> +- =_n132<8> +.names _n132<9> min$clear_n131$true<9> +- =_n132<9> +.names _n132<10> min$clear_n131$true<10> +- =_n132<10> +.names _n132<11> min$clear_n131$true<11> +- =_n132<11> +.names _n132<12> min$clear_n131$true<12> +- =_n132<12> +.names _n132<13> min$clear_n131$true<13> +- =_n132<13> +.names _n132<14> min$clear_n131$true<14> +- =_n132<14> +.names _n132<15> min$clear_n131$true<15> +- =_n132<15> +.names _n132<16> min$clear_n131$true<16> +- =_n132<16> +.names _n132<17> min$clear_n131$true<17> +- =_n132<17> +.names _n132<18> min$clear_n131$true<18> +- =_n132<18> +.names _n132<19> min$clear_n131$true<19> +- =_n132<19> +.names _n132<20> min$clear_n131$true<20> +- =_n132<20> +.names _n132<21> min$clear_n131$true<21> +- =_n132<21> +.names _n132<22> min$clear_n131$true<22> +- =_n132<22> +.names _n132<23> min$clear_n131$true<23> +- =_n132<23> +.names _n132<24> min$clear_n131$true<24> +- =_n132<24> +.names _n132<25> min$clear_n131$true<25> +- =_n132<25> +.names _n132<26> min$clear_n131$true<26> +- =_n132<26> +.names _n132<27> min$clear_n131$true<27> +- =_n132<27> +.names _n132<28> min$clear_n131$true<28> +- =_n132<28> +.names _n132<29> min$clear_n131$true<29> +- =_n132<29> +.names enable _n16f +0 1 +1 0 +.names _n16f _n170 +- =_n16f +# max = 0 +.names max$_n16f_n171$true<0> +0 +.names max$_n16f_n171$true<1> +0 +.names max$_n16f_n171$true<2> +0 +.names max$_n16f_n171$true<3> +0 +.names max$_n16f_n171$true<4> +0 +.names max$_n16f_n171$true<5> +0 +.names max$_n16f_n171$true<6> +0 +.names max$_n16f_n171$true<7> +0 +.names max$_n16f_n171$true<8> +0 +.names max$_n16f_n171$true<9> +0 +.names max$_n16f_n171$true<10> +0 +.names max$_n16f_n171$true<11> +0 +.names max$_n16f_n171$true<12> +0 +.names max$_n16f_n171$true<13> +0 +.names max$_n16f_n171$true<14> +0 +.names max$_n16f_n171$true<15> +0 +.names max$_n16f_n171$true<16> +0 +.names max$_n16f_n171$true<17> +0 +.names max$_n16f_n171$true<18> +0 +.names max$_n16f_n171$true<19> +0 +.names max$_n16f_n171$true<20> +0 +.names max$_n16f_n171$true<21> +0 +.names max$_n16f_n171$true<22> +0 +.names max$_n16f_n171$true<23> +0 +.names max$_n16f_n171$true<24> +0 +.names max$_n16f_n171$true<25> +0 +.names max$_n16f_n171$true<26> +0 +.names max$_n16f_n171$true<27> +0 +.names max$_n16f_n171$true<28> +0 +.names max$_n16f_n171$true<29> +0 +# min = {'b1} +.names _n174 +1 +.names _n174 _n173<0> +- =_n174 +.names _n175 +0 +.names _n176 +1 +.names _n176 _n173<1> +- =_n176 +.names _n177 +0 +.names _n178 +1 +.names _n178 _n173<2> +- =_n178 +.names _n179 +0 +.names _n17a +1 +.names _n17a _n173<3> +- =_n17a +.names _n17b +0 +.names _n17c +1 +.names _n17c _n173<4> +- =_n17c +.names _n17d +0 +.names _n17e +1 +.names _n17e _n173<5> +- =_n17e +.names _n17f +0 +.names _n180 +1 +.names _n180 _n173<6> +- =_n180 +.names _n181 +0 +.names _n182 +1 +.names _n182 _n173<7> +- =_n182 +.names _n183 +0 +.names _n184 +1 +.names _n184 _n173<8> +- =_n184 +.names _n185 +0 +.names _n186 +1 +.names _n186 _n173<9> +- =_n186 +.names _n187 +0 +.names _n188 +1 +.names _n188 _n173<10> +- =_n188 +.names _n189 +0 +.names _n18a +1 +.names _n18a _n173<11> +- =_n18a +.names _n18b +0 +.names _n18c +1 +.names _n18c _n173<12> +- =_n18c +.names _n18d +0 +.names _n18e +1 +.names _n18e _n173<13> +- =_n18e +.names _n18f +0 +.names _n190 +1 +.names _n190 _n173<14> +- =_n190 +.names _n191 +0 +.names _n192 +1 +.names _n192 _n173<15> +- =_n192 +.names _n193 +0 +.names _n194 +1 +.names _n194 _n173<16> +- =_n194 +.names _n195 +0 +.names _n196 +1 +.names _n196 _n173<17> +- =_n196 +.names _n197 +0 +.names _n198 +1 +.names _n198 _n173<18> +- =_n198 +.names _n199 +0 +.names _n19a +1 +.names _n19a _n173<19> +- =_n19a +.names _n19b +0 +.names _n19c +1 +.names _n19c _n173<20> +- =_n19c +.names _n19d +0 +.names _n19e +1 +.names _n19e _n173<21> +- =_n19e +.names _n19f +0 +.names _n1a0 +1 +.names _n1a0 _n173<22> +- =_n1a0 +.names _n1a1 +0 +.names _n1a2 +1 +.names _n1a2 _n173<23> +- =_n1a2 +.names _n1a3 +0 +.names _n1a4 +1 +.names _n1a4 _n173<24> +- =_n1a4 +.names _n1a5 +0 +.names _n1a6 +1 +.names _n1a6 _n173<25> +- =_n1a6 +.names _n1a7 +0 +.names _n1a8 +1 +.names _n1a8 _n173<26> +- =_n1a8 +.names _n1a9 +0 +.names _n1aa +1 +.names _n1aa _n173<27> +- =_n1aa +.names _n1ab +0 +.names _n1ac +1 +.names _n1ac _n173<28> +- =_n1ac +.names _n1ad +0 +.names _n1ae +1 +.names _n1ae _n173<29> +- =_n1ae +.names _n1af +0 +.names _n173<0> min$_n16f_n172$true<0> +- =_n173<0> +.names _n173<1> min$_n16f_n172$true<1> +- =_n173<1> +.names _n173<2> min$_n16f_n172$true<2> +- =_n173<2> +.names _n173<3> min$_n16f_n172$true<3> +- =_n173<3> +.names _n173<4> min$_n16f_n172$true<4> +- =_n173<4> +.names _n173<5> min$_n16f_n172$true<5> +- =_n173<5> +.names _n173<6> min$_n16f_n172$true<6> +- =_n173<6> +.names _n173<7> min$_n16f_n172$true<7> +- =_n173<7> +.names _n173<8> min$_n16f_n172$true<8> +- =_n173<8> +.names _n173<9> min$_n16f_n172$true<9> +- =_n173<9> +.names _n173<10> min$_n16f_n172$true<10> +- =_n173<10> +.names _n173<11> min$_n16f_n172$true<11> +- =_n173<11> +.names _n173<12> min$_n16f_n172$true<12> +- =_n173<12> +.names _n173<13> min$_n16f_n172$true<13> +- =_n173<13> +.names _n173<14> min$_n16f_n172$true<14> +- =_n173<14> +.names _n173<15> min$_n16f_n172$true<15> +- =_n173<15> +.names _n173<16> min$_n16f_n172$true<16> +- =_n173<16> +.names _n173<17> min$_n16f_n172$true<17> +- =_n173<17> +.names _n173<18> min$_n16f_n172$true<18> +- =_n173<18> +.names _n173<19> min$_n16f_n172$true<19> +- =_n173<19> +.names _n173<20> min$_n16f_n172$true<20> +- =_n173<20> +.names _n173<21> min$_n16f_n172$true<21> +- =_n173<21> +.names _n173<22> min$_n16f_n172$true<22> +- =_n173<22> +.names _n173<23> min$_n16f_n172$true<23> +- =_n173<23> +.names _n173<24> min$_n16f_n172$true<24> +- =_n173<24> +.names _n173<25> min$_n16f_n172$true<25> +- =_n173<25> +.names _n173<26> min$_n16f_n172$true<26> +- =_n173<26> +.names _n173<27> min$_n16f_n172$true<27> +- =_n173<27> +.names _n173<28> min$_n16f_n172$true<28> +- =_n173<28> +.names _n173<29> min$_n16f_n172$true<29> +- =_n173<29> +# last = in +.names in<0> last$_n16f_n1b0$false<0> +- =in<0> +.names in<1> last$_n16f_n1b0$false<1> +- =in<1> +.names in<2> last$_n16f_n1b0$false<2> +- =in<2> +.names in<3> last$_n16f_n1b0$false<3> +- =in<3> +.names in<4> last$_n16f_n1b0$false<4> +- =in<4> +.names in<5> last$_n16f_n1b0$false<5> +- =in<5> +.names in<6> last$_n16f_n1b0$false<6> +- =in<6> +.names in<7> last$_n16f_n1b0$false<7> +- =in<7> +.names in<8> last$_n16f_n1b0$false<8> +- =in<8> +.names in<9> last$_n16f_n1b0$false<9> +- =in<9> +.names in<10> last$_n16f_n1b0$false<10> +- =in<10> +.names in<11> last$_n16f_n1b0$false<11> +- =in<11> +.names in<12> last$_n16f_n1b0$false<12> +- =in<12> +.names in<13> last$_n16f_n1b0$false<13> +- =in<13> +.names in<14> last$_n16f_n1b0$false<14> +- =in<14> +.names in<15> last$_n16f_n1b0$false<15> +- =in<15> +.names in<16> last$_n16f_n1b0$false<16> +- =in<16> +.names in<17> last$_n16f_n1b0$false<17> +- =in<17> +.names in<18> last$_n16f_n1b0$false<18> +- =in<18> +.names in<19> last$_n16f_n1b0$false<19> +- =in<19> +.names in<20> last$_n16f_n1b0$false<20> +- =in<20> +.names in<21> last$_n16f_n1b0$false<21> +- =in<21> +.names in<22> last$_n16f_n1b0$false<22> +- =in<22> +.names in<23> last$_n16f_n1b0$false<23> +- =in<23> +.names in<24> last$_n16f_n1b0$false<24> +- =in<24> +.names in<25> last$_n16f_n1b0$false<25> +- =in<25> +.names in<26> last$_n16f_n1b0$false<26> +- =in<26> +.names in<27> last$_n16f_n1b0$false<27> +- =in<27> +.names in<28> last$_n16f_n1b0$false<28> +- =in<28> +.names in<29> last$_n16f_n1b0$false<29> +- =in<29> +.names reset _n1b1 +- =reset +# max = 0 +.names max$reset_n1b2$true<0> +0 +.names max$reset_n1b2$true<1> +0 +.names max$reset_n1b2$true<2> +0 +.names max$reset_n1b2$true<3> +0 +.names max$reset_n1b2$true<4> +0 +.names max$reset_n1b2$true<5> +0 +.names max$reset_n1b2$true<6> +0 +.names max$reset_n1b2$true<7> +0 +.names max$reset_n1b2$true<8> +0 +.names max$reset_n1b2$true<9> +0 +.names max$reset_n1b2$true<10> +0 +.names max$reset_n1b2$true<11> +0 +.names max$reset_n1b2$true<12> +0 +.names max$reset_n1b2$true<13> +0 +.names max$reset_n1b2$true<14> +0 +.names max$reset_n1b2$true<15> +0 +.names max$reset_n1b2$true<16> +0 +.names max$reset_n1b2$true<17> +0 +.names max$reset_n1b2$true<18> +0 +.names max$reset_n1b2$true<19> +0 +.names max$reset_n1b2$true<20> +0 +.names max$reset_n1b2$true<21> +0 +.names max$reset_n1b2$true<22> +0 +.names max$reset_n1b2$true<23> +0 +.names max$reset_n1b2$true<24> +0 +.names max$reset_n1b2$true<25> +0 +.names max$reset_n1b2$true<26> +0 +.names max$reset_n1b2$true<27> +0 +.names max$reset_n1b2$true<28> +0 +.names max$reset_n1b2$true<29> +0 +# min = {'b1} +.names _n1b5 +1 +.names _n1b5 _n1b4<0> +- =_n1b5 +.names _n1b6 +0 +.names _n1b7 +1 +.names _n1b7 _n1b4<1> +- =_n1b7 +.names _n1b8 +0 +.names _n1b9 +1 +.names _n1b9 _n1b4<2> +- =_n1b9 +.names _n1ba +0 +.names _n1bb +1 +.names _n1bb _n1b4<3> +- =_n1bb +.names _n1bc +0 +.names _n1bd +1 +.names _n1bd _n1b4<4> +- =_n1bd +.names _n1be +0 +.names _n1bf +1 +.names _n1bf _n1b4<5> +- =_n1bf +.names _n1c0 +0 +.names _n1c1 +1 +.names _n1c1 _n1b4<6> +- =_n1c1 +.names _n1c2 +0 +.names _n1c3 +1 +.names _n1c3 _n1b4<7> +- =_n1c3 +.names _n1c4 +0 +.names _n1c5 +1 +.names _n1c5 _n1b4<8> +- =_n1c5 +.names _n1c6 +0 +.names _n1c7 +1 +.names _n1c7 _n1b4<9> +- =_n1c7 +.names _n1c8 +0 +.names _n1c9 +1 +.names _n1c9 _n1b4<10> +- =_n1c9 +.names _n1ca +0 +.names _n1cb +1 +.names _n1cb _n1b4<11> +- =_n1cb +.names _n1cc +0 +.names _n1cd +1 +.names _n1cd _n1b4<12> +- =_n1cd +.names _n1ce +0 +.names _n1cf +1 +.names _n1cf _n1b4<13> +- =_n1cf +.names _n1d0 +0 +.names _n1d1 +1 +.names _n1d1 _n1b4<14> +- =_n1d1 +.names _n1d2 +0 +.names _n1d3 +1 +.names _n1d3 _n1b4<15> +- =_n1d3 +.names _n1d4 +0 +.names _n1d5 +1 +.names _n1d5 _n1b4<16> +- =_n1d5 +.names _n1d6 +0 +.names _n1d7 +1 +.names _n1d7 _n1b4<17> +- =_n1d7 +.names _n1d8 +0 +.names _n1d9 +1 +.names _n1d9 _n1b4<18> +- =_n1d9 +.names _n1da +0 +.names _n1db +1 +.names _n1db _n1b4<19> +- =_n1db +.names _n1dc +0 +.names _n1dd +1 +.names _n1dd _n1b4<20> +- =_n1dd +.names _n1de +0 +.names _n1df +1 +.names _n1df _n1b4<21> +- =_n1df +.names _n1e0 +0 +.names _n1e1 +1 +.names _n1e1 _n1b4<22> +- =_n1e1 +.names _n1e2 +0 +.names _n1e3 +1 +.names _n1e3 _n1b4<23> +- =_n1e3 +.names _n1e4 +0 +.names _n1e5 +1 +.names _n1e5 _n1b4<24> +- =_n1e5 +.names _n1e6 +0 +.names _n1e7 +1 +.names _n1e7 _n1b4<25> +- =_n1e7 +.names _n1e8 +0 +.names _n1e9 +1 +.names _n1e9 _n1b4<26> +- =_n1e9 +.names _n1ea +0 +.names _n1eb +1 +.names _n1eb _n1b4<27> +- =_n1eb +.names _n1ec +0 +.names _n1ed +1 +.names _n1ed _n1b4<28> +- =_n1ed +.names _n1ee +0 +.names _n1ef +1 +.names _n1ef _n1b4<29> +- =_n1ef +.names _n1f0 +0 +.names _n1b4<0> min$reset_n1b3$true<0> +- =_n1b4<0> +.names _n1b4<1> min$reset_n1b3$true<1> +- =_n1b4<1> +.names _n1b4<2> min$reset_n1b3$true<2> +- =_n1b4<2> +.names _n1b4<3> min$reset_n1b3$true<3> +- =_n1b4<3> +.names _n1b4<4> min$reset_n1b3$true<4> +- =_n1b4<4> +.names _n1b4<5> min$reset_n1b3$true<5> +- =_n1b4<5> +.names _n1b4<6> min$reset_n1b3$true<6> +- =_n1b4<6> +.names _n1b4<7> min$reset_n1b3$true<7> +- =_n1b4<7> +.names _n1b4<8> min$reset_n1b3$true<8> +- =_n1b4<8> +.names _n1b4<9> min$reset_n1b3$true<9> +- =_n1b4<9> +.names _n1b4<10> min$reset_n1b3$true<10> +- =_n1b4<10> +.names _n1b4<11> min$reset_n1b3$true<11> +- =_n1b4<11> +.names _n1b4<12> min$reset_n1b3$true<12> +- =_n1b4<12> +.names _n1b4<13> min$reset_n1b3$true<13> +- =_n1b4<13> +.names _n1b4<14> min$reset_n1b3$true<14> +- =_n1b4<14> +.names _n1b4<15> min$reset_n1b3$true<15> +- =_n1b4<15> +.names _n1b4<16> min$reset_n1b3$true<16> +- =_n1b4<16> +.names _n1b4<17> min$reset_n1b3$true<17> +- =_n1b4<17> +.names _n1b4<18> min$reset_n1b3$true<18> +- =_n1b4<18> +.names _n1b4<19> min$reset_n1b3$true<19> +- =_n1b4<19> +.names _n1b4<20> min$reset_n1b3$true<20> +- =_n1b4<20> +.names _n1b4<21> min$reset_n1b3$true<21> +- =_n1b4<21> +.names _n1b4<22> min$reset_n1b3$true<22> +- =_n1b4<22> +.names _n1b4<23> min$reset_n1b3$true<23> +- =_n1b4<23> +.names _n1b4<24> min$reset_n1b3$true<24> +- =_n1b4<24> +.names _n1b4<25> min$reset_n1b3$true<25> +- =_n1b4<25> +.names _n1b4<26> min$reset_n1b3$true<26> +- =_n1b4<26> +.names _n1b4<27> min$reset_n1b3$true<27> +- =_n1b4<27> +.names _n1b4<28> min$reset_n1b3$true<28> +- =_n1b4<28> +.names _n1b4<29> min$reset_n1b3$true<29> +- =_n1b4<29> +# max = sup +.names sup<0> max$reset_n1f1$false<0> +- =sup<0> +.names sup<1> max$reset_n1f1$false<1> +- =sup<1> +.names sup<2> max$reset_n1f1$false<2> +- =sup<2> +.names sup<3> max$reset_n1f1$false<3> +- =sup<3> +.names sup<4> max$reset_n1f1$false<4> +- =sup<4> +.names sup<5> max$reset_n1f1$false<5> +- =sup<5> +.names sup<6> max$reset_n1f1$false<6> +- =sup<6> +.names sup<7> max$reset_n1f1$false<7> +- =sup<7> +.names sup<8> max$reset_n1f1$false<8> +- =sup<8> +.names sup<9> max$reset_n1f1$false<9> +- =sup<9> +.names sup<10> max$reset_n1f1$false<10> +- =sup<10> +.names sup<11> max$reset_n1f1$false<11> +- =sup<11> +.names sup<12> max$reset_n1f1$false<12> +- =sup<12> +.names sup<13> max$reset_n1f1$false<13> +- =sup<13> +.names sup<14> max$reset_n1f1$false<14> +- =sup<14> +.names sup<15> max$reset_n1f1$false<15> +- =sup<15> +.names sup<16> max$reset_n1f1$false<16> +- =sup<16> +.names sup<17> max$reset_n1f1$false<17> +- =sup<17> +.names sup<18> max$reset_n1f1$false<18> +- =sup<18> +.names sup<19> max$reset_n1f1$false<19> +- =sup<19> +.names sup<20> max$reset_n1f1$false<20> +- =sup<20> +.names sup<21> max$reset_n1f1$false<21> +- =sup<21> +.names sup<22> max$reset_n1f1$false<22> +- =sup<22> +.names sup<23> max$reset_n1f1$false<23> +- =sup<23> +.names sup<24> max$reset_n1f1$false<24> +- =sup<24> +.names sup<25> max$reset_n1f1$false<25> +- =sup<25> +.names sup<26> max$reset_n1f1$false<26> +- =sup<26> +.names sup<27> max$reset_n1f1$false<27> +- =sup<27> +.names sup<28> max$reset_n1f1$false<28> +- =sup<28> +.names sup<29> max$reset_n1f1$false<29> +- =sup<29> +# min = inf +.names inf<0> min$reset_n1f2$false<0> +- =inf<0> +.names inf<1> min$reset_n1f2$false<1> +- =inf<1> +.names inf<2> min$reset_n1f2$false<2> +- =inf<2> +.names inf<3> min$reset_n1f2$false<3> +- =inf<3> +.names inf<4> min$reset_n1f2$false<4> +- =inf<4> +.names inf<5> min$reset_n1f2$false<5> +- =inf<5> +.names inf<6> min$reset_n1f2$false<6> +- =inf<6> +.names inf<7> min$reset_n1f2$false<7> +- =inf<7> +.names inf<8> min$reset_n1f2$false<8> +- =inf<8> +.names inf<9> min$reset_n1f2$false<9> +- =inf<9> +.names inf<10> min$reset_n1f2$false<10> +- =inf<10> +.names inf<11> min$reset_n1f2$false<11> +- =inf<11> +.names inf<12> min$reset_n1f2$false<12> +- =inf<12> +.names inf<13> min$reset_n1f2$false<13> +- =inf<13> +.names inf<14> min$reset_n1f2$false<14> +- =inf<14> +.names inf<15> min$reset_n1f2$false<15> +- =inf<15> +.names inf<16> min$reset_n1f2$false<16> +- =inf<16> +.names inf<17> min$reset_n1f2$false<17> +- =inf<17> +.names inf<18> min$reset_n1f2$false<18> +- =inf<18> +.names inf<19> min$reset_n1f2$false<19> +- =inf<19> +.names inf<20> min$reset_n1f2$false<20> +- =inf<20> +.names inf<21> min$reset_n1f2$false<21> +- =inf<21> +.names inf<22> min$reset_n1f2$false<22> +- =inf<22> +.names inf<23> min$reset_n1f2$false<23> +- =inf<23> +.names inf<24> min$reset_n1f2$false<24> +- =inf<24> +.names inf<25> min$reset_n1f2$false<25> +- =inf<25> +.names inf<26> min$reset_n1f2$false<26> +- =inf<26> +.names inf<27> min$reset_n1f2$false<27> +- =inf<27> +.names inf<28> min$reset_n1f2$false<28> +- =inf<28> +.names inf<29> min$reset_n1f2$false<29> +- =inf<29> +# if/else (reset ) +.names max$reset_n1b2$true<0> max$reset_n1f1$false<0> reset max$reset$raw_n1f6<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<1> max$reset_n1f1$false<1> reset max$reset$raw_n1f6<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<2> max$reset_n1f1$false<2> reset max$reset$raw_n1f6<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<3> max$reset_n1f1$false<3> reset max$reset$raw_n1f6<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<4> max$reset_n1f1$false<4> reset max$reset$raw_n1f6<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<5> max$reset_n1f1$false<5> reset max$reset$raw_n1f6<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<6> max$reset_n1f1$false<6> reset max$reset$raw_n1f6<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<7> max$reset_n1f1$false<7> reset max$reset$raw_n1f6<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<8> max$reset_n1f1$false<8> reset max$reset$raw_n1f6<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<9> max$reset_n1f1$false<9> reset max$reset$raw_n1f6<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<10> max$reset_n1f1$false<10> reset max$reset$raw_n1f6<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<11> max$reset_n1f1$false<11> reset max$reset$raw_n1f6<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<12> max$reset_n1f1$false<12> reset max$reset$raw_n1f6<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<13> max$reset_n1f1$false<13> reset max$reset$raw_n1f6<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<14> max$reset_n1f1$false<14> reset max$reset$raw_n1f6<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<15> max$reset_n1f1$false<15> reset max$reset$raw_n1f6<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<16> max$reset_n1f1$false<16> reset max$reset$raw_n1f6<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<17> max$reset_n1f1$false<17> reset max$reset$raw_n1f6<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<18> max$reset_n1f1$false<18> reset max$reset$raw_n1f6<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<19> max$reset_n1f1$false<19> reset max$reset$raw_n1f6<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<20> max$reset_n1f1$false<20> reset max$reset$raw_n1f6<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<21> max$reset_n1f1$false<21> reset max$reset$raw_n1f6<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<22> max$reset_n1f1$false<22> reset max$reset$raw_n1f6<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<23> max$reset_n1f1$false<23> reset max$reset$raw_n1f6<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<24> max$reset_n1f1$false<24> reset max$reset$raw_n1f6<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<25> max$reset_n1f1$false<25> reset max$reset$raw_n1f6<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<26> max$reset_n1f1$false<26> reset max$reset$raw_n1f6<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<27> max$reset_n1f1$false<27> reset max$reset$raw_n1f6<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<28> max$reset_n1f1$false<28> reset max$reset$raw_n1f6<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$reset_n1b2$true<29> max$reset_n1f1$false<29> reset max$reset$raw_n1f6<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<0> min$reset_n1f2$false<0> reset min$reset$raw_n215<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<1> min$reset_n1f2$false<1> reset min$reset$raw_n215<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<2> min$reset_n1f2$false<2> reset min$reset$raw_n215<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<3> min$reset_n1f2$false<3> reset min$reset$raw_n215<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<4> min$reset_n1f2$false<4> reset min$reset$raw_n215<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<5> min$reset_n1f2$false<5> reset min$reset$raw_n215<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<6> min$reset_n1f2$false<6> reset min$reset$raw_n215<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<7> min$reset_n1f2$false<7> reset min$reset$raw_n215<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<8> min$reset_n1f2$false<8> reset min$reset$raw_n215<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<9> min$reset_n1f2$false<9> reset min$reset$raw_n215<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<10> min$reset_n1f2$false<10> reset min$reset$raw_n215<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<11> min$reset_n1f2$false<11> reset min$reset$raw_n215<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<12> min$reset_n1f2$false<12> reset min$reset$raw_n215<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<13> min$reset_n1f2$false<13> reset min$reset$raw_n215<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<14> min$reset_n1f2$false<14> reset min$reset$raw_n215<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<15> min$reset_n1f2$false<15> reset min$reset$raw_n215<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<16> min$reset_n1f2$false<16> reset min$reset$raw_n215<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<17> min$reset_n1f2$false<17> reset min$reset$raw_n215<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<18> min$reset_n1f2$false<18> reset min$reset$raw_n215<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<19> min$reset_n1f2$false<19> reset min$reset$raw_n215<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<20> min$reset_n1f2$false<20> reset min$reset$raw_n215<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<21> min$reset_n1f2$false<21> reset min$reset$raw_n215<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<22> min$reset_n1f2$false<22> reset min$reset$raw_n215<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<23> min$reset_n1f2$false<23> reset min$reset$raw_n215<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<24> min$reset_n1f2$false<24> reset min$reset$raw_n215<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<25> min$reset_n1f2$false<25> reset min$reset$raw_n215<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<26> min$reset_n1f2$false<26> reset min$reset$raw_n215<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<27> min$reset_n1f2$false<27> reset min$reset$raw_n215<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<28> min$reset_n1f2$false<28> reset min$reset$raw_n215<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$reset_n1b3$true<29> min$reset_n1f2$false<29> reset min$reset$raw_n215<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (!enable ) +.names max$_n16f_n171$true<0> max$reset$raw_n1f6<0> _n16f max$_n16f$raw_n23d<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<1> max$reset$raw_n1f6<1> _n16f max$_n16f$raw_n23d<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<2> max$reset$raw_n1f6<2> _n16f max$_n16f$raw_n23d<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<3> max$reset$raw_n1f6<3> _n16f max$_n16f$raw_n23d<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<4> max$reset$raw_n1f6<4> _n16f max$_n16f$raw_n23d<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<5> max$reset$raw_n1f6<5> _n16f max$_n16f$raw_n23d<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<6> max$reset$raw_n1f6<6> _n16f max$_n16f$raw_n23d<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<7> max$reset$raw_n1f6<7> _n16f max$_n16f$raw_n23d<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<8> max$reset$raw_n1f6<8> _n16f max$_n16f$raw_n23d<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<9> max$reset$raw_n1f6<9> _n16f max$_n16f$raw_n23d<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<10> max$reset$raw_n1f6<10> _n16f max$_n16f$raw_n23d<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<11> max$reset$raw_n1f6<11> _n16f max$_n16f$raw_n23d<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<12> max$reset$raw_n1f6<12> _n16f max$_n16f$raw_n23d<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<13> max$reset$raw_n1f6<13> _n16f max$_n16f$raw_n23d<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<14> max$reset$raw_n1f6<14> _n16f max$_n16f$raw_n23d<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<15> max$reset$raw_n1f6<15> _n16f max$_n16f$raw_n23d<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<16> max$reset$raw_n1f6<16> _n16f max$_n16f$raw_n23d<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<17> max$reset$raw_n1f6<17> _n16f max$_n16f$raw_n23d<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<18> max$reset$raw_n1f6<18> _n16f max$_n16f$raw_n23d<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<19> max$reset$raw_n1f6<19> _n16f max$_n16f$raw_n23d<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<20> max$reset$raw_n1f6<20> _n16f max$_n16f$raw_n23d<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<21> max$reset$raw_n1f6<21> _n16f max$_n16f$raw_n23d<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<22> max$reset$raw_n1f6<22> _n16f max$_n16f$raw_n23d<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<23> max$reset$raw_n1f6<23> _n16f max$_n16f$raw_n23d<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<24> max$reset$raw_n1f6<24> _n16f max$_n16f$raw_n23d<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<25> max$reset$raw_n1f6<25> _n16f max$_n16f$raw_n23d<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<26> max$reset$raw_n1f6<26> _n16f max$_n16f$raw_n23d<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<27> max$reset$raw_n1f6<27> _n16f max$_n16f$raw_n23d<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<28> max$reset$raw_n1f6<28> _n16f max$_n16f$raw_n23d<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$_n16f_n171$true<29> max$reset$raw_n1f6<29> _n16f max$_n16f$raw_n23d<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<0> min$reset$raw_n215<0> _n16f min$_n16f$raw_n25c<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<1> min$reset$raw_n215<1> _n16f min$_n16f$raw_n25c<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<2> min$reset$raw_n215<2> _n16f min$_n16f$raw_n25c<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<3> min$reset$raw_n215<3> _n16f min$_n16f$raw_n25c<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<4> min$reset$raw_n215<4> _n16f min$_n16f$raw_n25c<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<5> min$reset$raw_n215<5> _n16f min$_n16f$raw_n25c<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<6> min$reset$raw_n215<6> _n16f min$_n16f$raw_n25c<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<7> min$reset$raw_n215<7> _n16f min$_n16f$raw_n25c<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<8> min$reset$raw_n215<8> _n16f min$_n16f$raw_n25c<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<9> min$reset$raw_n215<9> _n16f min$_n16f$raw_n25c<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<10> min$reset$raw_n215<10> _n16f min$_n16f$raw_n25c<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<11> min$reset$raw_n215<11> _n16f min$_n16f$raw_n25c<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<12> min$reset$raw_n215<12> _n16f min$_n16f$raw_n25c<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<13> min$reset$raw_n215<13> _n16f min$_n16f$raw_n25c<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<14> min$reset$raw_n215<14> _n16f min$_n16f$raw_n25c<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<15> min$reset$raw_n215<15> _n16f min$_n16f$raw_n25c<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<16> min$reset$raw_n215<16> _n16f min$_n16f$raw_n25c<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<17> min$reset$raw_n215<17> _n16f min$_n16f$raw_n25c<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<18> min$reset$raw_n215<18> _n16f min$_n16f$raw_n25c<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<19> min$reset$raw_n215<19> _n16f min$_n16f$raw_n25c<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<20> min$reset$raw_n215<20> _n16f min$_n16f$raw_n25c<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<21> min$reset$raw_n215<21> _n16f min$_n16f$raw_n25c<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<22> min$reset$raw_n215<22> _n16f min$_n16f$raw_n25c<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<23> min$reset$raw_n215<23> _n16f min$_n16f$raw_n25c<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<24> min$reset$raw_n215<24> _n16f min$_n16f$raw_n25c<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<25> min$reset$raw_n215<25> _n16f min$_n16f$raw_n25c<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<26> min$reset$raw_n215<26> _n16f min$_n16f$raw_n25c<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<27> min$reset$raw_n215<27> _n16f min$_n16f$raw_n25c<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<28> min$reset$raw_n215<28> _n16f min$_n16f$raw_n25c<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$_n16f_n172$true<29> min$reset$raw_n215<29> _n16f min$_n16f$raw_n25c<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<0> last$_n16f_n1b0$false<0> _n16f last$_n16f$raw_n27f<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<1> last$_n16f_n1b0$false<1> _n16f last$_n16f$raw_n27f<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<2> last$_n16f_n1b0$false<2> _n16f last$_n16f$raw_n27f<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<3> last$_n16f_n1b0$false<3> _n16f last$_n16f$raw_n27f<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<4> last$_n16f_n1b0$false<4> _n16f last$_n16f$raw_n27f<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<5> last$_n16f_n1b0$false<5> _n16f last$_n16f$raw_n27f<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<6> last$_n16f_n1b0$false<6> _n16f last$_n16f$raw_n27f<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<7> last$_n16f_n1b0$false<7> _n16f last$_n16f$raw_n27f<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<8> last$_n16f_n1b0$false<8> _n16f last$_n16f$raw_n27f<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<9> last$_n16f_n1b0$false<9> _n16f last$_n16f$raw_n27f<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<10> last$_n16f_n1b0$false<10> _n16f last$_n16f$raw_n27f<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<11> last$_n16f_n1b0$false<11> _n16f last$_n16f$raw_n27f<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<12> last$_n16f_n1b0$false<12> _n16f last$_n16f$raw_n27f<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<13> last$_n16f_n1b0$false<13> _n16f last$_n16f$raw_n27f<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<14> last$_n16f_n1b0$false<14> _n16f last$_n16f$raw_n27f<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<15> last$_n16f_n1b0$false<15> _n16f last$_n16f$raw_n27f<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<16> last$_n16f_n1b0$false<16> _n16f last$_n16f$raw_n27f<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<17> last$_n16f_n1b0$false<17> _n16f last$_n16f$raw_n27f<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<18> last$_n16f_n1b0$false<18> _n16f last$_n16f$raw_n27f<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<19> last$_n16f_n1b0$false<19> _n16f last$_n16f$raw_n27f<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<20> last$_n16f_n1b0$false<20> _n16f last$_n16f$raw_n27f<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<21> last$_n16f_n1b0$false<21> _n16f last$_n16f$raw_n27f<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<22> last$_n16f_n1b0$false<22> _n16f last$_n16f$raw_n27f<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<23> last$_n16f_n1b0$false<23> _n16f last$_n16f$raw_n27f<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<24> last$_n16f_n1b0$false<24> _n16f last$_n16f$raw_n27f<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<25> last$_n16f_n1b0$false<25> _n16f last$_n16f$raw_n27f<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<26> last$_n16f_n1b0$false<26> _n16f last$_n16f$raw_n27f<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<27> last$_n16f_n1b0$false<27> _n16f last$_n16f$raw_n27f<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<28> last$_n16f_n1b0$false<28> _n16f last$_n16f$raw_n27f<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<29> last$_n16f_n1b0$false<29> _n16f last$_n16f$raw_n27f<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# if/else (clear ) +.names max$clear_n130$true<0> max$_n16f$raw_n23d<0> clear max$clear$raw_n2a1<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<1> max$_n16f$raw_n23d<1> clear max$clear$raw_n2a1<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<2> max$_n16f$raw_n23d<2> clear max$clear$raw_n2a1<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<3> max$_n16f$raw_n23d<3> clear max$clear$raw_n2a1<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<4> max$_n16f$raw_n23d<4> clear max$clear$raw_n2a1<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<5> max$_n16f$raw_n23d<5> clear max$clear$raw_n2a1<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<6> max$_n16f$raw_n23d<6> clear max$clear$raw_n2a1<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<7> max$_n16f$raw_n23d<7> clear max$clear$raw_n2a1<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<8> max$_n16f$raw_n23d<8> clear max$clear$raw_n2a1<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<9> max$_n16f$raw_n23d<9> clear max$clear$raw_n2a1<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<10> max$_n16f$raw_n23d<10> clear max$clear$raw_n2a1<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<11> max$_n16f$raw_n23d<11> clear max$clear$raw_n2a1<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<12> max$_n16f$raw_n23d<12> clear max$clear$raw_n2a1<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<13> max$_n16f$raw_n23d<13> clear max$clear$raw_n2a1<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<14> max$_n16f$raw_n23d<14> clear max$clear$raw_n2a1<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<15> max$_n16f$raw_n23d<15> clear max$clear$raw_n2a1<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<16> max$_n16f$raw_n23d<16> clear max$clear$raw_n2a1<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<17> max$_n16f$raw_n23d<17> clear max$clear$raw_n2a1<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<18> max$_n16f$raw_n23d<18> clear max$clear$raw_n2a1<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<19> max$_n16f$raw_n23d<19> clear max$clear$raw_n2a1<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<20> max$_n16f$raw_n23d<20> clear max$clear$raw_n2a1<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<21> max$_n16f$raw_n23d<21> clear max$clear$raw_n2a1<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<22> max$_n16f$raw_n23d<22> clear max$clear$raw_n2a1<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<23> max$_n16f$raw_n23d<23> clear max$clear$raw_n2a1<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<24> max$_n16f$raw_n23d<24> clear max$clear$raw_n2a1<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<25> max$_n16f$raw_n23d<25> clear max$clear$raw_n2a1<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<26> max$_n16f$raw_n23d<26> clear max$clear$raw_n2a1<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<27> max$_n16f$raw_n23d<27> clear max$clear$raw_n2a1<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<28> max$_n16f$raw_n23d<28> clear max$clear$raw_n2a1<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names max$clear_n130$true<29> max$_n16f$raw_n23d<29> clear max$clear$raw_n2a1<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<0> min$_n16f$raw_n25c<0> clear min$clear$raw_n2c0<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<1> min$_n16f$raw_n25c<1> clear min$clear$raw_n2c0<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<2> min$_n16f$raw_n25c<2> clear min$clear$raw_n2c0<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<3> min$_n16f$raw_n25c<3> clear min$clear$raw_n2c0<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<4> min$_n16f$raw_n25c<4> clear min$clear$raw_n2c0<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<5> min$_n16f$raw_n25c<5> clear min$clear$raw_n2c0<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<6> min$_n16f$raw_n25c<6> clear min$clear$raw_n2c0<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<7> min$_n16f$raw_n25c<7> clear min$clear$raw_n2c0<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<8> min$_n16f$raw_n25c<8> clear min$clear$raw_n2c0<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<9> min$_n16f$raw_n25c<9> clear min$clear$raw_n2c0<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<10> min$_n16f$raw_n25c<10> clear min$clear$raw_n2c0<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<11> min$_n16f$raw_n25c<11> clear min$clear$raw_n2c0<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<12> min$_n16f$raw_n25c<12> clear min$clear$raw_n2c0<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<13> min$_n16f$raw_n25c<13> clear min$clear$raw_n2c0<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<14> min$_n16f$raw_n25c<14> clear min$clear$raw_n2c0<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<15> min$_n16f$raw_n25c<15> clear min$clear$raw_n2c0<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<16> min$_n16f$raw_n25c<16> clear min$clear$raw_n2c0<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<17> min$_n16f$raw_n25c<17> clear min$clear$raw_n2c0<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<18> min$_n16f$raw_n25c<18> clear min$clear$raw_n2c0<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<19> min$_n16f$raw_n25c<19> clear min$clear$raw_n2c0<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<20> min$_n16f$raw_n25c<20> clear min$clear$raw_n2c0<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<21> min$_n16f$raw_n25c<21> clear min$clear$raw_n2c0<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<22> min$_n16f$raw_n25c<22> clear min$clear$raw_n2c0<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<23> min$_n16f$raw_n25c<23> clear min$clear$raw_n2c0<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<24> min$_n16f$raw_n25c<24> clear min$clear$raw_n2c0<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<25> min$_n16f$raw_n25c<25> clear min$clear$raw_n2c0<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<26> min$_n16f$raw_n25c<26> clear min$clear$raw_n2c0<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<27> min$_n16f$raw_n25c<27> clear min$clear$raw_n2c0<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<28> min$_n16f$raw_n25c<28> clear min$clear$raw_n2c0<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names min$clear_n131$true<29> min$_n16f$raw_n25c<29> clear min$clear$raw_n2c0<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<0> last$_n16f$raw_n27f<0> clear last$clear$raw_n2df<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<1> last$_n16f$raw_n27f<1> clear last$clear$raw_n2df<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<2> last$_n16f$raw_n27f<2> clear last$clear$raw_n2df<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<3> last$_n16f$raw_n27f<3> clear last$clear$raw_n2df<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<4> last$_n16f$raw_n27f<4> clear last$clear$raw_n2df<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<5> last$_n16f$raw_n27f<5> clear last$clear$raw_n2df<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<6> last$_n16f$raw_n27f<6> clear last$clear$raw_n2df<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<7> last$_n16f$raw_n27f<7> clear last$clear$raw_n2df<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<8> last$_n16f$raw_n27f<8> clear last$clear$raw_n2df<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<9> last$_n16f$raw_n27f<9> clear last$clear$raw_n2df<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<10> last$_n16f$raw_n27f<10> clear last$clear$raw_n2df<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<11> last$_n16f$raw_n27f<11> clear last$clear$raw_n2df<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<12> last$_n16f$raw_n27f<12> clear last$clear$raw_n2df<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<13> last$_n16f$raw_n27f<13> clear last$clear$raw_n2df<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<14> last$_n16f$raw_n27f<14> clear last$clear$raw_n2df<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<15> last$_n16f$raw_n27f<15> clear last$clear$raw_n2df<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<16> last$_n16f$raw_n27f<16> clear last$clear$raw_n2df<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<17> last$_n16f$raw_n27f<17> clear last$clear$raw_n2df<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<18> last$_n16f$raw_n27f<18> clear last$clear$raw_n2df<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<19> last$_n16f$raw_n27f<19> clear last$clear$raw_n2df<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<20> last$_n16f$raw_n27f<20> clear last$clear$raw_n2df<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<21> last$_n16f$raw_n27f<21> clear last$clear$raw_n2df<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<22> last$_n16f$raw_n27f<22> clear last$clear$raw_n2df<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<23> last$_n16f$raw_n27f<23> clear last$clear$raw_n2df<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<24> last$_n16f$raw_n27f<24> clear last$clear$raw_n2df<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<25> last$_n16f$raw_n27f<25> clear last$clear$raw_n2df<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<26> last$_n16f$raw_n27f<26> clear last$clear$raw_n2df<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<27> last$_n16f$raw_n27f<27> clear last$clear$raw_n2df<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<28> last$_n16f$raw_n27f<28> clear last$clear$raw_n2df<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last$clear_n12f$true<29> last$_n16f$raw_n27f<29> clear last$clear$raw_n2df<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# assign out = clear ? 0 : !enable ? last : reset ? in : avg +.names enable _n305 +0 1 +1 0 +# reset ? in : avg +.names in<0> avg<0> reset _n306<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<1> avg<1> reset _n306<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<2> avg<2> reset _n306<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<3> avg<3> reset _n306<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<4> avg<4> reset _n306<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<5> avg<5> reset _n306<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<6> avg<6> reset _n306<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<7> avg<7> reset _n306<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<8> avg<8> reset _n306<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<9> avg<9> reset _n306<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<10> avg<10> reset _n306<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<11> avg<11> reset _n306<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<12> avg<12> reset _n306<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<13> avg<13> reset _n306<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<14> avg<14> reset _n306<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<15> avg<15> reset _n306<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<16> avg<16> reset _n306<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<17> avg<17> reset _n306<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<18> avg<18> reset _n306<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<19> avg<19> reset _n306<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<20> avg<20> reset _n306<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<21> avg<21> reset _n306<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<22> avg<22> reset _n306<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<23> avg<23> reset _n306<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<24> avg<24> reset _n306<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<25> avg<25> reset _n306<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<26> avg<26> reset _n306<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<27> avg<27> reset _n306<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<28> avg<28> reset _n306<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names in<29> avg<29> reset _n306<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# !enable ? last : reset ? in : avg +.names last<0> _n306<0> _n305 _n325<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<1> _n306<1> _n305 _n325<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<2> _n306<2> _n305 _n325<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<3> _n306<3> _n305 _n325<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<4> _n306<4> _n305 _n325<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<5> _n306<5> _n305 _n325<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<6> _n306<6> _n305 _n325<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<7> _n306<7> _n305 _n325<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<8> _n306<8> _n305 _n325<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<9> _n306<9> _n305 _n325<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<10> _n306<10> _n305 _n325<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<11> _n306<11> _n305 _n325<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<12> _n306<12> _n305 _n325<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<13> _n306<13> _n305 _n325<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<14> _n306<14> _n305 _n325<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<15> _n306<15> _n305 _n325<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<16> _n306<16> _n305 _n325<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<17> _n306<17> _n305 _n325<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<18> _n306<18> _n305 _n325<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<19> _n306<19> _n305 _n325<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<20> _n306<20> _n305 _n325<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<21> _n306<21> _n305 _n325<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<22> _n306<22> _n305 _n325<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<23> _n306<23> _n305 _n325<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<24> _n306<24> _n305 _n325<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<25> _n306<25> _n305 _n325<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<26> _n306<26> _n305 _n325<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<27> _n306<27> _n305 _n325<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<28> _n306<28> _n305 _n325<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names last<29> _n306<29> _n305 _n325<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<0> +0 +.names _n344<1> +0 +.names _n344<2> +0 +.names _n344<3> +0 +.names _n344<4> +0 +.names _n344<5> +0 +.names _n344<6> +0 +.names _n344<7> +0 +.names _n344<8> +0 +.names _n344<9> +0 +.names _n344<10> +0 +.names _n344<11> +0 +.names _n344<12> +0 +.names _n344<13> +0 +.names _n344<14> +0 +.names _n344<15> +0 +.names _n344<16> +0 +.names _n344<17> +0 +.names _n344<18> +0 +.names _n344<19> +0 +.names _n344<20> +0 +.names _n344<21> +0 +.names _n344<22> +0 +.names _n344<23> +0 +.names _n344<24> +0 +.names _n344<25> +0 +.names _n344<26> +0 +.names _n344<27> +0 +.names _n344<28> +0 +.names _n344<29> +0 +# clear ? 0 : !enable ? last : reset ? in : avg +.names _n344<0> _n325<0> clear _n345<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<1> _n325<1> clear _n345<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<2> _n325<2> clear _n345<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<3> _n325<3> clear _n345<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<4> _n325<4> clear _n345<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<5> _n325<5> clear _n345<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<6> _n325<6> clear _n345<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<7> _n325<7> clear _n345<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<8> _n325<8> clear _n345<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<9> _n325<9> clear _n345<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<10> _n325<10> clear _n345<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<11> _n325<11> clear _n345<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<12> _n325<12> clear _n345<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<13> _n325<13> clear _n345<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<14> _n325<14> clear _n345<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<15> _n325<15> clear _n345<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<16> _n325<16> clear _n345<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<17> _n325<17> clear _n345<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<18> _n325<18> clear _n345<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<19> _n325<19> clear _n345<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<20> _n325<20> clear _n345<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<21> _n325<21> clear _n345<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<22> _n325<22> clear _n345<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<23> _n325<23> clear _n345<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<24> _n325<24> clear _n345<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<25> _n325<25> clear _n345<25> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<26> _n325<26> clear _n345<26> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<27> _n325<27> clear _n345<27> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<28> _n325<28> clear _n345<28> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n344<29> _n325<29> clear _n345<29> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n345<0> out$raw_n304<0> +- =_n345<0> +.names _n345<1> out$raw_n304<1> +- =_n345<1> +.names _n345<2> out$raw_n304<2> +- =_n345<2> +.names _n345<3> out$raw_n304<3> +- =_n345<3> +.names _n345<4> out$raw_n304<4> +- =_n345<4> +.names _n345<5> out$raw_n304<5> +- =_n345<5> +.names _n345<6> out$raw_n304<6> +- =_n345<6> +.names _n345<7> out$raw_n304<7> +- =_n345<7> +.names _n345<8> out$raw_n304<8> +- =_n345<8> +.names _n345<9> out$raw_n304<9> +- =_n345<9> +.names _n345<10> out$raw_n304<10> +- =_n345<10> +.names _n345<11> out$raw_n304<11> +- =_n345<11> +.names _n345<12> out$raw_n304<12> +- =_n345<12> +.names _n345<13> out$raw_n304<13> +- =_n345<13> +.names _n345<14> out$raw_n304<14> +- =_n345<14> +.names _n345<15> out$raw_n304<15> +- =_n345<15> +.names _n345<16> out$raw_n304<16> +- =_n345<16> +.names _n345<17> out$raw_n304<17> +- =_n345<17> +.names _n345<18> out$raw_n304<18> +- =_n345<18> +.names _n345<19> out$raw_n304<19> +- =_n345<19> +.names _n345<20> out$raw_n304<20> +- =_n345<20> +.names _n345<21> out$raw_n304<21> +- =_n345<21> +.names _n345<22> out$raw_n304<22> +- =_n345<22> +.names _n345<23> out$raw_n304<23> +- =_n345<23> +.names _n345<24> out$raw_n304<24> +- =_n345<24> +.names _n345<25> out$raw_n304<25> +- =_n345<25> +.names _n345<26> out$raw_n304<26> +- =_n345<26> +.names _n345<27> out$raw_n304<27> +- =_n345<27> +.names _n345<28> out$raw_n304<28> +- =_n345<28> +.names _n345<29> out$raw_n304<29> +- =_n345<29> +# conflict arbitrators +.names inf$raw_neb<0> inf<0> +- =inf$raw_neb<0> +.names inf$raw_neb<1> inf<1> +- =inf$raw_neb<1> +.names inf$raw_neb<2> inf<2> +- =inf$raw_neb<2> +.names inf$raw_neb<3> inf<3> +- =inf$raw_neb<3> +.names inf$raw_neb<4> inf<4> +- =inf$raw_neb<4> +.names inf$raw_neb<5> inf<5> +- =inf$raw_neb<5> +.names inf$raw_neb<6> inf<6> +- =inf$raw_neb<6> +.names inf$raw_neb<7> inf<7> +- =inf$raw_neb<7> +.names inf$raw_neb<8> inf<8> +- =inf$raw_neb<8> +.names inf$raw_neb<9> inf<9> +- =inf$raw_neb<9> +.names inf$raw_neb<10> inf<10> +- =inf$raw_neb<10> +.names inf$raw_neb<11> inf<11> +- =inf$raw_neb<11> +.names inf$raw_neb<12> inf<12> +- =inf$raw_neb<12> +.names inf$raw_neb<13> inf<13> +- =inf$raw_neb<13> +.names inf$raw_neb<14> inf<14> +- =inf$raw_neb<14> +.names inf$raw_neb<15> inf<15> +- =inf$raw_neb<15> +.names inf$raw_neb<16> inf<16> +- =inf$raw_neb<16> +.names inf$raw_neb<17> inf<17> +- =inf$raw_neb<17> +.names inf$raw_neb<18> inf<18> +- =inf$raw_neb<18> +.names inf$raw_neb<19> inf<19> +- =inf$raw_neb<19> +.names inf$raw_neb<20> inf<20> +- =inf$raw_neb<20> +.names inf$raw_neb<21> inf<21> +- =inf$raw_neb<21> +.names inf$raw_neb<22> inf<22> +- =inf$raw_neb<22> +.names inf$raw_neb<23> inf<23> +- =inf$raw_neb<23> +.names inf$raw_neb<24> inf<24> +- =inf$raw_neb<24> +.names inf$raw_neb<25> inf<25> +- =inf$raw_neb<25> +.names inf$raw_neb<26> inf<26> +- =inf$raw_neb<26> +.names inf$raw_neb<27> inf<27> +- =inf$raw_neb<27> +.names inf$raw_neb<28> inf<28> +- =inf$raw_neb<28> +.names inf$raw_neb<29> inf<29> +- =inf$raw_neb<29> +.names _n12e _n170 _n1b1 _n364 +.def 0 + 1 - - 1 + 0 1 - 1 + 0 0 1 1 + 0 0 0 1 +.names _n364 max$clear$raw_n2a1<0> max$clear$raw_n2a1<1> max$clear$raw_n2a1<2> max$clear$raw_n2a1<3> max$clear$raw_n2a1<4> max$clear$raw_n2a1<5> max$clear$raw_n2a1<6> max$clear$raw_n2a1<7> max$clear$raw_n2a1<8> max$clear$raw_n2a1<9> max$clear$raw_n2a1<10> max$clear$raw_n2a1<11> max$clear$raw_n2a1<12> max$clear$raw_n2a1<13> max$clear$raw_n2a1<14> max$clear$raw_n2a1<15> max$clear$raw_n2a1<16> max$clear$raw_n2a1<17> max$clear$raw_n2a1<18> max$clear$raw_n2a1<19> max$clear$raw_n2a1<20> max$clear$raw_n2a1<21> max$clear$raw_n2a1<22> max$clear$raw_n2a1<23> max$clear$raw_n2a1<24> max$clear$raw_n2a1<25> max$clear$raw_n2a1<26> max$clear$raw_n2a1<27> max$clear$raw_n2a1<28> max$clear$raw_n2a1<29> max<0> max<1> max<2> max<3> max<4> max<5> max<6> max<7> max<8> max<9> max<10> max<11> max<12> max<13> max<14> max<15> max<16> max<17> max<18> max<19> max<20> max<21> max<22> max<23> max<24> max<25> max<26> max<27> max<28> max<29> -> _n365<0> _n365<1> _n365<2> _n365<3> _n365<4> _n365<5> _n365<6> _n365<7> _n365<8> _n365<9> _n365<10> _n365<11> _n365<12> _n365<13> _n365<14> _n365<15> _n365<16> _n365<17> _n365<18> _n365<19> _n365<20> _n365<21> _n365<22> _n365<23> _n365<24> _n365<25> _n365<26> _n365<27> _n365<28> _n365<29> +1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =max$clear$raw_n2a1<0> =max$clear$raw_n2a1<1> =max$clear$raw_n2a1<2> =max$clear$raw_n2a1<3> =max$clear$raw_n2a1<4> =max$clear$raw_n2a1<5> =max$clear$raw_n2a1<6> =max$clear$raw_n2a1<7> =max$clear$raw_n2a1<8> =max$clear$raw_n2a1<9> =max$clear$raw_n2a1<10> =max$clear$raw_n2a1<11> =max$clear$raw_n2a1<12> =max$clear$raw_n2a1<13> =max$clear$raw_n2a1<14> =max$clear$raw_n2a1<15> =max$clear$raw_n2a1<16> =max$clear$raw_n2a1<17> =max$clear$raw_n2a1<18> =max$clear$raw_n2a1<19> =max$clear$raw_n2a1<20> =max$clear$raw_n2a1<21> =max$clear$raw_n2a1<22> =max$clear$raw_n2a1<23> =max$clear$raw_n2a1<24> =max$clear$raw_n2a1<25> =max$clear$raw_n2a1<26> =max$clear$raw_n2a1<27> =max$clear$raw_n2a1<28> =max$clear$raw_n2a1<29> +0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =max<0> =max<1> =max<2> =max<3> =max<4> =max<5> =max<6> =max<7> =max<8> =max<9> =max<10> =max<11> =max<12> =max<13> =max<14> =max<15> =max<16> =max<17> =max<18> =max<19> =max<20> =max<21> =max<22> =max<23> =max<24> =max<25> =max<26> =max<27> =max<28> =max<29> +.names _n12e _n170 _n1b1 _n366 +.def 0 + 1 - - 1 + 0 1 - 1 + 0 0 1 1 + 0 0 0 1 +.names _n366 min$clear$raw_n2c0<0> min$clear$raw_n2c0<1> min$clear$raw_n2c0<2> min$clear$raw_n2c0<3> min$clear$raw_n2c0<4> min$clear$raw_n2c0<5> min$clear$raw_n2c0<6> min$clear$raw_n2c0<7> min$clear$raw_n2c0<8> min$clear$raw_n2c0<9> min$clear$raw_n2c0<10> min$clear$raw_n2c0<11> min$clear$raw_n2c0<12> min$clear$raw_n2c0<13> min$clear$raw_n2c0<14> min$clear$raw_n2c0<15> min$clear$raw_n2c0<16> min$clear$raw_n2c0<17> min$clear$raw_n2c0<18> min$clear$raw_n2c0<19> min$clear$raw_n2c0<20> min$clear$raw_n2c0<21> min$clear$raw_n2c0<22> min$clear$raw_n2c0<23> min$clear$raw_n2c0<24> min$clear$raw_n2c0<25> min$clear$raw_n2c0<26> min$clear$raw_n2c0<27> min$clear$raw_n2c0<28> min$clear$raw_n2c0<29> min<0> min<1> min<2> min<3> min<4> min<5> min<6> min<7> min<8> min<9> min<10> min<11> min<12> min<13> min<14> min<15> min<16> min<17> min<18> min<19> min<20> min<21> min<22> min<23> min<24> min<25> min<26> min<27> min<28> min<29> -> _n367<0> _n367<1> _n367<2> _n367<3> _n367<4> _n367<5> _n367<6> _n367<7> _n367<8> _n367<9> _n367<10> _n367<11> _n367<12> _n367<13> _n367<14> _n367<15> _n367<16> _n367<17> _n367<18> _n367<19> _n367<20> _n367<21> _n367<22> _n367<23> _n367<24> _n367<25> _n367<26> _n367<27> _n367<28> _n367<29> +1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =min$clear$raw_n2c0<0> =min$clear$raw_n2c0<1> =min$clear$raw_n2c0<2> =min$clear$raw_n2c0<3> =min$clear$raw_n2c0<4> =min$clear$raw_n2c0<5> =min$clear$raw_n2c0<6> =min$clear$raw_n2c0<7> =min$clear$raw_n2c0<8> =min$clear$raw_n2c0<9> =min$clear$raw_n2c0<10> =min$clear$raw_n2c0<11> =min$clear$raw_n2c0<12> =min$clear$raw_n2c0<13> =min$clear$raw_n2c0<14> =min$clear$raw_n2c0<15> =min$clear$raw_n2c0<16> =min$clear$raw_n2c0<17> =min$clear$raw_n2c0<18> =min$clear$raw_n2c0<19> =min$clear$raw_n2c0<20> =min$clear$raw_n2c0<21> =min$clear$raw_n2c0<22> =min$clear$raw_n2c0<23> =min$clear$raw_n2c0<24> =min$clear$raw_n2c0<25> =min$clear$raw_n2c0<26> =min$clear$raw_n2c0<27> =min$clear$raw_n2c0<28> =min$clear$raw_n2c0<29> +0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =min<0> =min<1> =min<2> =min<3> =min<4> =min<5> =min<6> =min<7> =min<8> =min<9> =min<10> =min<11> =min<12> =min<13> =min<14> =min<15> =min<16> =min<17> =min<18> =min<19> =min<20> =min<21> =min<22> =min<23> =min<24> =min<25> =min<26> =min<27> =min<28> =min<29> +.names aux$raw_n7e aux +0 0 +1 1 +.names out$raw_n304<0> out<0> +- =out$raw_n304<0> +.names out$raw_n304<1> out<1> +- =out$raw_n304<1> +.names out$raw_n304<2> out<2> +- =out$raw_n304<2> +.names out$raw_n304<3> out<3> +- =out$raw_n304<3> +.names out$raw_n304<4> out<4> +- =out$raw_n304<4> +.names out$raw_n304<5> out<5> +- =out$raw_n304<5> +.names out$raw_n304<6> out<6> +- =out$raw_n304<6> +.names out$raw_n304<7> out<7> +- =out$raw_n304<7> +.names out$raw_n304<8> out<8> +- =out$raw_n304<8> +.names out$raw_n304<9> out<9> +- =out$raw_n304<9> +.names out$raw_n304<10> out<10> +- =out$raw_n304<10> +.names out$raw_n304<11> out<11> +- =out$raw_n304<11> +.names out$raw_n304<12> out<12> +- =out$raw_n304<12> +.names out$raw_n304<13> out<13> +- =out$raw_n304<13> +.names out$raw_n304<14> out<14> +- =out$raw_n304<14> +.names out$raw_n304<15> out<15> +- =out$raw_n304<15> +.names out$raw_n304<16> out<16> +- =out$raw_n304<16> +.names out$raw_n304<17> out<17> +- =out$raw_n304<17> +.names out$raw_n304<18> out<18> +- =out$raw_n304<18> +.names out$raw_n304<19> out<19> +- =out$raw_n304<19> +.names out$raw_n304<20> out<20> +- =out$raw_n304<20> +.names out$raw_n304<21> out<21> +- =out$raw_n304<21> +.names out$raw_n304<22> out<22> +- =out$raw_n304<22> +.names out$raw_n304<23> out<23> +- =out$raw_n304<23> +.names out$raw_n304<24> out<24> +- =out$raw_n304<24> +.names out$raw_n304<25> out<25> +- =out$raw_n304<25> +.names out$raw_n304<26> out<26> +- =out$raw_n304<26> +.names out$raw_n304<27> out<27> +- =out$raw_n304<27> +.names out$raw_n304<28> out<28> +- =out$raw_n304<28> +.names out$raw_n304<29> out<29> +- =out$raw_n304<29> +.names avg$raw_n7d<0> avg<0> +- =avg$raw_n7d<0> +.names avg$raw_n7d<1> avg<1> +- =avg$raw_n7d<1> +.names avg$raw_n7d<2> avg<2> +- =avg$raw_n7d<2> +.names avg$raw_n7d<3> avg<3> +- =avg$raw_n7d<3> +.names avg$raw_n7d<4> avg<4> +- =avg$raw_n7d<4> +.names avg$raw_n7d<5> avg<5> +- =avg$raw_n7d<5> +.names avg$raw_n7d<6> avg<6> +- =avg$raw_n7d<6> +.names avg$raw_n7d<7> avg<7> +- =avg$raw_n7d<7> +.names avg$raw_n7d<8> avg<8> +- =avg$raw_n7d<8> +.names avg$raw_n7d<9> avg<9> +- =avg$raw_n7d<9> +.names avg$raw_n7d<10> avg<10> +- =avg$raw_n7d<10> +.names avg$raw_n7d<11> avg<11> +- =avg$raw_n7d<11> +.names avg$raw_n7d<12> avg<12> +- =avg$raw_n7d<12> +.names avg$raw_n7d<13> avg<13> +- =avg$raw_n7d<13> +.names avg$raw_n7d<14> avg<14> +- =avg$raw_n7d<14> +.names avg$raw_n7d<15> avg<15> +- =avg$raw_n7d<15> +.names avg$raw_n7d<16> avg<16> +- =avg$raw_n7d<16> +.names avg$raw_n7d<17> avg<17> +- =avg$raw_n7d<17> +.names avg$raw_n7d<18> avg<18> +- =avg$raw_n7d<18> +.names avg$raw_n7d<19> avg<19> +- =avg$raw_n7d<19> +.names avg$raw_n7d<20> avg<20> +- =avg$raw_n7d<20> +.names avg$raw_n7d<21> avg<21> +- =avg$raw_n7d<21> +.names avg$raw_n7d<22> avg<22> +- =avg$raw_n7d<22> +.names avg$raw_n7d<23> avg<23> +- =avg$raw_n7d<23> +.names avg$raw_n7d<24> avg<24> +- =avg$raw_n7d<24> +.names avg$raw_n7d<25> avg<25> +- =avg$raw_n7d<25> +.names avg$raw_n7d<26> avg<26> +- =avg$raw_n7d<26> +.names avg$raw_n7d<27> avg<27> +- =avg$raw_n7d<27> +.names avg$raw_n7d<28> avg<28> +- =avg$raw_n7d<28> +.names avg$raw_n7d<29> avg<29> +- =avg$raw_n7d<29> +.names _n12e _n170 _n368 +.def 0 + 1 - 1 + 0 0 1 +.names _n368 last$clear$raw_n2df<0> last$clear$raw_n2df<1> last$clear$raw_n2df<2> last$clear$raw_n2df<3> last$clear$raw_n2df<4> last$clear$raw_n2df<5> last$clear$raw_n2df<6> last$clear$raw_n2df<7> last$clear$raw_n2df<8> last$clear$raw_n2df<9> last$clear$raw_n2df<10> last$clear$raw_n2df<11> last$clear$raw_n2df<12> last$clear$raw_n2df<13> last$clear$raw_n2df<14> last$clear$raw_n2df<15> last$clear$raw_n2df<16> last$clear$raw_n2df<17> last$clear$raw_n2df<18> last$clear$raw_n2df<19> last$clear$raw_n2df<20> last$clear$raw_n2df<21> last$clear$raw_n2df<22> last$clear$raw_n2df<23> last$clear$raw_n2df<24> last$clear$raw_n2df<25> last$clear$raw_n2df<26> last$clear$raw_n2df<27> last$clear$raw_n2df<28> last$clear$raw_n2df<29> last<0> last<1> last<2> last<3> last<4> last<5> last<6> last<7> last<8> last<9> last<10> last<11> last<12> last<13> last<14> last<15> last<16> last<17> last<18> last<19> last<20> last<21> last<22> last<23> last<24> last<25> last<26> last<27> last<28> last<29> -> _n369<0> _n369<1> _n369<2> _n369<3> _n369<4> _n369<5> _n369<6> _n369<7> _n369<8> _n369<9> _n369<10> _n369<11> _n369<12> _n369<13> _n369<14> _n369<15> _n369<16> _n369<17> _n369<18> _n369<19> _n369<20> _n369<21> _n369<22> _n369<23> _n369<24> _n369<25> _n369<26> _n369<27> _n369<28> _n369<29> +1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =last$clear$raw_n2df<0> =last$clear$raw_n2df<1> =last$clear$raw_n2df<2> =last$clear$raw_n2df<3> =last$clear$raw_n2df<4> =last$clear$raw_n2df<5> =last$clear$raw_n2df<6> =last$clear$raw_n2df<7> =last$clear$raw_n2df<8> =last$clear$raw_n2df<9> =last$clear$raw_n2df<10> =last$clear$raw_n2df<11> =last$clear$raw_n2df<12> =last$clear$raw_n2df<13> =last$clear$raw_n2df<14> =last$clear$raw_n2df<15> =last$clear$raw_n2df<16> =last$clear$raw_n2df<17> =last$clear$raw_n2df<18> =last$clear$raw_n2df<19> =last$clear$raw_n2df<20> =last$clear$raw_n2df<21> =last$clear$raw_n2df<22> =last$clear$raw_n2df<23> =last$clear$raw_n2df<24> =last$clear$raw_n2df<25> =last$clear$raw_n2df<26> =last$clear$raw_n2df<27> =last$clear$raw_n2df<28> =last$clear$raw_n2df<29> +0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =last<0> =last<1> =last<2> =last<3> =last<4> =last<5> =last<6> =last<7> =last<8> =last<9> =last<10> =last<11> =last<12> =last<13> =last<14> =last<15> =last<16> =last<17> =last<18> =last<19> =last<20> =last<21> =last<22> =last<23> =last<24> =last<25> =last<26> =last<27> =last<28> =last<29> +.names sup$raw_na7<0> sup<0> +- =sup$raw_na7<0> +.names sup$raw_na7<1> sup<1> +- =sup$raw_na7<1> +.names sup$raw_na7<2> sup<2> +- =sup$raw_na7<2> +.names sup$raw_na7<3> sup<3> +- =sup$raw_na7<3> +.names sup$raw_na7<4> sup<4> +- =sup$raw_na7<4> +.names sup$raw_na7<5> sup<5> +- =sup$raw_na7<5> +.names sup$raw_na7<6> sup<6> +- =sup$raw_na7<6> +.names sup$raw_na7<7> sup<7> +- =sup$raw_na7<7> +.names sup$raw_na7<8> sup<8> +- =sup$raw_na7<8> +.names sup$raw_na7<9> sup<9> +- =sup$raw_na7<9> +.names sup$raw_na7<10> sup<10> +- =sup$raw_na7<10> +.names sup$raw_na7<11> sup<11> +- =sup$raw_na7<11> +.names sup$raw_na7<12> sup<12> +- =sup$raw_na7<12> +.names sup$raw_na7<13> sup<13> +- =sup$raw_na7<13> +.names sup$raw_na7<14> sup<14> +- =sup$raw_na7<14> +.names sup$raw_na7<15> sup<15> +- =sup$raw_na7<15> +.names sup$raw_na7<16> sup<16> +- =sup$raw_na7<16> +.names sup$raw_na7<17> sup<17> +- =sup$raw_na7<17> +.names sup$raw_na7<18> sup<18> +- =sup$raw_na7<18> +.names sup$raw_na7<19> sup<19> +- =sup$raw_na7<19> +.names sup$raw_na7<20> sup<20> +- =sup$raw_na7<20> +.names sup$raw_na7<21> sup<21> +- =sup$raw_na7<21> +.names sup$raw_na7<22> sup<22> +- =sup$raw_na7<22> +.names sup$raw_na7<23> sup<23> +- =sup$raw_na7<23> +.names sup$raw_na7<24> sup<24> +- =sup$raw_na7<24> +.names sup$raw_na7<25> sup<25> +- =sup$raw_na7<25> +.names sup$raw_na7<26> sup<26> +- =sup$raw_na7<26> +.names sup$raw_na7<27> sup<27> +- =sup$raw_na7<27> +.names sup$raw_na7<28> sup<28> +- =sup$raw_na7<28> +.names sup$raw_na7<29> sup<29> +- =sup$raw_na7<29> +# non-blocking assignments +# latches +.r max$raw_n3e<0> max<0> +.def 0 +1 1 +.r max$raw_n3e<1> max<1> +.def 0 +1 1 +.r max$raw_n3e<2> max<2> +.def 0 +1 1 +.r max$raw_n3e<3> max<3> +.def 0 +1 1 +.r max$raw_n3e<4> max<4> +.def 0 +1 1 +.r max$raw_n3e<5> max<5> +.def 0 +1 1 +.r max$raw_n3e<6> max<6> +.def 0 +1 1 +.r max$raw_n3e<7> max<7> +.def 0 +1 1 +.r max$raw_n3e<8> max<8> +.def 0 +1 1 +.r max$raw_n3e<9> max<9> +.def 0 +1 1 +.r max$raw_n3e<10> max<10> +.def 0 +1 1 +.r max$raw_n3e<11> max<11> +.def 0 +1 1 +.r max$raw_n3e<12> max<12> +.def 0 +1 1 +.r max$raw_n3e<13> max<13> +.def 0 +1 1 +.r max$raw_n3e<14> max<14> +.def 0 +1 1 +.r max$raw_n3e<15> max<15> +.def 0 +1 1 +.r max$raw_n3e<16> max<16> +.def 0 +1 1 +.r max$raw_n3e<17> max<17> +.def 0 +1 1 +.r max$raw_n3e<18> max<18> +.def 0 +1 1 +.r max$raw_n3e<19> max<19> +.def 0 +1 1 +.r max$raw_n3e<20> max<20> +.def 0 +1 1 +.r max$raw_n3e<21> max<21> +.def 0 +1 1 +.r max$raw_n3e<22> max<22> +.def 0 +1 1 +.r max$raw_n3e<23> max<23> +.def 0 +1 1 +.r max$raw_n3e<24> max<24> +.def 0 +1 1 +.r max$raw_n3e<25> max<25> +.def 0 +1 1 +.r max$raw_n3e<26> max<26> +.def 0 +1 1 +.r max$raw_n3e<27> max<27> +.def 0 +1 1 +.r max$raw_n3e<28> max<28> +.def 0 +1 1 +.r max$raw_n3e<29> max<29> +.def 0 +1 1 +.latch _n365<0> max<0> +.latch _n365<1> max<1> +.latch _n365<2> max<2> +.latch _n365<3> max<3> +.latch _n365<4> max<4> +.latch _n365<5> max<5> +.latch _n365<6> max<6> +.latch _n365<7> max<7> +.latch _n365<8> max<8> +.latch _n365<9> max<9> +.latch _n365<10> max<10> +.latch _n365<11> max<11> +.latch _n365<12> max<12> +.latch _n365<13> max<13> +.latch _n365<14> max<14> +.latch _n365<15> max<15> +.latch _n365<16> max<16> +.latch _n365<17> max<17> +.latch _n365<18> max<18> +.latch _n365<19> max<19> +.latch _n365<20> max<20> +.latch _n365<21> max<21> +.latch _n365<22> max<22> +.latch _n365<23> max<23> +.latch _n365<24> max<24> +.latch _n365<25> max<25> +.latch _n365<26> max<26> +.latch _n365<27> max<27> +.latch _n365<28> max<28> +.latch _n365<29> max<29> +.r min$raw_n0<0> min<0> +.def 0 +1 1 +.r min$raw_n0<1> min<1> +.def 0 +1 1 +.r min$raw_n0<2> min<2> +.def 0 +1 1 +.r min$raw_n0<3> min<3> +.def 0 +1 1 +.r min$raw_n0<4> min<4> +.def 0 +1 1 +.r min$raw_n0<5> min<5> +.def 0 +1 1 +.r min$raw_n0<6> min<6> +.def 0 +1 1 +.r min$raw_n0<7> min<7> +.def 0 +1 1 +.r min$raw_n0<8> min<8> +.def 0 +1 1 +.r min$raw_n0<9> min<9> +.def 0 +1 1 +.r min$raw_n0<10> min<10> +.def 0 +1 1 +.r min$raw_n0<11> min<11> +.def 0 +1 1 +.r min$raw_n0<12> min<12> +.def 0 +1 1 +.r min$raw_n0<13> min<13> +.def 0 +1 1 +.r min$raw_n0<14> min<14> +.def 0 +1 1 +.r min$raw_n0<15> min<15> +.def 0 +1 1 +.r min$raw_n0<16> min<16> +.def 0 +1 1 +.r min$raw_n0<17> min<17> +.def 0 +1 1 +.r min$raw_n0<18> min<18> +.def 0 +1 1 +.r min$raw_n0<19> min<19> +.def 0 +1 1 +.r min$raw_n0<20> min<20> +.def 0 +1 1 +.r min$raw_n0<21> min<21> +.def 0 +1 1 +.r min$raw_n0<22> min<22> +.def 0 +1 1 +.r min$raw_n0<23> min<23> +.def 0 +1 1 +.r min$raw_n0<24> min<24> +.def 0 +1 1 +.r min$raw_n0<25> min<25> +.def 0 +1 1 +.r min$raw_n0<26> min<26> +.def 0 +1 1 +.r min$raw_n0<27> min<27> +.def 0 +1 1 +.r min$raw_n0<28> min<28> +.def 0 +1 1 +.r min$raw_n0<29> min<29> +.def 0 +1 1 +.latch _n367<0> min<0> +.latch _n367<1> min<1> +.latch _n367<2> min<2> +.latch _n367<3> min<3> +.latch _n367<4> min<4> +.latch _n367<5> min<5> +.latch _n367<6> min<6> +.latch _n367<7> min<7> +.latch _n367<8> min<8> +.latch _n367<9> min<9> +.latch _n367<10> min<10> +.latch _n367<11> min<11> +.latch _n367<12> min<12> +.latch _n367<13> min<13> +.latch _n367<14> min<14> +.latch _n367<15> min<15> +.latch _n367<16> min<16> +.latch _n367<17> min<17> +.latch _n367<18> min<18> +.latch _n367<19> min<19> +.latch _n367<20> min<20> +.latch _n367<21> min<21> +.latch _n367<22> min<22> +.latch _n367<23> min<23> +.latch _n367<24> min<24> +.latch _n367<25> min<25> +.latch _n367<26> min<26> +.latch _n367<27> min<27> +.latch _n367<28> min<28> +.latch _n367<29> min<29> +.r last$raw_n3f<0> last<0> +.def 0 +1 1 +.r last$raw_n3f<1> last<1> +.def 0 +1 1 +.r last$raw_n3f<2> last<2> +.def 0 +1 1 +.r last$raw_n3f<3> last<3> +.def 0 +1 1 +.r last$raw_n3f<4> last<4> +.def 0 +1 1 +.r last$raw_n3f<5> last<5> +.def 0 +1 1 +.r last$raw_n3f<6> last<6> +.def 0 +1 1 +.r last$raw_n3f<7> last<7> +.def 0 +1 1 +.r last$raw_n3f<8> last<8> +.def 0 +1 1 +.r last$raw_n3f<9> last<9> +.def 0 +1 1 +.r last$raw_n3f<10> last<10> +.def 0 +1 1 +.r last$raw_n3f<11> last<11> +.def 0 +1 1 +.r last$raw_n3f<12> last<12> +.def 0 +1 1 +.r last$raw_n3f<13> last<13> +.def 0 +1 1 +.r last$raw_n3f<14> last<14> +.def 0 +1 1 +.r last$raw_n3f<15> last<15> +.def 0 +1 1 +.r last$raw_n3f<16> last<16> +.def 0 +1 1 +.r last$raw_n3f<17> last<17> +.def 0 +1 1 +.r last$raw_n3f<18> last<18> +.def 0 +1 1 +.r last$raw_n3f<19> last<19> +.def 0 +1 1 +.r last$raw_n3f<20> last<20> +.def 0 +1 1 +.r last$raw_n3f<21> last<21> +.def 0 +1 1 +.r last$raw_n3f<22> last<22> +.def 0 +1 1 +.r last$raw_n3f<23> last<23> +.def 0 +1 1 +.r last$raw_n3f<24> last<24> +.def 0 +1 1 +.r last$raw_n3f<25> last<25> +.def 0 +1 1 +.r last$raw_n3f<26> last<26> +.def 0 +1 1 +.r last$raw_n3f<27> last<27> +.def 0 +1 1 +.r last$raw_n3f<28> last<28> +.def 0 +1 1 +.r last$raw_n3f<29> last<29> +.def 0 +1 1 +.latch _n369<0> last<0> +.latch _n369<1> last<1> +.latch _n369<2> last<2> +.latch _n369<3> last<3> +.latch _n369<4> last<4> +.latch _n369<5> last<5> +.latch _n369<6> last<6> +.latch _n369<7> last<7> +.latch _n369<8> last<8> +.latch _n369<9> last<9> +.latch _n369<10> last<10> +.latch _n369<11> last<11> +.latch _n369<12> last<12> +.latch _n369<13> last<13> +.latch _n369<14> last<14> +.latch _n369<15> last<15> +.latch _n369<16> last<16> +.latch _n369<17> last<17> +.latch _n369<18> last<18> +.latch _n369<19> last<19> +.latch _n369<20> last<20> +.latch _n369<21> last<21> +.latch _n369<22> last<22> +.latch _n369<23> last<23> +.latch _n369<24> last<24> +.latch _n369<25> last<25> +.latch _n369<26> last<26> +.latch _n369<27> last<27> +.latch _n369<28> last<28> +.latch _n369<29> last<29> +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/mult6x6/README =================================================================== --- vis_dev/vis-2.1/examples/mult6x6/README (revision 11) +++ vis_dev/vis-2.1/examples/mult6x6/README (revision 11) @@ -0,0 +1,5 @@ +$Id: README,v 1.2 1997/03/01 21:46:39 fabio Exp $ + +This directory contains a collection of 6x6 array multipliers. +Two of them are correct and two are buggy. The script in this directory +checks the equivalence of pairs of multipliers using res_verify. Index: vis_dev/vis-2.1/examples/mult6x6/braun6x6 =================================================================== --- vis_dev/vis-2.1/examples/mult6x6/braun6x6 (revision 11) +++ vis_dev/vis-2.1/examples/mult6x6/braun6x6 (revision 11) @@ -0,0 +1,358 @@ +.model braun6x6 +.inputs x<5> x<4> x<3> x<2> x<1> x<0> y<5> y<4> y<3> y<2> y<1> y<0> +.outputs z<11> z<10> z<9> z<8> z<7> z<6> z<5> z<4> z<3> z<2> z<1> z<0> +.names y<0> x<0> A0_0 +11 1 +.names y<1> x<0> A0_1 +11 1 +.names y<2> x<0> A0_2 +11 1 +.names y<3> x<0> A0_3 +11 1 +.names y<4> x<0> A0_4 +11 1 +.names y<5> x<0> A0_5 +11 1 +.names y<0> x<1> A1_0 +11 1 +.names y<1> x<1> A1_1 +11 1 +.names y<2> x<1> A1_2 +11 1 +.names y<3> x<1> A1_3 +11 1 +.names y<4> x<1> A1_4 +11 1 +.names y<5> x<1> A1_5 +11 1 +.names A0_1 A1_0 S1_0 +10 1 +01 1 +.names A0_1 A1_0 C1_0 +11 1 +.names A0_2 A1_1 S1_1 +10 1 +01 1 +.names A0_2 A1_1 C1_1 +11 1 +.names A0_3 A1_2 S1_2 +10 1 +01 1 +.names A0_3 A1_2 C1_2 +11 1 +.names A0_4 A1_3 S1_3 +10 1 +01 1 +.names A0_4 A1_3 C1_3 +11 1 +.names A0_5 A1_4 S1_4 +10 1 +01 1 +.names A0_5 A1_4 C1_4 +11 1 +.names y<0> x<2> A2_0 +11 1 +.names y<1> x<2> A2_1 +11 1 +.names y<2> x<2> A2_2 +11 1 +.names y<3> x<2> A2_3 +11 1 +.names y<4> x<2> A2_4 +11 1 +.names y<5> x<2> A2_5 +11 1 +.names S1_1 A2_0 C1_0 S2_0 +100 1 +010 1 +001 1 +111 1 +.names S1_1 A2_0 C1_0 C2_0 +110 1 +101 1 +011 1 +111 1 +.names S1_2 A2_1 C1_1 S2_1 +100 1 +010 1 +001 1 +111 1 +.names S1_2 A2_1 C1_1 C2_1 +110 1 +101 1 +011 1 +111 1 +.names S1_3 A2_2 C1_2 S2_2 +100 1 +010 1 +001 1 +111 1 +.names S1_3 A2_2 C1_2 C2_2 +110 1 +101 1 +011 1 +111 1 +.names S1_4 A2_3 C1_3 S2_3 +100 1 +010 1 +001 1 +111 1 +.names S1_4 A2_3 C1_3 C2_3 +110 1 +101 1 +011 1 +111 1 +.names A1_5 A2_4 C1_4 S2_4 +100 1 +010 1 +001 1 +111 1 +.names A1_5 A2_4 C1_4 C2_4 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<3> A3_0 +11 1 +.names y<1> x<3> A3_1 +11 1 +.names y<2> x<3> A3_2 +11 1 +.names y<3> x<3> A3_3 +11 1 +.names y<4> x<3> A3_4 +11 1 +.names y<5> x<3> A3_5 +11 1 +.names S2_1 A3_0 C2_0 S3_0 +100 1 +010 1 +001 1 +111 1 +.names S2_1 A3_0 C2_0 C3_0 +110 1 +101 1 +011 1 +111 1 +.names S2_2 A3_1 C2_1 S3_1 +100 1 +010 1 +001 1 +111 1 +.names S2_2 A3_1 C2_1 C3_1 +110 1 +101 1 +011 1 +111 1 +.names S2_3 A3_2 C2_2 S3_2 +100 1 +010 1 +001 1 +111 1 +.names S2_3 A3_2 C2_2 C3_2 +110 1 +101 1 +011 1 +111 1 +.names S2_4 A3_3 C2_3 S3_3 +100 1 +010 1 +001 1 +111 1 +.names S2_4 A3_3 C2_3 C3_3 +110 1 +101 1 +011 1 +111 1 +.names A2_5 A3_4 C2_4 S3_4 +100 1 +010 1 +001 1 +111 1 +.names A2_5 A3_4 C2_4 C3_4 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<4> A4_0 +11 1 +.names y<1> x<4> A4_1 +11 1 +.names y<2> x<4> A4_2 +11 1 +.names y<3> x<4> A4_3 +11 1 +.names y<4> x<4> A4_4 +11 1 +.names y<5> x<4> A4_5 +11 1 +.names S3_1 A4_0 C3_0 S4_0 +100 1 +010 1 +001 1 +111 1 +.names S3_1 A4_0 C3_0 C4_0 +110 1 +101 1 +011 1 +111 1 +.names S3_2 A4_1 C3_1 S4_1 +100 1 +010 1 +001 1 +111 1 +.names S3_2 A4_1 C3_1 C4_1 +110 1 +101 1 +011 1 +111 1 +.names S3_3 A4_2 C3_2 S4_2 +100 1 +010 1 +001 1 +111 1 +.names S3_3 A4_2 C3_2 C4_2 +110 1 +101 1 +011 1 +111 1 +.names S3_4 A4_3 C3_3 S4_3 +100 1 +010 1 +001 1 +111 1 +.names S3_4 A4_3 C3_3 C4_3 +110 1 +101 1 +011 1 +111 1 +.names A3_5 A4_4 C3_4 S4_4 +100 1 +010 1 +001 1 +111 1 +.names A3_5 A4_4 C3_4 C4_4 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<5> A5_0 +11 1 +.names y<1> x<5> A5_1 +11 1 +.names y<2> x<5> A5_2 +11 1 +.names y<3> x<5> A5_3 +11 1 +.names y<4> x<5> A5_4 +11 1 +.names y<5> x<5> A5_5 +11 1 +.names S4_1 A5_0 C4_0 S5_0 +100 1 +010 1 +001 1 +111 1 +.names S4_1 A5_0 C4_0 C5_0 +110 1 +101 1 +011 1 +111 1 +.names S4_2 A5_1 C4_1 S5_1 +100 1 +010 1 +001 1 +111 1 +.names S4_2 A5_1 C4_1 C5_1 +110 1 +101 1 +011 1 +111 1 +.names S4_3 A5_2 C4_2 S5_2 +100 1 +010 1 +001 1 +111 1 +.names S4_3 A5_2 C4_2 C5_2 +110 1 +101 1 +011 1 +111 1 +.names S4_4 A5_3 C4_3 S5_3 +100 1 +010 1 +001 1 +111 1 +.names S4_4 A5_3 C4_3 C5_3 +110 1 +101 1 +011 1 +111 1 +.names A4_5 A5_4 C4_4 S5_4 +100 1 +010 1 +001 1 +111 1 +.names A4_5 A5_4 C4_4 C5_4 +110 1 +101 1 +011 1 +111 1 +.names A0_0 z<0> +1 1 +.names S1_0 z<1> +1 1 +.names S2_0 z<2> +1 1 +.names S3_0 z<3> +1 1 +.names S4_0 z<4> +1 1 +.names S5_0 z<5> +1 1 +.names C5_0 S5_1 z<6> +10 1 +01 1 +.names C5_0 S5_1 C6_0 +11 1 +.names C6_0 C5_1 S5_2 z<7> +100 1 +010 1 +001 1 +111 1 +.names C6_0 C5_1 S5_2 C6_1 +110 1 +101 1 +011 1 +111 1 +.names C6_1 C5_2 S5_3 z<8> +100 1 +010 1 +001 1 +111 1 +.names C6_1 C5_2 S5_3 C6_2 +110 1 +101 1 +011 1 +111 1 +.names C6_2 C5_3 S5_4 z<9> +100 1 +010 1 +001 1 +111 1 +.names C6_2 C5_3 S5_4 C6_3 +110 1 +101 1 +011 1 +111 1 +.names C6_3 C5_4 A5_5 z<10> +100 1 +010 1 +001 1 +111 1 +.names C6_3 C5_4 A5_5 z<11> +110 1 +101 1 +011 1 +111 1 +.end Index: vis_dev/vis-2.1/examples/mult6x6/bug6x6A =================================================================== --- vis_dev/vis-2.1/examples/mult6x6/bug6x6A (revision 11) +++ vis_dev/vis-2.1/examples/mult6x6/bug6x6A (revision 11) @@ -0,0 +1,370 @@ +.model bug6x6A +.inputs x<5> x<4> x<3> x<2> x<1> x<0> y<5> y<4> y<3> y<2> y<1> y<0> +.outputs z<11> z<10> z<9> z<8> z<7> z<6> z<5> z<4> z<3> z<2> z<1> z<0> +.names y<0> x<0> A0_0 +11 1 +.names y<1> x<0> A0_1 +11 1 +.names y<2> x<0> A0_2 +11 1 +.names y<3> x<0> A0_3 +11 1 +.names y<4> x<0> A0_4 +11 1 +.names y<5> x<0> A0_5 +11 1 +.names y<0> x<1> A1_0 +11 1 +.names y<1> x<1> A1_1 +11 1 +.names y<2> x<1> A1_2 +11 1 +.names y<3> x<1> A1_3 +11 1 +.names y<4> x<1> A1_4 +11 1 +.names y<5> x<1> A1_5 +11 1 +.names A0_1 A1_0 S1_1 +10 1 +01 1 +.names A0_1 A1_0 C1_1 +11 1 +.names A0_2 A1_1 C1_1 S1_2 +100 1 +010 1 +001 1 +111 1 +.names A0_2 A1_1 C1_1 C1_2 +110 1 +101 1 +011 1 +111 1 +.names A0_3 A1_2 C1_2 S1_3 +100 1 +010 1 +001 1 +111 1 +.names A0_3 A1_2 C1_2 C1_3 +110 1 +101 1 +011 1 +111 1 +.names A0_4 A1_3 C1_3 S1_4 +100 1 +010 1 +001 1 +111 1 +.names A0_4 A1_3 C1_3 C1_4 +110 1 +101 1 +011 1 +111 1 +.names A0_5 A1_4 C1_4 S1_5 +100 1 +010 1 +001 1 +111 1 +.names A0_5 A1_4 C1_4 C1_5 +110 1 +101 1 +011 1 +111 1 +.names A1_5 C1_5 S1_6 +10 1 +01 1 +.names A1_5 C1_5 C1_6 +11 1 +.names y<0> x<2> A2_0 +11 1 +.names y<1> x<2> A2_1 +11 1 +.names y<2> x<2> A2_2 +11 1 +.names y<3> x<2> A2_3 +11 1 +.names y<4> x<2> A2_4 +11 1 +.names y<5> x<2> A2_5 +11 1 +.names S1_2 A2_0 S2_2 +10 1 +01 1 +.names S1_2 A2_0 C2_2 +11 1 +.names S1_3 A2_1 C2_2 S2_3 +100 1 +010 1 +001 1 +111 1 +.names S1_3 A2_1 C2_2 C2_3 +110 1 +101 1 +011 1 +111 1 +.names S1_4 A2_2 C2_3 S2_4 +100 1 +010 1 +001 1 +111 1 +.names S1_4 A2_2 C2_3 C2_4 +110 1 +101 1 +011 1 +111 1 +.names S1_5 A2_3 C2_4 S2_5 +100 1 +010 1 +001 1 +111 1 +.names S1_5 A2_3 C2_4 C2_5 +110 1 +101 1 +011 1 +111 1 +.names S1_6 A2_4 C2_5 S2_6 +100 1 +010 1 +001 1 +111 1 +.names S1_6 A2_4 C2_5 C2_6 +110 1 +101 1 +011 1 +111 1 +.names C1_6 A2_5 C2_6 S2_7 +100 1 +010 1 +001 1 +111 1 +.names C1_6 A2_5 C2_6 C2_7 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<3> A3_0 +11 1 +.names y<1> x<3> A3_1 +11 1 +.names y<2> x<3> A3_2 +01 1 +.names y<3> x<3> A3_3 +11 1 +.names y<4> x<3> A3_4 +11 1 +.names y<5> x<3> A3_5 +11 1 +.names S2_3 A3_0 S3_3 +10 1 +01 1 +.names S2_3 A3_0 C3_3 +11 1 +.names S2_4 A3_1 C3_3 S3_4 +100 1 +010 1 +001 1 +111 1 +.names S2_4 A3_1 C3_3 C3_4 +110 1 +101 1 +011 1 +111 1 +.names S2_5 A3_2 C3_4 S3_5 +100 1 +010 1 +001 1 +111 1 +.names S2_5 A3_2 C3_4 C3_5 +110 1 +101 1 +011 1 +111 1 +.names S2_6 A3_3 C3_5 S3_6 +100 1 +010 1 +001 1 +111 1 +.names S2_6 A3_3 C3_5 C3_6 +110 1 +101 1 +011 1 +111 1 +.names S2_7 A3_4 C3_6 S3_7 +100 1 +010 1 +001 1 +111 1 +.names S2_7 A3_4 C3_6 C3_7 +110 1 +101 1 +011 1 +111 1 +.names C2_7 A3_5 C3_7 S3_8 +100 1 +010 1 +001 1 +111 1 +.names C2_7 A3_5 C3_7 C3_8 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<4> A4_0 +11 1 +.names y<1> x<4> A4_1 +11 1 +.names y<2> x<4> A4_2 +11 1 +.names y<3> x<4> A4_3 +11 1 +.names y<4> x<4> A4_4 +11 1 +.names y<5> x<4> A4_5 +11 1 +.names S3_4 A4_0 S4_4 +10 1 +01 1 +.names S3_4 A4_0 C4_4 +11 1 +.names S3_5 A4_1 C4_4 S4_5 +100 1 +010 1 +001 1 +111 1 +.names S3_5 A4_1 C4_4 C4_5 +110 1 +101 1 +011 1 +111 1 +.names S3_6 A4_2 C4_5 S4_6 +100 1 +010 1 +001 1 +111 1 +.names S3_6 A4_2 C4_5 C4_6 +110 1 +101 1 +011 1 +111 1 +.names S3_7 A4_3 C4_6 S4_7 +100 1 +010 1 +001 1 +111 1 +.names S3_7 A4_3 C4_6 C4_7 +110 1 +101 1 +011 1 +111 1 +.names S3_8 A4_4 C4_7 S4_8 +100 1 +010 1 +001 1 +111 1 +.names S3_8 A4_4 C4_7 C4_8 +110 1 +101 1 +011 1 +111 1 +.names C3_8 A4_5 C4_8 S4_9 +100 1 +010 1 +001 1 +111 1 +.names C3_8 A4_5 C4_8 C4_9 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<5> A5_0 +11 1 +.names y<1> x<5> A5_1 +11 1 +.names y<2> x<5> A5_2 +11 1 +.names y<3> x<5> A5_3 +11 1 +.names y<4> x<5> A5_4 +11 1 +.names y<5> x<5> A5_5 +11 1 +.names S4_5 A5_0 S5_5 +10 1 +01 1 +.names S4_5 A5_0 C5_5 +11 1 +.names S4_6 A5_1 C5_5 S5_6 +100 1 +010 1 +001 1 +111 1 +.names S4_6 A5_1 C5_5 C5_6 +110 1 +101 1 +011 1 +111 1 +.names S4_7 A5_2 C5_6 S5_7 +100 1 +010 1 +001 1 +111 1 +.names S4_7 A5_2 C5_6 C5_7 +110 1 +101 1 +011 1 +111 1 +.names S4_8 A5_3 C5_7 S5_8 +100 1 +010 1 +001 1 +111 1 +.names S4_8 A5_3 C5_7 C5_8 +110 1 +101 1 +011 1 +111 1 +.names S4_9 A5_4 C5_8 S5_9 +100 1 +010 1 +001 1 +011 1 +.names S4_9 A5_4 C5_8 C5_9 +110 1 +101 1 +011 1 +111 1 +.names C4_9 A5_5 C5_9 S5_10 +100 1 +010 1 +001 1 +111 1 +.names C4_9 A5_5 C5_9 C5_10 +110 1 +101 1 +011 1 +111 1 +.names A0_0 z<0> +1 1 +.names S1_1 z<1> +1 1 +.names S2_2 z<2> +1 1 +.names S3_3 z<3> +1 1 +.names S4_4 z<4> +1 1 +.names S5_5 z<5> +1 1 +.names S5_6 z<6> +1 1 +.names S5_7 z<7> +1 1 +.names S5_8 z<8> +1 1 +.names S5_9 z<9> +1 1 +.names S5_10 z<10> +1 1 +.names C5_10 z<11> +1 1 +.end Index: vis_dev/vis-2.1/examples/mult6x6/bug6x6B =================================================================== --- vis_dev/vis-2.1/examples/mult6x6/bug6x6B (revision 11) +++ vis_dev/vis-2.1/examples/mult6x6/bug6x6B (revision 11) @@ -0,0 +1,370 @@ +.model bug6x6B +.inputs x<5> x<4> x<3> x<2> x<1> x<0> y<5> y<4> y<3> y<2> y<1> y<0> +.outputs z<11> z<10> z<9> z<8> z<7> z<6> z<5> z<4> z<3> z<2> z<1> z<0> +.names y<0> x<0> A0_0 +11 1 +.names y<1> x<0> A0_1 +11 1 +.names y<2> x<0> A0_2 +11 1 +.names y<3> x<0> A0_3 +11 1 +.names y<4> x<0> A0_4 +11 1 +.names y<5> x<0> A0_5 +11 1 +.names y<0> x<1> A1_0 +11 1 +.names y<1> x<1> A1_1 +11 1 +.names y<2> x<1> A1_2 +11 1 +.names y<3> x<1> A1_3 +11 1 +.names y<4> x<1> A1_4 +11 1 +.names y<5> x<1> A1_5 +11 1 +.names A0_1 A1_0 S1_1 +10 1 +01 1 +.names A0_1 A1_0 C1_1 +11 1 +.names A0_2 A1_1 C1_1 S1_2 +100 1 +010 1 +001 1 +111 1 +.names A0_2 A1_1 C1_1 C1_2 +110 1 +101 1 +011 1 +111 1 +.names A0_3 A1_2 C1_2 S1_3 +100 1 +010 1 +001 1 +111 1 +.names A0_3 A1_2 C1_2 C1_3 +110 1 +101 1 +011 1 +111 1 +.names A0_4 A1_3 C1_3 S1_4 +100 1 +010 1 +001 1 +111 1 +.names A0_4 A1_3 C1_3 C1_4 +110 1 +101 1 +011 1 +111 1 +.names A0_5 A1_4 C1_4 S1_5 +100 1 +010 1 +001 1 +111 1 +.names A0_5 A1_4 C1_4 C1_5 +110 1 +101 1 +011 1 +111 1 +.names A1_5 C1_5 S1_6 +10 1 +01 1 +.names A1_5 C1_5 C1_6 +11 1 +.names y<0> x<2> A2_0 +11 1 +.names y<1> x<2> A2_1 +11 1 +.names y<2> x<2> A2_2 +11 1 +.names y<3> x<2> A2_3 +11 1 +.names y<4> x<2> A2_4 +11 1 +.names y<5> x<2> A2_5 +11 1 +.names S1_2 A2_0 S2_2 +10 1 +01 1 +.names S1_2 A2_0 C2_2 +11 1 +.names S1_3 A2_1 C2_2 S2_3 +100 1 +010 1 +001 1 +111 1 +.names S1_3 A2_1 C2_2 C2_3 +110 1 +101 1 +011 1 +111 1 +.names S1_4 A2_2 C2_3 S2_4 +100 1 +010 1 +001 1 +111 1 +.names S1_4 A2_2 C2_3 C2_4 +110 1 +101 1 +011 1 +111 1 +.names S1_5 A2_3 C2_4 S2_5 +100 1 +010 1 +001 1 +111 1 +.names S1_5 A2_3 C2_4 C2_5 +110 1 +101 1 +011 1 +111 1 +.names S1_6 A2_4 C2_5 S2_6 +100 1 +010 1 +001 1 +111 1 +.names S1_6 A2_4 C2_5 C2_6 +110 1 +101 1 +011 1 +111 1 +.names C1_6 A2_5 C2_6 S2_7 +100 1 +010 1 +001 1 +111 1 +.names C1_6 A2_5 C2_6 C2_7 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<3> A3_0 +11 1 +.names y<1> x<3> A3_1 +11 1 +.names y<2> x<3> A3_2 +11 1 +.names y<3> x<3> A3_3 +11 1 +.names y<4> x<3> A3_4 +11 1 +.names y<5> x<3> A3_5 +11 1 +.names S2_3 A3_0 S3_3 +10 1 +01 1 +.names S2_3 A3_0 C3_3 +11 1 +.names S2_4 A3_1 C3_3 S3_4 +100 1 +010 1 +001 1 +111 1 +.names S2_4 A3_1 C3_3 C3_4 +110 1 +101 1 +011 1 +111 1 +.names S2_5 A3_2 C3_4 S3_5 +100 1 +010 1 +001 1 +111 1 +.names S2_5 A3_2 C3_4 C3_5 +110 1 +101 1 +011 1 +111 1 +.names S2_6 A3_3 C3_5 S3_6 +100 1 +010 1 +001 1 +111 1 +.names S2_6 A3_3 C3_5 C3_6 +110 1 +101 1 +011 1 +111 1 +.names S2_7 A3_4 C3_6 S3_7 +100 1 +010 1 +001 1 +111 1 +.names S2_7 A3_4 C3_6 C3_7 +110 1 +101 1 +011 1 +111 1 +.names C2_7 A3_5 C3_7 S3_8 +100 1 +010 1 +001 1 +111 1 +.names C2_7 A3_5 C3_7 C3_8 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<4> A4_0 +11 1 +.names y<1> x<4> A4_1 +11 1 +.names y<2> x<4> A4_2 +11 1 +.names y<3> x<4> A4_3 +11 1 +.names y<4> x<4> A4_4 +11 1 +.names y<5> x<4> A4_5 +11 1 +.names S3_4 A4_0 S4_4 +10 1 +01 1 +.names S3_4 A4_0 C4_4 +11 1 +.names S3_5 A4_1 C4_4 S4_5 +100 1 +010 1 +001 1 +111 1 +.names S3_5 A4_1 C4_4 C4_5 +110 1 +101 1 +011 1 +111 1 +.names S3_6 A4_2 C4_5 S4_6 +100 1 +010 1 +001 1 +111 1 +.names S3_6 A4_2 C4_5 C4_6 +110 1 +101 1 +011 1 +111 1 +.names S3_7 A4_3 C4_6 S4_7 +100 1 +010 1 +001 1 +111 1 +.names S3_7 A4_3 C4_6 C4_7 +110 1 +101 1 +011 1 +111 1 +.names S3_8 A4_4 C4_7 S4_8 +100 1 +010 1 +001 1 +111 1 +.names S3_8 A4_4 C4_7 C4_8 +110 1 +101 1 +011 1 +111 1 +.names C3_8 A4_5 C4_8 S4_9 +100 1 +010 1 +001 1 +111 1 +.names C3_8 A4_5 C4_8 C4_9 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<5> A5_0 +11 1 +.names y<1> x<5> A5_1 +11 1 +.names y<2> x<5> A5_2 +11 1 +.names y<3> x<5> A5_3 +11 1 +.names y<4> x<5> A5_4 +11 1 +.names y<5> x<5> A5_5 +11 1 +.names S4_5 A5_0 S5_5 +10 1 +01 1 +.names S4_5 A5_0 C5_5 +11 1 +.names S4_6 A5_1 C5_5 S5_6 +100 1 +010 1 +001 1 +111 1 +.names S4_6 A5_1 C5_5 C5_6 +110 1 +101 1 +011 1 +111 1 +.names S4_7 A5_2 C5_6 S5_7 +100 1 +010 1 +001 1 +111 1 +.names S4_7 A5_2 C5_6 C5_7 +110 1 +101 1 +011 1 +111 1 +.names S4_8 A5_3 C5_7 S5_8 +100 1 +010 1 +001 1 +111 1 +.names S4_8 A5_3 C5_7 C5_8 +110 1 +101 1 +011 1 +111 1 +.names S4_9 A5_4 C5_8 S5_9 +100 1 +010 1 +001 1 +111 1 +.names S4_9 A5_4 C5_8 C5_9 +110 1 +101 1 +011 1 +111 1 +.names C4_9 A5_5 C5_9 S5_10 +100 1 +010 1 +001 1 +111 1 +.names C4_9 A5_5 C5_9 C5_10 +100 1 +101 1 +011 1 +111 1 +.names A0_0 z<0> +1 1 +.names S1_1 z<1> +1 1 +.names S2_2 z<2> +1 1 +.names S3_3 z<3> +1 1 +.names S4_4 z<4> +1 1 +.names S5_5 z<5> +1 1 +.names S5_6 z<6> +1 1 +.names S5_7 z<7> +1 1 +.names S5_8 z<8> +1 1 +.names S5_9 z<9> +1 1 +.names S5_10 z<10> +1 1 +.names C5_10 z<11> +1 1 +.end Index: vis_dev/vis-2.1/examples/mult6x6/check_result =================================================================== --- vis_dev/vis-2.1/examples/mult6x6/check_result (revision 11) +++ vis_dev/vis-2.1/examples/mult6x6/check_result (revision 11) @@ -0,0 +1,6 @@ +Residue Direct Verification successful. +Residue Verification successful +Residue Direct Verification failed at output node z<5> of the spec. +Residue Verification failed ! +Residue Direct Verification successful. +Residue Verification failed ! Index: vis_dev/vis-2.1/examples/mult6x6/check_script =================================================================== --- vis_dev/vis-2.1/examples/mult6x6/check_script (revision 11) +++ vis_dev/vis-2.1/examples/mult6x6/check_script (revision 11) @@ -0,0 +1,23 @@ +read_blif simple6x6 +flatten_hierarchy +set residue_verbosity 0 +set residue_layer_schedule alap +set residue_composition_method vector +res_verify -d 10 -o order6x6 -i braun6x6 + +read_blif bug6x6A +flatten_hierarchy +set residue_verbosity 0 +set residue_layer_schedule alap +set residue_composition_method vector +res_verify -d 10 -o order6x6 -i braun6x6 + + +read_blif bug6x6B +flatten_hierarchy +set residue_verbosity 0 +set residue_layer_schedule alap +set residue_composition_method vector +res_verify -d 10 -o order6x6 -i braun6x6 + +quit -s Index: vis_dev/vis-2.1/examples/mult6x6/order6x6 =================================================================== --- vis_dev/vis-2.1/examples/mult6x6/order6x6 (revision 11) +++ vis_dev/vis-2.1/examples/mult6x6/order6x6 (revision 11) @@ -0,0 +1,2 @@ +z<11> z<10> z<9> z<8> z<7> z<6> z<5> z<4> z<3> z<2> z<1> z<0> + Index: vis_dev/vis-2.1/examples/mult6x6/simple6x6 =================================================================== --- vis_dev/vis-2.1/examples/mult6x6/simple6x6 (revision 11) +++ vis_dev/vis-2.1/examples/mult6x6/simple6x6 (revision 11) @@ -0,0 +1,370 @@ +.model mult6x6 +.inputs x<5> x<4> x<3> x<2> x<1> x<0> y<5> y<4> y<3> y<2> y<1> y<0> +.outputs z<11> z<10> z<9> z<8> z<7> z<6> z<5> z<4> z<3> z<2> z<1> z<0> +.names y<0> x<0> A0_0 +11 1 +.names y<1> x<0> A0_1 +11 1 +.names y<2> x<0> A0_2 +11 1 +.names y<3> x<0> A0_3 +11 1 +.names y<4> x<0> A0_4 +11 1 +.names y<5> x<0> A0_5 +11 1 +.names y<0> x<1> A1_0 +11 1 +.names y<1> x<1> A1_1 +11 1 +.names y<2> x<1> A1_2 +11 1 +.names y<3> x<1> A1_3 +11 1 +.names y<4> x<1> A1_4 +11 1 +.names y<5> x<1> A1_5 +11 1 +.names A0_1 A1_0 S1_1 +10 1 +01 1 +.names A0_1 A1_0 C1_1 +11 1 +.names A0_2 A1_1 C1_1 S1_2 +100 1 +010 1 +001 1 +111 1 +.names A0_2 A1_1 C1_1 C1_2 +110 1 +101 1 +011 1 +111 1 +.names A0_3 A1_2 C1_2 S1_3 +100 1 +010 1 +001 1 +111 1 +.names A0_3 A1_2 C1_2 C1_3 +110 1 +101 1 +011 1 +111 1 +.names A0_4 A1_3 C1_3 S1_4 +100 1 +010 1 +001 1 +111 1 +.names A0_4 A1_3 C1_3 C1_4 +110 1 +101 1 +011 1 +111 1 +.names A0_5 A1_4 C1_4 S1_5 +100 1 +010 1 +001 1 +111 1 +.names A0_5 A1_4 C1_4 C1_5 +110 1 +101 1 +011 1 +111 1 +.names A1_5 C1_5 S1_6 +10 1 +01 1 +.names A1_5 C1_5 C1_6 +11 1 +.names y<0> x<2> A2_0 +11 1 +.names y<1> x<2> A2_1 +11 1 +.names y<2> x<2> A2_2 +11 1 +.names y<3> x<2> A2_3 +11 1 +.names y<4> x<2> A2_4 +11 1 +.names y<5> x<2> A2_5 +11 1 +.names S1_2 A2_0 S2_2 +10 1 +01 1 +.names S1_2 A2_0 C2_2 +11 1 +.names S1_3 A2_1 C2_2 S2_3 +100 1 +010 1 +001 1 +111 1 +.names S1_3 A2_1 C2_2 C2_3 +110 1 +101 1 +011 1 +111 1 +.names S1_4 A2_2 C2_3 S2_4 +100 1 +010 1 +001 1 +111 1 +.names S1_4 A2_2 C2_3 C2_4 +110 1 +101 1 +011 1 +111 1 +.names S1_5 A2_3 C2_4 S2_5 +100 1 +010 1 +001 1 +111 1 +.names S1_5 A2_3 C2_4 C2_5 +110 1 +101 1 +011 1 +111 1 +.names S1_6 A2_4 C2_5 S2_6 +100 1 +010 1 +001 1 +111 1 +.names S1_6 A2_4 C2_5 C2_6 +110 1 +101 1 +011 1 +111 1 +.names C1_6 A2_5 C2_6 S2_7 +100 1 +010 1 +001 1 +111 1 +.names C1_6 A2_5 C2_6 C2_7 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<3> A3_0 +11 1 +.names y<1> x<3> A3_1 +11 1 +.names y<2> x<3> A3_2 +11 1 +.names y<3> x<3> A3_3 +11 1 +.names y<4> x<3> A3_4 +11 1 +.names y<5> x<3> A3_5 +11 1 +.names S2_3 A3_0 S3_3 +10 1 +01 1 +.names S2_3 A3_0 C3_3 +11 1 +.names S2_4 A3_1 C3_3 S3_4 +100 1 +010 1 +001 1 +111 1 +.names S2_4 A3_1 C3_3 C3_4 +110 1 +101 1 +011 1 +111 1 +.names S2_5 A3_2 C3_4 S3_5 +100 1 +010 1 +001 1 +111 1 +.names S2_5 A3_2 C3_4 C3_5 +110 1 +101 1 +011 1 +111 1 +.names S2_6 A3_3 C3_5 S3_6 +100 1 +010 1 +001 1 +111 1 +.names S2_6 A3_3 C3_5 C3_6 +110 1 +101 1 +011 1 +111 1 +.names S2_7 A3_4 C3_6 S3_7 +100 1 +010 1 +001 1 +111 1 +.names S2_7 A3_4 C3_6 C3_7 +110 1 +101 1 +011 1 +111 1 +.names C2_7 A3_5 C3_7 S3_8 +100 1 +010 1 +001 1 +111 1 +.names C2_7 A3_5 C3_7 C3_8 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<4> A4_0 +11 1 +.names y<1> x<4> A4_1 +11 1 +.names y<2> x<4> A4_2 +11 1 +.names y<3> x<4> A4_3 +11 1 +.names y<4> x<4> A4_4 +11 1 +.names y<5> x<4> A4_5 +11 1 +.names S3_4 A4_0 S4_4 +10 1 +01 1 +.names S3_4 A4_0 C4_4 +11 1 +.names S3_5 A4_1 C4_4 S4_5 +100 1 +010 1 +001 1 +111 1 +.names S3_5 A4_1 C4_4 C4_5 +110 1 +101 1 +011 1 +111 1 +.names S3_6 A4_2 C4_5 S4_6 +100 1 +010 1 +001 1 +111 1 +.names S3_6 A4_2 C4_5 C4_6 +110 1 +101 1 +011 1 +111 1 +.names S3_7 A4_3 C4_6 S4_7 +100 1 +010 1 +001 1 +111 1 +.names S3_7 A4_3 C4_6 C4_7 +110 1 +101 1 +011 1 +111 1 +.names S3_8 A4_4 C4_7 S4_8 +100 1 +010 1 +001 1 +111 1 +.names S3_8 A4_4 C4_7 C4_8 +110 1 +101 1 +011 1 +111 1 +.names C3_8 A4_5 C4_8 S4_9 +100 1 +010 1 +001 1 +111 1 +.names C3_8 A4_5 C4_8 C4_9 +110 1 +101 1 +011 1 +111 1 +.names y<0> x<5> A5_0 +11 1 +.names y<1> x<5> A5_1 +11 1 +.names y<2> x<5> A5_2 +11 1 +.names y<3> x<5> A5_3 +11 1 +.names y<4> x<5> A5_4 +11 1 +.names y<5> x<5> A5_5 +11 1 +.names S4_5 A5_0 S5_5 +10 1 +01 1 +.names S4_5 A5_0 C5_5 +11 1 +.names S4_6 A5_1 C5_5 S5_6 +100 1 +010 1 +001 1 +111 1 +.names S4_6 A5_1 C5_5 C5_6 +110 1 +101 1 +011 1 +111 1 +.names S4_7 A5_2 C5_6 S5_7 +100 1 +010 1 +001 1 +111 1 +.names S4_7 A5_2 C5_6 C5_7 +110 1 +101 1 +011 1 +111 1 +.names S4_8 A5_3 C5_7 S5_8 +100 1 +010 1 +001 1 +111 1 +.names S4_8 A5_3 C5_7 C5_8 +110 1 +101 1 +011 1 +111 1 +.names S4_9 A5_4 C5_8 S5_9 +100 1 +010 1 +001 1 +111 1 +.names S4_9 A5_4 C5_8 C5_9 +110 1 +101 1 +011 1 +111 1 +.names C4_9 A5_5 C5_9 S5_10 +100 1 +010 1 +001 1 +111 1 +.names C4_9 A5_5 C5_9 C5_10 +110 1 +101 1 +011 1 +111 1 +.names A0_0 z<0> +1 1 +.names S1_1 z<1> +1 1 +.names S2_2 z<2> +1 1 +.names S3_3 z<3> +1 1 +.names S4_4 z<4> +1 1 +.names S5_5 z<5> +1 1 +.names S5_6 z<6> +1 1 +.names S5_7 z<7> +1 1 +.names S5_8 z<8> +1 1 +.names S5_9 z<9> +1 1 +.names S5_10 z<10> +1 1 +.names C5_10 z<11> +1 1 +.end Index: vis_dev/vis-2.1/examples/ping_pong/README =================================================================== --- vis_dev/vis-2.1/examples/ping_pong/README (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong/README (revision 11) @@ -0,0 +1,39 @@ +This directory has the verilog and pif files that are consistent +with the tutorial on ping_pong. So this directory should be put in +the examples directory for regression testing. + +For the language containment test on properties never_no_balls and +infinitely_often_hit, these have been put into ping_pong.v as +monitors. Without their fairness constraints, they have no effect +(except for expanding the state space). It turns out that the ioh property +cannot be expressed with just Buchi fairness constraints. So +there are not special fairness constraints and the property is +stated in terms of a CTL formula (prop2.ctl). + +The various commands that should be run on it are: + +read_blif_mv ping_pong.mv +init +compute_reach -v 1 +# reachable # states is 5 +read_fairness prop1.fair +compute_reach -v 1 +# reachable # states is still 5 +mc lang_empt.ctl +#this should pass + +read_fairness ping_pong.fair +mc prop2.ctl +#this should pass + +mc lang_empt.ctl +#this should fail + +mc ping_pong.ctl +# Both formulas should pass + +# now flush the fairness constraints. +read_fairness all.fair +mc ping_pong.ctl +#The first one should pass and the last should fail + Index: vis_dev/vis-2.1/examples/ping_pong/check_result =================================================================== --- vis_dev/vis-2.1/examples/ping_pong/check_result (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong/check_result (revision 11) @@ -0,0 +1,10 @@ +FSM depth = 2 +reachable states = 5 +# LE: language is not empty +# LE: language emptiness check passes +# LE: language is not empty +# MC: formula passed --- AG((ioh.state=PENDING -> AF(ioh.state=OKAY))) +# MC: formula passed --- AG((player_A.state=BALL + player_B.state=BALL)) +# MC: formula passed --- AF((player_A.state=BALL ^ player_B.state=BALL)) +# MC: formula passed --- AG((player_A.state=BALL + player_B.state=BALL)) +# MC: formula failed --- AF((player_A.state=BALL ^ player_B.state=BALL)) Index: vis_dev/vis-2.1/examples/ping_pong/check_script =================================================================== --- vis_dev/vis-2.1/examples/ping_pong/check_script (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong/check_script (revision 11) @@ -0,0 +1,25 @@ +read_blif_mv ping_pong.mv +init_verify +compute_reach -v 1 +print_fairness +lang_empty -d 0 +# reachable # states is 5 +read_fairness prop1.fair +print_fairness +lang_empty -d 0 +#this should pass +read_fairness ping_pong.fair +print_fairness +lang_empty -d 0 +#this should fail +model_check -d 0 prop2.ctl +#this should pass +model_check -d 0 ping_pong.ctl +# Both formulas should pass +# now flush the fairness constraints. +reset_fairness +print_fairness +model_check -d 0 ping_pong.ctl +#The first one should pass and the last should fail +time +quit -s Index: vis_dev/vis-2.1/examples/ping_pong/ping_pong.ctl =================================================================== --- vis_dev/vis-2.1/examples/ping_pong/ping_pong.ctl (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong/ping_pong.ctl (revision 11) @@ -0,0 +1,10 @@ +# There is always at least one ball in play. +AG((player_A.state=BALL) + (player_B.state=BALL)); + +# If player_A is not hitting the ball right now, then he will sometime +# in the future. +#AG((ping_pong.player_A.me=NO_HIT) => AF(ping_pong.player_A.me=HIT)); +# this formula is not consistant with a Kripke structure. + +# Eventually, only one ball is in play. +AF((player_A.state=BALL) ^ (player_B.state=BALL)); Index: vis_dev/vis-2.1/examples/ping_pong/ping_pong.fair =================================================================== --- vis_dev/vis-2.1/examples/ping_pong/ping_pong.fair (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong/ping_pong.fair (revision 11) @@ -0,0 +1,8 @@ +#.model player +#.state st1 = state:BALL +#.negfair +#.subsets {st1} +#.endfair +#.endmodel +!(player_A.state=BALL); +!(player_B.state=BALL); Index: vis_dev/vis-2.1/examples/ping_pong/ping_pong.inv =================================================================== --- vis_dev/vis-2.1/examples/ping_pong/ping_pong.inv (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong/ping_pong.inv (revision 11) @@ -0,0 +1,2 @@ +# There is always at least one ball in play. +(player_A.state=BALL + player_B.state=BALL); Index: vis_dev/vis-2.1/examples/ping_pong/ping_pong.mv =================================================================== --- vis_dev/vis-2.1/examples/ping_pong/ping_pong.mv (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong/ping_pong.mv (revision 11) @@ -0,0 +1,336 @@ +# vl2mv ping_pong.v +# version: 0.2 +# date: 11:16:44 12/11/95 (PST) +.model ping_pong +# I/O ports + +.mv action_A 2 HIT NO_HIT +.mv state_B 2 BALL NO_BALL +.mv action_B 2 HIT NO_HIT +.mv state_A 2 BALL NO_BALL +.subckt player player_A opponent=action_B me=action_A state=state_A +.subckt player player_B opponent=action_A me=action_B state=state_B +.subckt never_no_balls nnb state_A=state_A state_B=state_B +.subckt infinitely_often_hit ioh player_action=action_A +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model player +# I/O ports +.outputs me +.outputs state +.inputs opponent + +.mv me 2 HIT NO_HIT +.mv state 2 BALL NO_BALL +.mv random 2 HIT NO_HIT +.mv opponent 2 HIT NO_HIT +# state = 0 +.mv state$raw_n0 2 BALL NO_BALL +.names state$raw_n0 +BALL +# non-blocking assignments for initial +# assign random = $NDset ( 0,1 ) +.names random +HIT +NO_HIT +# assign me = (state == BALL ) ? random : 1 +.mv me$raw_n3 2 HIT NO_HIT +.mv _n5 2 BALL NO_BALL +.names _n5 +BALL +# state == 0 +.names state _n5 _n4 +.def 0 +- =state 1 +.mv _n6 2 HIT NO_HIT +.names _n6 +NO_HIT +# (state == 0) ? random : 1 +.mv _n7 2 HIT NO_HIT +.names random _n6 _n4 _n7 +- - 0 =_n6 +- - 1 =random +.names _n7 me$raw_n3 +- =_n7 +.mv _na 2 BALL NO_BALL +.names _na +BALL +.names state _na _n9 +.def 0 +- =state 1 +.names _n9 _n8 +1 1 +0 0 +.mv _nc 2 HIT NO_HIT +.names _nc +HIT +# me == 0 +.names me _nc _nb +.def 0 +- =me 1 +.mv _ne 2 HIT NO_HIT +.names _ne +NO_HIT +# opponent == 1 +.names opponent _ne _nd +.def 0 +- =opponent 1 +# (me == 0) && (opponent == 1) +.names _nb _nd _nf +.def 0 +1 1 1 +.names _nf _n10 +- =_nf +# state = 1 +.mv state$_nf_n11$true 2 BALL NO_BALL +.names state$_nf_n11$true +NO_BALL +# if/else ((me == 0) && (opponent == 1)) +.mv state$_nf$raw_n14 2 BALL NO_BALL +.names state$_nf_n11$true state _nf state$_nf$raw_n14 +- - 0 =state +- - 1 =state$_nf_n11$true +.mv _n17 2 BALL NO_BALL +.names _n17 +NO_BALL +.names state _n17 _n16 +.def 0 +- =state 1 +.names _n16 _n15 +1 1 +0 0 +.mv _n19 2 HIT NO_HIT +.names _n19 +HIT +# opponent == 0 +.names opponent _n19 _n18 +.def 0 +- =opponent 1 +.names _n18 _n1a +- =_n18 +# state = 0 +.mv state$_n18_n1b$true 2 BALL NO_BALL +.names state$_n18_n1b$true +BALL +# if/else (opponent == 0) +.mv state$_n18$raw_n1e 2 BALL NO_BALL +.names state$_n18_n1b$true state _n18 state$_n18$raw_n1e +- - 0 =state +- - 1 =state$_n18_n1b$true +# case (state ) +.mv state$_n15$raw_n21 2 BALL NO_BALL +.names state$_n18$raw_n1e state _n15 state$_n15$raw_n21 +- - 0 =state +- - 1 =state$_n18$raw_n1e +.mv state$_n8$raw_n23 2 BALL NO_BALL +.names state$_nf$raw_n14 state$_n15$raw_n21 _n8 state$_n8$raw_n23 +- - 0 =state$_n15$raw_n21 +- - 1 =state$_nf$raw_n14 +# conflict arbitrators +.names me$raw_n3 me +- =me$raw_n3 +.names _n8 _n10 _n15 _n1a _n26 +.def 0 + 1 1 - - 1 + 0 - 1 1 1 +.mv _n27 2 BALL NO_BALL +.names _n26 state$_n8$raw_n23 state _n27 +1 - - =state$_n8$raw_n23 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n0 state +- =state$raw_n0 +.latch _n27 state +# quasi-continuous assignment +.end + + +.model never_no_balls +# I/O ports +.inputs state_B +.inputs state_A + +.mv state_B 2 BALL NO_BALL +.mv state 2 GOOD BAD +.mv state_A 2 BALL NO_BALL +# state = 0 +.mv state$raw_n2b 2 GOOD BAD +.names state$raw_n2b +GOOD +# non-blocking assignments for initial +.mv _n2e 2 GOOD BAD +.names _n2e +GOOD +.names state _n2e _n2d +.def 0 +- =state 1 +.names _n2d _n2c +1 1 +0 0 +.mv _n30 2 BALL NO_BALL +.names _n30 +NO_BALL +# state_A == 1 +.names state_A _n30 _n2f +.def 0 +- =state_A 1 +.mv _n32 2 BALL NO_BALL +.names _n32 +NO_BALL +# state_B == 1 +.names state_B _n32 _n31 +.def 0 +- =state_B 1 +# (state_A == 1) && (state_B == 1) +.names _n2f _n31 _n33 +.def 0 +1 1 1 +.names _n33 _n34 +- =_n33 +# state = 1 +.mv state$_n33_n35$true 2 GOOD BAD +.names state$_n33_n35$true +BAD +# if/else ((state_A == 1) && (state_B == 1)) +.mv state$_n33$raw_n38 2 GOOD BAD +.names state$_n33_n35$true state _n33 state$_n33$raw_n38 +- - 0 =state +- - 1 =state$_n33_n35$true +.mv _n3b 2 GOOD BAD +.names _n3b +BAD +.names state _n3b _n3a +.def 0 +- =state 1 +.names _n3a _n39 +1 1 +0 0 +# state = 1 +.mv state$_n39_n3c$true 2 GOOD BAD +.names state$_n39_n3c$true +BAD +# case (state ) +.mv state$_n39$raw_n3f 2 GOOD BAD +.names state$_n39_n3c$true state _n39 state$_n39$raw_n3f +- - 0 =state +- - 1 =state$_n39_n3c$true +.mv state$_n2c$raw_n41 2 GOOD BAD +.names state$_n33$raw_n38 state$_n39$raw_n3f _n2c state$_n2c$raw_n41 +- - 0 =state$_n39$raw_n3f +- - 1 =state$_n33$raw_n38 +# conflict arbitrators +.names _n2c _n34 _n39 _n44 +.def 0 + 1 1 - 1 + 0 - 1 1 +.mv _n45 2 GOOD BAD +.names _n44 state$_n2c$raw_n41 state _n45 +1 - - =state$_n2c$raw_n41 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n2b state +- =state$raw_n2b +.latch _n45 state +# quasi-continuous assignment +.end + + +.model infinitely_often_hit +# I/O ports +.inputs player_action + +.mv player_action 2 HIT NO_HIT +.mv state 2 OKAY PENDING +# state = 0 +.mv state$raw_n47 2 OKAY PENDING +.names state$raw_n47 +OKAY +# non-blocking assignments for initial +.mv _n4a 2 OKAY PENDING +.names _n4a +OKAY +.names state _n4a _n49 +.def 0 +- =state 1 +.names _n49 _n48 +1 1 +0 0 +.mv _n4c 2 HIT NO_HIT +.names _n4c +NO_HIT +# player_action == 1 +.names player_action _n4c _n4b +.def 0 +- =player_action 1 +.names _n4b _n4d +- =_n4b +# state = 1 +.mv state$_n4b_n4e$true 2 OKAY PENDING +.names state$_n4b_n4e$true +PENDING +# if/else (player_action == 1) +.mv state$_n4b$raw_n51 2 OKAY PENDING +.names state$_n4b_n4e$true state _n4b state$_n4b$raw_n51 +- - 0 =state +- - 1 =state$_n4b_n4e$true +.mv _n54 2 OKAY PENDING +.names _n54 +PENDING +.names state _n54 _n53 +.def 0 +- =state 1 +.names _n53 _n52 +1 1 +0 0 +.mv _n56 2 HIT NO_HIT +.names _n56 +HIT +# player_action == 0 +.names player_action _n56 _n55 +.def 0 +- =player_action 1 +.names _n55 _n57 +- =_n55 +# state = 0 +.mv state$_n55_n58$true 2 OKAY PENDING +.names state$_n55_n58$true +OKAY +# if/else (player_action == 0) +.mv state$_n55$raw_n5b 2 OKAY PENDING +.names state$_n55_n58$true state _n55 state$_n55$raw_n5b +- - 0 =state +- - 1 =state$_n55_n58$true +# case (state ) +.mv state$_n52$raw_n5e 2 OKAY PENDING +.names state$_n55$raw_n5b state _n52 state$_n52$raw_n5e +- - 0 =state +- - 1 =state$_n55$raw_n5b +.mv state$_n48$raw_n60 2 OKAY PENDING +.names state$_n4b$raw_n51 state$_n52$raw_n5e _n48 state$_n48$raw_n60 +- - 0 =state$_n52$raw_n5e +- - 1 =state$_n4b$raw_n51 +# conflict arbitrators +.names _n48 _n4d _n52 _n57 _n63 +.def 0 + 1 1 - - 1 + 0 - 1 1 1 +.mv _n64 2 OKAY PENDING +.names _n63 state$_n48$raw_n60 state _n64 +1 - - =state$_n48$raw_n60 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n47 state +- =state$raw_n47 +.latch _n64 state +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/ping_pong/ping_pong.v =================================================================== --- vis_dev/vis-2.1/examples/ping_pong/ping_pong.v (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong/ping_pong.v (revision 11) @@ -0,0 +1,141 @@ +/* + * This code implements a game of ping pong (table tennis) between 2 players, with + * a slight twist: each player puts a ball into play at the same time. There can + * be an indefinite delay from the time one player hits a ball until the time that + * the other player returns it. If both balls are in play, then both players + * always hit each ball at the same instant. + * + * While both balls are in play, exactly one player may choose not to return his + * ball. This leaves one ball in play. If just one ball is in play, the ball + * should remain in play forever. + */ + +typedef enum {BALL, NO_BALL} player_status; +typedef enum {HIT, NO_HIT} action_type; + +module ping_pong(clk); +input clk; + +/* signal declarations */ +action_type wire action_A, action_B; +player_status wire state_A, state_B; + +/* the ping pong players */ +player player_A(clk, action_B, action_A, state_A); +player player_B(clk, action_A, action_B, state_B); + +never_no_balls nnb(clk, state_A, state_B); +infinitely_often_hit ioh(clk, action_A); + +endmodule + + +/* + * Two state process. If the player doesn't have the ball (state NO_BALL) and the + * opponent hits the ball, then go to state BALL. If the player has the ball, then + * if he doesn't hit the ball, then he remains in state BALL. If he hits the ball, + * and the opponent doesn't also hit the ball, then go to state NO_BALL. + */ +module player(clk, opponent, me, state); +input clk; +input opponent; +output me; +output state; + +action_type wire opponent, me, random; +player_status reg state; + +initial state = BALL; + +/* set the value of the output of the player */ + +assign random = $ND(HIT, NO_HIT); +assign me = (state == BALL) ? random : NO_HIT; + +always @(posedge clk) begin + case(state) + BALL: + begin + if ((me == HIT) && (opponent == NO_HIT)) + state = NO_BALL; + end + + NO_BALL: + begin + if (opponent == HIT) + state = BALL; + end + + default:; + endcase; +end +endmodule + +/* + * If it's ever the case that neither player has a ball, then go to state BAD + * and stay there. + */ +typedef enum {GOOD, BAD} prop1_status; + +module never_no_balls(clk, state_A, state_B); +input clk; +input state_A; +input state_B; + +player_status wire state_A, state_B; +prop1_status reg state; + +initial state = GOOD; + +always @(posedge clk) begin + case(state) + GOOD: + begin + if ((state_A == NO_BALL) && (state_B == NO_BALL)) + state = BAD; + end + + BAD: + begin + state = BAD; + end + + default:; + endcase; +end +endmodule + + +/* + * If player does not hit the ball now, then he will sometime in the future. + */ +typedef enum {OKAY, PENDING} prop2_status; + +module infinitely_often_hit(clk, player_action); +input clk; +input player_action; + +action_type wire player_action; +prop2_status reg state; + +initial state = OKAY; + +always @(posedge clk) begin + case(state) + OKAY: + begin + if (player_action == NO_HIT) + state = PENDING; + end + + PENDING: + begin + if (player_action == HIT) + state = OKAY; + end + + default:; + endcase; +end +endmodule + Index: vis_dev/vis-2.1/examples/ping_pong/prop1.fair =================================================================== --- vis_dev/vis-2.1/examples/ping_pong/prop1.fair (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong/prop1.fair (revision 11) @@ -0,0 +1,8 @@ +#.include ping_pong.fair +!(player_A.state=BALL); +!(player_B.state=BALL); + +# begin fairness constraints on monitor nnb. +# The fairness constraints allow only bad behavior. + +(nnb.state = BAD); Index: vis_dev/vis-2.1/examples/ping_pong/prop2.ctl =================================================================== --- vis_dev/vis-2.1/examples/ping_pong/prop2.ctl (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong/prop2.ctl (revision 11) @@ -0,0 +1,1 @@ +AG((ioh.state=PENDING)->AF(ioh.state=OKAY)); Index: vis_dev/vis-2.1/examples/ping_pong_new/README =================================================================== --- vis_dev/vis-2.1/examples/ping_pong_new/README (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong_new/README (revision 11) @@ -0,0 +1,8 @@ +Shiple +19 NOV 1993 + +This example is a modification and extension of the original ping pong +example. In particular, the nondeterminism of player was moved from +the output to the transitions. This permits the exclusion of just the +behavior where the player is forever IDLE. Also, two instances of +ping pong balls has been added. Index: vis_dev/vis-2.1/examples/ping_pong_new/affalse =================================================================== --- vis_dev/vis-2.1/examples/ping_pong_new/affalse (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong_new/affalse (revision 11) @@ -0,0 +1,1 @@ +AF FALSE; Index: vis_dev/vis-2.1/examples/ping_pong_new/agtrue =================================================================== --- vis_dev/vis-2.1/examples/ping_pong_new/agtrue (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong_new/agtrue (revision 11) @@ -0,0 +1,1 @@ +AG TRUE; Index: vis_dev/vis-2.1/examples/ping_pong_new/check_result =================================================================== --- vis_dev/vis-2.1/examples/ping_pong_new/check_result (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong_new/check_result (revision 11) @@ -0,0 +1,15 @@ +FSM depth = 6 +reachable states = 16 +# LE: language is not empty +# MC: formula failed --- AF(FALSE) +# MC: formula passed --- AG(TRUE) +# MC: formula passed --- AG(!((ball_1.state=OUT_OF_PLAY * ball_2.state=OUT_OF_PLAY))) +# MC: formula passed --- AG((player_A.out=IDLE -> AF(player_A.out=HIT))) +# MC: formula failed --- AF((ball_1.state=OUT_OF_PLAY ^ ball_2.state=OUT_OF_PLAY)) +# MC: formula passed --- EF((ball_1.state=OUT_OF_PLAY ^ ball_2.state=OUT_OF_PLAY)) +# MC: formula failed --- AG((!(ball_1.state=OUT_OF_PLAY) * !(ball_2.state=OUT_OF_PLAY))) +# MC: formula passed --- AG(!((ball_1.state=OUT_OF_PLAY * ball_2.state=OUT_OF_PLAY))) +# MC: formula failed --- AG((player_A.out=IDLE -> AF(player_A.out=HIT))) +# MC: formula failed --- AF((ball_1.state=OUT_OF_PLAY ^ ball_2.state=OUT_OF_PLAY)) +# MC: formula passed --- EF((ball_1.state=OUT_OF_PLAY ^ ball_2.state=OUT_OF_PLAY)) +# MC: formula failed --- AG((!(ball_1.state=OUT_OF_PLAY) * !(ball_2.state=OUT_OF_PLAY))) Index: vis_dev/vis-2.1/examples/ping_pong_new/check_script =================================================================== --- vis_dev/vis-2.1/examples/ping_pong_new/check_script (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong_new/check_script (revision 11) @@ -0,0 +1,15 @@ +read_blif_mv ping_pong_new.mv +init_verify +compute_reach -v 1 +print_fairness +lang_empty -d 0 +model_check -d 0 affalse +model_check -d 0 agtrue +read_fairness ping_pong_new.fair +print_fairness +model_check -d 0 ping_pong_new.ctl +reset_fairness +print_fairness +model_check -d 0 ping_pong_new.ctl +time +quit -s Index: vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.ctl =================================================================== --- vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.ctl (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.ctl (revision 11) @@ -0,0 +1,21 @@ +# there is always at least one ball in play +# (passes with or without fairness constraint) +AG(!((ball_1.state=OUT_OF_PLAY) * (ball_2.state=OUT_OF_PLAY))); + +# if player_A produces IDLE now, then he will HIT sometime +# in the future (only passes with fairness constraint) +AG((player_A.out=IDLE) -> AF(player_A.out=HIT)); + +# Eventually only one ball is in play. Note ^ denotes XOR. +# (should fail with or without fairness constraints) +AF((ball_1.state=OUT_OF_PLAY) ^ (ball_2.state=OUT_OF_PLAY)); + +# There exists the possibility that eventually only one ball +# is in play (should pass with or without fairness constraints) +EF((ball_1.state=OUT_OF_PLAY) ^ (ball_2.state=OUT_OF_PLAY)); + +# there are always two balls in play +# (fails with or without fairness constraint) +AG(!(ball_1.state=OUT_OF_PLAY) * !(ball_2.state=OUT_OF_PLAY)); + + Index: vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.fair =================================================================== --- vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.fair (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.fair (revision 11) @@ -0,0 +1,8 @@ +#.model player +#.state st1 = state:WAIT_COMING +#.negfair +#.subsets {st1} +#.endfair +#.endmodel +!(player_A.state=WAIT_COMING); +!(player_B.state=WAIT_COMING); Index: vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.mv =================================================================== --- vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.mv (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.mv (revision 11) @@ -0,0 +1,365 @@ +# vl2mv ping_pong_new.v +# version: 0.2 +# date: 11:17:06 12/11/95 (PST) +.model ping_pong +# I/O ports + +.mv state_ball_2 3 TO_A TO_B OUT_OF_PLAY +.mv state_ball_1 3 TO_A TO_B OUT_OF_PLAY +.mv action_A 2 HIT IDLE +.mv state_B 3 HIT WAIT_GOING WAIT_COMING +.mv action_B 2 HIT IDLE +.mv state_A 3 HIT WAIT_GOING WAIT_COMING +.subckt player player_A opponent=action_B out=action_A state=state_A +.subckt player player_B opponent=action_A out=action_B state=state_B +.mv _n0 3 TO_A TO_B OUT_OF_PLAY +.names _n0 +TO_A +.subckt ball ball_1 action_A=action_A action_B=action_B state=state_ball_1 init=_n0 +.mv _n1 3 TO_A TO_B OUT_OF_PLAY +.names _n1 +TO_B +.subckt ball ball_2 action_A=action_A action_B=action_B state=state_ball_2 init=_n1 +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model player +# I/O ports +.outputs out +.outputs state +.inputs opponent + +.mv out 2 HIT IDLE +.mv r_state 3 HIT WAIT_GOING WAIT_COMING +.mv state 3 HIT WAIT_GOING WAIT_COMING +.mv opponent 2 HIT IDLE +# assign out = (state == 0) ? 0 : 1 +.mv out$raw_n2 2 HIT IDLE +.mv _n4 3 HIT WAIT_GOING WAIT_COMING +.names _n4 +HIT +# state == 0 +.names state _n4 _n3 +.def 0 +- =state 1 +.mv _n5 2 HIT IDLE +.names _n5 +HIT +.mv _n6 2 HIT IDLE +.names _n6 +IDLE +# (state == 0) ? 0 : 1 +.mv _n7 2 HIT IDLE +.names _n5 _n6 _n3 _n7 +- - 0 =_n6 +- - 1 =_n5 +.names _n7 out$raw_n2 +- =_n7 +# assign r_state = $NDset ( 2,0 ) +.names r_state +WAIT_COMING +HIT +# state = 0 +.mv state$raw_na 3 HIT WAIT_GOING WAIT_COMING +.names state$raw_na +HIT +# non-blocking assignments for initial +.mv _nd 3 HIT WAIT_GOING WAIT_COMING +.names _nd +HIT +.names state _nd _nc +.def 0 +- =state 1 +.names _nc _nb +1 1 +0 0 +.mv _nf 2 HIT IDLE +.names _nf +IDLE +# opponent == 1 +.names opponent _nf _ne +.def 0 +- =opponent 1 +.names _ne _n10 +- =_ne +# state = 1 +.mv state$_ne_n11$true 3 HIT WAIT_GOING WAIT_COMING +.names state$_ne_n11$true +WAIT_GOING +.mv _n13 2 HIT IDLE +.names _n13 +HIT +# opponent == 0 +.names opponent _n13 _n12 +.def 0 +- =opponent 1 +.names _n12 _n14 +- =_n12 +# state = 2 +.mv state$_n12_n15$true 3 HIT WAIT_GOING WAIT_COMING +.names state$_n12_n15$true +WAIT_COMING +# if/else (opponent == 0) +.mv state$_n12$raw_n18 3 HIT WAIT_GOING WAIT_COMING +.names state$_n12_n15$true state _n12 state$_n12$raw_n18 +- - 0 =state +- - 1 =state$_n12_n15$true +# if/else (opponent == 1) +.mv state$_ne$raw_n1a 3 HIT WAIT_GOING WAIT_COMING +.names state$_ne_n11$true state$_n12$raw_n18 _ne state$_ne$raw_n1a +- - 0 =state$_n12$raw_n18 +- - 1 =state$_ne_n11$true +.mv _n1f 3 HIT WAIT_GOING WAIT_COMING +.names _n1f +WAIT_GOING +.names state _n1f _n1e +.def 0 +- =state 1 +.names _n1e _n1d +1 1 +0 0 +.mv _n21 2 HIT IDLE +.names _n21 +HIT +# opponent == 0 +.names opponent _n21 _n20 +.def 0 +- =opponent 1 +.names _n20 _n22 +- =_n20 +# state = 2 +.mv state$_n20_n23$true 3 HIT WAIT_GOING WAIT_COMING +.names state$_n20_n23$true +WAIT_COMING +# if/else (opponent == 0) +.mv state$_n20$raw_n26 3 HIT WAIT_GOING WAIT_COMING +.names state$_n20_n23$true state _n20 state$_n20$raw_n26 +- - 0 =state +- - 1 =state$_n20_n23$true +.mv _n29 3 HIT WAIT_GOING WAIT_COMING +.names _n29 +WAIT_COMING +.names state _n29 _n28 +.def 0 +- =state 1 +.names _n28 _n27 +1 1 +0 0 +# state = r_state +.mv state$_n27_n2a$true 3 HIT WAIT_GOING WAIT_COMING +.names r_state state$_n27_n2a$true +- =r_state +# case (state ) +.mv state$_n27$raw_n2d 3 HIT WAIT_GOING WAIT_COMING +.names state$_n27_n2a$true state _n27 state$_n27$raw_n2d +- - 0 =state +- - 1 =state$_n27_n2a$true +.mv state$_n1d$raw_n2f 3 HIT WAIT_GOING WAIT_COMING +.names state$_n20$raw_n26 state$_n27$raw_n2d _n1d state$_n1d$raw_n2f +- - 0 =state$_n27$raw_n2d +- - 1 =state$_n20$raw_n26 +.mv state$_nb$raw_n33 3 HIT WAIT_GOING WAIT_COMING +.names state$_ne$raw_n1a state$_n1d$raw_n2f _nb state$_nb$raw_n33 +- - 0 =state$_n1d$raw_n2f +- - 1 =state$_ne$raw_n1a +# conflict arbitrators +.names out$raw_n2 out +- =out$raw_n2 +.names _nb _n10 _n14 _n1d _n22 _n27 _n36 +.def 0 + 1 1 - - - - 1 + 1 0 1 - - - 1 + 0 - - 1 1 - 1 + 0 - - 0 - 1 1 +.mv _n37 3 HIT WAIT_GOING WAIT_COMING +.names _n36 state$_nb$raw_n33 state _n37 +1 - - =state$_nb$raw_n33 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_na state +- =state$raw_na +.latch _n37 state +# quasi-continuous assignment +.end + + +.model ball +# I/O ports +.inputs action_A +.inputs action_B +.outputs state +.inputs init + +.mv action_A 2 HIT IDLE +.mv action_B 2 HIT IDLE +.mv state 3 TO_A TO_B OUT_OF_PLAY +.mv init 3 TO_A TO_B OUT_OF_PLAY +# state = init +.mv state$raw_n3c 3 TO_A TO_B OUT_OF_PLAY +.names init state$raw_n3c +- =init +# non-blocking assignments for initial +.mv _n3f 3 TO_A TO_B OUT_OF_PLAY +.names _n3f +TO_A +.names state _n3f _n3e +.def 0 +- =state 1 +.names _n3e _n3d +1 1 +0 0 +.mv _n41 2 HIT IDLE +.names _n41 +HIT +# action_A == 0 +.names action_A _n41 _n40 +.def 0 +- =action_A 1 +.names _n40 _n42 +- =_n40 +# state = 1 +.mv state$_n40_n43$true 3 TO_A TO_B OUT_OF_PLAY +.names state$_n40_n43$true +TO_B +.mv _n45 2 HIT IDLE +.names _n45 +IDLE +# action_A == 1 +.names action_A _n45 _n44 +.def 0 +- =action_A 1 +.mv _n47 2 HIT IDLE +.names _n47 +HIT +# action_B == 0 +.names action_B _n47 _n46 +.def 0 +- =action_B 1 +# (action_A == 1) && (action_B == 0) +.names _n44 _n46 _n48 +.def 0 +1 1 1 +.names _n48 _n49 +- =_n48 +# state = 2 +.mv state$_n48_n4a$true 3 TO_A TO_B OUT_OF_PLAY +.names state$_n48_n4a$true +OUT_OF_PLAY +# if/else ((action_A == 1) && (action_B == 0)) +.mv state$_n48$raw_n4d 3 TO_A TO_B OUT_OF_PLAY +.names state$_n48_n4a$true state _n48 state$_n48$raw_n4d +- - 0 =state +- - 1 =state$_n48_n4a$true +# if/else (action_A == 0) +.mv state$_n40$raw_n4f 3 TO_A TO_B OUT_OF_PLAY +.names state$_n40_n43$true state$_n48$raw_n4d _n40 state$_n40$raw_n4f +- - 0 =state$_n48$raw_n4d +- - 1 =state$_n40_n43$true +.mv _n54 3 TO_A TO_B OUT_OF_PLAY +.names _n54 +TO_B +.names state _n54 _n53 +.def 0 +- =state 1 +.names _n53 _n52 +1 1 +0 0 +.mv _n56 2 HIT IDLE +.names _n56 +HIT +# action_B == 0 +.names action_B _n56 _n55 +.def 0 +- =action_B 1 +.names _n55 _n57 +- =_n55 +# state = 0 +.mv state$_n55_n58$true 3 TO_A TO_B OUT_OF_PLAY +.names state$_n55_n58$true +TO_A +.mv _n5a 2 HIT IDLE +.names _n5a +IDLE +# action_B == 1 +.names action_B _n5a _n59 +.def 0 +- =action_B 1 +.mv _n5c 2 HIT IDLE +.names _n5c +HIT +# action_A == 0 +.names action_A _n5c _n5b +.def 0 +- =action_A 1 +# (action_B == 1) && (action_A == 0) +.names _n59 _n5b _n5d +.def 0 +1 1 1 +.names _n5d _n5e +- =_n5d +# state = 2 +.mv state$_n5d_n5f$true 3 TO_A TO_B OUT_OF_PLAY +.names state$_n5d_n5f$true +OUT_OF_PLAY +# if/else ((action_B == 1) && (action_A == 0)) +.mv state$_n5d$raw_n62 3 TO_A TO_B OUT_OF_PLAY +.names state$_n5d_n5f$true state _n5d state$_n5d$raw_n62 +- - 0 =state +- - 1 =state$_n5d_n5f$true +# if/else (action_B == 0) +.mv state$_n55$raw_n64 3 TO_A TO_B OUT_OF_PLAY +.names state$_n55_n58$true state$_n5d$raw_n62 _n55 state$_n55$raw_n64 +- - 0 =state$_n5d$raw_n62 +- - 1 =state$_n55_n58$true +.mv _n69 3 TO_A TO_B OUT_OF_PLAY +.names _n69 +OUT_OF_PLAY +.names state _n69 _n68 +.def 0 +- =state 1 +.names _n68 _n67 +1 1 +0 0 +# state = 2 +.mv state$_n67_n6a$true 3 TO_A TO_B OUT_OF_PLAY +.names state$_n67_n6a$true +OUT_OF_PLAY +# case (state ) +.mv state$_n67$raw_n6d 3 TO_A TO_B OUT_OF_PLAY +.names state$_n67_n6a$true state _n67 state$_n67$raw_n6d +- - 0 =state +- - 1 =state$_n67_n6a$true +.mv state$_n52$raw_n6f 3 TO_A TO_B OUT_OF_PLAY +.names state$_n55$raw_n64 state$_n67$raw_n6d _n52 state$_n52$raw_n6f +- - 0 =state$_n67$raw_n6d +- - 1 =state$_n55$raw_n64 +.mv state$_n3d$raw_n73 3 TO_A TO_B OUT_OF_PLAY +.names state$_n40$raw_n4f state$_n52$raw_n6f _n3d state$_n3d$raw_n73 +- - 0 =state$_n52$raw_n6f +- - 1 =state$_n40$raw_n4f +# conflict arbitrators +.names _n3d _n42 _n49 _n52 _n57 _n5e _n67 _n76 +.def 0 + 1 1 - - - - - 1 + 1 0 1 - - - - 1 + 0 - - 1 1 - - 1 + 0 - - 1 0 1 - 1 + 0 - - 0 - - 1 1 +.mv _n77 3 TO_A TO_B OUT_OF_PLAY +.names _n76 state$_n3d$raw_n73 state _n77 +1 - - =state$_n3d$raw_n73 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n3c state +- =state$raw_n3c +.latch _n77 state +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.v =================================================================== --- vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.v (revision 11) +++ vis_dev/vis-2.1/examples/ping_pong_new/ping_pong_new.v (revision 11) @@ -0,0 +1,143 @@ +/* + * This code implements a game of ping pong (table tennis) between 2 players, with + * a slight twist: each player puts a ball into play at the same time. There can + * be an arbitrary, but finite, delay from the time one player hits a ball until + * the time that the other player returns it. If both balls are in play, then + * both players always hit each ball at the same instant. + * + * While both balls are in play, exactly one player may choose not to return his + * ball. This leaves one ball in play. If just one ball is in play, the ball + * should remain in play forever. + * + */ + +typedef enum {HIT, WAIT_GOING, WAIT_COMING} player_status; +typedef enum {HIT, IDLE} action_type; +typedef enum {TO_A, TO_B, OUT_OF_PLAY} ball_status; + +module ping_pong(clk); +input clk; + +/* signal declarations */ +action_type wire action_A, action_B; +player_status wire state_A, state_B; +ball_status wire state_ball_1, state_ball_2; + +/* the ping pong players */ +player player_A(clk, action_B, action_A, state_A); +player player_B(clk, action_A, action_B, state_B); + +/* the balls */ +ball ball_1(clk, action_A, action_B, state_ball_1, TO_A); +ball ball_2(clk, action_A, action_B, state_ball_2, TO_B); + +endmodule + +/* + * Three state process. If the player is waiting while the ball is going away from + * him (state WAIT_GOING) and the opponent hits the ball, then go to state WAIT_COMING. + * The player can remain in state WAIT_COMING an arbitrary, but finite, amount of time. + * The player non-deterministically moves from state WAIT_COMING to state HIT. From + * state HIT, the player immediately hits the ball. Depending on the action of the + * opponent, the player either moves to state WAIT_GOING or to state WAIT_COMING. + * + * Note that in state WAIT_GOING, there is only one ball still in play. Also, in state + * WAIT_COMING, it's possible that there is a ball going away, as well as coming towards + * the player. However, in state WAIT_GOING, there cannot be a ball coming towards + * the player. + */ +module player(clk, opponent, out, state); +input clk; +input opponent; +output out; +output state; + +action_type wire opponent, out; +player_status reg state; +player_status wire r_state; + +assign out = (state==HIT) ? HIT : IDLE; +assign r_state = $ND(WAIT_COMING, HIT); + +initial state = HIT; + +always @(posedge clk) begin + case(state) + HIT: + begin + if (opponent == IDLE) + state = WAIT_GOING; + else if (opponent == HIT) + state = WAIT_COMING; + end + + WAIT_GOING: + begin + if (opponent == HIT) + state = WAIT_COMING; + end + + WAIT_COMING: + begin + state = r_state; + end + + default:; + endcase; +end +endmodule + + +/* + * Three state process. The ball is either going towards player A + * (state TO_A) or towards B. If it's ever the case that the ball + * is going towards A, and A is IDLE and B HITS another ball, then + * this ball goes OUT_OF_PLAY, since two balls are now going + * towards A, and the assumption is that A cannot return both balls. + * The symmetic case holds when in TO_B. + * + * Note that this module does not produce any outputs (except for its + * state, which is read only by the property). Thus, if the + * property being checked just deals directly with the players, then + * the balls can be safely ignored. + */ +module ball(clk, action_A, action_B, state, init); +input clk; +input action_A, action_B; +input init; +output state; + +action_type wire action_A, action_B; +ball_status reg state; +ball_status wire init; + +initial state = init; + +always @(posedge clk) begin + case(state) + TO_A: + begin + if (action_A == HIT) + state = TO_B; + else if ((action_A == IDLE) && (action_B == HIT)) + state = OUT_OF_PLAY; + end + + TO_B: + begin + if (action_B == HIT) + state = TO_A; + else if ((action_B == IDLE) && (action_A == HIT)) + state = OUT_OF_PLAY; + end + + OUT_OF_PLAY: + begin + state = OUT_OF_PLAY; + end + + default:; + endcase; +end +endmodule + Index: vis_dev/vis-2.1/examples/production_cell/README =================================================================== --- vis_dev/vis-2.1/examples/production_cell/README (revision 11) +++ vis_dev/vis-2.1/examples/production_cell/README (revision 11) @@ -0,0 +1,32 @@ +$Id: README,v 1.1 1998/09/18 14:26:52 abel Exp $ + +Production Cell: + +This examples was obtained from: + +@InBook{Lindne94, + author = {Thomas Lindner}, + title = {Case Study "Production Cell": A Comparative Study in Formal + Software Development}, + chapter = 2, + publisher = {FZI}, + year = 1994, + pages = {9,21} +} + +It models the control of a plant in which a crane, two conveyor belts, a +rotating table, an articulated arm and a press are involved. The system is +closed, that is, there are no inputs. + +The movement of all the pieces has been discretized and encoded. The number of +latches that the FSM will have is strongly dependent on the resolution chosen +for these encodings. That would be a possible way to obtain a more challenging +problem out of the same example. A parametric description, with one parameter +for each encoding would be ideal. + +The formulas verified in the model refer to the limitation in the mobility of +the different parts (safety) as well as the continuous progress of the system. + +See prodcell.ctl for the detailed set of formulas. + +Author: Abelardo Pardo Index: vis_dev/vis-2.1/examples/production_cell/check_result =================================================================== --- vis_dev/vis-2.1/examples/production_cell/check_result (revision 11) +++ vis_dev/vis-2.1/examples/production_cell/check_result (revision 11) @@ -0,0 +1,20 @@ +# ABS: formula failed --- NOT[ AG(!((TC.Crane.HorizontalPos=OverFB * TC.CraneCNTR.HorizontalMove=GoLeft))) ] +# ABS: formula failed --- NOT[ AG(!((TC.Crane.HorizontalPos=OverDB * TC.CraneCNTR.HorizontalMove=GoRight))) ] +# ABS: formula failed --- NOT[ AG(!((TC.Crane.HorizontalPos=Middle * !(TC.Crane.VerticalPos=UpMost)))) ] +# ABS: formula failed --- NOT[ AG(!((TC.Crane.HorizontalPos=OverDB * TC.Crane.VerticalPos=FBHight))) ] +# ABS: formula failed --- NOT[ AG(!((TC.Crane.VerticalPos=UpMost * TC.CraneCNTR.VerticalMove=GoUp))) ] +# ABS: formula failed --- NOT[ AG(!((TC.Crane.VerticalPos=FBHight * TC.CraneCNTR.VerticalMove=GoDown))) ] +# ABS: formula failed --- NOT[ AG((!(TC.Crane.HorizontalMove=Stop) -> TC.CraneCNTR.VerticalPos=UpMost)) ] +# ABS: formula passed --- NOT[ AG(!(((PR.Pr.PressPosition=Mid * AR.Arm.RALoadArm=Extended) * AR.Arm.RAAnglePos=OverLoadedPress))) ] +# ABS: formula failed --- NOT[ AG(!(((PR.Pr.PressPosition=Top * AR.Arm.RAUnLoadArm=Extended) * AR.Arm.RAAnglePos=OverUnLoadedPress))) ] +# ABS: formula failed --- NOT[ AG((DB.DBeltCNTR.PieceOutDB=Y -> AF(TC.CraneCNTR.PieceGrabbedFromDB=Y))) ] +# MC: formula passed --- AG(!((TC.Crane.HorizontalPos=OverFB * TC.CraneCNTR.HorizontalMove=GoLeft))) +# MC: formula passed --- AG(!((TC.Crane.HorizontalPos=OverDB * TC.CraneCNTR.HorizontalMove=GoRight))) +# MC: formula passed --- AG(!((TC.Crane.HorizontalPos=Middle * !(TC.Crane.VerticalPos=UpMost)))) +# MC: formula passed --- AG(!((TC.Crane.HorizontalPos=OverDB * TC.Crane.VerticalPos=FBHight))) +# MC: formula passed --- AG(!((TC.Crane.VerticalPos=UpMost * TC.CraneCNTR.VerticalMove=GoUp))) +# MC: formula passed --- AG(!((TC.Crane.VerticalPos=FBHight * TC.CraneCNTR.VerticalMove=GoDown))) +# MC: formula passed --- AG((!(TC.Crane.HorizontalMove=Stop) -> TC.CraneCNTR.VerticalPos=UpMost)) +# MC: formula failed --- AG(!(((PR.Pr.PressPosition=Mid * AR.Arm.RALoadArm=Extended) * AR.Arm.RAAnglePos=OverLoadedPress))) +# MC: formula passed --- AG(!(((PR.Pr.PressPosition=Top * AR.Arm.RAUnLoadArm=Extended) * AR.Arm.RAAnglePos=OverUnLoadedPress))) +# MC: formula passed --- AG((DB.DBeltCNTR.PieceOutDB=Y -> AF(TC.CraneCNTR.PieceGrabbedFromDB=Y))) Index: vis_dev/vis-2.1/examples/production_cell/check_script =================================================================== --- vis_dev/vis-2.1/examples/production_cell/check_script (revision 11) +++ vis_dev/vis-2.1/examples/production_cell/check_script (revision 11) @@ -0,0 +1,11 @@ +read_blif_mv prodcell.mv +flatten_hierarchy +static_order -s input_and_latch prodcell.ord +build_partition_mdds +incremental_ctl_verification -n -D2 -s prodcell.ctl +flatten_hierarchy +static_order -s input_and_latch prodcell.ord +build_partition_mdds +set image_farside_method 1 +model_check -c -r -D0 -i -v2 -d1 prodcell.ctl +quit -s Index: vis_dev/vis-2.1/examples/production_cell/prodcell.ctl =================================================================== --- vis_dev/vis-2.1/examples/production_cell/prodcell.ctl (revision 11) +++ vis_dev/vis-2.1/examples/production_cell/prodcell.ctl (revision 11) @@ -0,0 +1,113 @@ +# +# Specification for the ProductionCell +# +# WARNING: All the formulas are included here, but only a few of them are used +# for the check_script +# +# Author: Abelardo Pardo +# +# Limitation of Mobility for the Travelling Crane +# +AG(!((TC.Crane.HorizontalPos = OverFB) * + (TC.CraneCNTR.HorizontalMove = GoLeft))); # 1 +AG(!((TC.Crane.HorizontalPos = OverDB) * + (TC.CraneCNTR.HorizontalMove = GoRight))); # 2 +AG(!((TC.Crane.HorizontalPos = Middle) * + (!(TC.Crane.VerticalPos = UpMost)))); # 3 +AG(!((TC.Crane.HorizontalPos = OverDB) * + (TC.Crane.VerticalPos = FBHight))); # 4 +AG(!(TC.Crane.VerticalPos = UpMost * + TC.CraneCNTR.VerticalMove = GoUp)); # 5 +AG(!(TC.Crane.VerticalPos = FBHight * + TC.CraneCNTR.VerticalMove = GoDown)); # 6 +AG(!TC.Crane.HorizontalMove = Stop -> + TC.CraneCNTR.VerticalPos = UpMost); # 7 +# +# Limitation of Mobility of the Rotary Table +# +#AG(!(RT.RTable.RTAngle = S * +# RT.RTableCNTR.RTRotaryMotor = CWise)); # 8 +#AG(!(RT.RTable.RTAngle = SE * +# RT.RTableCNTR.RTRotaryMotor = CCWise)); # 9 +#AG(!(RT.RTable.RTHight = Top * +# RT.RTableCNTR.RTVerticalMotor = GoUp)); # 10 +#AG(!(RT.RTable.RTHight = Bot * +# RT.RTableCNTR.RTVerticalMotor = GoDown)); # 11 +# +# Limitation of Mobility of the Rotary Arm +# +#AG(!(AR.Arm.RAAnglePos = OverRT * +# AR.ACNTR.RARotaryMotor = CWise)); # 12 +#AG(!(AR.Arm.RAAnglePos = OverLoadedPress * +# AR.ACNTR.RARotaryMotor = CCWise)); # 13 +#AG(!(AR.Arm.RALoadArm = Retracted * +# AR.ACNTR.RAExtendLoadArm = Retract)); # 14 +#AG(!(AR.Arm.RALoadArm = Extended * +# AR.ACNTR.RAExtendLoadArm = Extend)); # 15 +#AG(!(AR.Arm.RAUnLoadArm = Retracted * +# AR.ACNTR.RAExtendUnLoadArm = Retract)); # 16 +#AG(!(AR.Arm.RAUnLoadArm = Extended * +# AR.ACNTR.RAExtendUnLoadArm = Extend)); # 17 +#AG(!((!AR.Arm.RALoadArm = Retracted) * +# (!AR.Arm.RAUnLoadArm = Retracted))); # 18 +#AG(!AR.ACNTR.RARotaryMotor = Stop -> +# (AR.Arm.RALoadArm = Retracted * AR.Arm.RAUnLoadArm = Retracted)); # 19 +# +# Limitation of Mobility for the Press +# +#AG(!(PR.Pr.PressPosition = Top * PR.PrCNTR.PressMotor = GoUp)); # 20 +#AG(!(PR.Pr.PressPosition = Bot * PR.PrCNTR.PressMotor = GoDown)); # 21 +#AG((AR.Arm.RAAnglePos = OverLoadedPress * !AR.Arm.RALoadArm = Retracted) +# -> PR.Pr.PressPosition = Mid); # 22 +AG(!(PR.Pr.PressPosition = Mid * AR.Arm.RALoadArm = Extended * + AR.Arm.RAAnglePos = OverLoadedPress)); # 23 +AG(!(PR.Pr.PressPosition = Top * AR.Arm.RAUnLoadArm = Extended * + AR.Arm.RAAnglePos = OverUnLoadedPress)); # 24 +# +# Correctness of the communication protocol DB -> Crane +# +AG(DB.DBeltCNTR.PieceOutDB = Y -> + AF(TC.CraneCNTR.PieceGrabbedFromDB = Y)); # 25 +#AG(DB.DBeltCNTR.PieceOutDB = Y -> +# A(DB.DBeltCNTR.PieceOutDB = Y U TC.CraneCNTR.PieceGrabbedFromDB = Y)); # 26 +# +# Correctness of the communication protocol ARM -> DB +# +#AG(DB.DBeltCNTR.DBReady = Y -> AF(AR.ACNTR.PieceOutArm = Y)); # 27 +#AG(DB.DBeltCNTR.DBReady = Y -> +# A(DB.DBeltCNTR.DBReady = Y U AR.ACNTR.PieceOutArm = Y)); # 28 +# +# Correctness of the communication protocol RT -> Arm +# +#AG(RT.RTableCNTR.RTOutReady = Y -> +# (AF(AR.ACNTR.PieceGrabbedFromRT = Y))); # 29 +#AG(RT.RTableCNTR.RTOutReady = Y -> +# A(RT.RTableCNTR.RTOutReady = Y U AR.ACNTR.PieceGrabbedFromRT = Y)); # 30 +# +# Correctness of the communication protocol FB -> Crane +# +#AG(FB.FBeltCNTR.FBReady = Y -> AF(TC.CraneCNTR.PieceReleasedOnFB = Y)); # 31 +#AG(FB.FBeltCNTR.FBReady = Y -> +# A(FB.FBeltCNTR.FBReady = Y U TC.CraneCNTR.PieceReleasedOnFB = Y)); # 32 +# +# Correctness of the communication protocol FB -> RT (2358 seconds) +# +#AG(FB.FBeltCNTR.PieceOutFB = Y -> +# AF(RT.RTableCNTR.PieceGrabbedFromFB = Y)); # 33 +#AG(FB.FBeltCNTR.PieceOutFB = Y -> +# A(FB.FBeltCNTR.PieceOutFB = Y U RT.RTableCNTR.PieceGrabbedFromFB = Y)); # 34 +# +# Correctness of the communication protocol ARM -> LOAD PRESS +# +#AG( PR.PrCNTR.PressReadyToBeLoaded = Y -> +# AF(AR.ACNTR.ArmLoadedPress = Y)); # 35 +#AG(PR.PrCNTR.PressReadyToBeLoaded = Y -> +# A(PR.PrCNTR.PressReadyToBeLoaded = Y U AR.ACNTR.ArmLoadedPress = Y)); # 36 +# +# Correctness of the communication protocol ARM -> UNLOAD PRESS +# +#AG( PR.PrCNTR.PressReadyToBeUnLoaded = Y -> +# AF(AR.ACNTR.ArmUnLoadedPress = Y)); # 37 +#AG(PR.PrCNTR.PressReadyToBeUnLoaded = Y -> +# A(PR.PrCNTR.PressReadyToBeUnLoaded = Y U +# AR.ACNTR.ArmUnLoadedPress = Y)); # 38 Index: vis_dev/vis-2.1/examples/production_cell/prodcell.mv =================================================================== --- vis_dev/vis-2.1/examples/production_cell/prodcell.mv (revision 11) +++ vis_dev/vis-2.1/examples/production_cell/prodcell.mv (revision 11) @@ -0,0 +1,8648 @@ +# vl2mv model.vl +# version: 0.2 +# date: 14:05:28 12/30/96 (MST) +.model ProductionCell +# I/O ports +.mv PressReadyToBeLoaded 2 Y N +.mv ArmLoadedPress 2 Y N +.mv PressReadyToBeUnLoaded 2 Y N +.mv ArmUnLoadedPress 2 Y N +.mv PieceReleasedOnFB 2 Y N +.mv FBReady 2 Y N +.mv PieceGrabbedFromDB 2 Y N +.mv RTOutReady 2 Y N +.mv PieceGrabbedFromFB 2 Y N +.mv PieceOutFB 2 Y N +.mv PieceOutArm 2 Y N +.mv PieceGrabbedFromRT 2 Y N +.mv PieceOutDB 2 Y N +.mv DBReady 2 Y N +.subckt TravellingCraneSet TC PieceOutDB=PieceOutDB FBReady=FBReady PieceGrabbedFromDB=PieceGrabbedFromDB PieceReleasedOnFB=PieceReleasedOnFB +.subckt DepositBeltSet DB PieceGrabbedFromDB=PieceGrabbedFromDB PieceOutArm=PieceOutArm PieceOutDB=PieceOutDB DBReady=DBReady +.subckt FeedBeltSet FB PieceGrabbedFromFB=PieceGrabbedFromFB PieceReleasedOnFB=PieceReleasedOnFB FBReady=FBReady PieceOutFB=PieceOutFB +.subckt RotaryTableSet RT PieceOutFB=PieceOutFB PieceGrabbedFromRT=PieceGrabbedFromRT PieceGrabbedFromFB=PieceGrabbedFromFB RTOutReady=RTOutReady +.subckt PressSet PR ArmLoadedPress=ArmLoadedPress ArmUnLoadedPress=ArmUnLoadedPress PressReadyToBeLoaded=PressReadyToBeLoaded PressReadyToBeUnLoaded=PressReadyToBeUnLoaded +.subckt ArmSet AR DBReady=DBReady PressReadyToBeUnLoaded=PressReadyToBeUnLoaded PressReadyToBeLoaded=PressReadyToBeLoaded RTOutReady=RTOutReady PieceOutArm=PieceOutArm ArmUnLoadedPress=ArmUnLoadedPress ArmLoadedPress=ArmLoadedPress PieceGrabbedFromRT=PieceGrabbedFromRT +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model TravellingCraneSet +# I/O ports +.outputs PieceReleasedOnFB +.outputs PieceGrabbedFromDB +.inputs FBReady +.inputs PieceOutDB +.mv VerticalMove 3 GoUp GoDown Stop +.mv VerticalPos 3 UpMost DBHight FBHight +.mv PieceReleasedOnFB 2 Y N +.mv PieceGrabbedFromDB 2 Y N +.mv FBReady 2 Y N +.mv CraneOnTheRight 2 Y N +.mv CraneOnTheLeft 2 Y N +.mv HorizontalMove 3 GoLeft GoRight Stop +.mv PieceOutDB 2 Y N +.subckt TravellingCrane Crane HorizontalMove=HorizontalMove VerticalMove=VerticalMove CraneOnTheLeft=CraneOnTheLeft CraneOnTheRight=CraneOnTheRight VerticalPos=VerticalPos +.subckt TravellingCraneCNTR CraneCNTR FBReady=FBReady PieceOutDB=PieceOutDB CraneOnTheLeft=CraneOnTheLeft CraneOnTheRight=CraneOnTheRight VerticalPos=VerticalPos HorizontalMove=HorizontalMove VerticalMove=VerticalMove PieceReleasedOnFB=PieceReleasedOnFB PieceGrabbedFromDB=PieceGrabbedFromDB +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model DepositBeltSet +# I/O ports +.inputs PieceGrabbedFromDB +.outputs PieceOutDB +.inputs PieceOutArm +.outputs DBReady +.mv PieceGrabbedFromDB 2 Y N +.mv DBelt3 2 E F +.mv DBelt2 2 E F +.mv DBelt1 2 E F +.mv DBelt0 2 E F +.mv PieceOutDB 2 Y N +.mv PieceOutArm 2 Y N +.mv DBMotorSwitch 2 on off +.mv DBReady 2 Y N +.subckt DepositBelt DBelt DBMotorSwitch=DBMotorSwitch PieceOutArm=PieceOutArm PieceGrabbedFromDB=PieceGrabbedFromDB DBReady=DBReady DBelt0=DBelt0 DBelt1=DBelt1 DBelt2=DBelt2 DBelt3=DBelt3 +.subckt DepositBeltCNTR DBeltCNTR DBelt0=DBelt0 DBelt1=DBelt1 DBelt2=DBelt2 DBelt3=DBelt3 PieceGrabbedFromDB=PieceGrabbedFromDB PieceOutArm=PieceOutArm DBMotorSwitch=DBMotorSwitch DBReady=DBReady PieceOutDB=PieceOutDB +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model FeedBeltSet +# I/O ports +.outputs FBReady +.inputs PieceReleasedOnFB +.outputs PieceOutFB +.inputs PieceGrabbedFromFB +.mv FBelt3 2 E F +.mv FBelt2 2 E F +.mv FBReady 2 Y N +.mv PieceReleasedOnFB 2 Y N +.mv FBelt1 2 E F +.mv FBelt0 2 E F +.mv FBMotorSwitch 2 on off +.mv PieceOutFB 2 Y N +.mv PieceGrabbedFromFB 2 Y N +.subckt FeedBelt FBelt FBMotorSwitch=FBMotorSwitch PieceReleasedOnFB=PieceReleasedOnFB PieceGrabbedFromFB=PieceGrabbedFromFB FBReady=FBReady FBelt0=FBelt0 FBelt1=FBelt1 FBelt2=FBelt2 FBelt3=FBelt3 +.subckt FeedBeltCNTR FBeltCNTR FBelt0=FBelt0 FBelt1=FBelt1 FBelt2=FBelt2 FBelt3=FBelt3 PieceGrabbedFromFB=PieceGrabbedFromFB PieceReleasedOnFB=PieceReleasedOnFB FBMotorSwitch=FBMotorSwitch FBReady=FBReady PieceOutFB=PieceOutFB +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model RotaryTableSet +# I/O ports +.outputs RTOutReady +.outputs PieceGrabbedFromFB +.inputs PieceOutFB +.inputs PieceGrabbedFromRT +.mv RTOnTop 2 Y N +.mv RTOnArm 2 Y N +.mv RTOnFB 2 Y N +.mv RTOutReady 2 Y N +.mv RTOnBottom 2 Y N +.mv RTVerticalMotor 3 GoUp GoDown Stop +.mv RTRotaryMotor 3 CWise Stop CCWise +.mv PieceGrabbedFromFB 2 Y N +.mv PieceOutFB 2 Y N +.mv PieceGrabbedFromRT 2 Y N +.subckt RotaryTable RTable RTRotaryMotor=RTRotaryMotor RTVerticalMotor=RTVerticalMotor RTOnFB=RTOnFB RTOnArm=RTOnArm RTOnTop=RTOnTop RTOnBottom=RTOnBottom +.subckt RotaryTableCNTR RTableCNTR PieceOutFB=PieceOutFB PieceGrabbedFromRT=PieceGrabbedFromRT RTOnFB=RTOnFB RTOnArm=RTOnArm RTOnTop=RTOnTop RTOnBottom=RTOnBottom RTRotaryMotor=RTRotaryMotor RTVerticalMotor=RTVerticalMotor PieceGrabbedFromFB=PieceGrabbedFromFB RTOutReady=RTOutReady +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model PressSet +# I/O ports +.outputs PressReadyToBeUnLoaded +.outputs PressReadyToBeLoaded +.inputs ArmLoadedPress +.inputs ArmUnLoadedPress +.mv PressReadyToBeUnLoaded 2 Y N +.mv PressReadyToBeLoaded 2 Y N +.mv ArmLoadedPress 2 Y N +.mv ArmUnLoadedPress 2 Y N +.mv PressMotor 3 GoUp GoDown Stop +.mv PressPosition 3 Top Mid Bot +.subckt Press Pr PressMotor=PressMotor PressPosition=PressPosition +.subckt PressCNTR PrCNTR PressPosition=PressPosition ArmLoadedPress=ArmLoadedPress ArmUnLoadedPress=ArmUnLoadedPress PressMotor=PressMotor PressReadyToBeLoaded=PressReadyToBeLoaded PressReadyToBeUnLoaded=PressReadyToBeUnLoaded +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model ArmSet +# I/O ports +.outputs ArmLoadedPress +.inputs PressReadyToBeLoaded +.inputs PressReadyToBeUnLoaded +.outputs ArmUnLoadedPress +.inputs RTOutReady +.outputs PieceGrabbedFromRT +.outputs PieceOutArm +.inputs DBReady +.mv RAExtendUnLoadArm 3 Extend Retract Stop +.mv RAArmOverDB 2 Y N +.mv RAArmOverLoadedPress 2 Y N +.mv RAUnLoadArmExtended 2 Y N +.mv ArmLoadedPress 2 Y N +.mv PressReadyToBeLoaded 2 Y N +.mv PressReadyToBeUnLoaded 2 Y N +.mv RARotaryMotor 3 CWise Stop CCWise +.mv ArmUnLoadedPress 2 Y N +.mv RAArmOverUnLoadedPress 2 Y N +.mv RALoadArmExtended 2 Y N +.mv RTOutReady 2 Y N +.mv RAExtendLoadArm 3 Extend Retract Stop +.mv RAArmOverRT 2 Y N +.mv RALoadArmRetracted 2 Y N +.mv PieceGrabbedFromRT 2 Y N +.mv PieceOutArm 2 Y N +.mv RAUnLoadArmRetracted 2 Y N +.mv DBReady 2 Y N +.subckt RobotArm Arm RAExtendLoadArm=RAExtendLoadArm RAExtendUnLoadArm=RAExtendUnLoadArm RARotaryMotor=RARotaryMotor RALoadArmExtended=RALoadArmExtended RALoadArmRetracted=RALoadArmRetracted RAUnLoadArmExtended=RAUnLoadArmExtended RAUnLoadArmRetracted=RAUnLoadArmRetracted RAArmOverRT=RAArmOverRT RAArmOverUnLoadedPress=RAArmOverUnLoadedPress RAArmOverLoadedPress=RAArmOverLoadedPress RAArmOverDB=RAArmOverDB +.subckt RobotArmCNTR ACNTR RALoadArmExtended=RALoadArmExtended RALoadArmRetracted=RALoadArmRetracted RAUnLoadArmExtended=RAUnLoadArmExtended RAUnLoadArmRetracted=RAUnLoadArmRetracted RAArmOverRT=RAArmOverRT RAArmOverUnLoadedPress=RAArmOverUnLoadedPress RAArmOverLoadedPress=RAArmOverLoadedPress RAArmOverDB=RAArmOverDB DBReady=DBReady PressReadyToBeUnLoaded=PressReadyToBeUnLoaded PressReadyToBeLoaded=PressReadyToBeLoaded RTOutReady=RTOutReady RAExtendLoadArm=RAExtendLoadArm RAExtendUnLoadArm=RAExtendUnLoadArm RARotaryMotor=RARotaryMotor PieceOutArm=PieceOutArm ArmUnLoadedPress=ArmUnLoadedPress ArmLoadedPress=ArmLoadedPress PieceGrabbedFromRT=PieceGrabbedFromRT +# conflict arbitrators +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model TravellingCrane +# I/O ports +.inputs VerticalMove +.outputs VerticalPos +.outputs CraneOnTheRight +.outputs CraneOnTheLeft +.inputs HorizontalMove +.mv VerticalMove 3 GoUp GoDown Stop +.mv VerticalPos 3 UpMost DBHight FBHight +.mv CraneOnTheRight 2 Y N +.mv CraneOnTheLeft 2 Y N +.mv HorizontalMove 3 GoLeft GoRight Stop +.mv HorizontalPos 3 OverFB Middle OverDB +# assign CraneOnTheLeft = (HorizontalPos == OverFB ) ? 0 : 1 +.mv CraneOnTheLeft$raw_n0 2 Y N +.mv _n2 3 OverFB Middle OverDB +.names _n2 +OverFB +# HorizontalPos == 0 +.names HorizontalPos _n2 _n1 +.def 0 +- =HorizontalPos 1 +.mv _n3 2 Y N +.names _n3 +Y +.mv _n4 2 Y N +.names _n4 +N +# (HorizontalPos == 0) ? 0 : 1 +.mv _n5 2 Y N +.names _n3 _n4 _n1 _n5 +- - 0 =_n4 +- - 1 =_n3 +.names _n5 CraneOnTheLeft$raw_n0 +- =_n5 +# assign CraneOnTheRight = (HorizontalPos == OverDB ) ? 0 : 1 +.mv CraneOnTheRight$raw_n6 2 Y N +.mv _n8 3 OverFB Middle OverDB +.names _n8 +OverDB +# HorizontalPos == 2 +.names HorizontalPos _n8 _n7 +.def 0 +- =HorizontalPos 1 +.mv _n9 2 Y N +.names _n9 +Y +.mv _na 2 Y N +.names _na +N +# (HorizontalPos == 2) ? 0 : 1 +.mv _nb 2 Y N +.names _n9 _na _n7 _nb +- - 0 =_na +- - 1 =_n9 +.names _nb CraneOnTheRight$raw_n6 +- =_nb +# HorizontalPos = $NDset ( 1,2,0 ) +.mv HorizontalPos$raw_nc 3 OverFB Middle OverDB +.mv HorizontalPos$raw_nc$initial$_nd 3 OverFB Middle OverDB +.names HorizontalPos$raw_nc$initial$_nd +Middle +OverDB +OverFB +.names HorizontalPos$raw_nc$initial$_nd HorizontalPos$raw_nc +- =HorizontalPos$raw_nc$initial$_nd +# VerticalPos = 0 +.mv VerticalPos$raw_ne 3 UpMost DBHight FBHight +.names VerticalPos$raw_ne +UpMost +# non-blocking assignments for initial +.mv _n10 3 GoLeft GoRight Stop +.names _n10 +GoLeft +# HorizontalMove == 0 +.names HorizontalMove _n10 _nf +.def 0 +- =HorizontalMove 1 +.names _nf _n11 +- =_nf +.mv _n13 3 OverFB Middle OverDB +.names _n13 +Middle +# HorizontalPos == 1 +.names HorizontalPos _n13 _n12 +.def 0 +- =HorizontalPos 1 +.names _n12 _n14 +- =_n12 +# HorizontalPos = 0 +.mv HorizontalPos$_n12_n15$true 3 OverFB Middle OverDB +.names HorizontalPos$_n12_n15$true +OverFB +.mv _n17 3 OverFB Middle OverDB +.names _n17 +OverDB +# HorizontalPos == 2 +.names HorizontalPos _n17 _n16 +.def 0 +- =HorizontalPos 1 +.names _n16 _n18 +- =_n16 +# HorizontalPos = 1 +.mv HorizontalPos$_n16_n19$true 3 OverFB Middle OverDB +.names HorizontalPos$_n16_n19$true +Middle +# if/else (HorizontalPos == 2) +.mv HorizontalPos$_n16$raw_n1c 3 OverFB Middle OverDB +.names HorizontalPos$_n16_n19$true HorizontalPos _n16 HorizontalPos$_n16$raw_n1c +- - 0 =HorizontalPos +- - 1 =HorizontalPos$_n16_n19$true +# if/else (HorizontalPos == 1) +.mv HorizontalPos$_n12$raw_n1e 3 OverFB Middle OverDB +.names HorizontalPos$_n12_n15$true HorizontalPos$_n16$raw_n1c _n12 HorizontalPos$_n12$raw_n1e +- - 0 =HorizontalPos$_n16$raw_n1c +- - 1 =HorizontalPos$_n12_n15$true +# if/else (HorizontalMove == 0) +.mv HorizontalPos$_nf$raw_n23 3 OverFB Middle OverDB +.names HorizontalPos$_n12$raw_n1e HorizontalPos _nf HorizontalPos$_nf$raw_n23 +- - 0 =HorizontalPos +- - 1 =HorizontalPos$_n12$raw_n1e +.mv _n25 3 GoLeft GoRight Stop +.names _n25 +GoRight +# HorizontalMove == 1 +.names HorizontalMove _n25 _n24 +.def 0 +- =HorizontalMove 1 +.names _n24 _n26 +- =_n24 +.mv _n28 3 OverFB Middle OverDB +.names _n28 +Middle +# HorizontalPos == 1 +.names HorizontalPos$_nf$raw_n23 _n28 _n27 +.def 0 +- =HorizontalPos$_nf$raw_n23 1 +.names _n27 _n29 +- =_n27 +# HorizontalPos = 2 +.mv HorizontalPos$_n27_n2a$true 3 OverFB Middle OverDB +.names HorizontalPos$_n27_n2a$true +OverDB +.mv _n2c 3 OverFB Middle OverDB +.names _n2c +OverFB +# HorizontalPos == 0 +.names HorizontalPos$_nf$raw_n23 _n2c _n2b +.def 0 +- =HorizontalPos$_nf$raw_n23 1 +.names _n2b _n2d +- =_n2b +# HorizontalPos = 1 +.mv HorizontalPos$_n2b_n2e$true 3 OverFB Middle OverDB +.names HorizontalPos$_n2b_n2e$true +Middle +# if/else (HorizontalPos == 0) +.mv HorizontalPos$_n2b$raw_n2f 3 OverFB Middle OverDB +.names HorizontalPos$_n2b_n2e$true HorizontalPos$_nf$raw_n23 _n2b HorizontalPos$_n2b$raw_n2f +- - 0 =HorizontalPos$_nf$raw_n23 +- - 1 =HorizontalPos$_n2b_n2e$true +# if/else (HorizontalPos == 1) +.mv HorizontalPos$_n27$raw_n33 3 OverFB Middle OverDB +.names HorizontalPos$_n27_n2a$true HorizontalPos$_n2b$raw_n2f _n27 HorizontalPos$_n27$raw_n33 +- - 0 =HorizontalPos$_n2b$raw_n2f +- - 1 =HorizontalPos$_n27_n2a$true +# if/else (HorizontalMove == 1) +.mv HorizontalPos$_n24$raw_n37 3 OverFB Middle OverDB +.names HorizontalPos$_n27$raw_n33 HorizontalPos$_nf$raw_n23 _n24 HorizontalPos$_n24$raw_n37 +- - 0 =HorizontalPos$_nf$raw_n23 +- - 1 =HorizontalPos$_n27$raw_n33 +.mv _n3c 3 GoUp GoDown Stop +.names _n3c +GoUp +# VerticalMove == 0 +.names VerticalMove _n3c _n3b +.def 0 +- =VerticalMove 1 +.names _n3b _n3d +- =_n3b +.mv _n3f 3 UpMost DBHight FBHight +.names _n3f +DBHight +# VerticalPos == 1 +.names VerticalPos _n3f _n3e +.def 0 +- =VerticalPos 1 +.names _n3e _n40 +- =_n3e +# VerticalPos = 0 +.mv VerticalPos$_n3e_n41$true 3 UpMost DBHight FBHight +.names VerticalPos$_n3e_n41$true +UpMost +.mv _n43 3 UpMost DBHight FBHight +.names _n43 +FBHight +# VerticalPos == 2 +.names VerticalPos _n43 _n42 +.def 0 +- =VerticalPos 1 +.names _n42 _n44 +- =_n42 +# VerticalPos = 1 +.mv VerticalPos$_n42_n45$true 3 UpMost DBHight FBHight +.names VerticalPos$_n42_n45$true +DBHight +# if/else (VerticalPos == 2) +.mv VerticalPos$_n42$raw_n4a 3 UpMost DBHight FBHight +.names VerticalPos$_n42_n45$true VerticalPos _n42 VerticalPos$_n42$raw_n4a +- - 0 =VerticalPos +- - 1 =VerticalPos$_n42_n45$true +# if/else (VerticalPos == 1) +.mv VerticalPos$_n3e$raw_n4f 3 UpMost DBHight FBHight +.names VerticalPos$_n3e_n41$true VerticalPos$_n42$raw_n4a _n3e VerticalPos$_n3e$raw_n4f +- - 0 =VerticalPos$_n42$raw_n4a +- - 1 =VerticalPos$_n3e_n41$true +# if/else (VerticalMove == 0) +.mv VerticalPos$_n3b$raw_n59 3 UpMost DBHight FBHight +.names VerticalPos$_n3e$raw_n4f VerticalPos _n3b VerticalPos$_n3b$raw_n59 +- - 0 =VerticalPos +- - 1 =VerticalPos$_n3e$raw_n4f +.mv _n5d 3 GoUp GoDown Stop +.names _n5d +GoDown +# VerticalMove == 1 +.names VerticalMove _n5d _n5c +.def 0 +- =VerticalMove 1 +.names _n5c _n5e +- =_n5c +.mv _n60 3 UpMost DBHight FBHight +.names _n60 +UpMost +# VerticalPos == 0 +.names VerticalPos$_n3b$raw_n59 _n60 _n5f +.def 0 +- =VerticalPos$_n3b$raw_n59 1 +.names _n5f _n61 +- =_n5f +# VerticalPos = 1 +.mv VerticalPos$_n5f_n62$true 3 UpMost DBHight FBHight +.names VerticalPos$_n5f_n62$true +DBHight +.mv _n64 3 UpMost DBHight FBHight +.names _n64 +DBHight +# VerticalPos == 1 +.names VerticalPos$_n3b$raw_n59 _n64 _n63 +.def 0 +- =VerticalPos$_n3b$raw_n59 1 +.names _n63 _n65 +- =_n63 +# VerticalPos = 2 +.mv VerticalPos$_n63_n66$true 3 UpMost DBHight FBHight +.names VerticalPos$_n63_n66$true +FBHight +# if/else (VerticalPos == 1) +.mv VerticalPos$_n63$raw_n67 3 UpMost DBHight FBHight +.names VerticalPos$_n63_n66$true VerticalPos$_n3b$raw_n59 _n63 VerticalPos$_n63$raw_n67 +- - 0 =VerticalPos$_n3b$raw_n59 +- - 1 =VerticalPos$_n63_n66$true +# if/else (VerticalPos == 0) +.mv VerticalPos$_n5f$raw_n6f 3 UpMost DBHight FBHight +.names VerticalPos$_n5f_n62$true VerticalPos$_n63$raw_n67 _n5f VerticalPos$_n5f$raw_n6f +- - 0 =VerticalPos$_n63$raw_n67 +- - 1 =VerticalPos$_n5f_n62$true +# if/else (VerticalMove == 1) +.mv VerticalPos$_n5c$raw_n77 3 UpMost DBHight FBHight +.names VerticalPos$_n5f$raw_n6f VerticalPos$_n3b$raw_n59 _n5c VerticalPos$_n5c$raw_n77 +- - 0 =VerticalPos$_n3b$raw_n59 +- - 1 =VerticalPos$_n5f$raw_n6f +# conflict arbitrators +.names _n3d _n40 _n44 _n5e _n61 _n65 _n7f +.def 0 + 1 1 - - - - 1 + 1 0 1 - - - 1 + - - - 1 1 - 1 + - - - 1 0 1 1 +.mv _n80 3 UpMost DBHight FBHight +.names _n7f VerticalPos$_n5c$raw_n77 VerticalPos _n80 +1 - - =VerticalPos$_n5c$raw_n77 +0 - - =VerticalPos +.names CraneOnTheRight$raw_n6 CraneOnTheRight +- =CraneOnTheRight$raw_n6 +.names CraneOnTheLeft$raw_n0 CraneOnTheLeft +- =CraneOnTheLeft$raw_n0 +.names _n11 _n14 _n18 _n26 _n29 _n2d _n87 +.def 0 + 1 1 - - - - 1 + 1 0 1 - - - 1 + - - - 1 1 - 1 + - - - 1 0 1 1 +.mv _n88 3 OverFB Middle OverDB +.names _n87 HorizontalPos$_n24$raw_n37 HorizontalPos _n88 +1 - - =HorizontalPos$_n24$raw_n37 +0 - - =HorizontalPos +# non-blocking assignments +# latches +.r VerticalPos$raw_ne VerticalPos +- =VerticalPos$raw_ne +.latch _n80 VerticalPos +.r HorizontalPos$raw_nc HorizontalPos +- =HorizontalPos$raw_nc +.latch _n88 HorizontalPos +# quasi-continuous assignment +.end + + +.model TravellingCraneCNTR +# I/O ports +.outputs VerticalMove +.outputs PieceGrabbedFromDB +.outputs PieceReleasedOnFB +.inputs VerticalPos +.inputs FBReady +.inputs CraneOnTheRight +.inputs CraneOnTheLeft +.outputs HorizontalMove +.inputs PieceOutDB +.mv VerticalMove 3 GoUp GoDown Stop +.mv PieceGrabbedFromDB 2 Y N +.mv PieceReleasedOnFB 2 Y N +.mv VerticalPos 3 UpMost DBHight FBHight +.mv FBReady 2 Y N +.mv CraneOnTheRight 2 Y N +.mv CraneOnTheLeft 2 Y N +.mv HorizontalMove 3 GoLeft GoRight Stop +.mv PieceOutDB 2 Y N +.mv Grip 2 Grab Free +# HorizontalMove = 2 +.mv HorizontalMove$raw_n8f 3 GoLeft GoRight Stop +.names HorizontalMove$raw_n8f +Stop +# VerticalMove = 2 +.mv VerticalMove$raw_n90 3 GoUp GoDown Stop +.names VerticalMove$raw_n90 +Stop +# Grip = 1 +.mv Grip$raw_n91 2 Grab Free +.names Grip$raw_n91 +Free +# PieceReleasedOnFB = 1 +.mv PieceReleasedOnFB$raw_n92 2 Y N +.names PieceReleasedOnFB$raw_n92 +N +# PieceGrabbedFromDB = 1 +.mv PieceGrabbedFromDB$raw_n93 2 Y N +.names PieceGrabbedFromDB$raw_n93 +N +# non-blocking assignments for initial +.mv _n96 2 Grab Free +.names _n96 +Grab +.names Grip _n96 _n95 +.def 0 +- =Grip 1 +.names _n95 _n94 +1 1 +0 0 +.mv _n99 3 UpMost DBHight FBHight +.names _n99 +UpMost +.names VerticalPos _n99 _n98 +.def 0 +- =VerticalPos 1 +.names _n98 _n97 +1 1 +0 0 +# Grip = 0 +.mv Grip$_n97_n9a$true 2 Grab Free +.names Grip$_n97_n9a$true +Grab +.mv _n9c 2 Y N +.names _n9c +Y +# CraneOnTheLeft == 0 +.names CraneOnTheLeft _n9c _n9b +.def 0 +- =CraneOnTheLeft 1 +.names _n9b _n9d +- =_n9b +# HorizontalMove = 2 +.mv HorizontalMove$_n9b_n9e$true 3 GoLeft GoRight Stop +.names HorizontalMove$_n9b_n9e$true +Stop +# VerticalMove = 1 +.mv VerticalMove$_n9b_n9f$true 3 GoUp GoDown Stop +.names VerticalMove$_n9b_n9f$true +GoDown +.mv _na1 2 Y N +.names _na1 +N +# CraneOnTheRight == 1 +.names CraneOnTheRight _na1 _na0 +.def 0 +- =CraneOnTheRight 1 +.mv _na3 2 Y N +.names _na3 +N +# CraneOnTheLeft == 1 +.names CraneOnTheLeft _na3 _na2 +.def 0 +- =CraneOnTheLeft 1 +# CraneOnTheRight == 1 && CraneOnTheLeft == 1 +.names _na0 _na2 _na4 +.def 0 +1 1 1 +.names _na4 _na5 +- =_na4 +.mv _na7 3 GoLeft GoRight Stop +.names _na7 +GoLeft +# HorizontalMove == 0 +.names HorizontalMove _na7 _na6 +.def 0 +- =HorizontalMove 1 +.names _na6 _na8 +- =_na6 +# HorizontalMove = 2 +.mv HorizontalMove$_na6_na9$true 3 GoLeft GoRight Stop +.names HorizontalMove$_na6_na9$true +Stop +# VerticalMove = 1 +.mv VerticalMove$_na6_naa$true 3 GoUp GoDown Stop +.names VerticalMove$_na6_naa$true +GoDown +# HorizontalMove = 0 +.mv HorizontalMove$_na6_nab$false 3 GoLeft GoRight Stop +.names HorizontalMove$_na6_nab$false +GoLeft +# VerticalMove = 2 +.mv VerticalMove$_na6_nac$false 3 GoUp GoDown Stop +.names VerticalMove$_na6_nac$false +Stop +# if/else (HorizontalMove == 0) +.mv VerticalMove$_na6$raw_nb0 3 GoUp GoDown Stop +.names VerticalMove$_na6_naa$true VerticalMove$_na6_nac$false _na6 VerticalMove$_na6$raw_nb0 +- - 0 =VerticalMove$_na6_nac$false +- - 1 =VerticalMove$_na6_naa$true +.mv HorizontalMove$_na6$raw_nb1 3 GoLeft GoRight Stop +.names HorizontalMove$_na6_na9$true HorizontalMove$_na6_nab$false _na6 HorizontalMove$_na6$raw_nb1 +- - 0 =HorizontalMove$_na6_nab$false +- - 1 =HorizontalMove$_na6_na9$true +# HorizontalMove = 0 +.mv HorizontalMove$_na4_nb9$false 3 GoLeft GoRight Stop +.names HorizontalMove$_na4_nb9$false +GoLeft +# VerticalMove = 2 +.mv VerticalMove$_na4_nba$false 3 GoUp GoDown Stop +.names VerticalMove$_na4_nba$false +Stop +# if/else (CraneOnTheRight == 1 && CraneOnTheLeft == 1) +.mv VerticalMove$_na4$raw_nbe 3 GoUp GoDown Stop +.names VerticalMove$_na6$raw_nb0 VerticalMove$_na4_nba$false _na4 VerticalMove$_na4$raw_nbe +- - 0 =VerticalMove$_na4_nba$false +- - 1 =VerticalMove$_na6$raw_nb0 +.mv HorizontalMove$_na4$raw_nbf 3 GoLeft GoRight Stop +.names HorizontalMove$_na6$raw_nb1 HorizontalMove$_na4_nb9$false _na4 HorizontalMove$_na4$raw_nbf +- - 0 =HorizontalMove$_na4_nb9$false +- - 1 =HorizontalMove$_na6$raw_nb1 +# if/else (CraneOnTheLeft == 0) +.mv VerticalMove$_n9b$raw_nca 3 GoUp GoDown Stop +.names VerticalMove$_n9b_n9f$true VerticalMove$_na4$raw_nbe _n9b VerticalMove$_n9b$raw_nca +- - 0 =VerticalMove$_na4$raw_nbe +- - 1 =VerticalMove$_n9b_n9f$true +.mv HorizontalMove$_n9b$raw_ncb 3 GoLeft GoRight Stop +.names HorizontalMove$_n9b_n9e$true HorizontalMove$_na4$raw_nbf _n9b HorizontalMove$_n9b$raw_ncb +- - 0 =HorizontalMove$_na4$raw_nbf +- - 1 =HorizontalMove$_n9b_n9e$true +.mv _nd5 3 UpMost DBHight FBHight +.names _nd5 +DBHight +.names VerticalPos _nd5 _nd4 +.def 0 +- =VerticalPos 1 +.names _nd4 _nd3 +1 1 +0 0 +.mv _nd7 2 Y N +.names _nd7 +Y +# CraneOnTheLeft == 0 +.names CraneOnTheLeft _nd7 _nd6 +.def 0 +- =CraneOnTheLeft 1 +.names _nd6 _nd8 +- =_nd6 +.mv _nda 3 GoUp GoDown Stop +.names _nda +GoDown +# VerticalMove == 1 +.names VerticalMove _nda _nd9 +.def 0 +- =VerticalMove 1 +.names _nd9 _ndb +- =_nd9 +.mv _ndd 2 Y N +.names _ndd +Y +# FBReady == 0 +.names FBReady _ndd _ndc +.def 0 +- =FBReady 1 +.names _ndc _nde +- =_ndc +# Grip = 1 +.mv Grip$_ndc_ndf$true 2 Grab Free +.names Grip$_ndc_ndf$true +Free +# HorizontalMove = 2 +.mv HorizontalMove$_ndc_ne0$true 3 GoLeft GoRight Stop +.names HorizontalMove$_ndc_ne0$true +Stop +# VerticalMove = 0 +.mv VerticalMove$_ndc_ne1$true 3 GoUp GoDown Stop +.names VerticalMove$_ndc_ne1$true +GoUp +# PieceReleasedOnFB = 0 +.mv PieceReleasedOnFB$_ndc_ne2$true 2 Y N +.names PieceReleasedOnFB$_ndc_ne2$true +Y +# Grip = 0 +.mv Grip$_ndc_ne3$false 2 Grab Free +.names Grip$_ndc_ne3$false +Grab +# HorizontalMove = 2 +.mv HorizontalMove$_ndc_ne4$false 3 GoLeft GoRight Stop +.names HorizontalMove$_ndc_ne4$false +Stop +# VerticalMove = 2 +.mv VerticalMove$_ndc_ne5$false 3 GoUp GoDown Stop +.names VerticalMove$_ndc_ne5$false +Stop +# if/else (FBReady == 0) +.mv VerticalMove$_ndc$raw_nea 3 GoUp GoDown Stop +.names VerticalMove$_ndc_ne1$true VerticalMove$_ndc_ne5$false _ndc VerticalMove$_ndc$raw_nea +- - 0 =VerticalMove$_ndc_ne5$false +- - 1 =VerticalMove$_ndc_ne1$true +.mv HorizontalMove$_ndc$raw_nec 3 GoLeft GoRight Stop +.names HorizontalMove$_ndc_ne0$true HorizontalMove$_ndc_ne4$false _ndc HorizontalMove$_ndc$raw_nec +- - 0 =HorizontalMove$_ndc_ne4$false +- - 1 =HorizontalMove$_ndc_ne0$true +.mv Grip$_ndc$raw_ned 2 Grab Free +.names Grip$_ndc_ndf$true Grip$_ndc_ne3$false _ndc Grip$_ndc$raw_ned +- - 0 =Grip$_ndc_ne3$false +- - 1 =Grip$_ndc_ndf$true +.mv PieceReleasedOnFB$_ndc$raw_nef 2 Y N +.names PieceReleasedOnFB$_ndc_ne2$true PieceReleasedOnFB _ndc PieceReleasedOnFB$_ndc$raw_nef +- - 0 =PieceReleasedOnFB +- - 1 =PieceReleasedOnFB$_ndc_ne2$true +# Grip = 0 +.mv Grip$_nd9_nf5$false 2 Grab Free +.names Grip$_nd9_nf5$false +Grab +# HorizontalMove = 2 +.mv HorizontalMove$_nd9_nf6$false 3 GoLeft GoRight Stop +.names HorizontalMove$_nd9_nf6$false +Stop +# VerticalMove = 1 +.mv VerticalMove$_nd9_nf7$false 3 GoUp GoDown Stop +.names VerticalMove$_nd9_nf7$false +GoDown +# if/else (VerticalMove == 1) +.mv VerticalMove$_nd9$raw_nfc 3 GoUp GoDown Stop +.names VerticalMove$_ndc$raw_nea VerticalMove$_nd9_nf7$false _nd9 VerticalMove$_nd9$raw_nfc +- - 0 =VerticalMove$_nd9_nf7$false +- - 1 =VerticalMove$_ndc$raw_nea +.mv HorizontalMove$_nd9$raw_nfe 3 GoLeft GoRight Stop +.names HorizontalMove$_ndc$raw_nec HorizontalMove$_nd9_nf6$false _nd9 HorizontalMove$_nd9$raw_nfe +- - 0 =HorizontalMove$_nd9_nf6$false +- - 1 =HorizontalMove$_ndc$raw_nec +.mv Grip$_nd9$raw_nff 2 Grab Free +.names Grip$_ndc$raw_ned Grip$_nd9_nf5$false _nd9 Grip$_nd9$raw_nff +- - 0 =Grip$_nd9_nf5$false +- - 1 =Grip$_ndc$raw_ned +.mv PieceReleasedOnFB$_nd9$raw_n101 2 Y N +.names PieceReleasedOnFB$_ndc$raw_nef PieceReleasedOnFB _nd9 PieceReleasedOnFB$_nd9$raw_n101 +- - 0 =PieceReleasedOnFB +- - 1 =PieceReleasedOnFB$_ndc$raw_nef +# if/else (CraneOnTheLeft == 0) +.mv VerticalMove$_nd6$raw_n10f 3 GoUp GoDown Stop +.names VerticalMove$_nd9$raw_nfc VerticalMove _nd6 VerticalMove$_nd6$raw_n10f +- - 0 =VerticalMove +- - 1 =VerticalMove$_nd9$raw_nfc +.mv PieceReleasedOnFB$_nd6$raw_n110 2 Y N +.names PieceReleasedOnFB$_nd9$raw_n101 PieceReleasedOnFB _nd6 PieceReleasedOnFB$_nd6$raw_n110 +- - 0 =PieceReleasedOnFB +- - 1 =PieceReleasedOnFB$_nd9$raw_n101 +.mv HorizontalMove$_nd6$raw_n111 3 GoLeft GoRight Stop +.names HorizontalMove$_nd9$raw_nfe HorizontalMove _nd6 HorizontalMove$_nd6$raw_n111 +- - 0 =HorizontalMove +- - 1 =HorizontalMove$_nd9$raw_nfe +.mv Grip$_nd6$raw_n112 2 Grab Free +.names Grip$_nd9$raw_nff Grip _nd6 Grip$_nd6$raw_n112 +- - 0 =Grip +- - 1 =Grip$_nd9$raw_nff +.mv _n114 2 Y N +.names _n114 +Y +# CraneOnTheRight == 0 +.names CraneOnTheRight _n114 _n113 +.def 0 +- =CraneOnTheRight 1 +.names _n113 _n115 +- =_n113 +# Grip = 0 +.mv Grip$_n113_n116$true 2 Grab Free +.names Grip$_n113_n116$true +Grab +.mv _n118 3 GoUp GoDown Stop +.names _n118 +GoUp +# VerticalMove == 0 +.names VerticalMove$_nd6$raw_n10f _n118 _n117 +.def 0 +- =VerticalMove$_nd6$raw_n10f 1 +.names _n117 _n119 +- =_n117 +# HorizontalMove = 0 +.mv HorizontalMove$_n117_n11a$true 3 GoLeft GoRight Stop +.names HorizontalMove$_n117_n11a$true +GoLeft +# VerticalMove = 2 +.mv VerticalMove$_n117_n11b$true 3 GoUp GoDown Stop +.names VerticalMove$_n117_n11b$true +Stop +# HorizontalMove = 2 +.mv HorizontalMove$_n117_n11c$false 3 GoLeft GoRight Stop +.names HorizontalMove$_n117_n11c$false +Stop +# VerticalMove = 0 +.mv VerticalMove$_n117_n11d$false 3 GoUp GoDown Stop +.names VerticalMove$_n117_n11d$false +GoUp +# if/else (VerticalMove == 0) +.mv VerticalMove$_n117$raw_n11e 3 GoUp GoDown Stop +.names VerticalMove$_n117_n11b$true VerticalMove$_n117_n11d$false _n117 VerticalMove$_n117$raw_n11e +- - 0 =VerticalMove$_n117_n11d$false +- - 1 =VerticalMove$_n117_n11b$true +.mv HorizontalMove$_n117$raw_n120 3 GoLeft GoRight Stop +.names HorizontalMove$_n117_n11a$true HorizontalMove$_n117_n11c$false _n117 HorizontalMove$_n117$raw_n120 +- - 0 =HorizontalMove$_n117_n11c$false +- - 1 =HorizontalMove$_n117_n11a$true +# if/else (CraneOnTheRight == 0) +.mv VerticalMove$_n113$raw_n12e 3 GoUp GoDown Stop +.names VerticalMove$_n117$raw_n11e VerticalMove$_nd6$raw_n10f _n113 VerticalMove$_n113$raw_n12e +- - 0 =VerticalMove$_nd6$raw_n10f +- - 1 =VerticalMove$_n117$raw_n11e +.mv HorizontalMove$_n113$raw_n130 3 GoLeft GoRight Stop +.names HorizontalMove$_n117$raw_n120 HorizontalMove$_nd6$raw_n111 _n113 HorizontalMove$_n113$raw_n130 +- - 0 =HorizontalMove$_nd6$raw_n111 +- - 1 =HorizontalMove$_n117$raw_n120 +.mv Grip$_n113$raw_n131 2 Grab Free +.names Grip$_n113_n116$true Grip$_nd6$raw_n112 _n113 Grip$_n113$raw_n131 +- - 0 =Grip$_nd6$raw_n112 +- - 1 =Grip$_n113_n116$true +.mv _n140 3 UpMost DBHight FBHight +.names _n140 +FBHight +.names VerticalPos _n140 _n13f +.def 0 +- =VerticalPos 1 +.names _n13f _n13e +1 1 +0 0 +.mv _n142 2 Y N +.names _n142 +Y +# CraneOnTheLeft == 0 +.names CraneOnTheLeft _n142 _n141 +.def 0 +- =CraneOnTheLeft 1 +.names _n141 _n143 +- =_n141 +.mv _n145 2 Y N +.names _n145 +Y +# FBReady == 0 +.names FBReady _n145 _n144 +.def 0 +- =FBReady 1 +.names _n144 _n146 +- =_n144 +# Grip = 1 +.mv Grip$_n144_n147$true 2 Grab Free +.names Grip$_n144_n147$true +Free +# HorizontalMove = 2 +.mv HorizontalMove$_n144_n148$true 3 GoLeft GoRight Stop +.names HorizontalMove$_n144_n148$true +Stop +# VerticalMove = 0 +.mv VerticalMove$_n144_n149$true 3 GoUp GoDown Stop +.names VerticalMove$_n144_n149$true +GoUp +# PieceReleasedOnFB = 0 +.mv PieceReleasedOnFB$_n144_n14a$true 2 Y N +.names PieceReleasedOnFB$_n144_n14a$true +Y +# Grip = 0 +.mv Grip$_n144_n14b$false 2 Grab Free +.names Grip$_n144_n14b$false +Grab +# HorizontalMove = 2 +.mv HorizontalMove$_n144_n14c$false 3 GoLeft GoRight Stop +.names HorizontalMove$_n144_n14c$false +Stop +# VerticalMove = 2 +.mv VerticalMove$_n144_n14d$false 3 GoUp GoDown Stop +.names VerticalMove$_n144_n14d$false +Stop +# if/else (FBReady == 0) +.mv VerticalMove$_n144$raw_n152 3 GoUp GoDown Stop +.names VerticalMove$_n144_n149$true VerticalMove$_n144_n14d$false _n144 VerticalMove$_n144$raw_n152 +- - 0 =VerticalMove$_n144_n14d$false +- - 1 =VerticalMove$_n144_n149$true +.mv HorizontalMove$_n144$raw_n154 3 GoLeft GoRight Stop +.names HorizontalMove$_n144_n148$true HorizontalMove$_n144_n14c$false _n144 HorizontalMove$_n144$raw_n154 +- - 0 =HorizontalMove$_n144_n14c$false +- - 1 =HorizontalMove$_n144_n148$true +.mv Grip$_n144$raw_n155 2 Grab Free +.names Grip$_n144_n147$true Grip$_n144_n14b$false _n144 Grip$_n144$raw_n155 +- - 0 =Grip$_n144_n14b$false +- - 1 =Grip$_n144_n147$true +.mv PieceReleasedOnFB$_n144$raw_n157 2 Y N +.names PieceReleasedOnFB$_n144_n14a$true PieceReleasedOnFB _n144 PieceReleasedOnFB$_n144$raw_n157 +- - 0 =PieceReleasedOnFB +- - 1 =PieceReleasedOnFB$_n144_n14a$true +# if/else (CraneOnTheLeft == 0) +.mv VerticalMove$_n141$raw_n165 3 GoUp GoDown Stop +.names VerticalMove$_n144$raw_n152 VerticalMove _n141 VerticalMove$_n141$raw_n165 +- - 0 =VerticalMove +- - 1 =VerticalMove$_n144$raw_n152 +.mv PieceReleasedOnFB$_n141$raw_n166 2 Y N +.names PieceReleasedOnFB$_n144$raw_n157 PieceReleasedOnFB _n141 PieceReleasedOnFB$_n141$raw_n166 +- - 0 =PieceReleasedOnFB +- - 1 =PieceReleasedOnFB$_n144$raw_n157 +.mv HorizontalMove$_n141$raw_n167 3 GoLeft GoRight Stop +.names HorizontalMove$_n144$raw_n154 HorizontalMove _n141 HorizontalMove$_n141$raw_n167 +- - 0 =HorizontalMove +- - 1 =HorizontalMove$_n144$raw_n154 +.mv Grip$_n141$raw_n168 2 Grab Free +.names Grip$_n144$raw_n155 Grip _n141 Grip$_n141$raw_n168 +- - 0 =Grip +- - 1 =Grip$_n144$raw_n155 +# case (VerticalPos ) +.mv VerticalMove$_n13e$raw_n171 3 GoUp GoDown Stop +.names VerticalMove$_n141$raw_n165 VerticalMove _n13e VerticalMove$_n13e$raw_n171 +- - 0 =VerticalMove +- - 1 =VerticalMove$_n141$raw_n165 +.mv PieceReleasedOnFB$_n13e$raw_n172 2 Y N +.names PieceReleasedOnFB$_n141$raw_n166 PieceReleasedOnFB _n13e PieceReleasedOnFB$_n13e$raw_n172 +- - 0 =PieceReleasedOnFB +- - 1 =PieceReleasedOnFB$_n141$raw_n166 +.mv HorizontalMove$_n13e$raw_n173 3 GoLeft GoRight Stop +.names HorizontalMove$_n141$raw_n167 HorizontalMove _n13e HorizontalMove$_n13e$raw_n173 +- - 0 =HorizontalMove +- - 1 =HorizontalMove$_n141$raw_n167 +.mv Grip$_n13e$raw_n174 2 Grab Free +.names Grip$_n141$raw_n168 Grip _n13e Grip$_n13e$raw_n174 +- - 0 =Grip +- - 1 =Grip$_n141$raw_n168 +.mv VerticalMove$_nd3$raw_n175 3 GoUp GoDown Stop +.names VerticalMove$_n113$raw_n12e VerticalMove$_n13e$raw_n171 _nd3 VerticalMove$_nd3$raw_n175 +- - 0 =VerticalMove$_n13e$raw_n171 +- - 1 =VerticalMove$_n113$raw_n12e +.mv PieceReleasedOnFB$_nd3$raw_n176 2 Y N +.names PieceReleasedOnFB$_nd6$raw_n110 PieceReleasedOnFB$_n13e$raw_n172 _nd3 PieceReleasedOnFB$_nd3$raw_n176 +- - 0 =PieceReleasedOnFB$_n13e$raw_n172 +- - 1 =PieceReleasedOnFB$_nd6$raw_n110 +.mv HorizontalMove$_nd3$raw_n177 3 GoLeft GoRight Stop +.names HorizontalMove$_n113$raw_n130 HorizontalMove$_n13e$raw_n173 _nd3 HorizontalMove$_nd3$raw_n177 +- - 0 =HorizontalMove$_n13e$raw_n173 +- - 1 =HorizontalMove$_n113$raw_n130 +.mv Grip$_nd3$raw_n178 2 Grab Free +.names Grip$_n113$raw_n131 Grip$_n13e$raw_n174 _nd3 Grip$_nd3$raw_n178 +- - 0 =Grip$_n13e$raw_n174 +- - 1 =Grip$_n113$raw_n131 +.mv VerticalMove$_n97$raw_n185 3 GoUp GoDown Stop +.names VerticalMove$_n9b$raw_nca VerticalMove$_nd3$raw_n175 _n97 VerticalMove$_n97$raw_n185 +- - 0 =VerticalMove$_nd3$raw_n175 +- - 1 =VerticalMove$_n9b$raw_nca +.mv HorizontalMove$_n97$raw_n186 3 GoLeft GoRight Stop +.names HorizontalMove$_n9b$raw_ncb HorizontalMove$_nd3$raw_n177 _n97 HorizontalMove$_n97$raw_n186 +- - 0 =HorizontalMove$_nd3$raw_n177 +- - 1 =HorizontalMove$_n9b$raw_ncb +.mv Grip$_n97$raw_n187 2 Grab Free +.names Grip$_n97_n9a$true Grip$_nd3$raw_n178 _n97 Grip$_n97$raw_n187 +- - 0 =Grip$_nd3$raw_n178 +- - 1 =Grip$_n97_n9a$true +.mv PieceReleasedOnFB$_n97$raw_n18f 2 Y N +.names PieceReleasedOnFB PieceReleasedOnFB$_nd3$raw_n176 _n97 PieceReleasedOnFB$_n97$raw_n18f +- - 0 =PieceReleasedOnFB$_nd3$raw_n176 +- - 1 =PieceReleasedOnFB +.mv _n194 2 Grab Free +.names _n194 +Free +.names Grip _n194 _n193 +.def 0 +- =Grip 1 +.names _n193 _n192 +1 1 +0 0 +.mv _n197 3 UpMost DBHight FBHight +.names _n197 +UpMost +.names VerticalPos _n197 _n196 +.def 0 +- =VerticalPos 1 +.names _n196 _n195 +1 1 +0 0 +.mv _n199 2 Y N +.names _n199 +Y +# CraneOnTheLeft == 0 +.names CraneOnTheLeft _n199 _n198 +.def 0 +- =CraneOnTheLeft 1 +.names _n198 _n19a +- =_n198 +# Grip = 1 +.mv Grip$_n198_n19b$true 2 Grab Free +.names Grip$_n198_n19b$true +Free +# HorizontalMove = 1 +.mv HorizontalMove$_n198_n19c$true 3 GoLeft GoRight Stop +.names HorizontalMove$_n198_n19c$true +GoRight +# VerticalMove = 2 +.mv VerticalMove$_n198_n19d$true 3 GoUp GoDown Stop +.names VerticalMove$_n198_n19d$true +Stop +.mv _n19f 2 Y N +.names _n19f +N +# CraneOnTheRight == 1 +.names CraneOnTheRight _n19f _n19e +.def 0 +- =CraneOnTheRight 1 +.names _n19e _n1a0 +- =_n19e +.mv _n1a2 3 GoLeft GoRight Stop +.names _n1a2 +GoRight +# HorizontalMove == 1 +.names HorizontalMove _n1a2 _n1a1 +.def 0 +- =HorizontalMove 1 +.names _n1a1 _n1a3 +- =_n1a1 +# Grip = 1 +.mv Grip$_n1a1_n1a4$true 2 Grab Free +.names Grip$_n1a1_n1a4$true +Free +# HorizontalMove = 2 +.mv HorizontalMove$_n1a1_n1a5$true 3 GoLeft GoRight Stop +.names HorizontalMove$_n1a1_n1a5$true +Stop +# VerticalMove = 1 +.mv VerticalMove$_n1a1_n1a6$true 3 GoUp GoDown Stop +.names VerticalMove$_n1a1_n1a6$true +GoDown +# Grip = 1 +.mv Grip$_n1a1_n1a7$false 2 Grab Free +.names Grip$_n1a1_n1a7$false +Free +# HorizontalMove = 1 +.mv HorizontalMove$_n1a1_n1a8$false 3 GoLeft GoRight Stop +.names HorizontalMove$_n1a1_n1a8$false +GoRight +# VerticalMove = 2 +.mv VerticalMove$_n1a1_n1a9$false 3 GoUp GoDown Stop +.names VerticalMove$_n1a1_n1a9$false +Stop +# if/else (HorizontalMove == 1) +.mv VerticalMove$_n1a1$raw_n1ad 3 GoUp GoDown Stop +.names VerticalMove$_n1a1_n1a6$true VerticalMove$_n1a1_n1a9$false _n1a1 VerticalMove$_n1a1$raw_n1ad +- - 0 =VerticalMove$_n1a1_n1a9$false +- - 1 =VerticalMove$_n1a1_n1a6$true +.mv HorizontalMove$_n1a1$raw_n1ae 3 GoLeft GoRight Stop +.names HorizontalMove$_n1a1_n1a5$true HorizontalMove$_n1a1_n1a8$false _n1a1 HorizontalMove$_n1a1$raw_n1ae +- - 0 =HorizontalMove$_n1a1_n1a8$false +- - 1 =HorizontalMove$_n1a1_n1a5$true +.mv Grip$_n1a1$raw_n1af 2 Grab Free +.names Grip$_n1a1_n1a4$true Grip$_n1a1_n1a7$false _n1a1 Grip$_n1a1$raw_n1af +- - 0 =Grip$_n1a1_n1a7$false +- - 1 =Grip$_n1a1_n1a4$true +.mv _n1b7 2 Y N +.names _n1b7 +Y +# PieceOutDB == 0 +.names PieceOutDB _n1b7 _n1b6 +.def 0 +- =PieceOutDB 1 +.names _n1b6 _n1b8 +- =_n1b6 +.mv _n1ba 3 GoUp GoDown Stop +.names _n1ba +GoDown +# VerticalMove == 1 +.names VerticalMove _n1ba _n1b9 +.def 0 +- =VerticalMove 1 +.names _n1b9 _n1bb +- =_n1b9 +# Grip = 0 +.mv Grip$_n1b9_n1bc$true 2 Grab Free +.names Grip$_n1b9_n1bc$true +Grab +# HorizontalMove = 2 +.mv HorizontalMove$_n1b9_n1bd$true 3 GoLeft GoRight Stop +.names HorizontalMove$_n1b9_n1bd$true +Stop +# VerticalMove = 0 +.mv VerticalMove$_n1b9_n1be$true 3 GoUp GoDown Stop +.names VerticalMove$_n1b9_n1be$true +GoUp +# PieceGrabbedFromDB = 0 +.mv PieceGrabbedFromDB$_n1b9_n1bf$true 2 Y N +.names PieceGrabbedFromDB$_n1b9_n1bf$true +Y +# Grip = 1 +.mv Grip$_n1b9_n1c0$false 2 Grab Free +.names Grip$_n1b9_n1c0$false +Free +# HorizontalMove = 2 +.mv HorizontalMove$_n1b9_n1c1$false 3 GoLeft GoRight Stop +.names HorizontalMove$_n1b9_n1c1$false +Stop +# VerticalMove = 1 +.mv VerticalMove$_n1b9_n1c2$false 3 GoUp GoDown Stop +.names VerticalMove$_n1b9_n1c2$false +GoDown +# if/else (VerticalMove == 1) +.mv VerticalMove$_n1b9$raw_n1c7 3 GoUp GoDown Stop +.names VerticalMove$_n1b9_n1be$true VerticalMove$_n1b9_n1c2$false _n1b9 VerticalMove$_n1b9$raw_n1c7 +- - 0 =VerticalMove$_n1b9_n1c2$false +- - 1 =VerticalMove$_n1b9_n1be$true +.mv HorizontalMove$_n1b9$raw_n1c9 3 GoLeft GoRight Stop +.names HorizontalMove$_n1b9_n1bd$true HorizontalMove$_n1b9_n1c1$false _n1b9 HorizontalMove$_n1b9$raw_n1c9 +- - 0 =HorizontalMove$_n1b9_n1c1$false +- - 1 =HorizontalMove$_n1b9_n1bd$true +.mv Grip$_n1b9$raw_n1ca 2 Grab Free +.names Grip$_n1b9_n1bc$true Grip$_n1b9_n1c0$false _n1b9 Grip$_n1b9$raw_n1ca +- - 0 =Grip$_n1b9_n1c0$false +- - 1 =Grip$_n1b9_n1bc$true +.mv PieceGrabbedFromDB$_n1b9$raw_n1cc 2 Y N +.names PieceGrabbedFromDB$_n1b9_n1bf$true PieceGrabbedFromDB _n1b9 PieceGrabbedFromDB$_n1b9$raw_n1cc +- - 0 =PieceGrabbedFromDB +- - 1 =PieceGrabbedFromDB$_n1b9_n1bf$true +# Grip = 1 +.mv Grip$_n1b6_n1d2$false 2 Grab Free +.names Grip$_n1b6_n1d2$false +Free +# HorizontalMove = 2 +.mv HorizontalMove$_n1b6_n1d3$false 3 GoLeft GoRight Stop +.names HorizontalMove$_n1b6_n1d3$false +Stop +.mv _n1d5 3 GoUp GoDown Stop +.names _n1d5 +GoDown +# VerticalMove == 1 +.names VerticalMove _n1d5 _n1d4 +.def 0 +- =VerticalMove 1 +.names _n1d4 _n1d6 +- =_n1d4 +# VerticalMove = 2 +.mv VerticalMove$_n1d4_n1d7$true 3 GoUp GoDown Stop +.names VerticalMove$_n1d4_n1d7$true +Stop +# VerticalMove = 1 +.mv VerticalMove$_n1d4_n1d8$false 3 GoUp GoDown Stop +.names VerticalMove$_n1d4_n1d8$false +GoDown +# if/else (VerticalMove == 1) +.mv VerticalMove$_n1d4$raw_n1dc 3 GoUp GoDown Stop +.names VerticalMove$_n1d4_n1d7$true VerticalMove$_n1d4_n1d8$false _n1d4 VerticalMove$_n1d4$raw_n1dc +- - 0 =VerticalMove$_n1d4_n1d8$false +- - 1 =VerticalMove$_n1d4_n1d7$true +# if/else (PieceOutDB == 0) +.mv VerticalMove$_n1b6$raw_n1e9 3 GoUp GoDown Stop +.names VerticalMove$_n1b9$raw_n1c7 VerticalMove$_n1d4$raw_n1dc _n1b6 VerticalMove$_n1b6$raw_n1e9 +- - 0 =VerticalMove$_n1d4$raw_n1dc +- - 1 =VerticalMove$_n1b9$raw_n1c7 +.mv HorizontalMove$_n1b6$raw_n1eb 3 GoLeft GoRight Stop +.names HorizontalMove$_n1b9$raw_n1c9 HorizontalMove$_n1b6_n1d3$false _n1b6 HorizontalMove$_n1b6$raw_n1eb +- - 0 =HorizontalMove$_n1b6_n1d3$false +- - 1 =HorizontalMove$_n1b9$raw_n1c9 +.mv Grip$_n1b6$raw_n1ec 2 Grab Free +.names Grip$_n1b9$raw_n1ca Grip$_n1b6_n1d2$false _n1b6 Grip$_n1b6$raw_n1ec +- - 0 =Grip$_n1b6_n1d2$false +- - 1 =Grip$_n1b9$raw_n1ca +.mv PieceGrabbedFromDB$_n1b6$raw_n1ee 2 Y N +.names PieceGrabbedFromDB$_n1b9$raw_n1cc PieceGrabbedFromDB _n1b6 PieceGrabbedFromDB$_n1b6$raw_n1ee +- - 0 =PieceGrabbedFromDB +- - 1 =PieceGrabbedFromDB$_n1b9$raw_n1cc +# if/else (CraneOnTheRight == 1) +.mv VerticalMove$_n19e$raw_n1f7 3 GoUp GoDown Stop +.names VerticalMove$_n1a1$raw_n1ad VerticalMove$_n1b6$raw_n1e9 _n19e VerticalMove$_n19e$raw_n1f7 +- - 0 =VerticalMove$_n1b6$raw_n1e9 +- - 1 =VerticalMove$_n1a1$raw_n1ad +.mv HorizontalMove$_n19e$raw_n1f8 3 GoLeft GoRight Stop +.names HorizontalMove$_n1a1$raw_n1ae HorizontalMove$_n1b6$raw_n1eb _n19e HorizontalMove$_n19e$raw_n1f8 +- - 0 =HorizontalMove$_n1b6$raw_n1eb +- - 1 =HorizontalMove$_n1a1$raw_n1ae +.mv Grip$_n19e$raw_n1f9 2 Grab Free +.names Grip$_n1a1$raw_n1af Grip$_n1b6$raw_n1ec _n19e Grip$_n19e$raw_n1f9 +- - 0 =Grip$_n1b6$raw_n1ec +- - 1 =Grip$_n1a1$raw_n1af +.mv PieceGrabbedFromDB$_n19e$raw_n1fe 2 Y N +.names PieceGrabbedFromDB PieceGrabbedFromDB$_n1b6$raw_n1ee _n19e PieceGrabbedFromDB$_n19e$raw_n1fe +- - 0 =PieceGrabbedFromDB$_n1b6$raw_n1ee +- - 1 =PieceGrabbedFromDB +# if/else (CraneOnTheLeft == 0) +.mv VerticalMove$_n198$raw_n204 3 GoUp GoDown Stop +.names VerticalMove$_n198_n19d$true VerticalMove$_n19e$raw_n1f7 _n198 VerticalMove$_n198$raw_n204 +- - 0 =VerticalMove$_n19e$raw_n1f7 +- - 1 =VerticalMove$_n198_n19d$true +.mv HorizontalMove$_n198$raw_n205 3 GoLeft GoRight Stop +.names HorizontalMove$_n198_n19c$true HorizontalMove$_n19e$raw_n1f8 _n198 HorizontalMove$_n198$raw_n205 +- - 0 =HorizontalMove$_n19e$raw_n1f8 +- - 1 =HorizontalMove$_n198_n19c$true +.mv Grip$_n198$raw_n206 2 Grab Free +.names Grip$_n198_n19b$true Grip$_n19e$raw_n1f9 _n198 Grip$_n198$raw_n206 +- - 0 =Grip$_n19e$raw_n1f9 +- - 1 =Grip$_n198_n19b$true +.mv PieceGrabbedFromDB$_n198$raw_n20b 2 Y N +.names PieceGrabbedFromDB PieceGrabbedFromDB$_n19e$raw_n1fe _n198 PieceGrabbedFromDB$_n198$raw_n20b +- - 0 =PieceGrabbedFromDB$_n19e$raw_n1fe +- - 1 =PieceGrabbedFromDB +.mv _n210 3 UpMost DBHight FBHight +.names _n210 +DBHight +.names VerticalPos _n210 _n20f +.def 0 +- =VerticalPos 1 +.names _n20f _n20e +1 1 +0 0 +.mv _n212 2 Y N +.names _n212 +Y +# CraneOnTheLeft == 0 +.names CraneOnTheLeft _n212 _n211 +.def 0 +- =CraneOnTheLeft 1 +.names _n211 _n213 +- =_n211 +# Grip = 1 +.mv Grip$_n211_n214$true 2 Grab Free +.names Grip$_n211_n214$true +Free +.mv _n216 3 GoUp GoDown Stop +.names _n216 +GoUp +# VerticalMove == 0 +.names VerticalMove _n216 _n215 +.def 0 +- =VerticalMove 1 +.names _n215 _n217 +- =_n215 +# HorizontalMove = 1 +.mv HorizontalMove$_n215_n218$true 3 GoLeft GoRight Stop +.names HorizontalMove$_n215_n218$true +GoRight +# VerticalMove = 2 +.mv VerticalMove$_n215_n219$true 3 GoUp GoDown Stop +.names VerticalMove$_n215_n219$true +Stop +# HorizontalMove = 2 +.mv HorizontalMove$_n215_n21a$false 3 GoLeft GoRight Stop +.names HorizontalMove$_n215_n21a$false +Stop +# VerticalMove = 0 +.mv VerticalMove$_n215_n21b$false 3 GoUp GoDown Stop +.names VerticalMove$_n215_n21b$false +GoUp +# if/else (VerticalMove == 0) +.mv VerticalMove$_n215$raw_n21f 3 GoUp GoDown Stop +.names VerticalMove$_n215_n219$true VerticalMove$_n215_n21b$false _n215 VerticalMove$_n215$raw_n21f +- - 0 =VerticalMove$_n215_n21b$false +- - 1 =VerticalMove$_n215_n219$true +.mv HorizontalMove$_n215$raw_n220 3 GoLeft GoRight Stop +.names HorizontalMove$_n215_n218$true HorizontalMove$_n215_n21a$false _n215 HorizontalMove$_n215$raw_n220 +- - 0 =HorizontalMove$_n215_n21a$false +- - 1 =HorizontalMove$_n215_n218$true +# if/else (CraneOnTheLeft == 0) +.mv VerticalMove$_n211$raw_n22e 3 GoUp GoDown Stop +.names VerticalMove$_n215$raw_n21f VerticalMove _n211 VerticalMove$_n211$raw_n22e +- - 0 =VerticalMove +- - 1 =VerticalMove$_n215$raw_n21f +.mv HorizontalMove$_n211$raw_n22f 3 GoLeft GoRight Stop +.names HorizontalMove$_n215$raw_n220 HorizontalMove _n211 HorizontalMove$_n211$raw_n22f +- - 0 =HorizontalMove +- - 1 =HorizontalMove$_n215$raw_n220 +.mv Grip$_n211$raw_n230 2 Grab Free +.names Grip$_n211_n214$true Grip _n211 Grip$_n211$raw_n230 +- - 0 =Grip +- - 1 =Grip$_n211_n214$true +.mv _n232 2 Y N +.names _n232 +Y +# CraneOnTheRight == 0 +.names CraneOnTheRight _n232 _n231 +.def 0 +- =CraneOnTheRight 1 +.names _n231 _n233 +- =_n231 +.mv _n235 2 Y N +.names _n235 +Y +# PieceOutDB == 0 +.names PieceOutDB _n235 _n234 +.def 0 +- =PieceOutDB 1 +.names _n234 _n236 +- =_n234 +# Grip = 0 +.mv Grip$_n234_n237$true 2 Grab Free +.names Grip$_n234_n237$true +Grab +# HorizontalMove = 2 +.mv HorizontalMove$_n234_n238$true 3 GoLeft GoRight Stop +.names HorizontalMove$_n234_n238$true +Stop +# VerticalMove = 0 +.mv VerticalMove$_n234_n239$true 3 GoUp GoDown Stop +.names VerticalMove$_n234_n239$true +GoUp +# PieceGrabbedFromDB = 0 +.mv PieceGrabbedFromDB$_n234_n23a$true 2 Y N +.names PieceGrabbedFromDB$_n234_n23a$true +Y +# Grip = 1 +.mv Grip$_n234_n23b$false 2 Grab Free +.names Grip$_n234_n23b$false +Free +# HorizontalMove = 2 +.mv HorizontalMove$_n234_n23c$false 3 GoLeft GoRight Stop +.names HorizontalMove$_n234_n23c$false +Stop +# VerticalMove = 2 +.mv VerticalMove$_n234_n23d$false 3 GoUp GoDown Stop +.names VerticalMove$_n234_n23d$false +Stop +# if/else (PieceOutDB == 0) +.mv VerticalMove$_n234$raw_n23e 3 GoUp GoDown Stop +.names VerticalMove$_n234_n239$true VerticalMove$_n234_n23d$false _n234 VerticalMove$_n234$raw_n23e +- - 0 =VerticalMove$_n234_n23d$false +- - 1 =VerticalMove$_n234_n239$true +.mv HorizontalMove$_n234$raw_n240 3 GoLeft GoRight Stop +.names HorizontalMove$_n234_n238$true HorizontalMove$_n234_n23c$false _n234 HorizontalMove$_n234$raw_n240 +- - 0 =HorizontalMove$_n234_n23c$false +- - 1 =HorizontalMove$_n234_n238$true +.mv Grip$_n234$raw_n241 2 Grab Free +.names Grip$_n234_n237$true Grip$_n234_n23b$false _n234 Grip$_n234$raw_n241 +- - 0 =Grip$_n234_n23b$false +- - 1 =Grip$_n234_n237$true +.mv PieceGrabbedFromDB$_n234$raw_n247 2 Y N +.names PieceGrabbedFromDB$_n234_n23a$true PieceGrabbedFromDB _n234 PieceGrabbedFromDB$_n234$raw_n247 +- - 0 =PieceGrabbedFromDB +- - 1 =PieceGrabbedFromDB$_n234_n23a$true +# if/else (CraneOnTheRight == 0) +.mv VerticalMove$_n231$raw_n24d 3 GoUp GoDown Stop +.names VerticalMove$_n234$raw_n23e VerticalMove$_n211$raw_n22e _n231 VerticalMove$_n231$raw_n24d +- - 0 =VerticalMove$_n211$raw_n22e +- - 1 =VerticalMove$_n234$raw_n23e +.mv HorizontalMove$_n231$raw_n24f 3 GoLeft GoRight Stop +.names HorizontalMove$_n234$raw_n240 HorizontalMove$_n211$raw_n22f _n231 HorizontalMove$_n231$raw_n24f +- - 0 =HorizontalMove$_n211$raw_n22f +- - 1 =HorizontalMove$_n234$raw_n240 +.mv Grip$_n231$raw_n250 2 Grab Free +.names Grip$_n234$raw_n241 Grip$_n211$raw_n230 _n231 Grip$_n231$raw_n250 +- - 0 =Grip$_n211$raw_n230 +- - 1 =Grip$_n234$raw_n241 +.mv PieceGrabbedFromDB$_n231$raw_n256 2 Y N +.names PieceGrabbedFromDB$_n234$raw_n247 PieceGrabbedFromDB _n231 PieceGrabbedFromDB$_n231$raw_n256 +- - 0 =PieceGrabbedFromDB +- - 1 =PieceGrabbedFromDB$_n234$raw_n247 +.mv _n25e 3 UpMost DBHight FBHight +.names _n25e +FBHight +.names VerticalPos _n25e _n25d +.def 0 +- =VerticalPos 1 +.names _n25d _n25c +1 1 +0 0 +.mv _n260 2 Y N +.names _n260 +Y +# CraneOnTheLeft == 0 +.names CraneOnTheLeft _n260 _n25f +.def 0 +- =CraneOnTheLeft 1 +.names _n25f _n261 +- =_n25f +# Grip = 1 +.mv Grip$_n25f_n262$true 2 Grab Free +.names Grip$_n25f_n262$true +Free +# HorizontalMove = 2 +.mv HorizontalMove$_n25f_n263$true 3 GoLeft GoRight Stop +.names HorizontalMove$_n25f_n263$true +Stop +# VerticalMove = 0 +.mv VerticalMove$_n25f_n264$true 3 GoUp GoDown Stop +.names VerticalMove$_n25f_n264$true +GoUp +# if/else (CraneOnTheLeft == 0) +.mv VerticalMove$_n25f$raw_n26b 3 GoUp GoDown Stop +.names VerticalMove$_n25f_n264$true VerticalMove _n25f VerticalMove$_n25f$raw_n26b +- - 0 =VerticalMove +- - 1 =VerticalMove$_n25f_n264$true +.mv HorizontalMove$_n25f$raw_n26c 3 GoLeft GoRight Stop +.names HorizontalMove$_n25f_n263$true HorizontalMove _n25f HorizontalMove$_n25f$raw_n26c +- - 0 =HorizontalMove +- - 1 =HorizontalMove$_n25f_n263$true +.mv Grip$_n25f$raw_n26d 2 Grab Free +.names Grip$_n25f_n262$true Grip _n25f Grip$_n25f$raw_n26d +- - 0 =Grip +- - 1 =Grip$_n25f_n262$true +# case (VerticalPos ) +.mv VerticalMove$_n25c$raw_n274 3 GoUp GoDown Stop +.names VerticalMove$_n25f$raw_n26b VerticalMove _n25c VerticalMove$_n25c$raw_n274 +- - 0 =VerticalMove +- - 1 =VerticalMove$_n25f$raw_n26b +.mv HorizontalMove$_n25c$raw_n275 3 GoLeft GoRight Stop +.names HorizontalMove$_n25f$raw_n26c HorizontalMove _n25c HorizontalMove$_n25c$raw_n275 +- - 0 =HorizontalMove +- - 1 =HorizontalMove$_n25f$raw_n26c +.mv Grip$_n25c$raw_n276 2 Grab Free +.names Grip$_n25f$raw_n26d Grip _n25c Grip$_n25c$raw_n276 +- - 0 =Grip +- - 1 =Grip$_n25f$raw_n26d +.mv VerticalMove$_n20e$raw_n277 3 GoUp GoDown Stop +.names VerticalMove$_n231$raw_n24d VerticalMove$_n25c$raw_n274 _n20e VerticalMove$_n20e$raw_n277 +- - 0 =VerticalMove$_n25c$raw_n274 +- - 1 =VerticalMove$_n231$raw_n24d +.mv HorizontalMove$_n20e$raw_n279 3 GoLeft GoRight Stop +.names HorizontalMove$_n231$raw_n24f HorizontalMove$_n25c$raw_n275 _n20e HorizontalMove$_n20e$raw_n279 +- - 0 =HorizontalMove$_n25c$raw_n275 +- - 1 =HorizontalMove$_n231$raw_n24f +.mv Grip$_n20e$raw_n27a 2 Grab Free +.names Grip$_n231$raw_n250 Grip$_n25c$raw_n276 _n20e Grip$_n20e$raw_n27a +- - 0 =Grip$_n25c$raw_n276 +- - 1 =Grip$_n231$raw_n250 +.mv PieceGrabbedFromDB$_n20e$raw_n280 2 Y N +.names PieceGrabbedFromDB$_n231$raw_n256 PieceGrabbedFromDB _n20e PieceGrabbedFromDB$_n20e$raw_n280 +- - 0 =PieceGrabbedFromDB +- - 1 =PieceGrabbedFromDB$_n231$raw_n256 +.mv VerticalMove$_n195$raw_n286 3 GoUp GoDown Stop +.names VerticalMove$_n198$raw_n204 VerticalMove$_n20e$raw_n277 _n195 VerticalMove$_n195$raw_n286 +- - 0 =VerticalMove$_n20e$raw_n277 +- - 1 =VerticalMove$_n198$raw_n204 +.mv PieceGrabbedFromDB$_n195$raw_n287 2 Y N +.names PieceGrabbedFromDB$_n198$raw_n20b PieceGrabbedFromDB$_n20e$raw_n280 _n195 PieceGrabbedFromDB$_n195$raw_n287 +- - 0 =PieceGrabbedFromDB$_n20e$raw_n280 +- - 1 =PieceGrabbedFromDB$_n198$raw_n20b +.mv HorizontalMove$_n195$raw_n288 3 GoLeft GoRight Stop +.names HorizontalMove$_n198$raw_n205 HorizontalMove$_n20e$raw_n279 _n195 HorizontalMove$_n195$raw_n288 +- - 0 =HorizontalMove$_n20e$raw_n279 +- - 1 =HorizontalMove$_n198$raw_n205 +.mv Grip$_n195$raw_n289 2 Grab Free +.names Grip$_n198$raw_n206 Grip$_n20e$raw_n27a _n195 Grip$_n195$raw_n289 +- - 0 =Grip$_n20e$raw_n27a +- - 1 =Grip$_n198$raw_n206 +# case (Grip ) +.mv VerticalMove$_n192$raw_n29e 3 GoUp GoDown Stop +.names VerticalMove$_n195$raw_n286 VerticalMove _n192 VerticalMove$_n192$raw_n29e +- - 0 =VerticalMove +- - 1 =VerticalMove$_n195$raw_n286 +.mv PieceGrabbedFromDB$_n192$raw_n29f 2 Y N +.names PieceGrabbedFromDB$_n195$raw_n287 PieceGrabbedFromDB _n192 PieceGrabbedFromDB$_n192$raw_n29f +- - 0 =PieceGrabbedFromDB +- - 1 =PieceGrabbedFromDB$_n195$raw_n287 +.mv HorizontalMove$_n192$raw_n2a0 3 GoLeft GoRight Stop +.names HorizontalMove$_n195$raw_n288 HorizontalMove _n192 HorizontalMove$_n192$raw_n2a0 +- - 0 =HorizontalMove +- - 1 =HorizontalMove$_n195$raw_n288 +.mv Grip$_n192$raw_n2a1 2 Grab Free +.names Grip$_n195$raw_n289 Grip _n192 Grip$_n192$raw_n2a1 +- - 0 =Grip +- - 1 =Grip$_n195$raw_n289 +.mv VerticalMove$_n94$raw_n2a2 3 GoUp GoDown Stop +.names VerticalMove$_n97$raw_n185 VerticalMove$_n192$raw_n29e _n94 VerticalMove$_n94$raw_n2a2 +- - 0 =VerticalMove$_n192$raw_n29e +- - 1 =VerticalMove$_n97$raw_n185 +.mv HorizontalMove$_n94$raw_n2a4 3 GoLeft GoRight Stop +.names HorizontalMove$_n97$raw_n186 HorizontalMove$_n192$raw_n2a0 _n94 HorizontalMove$_n94$raw_n2a4 +- - 0 =HorizontalMove$_n192$raw_n2a0 +- - 1 =HorizontalMove$_n97$raw_n186 +.mv Grip$_n94$raw_n2a5 2 Grab Free +.names Grip$_n97$raw_n187 Grip$_n192$raw_n2a1 _n94 Grip$_n94$raw_n2a5 +- - 0 =Grip$_n192$raw_n2a1 +- - 1 =Grip$_n97$raw_n187 +.mv PieceReleasedOnFB$_n94$raw_n2ab 2 Y N +.names PieceReleasedOnFB$_n97$raw_n18f PieceReleasedOnFB _n94 PieceReleasedOnFB$_n94$raw_n2ab +- - 0 =PieceReleasedOnFB +- - 1 =PieceReleasedOnFB$_n97$raw_n18f +.mv PieceGrabbedFromDB$_n94$raw_n2af 2 Y N +.names PieceGrabbedFromDB PieceGrabbedFromDB$_n192$raw_n29f _n94 PieceGrabbedFromDB$_n94$raw_n2af +- - 0 =PieceGrabbedFromDB$_n192$raw_n29f +- - 1 =PieceGrabbedFromDB +.mv _n2b3 2 Y N +.names _n2b3 +N +# PieceOutDB == 1 +.names PieceOutDB _n2b3 _n2b2 +.def 0 +- =PieceOutDB 1 +.mv _n2b5 2 Y N +.names _n2b5 +Y +# PieceGrabbedFromDB == 0 +.names PieceGrabbedFromDB$_n94$raw_n2af _n2b5 _n2b4 +.def 0 +- =PieceGrabbedFromDB$_n94$raw_n2af 1 +# PieceOutDB == 1 && PieceGrabbedFromDB == 0 +.names _n2b2 _n2b4 _n2b6 +.def 0 +1 1 1 +.names _n2b6 _n2b7 +- =_n2b6 +# PieceGrabbedFromDB = 1 +.mv PieceGrabbedFromDB$_n2b6_n2b8$true 2 Y N +.names PieceGrabbedFromDB$_n2b6_n2b8$true +N +# if/else (PieceOutDB == 1 && PieceGrabbedFromDB == 0) +.mv PieceGrabbedFromDB$_n2b6$raw_n2ba 2 Y N +.names PieceGrabbedFromDB$_n2b6_n2b8$true PieceGrabbedFromDB$_n94$raw_n2af _n2b6 PieceGrabbedFromDB$_n2b6$raw_n2ba +- - 0 =PieceGrabbedFromDB$_n94$raw_n2af +- - 1 =PieceGrabbedFromDB$_n2b6_n2b8$true +.mv _n2ce 2 Y N +.names _n2ce +N +# FBReady == 1 +.names FBReady _n2ce _n2cd +.def 0 +- =FBReady 1 +.mv _n2d0 2 Y N +.names _n2d0 +Y +# PieceReleasedOnFB == 0 +.names PieceReleasedOnFB$_n94$raw_n2ab _n2d0 _n2cf +.def 0 +- =PieceReleasedOnFB$_n94$raw_n2ab 1 +# FBReady == 1 && PieceReleasedOnFB == 0 +.names _n2cd _n2cf _n2d1 +.def 0 +1 1 1 +.names _n2d1 _n2d2 +- =_n2d1 +# PieceReleasedOnFB = 1 +.mv PieceReleasedOnFB$_n2d1_n2d3$true 2 Y N +.names PieceReleasedOnFB$_n2d1_n2d3$true +N +# if/else (FBReady == 1 && PieceReleasedOnFB == 0) +.mv PieceReleasedOnFB$_n2d1$raw_n2d6 2 Y N +.names PieceReleasedOnFB$_n2d1_n2d3$true PieceReleasedOnFB$_n94$raw_n2ab _n2d1 PieceReleasedOnFB$_n2d1$raw_n2d6 +- - 0 =PieceReleasedOnFB$_n94$raw_n2ab +- - 1 =PieceReleasedOnFB$_n2d1_n2d3$true +# conflict arbitrators +.names _n94 _n97 _n9d _na5 _na8 _nd3 _nd8 _ndb _nde _n115 _n119 _n13e _n143 _n146 _n192 _n195 _n19a _n1a0 _n1a3 _n1b8 _n1bb _n1d6 _n20e _n213 _n217 _n233 _n236 _n25c _n261 _n2e8 +.def 0 + 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 0 1 1 - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 0 1 0 - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 0 0 - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 1 1 1 0 - - - - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 1 1 0 - - - - - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 1 - - - 1 1 - - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 1 - - - 1 0 - - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 0 - - - - - 1 1 1 - - - - - - - - - - - - - - - 1 + 1 0 - - - 0 - - - - - 1 1 0 - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 1 - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 0 1 1 - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 0 1 0 - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 0 0 - 1 1 - - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 0 0 - 1 0 - - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 0 0 - 0 - 1 - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 0 0 - 0 - 0 - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 0 - - - - - - 1 1 1 - - - - 1 + 0 - - - - - - - - - - - - - 1 0 - - - - - - 1 1 0 - - - - 1 + 0 - - - - - - - - - - - - - 1 0 - - - - - - 1 - - 1 1 - - 1 + 0 - - - - - - - - - - - - - 1 0 - - - - - - 1 - - 1 0 - - 1 + 0 - - - - - - - - - - - - - 1 0 - - - - - - 0 - - - - 1 1 1 +.mv _n2e9 3 GoUp GoDown Stop +.names _n2e8 VerticalMove$_n94$raw_n2a2 VerticalMove _n2e9 +1 - - =VerticalMove$_n94$raw_n2a2 +0 - - =VerticalMove +.names _n94 _n192 _n195 _n19a _n1a0 _n1b8 _n1bb _n20e _n233 _n236 _n2b7 _n2ef +.def 0 + 0 1 1 0 0 1 1 - - - - 1 + 0 1 0 - - - - 1 1 1 - 1 + - - - - - - - - - - 1 1 +.mv _n2f0 2 Y N +.names _n2ef PieceGrabbedFromDB$_n2b6$raw_n2ba PieceGrabbedFromDB _n2f0 +1 - - =PieceGrabbedFromDB$_n2b6$raw_n2ba +0 - - =PieceGrabbedFromDB +.names _n94 _n97 _nd3 _nd8 _ndb _nde _n13e _n143 _n146 _n2d2 _n2f6 +.def 0 + 1 0 1 1 1 1 - - - - 1 + 1 0 0 - - - 1 1 1 - 1 + - - - - - - - - - 1 1 +.mv _n2f7 2 Y N +.names _n2f6 PieceReleasedOnFB$_n2d1$raw_n2d6 PieceReleasedOnFB _n2f7 +1 - - =PieceReleasedOnFB$_n2d1$raw_n2d6 +0 - - =PieceReleasedOnFB +.names _n94 _n97 _n9d _na5 _na8 _nd3 _nd8 _ndb _nde _n115 _n119 _n13e _n143 _n146 _n192 _n195 _n19a _n1a0 _n1a3 _n1b8 _n1bb _n20e _n213 _n217 _n233 _n236 _n25c _n261 _n2fd +.def 0 + 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 0 1 1 - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 0 1 0 - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 0 0 - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 1 1 1 1 - - - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 1 1 1 0 - - - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 1 1 0 - - - - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 1 - - - 1 1 - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 1 - - - 1 0 - - - - - - - - - - - - - - - - - 1 + 1 0 - - - 0 - - - - - 1 1 1 - - - - - - - - - - - - - - 1 + 1 0 - - - 0 - - - - - 1 1 0 - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 1 - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 0 1 1 - - - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 0 1 0 - - - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 0 0 - 1 1 - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 0 0 - 1 0 - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 1 0 0 - 0 - - - - - - - - 1 + 0 - - - - - - - - - - - - - 1 0 - - - - - 1 1 1 - - - - 1 + 0 - - - - - - - - - - - - - 1 0 - - - - - 1 1 0 - - - - 1 + 0 - - - - - - - - - - - - - 1 0 - - - - - 1 - - 1 1 - - 1 + 0 - - - - - - - - - - - - - 1 0 - - - - - 1 - - 1 0 - - 1 + 0 - - - - - - - - - - - - - 1 0 - - - - - 0 - - - - 1 1 1 +.mv _n2fe 3 GoLeft GoRight Stop +.names _n2fd HorizontalMove$_n94$raw_n2a4 HorizontalMove _n2fe +1 - - =HorizontalMove$_n94$raw_n2a4 +0 - - =HorizontalMove +.names _n94 _n97 _nd3 _nd8 _ndb _nde _n115 _n13e _n143 _n146 _n192 _n195 _n19a _n1a0 _n1a3 _n1b8 _n1bb _n20e _n213 _n233 _n236 _n25c _n261 _n304 +.def 0 + 1 1 - - - - - - - - - - - - - - - - - - - - - 1 + 1 0 1 1 1 1 - - - - - - - - - - - - - - - - - 1 + 1 0 1 1 1 0 - - - - - - - - - - - - - - - - - 1 + 1 0 1 1 0 - - - - - - - - - - - - - - - - - - 1 + 1 0 1 - - - 1 - - - - - - - - - - - - - - - - 1 + 1 0 0 - - - - 1 1 1 - - - - - - - - - - - - - 1 + 1 0 0 - - - - 1 1 0 - - - - - - - - - - - - - 1 + 0 - - - - - - - - - 1 1 1 - - - - - - - - - - 1 + 0 - - - - - - - - - 1 1 0 1 1 - - - - - - - - 1 + 0 - - - - - - - - - 1 1 0 1 0 - - - - - - - - 1 + 0 - - - - - - - - - 1 1 0 0 - 1 1 - - - - - - 1 + 0 - - - - - - - - - 1 1 0 0 - 1 0 - - - - - - 1 + 0 - - - - - - - - - 1 1 0 0 - 0 - - - - - - - 1 + 0 - - - - - - - - - 1 0 - - - - - 1 1 - - - - 1 + 0 - - - - - - - - - 1 0 - - - - - 1 - 1 1 - - 1 + 0 - - - - - - - - - 1 0 - - - - - 1 - 1 0 - - 1 + 0 - - - - - - - - - 1 0 - - - - - 0 - - - 1 1 1 +.mv _n305 2 Grab Free +.names _n304 Grip$_n94$raw_n2a5 Grip _n305 +1 - - =Grip$_n94$raw_n2a5 +0 - - =Grip +# non-blocking assignments +# latches +.r VerticalMove$raw_n90 VerticalMove +- =VerticalMove$raw_n90 +.latch _n2e9 VerticalMove +.r PieceReleasedOnFB$raw_n92 PieceReleasedOnFB +- =PieceReleasedOnFB$raw_n92 +.latch _n2f7 PieceReleasedOnFB +.r PieceGrabbedFromDB$raw_n93 PieceGrabbedFromDB +- =PieceGrabbedFromDB$raw_n93 +.latch _n2f0 PieceGrabbedFromDB +.r HorizontalMove$raw_n8f HorizontalMove +- =HorizontalMove$raw_n8f +.latch _n2fe HorizontalMove +.r Grip$raw_n91 Grip +- =Grip$raw_n91 +.latch _n305 Grip +# quasi-continuous assignment +.end + + +.model DepositBelt +# I/O ports +.inputs PieceGrabbedFromDB +.outputs DBelt3 +.outputs DBelt2 +.outputs DBelt1 +.outputs DBelt0 +.inputs PieceOutArm +.inputs DBReady +.inputs DBMotorSwitch +.mv PieceGrabbedFromDB 2 Y N +.mv DBelt3 2 E F +.mv DBelt2 2 E F +.mv DBelt1 2 E F +.mv DBelt0 2 E F +.mv PieceOutArm 2 Y N +.mv DBReady 2 Y N +.mv DBMotorSwitch 2 on off +# DBelt0 = 1 +.mv DBelt0$raw_n30b 2 E F +.names DBelt0$raw_n30b +F +# DBelt1 = $NDset ( 0,1 ) +.mv DBelt1$raw_n30c 2 E F +.mv DBelt1$raw_n30c$initial$_n30d 2 E F +.names DBelt1$raw_n30c$initial$_n30d +E +F +.names DBelt1$raw_n30c$initial$_n30d DBelt1$raw_n30c +- =DBelt1$raw_n30c$initial$_n30d +# DBelt2 = $NDset ( 0,1 ) +.mv DBelt2$raw_n30e 2 E F +.mv DBelt2$raw_n30e$initial$_n30f 2 E F +.names DBelt2$raw_n30e$initial$_n30f +E +F +.names DBelt2$raw_n30e$initial$_n30f DBelt2$raw_n30e +- =DBelt2$raw_n30e$initial$_n30f +# DBelt3 = $NDset ( 0,1 ) +.mv DBelt3$raw_n310 2 E F +.mv DBelt3$raw_n310$initial$_n311 2 E F +.names DBelt3$raw_n310$initial$_n311 +E +F +.names DBelt3$raw_n310$initial$_n311 DBelt3$raw_n310 +- =DBelt3$raw_n310$initial$_n311 +# non-blocking assignments for initial +.mv _n313 2 on off +.names _n313 +on +# DBMotorSwitch == 0 +.names DBMotorSwitch _n313 _n312 +.def 0 +- =DBMotorSwitch 1 +.names _n312 _n314 +- =_n312 +# DBelt0 = DBelt1 +.mv DBelt0$_n312_n315$true 2 E F +.names DBelt1 DBelt0$_n312_n315$true +- =DBelt1 +# DBelt1 = DBelt2 +.mv DBelt1$_n312_n316$true 2 E F +.names DBelt2 DBelt1$_n312_n316$true +- =DBelt2 +# DBelt2 = DBelt3 +.mv DBelt2$_n312_n317$true 2 E F +.names DBelt3 DBelt2$_n312_n317$true +- =DBelt3 +# DBelt3 = 0 +.mv DBelt3$_n312_n318$true 2 E F +.names DBelt3$_n312_n318$true +E +# if/else (DBMotorSwitch == 0) +.mv DBelt3$_n312$raw_n321 2 E F +.names DBelt3$_n312_n318$true DBelt3 _n312 DBelt3$_n312$raw_n321 +- - 0 =DBelt3 +- - 1 =DBelt3$_n312_n318$true +.mv DBelt2$_n312$raw_n322 2 E F +.names DBelt2$_n312_n317$true DBelt2 _n312 DBelt2$_n312$raw_n322 +- - 0 =DBelt2 +- - 1 =DBelt2$_n312_n317$true +.mv DBelt1$_n312$raw_n323 2 E F +.names DBelt1$_n312_n316$true DBelt1 _n312 DBelt1$_n312$raw_n323 +- - 0 =DBelt1 +- - 1 =DBelt1$_n312_n316$true +.mv DBelt0$_n312$raw_n324 2 E F +.names DBelt0$_n312_n315$true DBelt0 _n312 DBelt0$_n312$raw_n324 +- - 0 =DBelt0 +- - 1 =DBelt0$_n312_n315$true +.mv _n326 2 E F +.names _n326 +E +# DBelt3 == 0 +.names DBelt3$_n312$raw_n321 _n326 _n325 +.def 0 +- =DBelt3$_n312$raw_n321 1 +.mv _n328 2 Y N +.names _n328 +Y +# PieceOutArm == 0 +.names PieceOutArm _n328 _n327 +.def 0 +- =PieceOutArm 1 +# DBelt3 == 0 && PieceOutArm == 0 +.names _n325 _n327 _n329 +.def 0 +1 1 1 +.mv _n32b 2 Y N +.names _n32b +Y +# DBReady == 0 +.names DBReady _n32b _n32a +.def 0 +- =DBReady 1 +# DBelt3 == 0 && PieceOutArm == 0 && DBReady == 0 +.names _n329 _n32a _n32c +.def 0 +1 1 1 +.names _n32c _n32d +- =_n32c +# DBelt3 = 1 +.mv DBelt3$_n32c_n32e$true 2 E F +.names DBelt3$_n32c_n32e$true +F +# if/else (DBelt3 == 0 && PieceOutArm == 0 && DBReady == 0) +.mv DBelt3$_n32c$raw_n32f 2 E F +.names DBelt3$_n32c_n32e$true DBelt3$_n312$raw_n321 _n32c DBelt3$_n32c$raw_n32f +- - 0 =DBelt3$_n312$raw_n321 +- - 1 =DBelt3$_n32c_n32e$true +.mv _n340 2 Y N +.names _n340 +Y +# PieceGrabbedFromDB == 0 +.names PieceGrabbedFromDB _n340 _n33f +.def 0 +- =PieceGrabbedFromDB 1 +.names _n33f _n341 +- =_n33f +# DBelt0 = 0 +.mv DBelt0$_n33f_n342$true 2 E F +.names DBelt0$_n33f_n342$true +E +# if/else (PieceGrabbedFromDB == 0) +.mv DBelt0$_n33f$raw_n346 2 E F +.names DBelt0$_n33f_n342$true DBelt0$_n312$raw_n324 _n33f DBelt0$_n33f$raw_n346 +- - 0 =DBelt0$_n312$raw_n324 +- - 1 =DBelt0$_n33f_n342$true +# conflict arbitrators +.names _n314 _n32d _n353 +.def 0 + 1 - 1 + - 1 1 +.mv _n354 2 E F +.names _n353 DBelt3$_n32c$raw_n32f DBelt3 _n354 +1 - - =DBelt3$_n32c$raw_n32f +0 - - =DBelt3 +.names _n314 _n359 +.def 0 + 1 1 +.mv _n35a 2 E F +.names _n359 DBelt2$_n312$raw_n322 DBelt2 _n35a +1 - - =DBelt2$_n312$raw_n322 +0 - - =DBelt2 +.names _n314 _n35f +.def 0 + 1 1 +.mv _n360 2 E F +.names _n35f DBelt1$_n312$raw_n323 DBelt1 _n360 +1 - - =DBelt1$_n312$raw_n323 +0 - - =DBelt1 +.names _n314 _n341 _n365 +.def 0 + 1 - 1 + - 1 1 +.mv _n366 2 E F +.names _n365 DBelt0$_n33f$raw_n346 DBelt0 _n366 +1 - - =DBelt0$_n33f$raw_n346 +0 - - =DBelt0 +# non-blocking assignments +# latches +.r DBelt3$raw_n310 DBelt3 +- =DBelt3$raw_n310 +.latch _n354 DBelt3 +.r DBelt2$raw_n30e DBelt2 +- =DBelt2$raw_n30e +.latch _n35a DBelt2 +.r DBelt1$raw_n30c DBelt1 +- =DBelt1$raw_n30c +.latch _n360 DBelt1 +.r DBelt0$raw_n30b DBelt0 +- =DBelt0$raw_n30b +.latch _n366 DBelt0 +# quasi-continuous assignment +.end + + +.model DepositBeltCNTR +# I/O ports +.inputs PieceGrabbedFromDB +.inputs DBelt3 +.inputs DBelt2 +.inputs DBelt1 +.inputs DBelt0 +.outputs PieceOutDB +.inputs PieceOutArm +.outputs DBReady +.outputs DBMotorSwitch +.mv PieceGrabbedFromDB 2 Y N +.mv DBelt3 2 E F +.mv DBelt2 2 E F +.mv DBelt1 2 E F +.mv DBelt0 2 E F +.mv PieceOutDB 2 Y N +.mv PieceOutArm 2 Y N +.mv DBReady 2 Y N +.mv DBMotorSwitch 2 on off +# DBMotorSwitch = 1 +.mv DBMotorSwitch$raw_n36b 2 on off +.names DBMotorSwitch$raw_n36b +off +# DBReady = 1 +.mv DBReady$raw_n36c 2 Y N +.names DBReady$raw_n36c +N +# PieceOutDB = 1 +.mv PieceOutDB$raw_n36d 2 Y N +.names PieceOutDB$raw_n36d +N +# non-blocking assignments for initial +.mv _n36f 2 E F +.names _n36f +F +# DBelt0 == 1 +.names DBelt0 _n36f _n36e +.def 0 +- =DBelt0 1 +.mv _n371 2 Y N +.names _n371 +N +# PieceOutDB == 1 +.names PieceOutDB _n371 _n370 +.def 0 +- =PieceOutDB 1 +# DBelt0 == 1 && PieceOutDB == 1 +.names _n36e _n370 _n372 +.def 0 +1 1 1 +.mv _n374 2 Y N +.names _n374 +N +# PieceGrabbedFromDB == 1 +.names PieceGrabbedFromDB _n374 _n373 +.def 0 +- =PieceGrabbedFromDB 1 +# DBelt0 == 1 && PieceOutDB == 1 && PieceGrabbedFromDB == 1 +.names _n372 _n373 _n375 +.def 0 +1 1 1 +.mv _n377 2 E F +.names _n377 +E +# DBelt0 == 0 +.names DBelt0 _n377 _n376 +.def 0 +- =DBelt0 1 +.mv _n379 2 E F +.names _n379 +F +# DBelt1 == 1 +.names DBelt1 _n379 _n378 +.def 0 +- =DBelt1 1 +# DBelt0 == 0 && DBelt1 == 1 +.names _n376 _n378 _n37a +.def 0 +1 1 1 +.mv _n37c 2 on off +.names _n37c +on +# DBMotorSwitch == 0 +.names DBMotorSwitch _n37c _n37b +.def 0 +- =DBMotorSwitch 1 +# DBelt0 == 0 && DBelt1 == 1 && DBMotorSwitch == 0 +.names _n37a _n37b _n37d +.def 0 +1 1 1 +.mv _n37f 2 Y N +.names _n37f +N +# PieceOutDB == 1 +.names PieceOutDB _n37f _n37e +.def 0 +- =PieceOutDB 1 +# DBelt0 == 0 && DBelt1 == 1 && DBMotorSwitch == 0 && PieceOutDB == 1 +.names _n37d _n37e _n380 +.def 0 +1 1 1 +.mv _n382 2 Y N +.names _n382 +N +# PieceGrabbedFromDB == 1 +.names PieceGrabbedFromDB _n382 _n381 +.def 0 +- =PieceGrabbedFromDB 1 +# DBelt0 == 0 && DBelt1 == 1 && DBMotorSwitch == 0 && PieceOutDB == 1 && PieceGrabbedFromDB == 1 +.names _n380 _n381 _n383 +.def 0 +1 1 1 +# (DBelt0 == 1 && PieceOutDB == 1 && PieceGrabbedFromDB == 1) || (DBelt0 == 0 && DBelt1 == 1 && DBMotorSwitch == 0 && PieceOutDB == 1 && PieceGrabbedFromDB == 1) +.names _n375 _n383 _n384 +.def 1 +0 0 0 +.names _n384 _n385 +- =_n384 +# PieceOutDB = 0 +.mv PieceOutDB$_n384_n386$true 2 Y N +.names PieceOutDB$_n384_n386$true +Y +# if/else ((DBelt0 == 1 && PieceOutDB == 1 && PieceGrabbedFromDB == 1) || (DBelt0 == 0 && DBelt1 == 1 && DBMotorSwitch == 0 && PieceOutDB == 1 && PieceGrabbedFromDB == 1)) +.mv PieceOutDB$_n384$raw_n389 2 Y N +.names PieceOutDB$_n384_n386$true PieceOutDB _n384 PieceOutDB$_n384$raw_n389 +- - 0 =PieceOutDB +- - 1 =PieceOutDB$_n384_n386$true +.mv _n38b 2 Y N +.names _n38b +Y +# PieceOutDB == 0 +.names PieceOutDB$_n384$raw_n389 _n38b _n38a +.def 0 +- =PieceOutDB$_n384$raw_n389 1 +.mv _n38d 2 Y N +.names _n38d +Y +# PieceGrabbedFromDB == 0 +.names PieceGrabbedFromDB _n38d _n38c +.def 0 +- =PieceGrabbedFromDB 1 +# PieceOutDB == 0 && PieceGrabbedFromDB == 0 +.names _n38a _n38c _n38e +.def 0 +1 1 1 +.names _n38e _n38f +- =_n38e +# PieceOutDB = 1 +.mv PieceOutDB$_n38e_n390$true 2 Y N +.names PieceOutDB$_n38e_n390$true +N +# if/else (PieceOutDB == 0 && PieceGrabbedFromDB == 0) +.mv PieceOutDB$_n38e$raw_n391 2 Y N +.names PieceOutDB$_n38e_n390$true PieceOutDB$_n384$raw_n389 _n38e PieceOutDB$_n38e$raw_n391 +- - 0 =PieceOutDB$_n384$raw_n389 +- - 1 =PieceOutDB$_n38e_n390$true +.mv _n396 2 E F +.names _n396 +E +# DBelt3 == 0 +.names DBelt3 _n396 _n395 +.def 0 +- =DBelt3 1 +.mv _n398 2 Y N +.names _n398 +N +# PieceOutArm == 1 +.names PieceOutArm _n398 _n397 +.def 0 +- =PieceOutArm 1 +# DBelt3 == 0 && PieceOutArm == 1 +.names _n395 _n397 _n399 +.def 0 +1 1 1 +.mv _n39b 2 Y N +.names _n39b +N +# DBReady == 1 +.names DBReady _n39b _n39a +.def 0 +- =DBReady 1 +# DBelt3 == 0 && PieceOutArm == 1 && DBReady == 1 +.names _n399 _n39a _n39c +.def 0 +1 1 1 +.names _n39c _n39d +- =_n39c +# DBReady = 0 +.mv DBReady$_n39c_n39e$true 2 Y N +.names DBReady$_n39c_n39e$true +Y +# if/else (DBelt3 == 0 && PieceOutArm == 1 && DBReady == 1) +.mv DBReady$_n39c$raw_n3a4 2 Y N +.names DBReady$_n39c_n39e$true DBReady _n39c DBReady$_n39c$raw_n3a4 +- - 0 =DBReady +- - 1 =DBReady$_n39c_n39e$true +.mv _n3a7 2 Y N +.names _n3a7 +Y +# PieceOutArm == 0 +.names PieceOutArm _n3a7 _n3a6 +.def 0 +- =PieceOutArm 1 +.mv _n3a9 2 Y N +.names _n3a9 +Y +# DBReady == 0 +.names DBReady$_n39c$raw_n3a4 _n3a9 _n3a8 +.def 0 +- =DBReady$_n39c$raw_n3a4 1 +# PieceOutArm == 0 && DBReady == 0 +.names _n3a6 _n3a8 _n3aa +.def 0 +1 1 1 +.names _n3aa _n3ab +- =_n3aa +# DBReady = 1 +.mv DBReady$_n3aa_n3ac$true 2 Y N +.names DBReady$_n3aa_n3ac$true +N +# DBMotorSwitch = 0 +.mv DBMotorSwitch$_n3aa_n3ad$true 2 on off +.names DBMotorSwitch$_n3aa_n3ad$true +on +# if/else (PieceOutArm == 0 && DBReady == 0) +.mv DBReady$_n3aa$raw_n3b0 2 Y N +.names DBReady$_n3aa_n3ac$true DBReady$_n39c$raw_n3a4 _n3aa DBReady$_n3aa$raw_n3b0 +- - 0 =DBReady$_n39c$raw_n3a4 +- - 1 =DBReady$_n3aa_n3ac$true +.mv DBMotorSwitch$_n3aa$raw_n3b5 2 on off +.names DBMotorSwitch$_n3aa_n3ad$true DBMotorSwitch _n3aa DBMotorSwitch$_n3aa$raw_n3b5 +- - 0 =DBMotorSwitch +- - 1 =DBMotorSwitch$_n3aa_n3ad$true +.mv _n3ba 2 E F +.names _n3ba +F +# DBelt0 == 1 +.names DBelt0 _n3ba _n3b9 +.def 0 +- =DBelt0 1 +.names _n3b9 _n3bb +- =_n3b9 +# DBMotorSwitch = 1 +.mv DBMotorSwitch$_n3b9_n3bc$true 2 on off +.names DBMotorSwitch$_n3b9_n3bc$true +off +# if/else (DBelt0 == 1) +.mv DBMotorSwitch$_n3b9$raw_n3bf 2 on off +.names DBMotorSwitch$_n3b9_n3bc$true DBMotorSwitch$_n3aa$raw_n3b5 _n3b9 DBMotorSwitch$_n3b9$raw_n3bf +- - 0 =DBMotorSwitch$_n3aa$raw_n3b5 +- - 1 =DBMotorSwitch$_n3b9_n3bc$true +.mv _n3ca 2 E F +.names _n3ca +E +# DBelt0 == 0 +.names DBelt0 _n3ca _n3c9 +.def 0 +- =DBelt0 1 +.mv _n3cc 2 on off +.names _n3cc +off +# DBMotorSwitch == 1 +.names DBMotorSwitch$_n3b9$raw_n3bf _n3cc _n3cb +.def 0 +- =DBMotorSwitch$_n3b9$raw_n3bf 1 +# DBelt0 == 0 && DBMotorSwitch == 1 +.names _n3c9 _n3cb _n3cd +.def 0 +1 1 1 +.mv _n3cf 2 E F +.names _n3cf +F +# DBelt1 == 1 +.names DBelt1 _n3cf _n3ce +.def 0 +- =DBelt1 1 +.mv _n3d1 2 E F +.names _n3d1 +F +# DBelt2 == 1 +.names DBelt2 _n3d1 _n3d0 +.def 0 +- =DBelt2 1 +# DBelt1 == 1 || DBelt2 == 1 +.names _n3ce _n3d0 _n3d2 +.def 1 +0 0 0 +.mv _n3d4 2 E F +.names _n3d4 +F +# DBelt3 == 1 +.names DBelt3 _n3d4 _n3d3 +.def 0 +- =DBelt3 1 +# DBelt1 == 1 || DBelt2 == 1 || DBelt3 == 1 +.names _n3d2 _n3d3 _n3d5 +.def 1 +0 0 0 +# DBelt0 == 0 && DBMotorSwitch == 1 && (DBelt1 == 1 || DBelt2 == 1 || DBelt3 == 1) +.names _n3cd _n3d5 _n3d6 +.def 0 +1 1 1 +.names _n3d6 _n3d7 +- =_n3d6 +# DBMotorSwitch = 0 +.mv DBMotorSwitch$_n3d6_n3d8$true 2 on off +.names DBMotorSwitch$_n3d6_n3d8$true +on +.mv _n3da 2 E F +.names _n3da +E +# DBelt0 == 0 +.names DBelt0 _n3da _n3d9 +.def 0 +- =DBelt0 1 +.mv _n3dc 2 on off +.names _n3dc +on +# DBMotorSwitch == 0 +.names DBMotorSwitch$_n3b9$raw_n3bf _n3dc _n3db +.def 0 +- =DBMotorSwitch$_n3b9$raw_n3bf 1 +# DBelt0 == 0 && DBMotorSwitch == 0 +.names _n3d9 _n3db _n3dd +.def 0 +1 1 1 +.mv _n3df 2 E F +.names _n3df +F +# DBelt1 == 1 +.names DBelt1 _n3df _n3de +.def 0 +- =DBelt1 1 +# DBelt0 == 0 && DBMotorSwitch == 0 && DBelt1 == 1 +.names _n3dd _n3de _n3e0 +.def 0 +1 1 1 +.names _n3e0 _n3e1 +- =_n3e0 +# DBMotorSwitch = 1 +.mv DBMotorSwitch$_n3e0_n3e2$true 2 on off +.names DBMotorSwitch$_n3e0_n3e2$true +off +# if/else (DBelt0 == 0 && DBMotorSwitch == 0 && DBelt1 == 1) +.mv DBMotorSwitch$_n3e0$raw_n3e4 2 on off +.names DBMotorSwitch$_n3e0_n3e2$true DBMotorSwitch$_n3b9$raw_n3bf _n3e0 DBMotorSwitch$_n3e0$raw_n3e4 +- - 0 =DBMotorSwitch$_n3b9$raw_n3bf +- - 1 =DBMotorSwitch$_n3e0_n3e2$true +# if/else (DBelt0 == 0 && DBMotorSwitch == 1 && (DBelt1 == 1 || DBelt2 == 1 || DBelt3 == 1)) +.mv DBMotorSwitch$_n3d6$raw_n3f1 2 on off +.names DBMotorSwitch$_n3d6_n3d8$true DBMotorSwitch$_n3e0$raw_n3e4 _n3d6 DBMotorSwitch$_n3d6$raw_n3f1 +- - 0 =DBMotorSwitch$_n3e0$raw_n3e4 +- - 1 =DBMotorSwitch$_n3d6_n3d8$true +# conflict arbitrators +.names _n385 _n38f _n3fb +.def 0 + 1 - 1 + - 1 1 +.mv _n3fc 2 Y N +.names _n3fb PieceOutDB$_n38e$raw_n391 PieceOutDB _n3fc +1 - - =PieceOutDB$_n38e$raw_n391 +0 - - =PieceOutDB +.names _n39d _n3ab _n400 +.def 0 + 1 - 1 + - 1 1 +.mv _n401 2 Y N +.names _n400 DBReady$_n3aa$raw_n3b0 DBReady _n401 +1 - - =DBReady$_n3aa$raw_n3b0 +0 - - =DBReady +.names _n3ab _n3bb _n3d7 _n3e1 _n405 +.def 0 + 1 - - - 1 + - 1 - - 1 + - - 1 - 1 + - - 0 1 1 +.mv _n406 2 on off +.names _n405 DBMotorSwitch$_n3d6$raw_n3f1 DBMotorSwitch _n406 +1 - - =DBMotorSwitch$_n3d6$raw_n3f1 +0 - - =DBMotorSwitch +# non-blocking assignments +# latches +.r PieceOutDB$raw_n36d PieceOutDB +- =PieceOutDB$raw_n36d +.latch _n3fc PieceOutDB +.r DBMotorSwitch$raw_n36b DBMotorSwitch +- =DBMotorSwitch$raw_n36b +.latch _n406 DBMotorSwitch +.r DBReady$raw_n36c DBReady +- =DBReady$raw_n36c +.latch _n401 DBReady +# quasi-continuous assignment +.end + + +.model FeedBelt +# I/O ports +.outputs FBelt3 +.outputs FBelt2 +.inputs FBReady +.inputs PieceReleasedOnFB +.outputs FBelt1 +.outputs FBelt0 +.inputs PieceGrabbedFromFB +.inputs FBMotorSwitch +.mv FBelt3 2 E F +.mv FBelt2 2 E F +.mv FBReady 2 Y N +.mv PieceReleasedOnFB 2 Y N +.mv FBelt1 2 E F +.mv FBelt0 2 E F +.mv PieceGrabbedFromFB 2 Y N +.mv FBMotorSwitch 2 on off +# FBelt0 = $NDset ( 0,1 ) +.mv FBelt0$raw_n40a 2 E F +.mv FBelt0$raw_n40a$initial$_n40b 2 E F +.names FBelt0$raw_n40a$initial$_n40b +E +F +.names FBelt0$raw_n40a$initial$_n40b FBelt0$raw_n40a +- =FBelt0$raw_n40a$initial$_n40b +# FBelt1 = $NDset ( 0,1 ) +.mv FBelt1$raw_n40c 2 E F +.mv FBelt1$raw_n40c$initial$_n40d 2 E F +.names FBelt1$raw_n40c$initial$_n40d +E +F +.names FBelt1$raw_n40c$initial$_n40d FBelt1$raw_n40c +- =FBelt1$raw_n40c$initial$_n40d +# FBelt2 = $NDset ( 0,1 ) +.mv FBelt2$raw_n40e 2 E F +.mv FBelt2$raw_n40e$initial$_n40f 2 E F +.names FBelt2$raw_n40e$initial$_n40f +E +F +.names FBelt2$raw_n40e$initial$_n40f FBelt2$raw_n40e +- =FBelt2$raw_n40e$initial$_n40f +# FBelt3 = $NDset ( 0,1 ) +.mv FBelt3$raw_n410 2 E F +.mv FBelt3$raw_n410$initial$_n411 2 E F +.names FBelt3$raw_n410$initial$_n411 +E +F +.names FBelt3$raw_n410$initial$_n411 FBelt3$raw_n410 +- =FBelt3$raw_n410$initial$_n411 +# non-blocking assignments for initial +.mv _n413 2 on off +.names _n413 +on +# FBMotorSwitch == 0 +.names FBMotorSwitch _n413 _n412 +.def 0 +- =FBMotorSwitch 1 +.names _n412 _n414 +- =_n412 +# FBelt0 = FBelt1 +.mv FBelt0$_n412_n415$true 2 E F +.names FBelt1 FBelt0$_n412_n415$true +- =FBelt1 +# FBelt1 = FBelt2 +.mv FBelt1$_n412_n416$true 2 E F +.names FBelt2 FBelt1$_n412_n416$true +- =FBelt2 +# FBelt2 = FBelt3 +.mv FBelt2$_n412_n417$true 2 E F +.names FBelt3 FBelt2$_n412_n417$true +- =FBelt3 +# FBelt3 = 0 +.mv FBelt3$_n412_n418$true 2 E F +.names FBelt3$_n412_n418$true +E +# if/else (FBMotorSwitch == 0) +.mv FBelt3$_n412$raw_n421 2 E F +.names FBelt3$_n412_n418$true FBelt3 _n412 FBelt3$_n412$raw_n421 +- - 0 =FBelt3 +- - 1 =FBelt3$_n412_n418$true +.mv FBelt2$_n412$raw_n422 2 E F +.names FBelt2$_n412_n417$true FBelt2 _n412 FBelt2$_n412$raw_n422 +- - 0 =FBelt2 +- - 1 =FBelt2$_n412_n417$true +.mv FBelt1$_n412$raw_n423 2 E F +.names FBelt1$_n412_n416$true FBelt1 _n412 FBelt1$_n412$raw_n423 +- - 0 =FBelt1 +- - 1 =FBelt1$_n412_n416$true +.mv FBelt0$_n412$raw_n424 2 E F +.names FBelt0$_n412_n415$true FBelt0 _n412 FBelt0$_n412$raw_n424 +- - 0 =FBelt0 +- - 1 =FBelt0$_n412_n415$true +.mv _n426 2 E F +.names _n426 +E +# FBelt3 == 0 +.names FBelt3$_n412$raw_n421 _n426 _n425 +.def 0 +- =FBelt3$_n412$raw_n421 1 +.mv _n428 2 Y N +.names _n428 +Y +# PieceReleasedOnFB == 0 +.names PieceReleasedOnFB _n428 _n427 +.def 0 +- =PieceReleasedOnFB 1 +# FBelt3 == 0 && PieceReleasedOnFB == 0 +.names _n425 _n427 _n429 +.def 0 +1 1 1 +.mv _n42b 2 Y N +.names _n42b +Y +# FBReady == 0 +.names FBReady _n42b _n42a +.def 0 +- =FBReady 1 +# FBelt3 == 0 && PieceReleasedOnFB == 0 && FBReady == 0 +.names _n429 _n42a _n42c +.def 0 +1 1 1 +.names _n42c _n42d +- =_n42c +# FBelt3 = 1 +.mv FBelt3$_n42c_n42e$true 2 E F +.names FBelt3$_n42c_n42e$true +F +# if/else (FBelt3 == 0 && PieceReleasedOnFB == 0 && FBReady == 0) +.mv FBelt3$_n42c$raw_n42f 2 E F +.names FBelt3$_n42c_n42e$true FBelt3$_n412$raw_n421 _n42c FBelt3$_n42c$raw_n42f +- - 0 =FBelt3$_n412$raw_n421 +- - 1 =FBelt3$_n42c_n42e$true +.mv _n440 2 Y N +.names _n440 +Y +# PieceGrabbedFromFB == 0 +.names PieceGrabbedFromFB _n440 _n43f +.def 0 +- =PieceGrabbedFromFB 1 +.names _n43f _n441 +- =_n43f +# FBelt0 = 0 +.mv FBelt0$_n43f_n442$true 2 E F +.names FBelt0$_n43f_n442$true +E +# if/else (PieceGrabbedFromFB == 0) +.mv FBelt0$_n43f$raw_n446 2 E F +.names FBelt0$_n43f_n442$true FBelt0$_n412$raw_n424 _n43f FBelt0$_n43f$raw_n446 +- - 0 =FBelt0$_n412$raw_n424 +- - 1 =FBelt0$_n43f_n442$true +# conflict arbitrators +.names _n414 _n42d _n453 +.def 0 + 1 - 1 + - 1 1 +.mv _n454 2 E F +.names _n453 FBelt3$_n42c$raw_n42f FBelt3 _n454 +1 - - =FBelt3$_n42c$raw_n42f +0 - - =FBelt3 +.names _n414 _n459 +.def 0 + 1 1 +.mv _n45a 2 E F +.names _n459 FBelt2$_n412$raw_n422 FBelt2 _n45a +1 - - =FBelt2$_n412$raw_n422 +0 - - =FBelt2 +.names _n414 _n45f +.def 0 + 1 1 +.mv _n460 2 E F +.names _n45f FBelt1$_n412$raw_n423 FBelt1 _n460 +1 - - =FBelt1$_n412$raw_n423 +0 - - =FBelt1 +.names _n414 _n441 _n465 +.def 0 + 1 - 1 + - 1 1 +.mv _n466 2 E F +.names _n465 FBelt0$_n43f$raw_n446 FBelt0 _n466 +1 - - =FBelt0$_n43f$raw_n446 +0 - - =FBelt0 +# non-blocking assignments +# latches +.r FBelt3$raw_n410 FBelt3 +- =FBelt3$raw_n410 +.latch _n454 FBelt3 +.r FBelt2$raw_n40e FBelt2 +- =FBelt2$raw_n40e +.latch _n45a FBelt2 +.r FBelt1$raw_n40c FBelt1 +- =FBelt1$raw_n40c +.latch _n460 FBelt1 +.r FBelt0$raw_n40a FBelt0 +- =FBelt0$raw_n40a +.latch _n466 FBelt0 +# quasi-continuous assignment +.end + + +.model FeedBeltCNTR +# I/O ports +.inputs FBelt3 +.outputs FBReady +.inputs PieceReleasedOnFB +.inputs FBelt2 +.inputs FBelt1 +.inputs FBelt0 +.outputs PieceOutFB +.outputs FBMotorSwitch +.inputs PieceGrabbedFromFB +.mv FBelt3 2 E F +.mv FBReady 2 Y N +.mv PieceReleasedOnFB 2 Y N +.mv FBelt2 2 E F +.mv FBelt1 2 E F +.mv FBelt0 2 E F +.mv PieceOutFB 2 Y N +.mv FBMotorSwitch 2 on off +.mv PieceGrabbedFromFB 2 Y N +# FBMotorSwitch = 1 +.mv FBMotorSwitch$raw_n46b 2 on off +.names FBMotorSwitch$raw_n46b +off +# FBReady = 1 +.mv FBReady$raw_n46c 2 Y N +.names FBReady$raw_n46c +N +# PieceOutFB = 1 +.mv PieceOutFB$raw_n46d 2 Y N +.names PieceOutFB$raw_n46d +N +# non-blocking assignments for initial +.mv _n46f 2 E F +.names _n46f +F +# FBelt0 == 1 +.names FBelt0 _n46f _n46e +.def 0 +- =FBelt0 1 +.mv _n471 2 Y N +.names _n471 +N +# PieceOutFB == 1 +.names PieceOutFB _n471 _n470 +.def 0 +- =PieceOutFB 1 +# FBelt0 == 1 && PieceOutFB == 1 +.names _n46e _n470 _n472 +.def 0 +1 1 1 +.mv _n474 2 Y N +.names _n474 +N +# PieceGrabbedFromFB == 1 +.names PieceGrabbedFromFB _n474 _n473 +.def 0 +- =PieceGrabbedFromFB 1 +# FBelt0 == 1 && PieceOutFB == 1 && PieceGrabbedFromFB == 1 +.names _n472 _n473 _n475 +.def 0 +1 1 1 +.mv _n477 2 E F +.names _n477 +E +# FBelt0 == 0 +.names FBelt0 _n477 _n476 +.def 0 +- =FBelt0 1 +.mv _n479 2 E F +.names _n479 +F +# FBelt1 == 1 +.names FBelt1 _n479 _n478 +.def 0 +- =FBelt1 1 +# FBelt0 == 0 && FBelt1 == 1 +.names _n476 _n478 _n47a +.def 0 +1 1 1 +.mv _n47c 2 on off +.names _n47c +on +# FBMotorSwitch == 0 +.names FBMotorSwitch _n47c _n47b +.def 0 +- =FBMotorSwitch 1 +# FBelt0 == 0 && FBelt1 == 1 && FBMotorSwitch == 0 +.names _n47a _n47b _n47d +.def 0 +1 1 1 +.mv _n47f 2 Y N +.names _n47f +N +# PieceOutFB == 1 +.names PieceOutFB _n47f _n47e +.def 0 +- =PieceOutFB 1 +# FBelt0 == 0 && FBelt1 == 1 && FBMotorSwitch == 0 && PieceOutFB == 1 +.names _n47d _n47e _n480 +.def 0 +1 1 1 +.mv _n482 2 Y N +.names _n482 +N +# PieceGrabbedFromFB == 1 +.names PieceGrabbedFromFB _n482 _n481 +.def 0 +- =PieceGrabbedFromFB 1 +# FBelt0 == 0 && FBelt1 == 1 && FBMotorSwitch == 0 && PieceOutFB == 1 && PieceGrabbedFromFB == 1 +.names _n480 _n481 _n483 +.def 0 +1 1 1 +# (FBelt0 == 1 && PieceOutFB == 1 && PieceGrabbedFromFB == 1) || (FBelt0 == 0 && FBelt1 == 1 && FBMotorSwitch == 0 && PieceOutFB == 1 && PieceGrabbedFromFB == 1) +.names _n475 _n483 _n484 +.def 1 +0 0 0 +.names _n484 _n485 +- =_n484 +# PieceOutFB = 0 +.mv PieceOutFB$_n484_n486$true 2 Y N +.names PieceOutFB$_n484_n486$true +Y +# if/else ((FBelt0 == 1 && PieceOutFB == 1 && PieceGrabbedFromFB == 1) || (FBelt0 == 0 && FBelt1 == 1 && FBMotorSwitch == 0 && PieceOutFB == 1 && PieceGrabbedFromFB == 1)) +.mv PieceOutFB$_n484$raw_n489 2 Y N +.names PieceOutFB$_n484_n486$true PieceOutFB _n484 PieceOutFB$_n484$raw_n489 +- - 0 =PieceOutFB +- - 1 =PieceOutFB$_n484_n486$true +.mv _n48b 2 Y N +.names _n48b +Y +# PieceOutFB == 0 +.names PieceOutFB$_n484$raw_n489 _n48b _n48a +.def 0 +- =PieceOutFB$_n484$raw_n489 1 +.mv _n48d 2 Y N +.names _n48d +Y +# PieceGrabbedFromFB == 0 +.names PieceGrabbedFromFB _n48d _n48c +.def 0 +- =PieceGrabbedFromFB 1 +# PieceOutFB == 0 && PieceGrabbedFromFB == 0 +.names _n48a _n48c _n48e +.def 0 +1 1 1 +.names _n48e _n48f +- =_n48e +# PieceOutFB = 1 +.mv PieceOutFB$_n48e_n490$true 2 Y N +.names PieceOutFB$_n48e_n490$true +N +# if/else (PieceOutFB == 0 && PieceGrabbedFromFB == 0) +.mv PieceOutFB$_n48e$raw_n491 2 Y N +.names PieceOutFB$_n48e_n490$true PieceOutFB$_n484$raw_n489 _n48e PieceOutFB$_n48e$raw_n491 +- - 0 =PieceOutFB$_n484$raw_n489 +- - 1 =PieceOutFB$_n48e_n490$true +.mv _n496 2 E F +.names _n496 +E +# FBelt3 == 0 +.names FBelt3 _n496 _n495 +.def 0 +- =FBelt3 1 +.mv _n498 2 Y N +.names _n498 +N +# PieceReleasedOnFB == 1 +.names PieceReleasedOnFB _n498 _n497 +.def 0 +- =PieceReleasedOnFB 1 +# FBelt3 == 0 && PieceReleasedOnFB == 1 +.names _n495 _n497 _n499 +.def 0 +1 1 1 +.mv _n49b 2 Y N +.names _n49b +N +# FBReady == 1 +.names FBReady _n49b _n49a +.def 0 +- =FBReady 1 +# FBelt3 == 0 && PieceReleasedOnFB == 1 && FBReady == 1 +.names _n499 _n49a _n49c +.def 0 +1 1 1 +.names _n49c _n49d +- =_n49c +# FBReady = 0 +.mv FBReady$_n49c_n49e$true 2 Y N +.names FBReady$_n49c_n49e$true +Y +# if/else (FBelt3 == 0 && PieceReleasedOnFB == 1 && FBReady == 1) +.mv FBReady$_n49c$raw_n4a3 2 Y N +.names FBReady$_n49c_n49e$true FBReady _n49c FBReady$_n49c$raw_n4a3 +- - 0 =FBReady +- - 1 =FBReady$_n49c_n49e$true +.mv _n4a7 2 Y N +.names _n4a7 +Y +# PieceReleasedOnFB == 0 +.names PieceReleasedOnFB _n4a7 _n4a6 +.def 0 +- =PieceReleasedOnFB 1 +.mv _n4a9 2 Y N +.names _n4a9 +Y +# FBReady == 0 +.names FBReady$_n49c$raw_n4a3 _n4a9 _n4a8 +.def 0 +- =FBReady$_n49c$raw_n4a3 1 +# PieceReleasedOnFB == 0 && FBReady == 0 +.names _n4a6 _n4a8 _n4aa +.def 0 +1 1 1 +.names _n4aa _n4ab +- =_n4aa +# FBReady = 1 +.mv FBReady$_n4aa_n4ac$true 2 Y N +.names FBReady$_n4aa_n4ac$true +N +# FBMotorSwitch = 0 +.mv FBMotorSwitch$_n4aa_n4ad$true 2 on off +.names FBMotorSwitch$_n4aa_n4ad$true +on +# if/else (PieceReleasedOnFB == 0 && FBReady == 0) +.mv FBReady$_n4aa$raw_n4ae 2 Y N +.names FBReady$_n4aa_n4ac$true FBReady$_n49c$raw_n4a3 _n4aa FBReady$_n4aa$raw_n4ae +- - 0 =FBReady$_n49c$raw_n4a3 +- - 1 =FBReady$_n4aa_n4ac$true +.mv FBMotorSwitch$_n4aa$raw_n4b5 2 on off +.names FBMotorSwitch$_n4aa_n4ad$true FBMotorSwitch _n4aa FBMotorSwitch$_n4aa$raw_n4b5 +- - 0 =FBMotorSwitch +- - 1 =FBMotorSwitch$_n4aa_n4ad$true +.mv _n4ba 2 E F +.names _n4ba +F +# FBelt0 == 1 +.names FBelt0 _n4ba _n4b9 +.def 0 +- =FBelt0 1 +.names _n4b9 _n4bb +- =_n4b9 +# FBMotorSwitch = 1 +.mv FBMotorSwitch$_n4b9_n4bc$true 2 on off +.names FBMotorSwitch$_n4b9_n4bc$true +off +# if/else (FBelt0 == 1) +.mv FBMotorSwitch$_n4b9$raw_n4bf 2 on off +.names FBMotorSwitch$_n4b9_n4bc$true FBMotorSwitch$_n4aa$raw_n4b5 _n4b9 FBMotorSwitch$_n4b9$raw_n4bf +- - 0 =FBMotorSwitch$_n4aa$raw_n4b5 +- - 1 =FBMotorSwitch$_n4b9_n4bc$true +.mv _n4ca 2 E F +.names _n4ca +E +# FBelt0 == 0 +.names FBelt0 _n4ca _n4c9 +.def 0 +- =FBelt0 1 +.mv _n4cc 2 on off +.names _n4cc +off +# FBMotorSwitch == 1 +.names FBMotorSwitch$_n4b9$raw_n4bf _n4cc _n4cb +.def 0 +- =FBMotorSwitch$_n4b9$raw_n4bf 1 +# FBelt0 == 0 && FBMotorSwitch == 1 +.names _n4c9 _n4cb _n4cd +.def 0 +1 1 1 +.mv _n4cf 2 E F +.names _n4cf +F +# FBelt1 == 1 +.names FBelt1 _n4cf _n4ce +.def 0 +- =FBelt1 1 +.mv _n4d1 2 E F +.names _n4d1 +F +# FBelt2 == 1 +.names FBelt2 _n4d1 _n4d0 +.def 0 +- =FBelt2 1 +# FBelt1 == 1 || FBelt2 == 1 +.names _n4ce _n4d0 _n4d2 +.def 1 +0 0 0 +.mv _n4d4 2 E F +.names _n4d4 +F +# FBelt3 == 1 +.names FBelt3 _n4d4 _n4d3 +.def 0 +- =FBelt3 1 +# FBelt1 == 1 || FBelt2 == 1 || FBelt3 == 1 +.names _n4d2 _n4d3 _n4d5 +.def 1 +0 0 0 +# FBelt0 == 0 && FBMotorSwitch == 1 && (FBelt1 == 1 || FBelt2 == 1 || FBelt3 == 1) +.names _n4cd _n4d5 _n4d6 +.def 0 +1 1 1 +.names _n4d6 _n4d7 +- =_n4d6 +# FBMotorSwitch = 0 +.mv FBMotorSwitch$_n4d6_n4d8$true 2 on off +.names FBMotorSwitch$_n4d6_n4d8$true +on +.mv _n4da 2 E F +.names _n4da +E +# FBelt0 == 0 +.names FBelt0 _n4da _n4d9 +.def 0 +- =FBelt0 1 +.mv _n4dc 2 on off +.names _n4dc +on +# FBMotorSwitch == 0 +.names FBMotorSwitch$_n4b9$raw_n4bf _n4dc _n4db +.def 0 +- =FBMotorSwitch$_n4b9$raw_n4bf 1 +# FBelt0 == 0 && FBMotorSwitch == 0 +.names _n4d9 _n4db _n4dd +.def 0 +1 1 1 +.mv _n4df 2 E F +.names _n4df +F +# FBelt1 == 1 +.names FBelt1 _n4df _n4de +.def 0 +- =FBelt1 1 +# FBelt0 == 0 && FBMotorSwitch == 0 && FBelt1 == 1 +.names _n4dd _n4de _n4e0 +.def 0 +1 1 1 +.names _n4e0 _n4e1 +- =_n4e0 +# FBMotorSwitch = 1 +.mv FBMotorSwitch$_n4e0_n4e2$true 2 on off +.names FBMotorSwitch$_n4e0_n4e2$true +off +# if/else (FBelt0 == 0 && FBMotorSwitch == 0 && FBelt1 == 1) +.mv FBMotorSwitch$_n4e0$raw_n4e4 2 on off +.names FBMotorSwitch$_n4e0_n4e2$true FBMotorSwitch$_n4b9$raw_n4bf _n4e0 FBMotorSwitch$_n4e0$raw_n4e4 +- - 0 =FBMotorSwitch$_n4b9$raw_n4bf +- - 1 =FBMotorSwitch$_n4e0_n4e2$true +# if/else (FBelt0 == 0 && FBMotorSwitch == 1 && (FBelt1 == 1 || FBelt2 == 1 || FBelt3 == 1)) +.mv FBMotorSwitch$_n4d6$raw_n4f1 2 on off +.names FBMotorSwitch$_n4d6_n4d8$true FBMotorSwitch$_n4e0$raw_n4e4 _n4d6 FBMotorSwitch$_n4d6$raw_n4f1 +- - 0 =FBMotorSwitch$_n4e0$raw_n4e4 +- - 1 =FBMotorSwitch$_n4d6_n4d8$true +# conflict arbitrators +.names _n49d _n4ab _n4fb +.def 0 + 1 - 1 + - 1 1 +.mv _n4fc 2 Y N +.names _n4fb FBReady$_n4aa$raw_n4ae FBReady _n4fc +1 - - =FBReady$_n4aa$raw_n4ae +0 - - =FBReady +.names _n485 _n48f _n500 +.def 0 + 1 - 1 + - 1 1 +.mv _n501 2 Y N +.names _n500 PieceOutFB$_n48e$raw_n491 PieceOutFB _n501 +1 - - =PieceOutFB$_n48e$raw_n491 +0 - - =PieceOutFB +.names _n4ab _n4bb _n4d7 _n4e1 _n505 +.def 0 + 1 - - - 1 + - 1 - - 1 + - - 1 - 1 + - - 0 1 1 +.mv _n506 2 on off +.names _n505 FBMotorSwitch$_n4d6$raw_n4f1 FBMotorSwitch _n506 +1 - - =FBMotorSwitch$_n4d6$raw_n4f1 +0 - - =FBMotorSwitch +# non-blocking assignments +# latches +.r FBReady$raw_n46c FBReady +- =FBReady$raw_n46c +.latch _n4fc FBReady +.r FBMotorSwitch$raw_n46b FBMotorSwitch +- =FBMotorSwitch$raw_n46b +.latch _n506 FBMotorSwitch +.r PieceOutFB$raw_n46d PieceOutFB +- =PieceOutFB$raw_n46d +.latch _n501 PieceOutFB +# quasi-continuous assignment +.end + + +.model RotaryTable +# I/O ports +.outputs RTOnTop +.outputs RTOnArm +.outputs RTOnFB +.outputs RTOnBottom +.inputs RTVerticalMotor +.inputs RTRotaryMotor +.mv RTOnTop 2 Y N +.mv RTOnArm 2 Y N +.mv RTOnFB 2 Y N +.mv RTAngle 3 S SSE SE +.mv RTOnBottom 2 Y N +.mv RTVerticalMotor 3 GoUp GoDown Stop +.mv RTRotaryMotor 3 CWise Stop CCWise +.mv RTHight 3 Top Mid Bot +# assign RTOnFB = (RTAngle == S ) ? 0 : 1 +.mv RTOnFB$raw_n50a 2 Y N +.mv _n50c 3 S SSE SE +.names _n50c +S +# RTAngle == 0 +.names RTAngle _n50c _n50b +.def 0 +- =RTAngle 1 +.mv _n50d 2 Y N +.names _n50d +Y +.mv _n50e 2 Y N +.names _n50e +N +# (RTAngle == 0) ? 0 : 1 +.mv _n50f 2 Y N +.names _n50d _n50e _n50b _n50f +- - 0 =_n50e +- - 1 =_n50d +.names _n50f RTOnFB$raw_n50a +- =_n50f +# assign RTOnArm = (RTAngle == SE ) ? 0 : 1 +.mv RTOnArm$raw_n510 2 Y N +.mv _n512 3 S SSE SE +.names _n512 +SE +# RTAngle == 2 +.names RTAngle _n512 _n511 +.def 0 +- =RTAngle 1 +.mv _n513 2 Y N +.names _n513 +Y +.mv _n514 2 Y N +.names _n514 +N +# (RTAngle == 2) ? 0 : 1 +.mv _n515 2 Y N +.names _n513 _n514 _n511 _n515 +- - 0 =_n514 +- - 1 =_n513 +.names _n515 RTOnArm$raw_n510 +- =_n515 +# assign RTOnTop = (RTHight == Top ) ? 0 : 1 +.mv RTOnTop$raw_n516 2 Y N +.mv _n518 3 Top Mid Bot +.names _n518 +Top +# RTHight == 0 +.names RTHight _n518 _n517 +.def 0 +- =RTHight 1 +.mv _n519 2 Y N +.names _n519 +Y +.mv _n51a 2 Y N +.names _n51a +N +# (RTHight == 0) ? 0 : 1 +.mv _n51b 2 Y N +.names _n519 _n51a _n517 _n51b +- - 0 =_n51a +- - 1 =_n519 +.names _n51b RTOnTop$raw_n516 +- =_n51b +# assign RTOnBottom = (RTHight == Bot ) ? 0 : 1 +.mv RTOnBottom$raw_n51c 2 Y N +.mv _n51e 3 Top Mid Bot +.names _n51e +Bot +# RTHight == 2 +.names RTHight _n51e _n51d +.def 0 +- =RTHight 1 +.mv _n51f 2 Y N +.names _n51f +Y +.mv _n520 2 Y N +.names _n520 +N +# (RTHight == 2) ? 0 : 1 +.mv _n521 2 Y N +.names _n51f _n520 _n51d _n521 +- - 0 =_n520 +- - 1 =_n51f +.names _n521 RTOnBottom$raw_n51c +- =_n521 +# RTAngle = $NDset ( 0,1,2 ) +.mv RTAngle$raw_n522 3 S SSE SE +.mv RTAngle$raw_n522$initial$_n523 3 S SSE SE +.names RTAngle$raw_n522$initial$_n523 +S +SSE +SE +.names RTAngle$raw_n522$initial$_n523 RTAngle$raw_n522 +- =RTAngle$raw_n522$initial$_n523 +# RTHight = $NDset ( 0,1,2 ) +.mv RTHight$raw_n524 3 Top Mid Bot +.mv RTHight$raw_n524$initial$_n525 3 Top Mid Bot +.names RTHight$raw_n524$initial$_n525 +Top +Mid +Bot +.names RTHight$raw_n524$initial$_n525 RTHight$raw_n524 +- =RTHight$raw_n524$initial$_n525 +# non-blocking assignments for initial +.mv _n527 3 CWise Stop CCWise +.names _n527 +CWise +# RTRotaryMotor == 0 +.names RTRotaryMotor _n527 _n526 +.def 0 +- =RTRotaryMotor 1 +.names _n526 _n528 +- =_n526 +.mv _n52b 3 S SSE SE +.names _n52b +SE +.names RTAngle _n52b _n52a +.def 0 +- =RTAngle 1 +.names _n52a _n529 +1 1 +0 0 +# RTAngle = 1 +.mv RTAngle$_n529_n52c$true 3 S SSE SE +.names RTAngle$_n529_n52c$true +SSE +.mv _n52f 3 S SSE SE +.names _n52f +SSE +.names RTAngle _n52f _n52e +.def 0 +- =RTAngle 1 +.names _n52e _n52d +1 1 +0 0 +# RTAngle = 0 +.mv RTAngle$_n52d_n530$true 3 S SSE SE +.names RTAngle$_n52d_n530$true +S +# case (RTAngle ) +.mv RTAngle$_n52d$raw_n533 3 S SSE SE +.names RTAngle$_n52d_n530$true RTAngle _n52d RTAngle$_n52d$raw_n533 +- - 0 =RTAngle +- - 1 =RTAngle$_n52d_n530$true +.mv RTAngle$_n529$raw_n534 3 S SSE SE +.names RTAngle$_n529_n52c$true RTAngle$_n52d$raw_n533 _n529 RTAngle$_n529$raw_n534 +- - 0 =RTAngle$_n52d$raw_n533 +- - 1 =RTAngle$_n529_n52c$true +# if/else (RTRotaryMotor == 0) +.mv RTAngle$_n526$raw_n53a 3 S SSE SE +.names RTAngle$_n529$raw_n534 RTAngle _n526 RTAngle$_n526$raw_n53a +- - 0 =RTAngle +- - 1 =RTAngle$_n529$raw_n534 +.mv _n53c 3 CWise Stop CCWise +.names _n53c +CCWise +# RTRotaryMotor == 2 +.names RTRotaryMotor _n53c _n53b +.def 0 +- =RTRotaryMotor 1 +.names _n53b _n53d +- =_n53b +.mv _n540 3 S SSE SE +.names _n540 +S +.names RTAngle$_n526$raw_n53a _n540 _n53f +.def 0 +- =RTAngle$_n526$raw_n53a 1 +.names _n53f _n53e +1 1 +0 0 +# RTAngle = 1 +.mv RTAngle$_n53e_n541$true 3 S SSE SE +.names RTAngle$_n53e_n541$true +SSE +.mv _n544 3 S SSE SE +.names _n544 +SSE +.names RTAngle$_n526$raw_n53a _n544 _n543 +.def 0 +- =RTAngle$_n526$raw_n53a 1 +.names _n543 _n542 +1 1 +0 0 +# RTAngle = 2 +.mv RTAngle$_n542_n545$true 3 S SSE SE +.names RTAngle$_n542_n545$true +SE +# case (RTAngle ) +.mv RTAngle$_n542$raw_n546 3 S SSE SE +.names RTAngle$_n542_n545$true RTAngle$_n526$raw_n53a _n542 RTAngle$_n542$raw_n546 +- - 0 =RTAngle$_n526$raw_n53a +- - 1 =RTAngle$_n542_n545$true +.mv RTAngle$_n53e$raw_n54a 3 S SSE SE +.names RTAngle$_n53e_n541$true RTAngle$_n542$raw_n546 _n53e RTAngle$_n53e$raw_n54a +- - 0 =RTAngle$_n542$raw_n546 +- - 1 =RTAngle$_n53e_n541$true +# if/else (RTRotaryMotor == 2) +.mv RTAngle$_n53b$raw_n54e 3 S SSE SE +.names RTAngle$_n53e$raw_n54a RTAngle$_n526$raw_n53a _n53b RTAngle$_n53b$raw_n54e +- - 0 =RTAngle$_n526$raw_n53a +- - 1 =RTAngle$_n53e$raw_n54a +.mv _n553 3 GoUp GoDown Stop +.names _n553 +GoUp +# RTVerticalMotor == 0 +.names RTVerticalMotor _n553 _n552 +.def 0 +- =RTVerticalMotor 1 +.names _n552 _n554 +- =_n552 +.mv _n557 3 Top Mid Bot +.names _n557 +Mid +.names RTHight _n557 _n556 +.def 0 +- =RTHight 1 +.names _n556 _n555 +1 1 +0 0 +# RTHight = 0 +.mv RTHight$_n555_n558$true 3 Top Mid Bot +.names RTHight$_n555_n558$true +Top +.mv _n55b 3 Top Mid Bot +.names _n55b +Bot +.names RTHight _n55b _n55a +.def 0 +- =RTHight 1 +.names _n55a _n559 +1 1 +0 0 +# RTHight = 1 +.mv RTHight$_n559_n55c$true 3 Top Mid Bot +.names RTHight$_n559_n55c$true +Mid +# case (RTHight ) +.mv RTHight$_n559$raw_n562 3 Top Mid Bot +.names RTHight$_n559_n55c$true RTHight _n559 RTHight$_n559$raw_n562 +- - 0 =RTHight +- - 1 =RTHight$_n559_n55c$true +.mv RTHight$_n555$raw_n565 3 Top Mid Bot +.names RTHight$_n555_n558$true RTHight$_n559$raw_n562 _n555 RTHight$_n555$raw_n565 +- - 0 =RTHight$_n559$raw_n562 +- - 1 =RTHight$_n555_n558$true +# if/else (RTVerticalMotor == 0) +.mv RTHight$_n552$raw_n571 3 Top Mid Bot +.names RTHight$_n555$raw_n565 RTHight _n552 RTHight$_n552$raw_n571 +- - 0 =RTHight +- - 1 =RTHight$_n555$raw_n565 +.mv _n574 3 GoUp GoDown Stop +.names _n574 +GoDown +# RTVerticalMotor == 1 +.names RTVerticalMotor _n574 _n573 +.def 0 +- =RTVerticalMotor 1 +.names _n573 _n575 +- =_n573 +.mv _n578 3 Top Mid Bot +.names _n578 +Mid +.names RTHight$_n552$raw_n571 _n578 _n577 +.def 0 +- =RTHight$_n552$raw_n571 1 +.names _n577 _n576 +1 1 +0 0 +# RTHight = 2 +.mv RTHight$_n576_n579$true 3 Top Mid Bot +.names RTHight$_n576_n579$true +Bot +.mv _n57c 3 Top Mid Bot +.names _n57c +Top +.names RTHight$_n552$raw_n571 _n57c _n57b +.def 0 +- =RTHight$_n552$raw_n571 1 +.names _n57b _n57a +1 1 +0 0 +# RTHight = 1 +.mv RTHight$_n57a_n57d$true 3 Top Mid Bot +.names RTHight$_n57a_n57d$true +Mid +# case (RTHight ) +.mv RTHight$_n57a$raw_n57f 3 Top Mid Bot +.names RTHight$_n57a_n57d$true RTHight$_n552$raw_n571 _n57a RTHight$_n57a$raw_n57f +- - 0 =RTHight$_n552$raw_n571 +- - 1 =RTHight$_n57a_n57d$true +.mv RTHight$_n576$raw_n587 3 Top Mid Bot +.names RTHight$_n576_n579$true RTHight$_n57a$raw_n57f _n576 RTHight$_n576$raw_n587 +- - 0 =RTHight$_n57a$raw_n57f +- - 1 =RTHight$_n576_n579$true +# if/else (RTVerticalMotor == 1) +.mv RTHight$_n573$raw_n58f 3 Top Mid Bot +.names RTHight$_n576$raw_n587 RTHight$_n552$raw_n571 _n573 RTHight$_n573$raw_n58f +- - 0 =RTHight$_n552$raw_n571 +- - 1 =RTHight$_n576$raw_n587 +# conflict arbitrators +.names RTOnTop$raw_n516 RTOnTop +- =RTOnTop$raw_n516 +.names RTOnArm$raw_n510 RTOnArm +- =RTOnArm$raw_n510 +.names RTOnFB$raw_n50a RTOnFB +- =RTOnFB$raw_n50a +.names _n528 _n529 _n52d _n53d _n53e _n542 _n596 +.def 0 + 1 1 - - - - 1 + 1 0 1 - - - 1 + - - - 1 1 - 1 + - - - 1 0 1 1 +.mv _n597 3 S SSE SE +.names _n596 RTAngle$_n53b$raw_n54e RTAngle _n597 +1 - - =RTAngle$_n53b$raw_n54e +0 - - =RTAngle +.names RTOnBottom$raw_n51c RTOnBottom +- =RTOnBottom$raw_n51c +.names _n554 _n555 _n559 _n575 _n576 _n57a _n5a2 +.def 0 + 1 1 - - - - 1 + 1 0 1 - - - 1 + - - - 1 1 - 1 + - - - 1 0 1 1 +.mv _n5a3 3 Top Mid Bot +.names _n5a2 RTHight$_n573$raw_n58f RTHight _n5a3 +1 - - =RTHight$_n573$raw_n58f +0 - - =RTHight +# non-blocking assignments +# latches +.r RTAngle$raw_n522 RTAngle +- =RTAngle$raw_n522 +.latch _n597 RTAngle +.r RTHight$raw_n524 RTHight +- =RTHight$raw_n524 +.latch _n5a3 RTHight +# quasi-continuous assignment +.end + + +.model RotaryTableCNTR +# I/O ports +.inputs RTOnTop +.inputs RTOnArm +.inputs RTOnFB +.outputs RTOutReady +.outputs RTVerticalMotor +.inputs RTOnBottom +.outputs PieceGrabbedFromFB +.outputs RTRotaryMotor +.inputs PieceOutFB +.inputs PieceGrabbedFromRT +.mv TableLoaded 2 Y N +.mv UpChoice 3 GoUp GoDown Stop +.mv RTOnTop 2 Y N +.mv RTOnArm 2 Y N +.mv RTOnFB 2 Y N +.mv CCWiseChoice 3 CWise Stop CCWise +.mv DownChoice 3 GoUp GoDown Stop +.mv RTOutReady 2 Y N +.mv CWiseChoice 3 CWise Stop CCWise +.mv RTVerticalMotor 3 GoUp GoDown Stop +.mv RTOnBottom 2 Y N +.mv PieceGrabbedFromFB 2 Y N +.mv RTRotaryMotor 3 CWise Stop CCWise +.mv PieceOutFB 2 Y N +.mv PieceGrabbedFromRT 2 Y N +# assign CWiseChoice = 0 +.mv CWiseChoice$raw_n5ae 3 CWise Stop CCWise +.names CWiseChoice$raw_n5ae +CWise +# assign CCWiseChoice = 2 +.mv CCWiseChoice$raw_n5af 3 CWise Stop CCWise +.names CCWiseChoice$raw_n5af +CCWise +# assign UpChoice = 0 +.mv UpChoice$raw_n5b0 3 GoUp GoDown Stop +.names UpChoice$raw_n5b0 +GoUp +# assign DownChoice = 1 +.mv DownChoice$raw_n5b1 3 GoUp GoDown Stop +.names DownChoice$raw_n5b1 +GoDown +# RTRotaryMotor = 1 +.mv RTRotaryMotor$raw_n5b2 3 CWise Stop CCWise +.names RTRotaryMotor$raw_n5b2 +Stop +# RTVerticalMotor = 2 +.mv RTVerticalMotor$raw_n5b3 3 GoUp GoDown Stop +.names RTVerticalMotor$raw_n5b3 +Stop +# PieceGrabbedFromFB = 1 +.mv PieceGrabbedFromFB$raw_n5b4 2 Y N +.names PieceGrabbedFromFB$raw_n5b4 +N +# RTOutReady = 1 +.mv RTOutReady$raw_n5b5 2 Y N +.names RTOutReady$raw_n5b5 +N +# TableLoaded = 1 +.mv TableLoaded$raw_n5b6 2 Y N +.names TableLoaded$raw_n5b6 +N +# non-blocking assignments for initial +.mv _n5b9 2 Y N +.names _n5b9 +Y +.names TableLoaded _n5b9 _n5b8 +.def 0 +- =TableLoaded 1 +.names _n5b8 _n5b7 +1 1 +0 0 +.mv _n5bb 2 Y N +.names _n5bb +Y +# RTOnTop == 0 +.names RTOnTop _n5bb _n5ba +.def 0 +- =RTOnTop 1 +.names _n5ba _n5bc +- =_n5ba +.mv _n5be 2 Y N +.names _n5be +Y +# RTOnFB == 0 +.names RTOnFB _n5be _n5bd +.def 0 +- =RTOnFB 1 +.names _n5bd _n5bf +- =_n5bd +# RTRotaryMotor = 2 +.mv RTRotaryMotor$_n5bd_n5c0$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n5bd_n5c0$true +CCWise +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n5bd_n5c1$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n5bd_n5c1$true +Stop +# if/else (RTOnFB == 0) +.mv RTVerticalMotor$_n5bd$raw_n5c6 3 GoUp GoDown Stop +.names RTVerticalMotor$_n5bd_n5c1$true RTVerticalMotor _n5bd RTVerticalMotor$_n5bd$raw_n5c6 +- - 0 =RTVerticalMotor +- - 1 =RTVerticalMotor$_n5bd_n5c1$true +.mv RTRotaryMotor$_n5bd$raw_n5c7 3 CWise Stop CCWise +.names RTRotaryMotor$_n5bd_n5c0$true RTRotaryMotor _n5bd RTRotaryMotor$_n5bd$raw_n5c7 +- - 0 =RTRotaryMotor +- - 1 =RTRotaryMotor$_n5bd_n5c0$true +.mv _n5c9 2 Y N +.names _n5c9 +N +# RTOnFB == 1 +.names RTOnFB _n5c9 _n5c8 +.def 0 +- =RTOnFB 1 +.mv _n5cb 2 Y N +.names _n5cb +N +# RTOnArm == 1 +.names RTOnArm _n5cb _n5ca +.def 0 +- =RTOnArm 1 +# RTOnFB == 1 && RTOnArm == 1 +.names _n5c8 _n5ca _n5cc +.def 0 +1 1 1 +.names _n5cc _n5cd +- =_n5cc +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n5cc_n5ce$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n5cc_n5ce$true +Stop +.mv _n5d0 3 CWise Stop CCWise +.names _n5d0 +CCWise +# RTRotaryMotor == 2 +.names RTRotaryMotor$_n5bd$raw_n5c7 _n5d0 _n5cf +.def 0 +- =RTRotaryMotor$_n5bd$raw_n5c7 1 +.names _n5cf _n5d1 +- =_n5cf +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n5cf_n5d2$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n5cf_n5d2$true +Stop +# RTOutReady = 0 +.mv RTOutReady$_n5cf_n5d3$true 2 Y N +.names RTOutReady$_n5cf_n5d3$true +Y +.mv _n5d5 3 CWise Stop CCWise +.names _n5d5 +Stop +# RTRotaryMotor == 1 +.names RTRotaryMotor$_n5bd$raw_n5c7 _n5d5 _n5d4 +.def 0 +- =RTRotaryMotor$_n5bd$raw_n5c7 1 +.names _n5d4 _n5d6 +- =_n5d4 +# RTRotaryMotor = 2 +.mv RTRotaryMotor$_n5d4_n5d7$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n5d4_n5d7$true +CCWise +# if/else (RTRotaryMotor == 1) +.mv RTRotaryMotor$_n5d4$raw_n5d9 3 CWise Stop CCWise +.names RTRotaryMotor$_n5d4_n5d7$true RTRotaryMotor$_n5bd$raw_n5c7 _n5d4 RTRotaryMotor$_n5d4$raw_n5d9 +- - 0 =RTRotaryMotor$_n5bd$raw_n5c7 +- - 1 =RTRotaryMotor$_n5d4_n5d7$true +# if/else (RTRotaryMotor == 2) +.mv RTRotaryMotor$_n5cf$raw_n5e2 3 CWise Stop CCWise +.names RTRotaryMotor$_n5cf_n5d2$true RTRotaryMotor$_n5d4$raw_n5d9 _n5cf RTRotaryMotor$_n5cf$raw_n5e2 +- - 0 =RTRotaryMotor$_n5d4$raw_n5d9 +- - 1 =RTRotaryMotor$_n5cf_n5d2$true +.mv RTOutReady$_n5cf$raw_n5e6 2 Y N +.names RTOutReady$_n5cf_n5d3$true RTOutReady _n5cf RTOutReady$_n5cf$raw_n5e6 +- - 0 =RTOutReady +- - 1 =RTOutReady$_n5cf_n5d3$true +# if/else (RTOnFB == 1 && RTOnArm == 1) +.mv RTVerticalMotor$_n5cc$raw_n5ec 3 GoUp GoDown Stop +.names RTVerticalMotor$_n5cc_n5ce$true RTVerticalMotor$_n5bd$raw_n5c6 _n5cc RTVerticalMotor$_n5cc$raw_n5ec +- - 0 =RTVerticalMotor$_n5bd$raw_n5c6 +- - 1 =RTVerticalMotor$_n5cc_n5ce$true +.mv RTRotaryMotor$_n5cc$raw_n5ed 3 CWise Stop CCWise +.names RTRotaryMotor$_n5cf$raw_n5e2 RTRotaryMotor$_n5bd$raw_n5c7 _n5cc RTRotaryMotor$_n5cc$raw_n5ed +- - 0 =RTRotaryMotor$_n5bd$raw_n5c7 +- - 1 =RTRotaryMotor$_n5cf$raw_n5e2 +.mv RTOutReady$_n5cc$raw_n5f1 2 Y N +.names RTOutReady$_n5cf$raw_n5e6 RTOutReady _n5cc RTOutReady$_n5cc$raw_n5f1 +- - 0 =RTOutReady +- - 1 =RTOutReady$_n5cf$raw_n5e6 +.mv _n5f7 2 Y N +.names _n5f7 +Y +# RTOnArm == 0 +.names RTOnArm _n5f7 _n5f6 +.def 0 +- =RTOnArm 1 +.names _n5f6 _n5f8 +- =_n5f6 +.mv _n5fa 2 Y N +.names _n5fa +Y +# PieceGrabbedFromRT == 0 +.names PieceGrabbedFromRT _n5fa _n5f9 +.def 0 +- =PieceGrabbedFromRT 1 +.names _n5f9 _n5fb +- =_n5f9 +# RTOutReady = 1 +.mv RTOutReady$_n5f9_n5fc$true 2 Y N +.names RTOutReady$_n5f9_n5fc$true +N +# RTRotaryMotor = CWiseChoice +.mv RTRotaryMotor$_n5f9_n5fd$true 3 CWise Stop CCWise +.names CWiseChoice RTRotaryMotor$_n5f9_n5fd$true +- =CWiseChoice +# RTVerticalMotor = DownChoice +.mv RTVerticalMotor$_n5f9_n5fe$true 3 GoUp GoDown Stop +.names DownChoice RTVerticalMotor$_n5f9_n5fe$true +- =DownChoice +# TableLoaded = 1 +.mv TableLoaded$_n5f9_n5ff$true 2 Y N +.names TableLoaded$_n5f9_n5ff$true +N +# RTOutReady = 0 +.mv RTOutReady$_n5f9_n600$false 2 Y N +.names RTOutReady$_n5f9_n600$false +Y +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n5f9_n601$false 3 CWise Stop CCWise +.names RTRotaryMotor$_n5f9_n601$false +Stop +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n5f9_n602$false 3 GoUp GoDown Stop +.names RTVerticalMotor$_n5f9_n602$false +Stop +# if/else (PieceGrabbedFromRT == 0) +.mv RTOutReady$_n5f9$raw_n604 2 Y N +.names RTOutReady$_n5f9_n5fc$true RTOutReady$_n5f9_n600$false _n5f9 RTOutReady$_n5f9$raw_n604 +- - 0 =RTOutReady$_n5f9_n600$false +- - 1 =RTOutReady$_n5f9_n5fc$true +.mv RTVerticalMotor$_n5f9$raw_n605 3 GoUp GoDown Stop +.names RTVerticalMotor$_n5f9_n5fe$true RTVerticalMotor$_n5f9_n602$false _n5f9 RTVerticalMotor$_n5f9$raw_n605 +- - 0 =RTVerticalMotor$_n5f9_n602$false +- - 1 =RTVerticalMotor$_n5f9_n5fe$true +.mv RTRotaryMotor$_n5f9$raw_n606 3 CWise Stop CCWise +.names RTRotaryMotor$_n5f9_n5fd$true RTRotaryMotor$_n5f9_n601$false _n5f9 RTRotaryMotor$_n5f9$raw_n606 +- - 0 =RTRotaryMotor$_n5f9_n601$false +- - 1 =RTRotaryMotor$_n5f9_n5fd$true +.mv TableLoaded$_n5f9$raw_n60b 2 Y N +.names TableLoaded$_n5f9_n5ff$true TableLoaded _n5f9 TableLoaded$_n5f9$raw_n60b +- - 0 =TableLoaded +- - 1 =TableLoaded$_n5f9_n5ff$true +# if/else (RTOnArm == 0) +.mv RTOutReady$_n5f6$raw_n613 2 Y N +.names RTOutReady$_n5f9$raw_n604 RTOutReady$_n5cc$raw_n5f1 _n5f6 RTOutReady$_n5f6$raw_n613 +- - 0 =RTOutReady$_n5cc$raw_n5f1 +- - 1 =RTOutReady$_n5f9$raw_n604 +.mv RTVerticalMotor$_n5f6$raw_n614 3 GoUp GoDown Stop +.names RTVerticalMotor$_n5f9$raw_n605 RTVerticalMotor$_n5cc$raw_n5ec _n5f6 RTVerticalMotor$_n5f6$raw_n614 +- - 0 =RTVerticalMotor$_n5cc$raw_n5ec +- - 1 =RTVerticalMotor$_n5f9$raw_n605 +.mv RTRotaryMotor$_n5f6$raw_n615 3 CWise Stop CCWise +.names RTRotaryMotor$_n5f9$raw_n606 RTRotaryMotor$_n5cc$raw_n5ed _n5f6 RTRotaryMotor$_n5f6$raw_n615 +- - 0 =RTRotaryMotor$_n5cc$raw_n5ed +- - 1 =RTRotaryMotor$_n5f9$raw_n606 +.mv TableLoaded$_n5f6$raw_n61a 2 Y N +.names TableLoaded$_n5f9$raw_n60b TableLoaded _n5f6 TableLoaded$_n5f6$raw_n61a +- - 0 =TableLoaded +- - 1 =TableLoaded$_n5f9$raw_n60b +# if/else (RTOnTop == 0) +.mv TableLoaded$_n5ba$raw_n629 2 Y N +.names TableLoaded$_n5f6$raw_n61a TableLoaded _n5ba TableLoaded$_n5ba$raw_n629 +- - 0 =TableLoaded +- - 1 =TableLoaded$_n5f6$raw_n61a +.mv RTOutReady$_n5ba$raw_n62a 2 Y N +.names RTOutReady$_n5f6$raw_n613 RTOutReady _n5ba RTOutReady$_n5ba$raw_n62a +- - 0 =RTOutReady +- - 1 =RTOutReady$_n5f6$raw_n613 +.mv RTVerticalMotor$_n5ba$raw_n62b 3 GoUp GoDown Stop +.names RTVerticalMotor$_n5f6$raw_n614 RTVerticalMotor _n5ba RTVerticalMotor$_n5ba$raw_n62b +- - 0 =RTVerticalMotor +- - 1 =RTVerticalMotor$_n5f6$raw_n614 +.mv RTRotaryMotor$_n5ba$raw_n62c 3 CWise Stop CCWise +.names RTRotaryMotor$_n5f6$raw_n615 RTRotaryMotor _n5ba RTRotaryMotor$_n5ba$raw_n62c +- - 0 =RTRotaryMotor +- - 1 =RTRotaryMotor$_n5f6$raw_n615 +.mv _n62e 2 Y N +.names _n62e +N +# RTOnTop == 1 +.names RTOnTop _n62e _n62d +.def 0 +- =RTOnTop 1 +.mv _n630 2 Y N +.names _n630 +N +# RTOnBottom == 1 +.names RTOnBottom _n630 _n62f +.def 0 +- =RTOnBottom 1 +# RTOnTop == 1 && RTOnBottom == 1 +.names _n62d _n62f _n631 +.def 0 +1 1 1 +.names _n631 _n632 +- =_n631 +.mv _n634 2 Y N +.names _n634 +Y +# RTOnFB == 0 +.names RTOnFB _n634 _n633 +.def 0 +- =RTOnFB 1 +.names _n633 _n635 +- =_n633 +# RTRotaryMotor = CCWiseChoice +.mv RTRotaryMotor$_n633_n636$true 3 CWise Stop CCWise +.names CCWiseChoice RTRotaryMotor$_n633_n636$true +- =CCWiseChoice +.mv _n638 3 GoUp GoDown Stop +.names _n638 +GoUp +# RTVerticalMotor == 0 +.names RTVerticalMotor$_n5ba$raw_n62b _n638 _n637 +.def 0 +- =RTVerticalMotor$_n5ba$raw_n62b 1 +.names _n637 _n639 +- =_n637 +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n637_n63a$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n637_n63a$true +Stop +# RTVerticalMotor = UpChoice +.mv RTVerticalMotor$_n637_n63b$false 3 GoUp GoDown Stop +.names UpChoice RTVerticalMotor$_n637_n63b$false +- =UpChoice +# if/else (RTVerticalMotor == 0) +.mv RTVerticalMotor$_n637$raw_n63e 3 GoUp GoDown Stop +.names RTVerticalMotor$_n637_n63a$true RTVerticalMotor$_n637_n63b$false _n637 RTVerticalMotor$_n637$raw_n63e +- - 0 =RTVerticalMotor$_n637_n63b$false +- - 1 =RTVerticalMotor$_n637_n63a$true +# if/else (RTOnFB == 0) +.mv RTVerticalMotor$_n633$raw_n64e 3 GoUp GoDown Stop +.names RTVerticalMotor$_n637$raw_n63e RTVerticalMotor$_n5ba$raw_n62b _n633 RTVerticalMotor$_n633$raw_n64e +- - 0 =RTVerticalMotor$_n5ba$raw_n62b +- - 1 =RTVerticalMotor$_n637$raw_n63e +.mv RTRotaryMotor$_n633$raw_n64f 3 CWise Stop CCWise +.names RTRotaryMotor$_n633_n636$true RTRotaryMotor$_n5ba$raw_n62c _n633 RTRotaryMotor$_n633$raw_n64f +- - 0 =RTRotaryMotor$_n5ba$raw_n62c +- - 1 =RTRotaryMotor$_n633_n636$true +.mv _n65d 2 Y N +.names _n65d +N +# RTOnFB == 1 +.names RTOnFB _n65d _n65c +.def 0 +- =RTOnFB 1 +.mv _n65f 2 Y N +.names _n65f +N +# RTOnArm == 1 +.names RTOnArm _n65f _n65e +.def 0 +- =RTOnArm 1 +# RTOnFB == 1 && RTOnArm == 1 +.names _n65c _n65e _n660 +.def 0 +1 1 1 +.names _n660 _n661 +- =_n660 +.mv _n663 3 CWise Stop CCWise +.names _n663 +CCWise +# RTRotaryMotor == 2 +.names RTRotaryMotor$_n633$raw_n64f _n663 _n662 +.def 0 +- =RTRotaryMotor$_n633$raw_n64f 1 +.mv _n665 3 GoUp GoDown Stop +.names _n665 +GoUp +# RTVerticalMotor == 0 +.names RTVerticalMotor$_n633$raw_n64e _n665 _n664 +.def 0 +- =RTVerticalMotor$_n633$raw_n64e 1 +# RTRotaryMotor == 2 && RTVerticalMotor == 0 +.names _n662 _n664 _n666 +.def 0 +1 1 1 +.names _n666 _n667 +- =_n666 +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n666_n668$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n666_n668$true +Stop +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n666_n669$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n666_n669$true +Stop +# RTOutReady = 0 +.mv RTOutReady$_n666_n66a$true 2 Y N +.names RTOutReady$_n666_n66a$true +Y +.mv _n66c 3 CWise Stop CCWise +.names _n66c +CCWise +# RTRotaryMotor != 2 +.names RTRotaryMotor$_n633$raw_n64f _n66c _n66b +.def 1 +- =RTRotaryMotor$_n633$raw_n64f 0 +.mv _n66e 3 GoUp GoDown Stop +.names _n66e +GoUp +# RTVerticalMotor == 0 +.names RTVerticalMotor$_n633$raw_n64e _n66e _n66d +.def 0 +- =RTVerticalMotor$_n633$raw_n64e 1 +# RTRotaryMotor != 2 && RTVerticalMotor == 0 +.names _n66b _n66d _n66f +.def 0 +1 1 1 +.names _n66f _n670 +- =_n66f +# RTRotaryMotor = CCWiseChoice +.mv RTRotaryMotor$_n66f_n671$true 3 CWise Stop CCWise +.names CCWiseChoice RTRotaryMotor$_n66f_n671$true +- =CCWiseChoice +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n66f_n672$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n66f_n672$true +Stop +.mv _n674 3 CWise Stop CCWise +.names _n674 +CCWise +# RTRotaryMotor == 2 +.names RTRotaryMotor$_n633$raw_n64f _n674 _n673 +.def 0 +- =RTRotaryMotor$_n633$raw_n64f 1 +.mv _n676 3 GoUp GoDown Stop +.names _n676 +GoUp +# RTVerticalMotor != 0 +.names RTVerticalMotor$_n633$raw_n64e _n676 _n675 +.def 1 +- =RTVerticalMotor$_n633$raw_n64e 0 +# RTRotaryMotor == 2 && RTVerticalMotor != 0 +.names _n673 _n675 _n677 +.def 0 +1 1 1 +.names _n677 _n678 +- =_n677 +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n677_n679$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n677_n679$true +Stop +# RTVerticalMotor = UpChoice +.mv RTVerticalMotor$_n677_n67a$true 3 GoUp GoDown Stop +.names UpChoice RTVerticalMotor$_n677_n67a$true +- =UpChoice +.mv _n67c 3 CWise Stop CCWise +.names _n67c +CCWise +# RTRotaryMotor != 2 +.names RTRotaryMotor$_n633$raw_n64f _n67c _n67b +.def 1 +- =RTRotaryMotor$_n633$raw_n64f 0 +.mv _n67e 3 GoUp GoDown Stop +.names _n67e +GoUp +# RTVerticalMotor != 0 +.names RTVerticalMotor$_n633$raw_n64e _n67e _n67d +.def 1 +- =RTVerticalMotor$_n633$raw_n64e 0 +# RTRotaryMotor != 2 && RTVerticalMotor != 0 +.names _n67b _n67d _n67f +.def 0 +1 1 1 +.names _n67f _n680 +- =_n67f +# RTRotaryMotor = CCWiseChoice +.mv RTRotaryMotor$_n67f_n681$true 3 CWise Stop CCWise +.names CCWiseChoice RTRotaryMotor$_n67f_n681$true +- =CCWiseChoice +# RTVerticalMotor = UpChoice +.mv RTVerticalMotor$_n67f_n682$true 3 GoUp GoDown Stop +.names UpChoice RTVerticalMotor$_n67f_n682$true +- =UpChoice +# if/else (RTRotaryMotor != 2 && RTVerticalMotor != 0) +.mv RTVerticalMotor$_n67f$raw_n685 3 GoUp GoDown Stop +.names RTVerticalMotor$_n67f_n682$true RTVerticalMotor$_n633$raw_n64e _n67f RTVerticalMotor$_n67f$raw_n685 +- - 0 =RTVerticalMotor$_n633$raw_n64e +- - 1 =RTVerticalMotor$_n67f_n682$true +.mv RTRotaryMotor$_n67f$raw_n686 3 CWise Stop CCWise +.names RTRotaryMotor$_n67f_n681$true RTRotaryMotor$_n633$raw_n64f _n67f RTRotaryMotor$_n67f$raw_n686 +- - 0 =RTRotaryMotor$_n633$raw_n64f +- - 1 =RTRotaryMotor$_n67f_n681$true +# if/else (RTRotaryMotor == 2 && RTVerticalMotor != 0) +.mv RTVerticalMotor$_n677$raw_n695 3 GoUp GoDown Stop +.names RTVerticalMotor$_n677_n67a$true RTVerticalMotor$_n67f$raw_n685 _n677 RTVerticalMotor$_n677$raw_n695 +- - 0 =RTVerticalMotor$_n67f$raw_n685 +- - 1 =RTVerticalMotor$_n677_n67a$true +.mv RTRotaryMotor$_n677$raw_n696 3 CWise Stop CCWise +.names RTRotaryMotor$_n677_n679$true RTRotaryMotor$_n67f$raw_n686 _n677 RTRotaryMotor$_n677$raw_n696 +- - 0 =RTRotaryMotor$_n67f$raw_n686 +- - 1 =RTRotaryMotor$_n677_n679$true +# if/else (RTRotaryMotor != 2 && RTVerticalMotor == 0) +.mv RTVerticalMotor$_n66f$raw_n6a5 3 GoUp GoDown Stop +.names RTVerticalMotor$_n66f_n672$true RTVerticalMotor$_n677$raw_n695 _n66f RTVerticalMotor$_n66f$raw_n6a5 +- - 0 =RTVerticalMotor$_n677$raw_n695 +- - 1 =RTVerticalMotor$_n66f_n672$true +.mv RTRotaryMotor$_n66f$raw_n6a6 3 CWise Stop CCWise +.names RTRotaryMotor$_n66f_n671$true RTRotaryMotor$_n677$raw_n696 _n66f RTRotaryMotor$_n66f$raw_n6a6 +- - 0 =RTRotaryMotor$_n677$raw_n696 +- - 1 =RTRotaryMotor$_n66f_n671$true +# if/else (RTRotaryMotor == 2 && RTVerticalMotor == 0) +.mv RTOutReady$_n666$raw_n6b4 2 Y N +.names RTOutReady$_n666_n66a$true RTOutReady$_n5ba$raw_n62a _n666 RTOutReady$_n666$raw_n6b4 +- - 0 =RTOutReady$_n5ba$raw_n62a +- - 1 =RTOutReady$_n666_n66a$true +.mv RTVerticalMotor$_n666$raw_n6b5 3 GoUp GoDown Stop +.names RTVerticalMotor$_n666_n669$true RTVerticalMotor$_n66f$raw_n6a5 _n666 RTVerticalMotor$_n666$raw_n6b5 +- - 0 =RTVerticalMotor$_n66f$raw_n6a5 +- - 1 =RTVerticalMotor$_n666_n669$true +.mv RTRotaryMotor$_n666$raw_n6b6 3 CWise Stop CCWise +.names RTRotaryMotor$_n666_n668$true RTRotaryMotor$_n66f$raw_n6a6 _n666 RTRotaryMotor$_n666$raw_n6b6 +- - 0 =RTRotaryMotor$_n66f$raw_n6a6 +- - 1 =RTRotaryMotor$_n666_n668$true +# if/else (RTOnFB == 1 && RTOnArm == 1) +.mv RTOutReady$_n660$raw_n6c4 2 Y N +.names RTOutReady$_n666$raw_n6b4 RTOutReady$_n5ba$raw_n62a _n660 RTOutReady$_n660$raw_n6c4 +- - 0 =RTOutReady$_n5ba$raw_n62a +- - 1 =RTOutReady$_n666$raw_n6b4 +.mv RTVerticalMotor$_n660$raw_n6c5 3 GoUp GoDown Stop +.names RTVerticalMotor$_n666$raw_n6b5 RTVerticalMotor$_n633$raw_n64e _n660 RTVerticalMotor$_n660$raw_n6c5 +- - 0 =RTVerticalMotor$_n633$raw_n64e +- - 1 =RTVerticalMotor$_n666$raw_n6b5 +.mv RTRotaryMotor$_n660$raw_n6c6 3 CWise Stop CCWise +.names RTRotaryMotor$_n666$raw_n6b6 RTRotaryMotor$_n633$raw_n64f _n660 RTRotaryMotor$_n660$raw_n6c6 +- - 0 =RTRotaryMotor$_n633$raw_n64f +- - 1 =RTRotaryMotor$_n666$raw_n6b6 +.mv _n6d4 2 Y N +.names _n6d4 +Y +# RTOnArm == 0 +.names RTOnArm _n6d4 _n6d3 +.def 0 +- =RTOnArm 1 +.names _n6d3 _n6d5 +- =_n6d3 +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n6d3_n6d6$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n6d3_n6d6$true +Stop +.mv _n6d8 3 GoUp GoDown Stop +.names _n6d8 +GoUp +# RTVerticalMotor == 0 +.names RTVerticalMotor$_n660$raw_n6c5 _n6d8 _n6d7 +.def 0 +- =RTVerticalMotor$_n660$raw_n6c5 1 +.names _n6d7 _n6d9 +- =_n6d7 +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n6d7_n6da$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n6d7_n6da$true +Stop +# RTOutReady = 0 +.mv RTOutReady$_n6d7_n6db$true 2 Y N +.names RTOutReady$_n6d7_n6db$true +Y +# RTVerticalMotor = 0 +.mv RTVerticalMotor$_n6d7_n6dc$false 3 GoUp GoDown Stop +.names RTVerticalMotor$_n6d7_n6dc$false +GoUp +# if/else (RTVerticalMotor == 0) +.mv RTOutReady$_n6d7$raw_n6de 2 Y N +.names RTOutReady$_n6d7_n6db$true RTOutReady$_n660$raw_n6c4 _n6d7 RTOutReady$_n6d7$raw_n6de +- - 0 =RTOutReady$_n660$raw_n6c4 +- - 1 =RTOutReady$_n6d7_n6db$true +.mv RTVerticalMotor$_n6d7$raw_n6df 3 GoUp GoDown Stop +.names RTVerticalMotor$_n6d7_n6da$true RTVerticalMotor$_n6d7_n6dc$false _n6d7 RTVerticalMotor$_n6d7$raw_n6df +- - 0 =RTVerticalMotor$_n6d7_n6dc$false +- - 1 =RTVerticalMotor$_n6d7_n6da$true +# if/else (RTOnArm == 0) +.mv RTOutReady$_n6d3$raw_n6ee 2 Y N +.names RTOutReady$_n6d7$raw_n6de RTOutReady$_n660$raw_n6c4 _n6d3 RTOutReady$_n6d3$raw_n6ee +- - 0 =RTOutReady$_n660$raw_n6c4 +- - 1 =RTOutReady$_n6d7$raw_n6de +.mv RTVerticalMotor$_n6d3$raw_n6ef 3 GoUp GoDown Stop +.names RTVerticalMotor$_n6d7$raw_n6df RTVerticalMotor$_n660$raw_n6c5 _n6d3 RTVerticalMotor$_n6d3$raw_n6ef +- - 0 =RTVerticalMotor$_n660$raw_n6c5 +- - 1 =RTVerticalMotor$_n6d7$raw_n6df +.mv RTRotaryMotor$_n6d3$raw_n6f0 3 CWise Stop CCWise +.names RTRotaryMotor$_n6d3_n6d6$true RTRotaryMotor$_n660$raw_n6c6 _n6d3 RTRotaryMotor$_n6d3$raw_n6f0 +- - 0 =RTRotaryMotor$_n660$raw_n6c6 +- - 1 =RTRotaryMotor$_n6d3_n6d6$true +# if/else (RTOnTop == 1 && RTOnBottom == 1) +.mv RTOutReady$_n631$raw_n6fe 2 Y N +.names RTOutReady$_n6d3$raw_n6ee RTOutReady$_n5ba$raw_n62a _n631 RTOutReady$_n631$raw_n6fe +- - 0 =RTOutReady$_n5ba$raw_n62a +- - 1 =RTOutReady$_n6d3$raw_n6ee +.mv RTVerticalMotor$_n631$raw_n6ff 3 GoUp GoDown Stop +.names RTVerticalMotor$_n6d3$raw_n6ef RTVerticalMotor$_n5ba$raw_n62b _n631 RTVerticalMotor$_n631$raw_n6ff +- - 0 =RTVerticalMotor$_n5ba$raw_n62b +- - 1 =RTVerticalMotor$_n6d3$raw_n6ef +.mv RTRotaryMotor$_n631$raw_n700 3 CWise Stop CCWise +.names RTRotaryMotor$_n6d3$raw_n6f0 RTRotaryMotor$_n5ba$raw_n62c _n631 RTRotaryMotor$_n631$raw_n700 +- - 0 =RTRotaryMotor$_n5ba$raw_n62c +- - 1 =RTRotaryMotor$_n6d3$raw_n6f0 +.mv _n70e 2 Y N +.names _n70e +Y +# RTOnBottom == 0 +.names RTOnBottom _n70e _n70d +.def 0 +- =RTOnBottom 1 +.names _n70d _n70f +- =_n70d +.mv _n711 2 Y N +.names _n711 +Y +# RTOnFB == 0 +.names RTOnFB _n711 _n710 +.def 0 +- =RTOnFB 1 +.names _n710 _n712 +- =_n710 +# RTRotaryMotor = CCWiseChoice +.mv RTRotaryMotor$_n710_n713$true 3 CWise Stop CCWise +.names CCWiseChoice RTRotaryMotor$_n710_n713$true +- =CCWiseChoice +# RTVerticalMotor = UpChoice +.mv RTVerticalMotor$_n710_n714$true 3 GoUp GoDown Stop +.names UpChoice RTVerticalMotor$_n710_n714$true +- =UpChoice +# if/else (RTOnFB == 0) +.mv RTVerticalMotor$_n710$raw_n717 3 GoUp GoDown Stop +.names RTVerticalMotor$_n710_n714$true RTVerticalMotor$_n631$raw_n6ff _n710 RTVerticalMotor$_n710$raw_n717 +- - 0 =RTVerticalMotor$_n631$raw_n6ff +- - 1 =RTVerticalMotor$_n710_n714$true +.mv RTRotaryMotor$_n710$raw_n718 3 CWise Stop CCWise +.names RTRotaryMotor$_n710_n713$true RTRotaryMotor$_n631$raw_n700 _n710 RTRotaryMotor$_n710$raw_n718 +- - 0 =RTRotaryMotor$_n631$raw_n700 +- - 1 =RTRotaryMotor$_n710_n713$true +.mv _n726 2 Y N +.names _n726 +N +# RTOnFB == 1 +.names RTOnFB _n726 _n725 +.def 0 +- =RTOnFB 1 +.mv _n728 2 Y N +.names _n728 +N +# RTOnArm == 1 +.names RTOnArm _n728 _n727 +.def 0 +- =RTOnArm 1 +# RTOnFB == 1 && RTOnArm == 1 +.names _n725 _n727 _n729 +.def 0 +1 1 1 +.names _n729 _n72a +- =_n729 +# RTVerticalMotor = UpChoice +.mv RTVerticalMotor$_n729_n72b$true 3 GoUp GoDown Stop +.names UpChoice RTVerticalMotor$_n729_n72b$true +- =UpChoice +.mv _n72d 3 CWise Stop CCWise +.names _n72d +CCWise +# RTRotaryMotor == 2 +.names RTRotaryMotor$_n710$raw_n718 _n72d _n72c +.def 0 +- =RTRotaryMotor$_n710$raw_n718 1 +.names _n72c _n72e +- =_n72c +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n72c_n72f$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n72c_n72f$true +Stop +# RTRotaryMotor = CCWiseChoice +.mv RTRotaryMotor$_n72c_n730$false 3 CWise Stop CCWise +.names CCWiseChoice RTRotaryMotor$_n72c_n730$false +- =CCWiseChoice +# if/else (RTRotaryMotor == 2) +.mv RTRotaryMotor$_n72c$raw_n734 3 CWise Stop CCWise +.names RTRotaryMotor$_n72c_n72f$true RTRotaryMotor$_n72c_n730$false _n72c RTRotaryMotor$_n72c$raw_n734 +- - 0 =RTRotaryMotor$_n72c_n730$false +- - 1 =RTRotaryMotor$_n72c_n72f$true +# if/else (RTOnFB == 1 && RTOnArm == 1) +.mv RTVerticalMotor$_n729$raw_n743 3 GoUp GoDown Stop +.names RTVerticalMotor$_n729_n72b$true RTVerticalMotor$_n710$raw_n717 _n729 RTVerticalMotor$_n729$raw_n743 +- - 0 =RTVerticalMotor$_n710$raw_n717 +- - 1 =RTVerticalMotor$_n729_n72b$true +.mv RTRotaryMotor$_n729$raw_n744 3 CWise Stop CCWise +.names RTRotaryMotor$_n72c$raw_n734 RTRotaryMotor$_n710$raw_n718 _n729 RTRotaryMotor$_n729$raw_n744 +- - 0 =RTRotaryMotor$_n710$raw_n718 +- - 1 =RTRotaryMotor$_n72c$raw_n734 +.mv _n752 2 Y N +.names _n752 +Y +# RTOnArm == 0 +.names RTOnArm _n752 _n751 +.def 0 +- =RTOnArm 1 +.names _n751 _n753 +- =_n751 +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n751_n754$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n751_n754$true +Stop +# RTVerticalMotor = 0 +.mv RTVerticalMotor$_n751_n755$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n751_n755$true +GoUp +# if/else (RTOnArm == 0) +.mv RTVerticalMotor$_n751$raw_n758 3 GoUp GoDown Stop +.names RTVerticalMotor$_n751_n755$true RTVerticalMotor$_n729$raw_n743 _n751 RTVerticalMotor$_n751$raw_n758 +- - 0 =RTVerticalMotor$_n729$raw_n743 +- - 1 =RTVerticalMotor$_n751_n755$true +.mv RTRotaryMotor$_n751$raw_n759 3 CWise Stop CCWise +.names RTRotaryMotor$_n751_n754$true RTRotaryMotor$_n729$raw_n744 _n751 RTRotaryMotor$_n751$raw_n759 +- - 0 =RTRotaryMotor$_n729$raw_n744 +- - 1 =RTRotaryMotor$_n751_n754$true +# if/else (RTOnBottom == 0) +.mv RTVerticalMotor$_n70d$raw_n768 3 GoUp GoDown Stop +.names RTVerticalMotor$_n751$raw_n758 RTVerticalMotor$_n631$raw_n6ff _n70d RTVerticalMotor$_n70d$raw_n768 +- - 0 =RTVerticalMotor$_n631$raw_n6ff +- - 1 =RTVerticalMotor$_n751$raw_n758 +.mv RTRotaryMotor$_n70d$raw_n769 3 CWise Stop CCWise +.names RTRotaryMotor$_n751$raw_n759 RTRotaryMotor$_n631$raw_n700 _n70d RTRotaryMotor$_n70d$raw_n769 +- - 0 =RTRotaryMotor$_n631$raw_n700 +- - 1 =RTRotaryMotor$_n751$raw_n759 +.mv _n778 2 Y N +.names _n778 +N +.names TableLoaded _n778 _n777 +.def 0 +- =TableLoaded 1 +.names _n777 _n776 +1 1 +0 0 +.mv _n77a 2 Y N +.names _n77a +Y +# RTOnTop == 0 +.names RTOnTop _n77a _n779 +.def 0 +- =RTOnTop 1 +.names _n779 _n77b +- =_n779 +.mv _n77d 2 Y N +.names _n77d +Y +# RTOnFB == 0 +.names RTOnFB _n77d _n77c +.def 0 +- =RTOnFB 1 +.names _n77c _n77e +- =_n77c +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n77c_n77f$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n77c_n77f$true +Stop +# RTVerticalMotor = 1 +.mv RTVerticalMotor$_n77c_n780$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n77c_n780$true +GoDown +# if/else (RTOnFB == 0) +.mv RTVerticalMotor$_n77c$raw_n785 3 GoUp GoDown Stop +.names RTVerticalMotor$_n77c_n780$true RTVerticalMotor _n77c RTVerticalMotor$_n77c$raw_n785 +- - 0 =RTVerticalMotor +- - 1 =RTVerticalMotor$_n77c_n780$true +.mv RTRotaryMotor$_n77c$raw_n786 3 CWise Stop CCWise +.names RTRotaryMotor$_n77c_n77f$true RTRotaryMotor _n77c RTRotaryMotor$_n77c$raw_n786 +- - 0 =RTRotaryMotor +- - 1 =RTRotaryMotor$_n77c_n77f$true +.mv _n788 2 Y N +.names _n788 +N +# RTOnFB == 1 +.names RTOnFB _n788 _n787 +.def 0 +- =RTOnFB 1 +.mv _n78a 2 Y N +.names _n78a +N +# RTOnArm == 1 +.names RTOnArm _n78a _n789 +.def 0 +- =RTOnArm 1 +# RTOnFB == 1 && RTOnArm == 1 +.names _n787 _n789 _n78b +.def 0 +1 1 1 +.names _n78b _n78c +- =_n78b +# RTVerticalMotor = DownChoice +.mv RTVerticalMotor$_n78b_n78d$true 3 GoUp GoDown Stop +.names DownChoice RTVerticalMotor$_n78b_n78d$true +- =DownChoice +.mv _n78f 3 CWise Stop CCWise +.names _n78f +CWise +# RTRotaryMotor == 0 +.names RTRotaryMotor$_n77c$raw_n786 _n78f _n78e +.def 0 +- =RTRotaryMotor$_n77c$raw_n786 1 +.names _n78e _n790 +- =_n78e +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n78e_n791$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n78e_n791$true +Stop +# RTRotaryMotor = CWiseChoice +.mv RTRotaryMotor$_n78e_n792$false 3 CWise Stop CCWise +.names CWiseChoice RTRotaryMotor$_n78e_n792$false +- =CWiseChoice +# if/else (RTRotaryMotor == 0) +.mv RTRotaryMotor$_n78e$raw_n794 3 CWise Stop CCWise +.names RTRotaryMotor$_n78e_n791$true RTRotaryMotor$_n78e_n792$false _n78e RTRotaryMotor$_n78e$raw_n794 +- - 0 =RTRotaryMotor$_n78e_n792$false +- - 1 =RTRotaryMotor$_n78e_n791$true +# if/else (RTOnFB == 1 && RTOnArm == 1) +.mv RTVerticalMotor$_n78b$raw_n79b 3 GoUp GoDown Stop +.names RTVerticalMotor$_n78b_n78d$true RTVerticalMotor$_n77c$raw_n785 _n78b RTVerticalMotor$_n78b$raw_n79b +- - 0 =RTVerticalMotor$_n77c$raw_n785 +- - 1 =RTVerticalMotor$_n78b_n78d$true +.mv RTRotaryMotor$_n78b$raw_n79c 3 CWise Stop CCWise +.names RTRotaryMotor$_n78e$raw_n794 RTRotaryMotor$_n77c$raw_n786 _n78b RTRotaryMotor$_n78b$raw_n79c +- - 0 =RTRotaryMotor$_n77c$raw_n786 +- - 1 =RTRotaryMotor$_n78e$raw_n794 +.mv _n7a4 2 Y N +.names _n7a4 +Y +# RTOnArm == 0 +.names RTOnArm _n7a4 _n7a3 +.def 0 +- =RTOnArm 1 +.names _n7a3 _n7a5 +- =_n7a3 +# RTRotaryMotor = CWiseChoice +.mv RTRotaryMotor$_n7a3_n7a6$true 3 CWise Stop CCWise +.names CWiseChoice RTRotaryMotor$_n7a3_n7a6$true +- =CWiseChoice +# RTVerticalMotor = DownChoice +.mv RTVerticalMotor$_n7a3_n7a7$true 3 GoUp GoDown Stop +.names DownChoice RTVerticalMotor$_n7a3_n7a7$true +- =DownChoice +# if/else (RTOnArm == 0) +.mv RTVerticalMotor$_n7a3$raw_n7a8 3 GoUp GoDown Stop +.names RTVerticalMotor$_n7a3_n7a7$true RTVerticalMotor$_n78b$raw_n79b _n7a3 RTVerticalMotor$_n7a3$raw_n7a8 +- - 0 =RTVerticalMotor$_n78b$raw_n79b +- - 1 =RTVerticalMotor$_n7a3_n7a7$true +.mv RTRotaryMotor$_n7a3$raw_n7a9 3 CWise Stop CCWise +.names RTRotaryMotor$_n7a3_n7a6$true RTRotaryMotor$_n78b$raw_n79c _n7a3 RTRotaryMotor$_n7a3$raw_n7a9 +- - 0 =RTRotaryMotor$_n78b$raw_n79c +- - 1 =RTRotaryMotor$_n7a3_n7a6$true +# if/else (RTOnTop == 0) +.mv RTVerticalMotor$_n779$raw_n7b4 3 GoUp GoDown Stop +.names RTVerticalMotor$_n7a3$raw_n7a8 RTVerticalMotor _n779 RTVerticalMotor$_n779$raw_n7b4 +- - 0 =RTVerticalMotor +- - 1 =RTVerticalMotor$_n7a3$raw_n7a8 +.mv RTRotaryMotor$_n779$raw_n7b5 3 CWise Stop CCWise +.names RTRotaryMotor$_n7a3$raw_n7a9 RTRotaryMotor _n779 RTRotaryMotor$_n779$raw_n7b5 +- - 0 =RTRotaryMotor +- - 1 =RTRotaryMotor$_n7a3$raw_n7a9 +.mv _n7b7 2 Y N +.names _n7b7 +N +# RTOnTop == 1 +.names RTOnTop _n7b7 _n7b6 +.def 0 +- =RTOnTop 1 +.mv _n7b9 2 Y N +.names _n7b9 +N +# RTOnBottom == 1 +.names RTOnBottom _n7b9 _n7b8 +.def 0 +- =RTOnBottom 1 +# RTOnTop == 1 && RTOnBottom == 1 +.names _n7b6 _n7b8 _n7ba +.def 0 +1 1 1 +.names _n7ba _n7bb +- =_n7ba +.mv _n7bd 2 Y N +.names _n7bd +Y +# RTOnFB == 0 +.names RTOnFB _n7bd _n7bc +.def 0 +- =RTOnFB 1 +.names _n7bc _n7be +- =_n7bc +.mv _n7c0 3 GoUp GoDown Stop +.names _n7c0 +GoDown +# RTVerticalMotor == 1 +.names RTVerticalMotor$_n779$raw_n7b4 _n7c0 _n7bf +.def 0 +- =RTVerticalMotor$_n779$raw_n7b4 1 +.names _n7bf _n7c1 +- =_n7bf +.mv _n7c3 2 Y N +.names _n7c3 +Y +# PieceOutFB == 0 +.names PieceOutFB _n7c3 _n7c2 +.def 0 +- =PieceOutFB 1 +.names _n7c2 _n7c4 +- =_n7c2 +# TableLoaded = 0 +.mv TableLoaded$_n7c2_n7c5$true 2 Y N +.names TableLoaded$_n7c2_n7c5$true +Y +# PieceGrabbedFromFB = 0 +.mv PieceGrabbedFromFB$_n7c2_n7c6$true 2 Y N +.names PieceGrabbedFromFB$_n7c2_n7c6$true +Y +# RTRotaryMotor = CCWiseChoice +.mv RTRotaryMotor$_n7c2_n7c7$true 3 CWise Stop CCWise +.names CCWiseChoice RTRotaryMotor$_n7c2_n7c7$true +- =CCWiseChoice +# RTVerticalMotor = UpChoice +.mv RTVerticalMotor$_n7c2_n7c8$true 3 GoUp GoDown Stop +.names UpChoice RTVerticalMotor$_n7c2_n7c8$true +- =UpChoice +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n7c2_n7c9$false 3 CWise Stop CCWise +.names RTRotaryMotor$_n7c2_n7c9$false +Stop +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n7c2_n7ca$false 3 GoUp GoDown Stop +.names RTVerticalMotor$_n7c2_n7ca$false +Stop +# if/else (PieceOutFB == 0) +.mv RTVerticalMotor$_n7c2$raw_n7cc 3 GoUp GoDown Stop +.names RTVerticalMotor$_n7c2_n7c8$true RTVerticalMotor$_n7c2_n7ca$false _n7c2 RTVerticalMotor$_n7c2$raw_n7cc +- - 0 =RTVerticalMotor$_n7c2_n7ca$false +- - 1 =RTVerticalMotor$_n7c2_n7c8$true +.mv RTRotaryMotor$_n7c2$raw_n7ce 3 CWise Stop CCWise +.names RTRotaryMotor$_n7c2_n7c7$true RTRotaryMotor$_n7c2_n7c9$false _n7c2 RTRotaryMotor$_n7c2$raw_n7ce +- - 0 =RTRotaryMotor$_n7c2_n7c9$false +- - 1 =RTRotaryMotor$_n7c2_n7c7$true +.mv TableLoaded$_n7c2$raw_n7d3 2 Y N +.names TableLoaded$_n7c2_n7c5$true TableLoaded _n7c2 TableLoaded$_n7c2$raw_n7d3 +- - 0 =TableLoaded +- - 1 =TableLoaded$_n7c2_n7c5$true +.mv PieceGrabbedFromFB$_n7c2$raw_n7d5 2 Y N +.names PieceGrabbedFromFB$_n7c2_n7c6$true PieceGrabbedFromFB _n7c2 PieceGrabbedFromFB$_n7c2$raw_n7d5 +- - 0 =PieceGrabbedFromFB +- - 1 =PieceGrabbedFromFB$_n7c2_n7c6$true +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n7bf_n7d9$false 3 CWise Stop CCWise +.names RTRotaryMotor$_n7bf_n7d9$false +Stop +# RTVerticalMotor = 1 +.mv RTVerticalMotor$_n7bf_n7da$false 3 GoUp GoDown Stop +.names RTVerticalMotor$_n7bf_n7da$false +GoDown +# if/else (RTVerticalMotor == 1) +.mv RTVerticalMotor$_n7bf$raw_n7dc 3 GoUp GoDown Stop +.names RTVerticalMotor$_n7c2$raw_n7cc RTVerticalMotor$_n7bf_n7da$false _n7bf RTVerticalMotor$_n7bf$raw_n7dc +- - 0 =RTVerticalMotor$_n7bf_n7da$false +- - 1 =RTVerticalMotor$_n7c2$raw_n7cc +.mv RTRotaryMotor$_n7bf$raw_n7de 3 CWise Stop CCWise +.names RTRotaryMotor$_n7c2$raw_n7ce RTRotaryMotor$_n7bf_n7d9$false _n7bf RTRotaryMotor$_n7bf$raw_n7de +- - 0 =RTRotaryMotor$_n7bf_n7d9$false +- - 1 =RTRotaryMotor$_n7c2$raw_n7ce +.mv TableLoaded$_n7bf$raw_n7e3 2 Y N +.names TableLoaded$_n7c2$raw_n7d3 TableLoaded _n7bf TableLoaded$_n7bf$raw_n7e3 +- - 0 =TableLoaded +- - 1 =TableLoaded$_n7c2$raw_n7d3 +.mv PieceGrabbedFromFB$_n7bf$raw_n7e5 2 Y N +.names PieceGrabbedFromFB$_n7c2$raw_n7d5 PieceGrabbedFromFB _n7bf PieceGrabbedFromFB$_n7bf$raw_n7e5 +- - 0 =PieceGrabbedFromFB +- - 1 =PieceGrabbedFromFB$_n7c2$raw_n7d5 +# if/else (RTOnFB == 0) +.mv RTVerticalMotor$_n7bc$raw_n7ea 3 GoUp GoDown Stop +.names RTVerticalMotor$_n7bf$raw_n7dc RTVerticalMotor$_n779$raw_n7b4 _n7bc RTVerticalMotor$_n7bc$raw_n7ea +- - 0 =RTVerticalMotor$_n779$raw_n7b4 +- - 1 =RTVerticalMotor$_n7bf$raw_n7dc +.mv RTRotaryMotor$_n7bc$raw_n7ec 3 CWise Stop CCWise +.names RTRotaryMotor$_n7bf$raw_n7de RTRotaryMotor$_n779$raw_n7b5 _n7bc RTRotaryMotor$_n7bc$raw_n7ec +- - 0 =RTRotaryMotor$_n779$raw_n7b5 +- - 1 =RTRotaryMotor$_n7bf$raw_n7de +.mv TableLoaded$_n7bc$raw_n7f1 2 Y N +.names TableLoaded$_n7bf$raw_n7e3 TableLoaded _n7bc TableLoaded$_n7bc$raw_n7f1 +- - 0 =TableLoaded +- - 1 =TableLoaded$_n7bf$raw_n7e3 +.mv PieceGrabbedFromFB$_n7bc$raw_n7f3 2 Y N +.names PieceGrabbedFromFB$_n7bf$raw_n7e5 PieceGrabbedFromFB _n7bc PieceGrabbedFromFB$_n7bc$raw_n7f3 +- - 0 =PieceGrabbedFromFB +- - 1 =PieceGrabbedFromFB$_n7bf$raw_n7e5 +.mv _n7f8 2 Y N +.names _n7f8 +N +# RTOnFB == 1 +.names RTOnFB _n7f8 _n7f7 +.def 0 +- =RTOnFB 1 +.mv _n7fa 2 Y N +.names _n7fa +N +# RTOnArm == 1 +.names RTOnArm _n7fa _n7f9 +.def 0 +- =RTOnArm 1 +# RTOnFB == 1 && RTOnArm == 1 +.names _n7f7 _n7f9 _n7fb +.def 0 +1 1 1 +.names _n7fb _n7fc +- =_n7fb +.mv _n7fe 3 CWise Stop CCWise +.names _n7fe +CWise +# RTRotaryMotor == 0 +.names RTRotaryMotor$_n7bc$raw_n7ec _n7fe _n7fd +.def 0 +- =RTRotaryMotor$_n7bc$raw_n7ec 1 +.mv _n800 3 GoUp GoDown Stop +.names _n800 +GoDown +# RTVerticalMotor == 1 +.names RTVerticalMotor$_n7bc$raw_n7ea _n800 _n7ff +.def 0 +- =RTVerticalMotor$_n7bc$raw_n7ea 1 +# RTRotaryMotor == 0 && RTVerticalMotor == 1 +.names _n7fd _n7ff _n801 +.def 0 +1 1 1 +.names _n801 _n802 +- =_n801 +.mv _n804 2 Y N +.names _n804 +Y +# PieceOutFB == 0 +.names PieceOutFB _n804 _n803 +.def 0 +- =PieceOutFB 1 +.names _n803 _n805 +- =_n803 +# TableLoaded = 0 +.mv TableLoaded$_n803_n806$true 2 Y N +.names TableLoaded$_n803_n806$true +Y +# PieceGrabbedFromFB = 0 +.mv PieceGrabbedFromFB$_n803_n807$true 2 Y N +.names PieceGrabbedFromFB$_n803_n807$true +Y +# RTRotaryMotor = CCWiseChoice +.mv RTRotaryMotor$_n803_n808$true 3 CWise Stop CCWise +.names CCWiseChoice RTRotaryMotor$_n803_n808$true +- =CCWiseChoice +# RTVerticalMotor = UpChoice +.mv RTVerticalMotor$_n803_n809$true 3 GoUp GoDown Stop +.names UpChoice RTVerticalMotor$_n803_n809$true +- =UpChoice +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n803_n80a$false 3 CWise Stop CCWise +.names RTRotaryMotor$_n803_n80a$false +Stop +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n803_n80b$false 3 GoUp GoDown Stop +.names RTVerticalMotor$_n803_n80b$false +Stop +# if/else (PieceOutFB == 0) +.mv TableLoaded$_n803$raw_n80c 2 Y N +.names TableLoaded$_n803_n806$true TableLoaded$_n7bc$raw_n7f1 _n803 TableLoaded$_n803$raw_n80c +- - 0 =TableLoaded$_n7bc$raw_n7f1 +- - 1 =TableLoaded$_n803_n806$true +.mv RTVerticalMotor$_n803$raw_n80d 3 GoUp GoDown Stop +.names RTVerticalMotor$_n803_n809$true RTVerticalMotor$_n803_n80b$false _n803 RTVerticalMotor$_n803$raw_n80d +- - 0 =RTVerticalMotor$_n803_n80b$false +- - 1 =RTVerticalMotor$_n803_n809$true +.mv RTRotaryMotor$_n803$raw_n80e 3 CWise Stop CCWise +.names RTRotaryMotor$_n803_n808$true RTRotaryMotor$_n803_n80a$false _n803 RTRotaryMotor$_n803$raw_n80e +- - 0 =RTRotaryMotor$_n803_n80a$false +- - 1 =RTRotaryMotor$_n803_n808$true +.mv PieceGrabbedFromFB$_n803$raw_n80f 2 Y N +.names PieceGrabbedFromFB$_n803_n807$true PieceGrabbedFromFB$_n7bc$raw_n7f3 _n803 PieceGrabbedFromFB$_n803$raw_n80f +- - 0 =PieceGrabbedFromFB$_n7bc$raw_n7f3 +- - 1 =PieceGrabbedFromFB$_n803_n807$true +.mv _n81d 3 CWise Stop CCWise +.names _n81d +CWise +# RTRotaryMotor != 0 +.names RTRotaryMotor$_n7bc$raw_n7ec _n81d _n81c +.def 1 +- =RTRotaryMotor$_n7bc$raw_n7ec 0 +.mv _n81f 3 GoUp GoDown Stop +.names _n81f +GoDown +# RTVerticalMotor == 1 +.names RTVerticalMotor$_n7bc$raw_n7ea _n81f _n81e +.def 0 +- =RTVerticalMotor$_n7bc$raw_n7ea 1 +# RTRotaryMotor != 0 && RTVerticalMotor == 1 +.names _n81c _n81e _n820 +.def 0 +1 1 1 +.names _n820 _n821 +- =_n820 +# RTRotaryMotor = CWiseChoice +.mv RTRotaryMotor$_n820_n822$true 3 CWise Stop CCWise +.names CWiseChoice RTRotaryMotor$_n820_n822$true +- =CWiseChoice +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n820_n823$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n820_n823$true +Stop +.mv _n825 3 CWise Stop CCWise +.names _n825 +CWise +# RTRotaryMotor == 0 +.names RTRotaryMotor$_n7bc$raw_n7ec _n825 _n824 +.def 0 +- =RTRotaryMotor$_n7bc$raw_n7ec 1 +.mv _n827 3 GoUp GoDown Stop +.names _n827 +GoDown +# RTVerticalMotor != 1 +.names RTVerticalMotor$_n7bc$raw_n7ea _n827 _n826 +.def 1 +- =RTVerticalMotor$_n7bc$raw_n7ea 0 +# RTRotaryMotor == 0 && RTVerticalMotor != 1 +.names _n824 _n826 _n828 +.def 0 +1 1 1 +.names _n828 _n829 +- =_n828 +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n828_n82a$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n828_n82a$true +Stop +# RTVerticalMotor = DownChoice +.mv RTVerticalMotor$_n828_n82b$true 3 GoUp GoDown Stop +.names DownChoice RTVerticalMotor$_n828_n82b$true +- =DownChoice +.mv _n82d 3 CWise Stop CCWise +.names _n82d +CWise +# RTRotaryMotor != 0 +.names RTRotaryMotor$_n7bc$raw_n7ec _n82d _n82c +.def 1 +- =RTRotaryMotor$_n7bc$raw_n7ec 0 +.mv _n82f 3 GoUp GoDown Stop +.names _n82f +GoDown +# RTVerticalMotor != 1 +.names RTVerticalMotor$_n7bc$raw_n7ea _n82f _n82e +.def 1 +- =RTVerticalMotor$_n7bc$raw_n7ea 0 +# RTRotaryMotor != 0 && RTVerticalMotor != 1 +.names _n82c _n82e _n830 +.def 0 +1 1 1 +.names _n830 _n831 +- =_n830 +# RTRotaryMotor = CWiseChoice +.mv RTRotaryMotor$_n830_n832$true 3 CWise Stop CCWise +.names CWiseChoice RTRotaryMotor$_n830_n832$true +- =CWiseChoice +# RTVerticalMotor = DownChoice +.mv RTVerticalMotor$_n830_n833$true 3 GoUp GoDown Stop +.names DownChoice RTVerticalMotor$_n830_n833$true +- =DownChoice +# if/else (RTRotaryMotor != 0 && RTVerticalMotor != 1) +.mv RTVerticalMotor$_n830$raw_n835 3 GoUp GoDown Stop +.names RTVerticalMotor$_n830_n833$true RTVerticalMotor$_n7bc$raw_n7ea _n830 RTVerticalMotor$_n830$raw_n835 +- - 0 =RTVerticalMotor$_n7bc$raw_n7ea +- - 1 =RTVerticalMotor$_n830_n833$true +.mv RTRotaryMotor$_n830$raw_n836 3 CWise Stop CCWise +.names RTRotaryMotor$_n830_n832$true RTRotaryMotor$_n7bc$raw_n7ec _n830 RTRotaryMotor$_n830$raw_n836 +- - 0 =RTRotaryMotor$_n7bc$raw_n7ec +- - 1 =RTRotaryMotor$_n830_n832$true +# if/else (RTRotaryMotor == 0 && RTVerticalMotor != 1) +.mv RTVerticalMotor$_n828$raw_n845 3 GoUp GoDown Stop +.names RTVerticalMotor$_n828_n82b$true RTVerticalMotor$_n830$raw_n835 _n828 RTVerticalMotor$_n828$raw_n845 +- - 0 =RTVerticalMotor$_n830$raw_n835 +- - 1 =RTVerticalMotor$_n828_n82b$true +.mv RTRotaryMotor$_n828$raw_n847 3 CWise Stop CCWise +.names RTRotaryMotor$_n828_n82a$true RTRotaryMotor$_n830$raw_n836 _n828 RTRotaryMotor$_n828$raw_n847 +- - 0 =RTRotaryMotor$_n830$raw_n836 +- - 1 =RTRotaryMotor$_n828_n82a$true +# if/else (RTRotaryMotor != 0 && RTVerticalMotor == 1) +.mv RTVerticalMotor$_n820$raw_n855 3 GoUp GoDown Stop +.names RTVerticalMotor$_n820_n823$true RTVerticalMotor$_n828$raw_n845 _n820 RTVerticalMotor$_n820$raw_n855 +- - 0 =RTVerticalMotor$_n828$raw_n845 +- - 1 =RTVerticalMotor$_n820_n823$true +.mv RTRotaryMotor$_n820$raw_n856 3 CWise Stop CCWise +.names RTRotaryMotor$_n820_n822$true RTRotaryMotor$_n828$raw_n847 _n820 RTRotaryMotor$_n820$raw_n856 +- - 0 =RTRotaryMotor$_n828$raw_n847 +- - 1 =RTRotaryMotor$_n820_n822$true +# if/else (RTRotaryMotor == 0 && RTVerticalMotor == 1) +.mv TableLoaded$_n801$raw_n864 2 Y N +.names TableLoaded$_n803$raw_n80c TableLoaded$_n7bc$raw_n7f1 _n801 TableLoaded$_n801$raw_n864 +- - 0 =TableLoaded$_n7bc$raw_n7f1 +- - 1 =TableLoaded$_n803$raw_n80c +.mv RTVerticalMotor$_n801$raw_n865 3 GoUp GoDown Stop +.names RTVerticalMotor$_n803$raw_n80d RTVerticalMotor$_n820$raw_n855 _n801 RTVerticalMotor$_n801$raw_n865 +- - 0 =RTVerticalMotor$_n820$raw_n855 +- - 1 =RTVerticalMotor$_n803$raw_n80d +.mv PieceGrabbedFromFB$_n801$raw_n866 2 Y N +.names PieceGrabbedFromFB$_n803$raw_n80f PieceGrabbedFromFB$_n7bc$raw_n7f3 _n801 PieceGrabbedFromFB$_n801$raw_n866 +- - 0 =PieceGrabbedFromFB$_n7bc$raw_n7f3 +- - 1 =PieceGrabbedFromFB$_n803$raw_n80f +.mv RTRotaryMotor$_n801$raw_n867 3 CWise Stop CCWise +.names RTRotaryMotor$_n803$raw_n80e RTRotaryMotor$_n820$raw_n856 _n801 RTRotaryMotor$_n801$raw_n867 +- - 0 =RTRotaryMotor$_n820$raw_n856 +- - 1 =RTRotaryMotor$_n803$raw_n80e +# if/else (RTOnFB == 1 && RTOnArm == 1) +.mv TableLoaded$_n7fb$raw_n874 2 Y N +.names TableLoaded$_n801$raw_n864 TableLoaded$_n7bc$raw_n7f1 _n7fb TableLoaded$_n7fb$raw_n874 +- - 0 =TableLoaded$_n7bc$raw_n7f1 +- - 1 =TableLoaded$_n801$raw_n864 +.mv RTVerticalMotor$_n7fb$raw_n875 3 GoUp GoDown Stop +.names RTVerticalMotor$_n801$raw_n865 RTVerticalMotor$_n7bc$raw_n7ea _n7fb RTVerticalMotor$_n7fb$raw_n875 +- - 0 =RTVerticalMotor$_n7bc$raw_n7ea +- - 1 =RTVerticalMotor$_n801$raw_n865 +.mv RTRotaryMotor$_n7fb$raw_n876 3 CWise Stop CCWise +.names RTRotaryMotor$_n801$raw_n867 RTRotaryMotor$_n7bc$raw_n7ec _n7fb RTRotaryMotor$_n7fb$raw_n876 +- - 0 =RTRotaryMotor$_n7bc$raw_n7ec +- - 1 =RTRotaryMotor$_n801$raw_n867 +.mv PieceGrabbedFromFB$_n7fb$raw_n877 2 Y N +.names PieceGrabbedFromFB$_n801$raw_n866 PieceGrabbedFromFB$_n7bc$raw_n7f3 _n7fb PieceGrabbedFromFB$_n7fb$raw_n877 +- - 0 =PieceGrabbedFromFB$_n7bc$raw_n7f3 +- - 1 =PieceGrabbedFromFB$_n801$raw_n866 +.mv _n885 2 Y N +.names _n885 +Y +# RTOnArm == 0 +.names RTOnArm _n885 _n884 +.def 0 +- =RTOnArm 1 +.names _n884 _n886 +- =_n884 +# RTRotaryMotor = CWiseChoice +.mv RTRotaryMotor$_n884_n887$true 3 CWise Stop CCWise +.names CWiseChoice RTRotaryMotor$_n884_n887$true +- =CWiseChoice +.mv _n889 3 GoUp GoDown Stop +.names _n889 +GoDown +# RTVerticalMotor == 1 +.names RTVerticalMotor$_n7fb$raw_n875 _n889 _n888 +.def 0 +- =RTVerticalMotor$_n7fb$raw_n875 1 +.names _n888 _n88a +- =_n888 +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n888_n88b$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n888_n88b$true +Stop +# RTVerticalMotor = 1 +.mv RTVerticalMotor$_n888_n88c$false 3 GoUp GoDown Stop +.names RTVerticalMotor$_n888_n88c$false +GoDown +# if/else (RTVerticalMotor == 1) +.mv RTVerticalMotor$_n888$raw_n88e 3 GoUp GoDown Stop +.names RTVerticalMotor$_n888_n88b$true RTVerticalMotor$_n888_n88c$false _n888 RTVerticalMotor$_n888$raw_n88e +- - 0 =RTVerticalMotor$_n888_n88c$false +- - 1 =RTVerticalMotor$_n888_n88b$true +# if/else (RTOnArm == 0) +.mv RTVerticalMotor$_n884$raw_n89e 3 GoUp GoDown Stop +.names RTVerticalMotor$_n888$raw_n88e RTVerticalMotor$_n7fb$raw_n875 _n884 RTVerticalMotor$_n884$raw_n89e +- - 0 =RTVerticalMotor$_n7fb$raw_n875 +- - 1 =RTVerticalMotor$_n888$raw_n88e +.mv RTRotaryMotor$_n884$raw_n89f 3 CWise Stop CCWise +.names RTRotaryMotor$_n884_n887$true RTRotaryMotor$_n7fb$raw_n876 _n884 RTRotaryMotor$_n884$raw_n89f +- - 0 =RTRotaryMotor$_n7fb$raw_n876 +- - 1 =RTRotaryMotor$_n884_n887$true +# if/else (RTOnTop == 1 && RTOnBottom == 1) +.mv RTVerticalMotor$_n7ba$raw_n8ae 3 GoUp GoDown Stop +.names RTVerticalMotor$_n884$raw_n89e RTVerticalMotor$_n779$raw_n7b4 _n7ba RTVerticalMotor$_n7ba$raw_n8ae +- - 0 =RTVerticalMotor$_n779$raw_n7b4 +- - 1 =RTVerticalMotor$_n884$raw_n89e +.mv RTRotaryMotor$_n7ba$raw_n8b0 3 CWise Stop CCWise +.names RTRotaryMotor$_n884$raw_n89f RTRotaryMotor$_n779$raw_n7b5 _n7ba RTRotaryMotor$_n7ba$raw_n8b0 +- - 0 =RTRotaryMotor$_n779$raw_n7b5 +- - 1 =RTRotaryMotor$_n884$raw_n89f +.mv TableLoaded$_n7ba$raw_n8b5 2 Y N +.names TableLoaded$_n7fb$raw_n874 TableLoaded _n7ba TableLoaded$_n7ba$raw_n8b5 +- - 0 =TableLoaded +- - 1 =TableLoaded$_n7fb$raw_n874 +.mv PieceGrabbedFromFB$_n7ba$raw_n8b7 2 Y N +.names PieceGrabbedFromFB$_n7fb$raw_n877 PieceGrabbedFromFB _n7ba PieceGrabbedFromFB$_n7ba$raw_n8b7 +- - 0 =PieceGrabbedFromFB +- - 1 =PieceGrabbedFromFB$_n7fb$raw_n877 +.mv _n8bc 2 Y N +.names _n8bc +Y +# RTOnBottom == 0 +.names RTOnBottom _n8bc _n8bb +.def 0 +- =RTOnBottom 1 +.names _n8bb _n8bd +- =_n8bb +.mv _n8bf 2 Y N +.names _n8bf +Y +# RTOnFB == 0 +.names RTOnFB _n8bf _n8be +.def 0 +- =RTOnFB 1 +.names _n8be _n8c0 +- =_n8be +.mv _n8c2 2 Y N +.names _n8c2 +Y +# PieceOutFB == 0 +.names PieceOutFB _n8c2 _n8c1 +.def 0 +- =PieceOutFB 1 +.names _n8c1 _n8c3 +- =_n8c1 +# PieceGrabbedFromFB = 0 +.mv PieceGrabbedFromFB$_n8c1_n8c4$true 2 Y N +.names PieceGrabbedFromFB$_n8c1_n8c4$true +Y +# RTRotaryMotor = CCWiseChoice +.mv RTRotaryMotor$_n8c1_n8c5$true 3 CWise Stop CCWise +.names CCWiseChoice RTRotaryMotor$_n8c1_n8c5$true +- =CCWiseChoice +# RTVerticalMotor = UpChoice +.mv RTVerticalMotor$_n8c1_n8c6$true 3 GoUp GoDown Stop +.names UpChoice RTVerticalMotor$_n8c1_n8c6$true +- =UpChoice +# TableLoaded = 0 +.mv TableLoaded$_n8c1_n8c7$true 2 Y N +.names TableLoaded$_n8c1_n8c7$true +Y +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n8c1_n8c8$false 3 CWise Stop CCWise +.names RTRotaryMotor$_n8c1_n8c8$false +Stop +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n8c1_n8c9$false 3 GoUp GoDown Stop +.names RTVerticalMotor$_n8c1_n8c9$false +Stop +# if/else (PieceOutFB == 0) +.mv TableLoaded$_n8c1$raw_n8ca 2 Y N +.names TableLoaded$_n8c1_n8c7$true TableLoaded$_n7ba$raw_n8b5 _n8c1 TableLoaded$_n8c1$raw_n8ca +- - 0 =TableLoaded$_n7ba$raw_n8b5 +- - 1 =TableLoaded$_n8c1_n8c7$true +.mv RTVerticalMotor$_n8c1$raw_n8cb 3 GoUp GoDown Stop +.names RTVerticalMotor$_n8c1_n8c6$true RTVerticalMotor$_n8c1_n8c9$false _n8c1 RTVerticalMotor$_n8c1$raw_n8cb +- - 0 =RTVerticalMotor$_n8c1_n8c9$false +- - 1 =RTVerticalMotor$_n8c1_n8c6$true +.mv RTRotaryMotor$_n8c1$raw_n8cc 3 CWise Stop CCWise +.names RTRotaryMotor$_n8c1_n8c5$true RTRotaryMotor$_n8c1_n8c8$false _n8c1 RTRotaryMotor$_n8c1$raw_n8cc +- - 0 =RTRotaryMotor$_n8c1_n8c8$false +- - 1 =RTRotaryMotor$_n8c1_n8c5$true +.mv PieceGrabbedFromFB$_n8c1$raw_n8cd 2 Y N +.names PieceGrabbedFromFB$_n8c1_n8c4$true PieceGrabbedFromFB$_n7ba$raw_n8b7 _n8c1 PieceGrabbedFromFB$_n8c1$raw_n8cd +- - 0 =PieceGrabbedFromFB$_n7ba$raw_n8b7 +- - 1 =PieceGrabbedFromFB$_n8c1_n8c4$true +# if/else (RTOnFB == 0) +.mv TableLoaded$_n8be$raw_n8da 2 Y N +.names TableLoaded$_n8c1$raw_n8ca TableLoaded$_n7ba$raw_n8b5 _n8be TableLoaded$_n8be$raw_n8da +- - 0 =TableLoaded$_n7ba$raw_n8b5 +- - 1 =TableLoaded$_n8c1$raw_n8ca +.mv RTVerticalMotor$_n8be$raw_n8db 3 GoUp GoDown Stop +.names RTVerticalMotor$_n8c1$raw_n8cb RTVerticalMotor$_n7ba$raw_n8ae _n8be RTVerticalMotor$_n8be$raw_n8db +- - 0 =RTVerticalMotor$_n7ba$raw_n8ae +- - 1 =RTVerticalMotor$_n8c1$raw_n8cb +.mv PieceGrabbedFromFB$_n8be$raw_n8dc 2 Y N +.names PieceGrabbedFromFB$_n8c1$raw_n8cd PieceGrabbedFromFB$_n7ba$raw_n8b7 _n8be PieceGrabbedFromFB$_n8be$raw_n8dc +- - 0 =PieceGrabbedFromFB$_n7ba$raw_n8b7 +- - 1 =PieceGrabbedFromFB$_n8c1$raw_n8cd +.mv RTRotaryMotor$_n8be$raw_n8dd 3 CWise Stop CCWise +.names RTRotaryMotor$_n8c1$raw_n8cc RTRotaryMotor$_n7ba$raw_n8b0 _n8be RTRotaryMotor$_n8be$raw_n8dd +- - 0 =RTRotaryMotor$_n7ba$raw_n8b0 +- - 1 =RTRotaryMotor$_n8c1$raw_n8cc +.mv _n8eb 2 Y N +.names _n8eb +N +# RTOnFB == 1 +.names RTOnFB _n8eb _n8ea +.def 0 +- =RTOnFB 1 +.mv _n8ed 2 Y N +.names _n8ed +N +# RTOnArm == 1 +.names RTOnArm _n8ed _n8ec +.def 0 +- =RTOnArm 1 +# RTOnFB == 1 && RTOnArm == 1 +.names _n8ea _n8ec _n8ee +.def 0 +1 1 1 +.names _n8ee _n8ef +- =_n8ee +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n8ee_n8f0$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n8ee_n8f0$true +Stop +.mv _n8f2 3 CWise Stop CCWise +.names _n8f2 +CWise +# RTRotaryMotor == 0 +.names RTRotaryMotor$_n8be$raw_n8dd _n8f2 _n8f1 +.def 0 +- =RTRotaryMotor$_n8be$raw_n8dd 1 +.names _n8f1 _n8f3 +- =_n8f1 +# RTRotaryMotor = 1 +.mv RTRotaryMotor$_n8f1_n8f4$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n8f1_n8f4$true +Stop +# RTRotaryMotor = 0 +.mv RTRotaryMotor$_n8f1_n8f5$false 3 CWise Stop CCWise +.names RTRotaryMotor$_n8f1_n8f5$false +CWise +# if/else (RTRotaryMotor == 0) +.mv RTRotaryMotor$_n8f1$raw_n8f8 3 CWise Stop CCWise +.names RTRotaryMotor$_n8f1_n8f4$true RTRotaryMotor$_n8f1_n8f5$false _n8f1 RTRotaryMotor$_n8f1$raw_n8f8 +- - 0 =RTRotaryMotor$_n8f1_n8f5$false +- - 1 =RTRotaryMotor$_n8f1_n8f4$true +# if/else (RTOnFB == 1 && RTOnArm == 1) +.mv RTVerticalMotor$_n8ee$raw_n907 3 GoUp GoDown Stop +.names RTVerticalMotor$_n8ee_n8f0$true RTVerticalMotor$_n8be$raw_n8db _n8ee RTVerticalMotor$_n8ee$raw_n907 +- - 0 =RTVerticalMotor$_n8be$raw_n8db +- - 1 =RTVerticalMotor$_n8ee_n8f0$true +.mv RTRotaryMotor$_n8ee$raw_n909 3 CWise Stop CCWise +.names RTRotaryMotor$_n8f1$raw_n8f8 RTRotaryMotor$_n8be$raw_n8dd _n8ee RTRotaryMotor$_n8ee$raw_n909 +- - 0 =RTRotaryMotor$_n8be$raw_n8dd +- - 1 =RTRotaryMotor$_n8f1$raw_n8f8 +.mv _n917 2 Y N +.names _n917 +Y +# RTOnArm == 0 +.names RTOnArm _n917 _n916 +.def 0 +- =RTOnArm 1 +.names _n916 _n918 +- =_n916 +# RTRotaryMotor = 0 +.mv RTRotaryMotor$_n916_n919$true 3 CWise Stop CCWise +.names RTRotaryMotor$_n916_n919$true +CWise +# RTVerticalMotor = 2 +.mv RTVerticalMotor$_n916_n91a$true 3 GoUp GoDown Stop +.names RTVerticalMotor$_n916_n91a$true +Stop +# if/else (RTOnArm == 0) +.mv RTVerticalMotor$_n916$raw_n91c 3 GoUp GoDown Stop +.names RTVerticalMotor$_n916_n91a$true RTVerticalMotor$_n8ee$raw_n907 _n916 RTVerticalMotor$_n916$raw_n91c +- - 0 =RTVerticalMotor$_n8ee$raw_n907 +- - 1 =RTVerticalMotor$_n916_n91a$true +.mv RTRotaryMotor$_n916$raw_n91e 3 CWise Stop CCWise +.names RTRotaryMotor$_n916_n919$true RTRotaryMotor$_n8ee$raw_n909 _n916 RTRotaryMotor$_n916$raw_n91e +- - 0 =RTRotaryMotor$_n8ee$raw_n909 +- - 1 =RTRotaryMotor$_n916_n919$true +# if/else (RTOnBottom == 0) +.mv TableLoaded$_n8bb$raw_n92b 2 Y N +.names TableLoaded$_n8be$raw_n8da TableLoaded$_n7ba$raw_n8b5 _n8bb TableLoaded$_n8bb$raw_n92b +- - 0 =TableLoaded$_n7ba$raw_n8b5 +- - 1 =TableLoaded$_n8be$raw_n8da +.mv RTVerticalMotor$_n8bb$raw_n92c 3 GoUp GoDown Stop +.names RTVerticalMotor$_n916$raw_n91c RTVerticalMotor$_n7ba$raw_n8ae _n8bb RTVerticalMotor$_n8bb$raw_n92c +- - 0 =RTVerticalMotor$_n7ba$raw_n8ae +- - 1 =RTVerticalMotor$_n916$raw_n91c +.mv RTRotaryMotor$_n8bb$raw_n92d 3 CWise Stop CCWise +.names RTRotaryMotor$_n916$raw_n91e RTRotaryMotor$_n7ba$raw_n8b0 _n8bb RTRotaryMotor$_n8bb$raw_n92d +- - 0 =RTRotaryMotor$_n7ba$raw_n8b0 +- - 1 =RTRotaryMotor$_n916$raw_n91e +.mv PieceGrabbedFromFB$_n8bb$raw_n92e 2 Y N +.names PieceGrabbedFromFB$_n8be$raw_n8dc PieceGrabbedFromFB$_n7ba$raw_n8b7 _n8bb PieceGrabbedFromFB$_n8bb$raw_n92e +- - 0 =PieceGrabbedFromFB$_n7ba$raw_n8b7 +- - 1 =PieceGrabbedFromFB$_n8be$raw_n8dc +# case (TableLoaded ) +.mv TableLoaded$_n776$raw_n943 2 Y N +.names TableLoaded$_n8bb$raw_n92b TableLoaded _n776 TableLoaded$_n776$raw_n943 +- - 0 =TableLoaded +- - 1 =TableLoaded$_n8bb$raw_n92b +.mv RTVerticalMotor$_n776$raw_n944 3 GoUp GoDown Stop +.names RTVerticalMotor$_n8bb$raw_n92c RTVerticalMotor _n776 RTVerticalMotor$_n776$raw_n944 +- - 0 =RTVerticalMotor +- - 1 =RTVerticalMotor$_n8bb$raw_n92c +.mv PieceGrabbedFromFB$_n776$raw_n945 2 Y N +.names PieceGrabbedFromFB$_n8bb$raw_n92e PieceGrabbedFromFB _n776 PieceGrabbedFromFB$_n776$raw_n945 +- - 0 =PieceGrabbedFromFB +- - 1 =PieceGrabbedFromFB$_n8bb$raw_n92e +.mv RTRotaryMotor$_n776$raw_n946 3 CWise Stop CCWise +.names RTRotaryMotor$_n8bb$raw_n92d RTRotaryMotor _n776 RTRotaryMotor$_n776$raw_n946 +- - 0 =RTRotaryMotor +- - 1 =RTRotaryMotor$_n8bb$raw_n92d +.mv TableLoaded$_n5b7$raw_n947 2 Y N +.names TableLoaded$_n5ba$raw_n629 TableLoaded$_n776$raw_n943 _n5b7 TableLoaded$_n5b7$raw_n947 +- - 0 =TableLoaded$_n776$raw_n943 +- - 1 =TableLoaded$_n5ba$raw_n629 +.mv RTVerticalMotor$_n5b7$raw_n949 3 GoUp GoDown Stop +.names RTVerticalMotor$_n70d$raw_n768 RTVerticalMotor$_n776$raw_n944 _n5b7 RTVerticalMotor$_n5b7$raw_n949 +- - 0 =RTVerticalMotor$_n776$raw_n944 +- - 1 =RTVerticalMotor$_n70d$raw_n768 +.mv RTRotaryMotor$_n5b7$raw_n94a 3 CWise Stop CCWise +.names RTRotaryMotor$_n70d$raw_n769 RTRotaryMotor$_n776$raw_n946 _n5b7 RTRotaryMotor$_n5b7$raw_n94a +- - 0 =RTRotaryMotor$_n776$raw_n946 +- - 1 =RTRotaryMotor$_n70d$raw_n769 +.mv RTOutReady$_n5b7$raw_n950 2 Y N +.names RTOutReady$_n631$raw_n6fe RTOutReady _n5b7 RTOutReady$_n5b7$raw_n950 +- - 0 =RTOutReady +- - 1 =RTOutReady$_n631$raw_n6fe +.mv PieceGrabbedFromFB$_n5b7$raw_n955 2 Y N +.names PieceGrabbedFromFB PieceGrabbedFromFB$_n776$raw_n945 _n5b7 PieceGrabbedFromFB$_n5b7$raw_n955 +- - 0 =PieceGrabbedFromFB$_n776$raw_n945 +- - 1 =PieceGrabbedFromFB +.mv _n958 2 Y N +.names _n958 +N +# PieceOutFB == 1 +.names PieceOutFB _n958 _n957 +.def 0 +- =PieceOutFB 1 +.mv _n95a 2 Y N +.names _n95a +Y +# PieceGrabbedFromFB == 0 +.names PieceGrabbedFromFB$_n5b7$raw_n955 _n95a _n959 +.def 0 +- =PieceGrabbedFromFB$_n5b7$raw_n955 1 +# PieceOutFB == 1 && PieceGrabbedFromFB == 0 +.names _n957 _n959 _n95b +.def 0 +1 1 1 +.names _n95b _n95c +- =_n95b +# PieceGrabbedFromFB = 1 +.mv PieceGrabbedFromFB$_n95b_n95d$true 2 Y N +.names PieceGrabbedFromFB$_n95b_n95d$true +N +# if/else (PieceOutFB == 1 && PieceGrabbedFromFB == 0) +.mv PieceGrabbedFromFB$_n95b$raw_n961 2 Y N +.names PieceGrabbedFromFB$_n95b_n95d$true PieceGrabbedFromFB$_n5b7$raw_n955 _n95b PieceGrabbedFromFB$_n95b$raw_n961 +- - 0 =PieceGrabbedFromFB$_n5b7$raw_n955 +- - 1 =PieceGrabbedFromFB$_n95b_n95d$true +.mv _n973 2 Y N +.names _n973 +Y +# RTOutReady == 0 +.names RTOutReady$_n5b7$raw_n950 _n973 _n972 +.def 0 +- =RTOutReady$_n5b7$raw_n950 1 +.mv _n975 2 Y N +.names _n975 +Y +# PieceGrabbedFromRT == 0 +.names PieceGrabbedFromRT _n975 _n974 +.def 0 +- =PieceGrabbedFromRT 1 +# RTOutReady == 0 && PieceGrabbedFromRT == 0 +.names _n972 _n974 _n976 +.def 0 +1 1 1 +.names _n976 _n977 +- =_n976 +# RTOutReady = 1 +.mv RTOutReady$_n976_n978$true 2 Y N +.names RTOutReady$_n976_n978$true +N +# if/else (RTOutReady == 0 && PieceGrabbedFromRT == 0) +.mv RTOutReady$_n976$raw_n97a 2 Y N +.names RTOutReady$_n976_n978$true RTOutReady$_n5b7$raw_n950 _n976 RTOutReady$_n976$raw_n97a +- - 0 =RTOutReady$_n5b7$raw_n950 +- - 1 =RTOutReady$_n976_n978$true +# conflict arbitrators +.names _n5b7 _n5bc _n5f8 _n5fb _n776 _n7bb _n7be _n7c1 _n7c4 _n7fc _n802 _n805 _n8bd _n8c0 _n8c3 _n98d +.def 0 + 1 1 1 1 - - - - - - - - - - - 1 + 0 - - - 1 1 1 1 1 - - - - - - 1 + 0 - - - 1 1 - - - 1 1 1 - - - 1 + 0 - - - 1 - - - - - - - 1 1 1 1 +.mv _n98e 2 Y N +.names _n98d TableLoaded$_n5b7$raw_n947 TableLoaded _n98e +1 - - =TableLoaded$_n5b7$raw_n947 +0 - - =TableLoaded +.names UpChoice$raw_n5b0 UpChoice +- =UpChoice$raw_n5b0 +.names CCWiseChoice$raw_n5af CCWiseChoice +- =CCWiseChoice$raw_n5af +.names DownChoice$raw_n5b1 DownChoice +- =DownChoice$raw_n5b1 +.names _n5b7 _n5bc _n5cd _n5d1 _n5f8 _n5fb _n632 _n661 _n667 _n6d5 _n6d9 _n977 _n99d +.def 0 + 1 1 1 1 - - - - - - - - 1 + 1 1 - - 1 1 - - - - - - 1 + 1 1 - - 1 0 - - - - - - 1 + 1 - - - - - 1 1 1 - - - 1 + 1 - - - - - 1 - - 1 1 - 1 + - - - - - - - - - - - 1 1 +.mv _n99e 2 Y N +.names _n99d RTOutReady$_n976$raw_n97a RTOutReady _n99e +1 - - =RTOutReady$_n976$raw_n97a +0 - - =RTOutReady +.names CWiseChoice$raw_n5ae CWiseChoice +- =CWiseChoice$raw_n5ae +.names _n5b7 _n5bc _n5bf _n5cd _n5f8 _n5fb _n632 _n635 _n639 _n661 _n667 _n670 _n678 _n680 _n6d5 _n6d9 _n70f _n712 _n72a _n753 _n776 _n77b _n77e _n78c _n7a5 _n7bb _n7be _n7c1 _n7c4 _n7fc _n802 _n805 _n821 _n829 _n831 _n886 _n88a _n8bd _n8c0 _n8c3 _n8ef _n918 _n9ad +.def 0 + 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - 1 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - 1 - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - 1 - - 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - 1 - - 1 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - 1 - - 1 0 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - 1 - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - 1 - - - - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - - - - - - - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - - - - - - - 1 - - 1 - - - - - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 1 - - 1 - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - 1 1 1 1 - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - 1 1 1 0 - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - 1 1 0 - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - 1 - - - 1 1 1 - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - 1 - - - 1 1 0 - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - 1 - - - 1 0 - 1 - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - 1 - - - 1 0 - 0 1 - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - 1 - - - 1 0 - 0 0 1 - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - 1 - - - - - - - - - 1 1 - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - 1 - - - - - - - - - 1 0 - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - 1 1 1 - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - 1 1 0 - - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - 1 - - 1 - 1 + 0 - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - 1 - - - 1 1 +.mv _n9ae 3 GoUp GoDown Stop +.names _n9ad RTVerticalMotor$_n5b7$raw_n949 RTVerticalMotor _n9ae +1 - - =RTVerticalMotor$_n5b7$raw_n949 +0 - - =RTVerticalMotor +.names _n5b7 _n776 _n7bb _n7be _n7c1 _n7c4 _n7fc _n802 _n805 _n8bd _n8c0 _n8c3 _n95c _n9bd +.def 0 + 0 1 1 1 1 1 - - - - - - - 1 + 0 1 1 - - - 1 1 1 - - - - 1 + 0 1 - - - - - - - 1 1 1 - 1 + - - - - - - - - - - - - 1 1 +.mv _n9be 2 Y N +.names _n9bd PieceGrabbedFromFB$_n95b$raw_n961 PieceGrabbedFromFB _n9be +1 - - =PieceGrabbedFromFB$_n95b$raw_n961 +0 - - =PieceGrabbedFromFB +.names _n5b7 _n5bc _n5bf _n5cd _n5d1 _n5d6 _n5f8 _n5fb _n632 _n635 _n661 _n667 _n670 _n678 _n680 _n6d5 _n70f _n712 _n72a _n72e _n753 _n776 _n77b _n77e _n78c _n790 _n7a5 _n7bb _n7be _n7c1 _n7c4 _n7fc _n802 _n805 _n821 _n829 _n831 _n886 _n8bd _n8c0 _n8c3 _n8ef _n8f3 _n918 _n9cd +.def 0 + 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 - 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 - - - - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - 1 - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - 1 - 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - 1 - 1 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - 1 - 1 0 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - 1 - - - - - - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - - - - - - - 1 - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - - - - - - - 1 - 1 0 - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - - - - - - - 1 - - - 1 - - - - - - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 1 - 1 1 - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 1 - 1 0 - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 1 - - - 1 - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - 1 1 1 1 - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - 1 1 1 0 - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - 1 1 0 - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - 1 - - - 1 1 1 - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - 1 - - - 1 1 0 - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - 1 - - - 1 0 - 1 - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - 1 - - - 1 0 - 0 1 - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - 1 - - - 1 0 - 0 0 1 - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - 1 - - - - - - - - - 1 - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - 1 1 1 - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - 1 1 0 - - - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - 1 - - 1 1 - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - 1 - - 1 0 - 1 + 0 - - - - - - - - - - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - 1 - - - - 1 1 +.mv _n9ce 3 CWise Stop CCWise +.names _n9cd RTRotaryMotor$_n5b7$raw_n94a RTRotaryMotor _n9ce +1 - - =RTRotaryMotor$_n5b7$raw_n94a +0 - - =RTRotaryMotor +# non-blocking assignments +# latches +.r TableLoaded$raw_n5b6 TableLoaded +- =TableLoaded$raw_n5b6 +.latch _n98e TableLoaded +.r RTOutReady$raw_n5b5 RTOutReady +- =RTOutReady$raw_n5b5 +.latch _n99e RTOutReady +.r RTVerticalMotor$raw_n5b3 RTVerticalMotor +- =RTVerticalMotor$raw_n5b3 +.latch _n9ae RTVerticalMotor +.r RTRotaryMotor$raw_n5b2 RTRotaryMotor +- =RTRotaryMotor$raw_n5b2 +.latch _n9ce RTRotaryMotor +.r PieceGrabbedFromFB$raw_n5b4 PieceGrabbedFromFB +- =PieceGrabbedFromFB$raw_n5b4 +.latch _n9be PieceGrabbedFromFB +# quasi-continuous assignment +.end + + +.model Press +# I/O ports +.inputs PressMotor +.outputs PressPosition +.mv PressMotor 3 GoUp GoDown Stop +.mv PressPosition 3 Top Mid Bot +# PressPosition = 1 +.mv PressPosition$raw_n9dd 3 Top Mid Bot +.names PressPosition$raw_n9dd +Mid +# non-blocking assignments for initial +.mv _n9df 3 GoUp GoDown Stop +.names _n9df +GoUp +# PressMotor == 0 +.names PressMotor _n9df _n9de +.def 0 +- =PressMotor 1 +.names _n9de _n9e0 +- =_n9de +.mv _n9e3 3 Top Mid Bot +.names _n9e3 +Mid +.names PressPosition _n9e3 _n9e2 +.def 0 +- =PressPosition 1 +.names _n9e2 _n9e1 +1 1 +0 0 +# PressPosition = 0 +.mv PressPosition$_n9e1_n9e4$true 3 Top Mid Bot +.names PressPosition$_n9e1_n9e4$true +Top +.mv _n9e7 3 Top Mid Bot +.names _n9e7 +Bot +.names PressPosition _n9e7 _n9e6 +.def 0 +- =PressPosition 1 +.names _n9e6 _n9e5 +1 1 +0 0 +# PressPosition = 1 +.mv PressPosition$_n9e5_n9e8$true 3 Top Mid Bot +.names PressPosition$_n9e5_n9e8$true +Mid +# case (PressPosition ) +.mv PressPosition$_n9e5$raw_n9eb 3 Top Mid Bot +.names PressPosition$_n9e5_n9e8$true PressPosition _n9e5 PressPosition$_n9e5$raw_n9eb +- - 0 =PressPosition +- - 1 =PressPosition$_n9e5_n9e8$true +.mv PressPosition$_n9e1$raw_n9ec 3 Top Mid Bot +.names PressPosition$_n9e1_n9e4$true PressPosition$_n9e5$raw_n9eb _n9e1 PressPosition$_n9e1$raw_n9ec +- - 0 =PressPosition$_n9e5$raw_n9eb +- - 1 =PressPosition$_n9e1_n9e4$true +# if/else (PressMotor == 0) +.mv PressPosition$_n9de$raw_n9f2 3 Top Mid Bot +.names PressPosition$_n9e1$raw_n9ec PressPosition _n9de PressPosition$_n9de$raw_n9f2 +- - 0 =PressPosition +- - 1 =PressPosition$_n9e1$raw_n9ec +.mv _n9f4 3 GoUp GoDown Stop +.names _n9f4 +GoDown +# PressMotor == 1 +.names PressMotor _n9f4 _n9f3 +.def 0 +- =PressMotor 1 +.names _n9f3 _n9f5 +- =_n9f3 +.mv _n9f8 3 Top Mid Bot +.names _n9f8 +Top +.names PressPosition$_n9de$raw_n9f2 _n9f8 _n9f7 +.def 0 +- =PressPosition$_n9de$raw_n9f2 1 +.names _n9f7 _n9f6 +1 1 +0 0 +# PressPosition = 1 +.mv PressPosition$_n9f6_n9f9$true 3 Top Mid Bot +.names PressPosition$_n9f6_n9f9$true +Mid +.mv _n9fc 3 Top Mid Bot +.names _n9fc +Mid +.names PressPosition$_n9de$raw_n9f2 _n9fc _n9fb +.def 0 +- =PressPosition$_n9de$raw_n9f2 1 +.names _n9fb _n9fa +1 1 +0 0 +# PressPosition = 2 +.mv PressPosition$_n9fa_n9fd$true 3 Top Mid Bot +.names PressPosition$_n9fa_n9fd$true +Bot +# case (PressPosition ) +.mv PressPosition$_n9fa$raw_n9fe 3 Top Mid Bot +.names PressPosition$_n9fa_n9fd$true PressPosition$_n9de$raw_n9f2 _n9fa PressPosition$_n9fa$raw_n9fe +- - 0 =PressPosition$_n9de$raw_n9f2 +- - 1 =PressPosition$_n9fa_n9fd$true +.mv PressPosition$_n9f6$raw_na02 3 Top Mid Bot +.names PressPosition$_n9f6_n9f9$true PressPosition$_n9fa$raw_n9fe _n9f6 PressPosition$_n9f6$raw_na02 +- - 0 =PressPosition$_n9fa$raw_n9fe +- - 1 =PressPosition$_n9f6_n9f9$true +# if/else (PressMotor == 1) +.mv PressPosition$_n9f3$raw_na06 3 Top Mid Bot +.names PressPosition$_n9f6$raw_na02 PressPosition$_n9de$raw_n9f2 _n9f3 PressPosition$_n9f3$raw_na06 +- - 0 =PressPosition$_n9de$raw_n9f2 +- - 1 =PressPosition$_n9f6$raw_na02 +# conflict arbitrators +.names _n9e0 _n9e1 _n9e5 _n9f5 _n9f6 _n9fa _na0a +.def 0 + 1 1 - - - - 1 + 1 0 1 - - - 1 + - - - 1 1 - 1 + - - - 1 0 1 1 +.mv _na0b 3 Top Mid Bot +.names _na0a PressPosition$_n9f3$raw_na06 PressPosition _na0b +1 - - =PressPosition$_n9f3$raw_na06 +0 - - =PressPosition +# non-blocking assignments +# latches +.r PressPosition$raw_n9dd PressPosition +- =PressPosition$raw_n9dd +.latch _na0b PressPosition +# quasi-continuous assignment +.end + + +.model PressCNTR +# I/O ports +.outputs PressReadyToBeUnLoaded +.outputs PressReadyToBeLoaded +.inputs ArmLoadedPress +.inputs ArmUnLoadedPress +.outputs PressMotor +.inputs PressPosition +.mv PressReadyToBeUnLoaded 2 Y N +.mv PressReadyToBeLoaded 2 Y N +.mv ArmLoadedPress 2 Y N +.mv ArmUnLoadedPress 2 Y N +.mv PressLoaded 2 Y N +.mv PressMotor 3 GoUp GoDown Stop +.mv PressPosition 3 Top Mid Bot +# PressMotor = 2 +.mv PressMotor$raw_na0d 3 GoUp GoDown Stop +.names PressMotor$raw_na0d +Stop +# PressReadyToBeLoaded = 1 +.mv PressReadyToBeLoaded$raw_na0e 2 Y N +.names PressReadyToBeLoaded$raw_na0e +N +# PressReadyToBeUnLoaded = 1 +.mv PressReadyToBeUnLoaded$raw_na0f 2 Y N +.names PressReadyToBeUnLoaded$raw_na0f +N +# PressLoaded = 1 +.mv PressLoaded$raw_na10 2 Y N +.names PressLoaded$raw_na10 +N +# non-blocking assignments for initial +.mv _na13 2 Y N +.names _na13 +Y +.names PressLoaded _na13 _na12 +.def 0 +- =PressLoaded 1 +.names _na12 _na11 +1 1 +0 0 +.mv _na16 3 Top Mid Bot +.names _na16 +Top +.names PressPosition _na16 _na15 +.def 0 +- =PressPosition 1 +.names _na15 _na14 +1 1 +0 0 +# PressMotor = 1 +.mv PressMotor$_na14_na17$true 3 GoUp GoDown Stop +.names PressMotor$_na14_na17$true +GoDown +.mv _na1a 3 Top Mid Bot +.names _na1a +Mid +.names PressPosition _na1a _na19 +.def 0 +- =PressPosition 1 +.names _na19 _na18 +1 1 +0 0 +.mv _na1c 3 GoUp GoDown Stop +.names _na1c +GoDown +# PressMotor == 1 +.names PressMotor _na1c _na1b +.def 0 +- =PressMotor 1 +.names _na1b _na1d +- =_na1b +# PressMotor = 2 +.mv PressMotor$_na1b_na1e$true 3 GoUp GoDown Stop +.names PressMotor$_na1b_na1e$true +Stop +# PressReadyToBeUnLoaded = 0 +.mv PressReadyToBeUnLoaded$_na1b_na1f$true 2 Y N +.names PressReadyToBeUnLoaded$_na1b_na1f$true +Y +# PressMotor = 1 +.mv PressMotor$_na1b_na20$false 3 GoUp GoDown Stop +.names PressMotor$_na1b_na20$false +GoDown +# if/else (PressMotor == 1) +.mv PressMotor$_na1b$raw_na24 3 GoUp GoDown Stop +.names PressMotor$_na1b_na1e$true PressMotor$_na1b_na20$false _na1b PressMotor$_na1b$raw_na24 +- - 0 =PressMotor$_na1b_na20$false +- - 1 =PressMotor$_na1b_na1e$true +.mv PressReadyToBeUnLoaded$_na1b$raw_na25 2 Y N +.names PressReadyToBeUnLoaded$_na1b_na1f$true PressReadyToBeUnLoaded _na1b PressReadyToBeUnLoaded$_na1b$raw_na25 +- - 0 =PressReadyToBeUnLoaded +- - 1 =PressReadyToBeUnLoaded$_na1b_na1f$true +.mv _na2a 3 Top Mid Bot +.names _na2a +Bot +.names PressPosition _na2a _na29 +.def 0 +- =PressPosition 1 +.names _na29 _na28 +1 1 +0 0 +.mv _na2c 2 Y N +.names _na2c +Y +# ArmUnLoadedPress == 0 +.names ArmUnLoadedPress _na2c _na2b +.def 0 +- =ArmUnLoadedPress 1 +.mv _na2e 2 Y N +.names _na2e +Y +# PressReadyToBeUnLoaded == 0 +.names PressReadyToBeUnLoaded _na2e _na2d +.def 0 +- =PressReadyToBeUnLoaded 1 +# ArmUnLoadedPress == 0 && PressReadyToBeUnLoaded == 0 +.names _na2b _na2d _na2f +.def 0 +1 1 1 +.names _na2f _na30 +- =_na2f +# PressMotor = 0 +.mv PressMotor$_na2f_na31$true 3 GoUp GoDown Stop +.names PressMotor$_na2f_na31$true +GoUp +# PressLoaded = 1 +.mv PressLoaded$_na2f_na32$true 2 Y N +.names PressLoaded$_na2f_na32$true +N +# PressReadyToBeUnLoaded = 1 +.mv PressReadyToBeUnLoaded$_na2f_na33$true 2 Y N +.names PressReadyToBeUnLoaded$_na2f_na33$true +N +# PressMotor = 2 +.mv PressMotor$_na2f_na34$false 3 GoUp GoDown Stop +.names PressMotor$_na2f_na34$false +Stop +# if/else (ArmUnLoadedPress == 0 && PressReadyToBeUnLoaded == 0) +.mv PressMotor$_na2f$raw_na3a 3 GoUp GoDown Stop +.names PressMotor$_na2f_na31$true PressMotor$_na2f_na34$false _na2f PressMotor$_na2f$raw_na3a +- - 0 =PressMotor$_na2f_na34$false +- - 1 =PressMotor$_na2f_na31$true +.mv PressReadyToBeUnLoaded$_na2f$raw_na3b 2 Y N +.names PressReadyToBeUnLoaded$_na2f_na33$true PressReadyToBeUnLoaded _na2f PressReadyToBeUnLoaded$_na2f$raw_na3b +- - 0 =PressReadyToBeUnLoaded +- - 1 =PressReadyToBeUnLoaded$_na2f_na33$true +.mv PressLoaded$_na2f$raw_na3c 2 Y N +.names PressLoaded$_na2f_na32$true PressLoaded _na2f PressLoaded$_na2f$raw_na3c +- - 0 =PressLoaded +- - 1 =PressLoaded$_na2f_na32$true +# case (PressPosition ) +.mv PressReadyToBeUnLoaded$_na28$raw_na45 2 Y N +.names PressReadyToBeUnLoaded$_na2f$raw_na3b PressReadyToBeUnLoaded _na28 PressReadyToBeUnLoaded$_na28$raw_na45 +- - 0 =PressReadyToBeUnLoaded +- - 1 =PressReadyToBeUnLoaded$_na2f$raw_na3b +.mv PressLoaded$_na28$raw_na46 2 Y N +.names PressLoaded$_na2f$raw_na3c PressLoaded _na28 PressLoaded$_na28$raw_na46 +- - 0 =PressLoaded +- - 1 =PressLoaded$_na2f$raw_na3c +.mv PressMotor$_na28$raw_na47 3 GoUp GoDown Stop +.names PressMotor$_na2f$raw_na3a PressMotor _na28 PressMotor$_na28$raw_na47 +- - 0 =PressMotor +- - 1 =PressMotor$_na2f$raw_na3a +.mv PressReadyToBeUnLoaded$_na18$raw_na48 2 Y N +.names PressReadyToBeUnLoaded$_na1b$raw_na25 PressReadyToBeUnLoaded$_na28$raw_na45 _na18 PressReadyToBeUnLoaded$_na18$raw_na48 +- - 0 =PressReadyToBeUnLoaded$_na28$raw_na45 +- - 1 =PressReadyToBeUnLoaded$_na1b$raw_na25 +.mv PressMotor$_na18$raw_na49 3 GoUp GoDown Stop +.names PressMotor$_na1b$raw_na24 PressMotor$_na28$raw_na47 _na18 PressMotor$_na18$raw_na49 +- - 0 =PressMotor$_na28$raw_na47 +- - 1 =PressMotor$_na1b$raw_na24 +.mv PressLoaded$_na18$raw_na4f 2 Y N +.names PressLoaded PressLoaded$_na28$raw_na46 _na18 PressLoaded$_na18$raw_na4f +- - 0 =PressLoaded$_na28$raw_na46 +- - 1 =PressLoaded +.mv PressMotor$_na14$raw_na51 3 GoUp GoDown Stop +.names PressMotor$_na14_na17$true PressMotor$_na18$raw_na49 _na14 PressMotor$_na14$raw_na51 +- - 0 =PressMotor$_na18$raw_na49 +- - 1 =PressMotor$_na14_na17$true +.mv PressReadyToBeUnLoaded$_na14$raw_na54 2 Y N +.names PressReadyToBeUnLoaded PressReadyToBeUnLoaded$_na18$raw_na48 _na14 PressReadyToBeUnLoaded$_na14$raw_na54 +- - 0 =PressReadyToBeUnLoaded$_na18$raw_na48 +- - 1 =PressReadyToBeUnLoaded +.mv PressLoaded$_na14$raw_na55 2 Y N +.names PressLoaded PressLoaded$_na18$raw_na4f _na14 PressLoaded$_na14$raw_na55 +- - 0 =PressLoaded$_na18$raw_na4f +- - 1 =PressLoaded +.mv _na59 2 Y N +.names _na59 +N +.names PressLoaded _na59 _na58 +.def 0 +- =PressLoaded 1 +.names _na58 _na57 +1 1 +0 0 +.mv _na5c 3 Top Mid Bot +.names _na5c +Top +.names PressPosition _na5c _na5b +.def 0 +- =PressPosition 1 +.names _na5b _na5a +1 1 +0 0 +.mv _na5e 3 GoUp GoDown Stop +.names _na5e +GoDown +# PressMotor == 1 +.names PressMotor _na5e _na5d +.def 0 +- =PressMotor 1 +.names _na5d _na5f +- =_na5d +# PressMotor = 2 +.mv PressMotor$_na5d_na60$true 3 GoUp GoDown Stop +.names PressMotor$_na5d_na60$true +Stop +# PressReadyToBeLoaded = 0 +.mv PressReadyToBeLoaded$_na5d_na61$true 2 Y N +.names PressReadyToBeLoaded$_na5d_na61$true +Y +# PressMotor = 1 +.mv PressMotor$_na5d_na62$false 3 GoUp GoDown Stop +.names PressMotor$_na5d_na62$false +GoDown +# if/else (PressMotor == 1) +.mv PressMotor$_na5d$raw_na66 3 GoUp GoDown Stop +.names PressMotor$_na5d_na60$true PressMotor$_na5d_na62$false _na5d PressMotor$_na5d$raw_na66 +- - 0 =PressMotor$_na5d_na62$false +- - 1 =PressMotor$_na5d_na60$true +.mv PressReadyToBeLoaded$_na5d$raw_na67 2 Y N +.names PressReadyToBeLoaded$_na5d_na61$true PressReadyToBeLoaded _na5d PressReadyToBeLoaded$_na5d$raw_na67 +- - 0 =PressReadyToBeLoaded +- - 1 =PressReadyToBeLoaded$_na5d_na61$true +.mv _na6c 3 Top Mid Bot +.names _na6c +Mid +.names PressPosition _na6c _na6b +.def 0 +- =PressPosition 1 +.names _na6b _na6a +1 1 +0 0 +.mv _na6e 2 Y N +.names _na6e +Y +# ArmLoadedPress == 0 +.names ArmLoadedPress _na6e _na6d +.def 0 +- =ArmLoadedPress 1 +.names _na6d _na6f +- =_na6d +# PressLoaded = 0 +.mv PressLoaded$_na6d_na70$true 2 Y N +.names PressLoaded$_na6d_na70$true +Y +# PressMotor = 0 +.mv PressMotor$_na6d_na71$true 3 GoUp GoDown Stop +.names PressMotor$_na6d_na71$true +GoUp +# PressMotor = 2 +.mv PressMotor$_na6d_na72$false 3 GoUp GoDown Stop +.names PressMotor$_na6d_na72$false +Stop +# PressReadyToBeLoaded = 0 +.mv PressReadyToBeLoaded$_na6d_na73$false 2 Y N +.names PressReadyToBeLoaded$_na6d_na73$false +Y +# if/else (ArmLoadedPress == 0) +.mv PressMotor$_na6d$raw_na77 3 GoUp GoDown Stop +.names PressMotor$_na6d_na71$true PressMotor$_na6d_na72$false _na6d PressMotor$_na6d$raw_na77 +- - 0 =PressMotor$_na6d_na72$false +- - 1 =PressMotor$_na6d_na71$true +.mv PressLoaded$_na6d$raw_na78 2 Y N +.names PressLoaded$_na6d_na70$true PressLoaded _na6d PressLoaded$_na6d$raw_na78 +- - 0 =PressLoaded +- - 1 =PressLoaded$_na6d_na70$true +.mv PressReadyToBeLoaded$_na6d$raw_na7a 2 Y N +.names PressReadyToBeLoaded PressReadyToBeLoaded$_na6d_na73$false _na6d PressReadyToBeLoaded$_na6d$raw_na7a +- - 0 =PressReadyToBeLoaded$_na6d_na73$false +- - 1 =PressReadyToBeLoaded +# case (PressPosition ) +.mv PressReadyToBeLoaded$_na6a$raw_na82 2 Y N +.names PressReadyToBeLoaded$_na6d$raw_na7a PressReadyToBeLoaded _na6a PressReadyToBeLoaded$_na6a$raw_na82 +- - 0 =PressReadyToBeLoaded +- - 1 =PressReadyToBeLoaded$_na6d$raw_na7a +.mv PressLoaded$_na6a$raw_na83 2 Y N +.names PressLoaded$_na6d$raw_na78 PressLoaded _na6a PressLoaded$_na6a$raw_na83 +- - 0 =PressLoaded +- - 1 =PressLoaded$_na6d$raw_na78 +.mv PressMotor$_na6a$raw_na84 3 GoUp GoDown Stop +.names PressMotor$_na6d$raw_na77 PressMotor _na6a PressMotor$_na6a$raw_na84 +- - 0 =PressMotor +- - 1 =PressMotor$_na6d$raw_na77 +.mv PressReadyToBeLoaded$_na5a$raw_na85 2 Y N +.names PressReadyToBeLoaded$_na5d$raw_na67 PressReadyToBeLoaded$_na6a$raw_na82 _na5a PressReadyToBeLoaded$_na5a$raw_na85 +- - 0 =PressReadyToBeLoaded$_na6a$raw_na82 +- - 1 =PressReadyToBeLoaded$_na5d$raw_na67 +.mv PressMotor$_na5a$raw_na86 3 GoUp GoDown Stop +.names PressMotor$_na5d$raw_na66 PressMotor$_na6a$raw_na84 _na5a PressMotor$_na5a$raw_na86 +- - 0 =PressMotor$_na6a$raw_na84 +- - 1 =PressMotor$_na5d$raw_na66 +.mv PressLoaded$_na5a$raw_na8c 2 Y N +.names PressLoaded PressLoaded$_na6a$raw_na83 _na5a PressLoaded$_na5a$raw_na8c +- - 0 =PressLoaded$_na6a$raw_na83 +- - 1 =PressLoaded +# case (PressLoaded ) +.mv PressReadyToBeLoaded$_na57$raw_na94 2 Y N +.names PressReadyToBeLoaded$_na5a$raw_na85 PressReadyToBeLoaded _na57 PressReadyToBeLoaded$_na57$raw_na94 +- - 0 =PressReadyToBeLoaded +- - 1 =PressReadyToBeLoaded$_na5a$raw_na85 +.mv PressLoaded$_na57$raw_na95 2 Y N +.names PressLoaded$_na5a$raw_na8c PressLoaded _na57 PressLoaded$_na57$raw_na95 +- - 0 =PressLoaded +- - 1 =PressLoaded$_na5a$raw_na8c +.mv PressMotor$_na57$raw_na96 3 GoUp GoDown Stop +.names PressMotor$_na5a$raw_na86 PressMotor _na57 PressMotor$_na57$raw_na96 +- - 0 =PressMotor +- - 1 =PressMotor$_na5a$raw_na86 +.mv PressLoaded$_na11$raw_na98 2 Y N +.names PressLoaded$_na14$raw_na55 PressLoaded$_na57$raw_na95 _na11 PressLoaded$_na11$raw_na98 +- - 0 =PressLoaded$_na57$raw_na95 +- - 1 =PressLoaded$_na14$raw_na55 +.mv PressMotor$_na11$raw_na99 3 GoUp GoDown Stop +.names PressMotor$_na14$raw_na51 PressMotor$_na57$raw_na96 _na11 PressMotor$_na11$raw_na99 +- - 0 =PressMotor$_na57$raw_na96 +- - 1 =PressMotor$_na14$raw_na51 +.mv PressReadyToBeUnLoaded$_na11$raw_na9d 2 Y N +.names PressReadyToBeUnLoaded$_na14$raw_na54 PressReadyToBeUnLoaded _na11 PressReadyToBeUnLoaded$_na11$raw_na9d +- - 0 =PressReadyToBeUnLoaded +- - 1 =PressReadyToBeUnLoaded$_na14$raw_na54 +.mv PressReadyToBeLoaded$_na11$raw_naa0 2 Y N +.names PressReadyToBeLoaded PressReadyToBeLoaded$_na57$raw_na94 _na11 PressReadyToBeLoaded$_na11$raw_naa0 +- - 0 =PressReadyToBeLoaded$_na57$raw_na94 +- - 1 =PressReadyToBeLoaded +.mv _naa4 2 Y N +.names _naa4 +Y +# ArmLoadedPress == 0 +.names ArmLoadedPress _naa4 _naa3 +.def 0 +- =ArmLoadedPress 1 +.mv _naa6 2 Y N +.names _naa6 +Y +# PressReadyToBeLoaded == 0 +.names PressReadyToBeLoaded$_na11$raw_naa0 _naa6 _naa5 +.def 0 +- =PressReadyToBeLoaded$_na11$raw_naa0 1 +# ArmLoadedPress == 0 && PressReadyToBeLoaded == 0 +.names _naa3 _naa5 _naa7 +.def 0 +1 1 1 +.names _naa7 _naa8 +- =_naa7 +# PressReadyToBeLoaded = 1 +.mv PressReadyToBeLoaded$_naa7_naa9$true 2 Y N +.names PressReadyToBeLoaded$_naa7_naa9$true +N +# if/else (ArmLoadedPress == 0 && PressReadyToBeLoaded == 0) +.mv PressReadyToBeLoaded$_naa7$raw_naaa 2 Y N +.names PressReadyToBeLoaded$_naa7_naa9$true PressReadyToBeLoaded$_na11$raw_naa0 _naa7 PressReadyToBeLoaded$_naa7$raw_naaa +- - 0 =PressReadyToBeLoaded$_na11$raw_naa0 +- - 1 =PressReadyToBeLoaded$_naa7_naa9$true +.mv _nabb 2 Y N +.names _nabb +Y +# PressReadyToBeUnLoaded == 0 +.names PressReadyToBeUnLoaded$_na11$raw_na9d _nabb _naba +.def 0 +- =PressReadyToBeUnLoaded$_na11$raw_na9d 1 +.mv _nabd 2 Y N +.names _nabd +Y +# ArmUnLoadedPress == 0 +.names ArmUnLoadedPress _nabd _nabc +.def 0 +- =ArmUnLoadedPress 1 +# PressReadyToBeUnLoaded == 0 && ArmUnLoadedPress == 0 +.names _naba _nabc _nabe +.def 0 +1 1 1 +.names _nabe _nabf +- =_nabe +# PressReadyToBeUnLoaded = 1 +.mv PressReadyToBeUnLoaded$_nabe_nac0$true 2 Y N +.names PressReadyToBeUnLoaded$_nabe_nac0$true +N +# if/else (PressReadyToBeUnLoaded == 0 && ArmUnLoadedPress == 0) +.mv PressReadyToBeUnLoaded$_nabe$raw_nac2 2 Y N +.names PressReadyToBeUnLoaded$_nabe_nac0$true PressReadyToBeUnLoaded$_na11$raw_na9d _nabe PressReadyToBeUnLoaded$_nabe$raw_nac2 +- - 0 =PressReadyToBeUnLoaded$_na11$raw_na9d +- - 1 =PressReadyToBeUnLoaded$_nabe_nac0$true +# conflict arbitrators +.names _na11 _na14 _na18 _na1d _na28 _na30 _nabf _nad1 +.def 0 + 1 0 1 1 - - - 1 + 1 0 0 - 1 1 - 1 + - - - - - - 1 1 +.mv _nad2 2 Y N +.names _nad1 PressReadyToBeUnLoaded$_nabe$raw_nac2 PressReadyToBeUnLoaded _nad2 +1 - - =PressReadyToBeUnLoaded$_nabe$raw_nac2 +0 - - =PressReadyToBeUnLoaded +.names _na11 _na57 _na5a _na5f _na6a _na6f _naa8 _nad6 +.def 0 + 0 1 1 1 - - - 1 + 0 1 0 - 1 0 - 1 + - - - - - - 1 1 +.mv _nad7 2 Y N +.names _nad6 PressReadyToBeLoaded$_naa7$raw_naaa PressReadyToBeLoaded _nad7 +1 - - =PressReadyToBeLoaded$_naa7$raw_naaa +0 - - =PressReadyToBeLoaded +.names _na11 _na14 _na18 _na28 _na30 _na57 _na5a _na6a _na6f _nadb +.def 0 + 1 0 0 1 1 - - - - 1 + 0 - - - - 1 0 1 1 1 +.mv _nadc 2 Y N +.names _nadb PressLoaded$_na11$raw_na98 PressLoaded _nadc +1 - - =PressLoaded$_na11$raw_na98 +0 - - =PressLoaded +.names _na11 _na14 _na18 _na1d _na28 _na30 _na57 _na5a _na5f _na6a _na6f _nae0 +.def 0 + 1 1 - - - - - - - - - 1 + 1 0 1 1 - - - - - - - 1 + 1 0 1 0 - - - - - - - 1 + 1 0 0 - 1 1 - - - - - 1 + 1 0 0 - 1 0 - - - - - 1 + 0 - - - - - 1 1 1 - - 1 + 0 - - - - - 1 1 0 - - 1 + 0 - - - - - 1 0 - 1 1 1 + 0 - - - - - 1 0 - 1 0 1 +.mv _nae1 3 GoUp GoDown Stop +.names _nae0 PressMotor$_na11$raw_na99 PressMotor _nae1 +1 - - =PressMotor$_na11$raw_na99 +0 - - =PressMotor +# non-blocking assignments +# latches +.r PressReadyToBeLoaded$raw_na0e PressReadyToBeLoaded +- =PressReadyToBeLoaded$raw_na0e +.latch _nad7 PressReadyToBeLoaded +.r PressReadyToBeUnLoaded$raw_na0f PressReadyToBeUnLoaded +- =PressReadyToBeUnLoaded$raw_na0f +.latch _nad2 PressReadyToBeUnLoaded +.r PressLoaded$raw_na10 PressLoaded +- =PressLoaded$raw_na10 +.latch _nadc PressLoaded +.r PressMotor$raw_na0d PressMotor +- =PressMotor$raw_na0d +.latch _nae1 PressMotor +# quasi-continuous assignment +.end + + +.model RobotArm +# I/O ports +.outputs RAArmOverDB +.outputs RAArmOverLoadedPress +.outputs RAUnLoadArmExtended +.inputs RAExtendUnLoadArm +.inputs RARotaryMotor +.outputs RAArmOverUnLoadedPress +.outputs RALoadArmExtended +.outputs RAArmOverRT +.outputs RALoadArmRetracted +.inputs RAExtendLoadArm +.outputs RAUnLoadArmRetracted +.mv RAArmOverDB 2 Y N +.mv RAArmOverLoadedPress 2 Y N +.mv RAUnLoadArmExtended 2 Y N +.mv RAExtendUnLoadArm 3 Extend Retract Stop +.mv RARotaryMotor 3 CWise Stop CCWise +.mv RALoadArm 3 Extended Retracted Middle +.mv RAAnglePos 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.mv RAArmOverUnLoadedPress 2 Y N +.mv RALoadArmExtended 2 Y N +.mv RAUnLoadArm 3 Extended Retracted Middle +.mv RAArmOverRT 2 Y N +.mv RALoadArmRetracted 2 Y N +.mv RAExtendLoadArm 3 Extend Retract Stop +.mv RAUnLoadArmRetracted 2 Y N +# assign RALoadArmExtended = (RALoadArm == Extended ) ? 0 : 1 +.mv RALoadArmExtended$raw_nae5 2 Y N +.mv _nae7 3 Extended Retracted Middle +.names _nae7 +Extended +# RALoadArm == 0 +.names RALoadArm _nae7 _nae6 +.def 0 +- =RALoadArm 1 +.mv _nae8 2 Y N +.names _nae8 +Y +.mv _nae9 2 Y N +.names _nae9 +N +# (RALoadArm == 0) ? 0 : 1 +.mv _naea 2 Y N +.names _nae8 _nae9 _nae6 _naea +- - 0 =_nae9 +- - 1 =_nae8 +.names _naea RALoadArmExtended$raw_nae5 +- =_naea +# assign RALoadArmRetracted = (RALoadArm == Retracted ) ? 0 : 1 +.mv RALoadArmRetracted$raw_naeb 2 Y N +.mv _naed 3 Extended Retracted Middle +.names _naed +Retracted +# RALoadArm == 1 +.names RALoadArm _naed _naec +.def 0 +- =RALoadArm 1 +.mv _naee 2 Y N +.names _naee +Y +.mv _naef 2 Y N +.names _naef +N +# (RALoadArm == 1) ? 0 : 1 +.mv _naf0 2 Y N +.names _naee _naef _naec _naf0 +- - 0 =_naef +- - 1 =_naee +.names _naf0 RALoadArmRetracted$raw_naeb +- =_naf0 +# assign RAUnLoadArmExtended = (RAUnLoadArm == Extended ) ? 0 : 1 +.mv RAUnLoadArmExtended$raw_naf1 2 Y N +.mv _naf3 3 Extended Retracted Middle +.names _naf3 +Extended +# RAUnLoadArm == 0 +.names RAUnLoadArm _naf3 _naf2 +.def 0 +- =RAUnLoadArm 1 +.mv _naf4 2 Y N +.names _naf4 +Y +.mv _naf5 2 Y N +.names _naf5 +N +# (RAUnLoadArm == 0) ? 0 : 1 +.mv _naf6 2 Y N +.names _naf4 _naf5 _naf2 _naf6 +- - 0 =_naf5 +- - 1 =_naf4 +.names _naf6 RAUnLoadArmExtended$raw_naf1 +- =_naf6 +# assign RAUnLoadArmRetracted = (RAUnLoadArm == Retracted ) ? 0 : 1 +.mv RAUnLoadArmRetracted$raw_naf7 2 Y N +.mv _naf9 3 Extended Retracted Middle +.names _naf9 +Retracted +# RAUnLoadArm == 1 +.names RAUnLoadArm _naf9 _naf8 +.def 0 +- =RAUnLoadArm 1 +.mv _nafa 2 Y N +.names _nafa +Y +.mv _nafb 2 Y N +.names _nafb +N +# (RAUnLoadArm == 1) ? 0 : 1 +.mv _nafc 2 Y N +.names _nafa _nafb _naf8 _nafc +- - 0 =_nafb +- - 1 =_nafa +.names _nafc RAUnLoadArmRetracted$raw_naf7 +- =_nafc +# assign RAArmOverRT = (RAAnglePos == OverRT ) ? 0 : 1 +.mv RAArmOverRT$raw_nafd 2 Y N +.mv _naff 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names _naff +OverRT +# RAAnglePos == 0 +.names RAAnglePos _naff _nafe +.def 0 +- =RAAnglePos 1 +.mv _nb00 2 Y N +.names _nb00 +Y +.mv _nb01 2 Y N +.names _nb01 +N +# (RAAnglePos == 0) ? 0 : 1 +.mv _nb02 2 Y N +.names _nb00 _nb01 _nafe _nb02 +- - 0 =_nb01 +- - 1 =_nb00 +.names _nb02 RAArmOverRT$raw_nafd +- =_nb02 +# assign RAArmOverUnLoadedPress = (RAAnglePos == OverUnLoadedPress ) ? 0 : 1 +.mv RAArmOverUnLoadedPress$raw_nb03 2 Y N +.mv _nb05 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names _nb05 +OverUnLoadedPress +# RAAnglePos == 3 +.names RAAnglePos _nb05 _nb04 +.def 0 +- =RAAnglePos 1 +.mv _nb06 2 Y N +.names _nb06 +Y +.mv _nb07 2 Y N +.names _nb07 +N +# (RAAnglePos == 3) ? 0 : 1 +.mv _nb08 2 Y N +.names _nb06 _nb07 _nb04 _nb08 +- - 0 =_nb07 +- - 1 =_nb06 +.names _nb08 RAArmOverUnLoadedPress$raw_nb03 +- =_nb08 +# assign RAArmOverLoadedPress = (RAAnglePos == OverLoadedPress ) ? 0 : 1 +.mv RAArmOverLoadedPress$raw_nb09 2 Y N +.mv _nb0b 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names _nb0b +OverLoadedPress +# RAAnglePos == 1 +.names RAAnglePos _nb0b _nb0a +.def 0 +- =RAAnglePos 1 +.mv _nb0c 2 Y N +.names _nb0c +Y +.mv _nb0d 2 Y N +.names _nb0d +N +# (RAAnglePos == 1) ? 0 : 1 +.mv _nb0e 2 Y N +.names _nb0c _nb0d _nb0a _nb0e +- - 0 =_nb0d +- - 1 =_nb0c +.names _nb0e RAArmOverLoadedPress$raw_nb09 +- =_nb0e +# assign RAArmOverDB = (RAAnglePos == OverDB ) ? 0 : 1 +.mv RAArmOverDB$raw_nb0f 2 Y N +.mv _nb11 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names _nb11 +OverDB +# RAAnglePos == 2 +.names RAAnglePos _nb11 _nb10 +.def 0 +- =RAAnglePos 1 +.mv _nb12 2 Y N +.names _nb12 +Y +.mv _nb13 2 Y N +.names _nb13 +N +# (RAAnglePos == 2) ? 0 : 1 +.mv _nb14 2 Y N +.names _nb12 _nb13 _nb10 _nb14 +- - 0 =_nb13 +- - 1 =_nb12 +.names _nb14 RAArmOverDB$raw_nb0f +- =_nb14 +# RALoadArm = 1 +.mv RALoadArm$raw_nb15 3 Extended Retracted Middle +.names RALoadArm$raw_nb15 +Retracted +# RAUnLoadArm = 1 +.mv RAUnLoadArm$raw_nb16 3 Extended Retracted Middle +.names RAUnLoadArm$raw_nb16 +Retracted +# RAAnglePos = $NDset ( 0,1,2,3 ) +.mv RAAnglePos$raw_nb17 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.mv RAAnglePos$raw_nb17$initial$_nb18 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$raw_nb17$initial$_nb18 +OverRT +OverLoadedPress +OverDB +OverUnLoadedPress +.names RAAnglePos$raw_nb17$initial$_nb18 RAAnglePos$raw_nb17 +- =RAAnglePos$raw_nb17$initial$_nb18 +# non-blocking assignments for initial +.mv _nb1a 3 Extend Retract Stop +.names _nb1a +Extend +# RAExtendLoadArm == 0 +.names RAExtendLoadArm _nb1a _nb19 +.def 0 +- =RAExtendLoadArm 1 +.names _nb19 _nb1b +- =_nb19 +.mv _nb1e 3 Extended Retracted Middle +.names _nb1e +Retracted +.names RALoadArm _nb1e _nb1d +.def 0 +- =RALoadArm 1 +.names _nb1d _nb1c +1 1 +0 0 +# RALoadArm = 2 +.mv RALoadArm$_nb1c_nb1f$true 3 Extended Retracted Middle +.names RALoadArm$_nb1c_nb1f$true +Middle +.mv _nb22 3 Extended Retracted Middle +.names _nb22 +Middle +.names RALoadArm _nb22 _nb21 +.def 0 +- =RALoadArm 1 +.names _nb21 _nb20 +1 1 +0 0 +# RALoadArm = 0 +.mv RALoadArm$_nb20_nb23$true 3 Extended Retracted Middle +.names RALoadArm$_nb20_nb23$true +Extended +# case (RALoadArm ) +.mv RALoadArm$_nb20$raw_nb26 3 Extended Retracted Middle +.names RALoadArm$_nb20_nb23$true RALoadArm _nb20 RALoadArm$_nb20$raw_nb26 +- - 0 =RALoadArm +- - 1 =RALoadArm$_nb20_nb23$true +.mv RALoadArm$_nb1c$raw_nb27 3 Extended Retracted Middle +.names RALoadArm$_nb1c_nb1f$true RALoadArm$_nb20$raw_nb26 _nb1c RALoadArm$_nb1c$raw_nb27 +- - 0 =RALoadArm$_nb20$raw_nb26 +- - 1 =RALoadArm$_nb1c_nb1f$true +# if/else (RAExtendLoadArm == 0) +.mv RALoadArm$_nb19$raw_nb2d 3 Extended Retracted Middle +.names RALoadArm$_nb1c$raw_nb27 RALoadArm _nb19 RALoadArm$_nb19$raw_nb2d +- - 0 =RALoadArm +- - 1 =RALoadArm$_nb1c$raw_nb27 +.mv _nb2f 3 Extend Retract Stop +.names _nb2f +Retract +# RAExtendLoadArm == 1 +.names RAExtendLoadArm _nb2f _nb2e +.def 0 +- =RAExtendLoadArm 1 +.names _nb2e _nb30 +- =_nb2e +.mv _nb33 3 Extended Retracted Middle +.names _nb33 +Extended +.names RALoadArm$_nb19$raw_nb2d _nb33 _nb32 +.def 0 +- =RALoadArm$_nb19$raw_nb2d 1 +.names _nb32 _nb31 +1 1 +0 0 +# RALoadArm = 2 +.mv RALoadArm$_nb31_nb34$true 3 Extended Retracted Middle +.names RALoadArm$_nb31_nb34$true +Middle +.mv _nb37 3 Extended Retracted Middle +.names _nb37 +Middle +.names RALoadArm$_nb19$raw_nb2d _nb37 _nb36 +.def 0 +- =RALoadArm$_nb19$raw_nb2d 1 +.names _nb36 _nb35 +1 1 +0 0 +# RALoadArm = 1 +.mv RALoadArm$_nb35_nb38$true 3 Extended Retracted Middle +.names RALoadArm$_nb35_nb38$true +Retracted +# case (RALoadArm ) +.mv RALoadArm$_nb35$raw_nb39 3 Extended Retracted Middle +.names RALoadArm$_nb35_nb38$true RALoadArm$_nb19$raw_nb2d _nb35 RALoadArm$_nb35$raw_nb39 +- - 0 =RALoadArm$_nb19$raw_nb2d +- - 1 =RALoadArm$_nb35_nb38$true +.mv RALoadArm$_nb31$raw_nb3d 3 Extended Retracted Middle +.names RALoadArm$_nb31_nb34$true RALoadArm$_nb35$raw_nb39 _nb31 RALoadArm$_nb31$raw_nb3d +- - 0 =RALoadArm$_nb35$raw_nb39 +- - 1 =RALoadArm$_nb31_nb34$true +# if/else (RAExtendLoadArm == 1) +.mv RALoadArm$_nb2e$raw_nb41 3 Extended Retracted Middle +.names RALoadArm$_nb31$raw_nb3d RALoadArm$_nb19$raw_nb2d _nb2e RALoadArm$_nb2e$raw_nb41 +- - 0 =RALoadArm$_nb19$raw_nb2d +- - 1 =RALoadArm$_nb31$raw_nb3d +.mv _nb46 3 Extend Retract Stop +.names _nb46 +Extend +# RAExtendUnLoadArm == 0 +.names RAExtendUnLoadArm _nb46 _nb45 +.def 0 +- =RAExtendUnLoadArm 1 +.names _nb45 _nb47 +- =_nb45 +.mv _nb4a 3 Extended Retracted Middle +.names _nb4a +Retracted +.names RAUnLoadArm _nb4a _nb49 +.def 0 +- =RAUnLoadArm 1 +.names _nb49 _nb48 +1 1 +0 0 +# RAUnLoadArm = 2 +.mv RAUnLoadArm$_nb48_nb4b$true 3 Extended Retracted Middle +.names RAUnLoadArm$_nb48_nb4b$true +Middle +.mv _nb4e 3 Extended Retracted Middle +.names _nb4e +Middle +.names RAUnLoadArm _nb4e _nb4d +.def 0 +- =RAUnLoadArm 1 +.names _nb4d _nb4c +1 1 +0 0 +# RAUnLoadArm = 0 +.mv RAUnLoadArm$_nb4c_nb4f$true 3 Extended Retracted Middle +.names RAUnLoadArm$_nb4c_nb4f$true +Extended +# case (RAUnLoadArm ) +.mv RAUnLoadArm$_nb4c$raw_nb55 3 Extended Retracted Middle +.names RAUnLoadArm$_nb4c_nb4f$true RAUnLoadArm _nb4c RAUnLoadArm$_nb4c$raw_nb55 +- - 0 =RAUnLoadArm +- - 1 =RAUnLoadArm$_nb4c_nb4f$true +.mv RAUnLoadArm$_nb48$raw_nb58 3 Extended Retracted Middle +.names RAUnLoadArm$_nb48_nb4b$true RAUnLoadArm$_nb4c$raw_nb55 _nb48 RAUnLoadArm$_nb48$raw_nb58 +- - 0 =RAUnLoadArm$_nb4c$raw_nb55 +- - 1 =RAUnLoadArm$_nb48_nb4b$true +# if/else (RAExtendUnLoadArm == 0) +.mv RAUnLoadArm$_nb45$raw_nb64 3 Extended Retracted Middle +.names RAUnLoadArm$_nb48$raw_nb58 RAUnLoadArm _nb45 RAUnLoadArm$_nb45$raw_nb64 +- - 0 =RAUnLoadArm +- - 1 =RAUnLoadArm$_nb48$raw_nb58 +.mv _nb67 3 Extend Retract Stop +.names _nb67 +Retract +# RAExtendUnLoadArm == 1 +.names RAExtendUnLoadArm _nb67 _nb66 +.def 0 +- =RAExtendUnLoadArm 1 +.names _nb66 _nb68 +- =_nb66 +.mv _nb6b 3 Extended Retracted Middle +.names _nb6b +Extended +.names RAUnLoadArm$_nb45$raw_nb64 _nb6b _nb6a +.def 0 +- =RAUnLoadArm$_nb45$raw_nb64 1 +.names _nb6a _nb69 +1 1 +0 0 +# RAUnLoadArm = 2 +.mv RAUnLoadArm$_nb69_nb6c$true 3 Extended Retracted Middle +.names RAUnLoadArm$_nb69_nb6c$true +Middle +.mv _nb6f 3 Extended Retracted Middle +.names _nb6f +Middle +.names RAUnLoadArm$_nb45$raw_nb64 _nb6f _nb6e +.def 0 +- =RAUnLoadArm$_nb45$raw_nb64 1 +.names _nb6e _nb6d +1 1 +0 0 +# RAUnLoadArm = 1 +.mv RAUnLoadArm$_nb6d_nb70$true 3 Extended Retracted Middle +.names RAUnLoadArm$_nb6d_nb70$true +Retracted +# case (RAUnLoadArm ) +.mv RAUnLoadArm$_nb6d$raw_nb72 3 Extended Retracted Middle +.names RAUnLoadArm$_nb6d_nb70$true RAUnLoadArm$_nb45$raw_nb64 _nb6d RAUnLoadArm$_nb6d$raw_nb72 +- - 0 =RAUnLoadArm$_nb45$raw_nb64 +- - 1 =RAUnLoadArm$_nb6d_nb70$true +.mv RAUnLoadArm$_nb69$raw_nb7a 3 Extended Retracted Middle +.names RAUnLoadArm$_nb69_nb6c$true RAUnLoadArm$_nb6d$raw_nb72 _nb69 RAUnLoadArm$_nb69$raw_nb7a +- - 0 =RAUnLoadArm$_nb6d$raw_nb72 +- - 1 =RAUnLoadArm$_nb69_nb6c$true +# if/else (RAExtendUnLoadArm == 1) +.mv RAUnLoadArm$_nb66$raw_nb82 3 Extended Retracted Middle +.names RAUnLoadArm$_nb69$raw_nb7a RAUnLoadArm$_nb45$raw_nb64 _nb66 RAUnLoadArm$_nb66$raw_nb82 +- - 0 =RAUnLoadArm$_nb45$raw_nb64 +- - 1 =RAUnLoadArm$_nb69$raw_nb7a +.mv _nb8a 3 CWise Stop CCWise +.names _nb8a +CCWise +# RARotaryMotor == 2 +.names RARotaryMotor _nb8a _nb89 +.def 0 +- =RARotaryMotor 1 +.names _nb89 _nb8b +- =_nb89 +.mv _nb8e 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names _nb8e +OverRT +.names RAAnglePos _nb8e _nb8d +.def 0 +- =RAAnglePos 1 +.names _nb8d _nb8c +1 1 +0 0 +# RAAnglePos = 3 +.mv RAAnglePos$_nb8c_nb8f$true 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nb8c_nb8f$true +OverUnLoadedPress +.mv _nb92 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names _nb92 +OverUnLoadedPress +.names RAAnglePos _nb92 _nb91 +.def 0 +- =RAAnglePos 1 +.names _nb91 _nb90 +1 1 +0 0 +# RAAnglePos = 2 +.mv RAAnglePos$_nb90_nb93$true 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nb90_nb93$true +OverDB +.mv _nb96 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names _nb96 +OverDB +.names RAAnglePos _nb96 _nb95 +.def 0 +- =RAAnglePos 1 +.names _nb95 _nb94 +1 1 +0 0 +# RAAnglePos = 1 +.mv RAAnglePos$_nb94_nb97$true 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nb94_nb97$true +OverLoadedPress +# case (RAAnglePos ) +.mv RAAnglePos$_nb94$raw_nb9f 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nb94_nb97$true RAAnglePos _nb94 RAAnglePos$_nb94$raw_nb9f +- - 0 =RAAnglePos +- - 1 =RAAnglePos$_nb94_nb97$true +.mv RAAnglePos$_nb90$raw_nba4 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nb90_nb93$true RAAnglePos$_nb94$raw_nb9f _nb90 RAAnglePos$_nb90$raw_nba4 +- - 0 =RAAnglePos$_nb94$raw_nb9f +- - 1 =RAAnglePos$_nb90_nb93$true +.mv RAAnglePos$_nb8c$raw_nbb0 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nb8c_nb8f$true RAAnglePos$_nb90$raw_nba4 _nb8c RAAnglePos$_nb8c$raw_nbb0 +- - 0 =RAAnglePos$_nb90$raw_nba4 +- - 1 =RAAnglePos$_nb8c_nb8f$true +# if/else (RARotaryMotor == 2) +.mv RAAnglePos$_nb89$raw_nbc2 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nb8c$raw_nbb0 RAAnglePos _nb89 RAAnglePos$_nb89$raw_nbc2 +- - 0 =RAAnglePos +- - 1 =RAAnglePos$_nb8c$raw_nbb0 +.mv _nbc7 3 CWise Stop CCWise +.names _nbc7 +CWise +# RARotaryMotor == 0 +.names RARotaryMotor _nbc7 _nbc6 +.def 0 +- =RARotaryMotor 1 +.names _nbc6 _nbc8 +- =_nbc6 +.mv _nbcb 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names _nbcb +OverLoadedPress +.names RAAnglePos$_nb89$raw_nbc2 _nbcb _nbca +.def 0 +- =RAAnglePos$_nb89$raw_nbc2 1 +.names _nbca _nbc9 +1 1 +0 0 +# RAAnglePos = 2 +.mv RAAnglePos$_nbc9_nbcc$true 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nbc9_nbcc$true +OverDB +.mv _nbcf 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names _nbcf +OverDB +.names RAAnglePos$_nb89$raw_nbc2 _nbcf _nbce +.def 0 +- =RAAnglePos$_nb89$raw_nbc2 1 +.names _nbce _nbcd +1 1 +0 0 +# RAAnglePos = 3 +.mv RAAnglePos$_nbcd_nbd0$true 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nbcd_nbd0$true +OverUnLoadedPress +.mv _nbd3 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names _nbd3 +OverUnLoadedPress +.names RAAnglePos$_nb89$raw_nbc2 _nbd3 _nbd2 +.def 0 +- =RAAnglePos$_nb89$raw_nbc2 1 +.names _nbd2 _nbd1 +1 1 +0 0 +# RAAnglePos = 0 +.mv RAAnglePos$_nbd1_nbd4$true 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nbd1_nbd4$true +OverRT +# case (RAAnglePos ) +.mv RAAnglePos$_nbd1$raw_nbd6 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nbd1_nbd4$true RAAnglePos$_nb89$raw_nbc2 _nbd1 RAAnglePos$_nbd1$raw_nbd6 +- - 0 =RAAnglePos$_nb89$raw_nbc2 +- - 1 =RAAnglePos$_nbd1_nbd4$true +.mv RAAnglePos$_nbcd$raw_nbe2 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nbcd_nbd0$true RAAnglePos$_nbd1$raw_nbd6 _nbcd RAAnglePos$_nbcd$raw_nbe2 +- - 0 =RAAnglePos$_nbd1$raw_nbd6 +- - 1 =RAAnglePos$_nbcd_nbd0$true +.mv RAAnglePos$_nbc9$raw_nbee 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nbc9_nbcc$true RAAnglePos$_nbcd$raw_nbe2 _nbc9 RAAnglePos$_nbc9$raw_nbee +- - 0 =RAAnglePos$_nbcd$raw_nbe2 +- - 1 =RAAnglePos$_nbc9_nbcc$true +# if/else (RARotaryMotor == 0) +.mv RAAnglePos$_nbc6$raw_nbfa 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names RAAnglePos$_nbc9$raw_nbee RAAnglePos$_nb89$raw_nbc2 _nbc6 RAAnglePos$_nbc6$raw_nbfa +- - 0 =RAAnglePos$_nb89$raw_nbc2 +- - 1 =RAAnglePos$_nbc9$raw_nbee +# conflict arbitrators +.names RAArmOverDB$raw_nb0f RAArmOverDB +- =RAArmOverDB$raw_nb0f +.names RAArmOverLoadedPress$raw_nb09 RAArmOverLoadedPress +- =RAArmOverLoadedPress$raw_nb09 +.names RAUnLoadArmExtended$raw_naf1 RAUnLoadArmExtended +- =RAUnLoadArmExtended$raw_naf1 +.names _nb1b _nb1c _nb20 _nb30 _nb31 _nb35 _nc05 +.def 0 + 1 1 - - - - 1 + 1 0 1 - - - 1 + - - - 1 1 - 1 + - - - 1 0 1 1 +.mv _nc06 3 Extended Retracted Middle +.names _nc05 RALoadArm$_nb2e$raw_nb41 RALoadArm _nc06 +1 - - =RALoadArm$_nb2e$raw_nb41 +0 - - =RALoadArm +.names _nb8b _nb8c _nb90 _nb94 _nbc8 _nbc9 _nbcd _nbd1 _nc1a +.def 0 + 1 1 - - - - - - 1 + 1 0 1 - - - - - 1 + 1 0 0 1 - - - - 1 + - - - - 1 1 - - 1 + - - - - 1 0 1 - 1 + - - - - 1 0 0 1 1 +.mv _nc1b 4 OverRT OverLoadedPress OverDB OverUnLoadedPress +.names _nc1a RAAnglePos$_nbc6$raw_nbfa RAAnglePos _nc1b +1 - - =RAAnglePos$_nbc6$raw_nbfa +0 - - =RAAnglePos +.names RAArmOverUnLoadedPress$raw_nb03 RAArmOverUnLoadedPress +- =RAArmOverUnLoadedPress$raw_nb03 +.names RALoadArmExtended$raw_nae5 RALoadArmExtended +- =RALoadArmExtended$raw_nae5 +.names _nb47 _nb48 _nb4c _nb68 _nb69 _nb6d _nc2f +.def 0 + 1 1 - - - - 1 + 1 0 1 - - - 1 + - - - 1 1 - 1 + - - - 1 0 1 1 +.mv _nc30 3 Extended Retracted Middle +.names _nc2f RAUnLoadArm$_nb66$raw_nb82 RAUnLoadArm _nc30 +1 - - =RAUnLoadArm$_nb66$raw_nb82 +0 - - =RAUnLoadArm +.names RAArmOverRT$raw_nafd RAArmOverRT +- =RAArmOverRT$raw_nafd +.names RALoadArmRetracted$raw_naeb RALoadArmRetracted +- =RALoadArmRetracted$raw_naeb +.names RAUnLoadArmRetracted$raw_naf7 RAUnLoadArmRetracted +- =RAUnLoadArmRetracted$raw_naf7 +# non-blocking assignments +# latches +.r RALoadArm$raw_nb15 RALoadArm +- =RALoadArm$raw_nb15 +.latch _nc06 RALoadArm +.r RAAnglePos$raw_nb17 RAAnglePos +- =RAAnglePos$raw_nb17 +.latch _nc1b RAAnglePos +.r RAUnLoadArm$raw_nb16 RAUnLoadArm +- =RAUnLoadArm$raw_nb16 +.latch _nc30 RAUnLoadArm +# quasi-continuous assignment +.end + + +.model RobotArmCNTR +# I/O ports +.outputs ArmLoadedPress +.outputs RAExtendUnLoadArm +.inputs PressReadyToBeLoaded +.inputs PressReadyToBeUnLoaded +.inputs RAArmOverDB +.inputs RAArmOverLoadedPress +.inputs RAUnLoadArmExtended +.outputs ArmUnLoadedPress +.outputs RARotaryMotor +.inputs RTOutReady +.inputs RAArmOverUnLoadedPress +.inputs RALoadArmExtended +.outputs RAExtendLoadArm +.inputs RAArmOverRT +.inputs RALoadArmRetracted +.outputs PieceGrabbedFromRT +.outputs PieceOutArm +.inputs DBReady +.inputs RAUnLoadArmRetracted +.mv UnLoadArmLoaded 2 Y N +.mv ArmLoadedPress 2 Y N +.mv RAExtendUnLoadArm 3 Extend Retract Stop +.mv PressReadyToBeLoaded 2 Y N +.mv PressReadyToBeUnLoaded 2 Y N +.mv RAArmOverDB 2 Y N +.mv RAArmOverLoadedPress 2 Y N +.mv RAUnLoadArmExtended 2 Y N +.mv ArmUnLoadedPress 2 Y N +.mv RARotaryMotor 3 CWise Stop CCWise +.mv RTOutReady 2 Y N +.mv RAArmOverUnLoadedPress 2 Y N +.mv RALoadArmExtended 2 Y N +.mv RAExtendLoadArm 3 Extend Retract Stop +.mv RAArmOverRT 2 Y N +.mv RALoadArmRetracted 2 Y N +.mv PieceGrabbedFromRT 2 Y N +.mv PieceOutArm 2 Y N +.mv LoadArmLoaded 2 Y N +.mv DBReady 2 Y N +.mv RAUnLoadArmRetracted 2 Y N +# RAExtendLoadArm = 2 +.mv RAExtendLoadArm$raw_nc44 3 Extend Retract Stop +.names RAExtendLoadArm$raw_nc44 +Stop +# RAExtendUnLoadArm = 2 +.mv RAExtendUnLoadArm$raw_nc45 3 Extend Retract Stop +.names RAExtendUnLoadArm$raw_nc45 +Stop +# RARotaryMotor = 1 +.mv RARotaryMotor$raw_nc46 3 CWise Stop CCWise +.names RARotaryMotor$raw_nc46 +Stop +# PieceOutArm = 1 +.mv PieceOutArm$raw_nc47 2 Y N +.names PieceOutArm$raw_nc47 +N +# ArmUnLoadedPress = 1 +.mv ArmUnLoadedPress$raw_nc48 2 Y N +.names ArmUnLoadedPress$raw_nc48 +N +# ArmLoadedPress = 1 +.mv ArmLoadedPress$raw_nc49 2 Y N +.names ArmLoadedPress$raw_nc49 +N +# PieceGrabbedFromRT = 1 +.mv PieceGrabbedFromRT$raw_nc4a 2 Y N +.names PieceGrabbedFromRT$raw_nc4a +N +# LoadArmLoaded = 1 +.mv LoadArmLoaded$raw_nc4b 2 Y N +.names LoadArmLoaded$raw_nc4b +N +# UnLoadArmLoaded = 1 +.mv UnLoadArmLoaded$raw_nc4c 2 Y N +.names UnLoadArmLoaded$raw_nc4c +N +# non-blocking assignments for initial +.mv _nc4e 2 Y N +.names _nc4e +N +# LoadArmLoaded == 1 +.names LoadArmLoaded _nc4e _nc4d +.def 0 +- =LoadArmLoaded 1 +.mv _nc50 2 Y N +.names _nc50 +N +# UnLoadArmLoaded == 1 +.names UnLoadArmLoaded _nc50 _nc4f +.def 0 +- =UnLoadArmLoaded 1 +# LoadArmLoaded == 1 && UnLoadArmLoaded == 1 +.names _nc4d _nc4f _nc51 +.def 0 +1 1 1 +.names _nc51 _nc52 +- =_nc51 +.mv _nc54 2 Y N +.names _nc54 +Y +# RAArmOverRT == 0 +.names RAArmOverRT _nc54 _nc53 +.def 0 +- =RAArmOverRT 1 +.names _nc53 _nc55 +- =_nc53 +.mv _nc57 2 Y N +.names _nc57 +Y +# RALoadArmRetracted == 0 +.names RALoadArmRetracted _nc57 _nc56 +.def 0 +- =RALoadArmRetracted 1 +.mv _nc59 2 Y N +.names _nc59 +Y +# RAUnLoadArmRetracted == 0 +.names RAUnLoadArmRetracted _nc59 _nc58 +.def 0 +- =RAUnLoadArmRetracted 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 +.names _nc56 _nc58 _nc5a +.def 0 +1 1 1 +.mv _nc5c 3 Extend Retract Stop +.names _nc5c +Stop +# RAExtendLoadArm == 2 +.names RAExtendLoadArm _nc5c _nc5b +.def 0 +- =RAExtendLoadArm 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 +.names _nc5a _nc5b _nc5d +.def 0 +1 1 1 +.mv _nc5f 3 Extend Retract Stop +.names _nc5f +Stop +# RAExtendUnLoadArm == 2 +.names RAExtendUnLoadArm _nc5f _nc5e +.def 0 +- =RAExtendUnLoadArm 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 +.names _nc5d _nc5e _nc60 +.def 0 +1 1 1 +.mv _nc62 3 CWise Stop CCWise +.names _nc62 +Stop +# RARotaryMotor == 1 +.names RARotaryMotor _nc62 _nc61 +.def 0 +- =RARotaryMotor 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1 +.names _nc60 _nc61 _nc63 +.def 0 +1 1 1 +.names _nc63 _nc64 +- =_nc63 +.mv _nc66 2 Y N +.names _nc66 +Y +# RTOutReady == 0 +.names RTOutReady _nc66 _nc65 +.def 0 +- =RTOutReady 1 +.names _nc65 _nc67 +- =_nc65 +# RAExtendLoadArm = 0 +.mv RAExtendLoadArm$_nc65_nc68$true 3 Extend Retract Stop +.names RAExtendLoadArm$_nc65_nc68$true +Extend +.mv _nc6a 2 Y N +.names _nc6a +Y +# PressReadyToBeUnLoaded == 0 +.names PressReadyToBeUnLoaded _nc6a _nc69 +.def 0 +- =PressReadyToBeUnLoaded 1 +.names _nc69 _nc6b +- =_nc69 +# RARotaryMotor = 2 +.mv RARotaryMotor$_nc69_nc6c$true 3 CWise Stop CCWise +.names RARotaryMotor$_nc69_nc6c$true +CCWise +# if/else (PressReadyToBeUnLoaded == 0) +.mv RARotaryMotor$_nc69$raw_nc6f 3 CWise Stop CCWise +.names RARotaryMotor$_nc69_nc6c$true RARotaryMotor _nc69 RARotaryMotor$_nc69$raw_nc6f +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_nc69_nc6c$true +# if/else (RTOutReady == 0) +.mv RAExtendLoadArm$_nc65$raw_nc72 3 Extend Retract Stop +.names RAExtendLoadArm$_nc65_nc68$true RAExtendLoadArm _nc65 RAExtendLoadArm$_nc65$raw_nc72 +- - 0 =RAExtendLoadArm +- - 1 =RAExtendLoadArm$_nc65_nc68$true +.mv RARotaryMotor$_nc65$raw_nc73 3 CWise Stop CCWise +.names RARotaryMotor RARotaryMotor$_nc69$raw_nc6f _nc65 RARotaryMotor$_nc65$raw_nc73 +- - 0 =RARotaryMotor$_nc69$raw_nc6f +- - 1 =RARotaryMotor +.mv _nc75 2 Y N +.names _nc75 +Y +# RALoadArmRetracted == 0 +.names RALoadArmRetracted _nc75 _nc74 +.def 0 +- =RALoadArmRetracted 1 +.mv _nc77 2 Y N +.names _nc77 +Y +# RAUnLoadArmRetracted == 0 +.names RAUnLoadArmRetracted _nc77 _nc76 +.def 0 +- =RAUnLoadArmRetracted 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 +.names _nc74 _nc76 _nc78 +.def 0 +1 1 1 +.mv _nc7a 3 Extend Retract Stop +.names _nc7a +Stop +# RAExtendLoadArm == 2 +.names RAExtendLoadArm _nc7a _nc79 +.def 0 +- =RAExtendLoadArm 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 +.names _nc78 _nc79 _nc7b +.def 0 +1 1 1 +.mv _nc7d 3 Extend Retract Stop +.names _nc7d +Stop +# RAExtendUnLoadArm == 2 +.names RAExtendUnLoadArm _nc7d _nc7c +.def 0 +- =RAExtendUnLoadArm 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 +.names _nc7b _nc7c _nc7e +.def 0 +1 1 1 +.mv _nc80 3 CWise Stop CCWise +.names _nc80 +CCWise +# RARotaryMotor == 2 +.names RARotaryMotor _nc80 _nc7f +.def 0 +- =RARotaryMotor 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 2 +.names _nc7e _nc7f _nc81 +.def 0 +1 1 1 +.names _nc81 _nc82 +- =_nc81 +.mv _nc84 2 Y N +.names _nc84 +Y +# PressReadyToBeUnLoaded == 0 +.names PressReadyToBeUnLoaded _nc84 _nc83 +.def 0 +- =PressReadyToBeUnLoaded 1 +.names _nc83 _nc85 +- =_nc83 +# RARotaryMotor = 1 +.mv RARotaryMotor$_nc83_nc86$true 3 CWise Stop CCWise +.names RARotaryMotor$_nc83_nc86$true +Stop +# RAExtendUnLoadArm = 0 +.mv RAExtendUnLoadArm$_nc83_nc87$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nc83_nc87$true +Extend +# if/else (PressReadyToBeUnLoaded == 0) +.mv RAExtendUnLoadArm$_nc83$raw_nc8c 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nc83_nc87$true RAExtendUnLoadArm _nc83 RAExtendUnLoadArm$_nc83$raw_nc8c +- - 0 =RAExtendUnLoadArm +- - 1 =RAExtendUnLoadArm$_nc83_nc87$true +.mv RARotaryMotor$_nc83$raw_nc8d 3 CWise Stop CCWise +.names RARotaryMotor$_nc83_nc86$true RARotaryMotor _nc83 RARotaryMotor$_nc83$raw_nc8d +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_nc83_nc86$true +.mv _nc8f 2 Y N +.names _nc8f +N +# RALoadArmRetracted == 1 +.names RALoadArmRetracted _nc8f _nc8e +.def 0 +- =RALoadArmRetracted 1 +.mv _nc91 2 Y N +.names _nc91 +N +# RALoadArmExtended == 1 +.names RALoadArmExtended _nc91 _nc90 +.def 0 +- =RALoadArmExtended 1 +# RALoadArmRetracted == 1 && RALoadArmExtended == 1 +.names _nc8e _nc90 _nc92 +.def 0 +1 1 1 +.mv _nc94 2 Y N +.names _nc94 +Y +# RAUnLoadArmRetracted == 0 +.names RAUnLoadArmRetracted _nc94 _nc93 +.def 0 +- =RAUnLoadArmRetracted 1 +# RALoadArmRetracted == 1 && RALoadArmExtended == 1 && RAUnLoadArmRetracted == 0 +.names _nc92 _nc93 _nc95 +.def 0 +1 1 1 +.mv _nc97 3 Extend Retract Stop +.names _nc97 +Extend +# RAExtendLoadArm == 0 +.names RAExtendLoadArm _nc97 _nc96 +.def 0 +- =RAExtendLoadArm 1 +# RALoadArmRetracted == 1 && RALoadArmExtended == 1 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 0 +.names _nc95 _nc96 _nc98 +.def 0 +1 1 1 +.mv _nc9a 3 Extend Retract Stop +.names _nc9a +Stop +# RAExtendUnLoadArm == 2 +.names RAExtendUnLoadArm _nc9a _nc99 +.def 0 +- =RAExtendUnLoadArm 1 +# RALoadArmRetracted == 1 && RALoadArmExtended == 1 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 0 && RAExtendUnLoadArm == 2 +.names _nc98 _nc99 _nc9b +.def 0 +1 1 1 +.mv _nc9d 3 CWise Stop CCWise +.names _nc9d +Stop +# RARotaryMotor == 1 +.names RARotaryMotor _nc9d _nc9c +.def 0 +- =RARotaryMotor 1 +# RALoadArmRetracted == 1 && RALoadArmExtended == 1 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 0 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1 +.names _nc9b _nc9c _nc9e +.def 0 +1 1 1 +.names _nc9e _nc9f +- =_nc9e +# RAExtendLoadArm = 1 +.mv RAExtendLoadArm$_nc9e_nca0$true 3 Extend Retract Stop +.names RAExtendLoadArm$_nc9e_nca0$true +Retract +# LoadArmLoaded = 0 +.mv LoadArmLoaded$_nc9e_nca1$true 2 Y N +.names LoadArmLoaded$_nc9e_nca1$true +Y +# PieceGrabbedFromRT = 0 +.mv PieceGrabbedFromRT$_nc9e_nca2$true 2 Y N +.names PieceGrabbedFromRT$_nc9e_nca2$true +Y +# if/else (RALoadArmRetracted == 1 && RALoadArmExtended == 1 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 0 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1) +.mv RAExtendLoadArm$_nc9e$raw_nca9 3 Extend Retract Stop +.names RAExtendLoadArm$_nc9e_nca0$true RAExtendLoadArm _nc9e RAExtendLoadArm$_nc9e$raw_nca9 +- - 0 =RAExtendLoadArm +- - 1 =RAExtendLoadArm$_nc9e_nca0$true +.mv PieceGrabbedFromRT$_nc9e$raw_ncaa 2 Y N +.names PieceGrabbedFromRT$_nc9e_nca2$true PieceGrabbedFromRT _nc9e PieceGrabbedFromRT$_nc9e$raw_ncaa +- - 0 =PieceGrabbedFromRT +- - 1 =PieceGrabbedFromRT$_nc9e_nca2$true +.mv LoadArmLoaded$_nc9e$raw_ncab 2 Y N +.names LoadArmLoaded$_nc9e_nca1$true LoadArmLoaded _nc9e LoadArmLoaded$_nc9e$raw_ncab +- - 0 =LoadArmLoaded +- - 1 =LoadArmLoaded$_nc9e_nca1$true +# if/else (RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 2) +.mv RAExtendUnLoadArm$_nc81$raw_ncb0 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nc83$raw_nc8c RAExtendUnLoadArm _nc81 RAExtendUnLoadArm$_nc81$raw_ncb0 +- - 0 =RAExtendUnLoadArm +- - 1 =RAExtendUnLoadArm$_nc83$raw_nc8c +.mv RARotaryMotor$_nc81$raw_ncb1 3 CWise Stop CCWise +.names RARotaryMotor$_nc83$raw_nc8d RARotaryMotor _nc81 RARotaryMotor$_nc81$raw_ncb1 +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_nc83$raw_nc8d +.mv RAExtendLoadArm$_nc81$raw_ncb2 3 Extend Retract Stop +.names RAExtendLoadArm RAExtendLoadArm$_nc9e$raw_nca9 _nc81 RAExtendLoadArm$_nc81$raw_ncb2 +- - 0 =RAExtendLoadArm$_nc9e$raw_nca9 +- - 1 =RAExtendLoadArm +.mv PieceGrabbedFromRT$_nc81$raw_ncb3 2 Y N +.names PieceGrabbedFromRT PieceGrabbedFromRT$_nc9e$raw_ncaa _nc81 PieceGrabbedFromRT$_nc81$raw_ncb3 +- - 0 =PieceGrabbedFromRT$_nc9e$raw_ncaa +- - 1 =PieceGrabbedFromRT +.mv LoadArmLoaded$_nc81$raw_ncb4 2 Y N +.names LoadArmLoaded LoadArmLoaded$_nc9e$raw_ncab _nc81 LoadArmLoaded$_nc81$raw_ncb4 +- - 0 =LoadArmLoaded$_nc9e$raw_ncab +- - 1 =LoadArmLoaded +# if/else (RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1) +.mv RARotaryMotor$_nc63$raw_ncb7 3 CWise Stop CCWise +.names RARotaryMotor$_nc65$raw_nc73 RARotaryMotor$_nc81$raw_ncb1 _nc63 RARotaryMotor$_nc63$raw_ncb7 +- - 0 =RARotaryMotor$_nc81$raw_ncb1 +- - 1 =RARotaryMotor$_nc65$raw_nc73 +.mv RAExtendLoadArm$_nc63$raw_ncb8 3 Extend Retract Stop +.names RAExtendLoadArm$_nc65$raw_nc72 RAExtendLoadArm$_nc81$raw_ncb2 _nc63 RAExtendLoadArm$_nc63$raw_ncb8 +- - 0 =RAExtendLoadArm$_nc81$raw_ncb2 +- - 1 =RAExtendLoadArm$_nc65$raw_nc72 +.mv RAExtendUnLoadArm$_nc63$raw_ncbb 3 Extend Retract Stop +.names RAExtendUnLoadArm RAExtendUnLoadArm$_nc81$raw_ncb0 _nc63 RAExtendUnLoadArm$_nc63$raw_ncbb +- - 0 =RAExtendUnLoadArm$_nc81$raw_ncb0 +- - 1 =RAExtendUnLoadArm +.mv PieceGrabbedFromRT$_nc63$raw_ncbe 2 Y N +.names PieceGrabbedFromRT PieceGrabbedFromRT$_nc81$raw_ncb3 _nc63 PieceGrabbedFromRT$_nc63$raw_ncbe +- - 0 =PieceGrabbedFromRT$_nc81$raw_ncb3 +- - 1 =PieceGrabbedFromRT +.mv LoadArmLoaded$_nc63$raw_ncbf 2 Y N +.names LoadArmLoaded LoadArmLoaded$_nc81$raw_ncb4 _nc63 LoadArmLoaded$_nc63$raw_ncbf +- - 0 =LoadArmLoaded$_nc81$raw_ncb4 +- - 1 =LoadArmLoaded +# if/else (RAArmOverRT == 0) +.mv RAExtendUnLoadArm$_nc53$raw_ncca 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nc63$raw_ncbb RAExtendUnLoadArm _nc53 RAExtendUnLoadArm$_nc53$raw_ncca +- - 0 =RAExtendUnLoadArm +- - 1 =RAExtendUnLoadArm$_nc63$raw_ncbb +.mv RARotaryMotor$_nc53$raw_nccb 3 CWise Stop CCWise +.names RARotaryMotor$_nc63$raw_ncb7 RARotaryMotor _nc53 RARotaryMotor$_nc53$raw_nccb +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_nc63$raw_ncb7 +.mv RAExtendLoadArm$_nc53$raw_nccc 3 Extend Retract Stop +.names RAExtendLoadArm$_nc63$raw_ncb8 RAExtendLoadArm _nc53 RAExtendLoadArm$_nc53$raw_nccc +- - 0 =RAExtendLoadArm +- - 1 =RAExtendLoadArm$_nc63$raw_ncb8 +.mv PieceGrabbedFromRT$_nc53$raw_nccd 2 Y N +.names PieceGrabbedFromRT$_nc63$raw_ncbe PieceGrabbedFromRT _nc53 PieceGrabbedFromRT$_nc53$raw_nccd +- - 0 =PieceGrabbedFromRT +- - 1 =PieceGrabbedFromRT$_nc63$raw_ncbe +.mv LoadArmLoaded$_nc53$raw_ncce 2 Y N +.names LoadArmLoaded$_nc63$raw_ncbf LoadArmLoaded _nc53 LoadArmLoaded$_nc53$raw_ncce +- - 0 =LoadArmLoaded +- - 1 =LoadArmLoaded$_nc63$raw_ncbf +.mv _ncd0 2 Y N +.names _ncd0 +Y +# RAArmOverLoadedPress == 0 +.names RAArmOverLoadedPress _ncd0 _nccf +.def 0 +- =RAArmOverLoadedPress 1 +.names _nccf _ncd1 +- =_nccf +.mv _ncd3 2 Y N +.names _ncd3 +Y +# RALoadArmRetracted == 0 +.names RALoadArmRetracted _ncd3 _ncd2 +.def 0 +- =RALoadArmRetracted 1 +.mv _ncd5 2 Y N +.names _ncd5 +Y +# RAUnLoadArmRetracted == 0 +.names RAUnLoadArmRetracted _ncd5 _ncd4 +.def 0 +- =RAUnLoadArmRetracted 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 +.names _ncd2 _ncd4 _ncd6 +.def 0 +1 1 1 +.mv _ncd8 3 Extend Retract Stop +.names _ncd8 +Stop +# RAExtendLoadArm == 2 +.names RAExtendLoadArm$_nc53$raw_nccc _ncd8 _ncd7 +.def 0 +- =RAExtendLoadArm$_nc53$raw_nccc 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 +.names _ncd6 _ncd7 _ncd9 +.def 0 +1 1 1 +.mv _ncdb 3 Extend Retract Stop +.names _ncdb +Stop +# RAExtendUnLoadArm == 2 +.names RAExtendUnLoadArm$_nc53$raw_ncca _ncdb _ncda +.def 0 +- =RAExtendUnLoadArm$_nc53$raw_ncca 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 +.names _ncd9 _ncda _ncdc +.def 0 +1 1 1 +.mv _ncde 3 CWise Stop CCWise +.names _ncde +Stop +# RARotaryMotor == 1 +.names RARotaryMotor$_nc53$raw_nccb _ncde _ncdd +.def 0 +- =RARotaryMotor$_nc53$raw_nccb 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1 +.names _ncdc _ncdd _ncdf +.def 0 +1 1 1 +.names _ncdf _nce0 +- =_ncdf +# RARotaryMotor = 0 +.mv RARotaryMotor$_ncdf_nce1$true 3 CWise Stop CCWise +.names RARotaryMotor$_ncdf_nce1$true +CWise +# if/else (RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1) +.mv RARotaryMotor$_ncdf$raw_nce3 3 CWise Stop CCWise +.names RARotaryMotor$_ncdf_nce1$true RARotaryMotor$_nc53$raw_nccb _ncdf RARotaryMotor$_ncdf$raw_nce3 +- - 0 =RARotaryMotor$_nc53$raw_nccb +- - 1 =RARotaryMotor$_ncdf_nce1$true +.mv _ncf7 2 Y N +.names _ncf7 +N +# RALoadArmRetracted == 1 +.names RALoadArmRetracted _ncf7 _ncf6 +.def 0 +- =RALoadArmRetracted 1 +.mv _ncf9 2 Y N +.names _ncf9 +N +# RALoadArmExtended == 1 +.names RALoadArmExtended _ncf9 _ncf8 +.def 0 +- =RALoadArmExtended 1 +# RALoadArmRetracted == 1 && RALoadArmExtended == 1 +.names _ncf6 _ncf8 _ncfa +.def 0 +1 1 1 +.mv _ncfc 2 Y N +.names _ncfc +Y +# RAUnLoadArmRetracted == 0 +.names RAUnLoadArmRetracted _ncfc _ncfb +.def 0 +- =RAUnLoadArmRetracted 1 +# RALoadArmRetracted == 1 && RALoadArmExtended == 1 && RAUnLoadArmRetracted == 0 +.names _ncfa _ncfb _ncfd +.def 0 +1 1 1 +.mv _ncff 3 Extend Retract Stop +.names _ncff +Retract +# RAExtendLoadArm == 1 +.names RAExtendLoadArm$_nc53$raw_nccc _ncff _ncfe +.def 0 +- =RAExtendLoadArm$_nc53$raw_nccc 1 +# RALoadArmRetracted == 1 && RALoadArmExtended == 1 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 1 +.names _ncfd _ncfe _nd00 +.def 0 +1 1 1 +.mv _nd02 3 Extend Retract Stop +.names _nd02 +Stop +# RAExtendUnLoadArm == 2 +.names RAExtendUnLoadArm$_nc53$raw_ncca _nd02 _nd01 +.def 0 +- =RAExtendUnLoadArm$_nc53$raw_ncca 1 +# RALoadArmRetracted == 1 && RALoadArmExtended == 1 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 1 && RAExtendUnLoadArm == 2 +.names _nd00 _nd01 _nd03 +.def 0 +1 1 1 +.mv _nd05 3 CWise Stop CCWise +.names _nd05 +Stop +# RARotaryMotor == 1 +.names RARotaryMotor$_ncdf$raw_nce3 _nd05 _nd04 +.def 0 +- =RARotaryMotor$_ncdf$raw_nce3 1 +# RALoadArmRetracted == 1 && RALoadArmExtended == 1 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 1 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1 +.names _nd03 _nd04 _nd06 +.def 0 +1 1 1 +.names _nd06 _nd07 +- =_nd06 +# RAExtendLoadArm = 2 +.mv RAExtendLoadArm$_nd06_nd08$true 3 Extend Retract Stop +.names RAExtendLoadArm$_nd06_nd08$true +Stop +# RARotaryMotor = 0 +.mv RARotaryMotor$_nd06_nd09$true 3 CWise Stop CCWise +.names RARotaryMotor$_nd06_nd09$true +CWise +# if/else (RALoadArmRetracted == 1 && RALoadArmExtended == 1 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 1 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1) +.mv RARotaryMotor$_nd06$raw_nd0b 3 CWise Stop CCWise +.names RARotaryMotor$_nd06_nd09$true RARotaryMotor$_ncdf$raw_nce3 _nd06 RARotaryMotor$_nd06$raw_nd0b +- - 0 =RARotaryMotor$_ncdf$raw_nce3 +- - 1 =RARotaryMotor$_nd06_nd09$true +.mv RAExtendLoadArm$_nd06$raw_nd0c 3 Extend Retract Stop +.names RAExtendLoadArm$_nd06_nd08$true RAExtendLoadArm$_nc53$raw_nccc _nd06 RAExtendLoadArm$_nd06$raw_nd0c +- - 0 =RAExtendLoadArm$_nc53$raw_nccc +- - 1 =RAExtendLoadArm$_nd06_nd08$true +# if/else (RAArmOverLoadedPress == 0) +.mv RARotaryMotor$_nccf$raw_nd1f 3 CWise Stop CCWise +.names RARotaryMotor$_nd06$raw_nd0b RARotaryMotor$_nc53$raw_nccb _nccf RARotaryMotor$_nccf$raw_nd1f +- - 0 =RARotaryMotor$_nc53$raw_nccb +- - 1 =RARotaryMotor$_nd06$raw_nd0b +.mv RAExtendLoadArm$_nccf$raw_nd20 3 Extend Retract Stop +.names RAExtendLoadArm$_nd06$raw_nd0c RAExtendLoadArm$_nc53$raw_nccc _nccf RAExtendLoadArm$_nccf$raw_nd20 +- - 0 =RAExtendLoadArm$_nc53$raw_nccc +- - 1 =RAExtendLoadArm$_nd06$raw_nd0c +.mv _nd33 2 Y N +.names _nd33 +Y +# RAArmOverUnLoadedPress == 0 +.names RAArmOverUnLoadedPress _nd33 _nd32 +.def 0 +- =RAArmOverUnLoadedPress 1 +.names _nd32 _nd34 +- =_nd32 +.mv _nd36 2 Y N +.names _nd36 +Y +# RALoadArmRetracted == 0 +.names RALoadArmRetracted _nd36 _nd35 +.def 0 +- =RALoadArmRetracted 1 +.mv _nd38 2 Y N +.names _nd38 +Y +# RAUnLoadArmRetracted == 0 +.names RAUnLoadArmRetracted _nd38 _nd37 +.def 0 +- =RAUnLoadArmRetracted 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 +.names _nd35 _nd37 _nd39 +.def 0 +1 1 1 +.mv _nd3b 3 Extend Retract Stop +.names _nd3b +Stop +# RAExtendLoadArm == 2 +.names RAExtendLoadArm$_nccf$raw_nd20 _nd3b _nd3a +.def 0 +- =RAExtendLoadArm$_nccf$raw_nd20 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 +.names _nd39 _nd3a _nd3c +.def 0 +1 1 1 +.mv _nd3e 3 Extend Retract Stop +.names _nd3e +Stop +# RAExtendUnLoadArm == 2 +.names RAExtendUnLoadArm$_nc53$raw_ncca _nd3e _nd3d +.def 0 +- =RAExtendUnLoadArm$_nc53$raw_ncca 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 +.names _nd3c _nd3d _nd3f +.def 0 +1 1 1 +.mv _nd41 3 CWise Stop CCWise +.names _nd41 +Stop +# RARotaryMotor == 1 +.names RARotaryMotor$_nccf$raw_nd1f _nd41 _nd40 +.def 0 +- =RARotaryMotor$_nccf$raw_nd1f 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1 +.names _nd3f _nd40 _nd42 +.def 0 +1 1 1 +.names _nd42 _nd43 +- =_nd42 +.mv _nd45 2 Y N +.names _nd45 +Y +# PressReadyToBeUnLoaded == 0 +.names PressReadyToBeUnLoaded _nd45 _nd44 +.def 0 +- =PressReadyToBeUnLoaded 1 +.names _nd44 _nd46 +- =_nd44 +# RAExtendLoadArm = 0 +.mv RAExtendLoadArm$_nd44_nd47$true 3 Extend Retract Stop +.names RAExtendLoadArm$_nd44_nd47$true +Extend +# RARotaryMotor = 0 +.mv RARotaryMotor$_nd44_nd48$false 3 CWise Stop CCWise +.names RARotaryMotor$_nd44_nd48$false +CWise +# if/else (PressReadyToBeUnLoaded == 0) +.mv RARotaryMotor$_nd44$raw_nd4a 3 CWise Stop CCWise +.names RARotaryMotor$_nccf$raw_nd1f RARotaryMotor$_nd44_nd48$false _nd44 RARotaryMotor$_nd44$raw_nd4a +- - 0 =RARotaryMotor$_nd44_nd48$false +- - 1 =RARotaryMotor$_nccf$raw_nd1f +.mv RAExtendLoadArm$_nd44$raw_nd4b 3 Extend Retract Stop +.names RAExtendLoadArm$_nd44_nd47$true RAExtendLoadArm$_nccf$raw_nd20 _nd44 RAExtendLoadArm$_nd44$raw_nd4b +- - 0 =RAExtendLoadArm$_nccf$raw_nd20 +- - 1 =RAExtendLoadArm$_nd44_nd47$true +.mv _nd5e 2 Y N +.names _nd5e +Y +# RALoadArmRetracted == 0 +.names RALoadArmRetracted _nd5e _nd5d +.def 0 +- =RALoadArmRetracted 1 +.mv _nd60 2 Y N +.names _nd60 +Y +# RAUnLoadArmRetracted == 0 +.names RAUnLoadArmRetracted _nd60 _nd5f +.def 0 +- =RAUnLoadArmRetracted 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 +.names _nd5d _nd5f _nd61 +.def 0 +1 1 1 +.mv _nd63 3 Extend Retract Stop +.names _nd63 +Stop +# RAExtendLoadArm == 2 +.names RAExtendLoadArm$_nccf$raw_nd20 _nd63 _nd62 +.def 0 +- =RAExtendLoadArm$_nccf$raw_nd20 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 +.names _nd61 _nd62 _nd64 +.def 0 +1 1 1 +.mv _nd66 3 Extend Retract Stop +.names _nd66 +Stop +# RAExtendUnLoadArm == 2 +.names RAExtendUnLoadArm$_nc53$raw_ncca _nd66 _nd65 +.def 0 +- =RAExtendUnLoadArm$_nc53$raw_ncca 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 +.names _nd64 _nd65 _nd67 +.def 0 +1 1 1 +.mv _nd69 3 CWise Stop CCWise +.names _nd69 +CWise +# RARotaryMotor == 0 +.names RARotaryMotor$_nccf$raw_nd1f _nd69 _nd68 +.def 0 +- =RARotaryMotor$_nccf$raw_nd1f 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 0 +.names _nd67 _nd68 _nd6a +.def 0 +1 1 1 +.names _nd6a _nd6b +- =_nd6a +# RARotaryMotor = 1 +.mv RARotaryMotor$_nd6a_nd6c$true 3 CWise Stop CCWise +.names RARotaryMotor$_nd6a_nd6c$true +Stop +.mv _nd6e 2 Y N +.names _nd6e +Y +# RTOutReady == 0 +.names RTOutReady _nd6e _nd6d +.def 0 +- =RTOutReady 1 +.names _nd6d _nd6f +- =_nd6d +# RAExtendLoadArm = 0 +.mv RAExtendLoadArm$_nd6d_nd70$true 3 Extend Retract Stop +.names RAExtendLoadArm$_nd6d_nd70$true +Extend +# if/else (RTOutReady == 0) +.mv RAExtendLoadArm$_nd6d$raw_nd73 3 Extend Retract Stop +.names RAExtendLoadArm$_nd6d_nd70$true RAExtendLoadArm$_nccf$raw_nd20 _nd6d RAExtendLoadArm$_nd6d$raw_nd73 +- - 0 =RAExtendLoadArm$_nccf$raw_nd20 +- - 1 =RAExtendLoadArm$_nd6d_nd70$true +.mv _nd86 2 Y N +.names _nd86 +Y +# RALoadArmRetracted == 0 +.names RALoadArmRetracted _nd86 _nd85 +.def 0 +- =RALoadArmRetracted 1 +.mv _nd88 2 Y N +.names _nd88 +N +# RAUnLoadArmRetracted == 1 +.names RAUnLoadArmRetracted _nd88 _nd87 +.def 0 +- =RAUnLoadArmRetracted 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 1 +.names _nd85 _nd87 _nd89 +.def 0 +1 1 1 +.mv _nd8b 2 Y N +.names _nd8b +N +# RAUnLoadArmExtended == 1 +.names RAUnLoadArmExtended _nd8b _nd8a +.def 0 +- =RAUnLoadArmExtended 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 1 && RAUnLoadArmExtended == 1 +.names _nd89 _nd8a _nd8c +.def 0 +1 1 1 +.mv _nd8e 3 Extend Retract Stop +.names _nd8e +Stop +# RAExtendLoadArm == 2 +.names RAExtendLoadArm$_nccf$raw_nd20 _nd8e _nd8d +.def 0 +- =RAExtendLoadArm$_nccf$raw_nd20 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 1 && RAUnLoadArmExtended == 1 && RAExtendLoadArm == 2 +.names _nd8c _nd8d _nd8f +.def 0 +1 1 1 +.mv _nd91 3 Extend Retract Stop +.names _nd91 +Extend +# RAExtendUnLoadArm == 0 +.names RAExtendUnLoadArm$_nc53$raw_ncca _nd91 _nd90 +.def 0 +- =RAExtendUnLoadArm$_nc53$raw_ncca 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 1 && RAUnLoadArmExtended == 1 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 0 +.names _nd8f _nd90 _nd92 +.def 0 +1 1 1 +.mv _nd94 3 CWise Stop CCWise +.names _nd94 +Stop +# RARotaryMotor == 1 +.names RARotaryMotor$_nccf$raw_nd1f _nd94 _nd93 +.def 0 +- =RARotaryMotor$_nccf$raw_nd1f 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 1 && RAUnLoadArmExtended == 1 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 0 && RARotaryMotor == 1 +.names _nd92 _nd93 _nd95 +.def 0 +1 1 1 +.names _nd95 _nd96 +- =_nd95 +# RAExtendUnLoadArm = 1 +.mv RAExtendUnLoadArm$_nd95_nd97$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nd95_nd97$true +Retract +# ArmUnLoadedPress = 0 +.mv ArmUnLoadedPress$_nd95_nd98$true 2 Y N +.names ArmUnLoadedPress$_nd95_nd98$true +Y +# UnLoadArmLoaded = 0 +.mv UnLoadArmLoaded$_nd95_nd99$true 2 Y N +.names UnLoadArmLoaded$_nd95_nd99$true +Y +# if/else (RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 1 && RAUnLoadArmExtended == 1 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 0 && RARotaryMotor == 1) +.mv RAExtendUnLoadArm$_nd95$raw_nd9b 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nd95_nd97$true RAExtendUnLoadArm$_nc53$raw_ncca _nd95 RAExtendUnLoadArm$_nd95$raw_nd9b +- - 0 =RAExtendUnLoadArm$_nc53$raw_ncca +- - 1 =RAExtendUnLoadArm$_nd95_nd97$true +.mv UnLoadArmLoaded$_nd95$raw_nda8 2 Y N +.names UnLoadArmLoaded$_nd95_nd99$true UnLoadArmLoaded _nd95 UnLoadArmLoaded$_nd95$raw_nda8 +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_nd95_nd99$true +.mv ArmUnLoadedPress$_nd95$raw_ndaa 2 Y N +.names ArmUnLoadedPress$_nd95_nd98$true ArmUnLoadedPress _nd95 ArmUnLoadedPress$_nd95$raw_ndaa +- - 0 =ArmUnLoadedPress +- - 1 =ArmUnLoadedPress$_nd95_nd98$true +# if/else (RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 0) +.mv RAExtendUnLoadArm$_nd6a$raw_ndb4 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nc53$raw_ncca RAExtendUnLoadArm$_nd95$raw_nd9b _nd6a RAExtendUnLoadArm$_nd6a$raw_ndb4 +- - 0 =RAExtendUnLoadArm$_nd95$raw_nd9b +- - 1 =RAExtendUnLoadArm$_nc53$raw_ncca +.mv RARotaryMotor$_nd6a$raw_ndb5 3 CWise Stop CCWise +.names RARotaryMotor$_nd6a_nd6c$true RARotaryMotor$_nccf$raw_nd1f _nd6a RARotaryMotor$_nd6a$raw_ndb5 +- - 0 =RARotaryMotor$_nccf$raw_nd1f +- - 1 =RARotaryMotor$_nd6a_nd6c$true +.mv RAExtendLoadArm$_nd6a$raw_ndb6 3 Extend Retract Stop +.names RAExtendLoadArm$_nd6d$raw_nd73 RAExtendLoadArm$_nccf$raw_nd20 _nd6a RAExtendLoadArm$_nd6a$raw_ndb6 +- - 0 =RAExtendLoadArm$_nccf$raw_nd20 +- - 1 =RAExtendLoadArm$_nd6d$raw_nd73 +.mv UnLoadArmLoaded$_nd6a$raw_ndc3 2 Y N +.names UnLoadArmLoaded UnLoadArmLoaded$_nd95$raw_nda8 _nd6a UnLoadArmLoaded$_nd6a$raw_ndc3 +- - 0 =UnLoadArmLoaded$_nd95$raw_nda8 +- - 1 =UnLoadArmLoaded +.mv ArmUnLoadedPress$_nd6a$raw_ndc5 2 Y N +.names ArmUnLoadedPress ArmUnLoadedPress$_nd95$raw_ndaa _nd6a ArmUnLoadedPress$_nd6a$raw_ndc5 +- - 0 =ArmUnLoadedPress$_nd95$raw_ndaa +- - 1 =ArmUnLoadedPress +# if/else (RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1) +.mv RAExtendUnLoadArm$_nd42$raw_ndca 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nc53$raw_ncca RAExtendUnLoadArm$_nd6a$raw_ndb4 _nd42 RAExtendUnLoadArm$_nd42$raw_ndca +- - 0 =RAExtendUnLoadArm$_nd6a$raw_ndb4 +- - 1 =RAExtendUnLoadArm$_nc53$raw_ncca +.mv RARotaryMotor$_nd42$raw_ndcb 3 CWise Stop CCWise +.names RARotaryMotor$_nd44$raw_nd4a RARotaryMotor$_nd6a$raw_ndb5 _nd42 RARotaryMotor$_nd42$raw_ndcb +- - 0 =RARotaryMotor$_nd6a$raw_ndb5 +- - 1 =RARotaryMotor$_nd44$raw_nd4a +.mv RAExtendLoadArm$_nd42$raw_ndcc 3 Extend Retract Stop +.names RAExtendLoadArm$_nd44$raw_nd4b RAExtendLoadArm$_nd6a$raw_ndb6 _nd42 RAExtendLoadArm$_nd42$raw_ndcc +- - 0 =RAExtendLoadArm$_nd6a$raw_ndb6 +- - 1 =RAExtendLoadArm$_nd44$raw_nd4b +.mv UnLoadArmLoaded$_nd42$raw_ndd9 2 Y N +.names UnLoadArmLoaded UnLoadArmLoaded$_nd6a$raw_ndc3 _nd42 UnLoadArmLoaded$_nd42$raw_ndd9 +- - 0 =UnLoadArmLoaded$_nd6a$raw_ndc3 +- - 1 =UnLoadArmLoaded +.mv ArmUnLoadedPress$_nd42$raw_nddb 2 Y N +.names ArmUnLoadedPress ArmUnLoadedPress$_nd6a$raw_ndc5 _nd42 ArmUnLoadedPress$_nd42$raw_nddb +- - 0 =ArmUnLoadedPress$_nd6a$raw_ndc5 +- - 1 =ArmUnLoadedPress +# if/else (RAArmOverUnLoadedPress == 0) +.mv RAExtendUnLoadArm$_nd32$raw_nde1 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nd42$raw_ndca RAExtendUnLoadArm$_nc53$raw_ncca _nd32 RAExtendUnLoadArm$_nd32$raw_nde1 +- - 0 =RAExtendUnLoadArm$_nc53$raw_ncca +- - 1 =RAExtendUnLoadArm$_nd42$raw_ndca +.mv RARotaryMotor$_nd32$raw_nde3 3 CWise Stop CCWise +.names RARotaryMotor$_nd42$raw_ndcb RARotaryMotor$_nccf$raw_nd1f _nd32 RARotaryMotor$_nd32$raw_nde3 +- - 0 =RARotaryMotor$_nccf$raw_nd1f +- - 1 =RARotaryMotor$_nd42$raw_ndcb +.mv RAExtendLoadArm$_nd32$raw_nde4 3 Extend Retract Stop +.names RAExtendLoadArm$_nd42$raw_ndcc RAExtendLoadArm$_nccf$raw_nd20 _nd32 RAExtendLoadArm$_nd32$raw_nde4 +- - 0 =RAExtendLoadArm$_nccf$raw_nd20 +- - 1 =RAExtendLoadArm$_nd42$raw_ndcc +.mv UnLoadArmLoaded$_nd32$raw_ndee 2 Y N +.names UnLoadArmLoaded$_nd42$raw_ndd9 UnLoadArmLoaded _nd32 UnLoadArmLoaded$_nd32$raw_ndee +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_nd42$raw_ndd9 +.mv ArmUnLoadedPress$_nd32$raw_ndf0 2 Y N +.names ArmUnLoadedPress$_nd42$raw_nddb ArmUnLoadedPress _nd32 ArmUnLoadedPress$_nd32$raw_ndf0 +- - 0 =ArmUnLoadedPress +- - 1 =ArmUnLoadedPress$_nd42$raw_nddb +.mv _ndfb 2 Y N +.names _ndfb +Y +# RAArmOverDB == 0 +.names RAArmOverDB _ndfb _ndfa +.def 0 +- =RAArmOverDB 1 +.names _ndfa _ndfc +- =_ndfa +.mv _ndfe 2 Y N +.names _ndfe +Y +# RALoadArmRetracted == 0 +.names RALoadArmRetracted _ndfe _ndfd +.def 0 +- =RALoadArmRetracted 1 +.mv _ne00 2 Y N +.names _ne00 +Y +# RAUnLoadArmRetracted == 0 +.names RAUnLoadArmRetracted _ne00 _ndff +.def 0 +- =RAUnLoadArmRetracted 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 +.names _ndfd _ndff _ne01 +.def 0 +1 1 1 +.mv _ne03 3 Extend Retract Stop +.names _ne03 +Stop +# RAExtendLoadArm == 2 +.names RAExtendLoadArm$_nd32$raw_nde4 _ne03 _ne02 +.def 0 +- =RAExtendLoadArm$_nd32$raw_nde4 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 +.names _ne01 _ne02 _ne04 +.def 0 +1 1 1 +.mv _ne06 3 Extend Retract Stop +.names _ne06 +Stop +# RAExtendUnLoadArm == 2 +.names RAExtendUnLoadArm$_nd32$raw_nde1 _ne06 _ne05 +.def 0 +- =RAExtendUnLoadArm$_nd32$raw_nde1 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 +.names _ne04 _ne05 _ne07 +.def 0 +1 1 1 +.mv _ne09 3 CWise Stop CCWise +.names _ne09 +Stop +# RARotaryMotor == 1 +.names RARotaryMotor$_nd32$raw_nde3 _ne09 _ne08 +.def 0 +- =RARotaryMotor$_nd32$raw_nde3 1 +# RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1 +.names _ne07 _ne08 _ne0a +.def 0 +1 1 1 +.names _ne0a _ne0b +- =_ne0a +# RARotaryMotor = 0 +.mv RARotaryMotor$_ne0a_ne0c$true 3 CWise Stop CCWise +.names RARotaryMotor$_ne0a_ne0c$true +CWise +# if/else (RALoadArmRetracted == 0 && RAUnLoadArmRetracted == 0 && RAExtendLoadArm == 2 && RAExtendUnLoadArm == 2 && RARotaryMotor == 1) +.mv RARotaryMotor$_ne0a$raw_ne10 3 CWise Stop CCWise +.names RARotaryMotor$_ne0a_ne0c$true RARotaryMotor$_nd32$raw_nde3 _ne0a RARotaryMotor$_ne0a$raw_ne10 +- - 0 =RARotaryMotor$_nd32$raw_nde3 +- - 1 =RARotaryMotor$_ne0a_ne0c$true +.mv _ne2a 3 Extend Retract Stop +.names _ne2a +Retract +# RAExtendUnLoadArm == 1 +.names RAExtendUnLoadArm$_nd32$raw_nde1 _ne2a _ne29 +.def 0 +- =RAExtendUnLoadArm$_nd32$raw_nde1 1 +.mv _ne2c 2 Y N +.names _ne2c +N +# RAUnLoadArmExtended == 1 +.names RAUnLoadArmExtended _ne2c _ne2b +.def 0 +- =RAUnLoadArmExtended 1 +# RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 +.names _ne29 _ne2b _ne2d +.def 0 +1 1 1 +.mv _ne2f 2 Y N +.names _ne2f +N +# RAUnLoadArmRetracted == 1 +.names RAUnLoadArmRetracted _ne2f _ne2e +.def 0 +- =RAUnLoadArmRetracted 1 +# RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1 +.names _ne2d _ne2e _ne30 +.def 0 +1 1 1 +.names _ne30 _ne31 +- =_ne30 +# RAExtendUnLoadArm = 2 +.mv RAExtendUnLoadArm$_ne30_ne32$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_ne30_ne32$true +Stop +# RARotaryMotor = 0 +.mv RARotaryMotor$_ne30_ne33$true 3 CWise Stop CCWise +.names RARotaryMotor$_ne30_ne33$true +CWise +# if/else (RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1) +.mv RAExtendUnLoadArm$_ne30$raw_ne35 3 Extend Retract Stop +.names RAExtendUnLoadArm$_ne30_ne32$true RAExtendUnLoadArm$_nd32$raw_nde1 _ne30 RAExtendUnLoadArm$_ne30$raw_ne35 +- - 0 =RAExtendUnLoadArm$_nd32$raw_nde1 +- - 1 =RAExtendUnLoadArm$_ne30_ne32$true +.mv RARotaryMotor$_ne30$raw_ne37 3 CWise Stop CCWise +.names RARotaryMotor$_ne30_ne33$true RARotaryMotor$_ne0a$raw_ne10 _ne30 RARotaryMotor$_ne30$raw_ne37 +- - 0 =RARotaryMotor$_ne0a$raw_ne10 +- - 1 =RARotaryMotor$_ne30_ne33$true +.mv _ne51 3 CWise Stop CCWise +.names _ne51 +CWise +# RARotaryMotor == 0 +.names RARotaryMotor$_ne30$raw_ne37 _ne51 _ne50 +.def 0 +- =RARotaryMotor$_ne30$raw_ne37 1 +.names _ne50 _ne52 +- =_ne50 +.mv _ne54 2 Y N +.names _ne54 +Y +# PressReadyToBeUnLoaded == 0 +.names PressReadyToBeUnLoaded _ne54 _ne53 +.def 0 +- =PressReadyToBeUnLoaded 1 +.mv _ne56 2 Y N +.names _ne56 +N +# RTOutReady == 1 +.names RTOutReady _ne56 _ne55 +.def 0 +- =RTOutReady 1 +# PressReadyToBeUnLoaded == 0 && RTOutReady == 1 +.names _ne53 _ne55 _ne57 +.def 0 +1 1 1 +.names _ne57 _ne58 +- =_ne57 +# RARotaryMotor = 1 +.mv RARotaryMotor$_ne57_ne59$true 3 CWise Stop CCWise +.names RARotaryMotor$_ne57_ne59$true +Stop +# RAExtendUnLoadArm = 0 +.mv RAExtendUnLoadArm$_ne57_ne5a$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_ne57_ne5a$true +Extend +# if/else (PressReadyToBeUnLoaded == 0 && RTOutReady == 1) +.mv RAExtendUnLoadArm$_ne57$raw_ne5b 3 Extend Retract Stop +.names RAExtendUnLoadArm$_ne57_ne5a$true RAExtendUnLoadArm$_ne30$raw_ne35 _ne57 RAExtendUnLoadArm$_ne57$raw_ne5b +- - 0 =RAExtendUnLoadArm$_ne30$raw_ne35 +- - 1 =RAExtendUnLoadArm$_ne57_ne5a$true +.mv RARotaryMotor$_ne57$raw_ne5d 3 CWise Stop CCWise +.names RARotaryMotor$_ne57_ne59$true RARotaryMotor$_ne30$raw_ne37 _ne57 RARotaryMotor$_ne57$raw_ne5d +- - 0 =RARotaryMotor$_ne30$raw_ne37 +- - 1 =RARotaryMotor$_ne57_ne59$true +# if/else (RARotaryMotor == 0) +.mv RAExtendUnLoadArm$_ne50$raw_ne78 3 Extend Retract Stop +.names RAExtendUnLoadArm$_ne57$raw_ne5b RAExtendUnLoadArm$_ne30$raw_ne35 _ne50 RAExtendUnLoadArm$_ne50$raw_ne78 +- - 0 =RAExtendUnLoadArm$_ne30$raw_ne35 +- - 1 =RAExtendUnLoadArm$_ne57$raw_ne5b +.mv RARotaryMotor$_ne50$raw_ne7a 3 CWise Stop CCWise +.names RARotaryMotor$_ne57$raw_ne5d RARotaryMotor$_ne30$raw_ne37 _ne50 RARotaryMotor$_ne50$raw_ne7a +- - 0 =RARotaryMotor$_ne30$raw_ne37 +- - 1 =RARotaryMotor$_ne57$raw_ne5d +# if/else (RAArmOverDB == 0) +.mv RAExtendUnLoadArm$_ndfa$raw_ne93 3 Extend Retract Stop +.names RAExtendUnLoadArm$_ne50$raw_ne78 RAExtendUnLoadArm$_nd32$raw_nde1 _ndfa RAExtendUnLoadArm$_ndfa$raw_ne93 +- - 0 =RAExtendUnLoadArm$_nd32$raw_nde1 +- - 1 =RAExtendUnLoadArm$_ne50$raw_ne78 +.mv RARotaryMotor$_ndfa$raw_ne95 3 CWise Stop CCWise +.names RARotaryMotor$_ne50$raw_ne7a RARotaryMotor$_nd32$raw_nde3 _ndfa RARotaryMotor$_ndfa$raw_ne95 +- - 0 =RARotaryMotor$_nd32$raw_nde3 +- - 1 =RARotaryMotor$_ne50$raw_ne7a +.mv _neb0 2 Y N +.names _neb0 +N +# LoadArmLoaded == 1 +.names LoadArmLoaded _neb0 _neaf +.def 0 +- =LoadArmLoaded 1 +.mv _neb2 2 Y N +.names _neb2 +Y +# UnLoadArmLoaded == 0 +.names UnLoadArmLoaded _neb2 _neb1 +.def 0 +- =UnLoadArmLoaded 1 +# LoadArmLoaded == 1 && UnLoadArmLoaded == 0 +.names _neaf _neb1 _neb3 +.def 0 +1 1 1 +.names _neb3 _neb4 +- =_neb3 +.mv _neb6 2 Y N +.names _neb6 +Y +# RAArmOverUnLoadedPress == 0 +.names RAArmOverUnLoadedPress _neb6 _neb5 +.def 0 +- =RAArmOverUnLoadedPress 1 +.names _neb5 _neb7 +- =_neb5 +.mv _neb9 3 CWise Stop CCWise +.names _neb9 +CCWise +# RARotaryMotor == 2 +.names RARotaryMotor _neb9 _neb8 +.def 0 +- =RARotaryMotor 1 +.names _neb8 _neba +- =_neb8 +# RARotaryMotor = 1 +.mv RARotaryMotor$_neb8_nebb$true 3 CWise Stop CCWise +.names RARotaryMotor$_neb8_nebb$true +Stop +# RAExtendUnLoadArm = 0 +.mv RAExtendUnLoadArm$_neb8_nebc$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_neb8_nebc$true +Extend +# if/else (RARotaryMotor == 2) +.mv RAExtendUnLoadArm$_neb8$raw_nec1 3 Extend Retract Stop +.names RAExtendUnLoadArm$_neb8_nebc$true RAExtendUnLoadArm _neb8 RAExtendUnLoadArm$_neb8$raw_nec1 +- - 0 =RAExtendUnLoadArm +- - 1 =RAExtendUnLoadArm$_neb8_nebc$true +.mv RARotaryMotor$_neb8$raw_nec2 3 CWise Stop CCWise +.names RARotaryMotor$_neb8_nebb$true RARotaryMotor _neb8 RARotaryMotor$_neb8$raw_nec2 +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_neb8_nebb$true +.mv _nec4 3 Extend Retract Stop +.names _nec4 +Retract +# RAExtendUnLoadArm == 1 +.names RAExtendUnLoadArm$_neb8$raw_nec1 _nec4 _nec3 +.def 0 +- =RAExtendUnLoadArm$_neb8$raw_nec1 1 +.mv _nec6 2 Y N +.names _nec6 +N +# RAUnLoadArmExtended == 1 +.names RAUnLoadArmExtended _nec6 _nec5 +.def 0 +- =RAUnLoadArmExtended 1 +# RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 +.names _nec3 _nec5 _nec7 +.def 0 +1 1 1 +.mv _nec9 2 Y N +.names _nec9 +N +# RAUnLoadArmRetracted == 1 +.names RAUnLoadArmRetracted _nec9 _nec8 +.def 0 +- =RAUnLoadArmRetracted 1 +# RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1 +.names _nec7 _nec8 _neca +.def 0 +1 1 1 +.names _neca _necb +- =_neca +# RAExtendUnLoadArm = 2 +.mv RAExtendUnLoadArm$_neca_necc$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_neca_necc$true +Stop +# RARotaryMotor = 2 +.mv RARotaryMotor$_neca_necd$true 3 CWise Stop CCWise +.names RARotaryMotor$_neca_necd$true +CCWise +# if/else (RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1) +.mv RAExtendUnLoadArm$_neca$raw_nece 3 Extend Retract Stop +.names RAExtendUnLoadArm$_neca_necc$true RAExtendUnLoadArm$_neb8$raw_nec1 _neca RAExtendUnLoadArm$_neca$raw_nece +- - 0 =RAExtendUnLoadArm$_neb8$raw_nec1 +- - 1 =RAExtendUnLoadArm$_neca_necc$true +.mv RARotaryMotor$_neca$raw_necf 3 CWise Stop CCWise +.names RARotaryMotor$_neca_necd$true RARotaryMotor$_neb8$raw_nec2 _neca RARotaryMotor$_neca$raw_necf +- - 0 =RARotaryMotor$_neb8$raw_nec2 +- - 1 =RARotaryMotor$_neca_necd$true +# if/else (RAArmOverUnLoadedPress == 0) +.mv RAExtendUnLoadArm$_neb5$raw_neda 3 Extend Retract Stop +.names RAExtendUnLoadArm$_neca$raw_nece RAExtendUnLoadArm _neb5 RAExtendUnLoadArm$_neb5$raw_neda +- - 0 =RAExtendUnLoadArm +- - 1 =RAExtendUnLoadArm$_neca$raw_nece +.mv RARotaryMotor$_neb5$raw_nedb 3 CWise Stop CCWise +.names RARotaryMotor$_neca$raw_necf RARotaryMotor _neb5 RARotaryMotor$_neb5$raw_nedb +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_neca$raw_necf +.mv _nedd 2 Y N +.names _nedd +Y +# RAArmOverDB == 0 +.names RAArmOverDB _nedd _nedc +.def 0 +- =RAArmOverDB 1 +.names _nedc _nede +- =_nedc +.mv _nee0 3 Extend Retract Stop +.names _nee0 +Extend +# RAExtendUnLoadArm == 0 +.names RAExtendUnLoadArm$_neb5$raw_neda _nee0 _nedf +.def 0 +- =RAExtendUnLoadArm$_neb5$raw_neda 1 +.mv _nee2 2 Y N +.names _nee2 +N +# RAUnLoadArmExtended == 1 +.names RAUnLoadArmExtended _nee2 _nee1 +.def 0 +- =RAUnLoadArmExtended 1 +# RAExtendUnLoadArm == 0 && RAUnLoadArmExtended == 1 +.names _nedf _nee1 _nee3 +.def 0 +1 1 1 +.mv _nee5 2 Y N +.names _nee5 +N +# RAUnLoadArmRetracted == 1 +.names RAUnLoadArmRetracted _nee5 _nee4 +.def 0 +- =RAUnLoadArmRetracted 1 +# RAExtendUnLoadArm == 0 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1 +.names _nee3 _nee4 _nee6 +.def 0 +1 1 1 +.names _nee6 _nee7 +- =_nee6 +.mv _nee9 2 Y N +.names _nee9 +Y +# DBReady == 0 +.names DBReady _nee9 _nee8 +.def 0 +- =DBReady 1 +.names _nee8 _neea +- =_nee8 +# RAExtendUnLoadArm = 1 +.mv RAExtendUnLoadArm$_nee8_neeb$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nee8_neeb$true +Retract +# PieceOutArm = 0 +.mv PieceOutArm$_nee8_neec$true 2 Y N +.names PieceOutArm$_nee8_neec$true +Y +# UnLoadArmLoaded = 1 +.mv UnLoadArmLoaded$_nee8_need$true 2 Y N +.names UnLoadArmLoaded$_nee8_need$true +N +# RAExtendUnLoadArm = 2 +.mv RAExtendUnLoadArm$_nee8_neee$false 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nee8_neee$false +Stop +# if/else (DBReady == 0) +.mv RAExtendUnLoadArm$_nee8$raw_nef0 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nee8_neeb$true RAExtendUnLoadArm$_nee8_neee$false _nee8 RAExtendUnLoadArm$_nee8$raw_nef0 +- - 0 =RAExtendUnLoadArm$_nee8_neee$false +- - 1 =RAExtendUnLoadArm$_nee8_neeb$true +.mv UnLoadArmLoaded$_nee8$raw_nef7 2 Y N +.names UnLoadArmLoaded$_nee8_need$true UnLoadArmLoaded _nee8 UnLoadArmLoaded$_nee8$raw_nef7 +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_nee8_need$true +.mv PieceOutArm$_nee8$raw_nefa 2 Y N +.names PieceOutArm$_nee8_neec$true PieceOutArm _nee8 PieceOutArm$_nee8$raw_nefa +- - 0 =PieceOutArm +- - 1 =PieceOutArm$_nee8_neec$true +# if/else (RAExtendUnLoadArm == 0 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1) +.mv RAExtendUnLoadArm$_nee6$raw_nefe 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nee8$raw_nef0 RAExtendUnLoadArm$_neb5$raw_neda _nee6 RAExtendUnLoadArm$_nee6$raw_nefe +- - 0 =RAExtendUnLoadArm$_neb5$raw_neda +- - 1 =RAExtendUnLoadArm$_nee8$raw_nef0 +.mv UnLoadArmLoaded$_nee6$raw_nf05 2 Y N +.names UnLoadArmLoaded$_nee8$raw_nef7 UnLoadArmLoaded _nee6 UnLoadArmLoaded$_nee6$raw_nf05 +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_nee8$raw_nef7 +.mv PieceOutArm$_nee6$raw_nf08 2 Y N +.names PieceOutArm$_nee8$raw_nefa PieceOutArm _nee6 PieceOutArm$_nee6$raw_nf08 +- - 0 =PieceOutArm +- - 1 =PieceOutArm$_nee8$raw_nefa +.mv _nf0c 3 Extend Retract Stop +.names _nf0c +Stop +# RAExtendUnLoadArm == 2 +.names RAExtendUnLoadArm$_nee6$raw_nefe _nf0c _nf0b +.def 0 +- =RAExtendUnLoadArm$_nee6$raw_nefe 1 +.mv _nf0e 2 Y N +.names _nf0e +Y +# RAUnLoadArmExtended == 0 +.names RAUnLoadArmExtended _nf0e _nf0d +.def 0 +- =RAUnLoadArmExtended 1 +# RAExtendUnLoadArm == 2 && RAUnLoadArmExtended == 0 +.names _nf0b _nf0d _nf0f +.def 0 +1 1 1 +.mv _nf11 2 Y N +.names _nf11 +Y +# DBReady == 0 +.names DBReady _nf11 _nf10 +.def 0 +- =DBReady 1 +# RAExtendUnLoadArm == 2 && RAUnLoadArmExtended == 0 && DBReady == 0 +.names _nf0f _nf10 _nf12 +.def 0 +1 1 1 +.names _nf12 _nf13 +- =_nf12 +# RAExtendUnLoadArm = 1 +.mv RAExtendUnLoadArm$_nf12_nf14$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nf12_nf14$true +Retract +# PieceOutArm = 0 +.mv PieceOutArm$_nf12_nf15$true 2 Y N +.names PieceOutArm$_nf12_nf15$true +Y +# UnLoadArmLoaded = 1 +.mv UnLoadArmLoaded$_nf12_nf16$true 2 Y N +.names UnLoadArmLoaded$_nf12_nf16$true +N +# if/else (RAExtendUnLoadArm == 2 && RAUnLoadArmExtended == 0 && DBReady == 0) +.mv RAExtendUnLoadArm$_nf12$raw_nf17 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nf12_nf14$true RAExtendUnLoadArm$_nee6$raw_nefe _nf12 RAExtendUnLoadArm$_nf12$raw_nf17 +- - 0 =RAExtendUnLoadArm$_nee6$raw_nefe +- - 1 =RAExtendUnLoadArm$_nf12_nf14$true +.mv UnLoadArmLoaded$_nf12$raw_nf18 2 Y N +.names UnLoadArmLoaded$_nf12_nf16$true UnLoadArmLoaded$_nee6$raw_nf05 _nf12 UnLoadArmLoaded$_nf12$raw_nf18 +- - 0 =UnLoadArmLoaded$_nee6$raw_nf05 +- - 1 =UnLoadArmLoaded$_nf12_nf16$true +.mv PieceOutArm$_nf12$raw_nf1a 2 Y N +.names PieceOutArm$_nf12_nf15$true PieceOutArm$_nee6$raw_nf08 _nf12 PieceOutArm$_nf12$raw_nf1a +- - 0 =PieceOutArm$_nee6$raw_nf08 +- - 1 =PieceOutArm$_nf12_nf15$true +# if/else (RAArmOverDB == 0) +.mv RAExtendUnLoadArm$_nedc$raw_nf28 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nf12$raw_nf17 RAExtendUnLoadArm$_neb5$raw_neda _nedc RAExtendUnLoadArm$_nedc$raw_nf28 +- - 0 =RAExtendUnLoadArm$_neb5$raw_neda +- - 1 =RAExtendUnLoadArm$_nf12$raw_nf17 +.mv UnLoadArmLoaded$_nedc$raw_nf2f 2 Y N +.names UnLoadArmLoaded$_nf12$raw_nf18 UnLoadArmLoaded _nedc UnLoadArmLoaded$_nedc$raw_nf2f +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_nf12$raw_nf18 +.mv PieceOutArm$_nedc$raw_nf32 2 Y N +.names PieceOutArm$_nf12$raw_nf1a PieceOutArm _nedc PieceOutArm$_nedc$raw_nf32 +- - 0 =PieceOutArm +- - 1 =PieceOutArm$_nf12$raw_nf1a +.mv _nf36 2 Y N +.names _nf36 +Y +# LoadArmLoaded == 0 +.names LoadArmLoaded _nf36 _nf35 +.def 0 +- =LoadArmLoaded 1 +.mv _nf38 2 Y N +.names _nf38 +N +# UnLoadArmLoaded == 1 +.names UnLoadArmLoaded _nf38 _nf37 +.def 0 +- =UnLoadArmLoaded 1 +# LoadArmLoaded == 0 && UnLoadArmLoaded == 1 +.names _nf35 _nf37 _nf39 +.def 0 +1 1 1 +.names _nf39 _nf3a +- =_nf39 +.mv _nf3c 2 Y N +.names _nf3c +Y +# RAArmOverRT == 0 +.names RAArmOverRT _nf3c _nf3b +.def 0 +- =RAArmOverRT 1 +.names _nf3b _nf3d +- =_nf3b +.mv _nf3f 3 CWise Stop CCWise +.names _nf3f +CCWise +# RARotaryMotor == 2 +.names RARotaryMotor _nf3f _nf3e +.def 0 +- =RARotaryMotor 1 +.names _nf3e _nf40 +- =_nf3e +.mv _nf42 2 Y N +.names _nf42 +Y +# PressReadyToBeUnLoaded == 0 +.names PressReadyToBeUnLoaded _nf42 _nf41 +.def 0 +- =PressReadyToBeUnLoaded 1 +.names _nf41 _nf43 +- =_nf41 +# RARotaryMotor = 1 +.mv RARotaryMotor$_nf41_nf44$true 3 CWise Stop CCWise +.names RARotaryMotor$_nf41_nf44$true +Stop +# RAExtendUnLoadArm = 0 +.mv RAExtendUnLoadArm$_nf41_nf45$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nf41_nf45$true +Extend +# if/else (PressReadyToBeUnLoaded == 0) +.mv RAExtendUnLoadArm$_nf41$raw_nf4a 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nf41_nf45$true RAExtendUnLoadArm _nf41 RAExtendUnLoadArm$_nf41$raw_nf4a +- - 0 =RAExtendUnLoadArm +- - 1 =RAExtendUnLoadArm$_nf41_nf45$true +.mv RARotaryMotor$_nf41$raw_nf4b 3 CWise Stop CCWise +.names RARotaryMotor$_nf41_nf44$true RARotaryMotor _nf41 RARotaryMotor$_nf41$raw_nf4b +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_nf41_nf44$true +# if/else (RARotaryMotor == 2) +.mv RAExtendUnLoadArm$_nf3e$raw_nf50 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nf41$raw_nf4a RAExtendUnLoadArm _nf3e RAExtendUnLoadArm$_nf3e$raw_nf50 +- - 0 =RAExtendUnLoadArm +- - 1 =RAExtendUnLoadArm$_nf41$raw_nf4a +.mv RARotaryMotor$_nf3e$raw_nf51 3 CWise Stop CCWise +.names RARotaryMotor$_nf41$raw_nf4b RARotaryMotor _nf3e RARotaryMotor$_nf3e$raw_nf51 +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_nf41$raw_nf4b +.mv _nf53 3 Extend Retract Stop +.names _nf53 +Retract +# RAExtendLoadArm == 1 +.names RAExtendLoadArm _nf53 _nf52 +.def 0 +- =RAExtendLoadArm 1 +.mv _nf55 2 Y N +.names _nf55 +N +# RALoadArmExtended == 1 +.names RALoadArmExtended _nf55 _nf54 +.def 0 +- =RALoadArmExtended 1 +# RAExtendLoadArm == 1 && RALoadArmExtended == 1 +.names _nf52 _nf54 _nf56 +.def 0 +1 1 1 +.mv _nf58 2 Y N +.names _nf58 +N +# RALoadArmRetracted == 1 +.names RALoadArmRetracted _nf58 _nf57 +.def 0 +- =RALoadArmRetracted 1 +# RAExtendLoadArm == 1 && RALoadArmExtended == 1 && RALoadArmRetracted == 1 +.names _nf56 _nf57 _nf59 +.def 0 +1 1 1 +.names _nf59 _nf5a +- =_nf59 +# RAExtendLoadArm = 2 +.mv RAExtendLoadArm$_nf59_nf5b$true 3 Extend Retract Stop +.names RAExtendLoadArm$_nf59_nf5b$true +Stop +# RARotaryMotor = 2 +.mv RARotaryMotor$_nf59_nf5c$true 3 CWise Stop CCWise +.names RARotaryMotor$_nf59_nf5c$true +CCWise +# if/else (RAExtendLoadArm == 1 && RALoadArmExtended == 1 && RALoadArmRetracted == 1) +.mv RARotaryMotor$_nf59$raw_nf5e 3 CWise Stop CCWise +.names RARotaryMotor$_nf59_nf5c$true RARotaryMotor$_nf3e$raw_nf51 _nf59 RARotaryMotor$_nf59$raw_nf5e +- - 0 =RARotaryMotor$_nf3e$raw_nf51 +- - 1 =RARotaryMotor$_nf59_nf5c$true +.mv RAExtendLoadArm$_nf59$raw_nf65 3 Extend Retract Stop +.names RAExtendLoadArm$_nf59_nf5b$true RAExtendLoadArm _nf59 RAExtendLoadArm$_nf59$raw_nf65 +- - 0 =RAExtendLoadArm +- - 1 =RAExtendLoadArm$_nf59_nf5b$true +# if/else (RAArmOverRT == 0) +.mv RAExtendUnLoadArm$_nf3b$raw_nf6e 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nf3e$raw_nf50 RAExtendUnLoadArm _nf3b RAExtendUnLoadArm$_nf3b$raw_nf6e +- - 0 =RAExtendUnLoadArm +- - 1 =RAExtendUnLoadArm$_nf3e$raw_nf50 +.mv RARotaryMotor$_nf3b$raw_nf6f 3 CWise Stop CCWise +.names RARotaryMotor$_nf59$raw_nf5e RARotaryMotor _nf3b RARotaryMotor$_nf3b$raw_nf6f +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_nf59$raw_nf5e +.mv RAExtendLoadArm$_nf3b$raw_nf70 3 Extend Retract Stop +.names RAExtendLoadArm$_nf59$raw_nf65 RAExtendLoadArm _nf3b RAExtendLoadArm$_nf3b$raw_nf70 +- - 0 =RAExtendLoadArm +- - 1 =RAExtendLoadArm$_nf59$raw_nf65 +.mv _nf72 2 Y N +.names _nf72 +Y +# RAArmOverLoadedPress == 0 +.names RAArmOverLoadedPress _nf72 _nf71 +.def 0 +- =RAArmOverLoadedPress 1 +.names _nf71 _nf73 +- =_nf71 +.mv _nf75 3 Extend Retract Stop +.names _nf75 +Stop +# RAExtendLoadArm == 2 +.names RAExtendLoadArm$_nf3b$raw_nf70 _nf75 _nf74 +.def 0 +- =RAExtendLoadArm$_nf3b$raw_nf70 1 +.mv _nf77 3 CWise Stop CCWise +.names _nf77 +Stop +# RARotaryMotor == 1 +.names RARotaryMotor$_nf3b$raw_nf6f _nf77 _nf76 +.def 0 +- =RARotaryMotor$_nf3b$raw_nf6f 1 +# RAExtendLoadArm == 2 && RARotaryMotor == 1 +.names _nf74 _nf76 _nf78 +.def 0 +1 1 1 +.mv _nf7a 3 Extend Retract Stop +.names _nf7a +Stop +# RAExtendUnLoadArm == 2 +.names RAExtendUnLoadArm$_nf3b$raw_nf6e _nf7a _nf79 +.def 0 +- =RAExtendUnLoadArm$_nf3b$raw_nf6e 1 +# RAExtendLoadArm == 2 && RARotaryMotor == 1 && RAExtendUnLoadArm == 2 +.names _nf78 _nf79 _nf7b +.def 0 +1 1 1 +.mv _nf7d 2 Y N +.names _nf7d +Y +# RALoadArmRetracted == 0 +.names RALoadArmRetracted _nf7d _nf7c +.def 0 +- =RALoadArmRetracted 1 +# RAExtendLoadArm == 2 && RARotaryMotor == 1 && RAExtendUnLoadArm == 2 && RALoadArmRetracted == 0 +.names _nf7b _nf7c _nf7e +.def 0 +1 1 1 +.names _nf7e _nf7f +- =_nf7e +.mv _nf81 2 Y N +.names _nf81 +Y +# PressReadyToBeLoaded == 0 +.names PressReadyToBeLoaded _nf81 _nf80 +.def 0 +- =PressReadyToBeLoaded 1 +.names _nf80 _nf82 +- =_nf80 +# RAExtendLoadArm = 0 +.mv RAExtendLoadArm$_nf80_nf83$true 3 Extend Retract Stop +.names RAExtendLoadArm$_nf80_nf83$true +Extend +# if/else (PressReadyToBeLoaded == 0) +.mv RAExtendLoadArm$_nf80$raw_nf86 3 Extend Retract Stop +.names RAExtendLoadArm$_nf80_nf83$true RAExtendLoadArm$_nf3b$raw_nf70 _nf80 RAExtendLoadArm$_nf80$raw_nf86 +- - 0 =RAExtendLoadArm$_nf3b$raw_nf70 +- - 1 =RAExtendLoadArm$_nf80_nf83$true +# if/else (RAExtendLoadArm == 2 && RARotaryMotor == 1 && RAExtendUnLoadArm == 2 && RALoadArmRetracted == 0) +.mv RAExtendLoadArm$_nf7e$raw_nf92 3 Extend Retract Stop +.names RAExtendLoadArm$_nf80$raw_nf86 RAExtendLoadArm$_nf3b$raw_nf70 _nf7e RAExtendLoadArm$_nf7e$raw_nf92 +- - 0 =RAExtendLoadArm$_nf3b$raw_nf70 +- - 1 =RAExtendLoadArm$_nf80$raw_nf86 +.mv _nf9d 3 Extend Retract Stop +.names _nf9d +Extend +# RAExtendLoadArm == 0 +.names RAExtendLoadArm$_nf7e$raw_nf92 _nf9d _nf9c +.def 0 +- =RAExtendLoadArm$_nf7e$raw_nf92 1 +.mv _nf9f 2 Y N +.names _nf9f +N +# RALoadArmExtended == 1 +.names RALoadArmExtended _nf9f _nf9e +.def 0 +- =RALoadArmExtended 1 +# RAExtendLoadArm == 0 && RALoadArmExtended == 1 +.names _nf9c _nf9e _nfa0 +.def 0 +1 1 1 +.mv _nfa2 2 Y N +.names _nfa2 +N +# RALoadArmRetracted == 1 +.names RALoadArmRetracted _nfa2 _nfa1 +.def 0 +- =RALoadArmRetracted 1 +# RAExtendLoadArm == 0 && RALoadArmExtended == 1 && RALoadArmRetracted == 1 +.names _nfa0 _nfa1 _nfa3 +.def 0 +1 1 1 +.names _nfa3 _nfa4 +- =_nfa3 +# RAExtendLoadArm = 1 +.mv RAExtendLoadArm$_nfa3_nfa5$true 3 Extend Retract Stop +.names RAExtendLoadArm$_nfa3_nfa5$true +Retract +# ArmLoadedPress = 0 +.mv ArmLoadedPress$_nfa3_nfa6$true 2 Y N +.names ArmLoadedPress$_nfa3_nfa6$true +Y +# LoadArmLoaded = 1 +.mv LoadArmLoaded$_nfa3_nfa7$true 2 Y N +.names LoadArmLoaded$_nfa3_nfa7$true +N +# if/else (RAExtendLoadArm == 0 && RALoadArmExtended == 1 && RALoadArmRetracted == 1) +.mv RAExtendLoadArm$_nfa3$raw_nfab 3 Extend Retract Stop +.names RAExtendLoadArm$_nfa3_nfa5$true RAExtendLoadArm$_nf7e$raw_nf92 _nfa3 RAExtendLoadArm$_nfa3$raw_nfab +- - 0 =RAExtendLoadArm$_nf7e$raw_nf92 +- - 1 =RAExtendLoadArm$_nfa3_nfa5$true +.mv ArmLoadedPress$_nfa3$raw_nfb2 2 Y N +.names ArmLoadedPress$_nfa3_nfa6$true ArmLoadedPress _nfa3 ArmLoadedPress$_nfa3$raw_nfb2 +- - 0 =ArmLoadedPress +- - 1 =ArmLoadedPress$_nfa3_nfa6$true +.mv LoadArmLoaded$_nfa3$raw_nfb6 2 Y N +.names LoadArmLoaded$_nfa3_nfa7$true LoadArmLoaded _nfa3 LoadArmLoaded$_nfa3$raw_nfb6 +- - 0 =LoadArmLoaded +- - 1 =LoadArmLoaded$_nfa3_nfa7$true +# if/else (RAArmOverLoadedPress == 0) +.mv RAExtendLoadArm$_nf71$raw_nfbd 3 Extend Retract Stop +.names RAExtendLoadArm$_nfa3$raw_nfab RAExtendLoadArm$_nf3b$raw_nf70 _nf71 RAExtendLoadArm$_nf71$raw_nfbd +- - 0 =RAExtendLoadArm$_nf3b$raw_nf70 +- - 1 =RAExtendLoadArm$_nfa3$raw_nfab +.mv ArmLoadedPress$_nf71$raw_nfc4 2 Y N +.names ArmLoadedPress$_nfa3$raw_nfb2 ArmLoadedPress _nf71 ArmLoadedPress$_nf71$raw_nfc4 +- - 0 =ArmLoadedPress +- - 1 =ArmLoadedPress$_nfa3$raw_nfb2 +.mv LoadArmLoaded$_nf71$raw_nfc8 2 Y N +.names LoadArmLoaded$_nfa3$raw_nfb6 LoadArmLoaded _nf71 LoadArmLoaded$_nf71$raw_nfc8 +- - 0 =LoadArmLoaded +- - 1 =LoadArmLoaded$_nfa3$raw_nfb6 +.mv _nfcd 2 Y N +.names _nfcd +Y +# RAArmOverUnLoadedPress == 0 +.names RAArmOverUnLoadedPress _nfcd _nfcc +.def 0 +- =RAArmOverUnLoadedPress 1 +.names _nfcc _nfce +- =_nfcc +.mv _nfd0 3 Extend Retract Stop +.names _nfd0 +Extend +# RAExtendUnLoadArm == 0 +.names RAExtendUnLoadArm$_nf3b$raw_nf6e _nfd0 _nfcf +.def 0 +- =RAExtendUnLoadArm$_nf3b$raw_nf6e 1 +.mv _nfd2 2 Y N +.names _nfd2 +N +# RAUnLoadArmExtended == 1 +.names RAUnLoadArmExtended _nfd2 _nfd1 +.def 0 +- =RAUnLoadArmExtended 1 +# RAExtendUnLoadArm == 0 && RAUnLoadArmExtended == 1 +.names _nfcf _nfd1 _nfd3 +.def 0 +1 1 1 +.mv _nfd5 2 Y N +.names _nfd5 +N +# RAUnLoadArmRetracted == 1 +.names RAUnLoadArmRetracted _nfd5 _nfd4 +.def 0 +- =RAUnLoadArmRetracted 1 +# RAExtendUnLoadArm == 0 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1 +.names _nfd3 _nfd4 _nfd6 +.def 0 +1 1 1 +.names _nfd6 _nfd7 +- =_nfd6 +.mv _nfd9 2 Y N +.names _nfd9 +Y +# PressReadyToBeUnLoaded == 0 +.names PressReadyToBeUnLoaded _nfd9 _nfd8 +.def 0 +- =PressReadyToBeUnLoaded 1 +.names _nfd8 _nfda +- =_nfd8 +# ArmUnLoadedPress = 0 +.mv ArmUnLoadedPress$_nfd8_nfdb$true 2 Y N +.names ArmUnLoadedPress$_nfd8_nfdb$true +Y +# UnLoadArmLoaded = 0 +.mv UnLoadArmLoaded$_nfd8_nfdc$true 2 Y N +.names UnLoadArmLoaded$_nfd8_nfdc$true +Y +# RAExtendUnLoadArm = 1 +.mv RAExtendUnLoadArm$_nfd8_nfdd$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nfd8_nfdd$true +Retract +# if/else (PressReadyToBeUnLoaded == 0) +.mv RAExtendUnLoadArm$_nfd8$raw_nfdf 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nfd8_nfdd$true RAExtendUnLoadArm$_nf3b$raw_nf6e _nfd8 RAExtendUnLoadArm$_nfd8$raw_nfdf +- - 0 =RAExtendUnLoadArm$_nf3b$raw_nf6e +- - 1 =RAExtendUnLoadArm$_nfd8_nfdd$true +.mv UnLoadArmLoaded$_nfd8$raw_nfec 2 Y N +.names UnLoadArmLoaded$_nfd8_nfdc$true UnLoadArmLoaded _nfd8 UnLoadArmLoaded$_nfd8$raw_nfec +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_nfd8_nfdc$true +.mv ArmUnLoadedPress$_nfd8$raw_nfef 2 Y N +.names ArmUnLoadedPress$_nfd8_nfdb$true ArmUnLoadedPress _nfd8 ArmUnLoadedPress$_nfd8$raw_nfef +- - 0 =ArmUnLoadedPress +- - 1 =ArmUnLoadedPress$_nfd8_nfdb$true +# if/else (RAExtendUnLoadArm == 0 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1) +.mv RAExtendUnLoadArm$_nfd6$raw_nffa 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nfd8$raw_nfdf RAExtendUnLoadArm$_nf3b$raw_nf6e _nfd6 RAExtendUnLoadArm$_nfd6$raw_nffa +- - 0 =RAExtendUnLoadArm$_nf3b$raw_nf6e +- - 1 =RAExtendUnLoadArm$_nfd8$raw_nfdf +.mv UnLoadArmLoaded$_nfd6$raw_n1006 2 Y N +.names UnLoadArmLoaded$_nfd8$raw_nfec UnLoadArmLoaded _nfd6 UnLoadArmLoaded$_nfd6$raw_n1006 +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_nfd8$raw_nfec +.mv ArmUnLoadedPress$_nfd6$raw_n1009 2 Y N +.names ArmUnLoadedPress$_nfd8$raw_nfef ArmUnLoadedPress _nfd6 ArmUnLoadedPress$_nfd6$raw_n1009 +- - 0 =ArmUnLoadedPress +- - 1 =ArmUnLoadedPress$_nfd8$raw_nfef +# if/else (RAArmOverUnLoadedPress == 0) +.mv RAExtendUnLoadArm$_nfcc$raw_n1013 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nfd6$raw_nffa RAExtendUnLoadArm$_nf3b$raw_nf6e _nfcc RAExtendUnLoadArm$_nfcc$raw_n1013 +- - 0 =RAExtendUnLoadArm$_nf3b$raw_nf6e +- - 1 =RAExtendUnLoadArm$_nfd6$raw_nffa +.mv UnLoadArmLoaded$_nfcc$raw_n1020 2 Y N +.names UnLoadArmLoaded$_nfd6$raw_n1006 UnLoadArmLoaded _nfcc UnLoadArmLoaded$_nfcc$raw_n1020 +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_nfd6$raw_n1006 +.mv ArmUnLoadedPress$_nfcc$raw_n1023 2 Y N +.names ArmUnLoadedPress$_nfd6$raw_n1009 ArmUnLoadedPress _nfcc ArmUnLoadedPress$_nfcc$raw_n1023 +- - 0 =ArmUnLoadedPress +- - 1 =ArmUnLoadedPress$_nfd6$raw_n1009 +.mv _n102d 2 Y N +.names _n102d +Y +# RAArmOverDB == 0 +.names RAArmOverDB _n102d _n102c +.def 0 +- =RAArmOverDB 1 +.names _n102c _n102e +- =_n102c +.mv _n1030 3 CWise Stop CCWise +.names _n1030 +CCWise +# RARotaryMotor == 2 +.names RARotaryMotor$_nf3b$raw_nf6f _n1030 _n102f +.def 0 +- =RARotaryMotor$_nf3b$raw_nf6f 1 +.names _n102f _n1031 +- =_n102f +# RARotaryMotor = 1 +.mv RARotaryMotor$_n102f_n1032$true 3 CWise Stop CCWise +.names RARotaryMotor$_n102f_n1032$true +Stop +.mv _n1034 2 Y N +.names _n1034 +Y +# PressReadyToBeLoaded == 0 +.names PressReadyToBeLoaded _n1034 _n1033 +.def 0 +- =PressReadyToBeLoaded 1 +.names _n1033 _n1035 +- =_n1033 +# RAExtendLoadArm = 0 +.mv RAExtendLoadArm$_n1033_n1036$true 3 Extend Retract Stop +.names RAExtendLoadArm$_n1033_n1036$true +Extend +# if/else (PressReadyToBeLoaded == 0) +.mv RAExtendLoadArm$_n1033$raw_n103c 3 Extend Retract Stop +.names RAExtendLoadArm$_n1033_n1036$true RAExtendLoadArm$_nf71$raw_nfbd _n1033 RAExtendLoadArm$_n1033$raw_n103c +- - 0 =RAExtendLoadArm$_nf71$raw_nfbd +- - 1 =RAExtendLoadArm$_n1033_n1036$true +# if/else (RARotaryMotor == 2) +.mv RARotaryMotor$_n102f$raw_n1057 3 CWise Stop CCWise +.names RARotaryMotor$_n102f_n1032$true RARotaryMotor$_nf3b$raw_nf6f _n102f RARotaryMotor$_n102f$raw_n1057 +- - 0 =RARotaryMotor$_nf3b$raw_nf6f +- - 1 =RARotaryMotor$_n102f_n1032$true +.mv RAExtendLoadArm$_n102f$raw_n1058 3 Extend Retract Stop +.names RAExtendLoadArm$_n1033$raw_n103c RAExtendLoadArm$_nf71$raw_nfbd _n102f RAExtendLoadArm$_n102f$raw_n1058 +- - 0 =RAExtendLoadArm$_nf71$raw_nfbd +- - 1 =RAExtendLoadArm$_n1033$raw_n103c +.mv _n1070 3 Extend Retract Stop +.names _n1070 +Retract +# RAExtendUnLoadArm == 1 +.names RAExtendUnLoadArm$_nfcc$raw_n1013 _n1070 _n106f +.def 0 +- =RAExtendUnLoadArm$_nfcc$raw_n1013 1 +.mv _n1072 2 Y N +.names _n1072 +N +# RAUnLoadArmExtended == 1 +.names RAUnLoadArmExtended _n1072 _n1071 +.def 0 +- =RAUnLoadArmExtended 1 +# RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 +.names _n106f _n1071 _n1073 +.def 0 +1 1 1 +.mv _n1075 2 Y N +.names _n1075 +N +# RAUnLoadArmRetracted == 1 +.names RAUnLoadArmRetracted _n1075 _n1074 +.def 0 +- =RAUnLoadArmRetracted 1 +# RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1 +.names _n1073 _n1074 _n1076 +.def 0 +1 1 1 +.names _n1076 _n1077 +- =_n1076 +# RAExtendUnLoadArm = 2 +.mv RAExtendUnLoadArm$_n1076_n1078$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n1076_n1078$true +Stop +# RARotaryMotor = 2 +.mv RARotaryMotor$_n1076_n1079$true 3 CWise Stop CCWise +.names RARotaryMotor$_n1076_n1079$true +CCWise +# if/else (RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1) +.mv RAExtendUnLoadArm$_n1076$raw_n107c 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n1076_n1078$true RAExtendUnLoadArm$_nfcc$raw_n1013 _n1076 RAExtendUnLoadArm$_n1076$raw_n107c +- - 0 =RAExtendUnLoadArm$_nfcc$raw_n1013 +- - 1 =RAExtendUnLoadArm$_n1076_n1078$true +.mv RARotaryMotor$_n1076$raw_n107e 3 CWise Stop CCWise +.names RARotaryMotor$_n1076_n1079$true RARotaryMotor$_n102f$raw_n1057 _n1076 RARotaryMotor$_n1076$raw_n107e +- - 0 =RARotaryMotor$_n102f$raw_n1057 +- - 1 =RARotaryMotor$_n1076_n1079$true +# if/else (RAArmOverDB == 0) +.mv RAExtendUnLoadArm$_n102c$raw_n1096 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n1076$raw_n107c RAExtendUnLoadArm$_nfcc$raw_n1013 _n102c RAExtendUnLoadArm$_n102c$raw_n1096 +- - 0 =RAExtendUnLoadArm$_nfcc$raw_n1013 +- - 1 =RAExtendUnLoadArm$_n1076$raw_n107c +.mv RARotaryMotor$_n102c$raw_n1099 3 CWise Stop CCWise +.names RARotaryMotor$_n1076$raw_n107e RARotaryMotor$_nf3b$raw_nf6f _n102c RARotaryMotor$_n102c$raw_n1099 +- - 0 =RARotaryMotor$_nf3b$raw_nf6f +- - 1 =RARotaryMotor$_n1076$raw_n107e +.mv RAExtendLoadArm$_n102c$raw_n109b 3 Extend Retract Stop +.names RAExtendLoadArm$_n102f$raw_n1058 RAExtendLoadArm$_nf71$raw_nfbd _n102c RAExtendLoadArm$_n102c$raw_n109b +- - 0 =RAExtendLoadArm$_nf71$raw_nfbd +- - 1 =RAExtendLoadArm$_n102f$raw_n1058 +.mv _n10b3 2 Y N +.names _n10b3 +Y +# LoadArmLoaded == 0 +.names LoadArmLoaded _n10b3 _n10b2 +.def 0 +- =LoadArmLoaded 1 +.mv _n10b5 2 Y N +.names _n10b5 +Y +# UnLoadArmLoaded == 0 +.names UnLoadArmLoaded _n10b5 _n10b4 +.def 0 +- =UnLoadArmLoaded 1 +# LoadArmLoaded == 0 && UnLoadArmLoaded == 0 +.names _n10b2 _n10b4 _n10b6 +.def 0 +1 1 1 +.names _n10b6 _n10b7 +- =_n10b6 +.mv _n10b9 2 Y N +.names _n10b9 +Y +# RAArmOverUnLoadedPress == 0 +.names RAArmOverUnLoadedPress _n10b9 _n10b8 +.def 0 +- =RAArmOverUnLoadedPress 1 +.names _n10b8 _n10ba +- =_n10b8 +.mv _n10bc 3 CWise Stop CCWise +.names _n10bc +CCWise +# RARotaryMotor == 2 +.names RARotaryMotor _n10bc _n10bb +.def 0 +- =RARotaryMotor 1 +.names _n10bb _n10bd +- =_n10bb +# RARotaryMotor = 1 +.mv RARotaryMotor$_n10bb_n10be$true 3 CWise Stop CCWise +.names RARotaryMotor$_n10bb_n10be$true +Stop +# RAExtendUnLoadArm = 0 +.mv RAExtendUnLoadArm$_n10bb_n10bf$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n10bb_n10bf$true +Extend +# if/else (RARotaryMotor == 2) +.mv RAExtendUnLoadArm$_n10bb$raw_n10c4 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n10bb_n10bf$true RAExtendUnLoadArm _n10bb RAExtendUnLoadArm$_n10bb$raw_n10c4 +- - 0 =RAExtendUnLoadArm +- - 1 =RAExtendUnLoadArm$_n10bb_n10bf$true +.mv RARotaryMotor$_n10bb$raw_n10c5 3 CWise Stop CCWise +.names RARotaryMotor$_n10bb_n10be$true RARotaryMotor _n10bb RARotaryMotor$_n10bb$raw_n10c5 +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_n10bb_n10be$true +.mv _n10c7 3 Extend Retract Stop +.names _n10c7 +Retract +# RAExtendUnLoadArm == 1 +.names RAExtendUnLoadArm$_n10bb$raw_n10c4 _n10c7 _n10c6 +.def 0 +- =RAExtendUnLoadArm$_n10bb$raw_n10c4 1 +.mv _n10c9 2 Y N +.names _n10c9 +N +# RAUnLoadArmExtended == 1 +.names RAUnLoadArmExtended _n10c9 _n10c8 +.def 0 +- =RAUnLoadArmExtended 1 +# RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 +.names _n10c6 _n10c8 _n10ca +.def 0 +1 1 1 +.mv _n10cc 2 Y N +.names _n10cc +N +# RAUnLoadArmRetracted == 1 +.names RAUnLoadArmRetracted _n10cc _n10cb +.def 0 +- =RAUnLoadArmRetracted 1 +# RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1 +.names _n10ca _n10cb _n10cd +.def 0 +1 1 1 +.names _n10cd _n10ce +- =_n10cd +# RAExtendUnLoadArm = 2 +.mv RAExtendUnLoadArm$_n10cd_n10cf$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n10cd_n10cf$true +Stop +# RARotaryMotor = 2 +.mv RARotaryMotor$_n10cd_n10d0$true 3 CWise Stop CCWise +.names RARotaryMotor$_n10cd_n10d0$true +CCWise +# if/else (RAExtendUnLoadArm == 1 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1) +.mv RAExtendUnLoadArm$_n10cd$raw_n10d1 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n10cd_n10cf$true RAExtendUnLoadArm$_n10bb$raw_n10c4 _n10cd RAExtendUnLoadArm$_n10cd$raw_n10d1 +- - 0 =RAExtendUnLoadArm$_n10bb$raw_n10c4 +- - 1 =RAExtendUnLoadArm$_n10cd_n10cf$true +.mv RARotaryMotor$_n10cd$raw_n10d2 3 CWise Stop CCWise +.names RARotaryMotor$_n10cd_n10d0$true RARotaryMotor$_n10bb$raw_n10c5 _n10cd RARotaryMotor$_n10cd$raw_n10d2 +- - 0 =RARotaryMotor$_n10bb$raw_n10c5 +- - 1 =RARotaryMotor$_n10cd_n10d0$true +# if/else (RAArmOverUnLoadedPress == 0) +.mv RAExtendUnLoadArm$_n10b8$raw_n10dd 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n10cd$raw_n10d1 RAExtendUnLoadArm _n10b8 RAExtendUnLoadArm$_n10b8$raw_n10dd +- - 0 =RAExtendUnLoadArm +- - 1 =RAExtendUnLoadArm$_n10cd$raw_n10d1 +.mv RARotaryMotor$_n10b8$raw_n10de 3 CWise Stop CCWise +.names RARotaryMotor$_n10cd$raw_n10d2 RARotaryMotor _n10b8 RARotaryMotor$_n10b8$raw_n10de +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_n10cd$raw_n10d2 +.mv _n10e0 2 Y N +.names _n10e0 +Y +# RAArmOverDB == 0 +.names RAArmOverDB _n10e0 _n10df +.def 0 +- =RAArmOverDB 1 +.names _n10df _n10e1 +- =_n10df +.mv _n10e3 3 Extend Retract Stop +.names _n10e3 +Extend +# RAExtendUnLoadArm == 0 +.names RAExtendUnLoadArm$_n10b8$raw_n10dd _n10e3 _n10e2 +.def 0 +- =RAExtendUnLoadArm$_n10b8$raw_n10dd 1 +.mv _n10e5 2 Y N +.names _n10e5 +N +# RAUnLoadArmExtended == 1 +.names RAUnLoadArmExtended _n10e5 _n10e4 +.def 0 +- =RAUnLoadArmExtended 1 +# RAExtendUnLoadArm == 0 && RAUnLoadArmExtended == 1 +.names _n10e2 _n10e4 _n10e6 +.def 0 +1 1 1 +.mv _n10e8 2 Y N +.names _n10e8 +N +# RAUnLoadArmRetracted == 1 +.names RAUnLoadArmRetracted _n10e8 _n10e7 +.def 0 +- =RAUnLoadArmRetracted 1 +# RAExtendUnLoadArm == 0 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1 +.names _n10e6 _n10e7 _n10e9 +.def 0 +1 1 1 +.names _n10e9 _n10ea +- =_n10e9 +# RAExtendUnLoadArm = 2 +.mv RAExtendUnLoadArm$_n10e9_n10eb$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n10e9_n10eb$true +Stop +.mv _n10ed 2 Y N +.names _n10ed +Y +# DBReady == 0 +.names DBReady _n10ed _n10ec +.def 0 +- =DBReady 1 +.names _n10ec _n10ee +- =_n10ec +# RAExtendUnLoadArm = 1 +.mv RAExtendUnLoadArm$_n10ec_n10ef$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n10ec_n10ef$true +Retract +# UnLoadArmLoaded = 1 +.mv UnLoadArmLoaded$_n10ec_n10f0$true 2 Y N +.names UnLoadArmLoaded$_n10ec_n10f0$true +N +# PieceOutArm = 0 +.mv PieceOutArm$_n10ec_n10f1$true 2 Y N +.names PieceOutArm$_n10ec_n10f1$true +Y +# if/else (DBReady == 0) +.mv RAExtendUnLoadArm$_n10ec$raw_n10f3 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n10ec_n10ef$true RAExtendUnLoadArm$_n10e9_n10eb$true _n10ec RAExtendUnLoadArm$_n10ec$raw_n10f3 +- - 0 =RAExtendUnLoadArm$_n10e9_n10eb$true +- - 1 =RAExtendUnLoadArm$_n10ec_n10ef$true +.mv UnLoadArmLoaded$_n10ec$raw_n10fa 2 Y N +.names UnLoadArmLoaded$_n10ec_n10f0$true UnLoadArmLoaded _n10ec UnLoadArmLoaded$_n10ec$raw_n10fa +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_n10ec_n10f0$true +.mv PieceOutArm$_n10ec$raw_n10fd 2 Y N +.names PieceOutArm$_n10ec_n10f1$true PieceOutArm _n10ec PieceOutArm$_n10ec$raw_n10fd +- - 0 =PieceOutArm +- - 1 =PieceOutArm$_n10ec_n10f1$true +# if/else (RAExtendUnLoadArm == 0 && RAUnLoadArmExtended == 1 && RAUnLoadArmRetracted == 1) +.mv RAExtendUnLoadArm$_n10e9$raw_n1101 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n10ec$raw_n10f3 RAExtendUnLoadArm$_n10b8$raw_n10dd _n10e9 RAExtendUnLoadArm$_n10e9$raw_n1101 +- - 0 =RAExtendUnLoadArm$_n10b8$raw_n10dd +- - 1 =RAExtendUnLoadArm$_n10ec$raw_n10f3 +.mv UnLoadArmLoaded$_n10e9$raw_n1108 2 Y N +.names UnLoadArmLoaded$_n10ec$raw_n10fa UnLoadArmLoaded _n10e9 UnLoadArmLoaded$_n10e9$raw_n1108 +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_n10ec$raw_n10fa +.mv PieceOutArm$_n10e9$raw_n110b 2 Y N +.names PieceOutArm$_n10ec$raw_n10fd PieceOutArm _n10e9 PieceOutArm$_n10e9$raw_n110b +- - 0 =PieceOutArm +- - 1 =PieceOutArm$_n10ec$raw_n10fd +.mv _n110f 3 Extend Retract Stop +.names _n110f +Stop +# RAExtendUnLoadArm == 2 +.names RAExtendUnLoadArm$_n10e9$raw_n1101 _n110f _n110e +.def 0 +- =RAExtendUnLoadArm$_n10e9$raw_n1101 1 +.mv _n1111 2 Y N +.names _n1111 +Y +# RAUnLoadArmExtended == 0 +.names RAUnLoadArmExtended _n1111 _n1110 +.def 0 +- =RAUnLoadArmExtended 1 +# RAExtendUnLoadArm == 2 && RAUnLoadArmExtended == 0 +.names _n110e _n1110 _n1112 +.def 0 +1 1 1 +.names _n1112 _n1113 +- =_n1112 +.mv _n1115 2 Y N +.names _n1115 +Y +# DBReady == 0 +.names DBReady _n1115 _n1114 +.def 0 +- =DBReady 1 +.names _n1114 _n1116 +- =_n1114 +# RAExtendUnLoadArm = 1 +.mv RAExtendUnLoadArm$_n1114_n1117$true 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n1114_n1117$true +Retract +# UnLoadArmLoaded = 1 +.mv UnLoadArmLoaded$_n1114_n1118$true 2 Y N +.names UnLoadArmLoaded$_n1114_n1118$true +N +# PieceOutArm = 0 +.mv PieceOutArm$_n1114_n1119$true 2 Y N +.names PieceOutArm$_n1114_n1119$true +Y +# if/else (DBReady == 0) +.mv UnLoadArmLoaded$_n1114$raw_n111a 2 Y N +.names UnLoadArmLoaded$_n1114_n1118$true UnLoadArmLoaded$_n10e9$raw_n1108 _n1114 UnLoadArmLoaded$_n1114$raw_n111a +- - 0 =UnLoadArmLoaded$_n10e9$raw_n1108 +- - 1 =UnLoadArmLoaded$_n1114_n1118$true +.mv RAExtendUnLoadArm$_n1114$raw_n111b 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n1114_n1117$true RAExtendUnLoadArm$_n10e9$raw_n1101 _n1114 RAExtendUnLoadArm$_n1114$raw_n111b +- - 0 =RAExtendUnLoadArm$_n10e9$raw_n1101 +- - 1 =RAExtendUnLoadArm$_n1114_n1117$true +.mv PieceOutArm$_n1114$raw_n111d 2 Y N +.names PieceOutArm$_n1114_n1119$true PieceOutArm$_n10e9$raw_n110b _n1114 PieceOutArm$_n1114$raw_n111d +- - 0 =PieceOutArm$_n10e9$raw_n110b +- - 1 =PieceOutArm$_n1114_n1119$true +# if/else (RAExtendUnLoadArm == 2 && RAUnLoadArmExtended == 0) +.mv RAExtendUnLoadArm$_n1112$raw_n112a 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n1114$raw_n111b RAExtendUnLoadArm$_n10e9$raw_n1101 _n1112 RAExtendUnLoadArm$_n1112$raw_n112a +- - 0 =RAExtendUnLoadArm$_n10e9$raw_n1101 +- - 1 =RAExtendUnLoadArm$_n1114$raw_n111b +.mv UnLoadArmLoaded$_n1112$raw_n112b 2 Y N +.names UnLoadArmLoaded$_n1114$raw_n111a UnLoadArmLoaded$_n10e9$raw_n1108 _n1112 UnLoadArmLoaded$_n1112$raw_n112b +- - 0 =UnLoadArmLoaded$_n10e9$raw_n1108 +- - 1 =UnLoadArmLoaded$_n1114$raw_n111a +.mv PieceOutArm$_n1112$raw_n112d 2 Y N +.names PieceOutArm$_n1114$raw_n111d PieceOutArm$_n10e9$raw_n110b _n1112 PieceOutArm$_n1112$raw_n112d +- - 0 =PieceOutArm$_n10e9$raw_n110b +- - 1 =PieceOutArm$_n1114$raw_n111d +# if/else (RAArmOverDB == 0) +.mv RAExtendUnLoadArm$_n10df$raw_n113b 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n1112$raw_n112a RAExtendUnLoadArm$_n10b8$raw_n10dd _n10df RAExtendUnLoadArm$_n10df$raw_n113b +- - 0 =RAExtendUnLoadArm$_n10b8$raw_n10dd +- - 1 =RAExtendUnLoadArm$_n1112$raw_n112a +.mv UnLoadArmLoaded$_n10df$raw_n1142 2 Y N +.names UnLoadArmLoaded$_n1112$raw_n112b UnLoadArmLoaded _n10df UnLoadArmLoaded$_n10df$raw_n1142 +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_n1112$raw_n112b +.mv PieceOutArm$_n10df$raw_n1145 2 Y N +.names PieceOutArm$_n1112$raw_n112d PieceOutArm _n10df PieceOutArm$_n10df$raw_n1145 +- - 0 =PieceOutArm +- - 1 =PieceOutArm$_n1112$raw_n112d +# if/else (LoadArmLoaded == 0 && UnLoadArmLoaded == 0) +.mv UnLoadArmLoaded$_n10b6$raw_n1150 2 Y N +.names UnLoadArmLoaded$_n10df$raw_n1142 UnLoadArmLoaded _n10b6 UnLoadArmLoaded$_n10b6$raw_n1150 +- - 0 =UnLoadArmLoaded +- - 1 =UnLoadArmLoaded$_n10df$raw_n1142 +.mv RAExtendUnLoadArm$_n10b6$raw_n1151 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n10df$raw_n113b RAExtendUnLoadArm _n10b6 RAExtendUnLoadArm$_n10b6$raw_n1151 +- - 0 =RAExtendUnLoadArm +- - 1 =RAExtendUnLoadArm$_n10df$raw_n113b +.mv RARotaryMotor$_n10b6$raw_n1152 3 CWise Stop CCWise +.names RARotaryMotor$_n10b8$raw_n10de RARotaryMotor _n10b6 RARotaryMotor$_n10b6$raw_n1152 +- - 0 =RARotaryMotor +- - 1 =RARotaryMotor$_n10b8$raw_n10de +.mv PieceOutArm$_n10b6$raw_n1153 2 Y N +.names PieceOutArm$_n10df$raw_n1145 PieceOutArm _n10b6 PieceOutArm$_n10b6$raw_n1153 +- - 0 =PieceOutArm +- - 1 =PieceOutArm$_n10df$raw_n1145 +# if/else (LoadArmLoaded == 0 && UnLoadArmLoaded == 1) +.mv UnLoadArmLoaded$_nf39$raw_n115b 2 Y N +.names UnLoadArmLoaded$_nfcc$raw_n1020 UnLoadArmLoaded$_n10b6$raw_n1150 _nf39 UnLoadArmLoaded$_nf39$raw_n115b +- - 0 =UnLoadArmLoaded$_n10b6$raw_n1150 +- - 1 =UnLoadArmLoaded$_nfcc$raw_n1020 +.mv RAExtendUnLoadArm$_nf39$raw_n115d 3 Extend Retract Stop +.names RAExtendUnLoadArm$_n102c$raw_n1096 RAExtendUnLoadArm$_n10b6$raw_n1151 _nf39 RAExtendUnLoadArm$_nf39$raw_n115d +- - 0 =RAExtendUnLoadArm$_n10b6$raw_n1151 +- - 1 =RAExtendUnLoadArm$_n102c$raw_n1096 +.mv RARotaryMotor$_nf39$raw_n115f 3 CWise Stop CCWise +.names RARotaryMotor$_n102c$raw_n1099 RARotaryMotor$_n10b6$raw_n1152 _nf39 RARotaryMotor$_nf39$raw_n115f +- - 0 =RARotaryMotor$_n10b6$raw_n1152 +- - 1 =RARotaryMotor$_n102c$raw_n1099 +.mv ArmLoadedPress$_nf39$raw_n1163 2 Y N +.names ArmLoadedPress$_nf71$raw_nfc4 ArmLoadedPress _nf39 ArmLoadedPress$_nf39$raw_n1163 +- - 0 =ArmLoadedPress +- - 1 =ArmLoadedPress$_nf71$raw_nfc4 +.mv ArmUnLoadedPress$_nf39$raw_n1165 2 Y N +.names ArmUnLoadedPress$_nfcc$raw_n1023 ArmUnLoadedPress _nf39 ArmUnLoadedPress$_nf39$raw_n1165 +- - 0 =ArmUnLoadedPress +- - 1 =ArmUnLoadedPress$_nfcc$raw_n1023 +.mv RAExtendLoadArm$_nf39$raw_n1167 3 Extend Retract Stop +.names RAExtendLoadArm$_n102c$raw_n109b RAExtendLoadArm _nf39 RAExtendLoadArm$_nf39$raw_n1167 +- - 0 =RAExtendLoadArm +- - 1 =RAExtendLoadArm$_n102c$raw_n109b +.mv LoadArmLoaded$_nf39$raw_n1168 2 Y N +.names LoadArmLoaded$_nf71$raw_nfc8 LoadArmLoaded _nf39 LoadArmLoaded$_nf39$raw_n1168 +- - 0 =LoadArmLoaded +- - 1 =LoadArmLoaded$_nf71$raw_nfc8 +.mv PieceOutArm$_nf39$raw_n116c 2 Y N +.names PieceOutArm PieceOutArm$_n10b6$raw_n1153 _nf39 PieceOutArm$_nf39$raw_n116c +- - 0 =PieceOutArm$_n10b6$raw_n1153 +- - 1 =PieceOutArm +# if/else (LoadArmLoaded == 1 && UnLoadArmLoaded == 0) +.mv UnLoadArmLoaded$_neb3$raw_n1171 2 Y N +.names UnLoadArmLoaded$_nedc$raw_nf2f UnLoadArmLoaded$_nf39$raw_n115b _neb3 UnLoadArmLoaded$_neb3$raw_n1171 +- - 0 =UnLoadArmLoaded$_nf39$raw_n115b +- - 1 =UnLoadArmLoaded$_nedc$raw_nf2f +.mv RAExtendUnLoadArm$_neb3$raw_n1172 3 Extend Retract Stop +.names RAExtendUnLoadArm$_nedc$raw_nf28 RAExtendUnLoadArm$_nf39$raw_n115d _neb3 RAExtendUnLoadArm$_neb3$raw_n1172 +- - 0 =RAExtendUnLoadArm$_nf39$raw_n115d +- - 1 =RAExtendUnLoadArm$_nedc$raw_nf28 +.mv RARotaryMotor$_neb3$raw_n1173 3 CWise Stop CCWise +.names RARotaryMotor$_neb5$raw_nedb RARotaryMotor$_nf39$raw_n115f _neb3 RARotaryMotor$_neb3$raw_n1173 +- - 0 =RARotaryMotor$_nf39$raw_n115f +- - 1 =RARotaryMotor$_neb5$raw_nedb +.mv PieceOutArm$_neb3$raw_n1174 2 Y N +.names PieceOutArm$_nedc$raw_nf32 PieceOutArm$_nf39$raw_n116c _neb3 PieceOutArm$_neb3$raw_n1174 +- - 0 =PieceOutArm$_nf39$raw_n116c +- - 1 =PieceOutArm$_nedc$raw_nf32 +.mv ArmLoadedPress$_neb3$raw_n1179 2 Y N +.names ArmLoadedPress ArmLoadedPress$_nf39$raw_n1163 _neb3 ArmLoadedPress$_neb3$raw_n1179 +- - 0 =ArmLoadedPress$_nf39$raw_n1163 +- - 1 =ArmLoadedPress +.mv ArmUnLoadedPress$_neb3$raw_n117c 2 Y N +.names ArmUnLoadedPress ArmUnLoadedPress$_nf39$raw_n1165 _neb3 ArmUnLoadedPress$_neb3$raw_n117c +- - 0 =ArmUnLoadedPress$_nf39$raw_n1165 +- - 1 =ArmUnLoadedPress +.mv RAExtendLoadArm$_neb3$raw_n117e 3 Extend Retract Stop +.names RAExtendLoadArm RAExtendLoadArm$_nf39$raw_n1167 _neb3 RAExtendLoadArm$_neb3$raw_n117e +- - 0 =RAExtendLoadArm$_nf39$raw_n1167 +- - 1 =RAExtendLoadArm +.mv LoadArmLoaded$_neb3$raw_n1180 2 Y N +.names LoadArmLoaded LoadArmLoaded$_nf39$raw_n1168 _neb3 LoadArmLoaded$_neb3$raw_n1180 +- - 0 =LoadArmLoaded$_nf39$raw_n1168 +- - 1 =LoadArmLoaded +# if/else (LoadArmLoaded == 1 && UnLoadArmLoaded == 1) +.mv UnLoadArmLoaded$_nc51$raw_n1188 2 Y N +.names UnLoadArmLoaded$_nd32$raw_ndee UnLoadArmLoaded$_neb3$raw_n1171 _nc51 UnLoadArmLoaded$_nc51$raw_n1188 +- - 0 =UnLoadArmLoaded$_neb3$raw_n1171 +- - 1 =UnLoadArmLoaded$_nd32$raw_ndee +.mv RAExtendUnLoadArm$_nc51$raw_n1189 3 Extend Retract Stop +.names RAExtendUnLoadArm$_ndfa$raw_ne93 RAExtendUnLoadArm$_neb3$raw_n1172 _nc51 RAExtendUnLoadArm$_nc51$raw_n1189 +- - 0 =RAExtendUnLoadArm$_neb3$raw_n1172 +- - 1 =RAExtendUnLoadArm$_ndfa$raw_ne93 +.mv ArmUnLoadedPress$_nc51$raw_n118a 2 Y N +.names ArmUnLoadedPress$_nd32$raw_ndf0 ArmUnLoadedPress$_neb3$raw_n117c _nc51 ArmUnLoadedPress$_nc51$raw_n118a +- - 0 =ArmUnLoadedPress$_neb3$raw_n117c +- - 1 =ArmUnLoadedPress$_nd32$raw_ndf0 +.mv RARotaryMotor$_nc51$raw_n118b 3 CWise Stop CCWise +.names RARotaryMotor$_ndfa$raw_ne95 RARotaryMotor$_neb3$raw_n1173 _nc51 RARotaryMotor$_nc51$raw_n118b +- - 0 =RARotaryMotor$_neb3$raw_n1173 +- - 1 =RARotaryMotor$_ndfa$raw_ne95 +.mv RAExtendLoadArm$_nc51$raw_n118c 3 Extend Retract Stop +.names RAExtendLoadArm$_nd32$raw_nde4 RAExtendLoadArm$_neb3$raw_n117e _nc51 RAExtendLoadArm$_nc51$raw_n118c +- - 0 =RAExtendLoadArm$_neb3$raw_n117e +- - 1 =RAExtendLoadArm$_nd32$raw_nde4 +.mv LoadArmLoaded$_nc51$raw_n118e 2 Y N +.names LoadArmLoaded$_nc53$raw_ncce LoadArmLoaded$_neb3$raw_n1180 _nc51 LoadArmLoaded$_nc51$raw_n118e +- - 0 =LoadArmLoaded$_neb3$raw_n1180 +- - 1 =LoadArmLoaded$_nc53$raw_ncce +.mv PieceGrabbedFromRT$_nc51$raw_n1194 2 Y N +.names PieceGrabbedFromRT$_nc53$raw_nccd PieceGrabbedFromRT _nc51 PieceGrabbedFromRT$_nc51$raw_n1194 +- - 0 =PieceGrabbedFromRT +- - 1 =PieceGrabbedFromRT$_nc53$raw_nccd +.mv ArmLoadedPress$_nc51$raw_n1196 2 Y N +.names ArmLoadedPress ArmLoadedPress$_neb3$raw_n1179 _nc51 ArmLoadedPress$_nc51$raw_n1196 +- - 0 =ArmLoadedPress$_neb3$raw_n1179 +- - 1 =ArmLoadedPress +.mv PieceOutArm$_nc51$raw_n119c 2 Y N +.names PieceOutArm PieceOutArm$_neb3$raw_n1174 _nc51 PieceOutArm$_nc51$raw_n119c +- - 0 =PieceOutArm$_neb3$raw_n1174 +- - 1 =PieceOutArm +.mv _n119f 2 Y N +.names _n119f +N +# DBReady == 1 +.names DBReady _n119f _n119e +.def 0 +- =DBReady 1 +.mv _n11a1 2 Y N +.names _n11a1 +Y +# PieceOutArm == 0 +.names PieceOutArm$_nc51$raw_n119c _n11a1 _n11a0 +.def 0 +- =PieceOutArm$_nc51$raw_n119c 1 +# DBReady == 1 && PieceOutArm == 0 +.names _n119e _n11a0 _n11a2 +.def 0 +1 1 1 +.names _n11a2 _n11a3 +- =_n11a2 +# PieceOutArm = 1 +.mv PieceOutArm$_n11a2_n11a4$true 2 Y N +.names PieceOutArm$_n11a2_n11a4$true +N +# if/else (DBReady == 1 && PieceOutArm == 0) +.mv PieceOutArm$_n11a2$raw_n11ac 2 Y N +.names PieceOutArm$_n11a2_n11a4$true PieceOutArm$_nc51$raw_n119c _n11a2 PieceOutArm$_n11a2$raw_n11ac +- - 0 =PieceOutArm$_nc51$raw_n119c +- - 1 =PieceOutArm$_n11a2_n11a4$true +.mv _n11ca 2 Y N +.names _n11ca +N +# PressReadyToBeUnLoaded == 1 +.names PressReadyToBeUnLoaded _n11ca _n11c9 +.def 0 +- =PressReadyToBeUnLoaded 1 +.mv _n11cc 2 Y N +.names _n11cc +Y +# ArmUnLoadedPress == 0 +.names ArmUnLoadedPress$_nc51$raw_n118a _n11cc _n11cb +.def 0 +- =ArmUnLoadedPress$_nc51$raw_n118a 1 +# PressReadyToBeUnLoaded == 1 && ArmUnLoadedPress == 0 +.names _n11c9 _n11cb _n11cd +.def 0 +1 1 1 +.names _n11cd _n11ce +- =_n11cd +# ArmUnLoadedPress = 1 +.mv ArmUnLoadedPress$_n11cd_n11cf$true 2 Y N +.names ArmUnLoadedPress$_n11cd_n11cf$true +N +# if/else (PressReadyToBeUnLoaded == 1 && ArmUnLoadedPress == 0) +.mv ArmUnLoadedPress$_n11cd$raw_n11d3 2 Y N +.names ArmUnLoadedPress$_n11cd_n11cf$true ArmUnLoadedPress$_nc51$raw_n118a _n11cd ArmUnLoadedPress$_n11cd$raw_n11d3 +- - 0 =ArmUnLoadedPress$_nc51$raw_n118a +- - 1 =ArmUnLoadedPress$_n11cd_n11cf$true +.mv _n11f5 2 Y N +.names _n11f5 +Y +# ArmLoadedPress == 0 +.names ArmLoadedPress$_nc51$raw_n1196 _n11f5 _n11f4 +.def 0 +- =ArmLoadedPress$_nc51$raw_n1196 1 +.mv _n11f7 2 Y N +.names _n11f7 +N +# PressReadyToBeLoaded == 1 +.names PressReadyToBeLoaded _n11f7 _n11f6 +.def 0 +- =PressReadyToBeLoaded 1 +# ArmLoadedPress == 0 && PressReadyToBeLoaded == 1 +.names _n11f4 _n11f6 _n11f8 +.def 0 +1 1 1 +.names _n11f8 _n11f9 +- =_n11f8 +# ArmLoadedPress = 1 +.mv ArmLoadedPress$_n11f8_n11fa$true 2 Y N +.names ArmLoadedPress$_n11f8_n11fa$true +N +# if/else (ArmLoadedPress == 0 && PressReadyToBeLoaded == 1) +.mv ArmLoadedPress$_n11f8$raw_n11fd 2 Y N +.names ArmLoadedPress$_n11f8_n11fa$true ArmLoadedPress$_nc51$raw_n1196 _n11f8 ArmLoadedPress$_n11f8$raw_n11fd +- - 0 =ArmLoadedPress$_nc51$raw_n1196 +- - 1 =ArmLoadedPress$_n11f8_n11fa$true +.mv _n1220 2 Y N +.names _n1220 +N +# RTOutReady == 1 +.names RTOutReady _n1220 _n121f +.def 0 +- =RTOutReady 1 +.mv _n1222 2 Y N +.names _n1222 +Y +# PieceGrabbedFromRT == 0 +.names PieceGrabbedFromRT$_nc51$raw_n1194 _n1222 _n1221 +.def 0 +- =PieceGrabbedFromRT$_nc51$raw_n1194 1 +# RTOutReady == 1 && PieceGrabbedFromRT == 0 +.names _n121f _n1221 _n1223 +.def 0 +1 1 1 +.names _n1223 _n1224 +- =_n1223 +# PieceGrabbedFromRT = 1 +.mv PieceGrabbedFromRT$_n1223_n1225$true 2 Y N +.names PieceGrabbedFromRT$_n1223_n1225$true +N +# if/else (RTOutReady == 1 && PieceGrabbedFromRT == 0) +.mv PieceGrabbedFromRT$_n1223$raw_n122c 2 Y N +.names PieceGrabbedFromRT$_n1223_n1225$true PieceGrabbedFromRT$_nc51$raw_n1194 _n1223 PieceGrabbedFromRT$_n1223$raw_n122c +- - 0 =PieceGrabbedFromRT$_nc51$raw_n1194 +- - 1 =PieceGrabbedFromRT$_n1223_n1225$true +# conflict arbitrators +.names _nc52 _nd34 _nd43 _nd6b _nd96 _neb4 _nede _nee7 _neea _nf13 _nf3a _nfce _nfd7 _nfda _n10b7 _n10e1 _n10ea _n10ee _n1113 _n1116 _n124a +.def 0 + 1 1 0 0 1 - - - - - - - - - - - - - - - 1 + 0 - - - - 1 1 1 1 - - - - - - - - - - - 1 + 0 - - - - 1 1 - - 1 - - - - - - - - - - 1 + 0 - - - - 0 - - - - 1 1 1 1 - - - - - - 1 + 0 - - - - 0 - - - - 0 - - - 1 1 1 1 - - 1 + 0 - - - - 0 - - - - 0 - - - 1 1 - - 1 1 1 +.mv _n124b 2 Y N +.names _n124a UnLoadArmLoaded$_nc51$raw_n1188 UnLoadArmLoaded _n124b +1 - - =UnLoadArmLoaded$_nc51$raw_n1188 +0 - - =UnLoadArmLoaded +.names _nc52 _neb4 _nf3a _nf73 _nfa4 _n11f9 _n1258 +.def 0 + 0 0 1 1 1 - 1 + - - - - - 1 1 +.mv _n1259 2 Y N +.names _n1258 ArmLoadedPress$_n11f8$raw_n11fd ArmLoadedPress _n1259 +1 - - =ArmLoadedPress$_n11f8$raw_n11fd +0 - - =ArmLoadedPress +.names _nc52 _nc55 _nc64 _nc82 _nc85 _nd34 _nd43 _nd6b _nd96 _ndfc _ne31 _ne52 _ne58 _neb4 _neb7 _neba _necb _nede _nee7 _neea _nf13 _nf3a _nf3d _nf40 _nf43 _nfce _nfd7 _nfda _n102e _n1077 _n10b7 _n10ba _n10bd _n10ce _n10e1 _n10ea _n10ee _n1113 _n1116 _n1266 +.def 0 + 1 1 0 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - 1 0 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - 1 - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - 1 - - - 1 1 1 - - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - 1 - - - 1 1 0 - - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - 1 - - - 1 - - 1 - - - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - 0 - - - - - - - 1 1 1 1 - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - 0 - - - - - - - 1 - - - 1 1 1 - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - 0 - - - - - - - 1 - - - - - - 1 1 - - - - - - - - - 1 + 0 - - - - - - - - - - - - 0 - - - - - - - 0 - - - - - - - - 1 1 1 - - - - - - 1 + 0 - - - - - - - - - - - - 0 - - - - - - - 0 - - - - - - - - 1 1 - 1 - - - - - 1 + 0 - - - - - - - - - - - - 0 - - - - - - - 0 - - - - - - - - 1 - - - 1 1 - - - 1 + 0 - - - - - - - - - - - - 0 - - - - - - - 0 - - - - - - - - 1 - - - 1 1 1 - - 1 + 0 - - - - - - - - - - - - 0 - - - - - - - 0 - - - - - - - - 1 - - - 1 - - 1 1 1 +.mv _n1267 3 Extend Retract Stop +.names _n1266 RAExtendUnLoadArm$_nc51$raw_n1189 RAExtendUnLoadArm _n1267 +1 - - =RAExtendUnLoadArm$_nc51$raw_n1189 +0 - - =RAExtendUnLoadArm +.names _nc52 _nd34 _nd43 _nd6b _nd96 _neb4 _nf3a _nfce _nfd7 _nfda _n11ce _n1274 +.def 0 + 1 1 0 0 1 - - - - - - 1 + 0 - - - - 0 1 1 1 1 - 1 + - - - - - - - - - - 1 1 +.mv _n1275 2 Y N +.names _n1274 ArmUnLoadedPress$_n11cd$raw_n11d3 ArmUnLoadedPress _n1275 +1 - - =ArmUnLoadedPress$_n11cd$raw_n11d3 +0 - - =ArmUnLoadedPress +.names _nc52 _nc55 _nc64 _nc67 _nc6b _nc82 _nc85 _ncd1 _nce0 _nd07 _nd34 _nd43 _nd46 _nd6b _ndfc _ne0b _ne31 _ne52 _ne58 _neb4 _neb7 _neba _necb _nf3a _nf3d _nf40 _nf43 _nf5a _n102e _n1031 _n1077 _n10b7 _n10ba _n10bd _n10ce _n1282 +.def 0 + 1 1 1 0 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 1 0 - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - 1 1 0 - - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - 1 0 - 1 - - - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - - - - - 1 1 - - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - - - - - 1 - 1 - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - - - - - - - 1 - - 1 1 - - - - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - 1 1 1 - - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - 1 1 - 1 - - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - 0 - - - 1 1 1 1 - - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - 0 - - - 1 1 - - 1 - - - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - 0 - - - 1 - - - - 1 1 - - - - - 1 + 0 - - - - - - - - - - - - - - - - - - 0 - - - 1 - - - - 1 - 1 - - - - 1 + 0 - - - - - - - - - - - - - - - - - - 0 - - - 0 - - - - - - - 1 1 1 - 1 + 0 - - - - - - - - - - - - - - - - - - 0 - - - 0 - - - - - - - 1 1 - 1 1 +.mv _n1283 3 CWise Stop CCWise +.names _n1282 RARotaryMotor$_nc51$raw_n118b RARotaryMotor _n1283 +1 - - =RARotaryMotor$_nc51$raw_n118b +0 - - =RARotaryMotor +.names _nc52 _nc55 _nc64 _nc67 _nc82 _nc9f _ncd1 _nd07 _nd34 _nd43 _nd46 _nd6b _nd6f _neb4 _nf3a _nf3d _nf5a _nf73 _nf7f _nf82 _nfa4 _n102e _n1031 _n1035 _n1290 +.def 0 + 1 1 1 1 - - - - - - - - - - - - - - - - - - - - 1 + 1 1 0 - 0 1 - - - - - - - - - - - - - - - - - - 1 + 1 - - - - - 1 1 - - - - - - - - - - - - - - - - 1 + 1 - - - - - - - 1 1 1 - - - - - - - - - - - - - 1 + 1 - - - - - - - 1 0 - 1 1 - - - - - - - - - - - 1 + 0 - - - - - - - - - - - - 0 1 1 1 - - - - - - - 1 + 0 - - - - - - - - - - - - 0 1 - - 1 1 1 - - - - 1 + 0 - - - - - - - - - - - - 0 1 - - 1 - - 1 - - - 1 + 0 - - - - - - - - - - - - 0 1 - - - - - - 1 1 1 1 +.mv _n1291 3 Extend Retract Stop +.names _n1290 RAExtendLoadArm$_nc51$raw_n118c RAExtendLoadArm _n1291 +1 - - =RAExtendLoadArm$_nc51$raw_n118c +0 - - =RAExtendLoadArm +.names _nc52 _nc55 _nc64 _nc82 _nc9f _n1224 _n129e +.def 0 + 1 1 0 0 1 - 1 + - - - - - 1 1 +.mv _n129f 2 Y N +.names _n129e PieceGrabbedFromRT$_n1223$raw_n122c PieceGrabbedFromRT _n129f +1 - - =PieceGrabbedFromRT$_n1223$raw_n122c +0 - - =PieceGrabbedFromRT +.names _nc52 _neb4 _nede _nee7 _neea _nf13 _nf3a _n10b7 _n10e1 _n10ea _n10ee _n1113 _n1116 _n11a3 _n12ac +.def 0 + 0 1 1 1 1 - - - - - - - - - 1 + 0 1 1 - - 1 - - - - - - - - 1 + 0 0 - - - - 0 1 1 1 1 - - - 1 + 0 0 - - - - 0 1 1 - - 1 1 - 1 + - - - - - - - - - - - - - 1 1 +.mv _n12ad 2 Y N +.names _n12ac PieceOutArm$_n11a2$raw_n11ac PieceOutArm _n12ad +1 - - =PieceOutArm$_n11a2$raw_n11ac +0 - - =PieceOutArm +.names _nc52 _nc55 _nc64 _nc82 _nc9f _neb4 _nf3a _nf73 _nfa4 _n12ba +.def 0 + 1 1 0 0 1 - - - - 1 + 0 - - - - 0 1 1 1 1 +.mv _n12bb 2 Y N +.names _n12ba LoadArmLoaded$_nc51$raw_n118e LoadArmLoaded _n12bb +1 - - =LoadArmLoaded$_nc51$raw_n118e +0 - - =LoadArmLoaded +# non-blocking assignments +# latches +.r RAExtendUnLoadArm$raw_nc45 RAExtendUnLoadArm +- =RAExtendUnLoadArm$raw_nc45 +.latch _n1267 RAExtendUnLoadArm +.r ArmLoadedPress$raw_nc49 ArmLoadedPress +- =ArmLoadedPress$raw_nc49 +.latch _n1259 ArmLoadedPress +.r UnLoadArmLoaded$raw_nc4c UnLoadArmLoaded +- =UnLoadArmLoaded$raw_nc4c +.latch _n124b UnLoadArmLoaded +.r RARotaryMotor$raw_nc46 RARotaryMotor +- =RARotaryMotor$raw_nc46 +.latch _n1283 RARotaryMotor +.r ArmUnLoadedPress$raw_nc48 ArmUnLoadedPress +- =ArmUnLoadedPress$raw_nc48 +.latch _n1275 ArmUnLoadedPress +.r RAExtendLoadArm$raw_nc44 RAExtendLoadArm +- =RAExtendLoadArm$raw_nc44 +.latch _n1291 RAExtendLoadArm +.r PieceOutArm$raw_nc47 PieceOutArm +- =PieceOutArm$raw_nc47 +.latch _n12ad PieceOutArm +.r PieceGrabbedFromRT$raw_nc4a PieceGrabbedFromRT +- =PieceGrabbedFromRT$raw_nc4a +.latch _n129f PieceGrabbedFromRT +.r LoadArmLoaded$raw_nc4b LoadArmLoaded +- =LoadArmLoaded$raw_nc4b +.latch _n12bb LoadArmLoaded +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/production_cell/prodcell.ord =================================================================== --- vis_dev/vis-2.1/examples/production_cell/prodcell.ord (revision 11) +++ vis_dev/vis-2.1/examples/production_cell/prodcell.ord (revision 11) @@ -0,0 +1,106 @@ +# vis release 2.0 (compiled 12-Sep-02 at 4:37 PM) +# network name: ProductionCell +# generated: Thu Sep 12 16:50:04 2002 +# +# name type mddId vals levs +FBReady latch 25 2 (0) +FBReady$NS shadow 26 2 (1) +FB.FBelt3$NS shadow 12 2 (2) +FB.FBelt3 latch 11 2 (3) +FB.FBelt2$NS shadow 34 2 (4) +FB.FBelt2 latch 33 2 (5) +FB.FBMotorSwitch latch 27 2 (6) +FB.FBMotorSwitch$NS shadow 28 2 (7) +FB.FBelt0$NS shadow 30 2 (8) +FB.FBelt0 latch 29 2 (9) +FB.FBelt1$NS shadow 32 2 (10) +FB.FBelt1 latch 31 2 (11) +PieceOutFB$NS shadow 52 2 (12) +PieceOutFB latch 51 2 (13) +PieceGrabbedFromFB latch 53 2 (14) +PieceGrabbedFromFB$NS shadow 54 2 (15) +RT.RTRotaryMotor latch 43 3 (16, 17) +RT.RTRotaryMotor$NS shadow 44 3 (18, 19) +RT.RTableCNTR.TableLoaded$NS shadow 72 2 (20) +RT.RTableCNTR.TableLoaded latch 71 2 (21) +RT.RTable.RTAngle latch 41 3 (22, 25) +RT.RTable.RTAngle$NS shadow 42 3 (23, 24) +RT.RTable.RTHight latch 47 3 (26, 28) +RT.RTable.RTHight$NS shadow 48 3 (27, 29) +RT.RTVerticalMotor latch 49 3 (30, 31) +RT.RTVerticalMotor$NS shadow 50 3 (32, 33) +PieceReleasedOnFB latch 35 2 (34) +PieceReleasedOnFB$NS shadow 36 2 (35) +TC.Crane.HorizontalPos latch 15 3 (36, 38) +TC.Crane.HorizontalPos$NS shadow 16 3 (37, 39) +TC.HorizontalMove latch 23 3 (40, 41) +TC.HorizontalMove$NS shadow 24 3 (42, 43) +TC.VerticalMove latch 17 3 (44, 45) +TC.VerticalMove$NS shadow 18 3 (46, 47) +TC.VerticalPos latch 37 3 (48, 49) +TC.VerticalPos$NS shadow 38 3 (50, 51) +TC.CraneCNTR.Grip latch 39 2 (52) +TC.CraneCNTR.Grip$NS shadow 40 2 (53) +PieceGrabbedFromDB$NS shadow 20 2 (54) +PieceGrabbedFromDB latch 19 2 (55) +PieceOutDB latch 21 2 (56) +PieceOutDB$NS shadow 22 2 (57) +DB.DBelt0$NS shadow 90 2 (58) +DB.DBelt0 latch 89 2 (59) +DB.DBMotorSwitch$NS shadow 88 2 (60) +DB.DBMotorSwitch latch 87 2 (61) +DB.DBelt3$NS shadow 14 2 (62) +DB.DBelt3 latch 13 2 (63) +DB.DBelt2$NS shadow 94 2 (64) +DB.DBelt2 latch 93 2 (65) +DB.DBelt1 latch 91 2 (66) +DB.DBelt1$NS shadow 92 2 (67) +PieceOutArm latch 95 2 (68) +PieceOutArm$NS shadow 96 2 (69) +DBReady latch 85 2 (70) +DBReady$NS shadow 86 2 (71) +AR.Arm.RAAnglePos latch 73 4 (72, 74) +AR.Arm.RAAnglePos$NS shadow 74 4 (73, 75) +RTOutReady$NS shadow 70 2 (76) +RTOutReady latch 69 2 (77) +AR.RARotaryMotor latch 67 3 (78, 79) +AR.RARotaryMotor$NS shadow 68 3 (80, 81) +PieceGrabbedFromRT latch 45 2 (82) +PieceGrabbedFromRT$NS shadow 46 2 (83) +AR.ACNTR.UnLoadArmLoaded latch 99 2 (84) +AR.ACNTR.UnLoadArmLoaded$NS shadow 100 2 (85) +AR.ACNTR.LoadArmLoaded latch 97 2 (86) +AR.ACNTR.LoadArmLoaded$NS shadow 98 2 (87) +PR.PressPosition$NS shadow 78 3 (88, 89) +PR.PressPosition latch 77 3 (90, 91) +PR.PressMotor latch 79 3 (92, 93) +PR.PressMotor$NS shadow 80 3 (94, 95) +PR.PrCNTR.PressLoaded latch 81 2 (96) +PR.PrCNTR.PressLoaded$NS shadow 82 2 (97) +PressReadyToBeLoaded$NS shadow 58 2 (98) +PressReadyToBeLoaded latch 57 2 (99) +ArmLoadedPress latch 59 2 (100) +ArmLoadedPress$NS shadow 60 2 (101) +PressReadyToBeUnLoaded latch 75 2 (102) +PressReadyToBeUnLoaded$NS shadow 76 2 (103) +ArmUnLoadedPress latch 83 2 (104) +ArmUnLoadedPress$NS shadow 84 2 (105) +AR.RAExtendUnLoadArm$NS shadow 66 3 (106, 107) +AR.RAExtendUnLoadArm latch 65 3 (108, 109) +AR.Arm.RAUnLoadArm latch 61 3 (110, 111) +AR.Arm.RAUnLoadArm$NS shadow 62 3 (112, 113) +AR.RAExtendLoadArm$NS shadow 64 3 (114, 115) +AR.RAExtendLoadArm latch 63 3 (116, 117) +AR.Arm.RALoadArm$NS shadow 56 3 (118, 119) +AR.Arm.RALoadArm latch 55 3 (120, 121) +FB.FBelt.FBelt2$raw_n40e$initial$_n40f pseudo-input 4 2 (122) +TC.Crane.HorizontalPos$raw_nc$initial$_nd pseudo-input 0 3 (123, 134) +RT.RTable.RTHight$raw_n524$initial$_n525 pseudo-input 1 3 (124, 133) +RT.RTable.RTAngle$raw_n522$initial$_n523 pseudo-input 2 3 (125, 132) +DB.DBelt.DBelt2$raw_n30e$initial$_n30f pseudo-input 8 2 (126) +FB.FBelt.FBelt3$raw_n410$initial$_n411 pseudo-input 3 2 (127) +DB.DBelt.DBelt1$raw_n30c$initial$_n30d pseudo-input 9 2 (128) +FB.FBelt.FBelt1$raw_n40c$initial$_n40d pseudo-input 5 2 (129) +FB.FBelt.FBelt0$raw_n40a$initial$_n40b pseudo-input 6 2 (130) +DB.DBelt.DBelt3$raw_n310$initial$_n311 pseudo-input 7 2 (131) +AR.Arm.RAAnglePos$raw_nb17$initial$_nb18 pseudo-input 10 4 (135, 136) Index: vis_dev/vis-2.1/examples/production_cell/prodcell.v =================================================================== --- vis_dev/vis-2.1/examples/production_cell/prodcell.v (revision 11) +++ vis_dev/vis-2.1/examples/production_cell/prodcell.v (revision 11) @@ -0,0 +1,1786 @@ +/* + * prodcell.v + * + * Model of the production cell circuit. Based on the description given in: + * + * @InBook{Lindne94, + * author = {Thomas Lindner}, + * title = {Case Study "Production Cell": A Comparative Study in Formal + * Software Development}, + * chapter = 2, + * publisher = {FZI}, + * year = 1994, + * pages = {9,21} + * } + * + * author: Abelardo Pardo (abel@vlsi.colorado.edu) + * date: 96/8/16 + * + * + */ + +/* Types */ +typedef enum {Y, N} sensor; +typedef enum {on, off} switch; +typedef enum {GoLeft, GoRight, Stop} craneHorizontalMovement; +typedef enum {GoUp, GoDown, Stop} craneVerticalMovement; +typedef enum {Grab, Free} craneGrip; +typedef enum {OverFB, Middle, OverDB} tcHorizontalPosition; +typedef enum {UpMost, DBHight, FBHight} tcVerticalPosition; +typedef enum {E, F} unitInBelt; +typedef enum {S, SSE, SE} rtAnglePosition; +typedef enum {Top, Mid, Bot} rtVerticalPosition; +typedef enum {CWise, Stop, CCWise} rtAngleMovement; +typedef enum {GoUp, GoDown, Stop} rtVerticalMovement; +typedef enum {GoUp, GoDown, Stop} pressVerticalMovement; +typedef enum {Top, Mid, Bot} pressVerticalPosition; +typedef enum {Extend, Retract, Stop} armHorizontalMovement; +typedef enum {OverRT, OverLoadedPress, OverDB, OverUnLoadedPress} armAnglePosition; +typedef enum {CWise, Stop, CCWise} armAngleMovement; +typedef enum {Extended, Retracted, Middle} armPosition; + +/* + * + * MAIN MODULE: The production cell + * + */ +module ProductionCell(clk); + input clk; + + sensor wire PieceOutDB; + sensor wire PieceOutFB; + sensor wire PieceGrabbedFromDB; + sensor wire PieceGrabbedFromRT; + sensor wire PieceGrabbedFromFB; + sensor wire FBReady; + sensor wire PieceOutArm; + sensor wire PieceReleasedOnFB; + sensor wire DBReady; + sensor wire ArmUnLoadedPress; + sensor wire PressReadyToBeUnLoaded; + sensor wire ArmLoadedPress; + sensor wire PressReadyToBeLoaded; + sensor wire RTOutReady; + + TravellingCraneSet TC(clk, PieceOutDB, FBReady, PieceGrabbedFromDB, + PieceReleasedOnFB); + + DepositBeltSet DB(clk, PieceGrabbedFromDB, PieceOutArm, PieceOutDB, + DBReady); + + FeedBeltSet FB(clk, PieceGrabbedFromFB, PieceReleasedOnFB, FBReady, + PieceOutFB); + + RotaryTableSet RT(clk, PieceOutFB, PieceGrabbedFromRT, + PieceGrabbedFromFB, RTOutReady); + + PressSet PR(clk, ArmLoadedPress, ArmUnLoadedPress, + PressReadyToBeLoaded, PressReadyToBeUnLoaded); + + ArmSet AR(clk, DBReady, PressReadyToBeUnLoaded, PressReadyToBeLoaded, + RTOutReady, PieceOutArm, ArmUnLoadedPress, ArmLoadedPress, + PieceGrabbedFromRT); + +endmodule // ProductionCell + +/* + * + * TRAVELLING CRANE SET + * + */ +module TravellingCraneSet(clk, PieceOutDB, FBReady, PieceGrabbedFromDB, + PieceReleasedOnFB); + input clk; + input PieceOutDB; + input FBReady; + output PieceGrabbedFromDB; + output PieceReleasedOnFB; + + sensor wire PieceOutDB; + sensor wire FBReady; + sensor wire PieceGrabbedFromDB; + sensor wire PieceReleasedOnFB; + + craneHorizontalMovement wire HorizontalMove; + craneVerticalMovement wire VerticalMove; + + sensor wire CraneOnTheLeft; + sensor wire CraneOnTheRight; + + tcVerticalPosition wire VerticalPos; + + TravellingCrane Crane(clk, HorizontalMove, VerticalMove, + CraneOnTheLeft, CraneOnTheRight, VerticalPos); + + TravellingCraneCNTR CraneCNTR(clk, FBReady, PieceOutDB, CraneOnTheLeft, + CraneOnTheRight, VerticalPos, HorizontalMove, + VerticalMove, PieceReleasedOnFB, + PieceGrabbedFromDB); +endmodule // TravellingCraneSet + +/* + * + * TRAVELLING CRANE + * + */ +module TravellingCrane(clk, HorizontalMove, VerticalMove, CraneOnTheLeft, + CraneOnTheRight, VerticalPos); + input clk; + input HorizontalMove; /* Signal controlling the horizontal movement */ + input VerticalMove; /* Signal controlling the vertical movement */ + output CraneOnTheLeft; /* Crane is on the left most position */ + output CraneOnTheRight; /* Crane is on the right most position */ + output VerticalPos; /* Which vertical position the crane is */ + + craneHorizontalMovement wire HorizontalMove; + craneVerticalMovement wire VerticalMove; + + sensor wire CraneOnTheLeft; + sensor wire CraneOnTheRight; + + tcHorizontalPosition reg HorizontalPos; + tcVerticalPosition reg VerticalPos; + + assign CraneOnTheLeft = (HorizontalPos == OverFB) ? Y : N; + assign CraneOnTheRight = (HorizontalPos == OverDB) ? Y : N; + + initial + begin + HorizontalPos = $ND(Middle, OverDB, OverFB); + VerticalPos = UpMost; + end // initial + + always @(posedge clk) begin + + /* Horizontal Movement evolution */ + if (HorizontalMove == GoLeft) begin + if (HorizontalPos == Middle) begin + HorizontalPos = OverFB; + end // if (HorizontalPos == Middle) + else if (HorizontalPos == OverDB) begin + HorizontalPos = Middle; + end // if (HorizontalPos == OverDB) + end // if (HorizontalMove == GoLeft) + + if (HorizontalMove == GoRight) begin + if (HorizontalPos == Middle) begin + HorizontalPos = OverDB; + end // if (HorizontalPos == Middle) + else if (HorizontalPos == OverFB) begin + HorizontalPos = Middle; + end // if (HorizontalPos == OverFB) + end // if (HorizontalMove == GoRight) + + /* VerticalMovement Evolution */ + if (VerticalMove == GoUp) begin + if (VerticalPos == DBHight) begin + VerticalPos = UpMost; + end // if (VerticalPos == DBHight) + else if (VerticalPos == FBHight) begin + VerticalPos = DBHight; + end // if (VerticalPos == FBHight) + end // if (VerticalMove == GoUp) + + if (VerticalMove == GoDown) begin + if (VerticalPos == UpMost) begin + VerticalPos = DBHight; + end // if (VerticalPos == UpMost) + else if (VerticalPos == DBHight) begin + VerticalPos = FBHight; + end // else: !if(VerticalPos == UpMost) + end // if (VerticalMove == GoDown) + + end +endmodule // TravellingCrane + +/* + * + * TRAVELLING CRANE CONTROLER + * + */ +module TravellingCraneCNTR(clk, FBReady, PieceOutDB, CraneOnTheLeft, + CraneOnTheRight, VerticalPos, HorizontalMove, + VerticalMove, PieceReleasedOnFB, PieceGrabbedFromDB); + input clk; + input FBReady; /* FBBelt is ready to receive a piece */ + input PieceOutDB; /* Deposit Belt has a piece to be picked up */ + input CraneOnTheLeft; /* Crane is on the left most position */ + input CraneOnTheRight; /* Crane is on the right most position */ + input VerticalPos; /* Register storing crane's vertical position */ + output HorizontalMove; /* Register controlling the horizontal motor */ + output VerticalMove; /* Register controlling the vertical motor */ + output PieceReleasedOnFB; /* A piece was dropped on FB */ + output PieceGrabbedFromDB; /* A piece has been grabbed from DB */ + + sensor wire FBReady; + sensor wire CraneOnTheLeft; + sensor wire CraneOnTheRight; + tcVerticalPosition wire VerticalPos; + sensor wire PieceOutDB; + + craneHorizontalMovement reg HorizontalMove; + craneVerticalMovement reg VerticalMove; + craneGrip reg Grip; + sensor reg PieceReleasedOnFB; + sensor reg PieceGrabbedFromDB; + + + initial + begin + HorizontalMove = Stop; + VerticalMove = Stop; + Grip = Free; + PieceReleasedOnFB = N; + PieceGrabbedFromDB = N; + end // initial + + always @(posedge clk) begin + case (Grip) + Grab: begin + case (VerticalPos) + UpMost: begin + Grip = Grab; + if (CraneOnTheLeft == Y) begin + HorizontalMove = Stop; + VerticalMove = GoDown; + end // if (CraneOnTheLeft) + else begin + if (CraneOnTheRight == N && CraneOnTheLeft == N) begin + if (HorizontalMove == GoLeft) begin + HorizontalMove = Stop; + VerticalMove = GoDown; + end // if (HorizontalMove == GoLeft) + else begin + HorizontalMove = GoLeft; + VerticalMove = Stop; + end // else: !if(HorizontalMove == GoLeft) + end // if (CraneOnTheRight == N && CraneOnTheLeft == N) + else begin + HorizontalMove = GoLeft; + VerticalMove = Stop; + end // else: !if(CraneOnTheRight == N && CraneOnTheLeft == Y) + end // else: !if(CraneOnTheLeft == Y) + end // case: UpMost + DBHight: begin + if (CraneOnTheLeft == Y) begin + if (VerticalMove == GoDown) begin + if (FBReady == Y) begin + Grip = Free; + HorizontalMove = Stop; + VerticalMove = GoUp; + PieceReleasedOnFB = Y; + end // if (FBReady == Y) + else begin + Grip = Grab; + HorizontalMove = Stop; + VerticalMove = Stop; + end // else: !if(FBReady == Y) + end // if (VerticalMove == GoDown) + else begin + Grip = Grab; + HorizontalMove = Stop; + VerticalMove = GoDown; + end // else: !if(VerticalMove == GoDown) + end // if (CraneOnTheLeft == Y) + if (CraneOnTheRight == Y) begin + Grip = Grab; + if (VerticalMove == GoUp) begin + HorizontalMove = GoLeft; + VerticalMove = Stop; + end // if (VerticalMove == GoUp) + else begin + HorizontalMove = Stop; + VerticalMove = GoUp; + end // else: !if(VerticalMove == GoUp) + end // if (CraneOnTheRight == Y) + end // case: DBHight + FBHight: begin + if (CraneOnTheLeft == Y) begin + if (FBReady == Y) begin + Grip = Free; + HorizontalMove = Stop; + VerticalMove = GoUp; + PieceReleasedOnFB = Y; + end // if (FBReady == Y) + else begin + Grip = Grab; + HorizontalMove = Stop; + VerticalMove = Stop; + end // else: !if(FBReady == Y) + end // if (CraneOnTheLeft == Y) + end // case: FBHight + endcase // _case (VerticalPos) + end // case: Grab + Free: begin + case (VerticalPos) + UpMost: begin + if (CraneOnTheLeft == Y) begin + Grip = Free; + HorizontalMove = GoRight; + VerticalMove = Stop; + end // if (CraneOnTheLeft == Y) + else begin + if (CraneOnTheRight == N) begin + if (HorizontalMove == GoRight) begin + Grip = Free; + HorizontalMove = Stop; + VerticalMove = GoDown; + end // if (HorizontalMove == GoRight) + else begin + Grip = Free; + HorizontalMove = GoRight; + VerticalMove = Stop; + end // else: !if(HorizontalMove = GoRight) + end // if (CraneOnTheRight == N) + else begin + if (PieceOutDB == Y) begin + if (VerticalMove == GoDown) begin + Grip = Grab; + HorizontalMove = Stop; + VerticalMove = GoUp; + PieceGrabbedFromDB = Y; + end // if (VerticalMove == GoDown) + else begin + Grip = Free; + HorizontalMove = Stop; + VerticalMove = GoDown; + end // else: !if(VerticalMove == GoDown) + end // if (PieceOutDB == Y) + else begin + Grip = Free; + HorizontalMove = Stop; + if (VerticalMove == GoDown) begin + VerticalMove = Stop; + end // if (VerticalMove == GoDown) + else begin + VerticalMove = GoDown; + end // else: !if(VerticalMove == GoDown) + end // else: !if(PieceOutDB == Y) + end // else: !if(CraneOnTheRight == N) + end // else: !if(CraneOnTheLeft == Y) + end // case: UpMost + DBHight: begin + if (CraneOnTheLeft == Y) begin + Grip = Free; + if (VerticalMove == GoUp) begin + HorizontalMove = GoRight; + VerticalMove = Stop; + end // if (VerticalMove == GoUp) + else begin + HorizontalMove = Stop; + VerticalMove = GoUp; + end // else: !if(VerticalMove == GoUp) + end // if (CraneOnTheLeft == Y) + if (CraneOnTheRight == Y) begin + if (PieceOutDB == Y) begin + Grip = Grab; + HorizontalMove = Stop; + VerticalMove = GoUp; + PieceGrabbedFromDB = Y; + end // if (PieceOutDB == Y) + else begin + Grip = Free; + HorizontalMove = Stop; + VerticalMove = Stop; + end // else: !if(PieceOutDB == Y) + end // if (CraneOnTheRight == Y) + end // case: DBHight + FBHight: begin + if (CraneOnTheLeft == Y) begin + Grip = Free; + HorizontalMove = Stop; + VerticalMove = GoUp; + end // if (CraneOnTheLeft == Y) + end // case: FBHight + endcase // _case (VerticalPos) + end // case: Free + endcase // _case (Grip) + + /* Complete the handshake with both belts */ + if (PieceOutDB == N && PieceGrabbedFromDB == Y) begin + PieceGrabbedFromDB = N; + end // if (PieceOutDB == N && PieceGrabbedFromDB == Y) + + if (FBReady == N && PieceReleasedOnFB == Y) begin + PieceReleasedOnFB = N; + end // if (FBReady == N && PieceReleasedOnFB == Y) + + + end // always @ (posedge clk) +endmodule // TravellingCraneCNTR + +/* + * + * DEPOSIT BELT SET + * + */ +module DepositBeltSet(clk, PieceGrabbedFromDB, PieceOutArm, + PieceOutDB, DBReady); + input clk; + input PieceGrabbedFromDB; + input PieceOutArm; + output PieceOutDB; + output DBReady; + + sensor wire PieceGrabbedFromDB; + sensor wire PieceOutArm; + sensor wire PieceOutDB; + sensor wire DBReady; + + switch wire DBMotorSwitch; + unitInBelt wire DBelt0, DBelt1, DBelt2, DBelt3; + + DepositBelt DBelt(clk, DBMotorSwitch, PieceOutArm, PieceGrabbedFromDB, + DBReady, DBelt0, DBelt1, DBelt2, DBelt3); + + DepositBeltCNTR DBeltCNTR(clk, DBelt0, DBelt1, DBelt2, DBelt3, + PieceGrabbedFromDB, PieceOutArm, DBMotorSwitch, + DBReady, PieceOutDB); +endmodule // DepositBeltSet + +/* + * + * DEPOSIT BELT + * + */ +module DepositBelt(clk, DBMotorSwitch, PieceOutArm, PieceGrabbedFromDB, + DBReady, DBelt0, DBelt1, DBelt2, DBelt3); + input clk; + input DBMotorSwitch; /* Signal controlling the motor */ + input PieceOutArm; /* Presence of a piece in the arm */ + input PieceGrabbedFromDB; /* Piece was grabbed from the DB */ + input DBReady; /* The belt is ready to accept another piece */ + output DBelt0, DBelt1, DBelt2, DBelt3; /* Positions on the belt */ + + switch wire DBMotorSwitch; + sensor wire PieceOutArm; + sensor wire PieceGrabbedFromDB; + sensor wire DBReady; + + unitInBelt reg DBelt0, DBelt1, DBelt2, DBelt3; + + initial + begin + DBelt0 = F; + DBelt1 = $ND(E,F); + DBelt2 = $ND(E,F); + DBelt3 = $ND(E,F); + end // initial + + always @(posedge clk) begin + + /* Motion produced by the motor */ + if (DBMotorSwitch == on) begin + DBelt0 = DBelt1; + DBelt1 = DBelt2; + DBelt2 = DBelt3; + DBelt3 = E; + end // if (DBMotorSwitch == on) + if (DBelt3 == E && PieceOutArm == Y && DBReady == Y) begin + DBelt3 = F; + end // if (DBelt3 == E && PieceOutArm == Y && DBReady == N) + + /* The piece was grabbed by the crane */ + if (PieceGrabbedFromDB == Y) begin + DBelt0 = E; + end // if (PieceGrabbedFromDB == Y) + end // always @ (posedge clk) +endmodule // DepositBelt + + +/* + * + * DEPOSIT BELT CONTROL + * + */ +module DepositBeltCNTR(clk, DBelt0, DBelt1, DBelt2, DBelt3, + PieceGrabbedFromDB, PieceOutArm, DBMotorSwitch, + DBReady, PieceOutDB); + input clk; + input DBelt0, DBelt1, DBelt2, DBelt3; /* Belt positions */ + input PieceGrabbedFromDB; /* A piece was grabbed from the DB */ + input PieceOutArm; /* A piece is ready to be picked up by the belt */ + output DBMotorSwitch; /* Signal controlling the motor */ + output DBReady; /* The belt is ready to accept another piece */ + output PieceOutDB; /* Piece ready to be picked by the crane */ + + unitInBelt wire DBelt0, DBelt1, DBelt2, DBelt3; + sensor wire PieceGrabbedFromDB; + sensor wire PieceOutArm; + + switch reg DBMotorSwitch; + sensor reg DBReady; + sensor reg PieceOutDB; + + initial + begin + DBMotorSwitch = off; + DBReady = N; + PieceOutDB = N; + end + + always @(posedge clk) begin + + /* Control the handshake with the crane */ + if ((DBelt0 == F && PieceOutDB == N && PieceGrabbedFromDB == N) || + (DBelt0 == E && DBelt1 == F && DBMotorSwitch == on && + PieceOutDB == N && PieceGrabbedFromDB == N)) begin + PieceOutDB = Y; + end // if (DBelt0 == F && PieceOutDB == N && PieceGrabbedFromDB == N) + + if (PieceOutDB == Y && PieceGrabbedFromDB == Y) begin + PieceOutDB = N; + end // if (PieceOutDB == Y && PieceGrabbedFromDB == Y) + + + /* Control The handshake with the Arm */ + if (DBelt3 == E && PieceOutArm == N && DBReady == N) begin + DBReady = Y; + end // if (DBelt3 == E && PieceOutArm == Y && DBReady == N) + + if (PieceOutArm == Y && DBReady == Y) begin + DBReady = N; + DBMotorSwitch = on; + end // if (PieceOutArm == Y && DBReady == Y) + + /* Control the motor */ + if (DBelt0 == F) begin + DBMotorSwitch = off; + end // if (DBelt0 == F) + + if (DBelt0 == E && DBMotorSwitch == off && (DBelt1 == F || DBelt2 == F + || DBelt3 == F)) begin + DBMotorSwitch = on; + end + else begin + if (DBelt0 == E && DBMotorSwitch == on && DBelt1 == F) begin + DBMotorSwitch = off; + end // if (DBelt0 == E && DBMotorSwitch == on && DBelt1 == F) + end + + end // always @ (posedge clk) +endmodule // DepositBeltCNTR + +/* + * + * FEED BELT SET + * + */ +module FeedBeltSet(clk, PieceGrabbedFromFB, PieceReleasedOnFB, + FBReady, PieceOutFB); + input clk; + input PieceGrabbedFromFB; + input PieceReleasedOnFB; + output FBReady; + output PieceOutFB; + + sensor wire PieceGrabbedFromFB; + sensor wire PieceReleasedOnFB; + sensor wire FBReady; + sensor wire PieceOutFB; + + switch wire FBMotorSwitch; + unitInBelt wire FBelt0, FBelt1, FBelt2, FBelt3; + + FeedBelt FBelt(clk, FBMotorSwitch, PieceReleasedOnFB, PieceGrabbedFromFB, + FBReady, FBelt0, FBelt1, FBelt2, FBelt3); + + FeedBeltCNTR FBeltCNTR(clk, FBelt0, FBelt1, FBelt2, FBelt3, + PieceGrabbedFromFB, PieceReleasedOnFB, FBMotorSwitch, + FBReady, PieceOutFB); +endmodule // FeedBeltSet + + +/* + * + * FEED BELT + * + */ +module FeedBelt(clk, FBMotorSwitch, PieceReleasedOnFB, PieceGrabbedFromFB, + FBReady, FBelt0, FBelt1, FBelt2, FBelt3); + input clk; + input FBMotorSwitch; /* Motor controlling the belt */ + input PieceReleasedOnFB; /* Piece has been released in the belt */ + input PieceGrabbedFromFB; /* Piece was picked from the belt */ + input FBReady; /* Belt is ready to accept another piece */ + output FBelt0, FBelt1, FBelt2, FBelt3; /* Belt positions */ + + switch wire FBMotorSwitch; + sensor wire PieceReleasedOnFB; + sensor wire PieceGrabbedFromFB; + sensor wire FBReady; + + unitInBelt reg FBelt0, FBelt1, FBelt2, FBelt3; + + initial + begin + FBelt0 = $ND(E,F); + FBelt1 = $ND(E,F); + FBelt2 = $ND(E,F); + FBelt3 = $ND(E,F); + end // initial + + always @(posedge clk) begin + + /* Motion produced by the motor */ + if (FBMotorSwitch == on) begin + FBelt0 = FBelt1; + FBelt1 = FBelt2; + FBelt2 = FBelt3; + FBelt3 = E; + end // if (FBMotorSwitch == on) + if (FBelt3 == E && PieceReleasedOnFB == Y && FBReady == Y) begin + FBelt3 = F; + end // if (FBelt3 == E && PieceReleasedOnFB == Y && FBReady == N) + + /* The piece was grabbed by the crane */ + if (PieceGrabbedFromFB == Y) begin + FBelt0 = E; + end // if (PieceGrabbedFromFB == Y) + end // always @ (posedge clk) +endmodule // FeedBelt + + +/* + * + * FEED BELT CONTROL + * + */ +module FeedBeltCNTR(clk, FBelt0, FBelt1, FBelt2, FBelt3, + PieceGrabbedFromFB, PieceReleasedOnFB, FBMotorSwitch, + FBReady, PieceOutFB); + input clk; + input FBelt0, FBelt1, FBelt2, FBelt3; /* Belt Positions */ + input PieceGrabbedFromFB; /* Piece was grabbed from the belt */ + input PieceReleasedOnFB; /* Piece was deposited on the belt */ + output FBMotorSwitch; /* Signal controlling the motor */ + output FBReady; /* Belt is ready to receive another piece */ + output PieceOutFB; /* Belt has a piece ready to be picked */ + + unitInBelt wire FBelt0, FBelt1, FBelt2, FBelt3; + sensor wire PieceGrabbedFromFB; + sensor wire PieceReleasedOnFB; + + switch reg FBMotorSwitch; + sensor reg FBReady; + sensor reg PieceOutFB; + + initial + begin + FBMotorSwitch = off; + FBReady = N; + PieceOutFB = N; + end + + always @(posedge clk) begin + + /* Control the handshake with the crane */ + if ((FBelt0 == F && PieceOutFB == N && PieceGrabbedFromFB == N) || + (FBelt0 == E && FBelt1 == F && FBMotorSwitch == on && + PieceOutFB == N && PieceGrabbedFromFB == N)) begin + PieceOutFB = Y; + end // if (FBelt0 == F && PieceOutFB == N && PieceGrabbedFromFB == N) + + if (PieceOutFB == Y && PieceGrabbedFromFB == Y) begin + PieceOutFB = N; + end // if (PieceOutFB == Y && PieceGrabbedFromFB == Y) + + + /* Control The handshake with the Arm */ + if (FBelt3 == E && PieceReleasedOnFB == N && FBReady == N) begin + FBReady = Y; + end // if (FBelt3 == E && PieceReleasedOnFB == Y && FBReady == N) + + if (PieceReleasedOnFB == Y && FBReady == Y) begin + FBReady = N; + FBMotorSwitch = on; + end // if (PieceReleasedOnFB == Y && FBReady == Y) + + /* Control the motor */ + if (FBelt0 == F) begin + FBMotorSwitch = off; + end // if (FBelt0 == F) + + if (FBelt0 == E && FBMotorSwitch == off && (FBelt1 == F || FBelt2 == F + || FBelt3 == F)) begin + FBMotorSwitch = on; + end // if (FBelt0 == E && FBMotorSwitch == off &&... + else begin + if (FBelt0 == E && FBMotorSwitch == on && FBelt1 == F) begin + FBMotorSwitch = off; + end // if (FBelt0 == E && FBMotorSwitch == on && FBelt1 == F) + end + + end // always @ (posedge clk) +endmodule // FeedBeltCNTR + +/* + * + * ROTARY TABLE SET + * + */ +module RotaryTableSet(clk, PieceOutFB, PieceGrabbedFromRT, + PieceGrabbedFromFB, RTOutReady); + input clk; + input PieceOutFB; + input PieceGrabbedFromRT; + output PieceGrabbedFromFB; + output RTOutReady; + + sensor wire PieceOutFB; + sensor wire PieceGrabbedFromRT; + sensor wire PieceGrabbedFromFB; + sensor wire RTOutReady; + + rtAngleMovement wire RTRotaryMotor; + rtVerticalMovement wire RTVerticalMotor; + + sensor wire RTOnFB; + sensor wire RTOnArm; + sensor wire RTOnTop; + sensor wire RTOnBottom; + + RotaryTable RTable(clk, RTRotaryMotor, RTVerticalMotor, + RTOnFB, RTOnArm, RTOnTop, RTOnBottom); + RotaryTableCNTR RTableCNTR(clk, PieceOutFB, PieceGrabbedFromRT, + RTOnFB, RTOnArm, RTOnTop, RTOnBottom, + RTRotaryMotor, RTVerticalMotor, + PieceGrabbedFromFB, RTOutReady); +endmodule // RotarySet + +/* + * + * ROTARY TABLE + * + */ +module RotaryTable(clk, RTRotaryMotor, RTVerticalMotor, + RTOnFB, RTOnArm, RTOnTop, RTOnBottom); + input clk; + input RTRotaryMotor; + input RTVerticalMotor; + output RTOnFB; + output RTOnArm; + output RTOnTop; + output RTOnBottom; + + rtAngleMovement wire RTRotaryMotor; + rtVerticalMovement wire RTVerticalMotor; + + sensor wire RTOnFB; + sensor wire RTOnArm; + sensor wire RTOnTop; + sensor wire RTOnBottom; + + rtAnglePosition reg RTAngle; + rtVerticalPosition reg RTHight; + + assign RTOnFB = (RTAngle == S) ? Y : N; + assign RTOnArm = (RTAngle == SE) ? Y : N; + assign RTOnTop = (RTHight == Top) ? Y : N; + assign RTOnBottom = (RTHight == Bot) ? Y : N; + + initial + begin + RTAngle = $ND(S, SSE, SE); + RTHight = $ND(Top, Mid, Bot); + end // initial + + always @(posedge clk) begin + /* Rotary movement of the table */ + if (RTRotaryMotor == CWise) begin + case (RTAngle) + SE: begin + RTAngle = SSE; + end + SSE: begin + RTAngle = S; + end + endcase // _case (RTAngle) + end // if (RTRotaryMotor == CWise) + + if (RTRotaryMotor == CCWise) begin + case (RTAngle) + S: begin + RTAngle = SSE; + end + SSE: begin + RTAngle = SE; + end + endcase // _case (RTAngle) + end // if (RTRotaryMotor == CCWise) + + /* Vertical Movement of the table */ + if (RTVerticalMotor == GoUp) begin + case (RTHight) + Mid: begin + RTHight = Top; + end + Bot: begin + RTHight = Mid; + end + endcase // _case (RTHight) + end // if (RTVerticalMotor == GoUp) + + if (RTVerticalMotor == GoDown) begin + case (RTHight) + Mid: begin + RTHight = Bot; + end + Top: begin + RTHight = Mid; + end + endcase // _case (RTHight) + end // if (RTVerticalMotor = GoDown) + end // always @ (posedge clk) +endmodule // RotaryTable + +/* + * + * ROTARY TABLE CNTR + * + */ +module RotaryTableCNTR(clk, PieceOutFB, PieceGrabbedFromRT, + RTOnFB, RTOnArm, RTOnTop, RTOnBottom, + RTRotaryMotor, RTVerticalMotor, + PieceGrabbedFromFB, RTOutReady); + input clk; + input PieceOutFB; + input PieceGrabbedFromRT; + input RTOnFB; + input RTOnArm; + input RTOnTop; + input RTOnBottom; + output RTRotaryMotor; + output RTVerticalMotor; + output PieceGrabbedFromFB; + output RTOutReady; + + sensor wire PieceOutFB; + sensor wire PieceGrabbedFromRT; + sensor wire RTOnFB; + sensor wire RTOnArm; + sensor wire RTOnBottom; + sensor wire RTOnTop; + + rtAngleMovement wire CWiseChoice; + rtAngleMovement wire CCWiseChoice; + rtVerticalMovement wire UpChoice; + rtVerticalMovement wire DownChoice; + + rtAngleMovement reg RTRotaryMotor; + rtVerticalMovement reg RTVerticalMotor; + sensor reg PieceGrabbedFromFB; + sensor reg RTOutReady; + sensor reg TableLoaded; + +// assign CWiseChoice = $ND(Stop, CWise); +// assign CCWiseChoice = $ND(Stop, CCWise); +// assign UpChoice = $ND(Stop, GoUp); +// assign DownChoice = $ND(Stop, GoDown); + assign CWiseChoice = CWise; + assign CCWiseChoice = CCWise; + assign UpChoice = GoUp; + assign DownChoice = GoDown; + + initial + begin + RTRotaryMotor = Stop; + RTVerticalMotor = Stop; + PieceGrabbedFromFB = N; + RTOutReady = N; + TableLoaded = N; + end // initial + + always @(posedge clk) begin + case (TableLoaded) + Y: begin + if (RTOnTop == Y) begin + if (RTOnFB == Y) begin + RTRotaryMotor = CCWise; + RTVerticalMotor = Stop; + end // if (RTOnFB == Y) + if (RTOnFB == N && RTOnArm == N) begin + RTVerticalMotor = Stop; + if (RTRotaryMotor == CCWise) begin + RTRotaryMotor = Stop; + RTOutReady = Y; + end // if (RTRotaryMotor == CCWise) + else begin + if (RTRotaryMotor == Stop) begin + RTRotaryMotor = CCWise; + end // if (RTRotaryMotor == Stop) + end // else: !if(RTRotaryMotor == CCWise) + end // if (RTOnFB == N && RTOnArm == N) + if (RTOnArm == Y) begin + if (PieceGrabbedFromRT == Y) begin + RTOutReady = N; + RTRotaryMotor = CWiseChoice; + RTVerticalMotor = DownChoice; + TableLoaded = N; + end // if (PieceGrabbedFromRT == Y) + else begin + RTOutReady = Y; + RTRotaryMotor = Stop; + RTVerticalMotor = Stop; + end // else: !if(PieceGrabbedFromRT == Y) + end // if (RTOnArm == Y) + end // if (RTOnTop == Y) + if (RTOnTop == N && RTOnBottom == N) begin + if (RTOnFB ==Y) begin + RTRotaryMotor = CCWiseChoice; + if (RTVerticalMotor == GoUp) begin + RTVerticalMotor = Stop; + end // if (RTVerticalMotor == GoUp) + else begin + RTVerticalMotor = UpChoice; + end // else: !if(RTVerticalMotor == GoUp) + end // if (RTOnFB ==Y) + if (RTOnFB == N && RTOnArm == N) begin + if (RTRotaryMotor == CCWise && RTVerticalMotor == GoUp) begin + RTRotaryMotor = Stop; + RTVerticalMotor = Stop; + RTOutReady = Y; + end // if (RTRotaryMotor == CCWise && RTVerticalMotor == GoUp) + else begin + if (RTRotaryMotor!=CCWise && RTVerticalMotor == GoUp) begin + RTRotaryMotor = CCWiseChoice; + RTVerticalMotor = Stop; + end + else begin + if (RTRotaryMotor == CCWise && + RTVerticalMotor != GoUp) begin + RTRotaryMotor = Stop; + RTVerticalMotor = UpChoice; + end + else begin + if (RTRotaryMotor != CCWise + && RTVerticalMotor != GoUp) begin + RTRotaryMotor = CCWiseChoice; + RTVerticalMotor = UpChoice; + end + end + end + end + end // if (RTOnFB == N && RTOnArm == N) + if (RTOnArm == Y) begin + RTRotaryMotor = Stop; + if (RTVerticalMotor == GoUp) begin + RTVerticalMotor = Stop; + RTOutReady = Y; + end // if (RTVerticalMotor == GoUp) + else begin + RTVerticalMotor = GoUp; + end // else: !if(RTVerticalMotor == GoUp) + end // if (RTOnArm == Y) + end // if (RTOnTop == N && RTOnBottom == N) + if (RTOnBottom == Y) begin + if (RTOnFB == Y) begin + RTRotaryMotor = CCWiseChoice; + RTVerticalMotor = UpChoice; + end // if (RTOnFB == Y) + if (RTOnFB == N && RTOnArm == N) begin + RTVerticalMotor = UpChoice; + if (RTRotaryMotor == CCWise) begin + RTRotaryMotor = Stop; + end // if (RTRotaryMotor == CCWise) + else begin + RTRotaryMotor = CCWiseChoice; + end // else: !if(RTRotaryMotor == CCWise) + end // if (RTOnFB == N && RTOnArm == N) + if (RTOnArm == Y) begin + RTRotaryMotor = Stop; + RTVerticalMotor = GoUp; + end // if (RTOnArm == Y) + end // if (RTOnBottom == Y) + end // case: Y + N:begin + if (RTOnTop == Y) begin + if (RTOnFB == Y) begin + RTRotaryMotor = Stop; + RTVerticalMotor = GoDown; + end // if (RTOnFB == Y) + if (RTOnFB == N && RTOnArm == N) begin + RTVerticalMotor = DownChoice; + if (RTRotaryMotor == CWise) begin + RTRotaryMotor = Stop; + end // if (RTRotaryMotor == CWise) + else begin + RTRotaryMotor = CWiseChoice; + end // else: !if(RTRotaryMotor == CWise) + end // if (RTOnFB == N && RTOnArm == N) + if (RTOnArm == Y) begin + RTRotaryMotor = CWiseChoice; + RTVerticalMotor = DownChoice; + end // if (RTOnArm == Y) + end // if (RTOnTop == Y) + if (RTOnTop == N && RTOnBottom == N) begin + if (RTOnFB == Y) begin + if (RTVerticalMotor == GoDown) begin + if (PieceOutFB == Y) begin + TableLoaded = Y; + PieceGrabbedFromFB = Y; + RTRotaryMotor = CCWiseChoice; + RTVerticalMotor = UpChoice; + end // if (PieceOutFB == Y) + else begin + RTRotaryMotor = Stop; + RTVerticalMotor = Stop; + end // else: !if(PieceOutFB == Y) + end // if (RTVerticalMotor == GoDown) + else begin + RTRotaryMotor = Stop; + RTVerticalMotor = GoDown; + end // else: !if(RTVerticalMotor == GoDown) + end // if (RTOnFB == Y) + if (RTOnFB == N && RTOnArm == N) begin + if (RTRotaryMotor == CWise && RTVerticalMotor == GoDown) begin + if (PieceOutFB == Y) begin + TableLoaded = Y; + PieceGrabbedFromFB = Y; + RTRotaryMotor = CCWiseChoice; + RTVerticalMotor = UpChoice; + end // if (PieceOutFB == Y) + else begin + RTRotaryMotor = Stop; + RTVerticalMotor = Stop; + end // else: !if(PieceOutFB == Y) + end // if (RTRotaryMotor == CWise && RTVerticalMotor == GoDown) + else begin + if (RTRotaryMotor != CWise && + RTVerticalMotor == GoDown) begin + RTRotaryMotor = CWiseChoice; + RTVerticalMotor = Stop; + end + else begin + if (RTRotaryMotor == CWise && + RTVerticalMotor != GoDown) begin + RTRotaryMotor = Stop; + RTVerticalMotor = DownChoice; + end + else begin + if (RTRotaryMotor != CWise && + RTVerticalMotor != GoDown) begin + RTRotaryMotor = CWiseChoice; + RTVerticalMotor = DownChoice; + end + end + end + end + end // if (RTOnFB == N && RTOnArm == N) + if (RTOnArm == Y) begin + RTRotaryMotor = CWiseChoice; + if (RTVerticalMotor == GoDown) begin + RTVerticalMotor = Stop; + end // if (RTVerticalMotor == GoDown) + else begin + RTVerticalMotor = GoDown; + end // else: !if(RTVerticalMotor == GoDown) + end // if (RTOnArm == Y) + end // if (RTOnTop == N && RTOnBottom == N) + if (RTOnBottom == Y) begin + if (RTOnFB == Y) begin + if (PieceOutFB == Y) begin + PieceGrabbedFromFB = Y; + RTRotaryMotor = CCWiseChoice; + RTVerticalMotor = UpChoice; + TableLoaded = Y; + end // if (PieceOutFB == Y) + else begin + RTRotaryMotor = Stop; + RTVerticalMotor = Stop; + end // else: !if(PieceOutFB == Y) + end // if (RTOnFB == Y) + if (RTOnFB == N && RTOnArm == N) begin + RTVerticalMotor = Stop; + if (RTRotaryMotor == CWise) begin + RTRotaryMotor = Stop; + end // if (RTRotaryMotor == CWise) + else begin + RTRotaryMotor = CWise; + end // else: !if(RTRotaryMotor == CWise) + end // if (RTOnFB == N && RTOnArm == N) + if (RTOnArm == Y) begin + RTRotaryMotor = CWise; + RTVerticalMotor = Stop; + end // if (RTOnArm == Y) + end // if (RTOnBottom == Y) + end // case: N + endcase // _case (TableLoaded) + + if (PieceOutFB == N && PieceGrabbedFromFB == Y) begin + PieceGrabbedFromFB = N; + end // if (PieceOutFB == N && PieceGrabbedFromFB == Y) + + if (RTOutReady == Y && PieceGrabbedFromRT == Y) begin + RTOutReady = N; + end // if (RTOutReady == Y && PieceGrabbedFromRT == Y) + + end // always @ (posedge clk) +endmodule // RotaryTableCNTR + +/* + * + * PRESS SET + * + */ +module PressSet(clk, ArmLoadedPress, ArmUnLoadedPress, + PressReadyToBeLoaded, PressReadyToBeUnLoaded); + input clk; + input ArmLoadedPress; + input ArmUnLoadedPress; + output PressReadyToBeLoaded; + output PressReadyToBeUnLoaded; + + sensor wire ArmLoadedPress; + sensor wire ArmUnLoadedPress; + sensor wire PressReadyToBeLoaded; + sensor wire PressReadyToBeUnLoaded; + + pressVerticalMovement wire PressMotor; + pressVerticalPosition wire PressPosition; + + Press Pr(clk, PressMotor, PressPosition); + PressCNTR PrCNTR(clk, PressPosition, ArmLoadedPress, ArmUnLoadedPress, + PressMotor, PressReadyToBeLoaded, PressReadyToBeUnLoaded); +endmodule // PressSet + +/* + * + * PRESS + * + */ +module Press(clk, PressMotor, PressPosition); + input clk; + input PressMotor; + output PressPosition; + + pressVerticalMovement wire PressMotor; + + pressVerticalPosition reg PressPosition; + + initial + begin + PressPosition = Mid; + end // initial + + always @(posedge clk) begin + if (PressMotor == GoUp) begin + case (PressPosition) + Mid: begin + PressPosition = Top; + end // case: Mid + Bot: begin + PressPosition = Mid; + end // case: Bot + endcase // _case (PressPosition) + end // if (PressMotor == GoUp) + + if (PressMotor == GoDown) begin + case (PressPosition) + Top: begin + PressPosition = Mid; + end // case: Top + Mid: begin + PressPosition = Bot; + end // case: Mid + endcase // _case (PressPosition) + end // if (PressMotor = GoDown) + + end // always @ (posedge clk) +endmodule // Press + +/* + * + * PRESS CNTR + * + */ +module PressCNTR(clk, PressPosition, ArmLoadedPress, ArmUnLoadedPress, + PressMotor, PressReadyToBeLoaded, PressReadyToBeUnLoaded); + input clk; + input PressPosition; + input ArmLoadedPress; + input ArmUnLoadedPress; + output PressMotor; + output PressReadyToBeLoaded; + output PressReadyToBeUnLoaded; + + pressVerticalPosition wire PressPosition; + sensor wire ArmLoadedPress; + sensor wire ArmUnLoadedPress; + + pressVerticalMovement reg PressMotor; + sensor reg PressReadyToBeLoaded; + sensor reg PressReadyToBeUnLoaded; + sensor reg PressLoaded; + + initial + begin + PressMotor = Stop; + PressReadyToBeLoaded = N; + PressReadyToBeUnLoaded = N; + PressLoaded = N; + end // initial + + always @(posedge clk) begin + + case (PressLoaded) + Y: begin + case (PressPosition) + Top: begin + PressMotor = GoDown; + end + Mid: begin + if (PressMotor == GoDown) begin + PressMotor = Stop; + PressReadyToBeUnLoaded = Y; + end // if (PressMotor == GoDown) + else begin + PressMotor = GoDown; + end // else: !if(PressMotor == GoDown) + end // case: Mid + Bot: begin + if (ArmUnLoadedPress == Y && PressReadyToBeUnLoaded == Y) begin + PressMotor = GoUp; + PressLoaded = N; + PressReadyToBeUnLoaded = N; + end // if (ArmUnLoadedPress == Y && PressReadyToBeUnLoaded == Y) + else begin + PressMotor = Stop; + end + end // case: Bot + endcase // _case (PressPosition) + end // case: Y + N: begin + case (PressPosition) + Top: begin + if (PressMotor == GoDown) begin + PressMotor = Stop; + PressReadyToBeLoaded = Y; + end // if (PressMotor == GoDown) + else begin + PressMotor = GoDown; + end // else: !if(PressMotor == GoDown) + end // case: Top + Mid: begin + if (ArmLoadedPress == Y) begin + PressLoaded = Y; + PressMotor = GoUp; + end // if (ArmLoadedPress == Y) + else begin + PressMotor = Stop; + PressReadyToBeLoaded = Y; + end // else: !if(ArmLoadedPress == Y) + end // case: Mid + endcase // _case (PressPosition) + end // case: N + endcase // _case (PressLoaded) + + if (ArmLoadedPress == Y && PressReadyToBeLoaded == Y) begin + PressReadyToBeLoaded = N; + end // if (ArmLoadedPress == N && PressReadyToBeLoaded == Y) + + if (PressReadyToBeUnLoaded == Y && ArmUnLoadedPress == Y) begin + PressReadyToBeUnLoaded = N; + end // if (PressReadyToBeUnLoaded == Y && ArmUnLoadedPress == Y) + end // always @ (posedge clk) + +endmodule // PressCNTR + +/* + * + * ARM SET + * + */ +module ArmSet(clk, DBReady, PressReadyToBeUnLoaded, PressReadyToBeLoaded, + RTOutReady, PieceOutArm, ArmUnLoadedPress, ArmLoadedPress, + PieceGrabbedFromRT); + input clk; + input DBReady; + input PressReadyToBeUnLoaded; + input PressReadyToBeLoaded; + input RTOutReady; + output PieceOutArm; + output ArmUnLoadedPress; + output ArmLoadedPress; + output PieceGrabbedFromRT; + + sensor wire DBReady; + sensor wire PressReadyToBeUnLoaded; + sensor wire PressReadyToBeLoaded; + sensor wire RTOutReady; + sensor wire PieceOutArm; + sensor wire ArmUnLoadedPress; + sensor wire ArmLoadedPress; + sensor wire PieceGrabbedFromRT; + + sensor wire RALoadArmExtended; + sensor wire RALoadArmRetracted; + sensor wire RAUnLoadArmExtended; + sensor wire RAUnLoadArmRetracted; + sensor wire RAArmOverRT; + sensor wire RAArmOverUnLoadedPress; + sensor wire RAArmOverLoadedPress; + sensor wire RAArmOverDB; + armHorizontalMovement wire RAExtendLoadArm; + armHorizontalMovement wire RAExtendUnLoadArm; + armAngleMovement wire RARotaryMotor; + + RobotArm Arm(clk, RAExtendLoadArm, RAExtendUnLoadArm, RARotaryMotor, + RALoadArmExtended, RALoadArmRetracted, RAUnLoadArmExtended, + RAUnLoadArmRetracted, RAArmOverRT, RAArmOverUnLoadedPress, + RAArmOverLoadedPress, RAArmOverDB); + + RobotArmCNTR ACNTR(clk, RALoadArmExtended, RALoadArmRetracted, + RAUnLoadArmExtended, RAUnLoadArmRetracted, RAArmOverRT, + RAArmOverUnLoadedPress, RAArmOverLoadedPress, RAArmOverDB, + DBReady, PressReadyToBeUnLoaded, PressReadyToBeLoaded, + RTOutReady, RAExtendLoadArm, RAExtendUnLoadArm, + RARotaryMotor, PieceOutArm, ArmUnLoadedPress, + ArmLoadedPress, PieceGrabbedFromRT); +endmodule // ArmSet + +/* + * + * ROBOT ARM + * + */ +module RobotArm(clk, RAExtendLoadArm, RAExtendUnLoadArm, RARotaryMotor, + RALoadArmExtended, RALoadArmRetracted, RAUnLoadArmExtended, + RAUnLoadArmRetracted, RAArmOverRT, RAArmOverUnLoadedPress, + RAArmOverLoadedPress, RAArmOverDB); + input clk; + input RAExtendLoadArm; + input RAExtendUnLoadArm; + input RARotaryMotor; + output RALoadArmExtended; + output RALoadArmRetracted; + output RAUnLoadArmExtended; + output RAUnLoadArmRetracted; + output RAArmOverRT; + output RAArmOverUnLoadedPress; + output RAArmOverLoadedPress; + output RAArmOverDB; + + armHorizontalMovement wire RAExtendLoadArm; + armHorizontalMovement wire RAExtendUnLoadArm; + armAngleMovement wire RARotaryMotor; + sensor wire RALoadArmExtended; + sensor wire RALoadArmRetracted; + sensor wire RAUnLoadArmExtended; + sensor wire RAUnLoadArmRetracted; + sensor wire RAArmOverRT; + sensor wire RAArmOverUnLoadedPress; + sensor wire RAArmOverLoadedPress; + sensor wire RAArmOverDB; + + armPosition reg RALoadArm; + armPosition reg RAUnLoadArm; + armAnglePosition reg RAAnglePos; + + assign RALoadArmExtended = (RALoadArm == Extended) ? Y : N; + assign RALoadArmRetracted = (RALoadArm == Retracted) ? Y : N; + assign RAUnLoadArmExtended = (RAUnLoadArm == Extended) ? Y : N; + assign RAUnLoadArmRetracted = (RAUnLoadArm == Retracted) ? Y : N; + assign RAArmOverRT = (RAAnglePos == OverRT) ? Y : N; + assign RAArmOverUnLoadedPress = (RAAnglePos == OverUnLoadedPress) ? Y : N; + assign RAArmOverLoadedPress = (RAAnglePos == OverLoadedPress) ? Y : N; + assign RAArmOverDB = (RAAnglePos == OverDB) ? Y : N; + + initial + begin + RALoadArm = Retracted; + RAUnLoadArm = Retracted; + RAAnglePos = $ND(OverRT, OverLoadedPress, OverDB, OverUnLoadedPress); + end // initial + + always @(posedge clk) begin + + /* Control the horizontal movement of the load arm */ + if (RAExtendLoadArm == Extend) begin + case (RALoadArm) + Retracted: begin + RALoadArm = Middle; + end // case: Retracted + Middle: begin + RALoadArm = Extended; + end // if (RALoadArm = Middle) + endcase // _case (RALoadArm) + end // if (RAExtendLoadArm == Extend) + + if (RAExtendLoadArm == Retract) begin + case (RALoadArm) + Extended: begin + RALoadArm = Middle; + end // case: Extended + Middle: begin + RALoadArm = Retracted; + end // if (RALoadArm == Middle) + endcase // _case (RALoadArm) + end // if (RAExtendLoadArm = Retract) + + /* Control the horizontal movement of the UnLoad arm */ + if (RAExtendUnLoadArm == Extend) begin + case (RAUnLoadArm) + Retracted: begin + RAUnLoadArm = Middle; + end // case: Retracted + Middle: begin + RAUnLoadArm = Extended; + end // case: Middle + endcase // _case (RAUnLoadArm) + end // if (RAExtendLoadArm == Extend) + + if (RAExtendUnLoadArm == Retract) begin + case (RAUnLoadArm) + Extended: begin + RAUnLoadArm = Middle; + end // case: Extended + Middle: begin + RAUnLoadArm = Retracted; + end // case: Middle + endcase // _case (RAUnLoadArm) + end // if (RAExtendUnLoadArm = Retract) + + /* Control the rotation of the arm */ + if (RARotaryMotor == CCWise) begin + case (RAAnglePos) + OverRT: begin + RAAnglePos = OverUnLoadedPress; + end // case: OverRT + OverUnLoadedPress: begin + RAAnglePos = OverDB; + end // case: OverLoadedPress + OverDB: begin + RAAnglePos = OverLoadedPress; + end // case: OverDB + endcase // _case (RAAnglePos) + end // if (RARotaryMotor == CCWise) + if (RARotaryMotor == CWise) begin + case (RAAnglePos) + OverLoadedPress: begin + RAAnglePos = OverDB; + end // case: OverLoadedPress + OverDB: begin + RAAnglePos = OverUnLoadedPress; + end // case: OverDB + OverUnLoadedPress: begin + RAAnglePos = OverRT; + end // case: OverUnLoadedPress + endcase // _case (RAAnglePos) + end // if (RARotaryMotor == CWise) + end // always @ (posedge clk) +endmodule // RobotArm + +/* + * + * ROBOT ARM CNTR + * + */ +module RobotArmCNTR(clk, RALoadArmExtended, RALoadArmRetracted, + RAUnLoadArmExtended, RAUnLoadArmRetracted, RAArmOverRT, + RAArmOverUnLoadedPress, RAArmOverLoadedPress, RAArmOverDB, + DBReady, PressReadyToBeUnLoaded, PressReadyToBeLoaded, + RTOutReady, RAExtendLoadArm, RAExtendUnLoadArm, + RARotaryMotor, PieceOutArm, ArmUnLoadedPress, + ArmLoadedPress, PieceGrabbedFromRT); + input clk; + input RALoadArmExtended; + input RALoadArmRetracted; + input RAUnLoadArmExtended; + input RAUnLoadArmRetracted; + input RAArmOverRT; + input RAArmOverUnLoadedPress; + input RAArmOverLoadedPress; + input RAArmOverDB; + input DBReady; + input PressReadyToBeUnLoaded; + input PressReadyToBeLoaded; + input RTOutReady; + output RAExtendLoadArm; + output RAExtendUnLoadArm; + output RARotaryMotor; + output PieceOutArm; + output ArmUnLoadedPress; + output ArmLoadedPress; + output PieceGrabbedFromRT; + + sensor wire DBReady; + sensor wire PressReadyToBeUnLoaded; + sensor wire PressReadyToBeLoaded; + sensor wire RTOutReady; + sensor wire RALoadArmExtended; + sensor wire RALoadArmRetracted; + sensor wire RAUnLoadArmExtended; + sensor wire RAUnLoadArmRetracted; + sensor wire RAArmOverRT; + sensor wire RAArmOverUnLoadedPress; + sensor wire RAArmOverLoadedPress; + sensor wire RAArmOverDB; + + armHorizontalMovement reg RAExtendLoadArm; + armHorizontalMovement reg RAExtendUnLoadArm; + armAngleMovement reg RARotaryMotor; + sensor reg PieceOutArm; + sensor reg ArmUnLoadedPress; + sensor reg ArmLoadedPress; + sensor reg PieceGrabbedFromRT; + sensor reg LoadArmLoaded; + sensor reg UnLoadArmLoaded; + + initial + begin + RAExtendLoadArm = Stop; + RAExtendUnLoadArm = Stop; + RARotaryMotor = Stop; + PieceOutArm = N; + ArmUnLoadedPress = N; + ArmLoadedPress = N; + PieceGrabbedFromRT = N; + LoadArmLoaded = N; + UnLoadArmLoaded = N; + end // initial + + always @(posedge clk) begin + if (LoadArmLoaded == N && UnLoadArmLoaded == N) begin + if (RAArmOverRT == Y) begin + if (RALoadArmRetracted == Y && RAUnLoadArmRetracted == Y && + RAExtendLoadArm == Stop && RAExtendUnLoadArm == Stop && + RARotaryMotor == Stop) begin + if (RTOutReady == Y) begin + RAExtendLoadArm = Extend; + end // if (RTOutReady == Y) + else begin + if (PressReadyToBeUnLoaded == Y) begin + RARotaryMotor = CCWise; + end // if (PressReadyToBeUnLoaded == Y) + end // else: !if(RTOutReady == Y) + end + else begin + if (RALoadArmRetracted == Y && RAUnLoadArmRetracted == Y && + RAExtendLoadArm == Stop && RAExtendUnLoadArm == Stop && + RARotaryMotor == CCWise) begin + if (PressReadyToBeUnLoaded == Y) begin + RARotaryMotor = Stop; + RAExtendUnLoadArm = Extend; + end // if (PressReadyToBeUnLoaded == Y) + end + else begin + if (RALoadArmRetracted == N && RALoadArmExtended == N && + RAUnLoadArmRetracted == Y && + RAExtendLoadArm == Extend && RAExtendUnLoadArm == Stop && + RARotaryMotor == Stop) begin + RAExtendLoadArm = Retract; + LoadArmLoaded = Y; + PieceGrabbedFromRT = Y; + end + end + end // else: !if(RALoadArmRetracted == Y &&... + end // if (RAArmOverRT == Y) + if (RAArmOverLoadedPress == Y) begin + if (RALoadArmRetracted == Y && RAUnLoadArmRetracted == Y && + RAExtendLoadArm == Stop && RAExtendUnLoadArm == Stop && + RARotaryMotor == Stop) begin + RARotaryMotor = CWise; + end // if (RALoadArmRetracted == Y && RAUnLoadArmRetracted == Y ... + if (RALoadArmRetracted == N && RALoadArmExtended == N && + RAUnLoadArmRetracted == Y && + RAExtendLoadArm == Retract && RAExtendUnLoadArm == Stop && + RARotaryMotor == Stop) begin + RAExtendLoadArm = Stop; + RARotaryMotor = CWise; + end // if (RALoadArmRetracted == N && RALoadArmExtended == N &&... + end // if (RAArmOverLoadedPress == Y) + if (RAArmOverUnLoadedPress == Y) begin + if (RALoadArmRetracted == Y && RAUnLoadArmRetracted == Y && + RAExtendLoadArm == Stop && RAExtendUnLoadArm == Stop && + RARotaryMotor == Stop) begin + if (PressReadyToBeUnLoaded == Y) begin + RAExtendLoadArm = Extend; + end // if (RTOutReady == Y) + else begin + RARotaryMotor = CWise; + end // else: !if(RTOutReady == Y) + end // if (RALoadArmRetracted == Y && RAUnLoadArmRetracted == Y ... + else begin + if (RALoadArmRetracted == Y && RAUnLoadArmRetracted == Y && + RAExtendLoadArm == Stop && RAExtendUnLoadArm == Stop && + RARotaryMotor == CWise) begin + RARotaryMotor = Stop; + if (RTOutReady == Y) begin + RAExtendLoadArm = Extend; + end // if (RTOutReady == Y) + end // if (RALoadArmRetracted == Y && ... + else begin + if (RALoadArmRetracted == Y && RAUnLoadArmRetracted == N && + RAUnLoadArmExtended == N && + RAExtendLoadArm == Stop && RAExtendUnLoadArm == Extend && + RARotaryMotor == Stop) begin + RAExtendUnLoadArm = Retract; + ArmUnLoadedPress = Y; + UnLoadArmLoaded = Y; + end // if (RALoadArmRetracted == Y && RAUnLoadArmRetr... + end // else: !if(RALoadArmRetracted == Y && RAUnLoadArmRetr... + end // else: !if(RALoadArmRetracted == Y && RAUnLoadArmRetract... + end // if (RAArmOverUnLoadedPress == Y) + if (RAArmOverDB == Y) begin + if (RALoadArmRetracted == Y && RAUnLoadArmRetracted == Y && + RAExtendLoadArm == Stop && RAExtendUnLoadArm == Stop && + RARotaryMotor == Stop) begin + RARotaryMotor = CWise; + end // if (RALoadArmRetracted == Y && RAUnLoadArmRetracte... + if (RAExtendUnLoadArm == Retract && RAUnLoadArmExtended == N && + RAUnLoadArmRetracted == N) begin + RAExtendUnLoadArm = Stop; + RARotaryMotor = CWise; + end + if (RARotaryMotor == CWise) begin + if (PressReadyToBeUnLoaded == Y && RTOutReady == N) begin + RARotaryMotor = Stop; + RAExtendUnLoadArm = Extend; + end // if (PressReadyToBeUnLoaded == Y && RTOutReady == N) + end // if (RARotaryMotor == CWise) + end // if (RAArmOverDB == Y) + end // if (LoadArmLoaded == N && UnLoadArmLoaded == N) + else begin + if (LoadArmLoaded == N && UnLoadArmLoaded == Y) begin + if (RAArmOverUnLoadedPress == Y) begin + if (RARotaryMotor == CCWise) begin + RARotaryMotor = Stop; + RAExtendUnLoadArm = Extend; + end // if (RARotaryMotor == CCWise) + if (RAExtendUnLoadArm == Retract && RAUnLoadArmExtended == N + && RAUnLoadArmRetracted == N) begin + RAExtendUnLoadArm = Stop; + RARotaryMotor = CCWise; + end + end // if (RAArmOverUnloadedPress == Y) + if (RAArmOverDB == Y) begin + if (RAExtendUnLoadArm == Extend && RAUnLoadArmExtended == N && + RAUnLoadArmRetracted == N) begin + if (DBReady == Y) begin + RAExtendUnLoadArm = Retract; + PieceOutArm = Y; + UnLoadArmLoaded = N; + end // if (DBReady == Y) + else begin + RAExtendUnLoadArm = Stop; + end // else: !if(DBReady == Y) + end + if (RAExtendUnLoadArm == Stop && RAUnLoadArmExtended == Y && + DBReady == Y) begin + RAExtendUnLoadArm = Retract; + PieceOutArm = Y; + UnLoadArmLoaded = N; + end + end // if (RAArmOverDB == Y) + end // if (LoadArmLoaded == N && UnLoadArmLoaded == Y) + else begin + if (LoadArmLoaded == Y && UnLoadArmLoaded == N) begin + if (RAArmOverRT == Y) begin + if (RARotaryMotor == CCWise) begin + if (PressReadyToBeUnLoaded == Y) begin + RARotaryMotor = Stop; + RAExtendUnLoadArm = Extend; + end // if (PressReadyToBeUnLoaded == Y) + end // if (RARotaryMotor == CCWise) + if (RAExtendLoadArm == Retract && RALoadArmExtended == N && + RALoadArmRetracted == N) begin + RAExtendLoadArm = Stop; + RARotaryMotor = CCWise; + end + end // if (RAArmOverUnLoadedPress == Y) + if (RAArmOverLoadedPress == Y) begin + if (RAExtendLoadArm == Stop && RARotaryMotor == Stop && + RAExtendUnLoadArm == Stop && + RALoadArmRetracted == Y) begin + if (PressReadyToBeLoaded == Y) begin + RAExtendLoadArm = Extend; + end // if (PressReadyToBeLoaded == Y) + end + if (RAExtendLoadArm == Extend && RALoadArmExtended == N && + RALoadArmRetracted == N) begin + RAExtendLoadArm = Retract; + ArmLoadedPress = Y; + LoadArmLoaded = N; + end + end // if (RAArmOverLoadedPress == Y) + if (RAArmOverUnLoadedPress == Y) begin + if (RAExtendUnLoadArm == Extend && RAUnLoadArmExtended == N + && RAUnLoadArmRetracted == N) begin + if (PressReadyToBeUnLoaded == Y) begin + ArmUnLoadedPress = Y; + UnLoadArmLoaded = Y; + RAExtendUnLoadArm = Retract; + end // if (PressReadyToBeUnLoaded == Y) + end + end // if (RAArmOverUnLoadedPress == Y) + if (RAArmOverDB == Y) begin + if (RARotaryMotor == CCWise) begin + RARotaryMotor = Stop; + if (PressReadyToBeLoaded == Y) begin + RAExtendLoadArm = Extend; + end // if (PressReadyToBeLoaded == Y) + end // if (RARotaryMotor == CCWise) + if (RAExtendUnLoadArm == Retract && RAUnLoadArmExtended == N + && RAUnLoadArmRetracted == N)begin + RAExtendUnLoadArm = Stop; + RARotaryMotor = CCWise; + end + end // if (RAArmOverDB == Y) + end // if (LoadArmLoaded == Y && UnLoadArmLoaded == N) + else begin + if (LoadArmLoaded == Y && UnLoadArmLoaded == Y) begin + if (RAArmOverUnLoadedPress == Y) begin + if (RARotaryMotor == CCWise) begin + RARotaryMotor = Stop; + RAExtendUnLoadArm = Extend; + end // if (RARotaryMotor = CCWise) + if (RAExtendUnLoadArm == Retract && + RAUnLoadArmExtended == N && + RAUnLoadArmRetracted == N) begin + RAExtendUnLoadArm = Stop; + RARotaryMotor = CCWise; + end + end // if (RAArmOverUnLoadedPress == Y) + if (RAArmOverDB == Y) begin + if (RAExtendUnLoadArm == Extend && RAUnLoadArmExtended == N + && RAUnLoadArmRetracted == N) begin + RAExtendUnLoadArm = Stop; + if (DBReady == Y) begin + RAExtendUnLoadArm = Retract; + UnLoadArmLoaded = N; + PieceOutArm = Y; + end // if (DBReady == Y) + end + if (RAExtendUnLoadArm == Stop && + RAUnLoadArmExtended == Y) begin + if (DBReady == Y) begin + RAExtendUnLoadArm = Retract; + UnLoadArmLoaded = N; + PieceOutArm = Y; + end // if (DBReady == Y) + end + end // if (RAArmOverDB == Y) + end // if (LoadArmLoaded == Y && UnLoadArmLoaded == Y) + + end // else: !if(LoadArmLoaded == Y && UnLoadArmLoaded == N) + end // else: !if(LoadArmLoaded == N && UnLoadArmLoaded == Y) + end // else: !if(LoadArmLoaded == N && UnLoadArmLoaded == N) + + if (DBReady == N && PieceOutArm == Y) begin + PieceOutArm = N; + end // if (DBReady == N && PieceOutArm == Y) + + if (PressReadyToBeUnLoaded == N && ArmUnLoadedPress == Y) begin + ArmUnLoadedPress = N; + end // if (PressReadyToBeUnLoaded == N && ArmUnLoadedPress == Y) + + if (ArmLoadedPress == Y && PressReadyToBeLoaded == N) begin + ArmLoadedPress = N; + end // if (ArmLoadedPress == Y && PieceRecivedOnPress == N) + + if (RTOutReady == N && PieceGrabbedFromRT == Y) begin + PieceGrabbedFromRT = N; + end // if (RTOutReady == N && PieceGrabbedFromRT == Y) + end // always @ (posedge clk) +endmodule // RobotArmCNTR Index: vis_dev/vis-2.1/examples/rcnum/README =================================================================== --- vis_dev/vis-2.1/examples/rcnum/README (revision 11) +++ vis_dev/vis-2.1/examples/rcnum/README (revision 11) @@ -0,0 +1,6 @@ +This directory contains a circuit for the computation of the so-called +3n+1 numbers. The CTL formula checks that all trajectories that do not +overflow end up in the cycle 4-2-1. + +This model uses 26-bit numbers and model checking takes substantial time +(about 3 hours on a 200MHz P6). Index: vis_dev/vis-2.1/examples/rcnum/check_result =================================================================== --- vis_dev/vis-2.1/examples/rcnum/check_result (revision 11) +++ vis_dev/vis-2.1/examples/rcnum/check_result (revision 11) @@ -0,0 +1,1 @@ +# MC: formula passed --- AF(((((((((((((((((((((((numOut<24>=0 * numOut<23>=0) * numOut<22>=0) * numOut<21>=0) * numOut<20>=0) * numOut<19>=0) * numOut<18>=0) * numOut<17>=0) * numOut<16>=0) * numOut<15>=0) * numOut<14>=0) * numOut<13>=0) * numOut<12>=0) * numOut<11>=0) * numOut<10>=0) * numOut<9>=0) * numOut<8>=0) * numOut<7>=0) * numOut<6>=0) * numOut<5>=0) * numOut<4>=0) * numOut<3>=0) * (numOut<1>=0 * numOut<0>=0))) Index: vis_dev/vis-2.1/examples/rcnum/check_script =================================================================== --- vis_dev/vis-2.1/examples/rcnum/check_script (revision 11) +++ vis_dev/vis-2.1/examples/rcnum/check_script (revision 11) @@ -0,0 +1,6 @@ +read_blif_mv rcnum25.mv +flatten_hierarchy +static_order +build_partition_mdds +model_check rcnum25.ctl +quit -s Index: vis_dev/vis-2.1/examples/rcnum/rcnum.v =================================================================== --- vis_dev/vis-2.1/examples/rcnum/rcnum.v (revision 11) +++ vis_dev/vis-2.1/examples/rcnum/rcnum.v (revision 11) @@ -0,0 +1,66 @@ +// This Verilog module describes a simple finite state machine for +// the computation of the so-called rollercoaster numbers. +// Given an initial number n[0] > 0, the rollercoaster number +// sequence (n[i]) starting at n[0] is given by these rules: +// if n[i] is even, n[i+1] = n[i]/2; +// if n[i] is odd, n[i+1] = n[i]*3+1. +// The sequences for most (small) numbers eventually reach the +// cycle (4,2,1). +// This finite state machine has a state register storing n[i]. +// Since the register is finite, only a few positive integers can +// be represented. Therefore 0 is used as trap state to indicate +// overflow. +// +// This description intentionally avoids the use of '*' and '/'. +// +// Author: Fabio Somenzi + + +module rollercoasterNumbers(clock,numOut); + input clock; + output [24:0] numOut; + reg [24:0] numOut; + + wire [24+2:0] tmp; + + initial begin + numOut[0] = $ND(0,1); + numOut[1] = $ND(0,1); + numOut[2] = $ND(0,1); + numOut[3] = $ND(0,1); + numOut[4] = $ND(0,1); + numOut[5] = $ND(0,1); + numOut[6] = $ND(0,1); + numOut[7] = $ND(0,1); + numOut[8] = $ND(0,1); + numOut[9] = $ND(0,1); + numOut[10] = $ND(0,1); + numOut[11] = $ND(0,1); + numOut[12] = $ND(0,1); + numOut[13] = $ND(0,1); + numOut[14] = $ND(0,1); + numOut[15] = $ND(0,1); + numOut[16] = $ND(0,1); + numOut[17] = $ND(0,1); + numOut[18] = $ND(0,1); + numOut[19] = $ND(0,1); + numOut[20] = $ND(0,1); + numOut[21] = $ND(0,1); + numOut[22] = $ND(0,1); + numOut[23] = $ND(0,1); + numOut[24] = $ND(0,1); + end + + // Compute n[i] * 3 + 1. + assign tmp = {2'b0,numOut} + {1'b0,numOut,1'b1}; + + always @ (posedge clock) + if (numOut[0]) begin + // Check overflow. + numOut = (tmp[24+2] | tmp[24+1]) ? 0 : tmp[24:0]; + end else begin + // Divide by 2. + numOut = {1'b0,numOut[24:1]}; + end + +endmodule // rollercoasterNumbers Index: vis_dev/vis-2.1/examples/rcnum/rcnum25.ctl =================================================================== --- vis_dev/vis-2.1/examples/rcnum/rcnum25.ctl (revision 11) +++ vis_dev/vis-2.1/examples/rcnum/rcnum25.ctl (revision 11) @@ -0,0 +1,5 @@ +#PASS: eventually either 4 or 0 is reached. +AF( + (numOut[24:3] = 0) * + (numOut[1:0] = 0) +); Index: vis_dev/vis-2.1/examples/rcnum/rcnum25.mv =================================================================== --- vis_dev/vis-2.1/examples/rcnum/rcnum25.mv (revision 11) +++ vis_dev/vis-2.1/examples/rcnum/rcnum25.mv (revision 11) @@ -0,0 +1,2522 @@ +# /projects/distribution/vl2mv/ix86/bin/vl2mv rcnum.v +# version: 0.2 +# date: 11:56:20 02/22/97 (MST) +.model rollercoasterNumbers +# I/O ports +.outputs numOut<0> numOut<1> numOut<2> numOut<3> numOut<4> numOut<5> numOut<6> numOut<7> numOut<8> numOut<9> numOut<10> numOut<11> numOut<12> numOut<13> numOut<14> numOut<15> numOut<16> numOut<17> numOut<18> numOut<19> numOut<20> numOut<21> numOut<22> numOut<23> numOut<24> +# numOut [0] = $NDset ( 0,1 ) +.names -> numOut$raw_n0$initial$_n1<0> +0 +1 +.names numOut$raw_n0$initial$_n1<0> numOut$raw_n0<0> +- =numOut$raw_n0$initial$_n1<0> +.names numOut<1> numOut$raw_n0<1> +- =numOut<1> +.names numOut<2> numOut$raw_n0<2> +- =numOut<2> +.names numOut<3> numOut$raw_n0<3> +- =numOut<3> +.names numOut<4> numOut$raw_n0<4> +- =numOut<4> +.names numOut<5> numOut$raw_n0<5> +- =numOut<5> +.names numOut<6> numOut$raw_n0<6> +- =numOut<6> +.names numOut<7> numOut$raw_n0<7> +- =numOut<7> +.names numOut<8> numOut$raw_n0<8> +- =numOut<8> +.names numOut<9> numOut$raw_n0<9> +- =numOut<9> +.names numOut<10> numOut$raw_n0<10> +- =numOut<10> +.names numOut<11> numOut$raw_n0<11> +- =numOut<11> +.names numOut<12> numOut$raw_n0<12> +- =numOut<12> +.names numOut<13> numOut$raw_n0<13> +- =numOut<13> +.names numOut<14> numOut$raw_n0<14> +- =numOut<14> +.names numOut<15> numOut$raw_n0<15> +- =numOut<15> +.names numOut<16> numOut$raw_n0<16> +- =numOut<16> +.names numOut<17> numOut$raw_n0<17> +- =numOut<17> +.names numOut<18> numOut$raw_n0<18> +- =numOut<18> +.names numOut<19> numOut$raw_n0<19> +- =numOut<19> +.names numOut<20> numOut$raw_n0<20> +- =numOut<20> +.names numOut<21> numOut$raw_n0<21> +- =numOut<21> +.names numOut<22> numOut$raw_n0<22> +- =numOut<22> +.names numOut<23> numOut$raw_n0<23> +- =numOut<23> +.names numOut<24> numOut$raw_n0<24> +- =numOut<24> +# numOut [1] = $NDset ( 0,1 ) +.names -> numOut$raw_n2$initial$_n3<1> +0 +1 +.names numOut$raw_n2$initial$_n3<1> numOut$raw_n2<1> +- =numOut$raw_n2$initial$_n3<1> +.names numOut$raw_n0<0> numOut$raw_n2<0> +- =numOut$raw_n0<0> +.names numOut$raw_n0<2> numOut$raw_n2<2> +- =numOut$raw_n0<2> +.names numOut$raw_n0<3> numOut$raw_n2<3> +- =numOut$raw_n0<3> +.names numOut$raw_n0<4> numOut$raw_n2<4> +- =numOut$raw_n0<4> +.names numOut$raw_n0<5> numOut$raw_n2<5> +- =numOut$raw_n0<5> +.names numOut$raw_n0<6> numOut$raw_n2<6> +- =numOut$raw_n0<6> +.names numOut$raw_n0<7> numOut$raw_n2<7> +- =numOut$raw_n0<7> +.names numOut$raw_n0<8> numOut$raw_n2<8> +- =numOut$raw_n0<8> +.names numOut$raw_n0<9> numOut$raw_n2<9> +- =numOut$raw_n0<9> +.names numOut$raw_n0<10> numOut$raw_n2<10> +- =numOut$raw_n0<10> +.names numOut$raw_n0<11> numOut$raw_n2<11> +- =numOut$raw_n0<11> +.names numOut$raw_n0<12> numOut$raw_n2<12> +- =numOut$raw_n0<12> +.names numOut$raw_n0<13> numOut$raw_n2<13> +- =numOut$raw_n0<13> +.names numOut$raw_n0<14> numOut$raw_n2<14> +- =numOut$raw_n0<14> +.names numOut$raw_n0<15> numOut$raw_n2<15> +- =numOut$raw_n0<15> +.names numOut$raw_n0<16> numOut$raw_n2<16> +- =numOut$raw_n0<16> +.names numOut$raw_n0<17> numOut$raw_n2<17> +- =numOut$raw_n0<17> +.names numOut$raw_n0<18> numOut$raw_n2<18> +- =numOut$raw_n0<18> +.names numOut$raw_n0<19> numOut$raw_n2<19> +- =numOut$raw_n0<19> +.names numOut$raw_n0<20> numOut$raw_n2<20> +- =numOut$raw_n0<20> +.names numOut$raw_n0<21> numOut$raw_n2<21> +- =numOut$raw_n0<21> +.names numOut$raw_n0<22> numOut$raw_n2<22> +- =numOut$raw_n0<22> +.names numOut$raw_n0<23> numOut$raw_n2<23> +- =numOut$raw_n0<23> +.names numOut$raw_n0<24> numOut$raw_n2<24> +- =numOut$raw_n0<24> +# numOut [2] = $NDset ( 0,1 ) +.names -> numOut$raw_n4$initial$_n5<2> +0 +1 +.names numOut$raw_n4$initial$_n5<2> numOut$raw_n4<2> +- =numOut$raw_n4$initial$_n5<2> +.names numOut$raw_n2<0> numOut$raw_n4<0> +- =numOut$raw_n2<0> +.names numOut$raw_n2<1> numOut$raw_n4<1> +- =numOut$raw_n2<1> +.names numOut$raw_n2<3> numOut$raw_n4<3> +- =numOut$raw_n2<3> +.names numOut$raw_n2<4> numOut$raw_n4<4> +- =numOut$raw_n2<4> +.names numOut$raw_n2<5> numOut$raw_n4<5> +- =numOut$raw_n2<5> +.names numOut$raw_n2<6> numOut$raw_n4<6> +- =numOut$raw_n2<6> +.names numOut$raw_n2<7> numOut$raw_n4<7> +- =numOut$raw_n2<7> +.names numOut$raw_n2<8> numOut$raw_n4<8> +- =numOut$raw_n2<8> +.names numOut$raw_n2<9> numOut$raw_n4<9> +- =numOut$raw_n2<9> +.names numOut$raw_n2<10> numOut$raw_n4<10> +- =numOut$raw_n2<10> +.names numOut$raw_n2<11> numOut$raw_n4<11> +- =numOut$raw_n2<11> +.names numOut$raw_n2<12> numOut$raw_n4<12> +- =numOut$raw_n2<12> +.names numOut$raw_n2<13> numOut$raw_n4<13> +- =numOut$raw_n2<13> +.names numOut$raw_n2<14> numOut$raw_n4<14> +- =numOut$raw_n2<14> +.names numOut$raw_n2<15> numOut$raw_n4<15> +- =numOut$raw_n2<15> +.names numOut$raw_n2<16> numOut$raw_n4<16> +- =numOut$raw_n2<16> +.names numOut$raw_n2<17> numOut$raw_n4<17> +- =numOut$raw_n2<17> +.names numOut$raw_n2<18> numOut$raw_n4<18> +- =numOut$raw_n2<18> +.names numOut$raw_n2<19> numOut$raw_n4<19> +- =numOut$raw_n2<19> +.names numOut$raw_n2<20> numOut$raw_n4<20> +- =numOut$raw_n2<20> +.names numOut$raw_n2<21> numOut$raw_n4<21> +- =numOut$raw_n2<21> +.names numOut$raw_n2<22> numOut$raw_n4<22> +- =numOut$raw_n2<22> +.names numOut$raw_n2<23> numOut$raw_n4<23> +- =numOut$raw_n2<23> +.names numOut$raw_n2<24> numOut$raw_n4<24> +- =numOut$raw_n2<24> +# numOut [3] = $NDset ( 0,1 ) +.names -> numOut$raw_n6$initial$_n7<3> +0 +1 +.names numOut$raw_n6$initial$_n7<3> numOut$raw_n6<3> +- =numOut$raw_n6$initial$_n7<3> +.names numOut$raw_n4<0> numOut$raw_n6<0> +- =numOut$raw_n4<0> +.names numOut$raw_n4<1> numOut$raw_n6<1> +- =numOut$raw_n4<1> +.names numOut$raw_n4<2> numOut$raw_n6<2> +- =numOut$raw_n4<2> +.names numOut$raw_n4<4> numOut$raw_n6<4> +- =numOut$raw_n4<4> +.names numOut$raw_n4<5> numOut$raw_n6<5> +- =numOut$raw_n4<5> +.names numOut$raw_n4<6> numOut$raw_n6<6> +- =numOut$raw_n4<6> +.names numOut$raw_n4<7> numOut$raw_n6<7> +- =numOut$raw_n4<7> +.names numOut$raw_n4<8> numOut$raw_n6<8> +- =numOut$raw_n4<8> +.names numOut$raw_n4<9> numOut$raw_n6<9> +- =numOut$raw_n4<9> +.names numOut$raw_n4<10> numOut$raw_n6<10> +- =numOut$raw_n4<10> +.names numOut$raw_n4<11> numOut$raw_n6<11> +- =numOut$raw_n4<11> +.names numOut$raw_n4<12> numOut$raw_n6<12> +- =numOut$raw_n4<12> +.names numOut$raw_n4<13> numOut$raw_n6<13> +- =numOut$raw_n4<13> +.names numOut$raw_n4<14> numOut$raw_n6<14> +- =numOut$raw_n4<14> +.names numOut$raw_n4<15> numOut$raw_n6<15> +- =numOut$raw_n4<15> +.names numOut$raw_n4<16> numOut$raw_n6<16> +- =numOut$raw_n4<16> +.names numOut$raw_n4<17> numOut$raw_n6<17> +- =numOut$raw_n4<17> +.names numOut$raw_n4<18> numOut$raw_n6<18> +- =numOut$raw_n4<18> +.names numOut$raw_n4<19> numOut$raw_n6<19> +- =numOut$raw_n4<19> +.names numOut$raw_n4<20> numOut$raw_n6<20> +- =numOut$raw_n4<20> +.names numOut$raw_n4<21> numOut$raw_n6<21> +- =numOut$raw_n4<21> +.names numOut$raw_n4<22> numOut$raw_n6<22> +- =numOut$raw_n4<22> +.names numOut$raw_n4<23> numOut$raw_n6<23> +- =numOut$raw_n4<23> +.names numOut$raw_n4<24> numOut$raw_n6<24> +- =numOut$raw_n4<24> +# numOut [4] = $NDset ( 0,1 ) +.names -> numOut$raw_n8$initial$_n9<4> +0 +1 +.names numOut$raw_n8$initial$_n9<4> numOut$raw_n8<4> +- =numOut$raw_n8$initial$_n9<4> +.names numOut$raw_n6<0> numOut$raw_n8<0> +- =numOut$raw_n6<0> +.names numOut$raw_n6<1> numOut$raw_n8<1> +- =numOut$raw_n6<1> +.names numOut$raw_n6<2> numOut$raw_n8<2> +- =numOut$raw_n6<2> +.names numOut$raw_n6<3> numOut$raw_n8<3> +- =numOut$raw_n6<3> +.names numOut$raw_n6<5> numOut$raw_n8<5> +- =numOut$raw_n6<5> +.names numOut$raw_n6<6> numOut$raw_n8<6> +- =numOut$raw_n6<6> +.names numOut$raw_n6<7> numOut$raw_n8<7> +- =numOut$raw_n6<7> +.names numOut$raw_n6<8> numOut$raw_n8<8> +- =numOut$raw_n6<8> +.names numOut$raw_n6<9> numOut$raw_n8<9> +- =numOut$raw_n6<9> +.names numOut$raw_n6<10> numOut$raw_n8<10> +- =numOut$raw_n6<10> +.names numOut$raw_n6<11> numOut$raw_n8<11> +- =numOut$raw_n6<11> +.names numOut$raw_n6<12> numOut$raw_n8<12> +- =numOut$raw_n6<12> +.names numOut$raw_n6<13> numOut$raw_n8<13> +- =numOut$raw_n6<13> +.names numOut$raw_n6<14> numOut$raw_n8<14> +- =numOut$raw_n6<14> +.names numOut$raw_n6<15> numOut$raw_n8<15> +- =numOut$raw_n6<15> +.names numOut$raw_n6<16> numOut$raw_n8<16> +- =numOut$raw_n6<16> +.names numOut$raw_n6<17> numOut$raw_n8<17> +- =numOut$raw_n6<17> +.names numOut$raw_n6<18> numOut$raw_n8<18> +- =numOut$raw_n6<18> +.names numOut$raw_n6<19> numOut$raw_n8<19> +- =numOut$raw_n6<19> +.names numOut$raw_n6<20> numOut$raw_n8<20> +- =numOut$raw_n6<20> +.names numOut$raw_n6<21> numOut$raw_n8<21> +- =numOut$raw_n6<21> +.names numOut$raw_n6<22> numOut$raw_n8<22> +- =numOut$raw_n6<22> +.names numOut$raw_n6<23> numOut$raw_n8<23> +- =numOut$raw_n6<23> +.names numOut$raw_n6<24> numOut$raw_n8<24> +- =numOut$raw_n6<24> +# numOut [5] = $NDset ( 0,1 ) +.names -> numOut$raw_na$initial$_nb<5> +0 +1 +.names numOut$raw_na$initial$_nb<5> numOut$raw_na<5> +- =numOut$raw_na$initial$_nb<5> +.names numOut$raw_n8<0> numOut$raw_na<0> +- =numOut$raw_n8<0> +.names numOut$raw_n8<1> numOut$raw_na<1> +- =numOut$raw_n8<1> +.names numOut$raw_n8<2> numOut$raw_na<2> +- =numOut$raw_n8<2> +.names numOut$raw_n8<3> numOut$raw_na<3> +- =numOut$raw_n8<3> +.names numOut$raw_n8<4> numOut$raw_na<4> +- =numOut$raw_n8<4> +.names numOut$raw_n8<6> numOut$raw_na<6> +- =numOut$raw_n8<6> +.names numOut$raw_n8<7> numOut$raw_na<7> +- =numOut$raw_n8<7> +.names numOut$raw_n8<8> numOut$raw_na<8> +- =numOut$raw_n8<8> +.names numOut$raw_n8<9> numOut$raw_na<9> +- =numOut$raw_n8<9> +.names numOut$raw_n8<10> numOut$raw_na<10> +- =numOut$raw_n8<10> +.names numOut$raw_n8<11> numOut$raw_na<11> +- =numOut$raw_n8<11> +.names numOut$raw_n8<12> numOut$raw_na<12> +- =numOut$raw_n8<12> +.names numOut$raw_n8<13> numOut$raw_na<13> +- =numOut$raw_n8<13> +.names numOut$raw_n8<14> numOut$raw_na<14> +- =numOut$raw_n8<14> +.names numOut$raw_n8<15> numOut$raw_na<15> +- =numOut$raw_n8<15> +.names numOut$raw_n8<16> numOut$raw_na<16> +- =numOut$raw_n8<16> +.names numOut$raw_n8<17> numOut$raw_na<17> +- =numOut$raw_n8<17> +.names numOut$raw_n8<18> numOut$raw_na<18> +- =numOut$raw_n8<18> +.names numOut$raw_n8<19> numOut$raw_na<19> +- =numOut$raw_n8<19> +.names numOut$raw_n8<20> numOut$raw_na<20> +- =numOut$raw_n8<20> +.names numOut$raw_n8<21> numOut$raw_na<21> +- =numOut$raw_n8<21> +.names numOut$raw_n8<22> numOut$raw_na<22> +- =numOut$raw_n8<22> +.names numOut$raw_n8<23> numOut$raw_na<23> +- =numOut$raw_n8<23> +.names numOut$raw_n8<24> numOut$raw_na<24> +- =numOut$raw_n8<24> +# numOut [6] = $NDset ( 0,1 ) +.names -> numOut$raw_nc$initial$_nd<6> +0 +1 +.names numOut$raw_nc$initial$_nd<6> numOut$raw_nc<6> +- =numOut$raw_nc$initial$_nd<6> +.names numOut$raw_na<0> numOut$raw_nc<0> +- =numOut$raw_na<0> +.names numOut$raw_na<1> numOut$raw_nc<1> +- =numOut$raw_na<1> +.names numOut$raw_na<2> numOut$raw_nc<2> +- =numOut$raw_na<2> +.names numOut$raw_na<3> numOut$raw_nc<3> +- =numOut$raw_na<3> +.names numOut$raw_na<4> numOut$raw_nc<4> +- =numOut$raw_na<4> +.names numOut$raw_na<5> numOut$raw_nc<5> +- =numOut$raw_na<5> +.names numOut$raw_na<7> numOut$raw_nc<7> +- =numOut$raw_na<7> +.names numOut$raw_na<8> numOut$raw_nc<8> +- =numOut$raw_na<8> +.names numOut$raw_na<9> numOut$raw_nc<9> +- =numOut$raw_na<9> +.names numOut$raw_na<10> numOut$raw_nc<10> +- =numOut$raw_na<10> +.names numOut$raw_na<11> numOut$raw_nc<11> +- =numOut$raw_na<11> +.names numOut$raw_na<12> numOut$raw_nc<12> +- =numOut$raw_na<12> +.names numOut$raw_na<13> numOut$raw_nc<13> +- =numOut$raw_na<13> +.names numOut$raw_na<14> numOut$raw_nc<14> +- =numOut$raw_na<14> +.names numOut$raw_na<15> numOut$raw_nc<15> +- =numOut$raw_na<15> +.names numOut$raw_na<16> numOut$raw_nc<16> +- =numOut$raw_na<16> +.names numOut$raw_na<17> numOut$raw_nc<17> +- =numOut$raw_na<17> +.names numOut$raw_na<18> numOut$raw_nc<18> +- =numOut$raw_na<18> +.names numOut$raw_na<19> numOut$raw_nc<19> +- =numOut$raw_na<19> +.names numOut$raw_na<20> numOut$raw_nc<20> +- =numOut$raw_na<20> +.names numOut$raw_na<21> numOut$raw_nc<21> +- =numOut$raw_na<21> +.names numOut$raw_na<22> numOut$raw_nc<22> +- =numOut$raw_na<22> +.names numOut$raw_na<23> numOut$raw_nc<23> +- =numOut$raw_na<23> +.names numOut$raw_na<24> numOut$raw_nc<24> +- =numOut$raw_na<24> +# numOut [7] = $NDset ( 0,1 ) +.names -> numOut$raw_ne$initial$_nf<7> +0 +1 +.names numOut$raw_ne$initial$_nf<7> numOut$raw_ne<7> +- =numOut$raw_ne$initial$_nf<7> +.names numOut$raw_nc<0> numOut$raw_ne<0> +- =numOut$raw_nc<0> +.names numOut$raw_nc<1> numOut$raw_ne<1> +- =numOut$raw_nc<1> +.names numOut$raw_nc<2> numOut$raw_ne<2> +- =numOut$raw_nc<2> +.names numOut$raw_nc<3> numOut$raw_ne<3> +- =numOut$raw_nc<3> +.names numOut$raw_nc<4> numOut$raw_ne<4> +- =numOut$raw_nc<4> +.names numOut$raw_nc<5> numOut$raw_ne<5> +- =numOut$raw_nc<5> +.names numOut$raw_nc<6> numOut$raw_ne<6> +- =numOut$raw_nc<6> +.names numOut$raw_nc<8> numOut$raw_ne<8> +- =numOut$raw_nc<8> +.names numOut$raw_nc<9> numOut$raw_ne<9> +- =numOut$raw_nc<9> +.names numOut$raw_nc<10> numOut$raw_ne<10> +- =numOut$raw_nc<10> +.names numOut$raw_nc<11> numOut$raw_ne<11> +- =numOut$raw_nc<11> +.names numOut$raw_nc<12> numOut$raw_ne<12> +- =numOut$raw_nc<12> +.names numOut$raw_nc<13> numOut$raw_ne<13> +- =numOut$raw_nc<13> +.names numOut$raw_nc<14> numOut$raw_ne<14> +- =numOut$raw_nc<14> +.names numOut$raw_nc<15> numOut$raw_ne<15> +- =numOut$raw_nc<15> +.names numOut$raw_nc<16> numOut$raw_ne<16> +- =numOut$raw_nc<16> +.names numOut$raw_nc<17> numOut$raw_ne<17> +- =numOut$raw_nc<17> +.names numOut$raw_nc<18> numOut$raw_ne<18> +- =numOut$raw_nc<18> +.names numOut$raw_nc<19> numOut$raw_ne<19> +- =numOut$raw_nc<19> +.names numOut$raw_nc<20> numOut$raw_ne<20> +- =numOut$raw_nc<20> +.names numOut$raw_nc<21> numOut$raw_ne<21> +- =numOut$raw_nc<21> +.names numOut$raw_nc<22> numOut$raw_ne<22> +- =numOut$raw_nc<22> +.names numOut$raw_nc<23> numOut$raw_ne<23> +- =numOut$raw_nc<23> +.names numOut$raw_nc<24> numOut$raw_ne<24> +- =numOut$raw_nc<24> +# numOut [8] = $NDset ( 0,1 ) +.names -> numOut$raw_n10$initial$_n11<8> +0 +1 +.names numOut$raw_n10$initial$_n11<8> numOut$raw_n10<8> +- =numOut$raw_n10$initial$_n11<8> +.names numOut$raw_ne<0> numOut$raw_n10<0> +- =numOut$raw_ne<0> +.names numOut$raw_ne<1> numOut$raw_n10<1> +- =numOut$raw_ne<1> +.names numOut$raw_ne<2> numOut$raw_n10<2> +- =numOut$raw_ne<2> +.names numOut$raw_ne<3> numOut$raw_n10<3> +- =numOut$raw_ne<3> +.names numOut$raw_ne<4> numOut$raw_n10<4> +- =numOut$raw_ne<4> +.names numOut$raw_ne<5> numOut$raw_n10<5> +- =numOut$raw_ne<5> +.names numOut$raw_ne<6> numOut$raw_n10<6> +- =numOut$raw_ne<6> +.names numOut$raw_ne<7> numOut$raw_n10<7> +- =numOut$raw_ne<7> +.names numOut$raw_ne<9> numOut$raw_n10<9> +- =numOut$raw_ne<9> +.names numOut$raw_ne<10> numOut$raw_n10<10> +- =numOut$raw_ne<10> +.names numOut$raw_ne<11> numOut$raw_n10<11> +- =numOut$raw_ne<11> +.names numOut$raw_ne<12> numOut$raw_n10<12> +- =numOut$raw_ne<12> +.names numOut$raw_ne<13> numOut$raw_n10<13> +- =numOut$raw_ne<13> +.names numOut$raw_ne<14> numOut$raw_n10<14> +- =numOut$raw_ne<14> +.names numOut$raw_ne<15> numOut$raw_n10<15> +- =numOut$raw_ne<15> +.names numOut$raw_ne<16> numOut$raw_n10<16> +- =numOut$raw_ne<16> +.names numOut$raw_ne<17> numOut$raw_n10<17> +- =numOut$raw_ne<17> +.names numOut$raw_ne<18> numOut$raw_n10<18> +- =numOut$raw_ne<18> +.names numOut$raw_ne<19> numOut$raw_n10<19> +- =numOut$raw_ne<19> +.names numOut$raw_ne<20> numOut$raw_n10<20> +- =numOut$raw_ne<20> +.names numOut$raw_ne<21> numOut$raw_n10<21> +- =numOut$raw_ne<21> +.names numOut$raw_ne<22> numOut$raw_n10<22> +- =numOut$raw_ne<22> +.names numOut$raw_ne<23> numOut$raw_n10<23> +- =numOut$raw_ne<23> +.names numOut$raw_ne<24> numOut$raw_n10<24> +- =numOut$raw_ne<24> +# numOut [9] = $NDset ( 0,1 ) +.names -> numOut$raw_n12$initial$_n13<9> +0 +1 +.names numOut$raw_n12$initial$_n13<9> numOut$raw_n12<9> +- =numOut$raw_n12$initial$_n13<9> +.names numOut$raw_n10<0> numOut$raw_n12<0> +- =numOut$raw_n10<0> +.names numOut$raw_n10<1> numOut$raw_n12<1> +- =numOut$raw_n10<1> +.names numOut$raw_n10<2> numOut$raw_n12<2> +- =numOut$raw_n10<2> +.names numOut$raw_n10<3> numOut$raw_n12<3> +- =numOut$raw_n10<3> +.names numOut$raw_n10<4> numOut$raw_n12<4> +- =numOut$raw_n10<4> +.names numOut$raw_n10<5> numOut$raw_n12<5> +- =numOut$raw_n10<5> +.names numOut$raw_n10<6> numOut$raw_n12<6> +- =numOut$raw_n10<6> +.names numOut$raw_n10<7> numOut$raw_n12<7> +- =numOut$raw_n10<7> +.names numOut$raw_n10<8> numOut$raw_n12<8> +- =numOut$raw_n10<8> +.names numOut$raw_n10<10> numOut$raw_n12<10> +- =numOut$raw_n10<10> +.names numOut$raw_n10<11> numOut$raw_n12<11> +- =numOut$raw_n10<11> +.names numOut$raw_n10<12> numOut$raw_n12<12> +- =numOut$raw_n10<12> +.names numOut$raw_n10<13> numOut$raw_n12<13> +- =numOut$raw_n10<13> +.names numOut$raw_n10<14> numOut$raw_n12<14> +- =numOut$raw_n10<14> +.names numOut$raw_n10<15> numOut$raw_n12<15> +- =numOut$raw_n10<15> +.names numOut$raw_n10<16> numOut$raw_n12<16> +- =numOut$raw_n10<16> +.names numOut$raw_n10<17> numOut$raw_n12<17> +- =numOut$raw_n10<17> +.names numOut$raw_n10<18> numOut$raw_n12<18> +- =numOut$raw_n10<18> +.names numOut$raw_n10<19> numOut$raw_n12<19> +- =numOut$raw_n10<19> +.names numOut$raw_n10<20> numOut$raw_n12<20> +- =numOut$raw_n10<20> +.names numOut$raw_n10<21> numOut$raw_n12<21> +- =numOut$raw_n10<21> +.names numOut$raw_n10<22> numOut$raw_n12<22> +- =numOut$raw_n10<22> +.names numOut$raw_n10<23> numOut$raw_n12<23> +- =numOut$raw_n10<23> +.names numOut$raw_n10<24> numOut$raw_n12<24> +- =numOut$raw_n10<24> +# numOut [10] = $NDset ( 0,1 ) +.names -> numOut$raw_n14$initial$_n15<10> +0 +1 +.names numOut$raw_n14$initial$_n15<10> numOut$raw_n14<10> +- =numOut$raw_n14$initial$_n15<10> +.names numOut$raw_n12<0> numOut$raw_n14<0> +- =numOut$raw_n12<0> +.names numOut$raw_n12<1> numOut$raw_n14<1> +- =numOut$raw_n12<1> +.names numOut$raw_n12<2> numOut$raw_n14<2> +- =numOut$raw_n12<2> +.names numOut$raw_n12<3> numOut$raw_n14<3> +- =numOut$raw_n12<3> +.names numOut$raw_n12<4> numOut$raw_n14<4> +- =numOut$raw_n12<4> +.names numOut$raw_n12<5> numOut$raw_n14<5> +- =numOut$raw_n12<5> +.names numOut$raw_n12<6> numOut$raw_n14<6> +- =numOut$raw_n12<6> +.names numOut$raw_n12<7> numOut$raw_n14<7> +- =numOut$raw_n12<7> +.names numOut$raw_n12<8> numOut$raw_n14<8> +- =numOut$raw_n12<8> +.names numOut$raw_n12<9> numOut$raw_n14<9> +- =numOut$raw_n12<9> +.names numOut$raw_n12<11> numOut$raw_n14<11> +- =numOut$raw_n12<11> +.names numOut$raw_n12<12> numOut$raw_n14<12> +- =numOut$raw_n12<12> +.names numOut$raw_n12<13> numOut$raw_n14<13> +- =numOut$raw_n12<13> +.names numOut$raw_n12<14> numOut$raw_n14<14> +- =numOut$raw_n12<14> +.names numOut$raw_n12<15> numOut$raw_n14<15> +- =numOut$raw_n12<15> +.names numOut$raw_n12<16> numOut$raw_n14<16> +- =numOut$raw_n12<16> +.names numOut$raw_n12<17> numOut$raw_n14<17> +- =numOut$raw_n12<17> +.names numOut$raw_n12<18> numOut$raw_n14<18> +- =numOut$raw_n12<18> +.names numOut$raw_n12<19> numOut$raw_n14<19> +- =numOut$raw_n12<19> +.names numOut$raw_n12<20> numOut$raw_n14<20> +- =numOut$raw_n12<20> +.names numOut$raw_n12<21> numOut$raw_n14<21> +- =numOut$raw_n12<21> +.names numOut$raw_n12<22> numOut$raw_n14<22> +- =numOut$raw_n12<22> +.names numOut$raw_n12<23> numOut$raw_n14<23> +- =numOut$raw_n12<23> +.names numOut$raw_n12<24> numOut$raw_n14<24> +- =numOut$raw_n12<24> +# numOut [11] = $NDset ( 0,1 ) +.names -> numOut$raw_n16$initial$_n17<11> +0 +1 +.names numOut$raw_n16$initial$_n17<11> numOut$raw_n16<11> +- =numOut$raw_n16$initial$_n17<11> +.names numOut$raw_n14<0> numOut$raw_n16<0> +- =numOut$raw_n14<0> +.names numOut$raw_n14<1> numOut$raw_n16<1> +- =numOut$raw_n14<1> +.names numOut$raw_n14<2> numOut$raw_n16<2> +- =numOut$raw_n14<2> +.names numOut$raw_n14<3> numOut$raw_n16<3> +- =numOut$raw_n14<3> +.names numOut$raw_n14<4> numOut$raw_n16<4> +- =numOut$raw_n14<4> +.names numOut$raw_n14<5> numOut$raw_n16<5> +- =numOut$raw_n14<5> +.names numOut$raw_n14<6> numOut$raw_n16<6> +- =numOut$raw_n14<6> +.names numOut$raw_n14<7> numOut$raw_n16<7> +- =numOut$raw_n14<7> +.names numOut$raw_n14<8> numOut$raw_n16<8> +- =numOut$raw_n14<8> +.names numOut$raw_n14<9> numOut$raw_n16<9> +- =numOut$raw_n14<9> +.names numOut$raw_n14<10> numOut$raw_n16<10> +- =numOut$raw_n14<10> +.names numOut$raw_n14<12> numOut$raw_n16<12> +- =numOut$raw_n14<12> +.names numOut$raw_n14<13> numOut$raw_n16<13> +- =numOut$raw_n14<13> +.names numOut$raw_n14<14> numOut$raw_n16<14> +- =numOut$raw_n14<14> +.names numOut$raw_n14<15> numOut$raw_n16<15> +- =numOut$raw_n14<15> +.names numOut$raw_n14<16> numOut$raw_n16<16> +- =numOut$raw_n14<16> +.names numOut$raw_n14<17> numOut$raw_n16<17> +- =numOut$raw_n14<17> +.names numOut$raw_n14<18> numOut$raw_n16<18> +- =numOut$raw_n14<18> +.names numOut$raw_n14<19> numOut$raw_n16<19> +- =numOut$raw_n14<19> +.names numOut$raw_n14<20> numOut$raw_n16<20> +- =numOut$raw_n14<20> +.names numOut$raw_n14<21> numOut$raw_n16<21> +- =numOut$raw_n14<21> +.names numOut$raw_n14<22> numOut$raw_n16<22> +- =numOut$raw_n14<22> +.names numOut$raw_n14<23> numOut$raw_n16<23> +- =numOut$raw_n14<23> +.names numOut$raw_n14<24> numOut$raw_n16<24> +- =numOut$raw_n14<24> +# numOut [12] = $NDset ( 0,1 ) +.names -> numOut$raw_n18$initial$_n19<12> +0 +1 +.names numOut$raw_n18$initial$_n19<12> numOut$raw_n18<12> +- =numOut$raw_n18$initial$_n19<12> +.names numOut$raw_n16<0> numOut$raw_n18<0> +- =numOut$raw_n16<0> +.names numOut$raw_n16<1> numOut$raw_n18<1> +- =numOut$raw_n16<1> +.names numOut$raw_n16<2> numOut$raw_n18<2> +- =numOut$raw_n16<2> +.names numOut$raw_n16<3> numOut$raw_n18<3> +- =numOut$raw_n16<3> +.names numOut$raw_n16<4> numOut$raw_n18<4> +- =numOut$raw_n16<4> +.names numOut$raw_n16<5> numOut$raw_n18<5> +- =numOut$raw_n16<5> +.names numOut$raw_n16<6> numOut$raw_n18<6> +- =numOut$raw_n16<6> +.names numOut$raw_n16<7> numOut$raw_n18<7> +- =numOut$raw_n16<7> +.names numOut$raw_n16<8> numOut$raw_n18<8> +- =numOut$raw_n16<8> +.names numOut$raw_n16<9> numOut$raw_n18<9> +- =numOut$raw_n16<9> +.names numOut$raw_n16<10> numOut$raw_n18<10> +- =numOut$raw_n16<10> +.names numOut$raw_n16<11> numOut$raw_n18<11> +- =numOut$raw_n16<11> +.names numOut$raw_n16<13> numOut$raw_n18<13> +- =numOut$raw_n16<13> +.names numOut$raw_n16<14> numOut$raw_n18<14> +- =numOut$raw_n16<14> +.names numOut$raw_n16<15> numOut$raw_n18<15> +- =numOut$raw_n16<15> +.names numOut$raw_n16<16> numOut$raw_n18<16> +- =numOut$raw_n16<16> +.names numOut$raw_n16<17> numOut$raw_n18<17> +- =numOut$raw_n16<17> +.names numOut$raw_n16<18> numOut$raw_n18<18> +- =numOut$raw_n16<18> +.names numOut$raw_n16<19> numOut$raw_n18<19> +- =numOut$raw_n16<19> +.names numOut$raw_n16<20> numOut$raw_n18<20> +- =numOut$raw_n16<20> +.names numOut$raw_n16<21> numOut$raw_n18<21> +- =numOut$raw_n16<21> +.names numOut$raw_n16<22> numOut$raw_n18<22> +- =numOut$raw_n16<22> +.names numOut$raw_n16<23> numOut$raw_n18<23> +- =numOut$raw_n16<23> +.names numOut$raw_n16<24> numOut$raw_n18<24> +- =numOut$raw_n16<24> +# numOut [13] = $NDset ( 0,1 ) +.names -> numOut$raw_n1a$initial$_n1b<13> +0 +1 +.names numOut$raw_n1a$initial$_n1b<13> numOut$raw_n1a<13> +- =numOut$raw_n1a$initial$_n1b<13> +.names numOut$raw_n18<0> numOut$raw_n1a<0> +- =numOut$raw_n18<0> +.names numOut$raw_n18<1> numOut$raw_n1a<1> +- =numOut$raw_n18<1> +.names numOut$raw_n18<2> numOut$raw_n1a<2> +- =numOut$raw_n18<2> +.names numOut$raw_n18<3> numOut$raw_n1a<3> +- =numOut$raw_n18<3> +.names numOut$raw_n18<4> numOut$raw_n1a<4> +- =numOut$raw_n18<4> +.names numOut$raw_n18<5> numOut$raw_n1a<5> +- =numOut$raw_n18<5> +.names numOut$raw_n18<6> numOut$raw_n1a<6> +- =numOut$raw_n18<6> +.names numOut$raw_n18<7> numOut$raw_n1a<7> +- =numOut$raw_n18<7> +.names numOut$raw_n18<8> numOut$raw_n1a<8> +- =numOut$raw_n18<8> +.names numOut$raw_n18<9> numOut$raw_n1a<9> +- =numOut$raw_n18<9> +.names numOut$raw_n18<10> numOut$raw_n1a<10> +- =numOut$raw_n18<10> +.names numOut$raw_n18<11> numOut$raw_n1a<11> +- =numOut$raw_n18<11> +.names numOut$raw_n18<12> numOut$raw_n1a<12> +- =numOut$raw_n18<12> +.names numOut$raw_n18<14> numOut$raw_n1a<14> +- =numOut$raw_n18<14> +.names numOut$raw_n18<15> numOut$raw_n1a<15> +- =numOut$raw_n18<15> +.names numOut$raw_n18<16> numOut$raw_n1a<16> +- =numOut$raw_n18<16> +.names numOut$raw_n18<17> numOut$raw_n1a<17> +- =numOut$raw_n18<17> +.names numOut$raw_n18<18> numOut$raw_n1a<18> +- =numOut$raw_n18<18> +.names numOut$raw_n18<19> numOut$raw_n1a<19> +- =numOut$raw_n18<19> +.names numOut$raw_n18<20> numOut$raw_n1a<20> +- =numOut$raw_n18<20> +.names numOut$raw_n18<21> numOut$raw_n1a<21> +- =numOut$raw_n18<21> +.names numOut$raw_n18<22> numOut$raw_n1a<22> +- =numOut$raw_n18<22> +.names numOut$raw_n18<23> numOut$raw_n1a<23> +- =numOut$raw_n18<23> +.names numOut$raw_n18<24> numOut$raw_n1a<24> +- =numOut$raw_n18<24> +# numOut [14] = $NDset ( 0,1 ) +.names -> numOut$raw_n1c$initial$_n1d<14> +0 +1 +.names numOut$raw_n1c$initial$_n1d<14> numOut$raw_n1c<14> +- =numOut$raw_n1c$initial$_n1d<14> +.names numOut$raw_n1a<0> numOut$raw_n1c<0> +- =numOut$raw_n1a<0> +.names numOut$raw_n1a<1> numOut$raw_n1c<1> +- =numOut$raw_n1a<1> +.names numOut$raw_n1a<2> numOut$raw_n1c<2> +- =numOut$raw_n1a<2> +.names numOut$raw_n1a<3> numOut$raw_n1c<3> +- =numOut$raw_n1a<3> +.names numOut$raw_n1a<4> numOut$raw_n1c<4> +- =numOut$raw_n1a<4> +.names numOut$raw_n1a<5> numOut$raw_n1c<5> +- =numOut$raw_n1a<5> +.names numOut$raw_n1a<6> numOut$raw_n1c<6> +- =numOut$raw_n1a<6> +.names numOut$raw_n1a<7> numOut$raw_n1c<7> +- =numOut$raw_n1a<7> +.names numOut$raw_n1a<8> numOut$raw_n1c<8> +- =numOut$raw_n1a<8> +.names numOut$raw_n1a<9> numOut$raw_n1c<9> +- =numOut$raw_n1a<9> +.names numOut$raw_n1a<10> numOut$raw_n1c<10> +- =numOut$raw_n1a<10> +.names numOut$raw_n1a<11> numOut$raw_n1c<11> +- =numOut$raw_n1a<11> +.names numOut$raw_n1a<12> numOut$raw_n1c<12> +- =numOut$raw_n1a<12> +.names numOut$raw_n1a<13> numOut$raw_n1c<13> +- =numOut$raw_n1a<13> +.names numOut$raw_n1a<15> numOut$raw_n1c<15> +- =numOut$raw_n1a<15> +.names numOut$raw_n1a<16> numOut$raw_n1c<16> +- =numOut$raw_n1a<16> +.names numOut$raw_n1a<17> numOut$raw_n1c<17> +- =numOut$raw_n1a<17> +.names numOut$raw_n1a<18> numOut$raw_n1c<18> +- =numOut$raw_n1a<18> +.names numOut$raw_n1a<19> numOut$raw_n1c<19> +- =numOut$raw_n1a<19> +.names numOut$raw_n1a<20> numOut$raw_n1c<20> +- =numOut$raw_n1a<20> +.names numOut$raw_n1a<21> numOut$raw_n1c<21> +- =numOut$raw_n1a<21> +.names numOut$raw_n1a<22> numOut$raw_n1c<22> +- =numOut$raw_n1a<22> +.names numOut$raw_n1a<23> numOut$raw_n1c<23> +- =numOut$raw_n1a<23> +.names numOut$raw_n1a<24> numOut$raw_n1c<24> +- =numOut$raw_n1a<24> +# numOut [15] = $NDset ( 0,1 ) +.names -> numOut$raw_n1e$initial$_n1f<15> +0 +1 +.names numOut$raw_n1e$initial$_n1f<15> numOut$raw_n1e<15> +- =numOut$raw_n1e$initial$_n1f<15> +.names numOut$raw_n1c<0> numOut$raw_n1e<0> +- =numOut$raw_n1c<0> +.names numOut$raw_n1c<1> numOut$raw_n1e<1> +- =numOut$raw_n1c<1> +.names numOut$raw_n1c<2> numOut$raw_n1e<2> +- =numOut$raw_n1c<2> +.names numOut$raw_n1c<3> numOut$raw_n1e<3> +- =numOut$raw_n1c<3> +.names numOut$raw_n1c<4> numOut$raw_n1e<4> +- =numOut$raw_n1c<4> +.names numOut$raw_n1c<5> numOut$raw_n1e<5> +- =numOut$raw_n1c<5> +.names numOut$raw_n1c<6> numOut$raw_n1e<6> +- =numOut$raw_n1c<6> +.names numOut$raw_n1c<7> numOut$raw_n1e<7> +- =numOut$raw_n1c<7> +.names numOut$raw_n1c<8> numOut$raw_n1e<8> +- =numOut$raw_n1c<8> +.names numOut$raw_n1c<9> numOut$raw_n1e<9> +- =numOut$raw_n1c<9> +.names numOut$raw_n1c<10> numOut$raw_n1e<10> +- =numOut$raw_n1c<10> +.names numOut$raw_n1c<11> numOut$raw_n1e<11> +- =numOut$raw_n1c<11> +.names numOut$raw_n1c<12> numOut$raw_n1e<12> +- =numOut$raw_n1c<12> +.names numOut$raw_n1c<13> numOut$raw_n1e<13> +- =numOut$raw_n1c<13> +.names numOut$raw_n1c<14> numOut$raw_n1e<14> +- =numOut$raw_n1c<14> +.names numOut$raw_n1c<16> numOut$raw_n1e<16> +- =numOut$raw_n1c<16> +.names numOut$raw_n1c<17> numOut$raw_n1e<17> +- =numOut$raw_n1c<17> +.names numOut$raw_n1c<18> numOut$raw_n1e<18> +- =numOut$raw_n1c<18> +.names numOut$raw_n1c<19> numOut$raw_n1e<19> +- =numOut$raw_n1c<19> +.names numOut$raw_n1c<20> numOut$raw_n1e<20> +- =numOut$raw_n1c<20> +.names numOut$raw_n1c<21> numOut$raw_n1e<21> +- =numOut$raw_n1c<21> +.names numOut$raw_n1c<22> numOut$raw_n1e<22> +- =numOut$raw_n1c<22> +.names numOut$raw_n1c<23> numOut$raw_n1e<23> +- =numOut$raw_n1c<23> +.names numOut$raw_n1c<24> numOut$raw_n1e<24> +- =numOut$raw_n1c<24> +# numOut [16] = $NDset ( 0,1 ) +.names -> numOut$raw_n20$initial$_n21<16> +0 +1 +.names numOut$raw_n20$initial$_n21<16> numOut$raw_n20<16> +- =numOut$raw_n20$initial$_n21<16> +.names numOut$raw_n1e<0> numOut$raw_n20<0> +- =numOut$raw_n1e<0> +.names numOut$raw_n1e<1> numOut$raw_n20<1> +- =numOut$raw_n1e<1> +.names numOut$raw_n1e<2> numOut$raw_n20<2> +- =numOut$raw_n1e<2> +.names numOut$raw_n1e<3> numOut$raw_n20<3> +- =numOut$raw_n1e<3> +.names numOut$raw_n1e<4> numOut$raw_n20<4> +- =numOut$raw_n1e<4> +.names numOut$raw_n1e<5> numOut$raw_n20<5> +- =numOut$raw_n1e<5> +.names numOut$raw_n1e<6> numOut$raw_n20<6> +- =numOut$raw_n1e<6> +.names numOut$raw_n1e<7> numOut$raw_n20<7> +- =numOut$raw_n1e<7> +.names numOut$raw_n1e<8> numOut$raw_n20<8> +- =numOut$raw_n1e<8> +.names numOut$raw_n1e<9> numOut$raw_n20<9> +- =numOut$raw_n1e<9> +.names numOut$raw_n1e<10> numOut$raw_n20<10> +- =numOut$raw_n1e<10> +.names numOut$raw_n1e<11> numOut$raw_n20<11> +- =numOut$raw_n1e<11> +.names numOut$raw_n1e<12> numOut$raw_n20<12> +- =numOut$raw_n1e<12> +.names numOut$raw_n1e<13> numOut$raw_n20<13> +- =numOut$raw_n1e<13> +.names numOut$raw_n1e<14> numOut$raw_n20<14> +- =numOut$raw_n1e<14> +.names numOut$raw_n1e<15> numOut$raw_n20<15> +- =numOut$raw_n1e<15> +.names numOut$raw_n1e<17> numOut$raw_n20<17> +- =numOut$raw_n1e<17> +.names numOut$raw_n1e<18> numOut$raw_n20<18> +- =numOut$raw_n1e<18> +.names numOut$raw_n1e<19> numOut$raw_n20<19> +- =numOut$raw_n1e<19> +.names numOut$raw_n1e<20> numOut$raw_n20<20> +- =numOut$raw_n1e<20> +.names numOut$raw_n1e<21> numOut$raw_n20<21> +- =numOut$raw_n1e<21> +.names numOut$raw_n1e<22> numOut$raw_n20<22> +- =numOut$raw_n1e<22> +.names numOut$raw_n1e<23> numOut$raw_n20<23> +- =numOut$raw_n1e<23> +.names numOut$raw_n1e<24> numOut$raw_n20<24> +- =numOut$raw_n1e<24> +# numOut [17] = $NDset ( 0,1 ) +.names -> numOut$raw_n22$initial$_n23<17> +0 +1 +.names numOut$raw_n22$initial$_n23<17> numOut$raw_n22<17> +- =numOut$raw_n22$initial$_n23<17> +.names numOut$raw_n20<0> numOut$raw_n22<0> +- =numOut$raw_n20<0> +.names numOut$raw_n20<1> numOut$raw_n22<1> +- =numOut$raw_n20<1> +.names numOut$raw_n20<2> numOut$raw_n22<2> +- =numOut$raw_n20<2> +.names numOut$raw_n20<3> numOut$raw_n22<3> +- =numOut$raw_n20<3> +.names numOut$raw_n20<4> numOut$raw_n22<4> +- =numOut$raw_n20<4> +.names numOut$raw_n20<5> numOut$raw_n22<5> +- =numOut$raw_n20<5> +.names numOut$raw_n20<6> numOut$raw_n22<6> +- =numOut$raw_n20<6> +.names numOut$raw_n20<7> numOut$raw_n22<7> +- =numOut$raw_n20<7> +.names numOut$raw_n20<8> numOut$raw_n22<8> +- =numOut$raw_n20<8> +.names numOut$raw_n20<9> numOut$raw_n22<9> +- =numOut$raw_n20<9> +.names numOut$raw_n20<10> numOut$raw_n22<10> +- =numOut$raw_n20<10> +.names numOut$raw_n20<11> numOut$raw_n22<11> +- =numOut$raw_n20<11> +.names numOut$raw_n20<12> numOut$raw_n22<12> +- =numOut$raw_n20<12> +.names numOut$raw_n20<13> numOut$raw_n22<13> +- =numOut$raw_n20<13> +.names numOut$raw_n20<14> numOut$raw_n22<14> +- =numOut$raw_n20<14> +.names numOut$raw_n20<15> numOut$raw_n22<15> +- =numOut$raw_n20<15> +.names numOut$raw_n20<16> numOut$raw_n22<16> +- =numOut$raw_n20<16> +.names numOut$raw_n20<18> numOut$raw_n22<18> +- =numOut$raw_n20<18> +.names numOut$raw_n20<19> numOut$raw_n22<19> +- =numOut$raw_n20<19> +.names numOut$raw_n20<20> numOut$raw_n22<20> +- =numOut$raw_n20<20> +.names numOut$raw_n20<21> numOut$raw_n22<21> +- =numOut$raw_n20<21> +.names numOut$raw_n20<22> numOut$raw_n22<22> +- =numOut$raw_n20<22> +.names numOut$raw_n20<23> numOut$raw_n22<23> +- =numOut$raw_n20<23> +.names numOut$raw_n20<24> numOut$raw_n22<24> +- =numOut$raw_n20<24> +# numOut [18] = $NDset ( 0,1 ) +.names -> numOut$raw_n24$initial$_n25<18> +0 +1 +.names numOut$raw_n24$initial$_n25<18> numOut$raw_n24<18> +- =numOut$raw_n24$initial$_n25<18> +.names numOut$raw_n22<0> numOut$raw_n24<0> +- =numOut$raw_n22<0> +.names numOut$raw_n22<1> numOut$raw_n24<1> +- =numOut$raw_n22<1> +.names numOut$raw_n22<2> numOut$raw_n24<2> +- =numOut$raw_n22<2> +.names numOut$raw_n22<3> numOut$raw_n24<3> +- =numOut$raw_n22<3> +.names numOut$raw_n22<4> numOut$raw_n24<4> +- =numOut$raw_n22<4> +.names numOut$raw_n22<5> numOut$raw_n24<5> +- =numOut$raw_n22<5> +.names numOut$raw_n22<6> numOut$raw_n24<6> +- =numOut$raw_n22<6> +.names numOut$raw_n22<7> numOut$raw_n24<7> +- =numOut$raw_n22<7> +.names numOut$raw_n22<8> numOut$raw_n24<8> +- =numOut$raw_n22<8> +.names numOut$raw_n22<9> numOut$raw_n24<9> +- =numOut$raw_n22<9> +.names numOut$raw_n22<10> numOut$raw_n24<10> +- =numOut$raw_n22<10> +.names numOut$raw_n22<11> numOut$raw_n24<11> +- =numOut$raw_n22<11> +.names numOut$raw_n22<12> numOut$raw_n24<12> +- =numOut$raw_n22<12> +.names numOut$raw_n22<13> numOut$raw_n24<13> +- =numOut$raw_n22<13> +.names numOut$raw_n22<14> numOut$raw_n24<14> +- =numOut$raw_n22<14> +.names numOut$raw_n22<15> numOut$raw_n24<15> +- =numOut$raw_n22<15> +.names numOut$raw_n22<16> numOut$raw_n24<16> +- =numOut$raw_n22<16> +.names numOut$raw_n22<17> numOut$raw_n24<17> +- =numOut$raw_n22<17> +.names numOut$raw_n22<19> numOut$raw_n24<19> +- =numOut$raw_n22<19> +.names numOut$raw_n22<20> numOut$raw_n24<20> +- =numOut$raw_n22<20> +.names numOut$raw_n22<21> numOut$raw_n24<21> +- =numOut$raw_n22<21> +.names numOut$raw_n22<22> numOut$raw_n24<22> +- =numOut$raw_n22<22> +.names numOut$raw_n22<23> numOut$raw_n24<23> +- =numOut$raw_n22<23> +.names numOut$raw_n22<24> numOut$raw_n24<24> +- =numOut$raw_n22<24> +# numOut [19] = $NDset ( 0,1 ) +.names -> numOut$raw_n26$initial$_n27<19> +0 +1 +.names numOut$raw_n26$initial$_n27<19> numOut$raw_n26<19> +- =numOut$raw_n26$initial$_n27<19> +.names numOut$raw_n24<0> numOut$raw_n26<0> +- =numOut$raw_n24<0> +.names numOut$raw_n24<1> numOut$raw_n26<1> +- =numOut$raw_n24<1> +.names numOut$raw_n24<2> numOut$raw_n26<2> +- =numOut$raw_n24<2> +.names numOut$raw_n24<3> numOut$raw_n26<3> +- =numOut$raw_n24<3> +.names numOut$raw_n24<4> numOut$raw_n26<4> +- =numOut$raw_n24<4> +.names numOut$raw_n24<5> numOut$raw_n26<5> +- =numOut$raw_n24<5> +.names numOut$raw_n24<6> numOut$raw_n26<6> +- =numOut$raw_n24<6> +.names numOut$raw_n24<7> numOut$raw_n26<7> +- =numOut$raw_n24<7> +.names numOut$raw_n24<8> numOut$raw_n26<8> +- =numOut$raw_n24<8> +.names numOut$raw_n24<9> numOut$raw_n26<9> +- =numOut$raw_n24<9> +.names numOut$raw_n24<10> numOut$raw_n26<10> +- =numOut$raw_n24<10> +.names numOut$raw_n24<11> numOut$raw_n26<11> +- =numOut$raw_n24<11> +.names numOut$raw_n24<12> numOut$raw_n26<12> +- =numOut$raw_n24<12> +.names numOut$raw_n24<13> numOut$raw_n26<13> +- =numOut$raw_n24<13> +.names numOut$raw_n24<14> numOut$raw_n26<14> +- =numOut$raw_n24<14> +.names numOut$raw_n24<15> numOut$raw_n26<15> +- =numOut$raw_n24<15> +.names numOut$raw_n24<16> numOut$raw_n26<16> +- =numOut$raw_n24<16> +.names numOut$raw_n24<17> numOut$raw_n26<17> +- =numOut$raw_n24<17> +.names numOut$raw_n24<18> numOut$raw_n26<18> +- =numOut$raw_n24<18> +.names numOut$raw_n24<20> numOut$raw_n26<20> +- =numOut$raw_n24<20> +.names numOut$raw_n24<21> numOut$raw_n26<21> +- =numOut$raw_n24<21> +.names numOut$raw_n24<22> numOut$raw_n26<22> +- =numOut$raw_n24<22> +.names numOut$raw_n24<23> numOut$raw_n26<23> +- =numOut$raw_n24<23> +.names numOut$raw_n24<24> numOut$raw_n26<24> +- =numOut$raw_n24<24> +# numOut [20] = $NDset ( 0,1 ) +.names -> numOut$raw_n28$initial$_n29<20> +0 +1 +.names numOut$raw_n28$initial$_n29<20> numOut$raw_n28<20> +- =numOut$raw_n28$initial$_n29<20> +.names numOut$raw_n26<0> numOut$raw_n28<0> +- =numOut$raw_n26<0> +.names numOut$raw_n26<1> numOut$raw_n28<1> +- =numOut$raw_n26<1> +.names numOut$raw_n26<2> numOut$raw_n28<2> +- =numOut$raw_n26<2> +.names numOut$raw_n26<3> numOut$raw_n28<3> +- =numOut$raw_n26<3> +.names numOut$raw_n26<4> numOut$raw_n28<4> +- =numOut$raw_n26<4> +.names numOut$raw_n26<5> numOut$raw_n28<5> +- =numOut$raw_n26<5> +.names numOut$raw_n26<6> numOut$raw_n28<6> +- =numOut$raw_n26<6> +.names numOut$raw_n26<7> numOut$raw_n28<7> +- =numOut$raw_n26<7> +.names numOut$raw_n26<8> numOut$raw_n28<8> +- =numOut$raw_n26<8> +.names numOut$raw_n26<9> numOut$raw_n28<9> +- =numOut$raw_n26<9> +.names numOut$raw_n26<10> numOut$raw_n28<10> +- =numOut$raw_n26<10> +.names numOut$raw_n26<11> numOut$raw_n28<11> +- =numOut$raw_n26<11> +.names numOut$raw_n26<12> numOut$raw_n28<12> +- =numOut$raw_n26<12> +.names numOut$raw_n26<13> numOut$raw_n28<13> +- =numOut$raw_n26<13> +.names numOut$raw_n26<14> numOut$raw_n28<14> +- =numOut$raw_n26<14> +.names numOut$raw_n26<15> numOut$raw_n28<15> +- =numOut$raw_n26<15> +.names numOut$raw_n26<16> numOut$raw_n28<16> +- =numOut$raw_n26<16> +.names numOut$raw_n26<17> numOut$raw_n28<17> +- =numOut$raw_n26<17> +.names numOut$raw_n26<18> numOut$raw_n28<18> +- =numOut$raw_n26<18> +.names numOut$raw_n26<19> numOut$raw_n28<19> +- =numOut$raw_n26<19> +.names numOut$raw_n26<21> numOut$raw_n28<21> +- =numOut$raw_n26<21> +.names numOut$raw_n26<22> numOut$raw_n28<22> +- =numOut$raw_n26<22> +.names numOut$raw_n26<23> numOut$raw_n28<23> +- =numOut$raw_n26<23> +.names numOut$raw_n26<24> numOut$raw_n28<24> +- =numOut$raw_n26<24> +# numOut [21] = $NDset ( 0,1 ) +.names -> numOut$raw_n2a$initial$_n2b<21> +0 +1 +.names numOut$raw_n2a$initial$_n2b<21> numOut$raw_n2a<21> +- =numOut$raw_n2a$initial$_n2b<21> +.names numOut$raw_n28<0> numOut$raw_n2a<0> +- =numOut$raw_n28<0> +.names numOut$raw_n28<1> numOut$raw_n2a<1> +- =numOut$raw_n28<1> +.names numOut$raw_n28<2> numOut$raw_n2a<2> +- =numOut$raw_n28<2> +.names numOut$raw_n28<3> numOut$raw_n2a<3> +- =numOut$raw_n28<3> +.names numOut$raw_n28<4> numOut$raw_n2a<4> +- =numOut$raw_n28<4> +.names numOut$raw_n28<5> numOut$raw_n2a<5> +- =numOut$raw_n28<5> +.names numOut$raw_n28<6> numOut$raw_n2a<6> +- =numOut$raw_n28<6> +.names numOut$raw_n28<7> numOut$raw_n2a<7> +- =numOut$raw_n28<7> +.names numOut$raw_n28<8> numOut$raw_n2a<8> +- =numOut$raw_n28<8> +.names numOut$raw_n28<9> numOut$raw_n2a<9> +- =numOut$raw_n28<9> +.names numOut$raw_n28<10> numOut$raw_n2a<10> +- =numOut$raw_n28<10> +.names numOut$raw_n28<11> numOut$raw_n2a<11> +- =numOut$raw_n28<11> +.names numOut$raw_n28<12> numOut$raw_n2a<12> +- =numOut$raw_n28<12> +.names numOut$raw_n28<13> numOut$raw_n2a<13> +- =numOut$raw_n28<13> +.names numOut$raw_n28<14> numOut$raw_n2a<14> +- =numOut$raw_n28<14> +.names numOut$raw_n28<15> numOut$raw_n2a<15> +- =numOut$raw_n28<15> +.names numOut$raw_n28<16> numOut$raw_n2a<16> +- =numOut$raw_n28<16> +.names numOut$raw_n28<17> numOut$raw_n2a<17> +- =numOut$raw_n28<17> +.names numOut$raw_n28<18> numOut$raw_n2a<18> +- =numOut$raw_n28<18> +.names numOut$raw_n28<19> numOut$raw_n2a<19> +- =numOut$raw_n28<19> +.names numOut$raw_n28<20> numOut$raw_n2a<20> +- =numOut$raw_n28<20> +.names numOut$raw_n28<22> numOut$raw_n2a<22> +- =numOut$raw_n28<22> +.names numOut$raw_n28<23> numOut$raw_n2a<23> +- =numOut$raw_n28<23> +.names numOut$raw_n28<24> numOut$raw_n2a<24> +- =numOut$raw_n28<24> +# numOut [22] = $NDset ( 0,1 ) +.names -> numOut$raw_n2c$initial$_n2d<22> +0 +1 +.names numOut$raw_n2c$initial$_n2d<22> numOut$raw_n2c<22> +- =numOut$raw_n2c$initial$_n2d<22> +.names numOut$raw_n2a<0> numOut$raw_n2c<0> +- =numOut$raw_n2a<0> +.names numOut$raw_n2a<1> numOut$raw_n2c<1> +- =numOut$raw_n2a<1> +.names numOut$raw_n2a<2> numOut$raw_n2c<2> +- =numOut$raw_n2a<2> +.names numOut$raw_n2a<3> numOut$raw_n2c<3> +- =numOut$raw_n2a<3> +.names numOut$raw_n2a<4> numOut$raw_n2c<4> +- =numOut$raw_n2a<4> +.names numOut$raw_n2a<5> numOut$raw_n2c<5> +- =numOut$raw_n2a<5> +.names numOut$raw_n2a<6> numOut$raw_n2c<6> +- =numOut$raw_n2a<6> +.names numOut$raw_n2a<7> numOut$raw_n2c<7> +- =numOut$raw_n2a<7> +.names numOut$raw_n2a<8> numOut$raw_n2c<8> +- =numOut$raw_n2a<8> +.names numOut$raw_n2a<9> numOut$raw_n2c<9> +- =numOut$raw_n2a<9> +.names numOut$raw_n2a<10> numOut$raw_n2c<10> +- =numOut$raw_n2a<10> +.names numOut$raw_n2a<11> numOut$raw_n2c<11> +- =numOut$raw_n2a<11> +.names numOut$raw_n2a<12> numOut$raw_n2c<12> +- =numOut$raw_n2a<12> +.names numOut$raw_n2a<13> numOut$raw_n2c<13> +- =numOut$raw_n2a<13> +.names numOut$raw_n2a<14> numOut$raw_n2c<14> +- =numOut$raw_n2a<14> +.names numOut$raw_n2a<15> numOut$raw_n2c<15> +- =numOut$raw_n2a<15> +.names numOut$raw_n2a<16> numOut$raw_n2c<16> +- =numOut$raw_n2a<16> +.names numOut$raw_n2a<17> numOut$raw_n2c<17> +- =numOut$raw_n2a<17> +.names numOut$raw_n2a<18> numOut$raw_n2c<18> +- =numOut$raw_n2a<18> +.names numOut$raw_n2a<19> numOut$raw_n2c<19> +- =numOut$raw_n2a<19> +.names numOut$raw_n2a<20> numOut$raw_n2c<20> +- =numOut$raw_n2a<20> +.names numOut$raw_n2a<21> numOut$raw_n2c<21> +- =numOut$raw_n2a<21> +.names numOut$raw_n2a<23> numOut$raw_n2c<23> +- =numOut$raw_n2a<23> +.names numOut$raw_n2a<24> numOut$raw_n2c<24> +- =numOut$raw_n2a<24> +# numOut [23] = $NDset ( 0,1 ) +.names -> numOut$raw_n2e$initial$_n2f<23> +0 +1 +.names numOut$raw_n2e$initial$_n2f<23> numOut$raw_n2e<23> +- =numOut$raw_n2e$initial$_n2f<23> +.names numOut$raw_n2c<0> numOut$raw_n2e<0> +- =numOut$raw_n2c<0> +.names numOut$raw_n2c<1> numOut$raw_n2e<1> +- =numOut$raw_n2c<1> +.names numOut$raw_n2c<2> numOut$raw_n2e<2> +- =numOut$raw_n2c<2> +.names numOut$raw_n2c<3> numOut$raw_n2e<3> +- =numOut$raw_n2c<3> +.names numOut$raw_n2c<4> numOut$raw_n2e<4> +- =numOut$raw_n2c<4> +.names numOut$raw_n2c<5> numOut$raw_n2e<5> +- =numOut$raw_n2c<5> +.names numOut$raw_n2c<6> numOut$raw_n2e<6> +- =numOut$raw_n2c<6> +.names numOut$raw_n2c<7> numOut$raw_n2e<7> +- =numOut$raw_n2c<7> +.names numOut$raw_n2c<8> numOut$raw_n2e<8> +- =numOut$raw_n2c<8> +.names numOut$raw_n2c<9> numOut$raw_n2e<9> +- =numOut$raw_n2c<9> +.names numOut$raw_n2c<10> numOut$raw_n2e<10> +- =numOut$raw_n2c<10> +.names numOut$raw_n2c<11> numOut$raw_n2e<11> +- =numOut$raw_n2c<11> +.names numOut$raw_n2c<12> numOut$raw_n2e<12> +- =numOut$raw_n2c<12> +.names numOut$raw_n2c<13> numOut$raw_n2e<13> +- =numOut$raw_n2c<13> +.names numOut$raw_n2c<14> numOut$raw_n2e<14> +- =numOut$raw_n2c<14> +.names numOut$raw_n2c<15> numOut$raw_n2e<15> +- =numOut$raw_n2c<15> +.names numOut$raw_n2c<16> numOut$raw_n2e<16> +- =numOut$raw_n2c<16> +.names numOut$raw_n2c<17> numOut$raw_n2e<17> +- =numOut$raw_n2c<17> +.names numOut$raw_n2c<18> numOut$raw_n2e<18> +- =numOut$raw_n2c<18> +.names numOut$raw_n2c<19> numOut$raw_n2e<19> +- =numOut$raw_n2c<19> +.names numOut$raw_n2c<20> numOut$raw_n2e<20> +- =numOut$raw_n2c<20> +.names numOut$raw_n2c<21> numOut$raw_n2e<21> +- =numOut$raw_n2c<21> +.names numOut$raw_n2c<22> numOut$raw_n2e<22> +- =numOut$raw_n2c<22> +.names numOut$raw_n2c<24> numOut$raw_n2e<24> +- =numOut$raw_n2c<24> +# numOut [24] = $NDset ( 0,1 ) +.names -> numOut$raw_n30$initial$_n31<24> +0 +1 +.names numOut$raw_n30$initial$_n31<24> numOut$raw_n30<24> +- =numOut$raw_n30$initial$_n31<24> +.names numOut$raw_n2e<0> numOut$raw_n30<0> +- =numOut$raw_n2e<0> +.names numOut$raw_n2e<1> numOut$raw_n30<1> +- =numOut$raw_n2e<1> +.names numOut$raw_n2e<2> numOut$raw_n30<2> +- =numOut$raw_n2e<2> +.names numOut$raw_n2e<3> numOut$raw_n30<3> +- =numOut$raw_n2e<3> +.names numOut$raw_n2e<4> numOut$raw_n30<4> +- =numOut$raw_n2e<4> +.names numOut$raw_n2e<5> numOut$raw_n30<5> +- =numOut$raw_n2e<5> +.names numOut$raw_n2e<6> numOut$raw_n30<6> +- =numOut$raw_n2e<6> +.names numOut$raw_n2e<7> numOut$raw_n30<7> +- =numOut$raw_n2e<7> +.names numOut$raw_n2e<8> numOut$raw_n30<8> +- =numOut$raw_n2e<8> +.names numOut$raw_n2e<9> numOut$raw_n30<9> +- =numOut$raw_n2e<9> +.names numOut$raw_n2e<10> numOut$raw_n30<10> +- =numOut$raw_n2e<10> +.names numOut$raw_n2e<11> numOut$raw_n30<11> +- =numOut$raw_n2e<11> +.names numOut$raw_n2e<12> numOut$raw_n30<12> +- =numOut$raw_n2e<12> +.names numOut$raw_n2e<13> numOut$raw_n30<13> +- =numOut$raw_n2e<13> +.names numOut$raw_n2e<14> numOut$raw_n30<14> +- =numOut$raw_n2e<14> +.names numOut$raw_n2e<15> numOut$raw_n30<15> +- =numOut$raw_n2e<15> +.names numOut$raw_n2e<16> numOut$raw_n30<16> +- =numOut$raw_n2e<16> +.names numOut$raw_n2e<17> numOut$raw_n30<17> +- =numOut$raw_n2e<17> +.names numOut$raw_n2e<18> numOut$raw_n30<18> +- =numOut$raw_n2e<18> +.names numOut$raw_n2e<19> numOut$raw_n30<19> +- =numOut$raw_n2e<19> +.names numOut$raw_n2e<20> numOut$raw_n30<20> +- =numOut$raw_n2e<20> +.names numOut$raw_n2e<21> numOut$raw_n30<21> +- =numOut$raw_n2e<21> +.names numOut$raw_n2e<22> numOut$raw_n30<22> +- =numOut$raw_n2e<22> +.names numOut$raw_n2e<23> numOut$raw_n30<23> +- =numOut$raw_n2e<23> +# non-blocking assignments for initial +# assign tmp = {'b00, numOut } + {'b0, numOut , 'b1} +.names numOut<0> _n33<0> +- =numOut<0> +.names numOut<1> _n33<1> +- =numOut<1> +.names numOut<2> _n33<2> +- =numOut<2> +.names numOut<3> _n33<3> +- =numOut<3> +.names numOut<4> _n33<4> +- =numOut<4> +.names numOut<5> _n33<5> +- =numOut<5> +.names numOut<6> _n33<6> +- =numOut<6> +.names numOut<7> _n33<7> +- =numOut<7> +.names numOut<8> _n33<8> +- =numOut<8> +.names numOut<9> _n33<9> +- =numOut<9> +.names numOut<10> _n33<10> +- =numOut<10> +.names numOut<11> _n33<11> +- =numOut<11> +.names numOut<12> _n33<12> +- =numOut<12> +.names numOut<13> _n33<13> +- =numOut<13> +.names numOut<14> _n33<14> +- =numOut<14> +.names numOut<15> _n33<15> +- =numOut<15> +.names numOut<16> _n33<16> +- =numOut<16> +.names numOut<17> _n33<17> +- =numOut<17> +.names numOut<18> _n33<18> +- =numOut<18> +.names numOut<19> _n33<19> +- =numOut<19> +.names numOut<20> _n33<20> +- =numOut<20> +.names numOut<21> _n33<21> +- =numOut<21> +.names numOut<22> _n33<22> +- =numOut<22> +.names numOut<23> _n33<23> +- =numOut<23> +.names numOut<24> _n33<24> +- =numOut<24> +.names _n34<0> +0 +.names _n34<1> +0 +.names _n34<0> _n33<25> +- =_n34<0> +.names _n34<1> _n33<26> +- =_n34<1> +.names _n36 +1 +.names _n36 _n35<0> +- =_n36 +.names _n37 +0 +.names numOut<0> _n35<1> +- =numOut<0> +.names numOut<1> _n35<2> +- =numOut<1> +.names numOut<2> _n35<3> +- =numOut<2> +.names numOut<3> _n35<4> +- =numOut<3> +.names numOut<4> _n35<5> +- =numOut<4> +.names numOut<5> _n35<6> +- =numOut<5> +.names numOut<6> _n35<7> +- =numOut<6> +.names numOut<7> _n35<8> +- =numOut<7> +.names numOut<8> _n35<9> +- =numOut<8> +.names numOut<9> _n35<10> +- =numOut<9> +.names numOut<10> _n35<11> +- =numOut<10> +.names numOut<11> _n35<12> +- =numOut<11> +.names numOut<12> _n35<13> +- =numOut<12> +.names numOut<13> _n35<14> +- =numOut<13> +.names numOut<14> _n35<15> +- =numOut<14> +.names numOut<15> _n35<16> +- =numOut<15> +.names numOut<16> _n35<17> +- =numOut<16> +.names numOut<17> _n35<18> +- =numOut<17> +.names numOut<18> _n35<19> +- =numOut<18> +.names numOut<19> _n35<20> +- =numOut<19> +.names numOut<20> _n35<21> +- =numOut<20> +.names numOut<21> _n35<22> +- =numOut<21> +.names numOut<22> _n35<23> +- =numOut<22> +.names numOut<23> _n35<24> +- =numOut<23> +.names numOut<24> _n35<25> +- =numOut<24> +.names _n38 +0 +.names _n38 _n35<26> +- =_n38 +.names _n39 +0 +# {'b00, numOut } + {'b0, numOut , 'b1} +.names _n3b +0 +.names _n33<0> _n35<0> _n3b _n3a<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n3d +0 +.names _n33<0> _n35<0> _n3d _n3c +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<1> _n35<1> _n3c _n3a<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<1> _n35<1> _n3c _n3e +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<2> _n35<2> _n3e _n3a<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<2> _n35<2> _n3e _n3f +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<3> _n35<3> _n3f _n3a<3> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<3> _n35<3> _n3f _n40 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<4> _n35<4> _n40 _n3a<4> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<4> _n35<4> _n40 _n41 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<5> _n35<5> _n41 _n3a<5> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<5> _n35<5> _n41 _n42 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<6> _n35<6> _n42 _n3a<6> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<6> _n35<6> _n42 _n43 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<7> _n35<7> _n43 _n3a<7> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<7> _n35<7> _n43 _n44 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<8> _n35<8> _n44 _n3a<8> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<8> _n35<8> _n44 _n45 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<9> _n35<9> _n45 _n3a<9> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<9> _n35<9> _n45 _n46 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<10> _n35<10> _n46 _n3a<10> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<10> _n35<10> _n46 _n47 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<11> _n35<11> _n47 _n3a<11> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<11> _n35<11> _n47 _n48 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<12> _n35<12> _n48 _n3a<12> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<12> _n35<12> _n48 _n49 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<13> _n35<13> _n49 _n3a<13> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<13> _n35<13> _n49 _n4a +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<14> _n35<14> _n4a _n3a<14> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<14> _n35<14> _n4a _n4b +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<15> _n35<15> _n4b _n3a<15> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<15> _n35<15> _n4b _n4c +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<16> _n35<16> _n4c _n3a<16> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<16> _n35<16> _n4c _n4d +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<17> _n35<17> _n4d _n3a<17> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<17> _n35<17> _n4d _n4e +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<18> _n35<18> _n4e _n3a<18> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<18> _n35<18> _n4e _n4f +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<19> _n35<19> _n4f _n3a<19> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<19> _n35<19> _n4f _n50 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<20> _n35<20> _n50 _n3a<20> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<20> _n35<20> _n50 _n51 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<21> _n35<21> _n51 _n3a<21> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<21> _n35<21> _n51 _n52 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<22> _n35<22> _n52 _n3a<22> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<22> _n35<22> _n52 _n53 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<23> _n35<23> _n53 _n3a<23> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<23> _n35<23> _n53 _n54 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<24> _n35<24> _n54 _n3a<24> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<24> _n35<24> _n54 _n55 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<25> _n35<25> _n55 _n3a<25> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n33<25> _n35<25> _n55 _n56 +.def 0 +0 1 1 1 +1 0 1 1 +1 1 0 1 +1 1 1 1 +.names _n33<26> _n35<26> _n56 _n3a<26> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +.names _n3a<0> tmp$raw_n32<0> +- =_n3a<0> +.names _n3a<1> tmp$raw_n32<1> +- =_n3a<1> +.names _n3a<2> tmp$raw_n32<2> +- =_n3a<2> +.names _n3a<3> tmp$raw_n32<3> +- =_n3a<3> +.names _n3a<4> tmp$raw_n32<4> +- =_n3a<4> +.names _n3a<5> tmp$raw_n32<5> +- =_n3a<5> +.names _n3a<6> tmp$raw_n32<6> +- =_n3a<6> +.names _n3a<7> tmp$raw_n32<7> +- =_n3a<7> +.names _n3a<8> tmp$raw_n32<8> +- =_n3a<8> +.names _n3a<9> tmp$raw_n32<9> +- =_n3a<9> +.names _n3a<10> tmp$raw_n32<10> +- =_n3a<10> +.names _n3a<11> tmp$raw_n32<11> +- =_n3a<11> +.names _n3a<12> tmp$raw_n32<12> +- =_n3a<12> +.names _n3a<13> tmp$raw_n32<13> +- =_n3a<13> +.names _n3a<14> tmp$raw_n32<14> +- =_n3a<14> +.names _n3a<15> tmp$raw_n32<15> +- =_n3a<15> +.names _n3a<16> tmp$raw_n32<16> +- =_n3a<16> +.names _n3a<17> tmp$raw_n32<17> +- =_n3a<17> +.names _n3a<18> tmp$raw_n32<18> +- =_n3a<18> +.names _n3a<19> tmp$raw_n32<19> +- =_n3a<19> +.names _n3a<20> tmp$raw_n32<20> +- =_n3a<20> +.names _n3a<21> tmp$raw_n32<21> +- =_n3a<21> +.names _n3a<22> tmp$raw_n32<22> +- =_n3a<22> +.names _n3a<23> tmp$raw_n32<23> +- =_n3a<23> +.names _n3a<24> tmp$raw_n32<24> +- =_n3a<24> +.names _n3a<25> tmp$raw_n32<25> +- =_n3a<25> +.names _n3a<26> tmp$raw_n32<26> +- =_n3a<26> +.names numOut<0> _n58 +.def 1 +0 0 +.names _n58 _n57 +- =_n58 +# numOut = (tmp [24 + 2] | tmp [24 + 1]) ? 0 : tmp [24 : 0] +# tmp [24 + 2] | tmp [24 + 1] +.names tmp<26> tmp<25> _n5a<0> +.def 1 +0 0 0 +.names _n5b<0> +0 +.names _n5b<1> +0 +.names _n5b<2> +0 +.names _n5b<3> +0 +.names _n5b<4> +0 +.names _n5b<5> +0 +.names _n5b<6> +0 +.names _n5b<7> +0 +.names _n5b<8> +0 +.names _n5b<9> +0 +.names _n5b<10> +0 +.names _n5b<11> +0 +.names _n5b<12> +0 +.names _n5b<13> +0 +.names _n5b<14> +0 +.names _n5b<15> +0 +.names _n5b<16> +0 +.names _n5b<17> +0 +.names _n5b<18> +0 +.names _n5b<19> +0 +.names _n5b<20> +0 +.names _n5b<21> +0 +.names _n5b<22> +0 +.names _n5b<23> +0 +.names _n5b<24> +0 +# (tmp [24 + 2] | tmp [24 + 1]) ? 0 : tmp [24 : 0] +.names _n5a<0> _n5d +.def 1 +0 0 +.names _n5b<0> tmp<0> _n5d _n5c<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<1> tmp<1> _n5d _n5c<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<2> tmp<2> _n5d _n5c<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<3> tmp<3> _n5d _n5c<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<4> tmp<4> _n5d _n5c<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<5> tmp<5> _n5d _n5c<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<6> tmp<6> _n5d _n5c<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<7> tmp<7> _n5d _n5c<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<8> tmp<8> _n5d _n5c<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<9> tmp<9> _n5d _n5c<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<10> tmp<10> _n5d _n5c<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<11> tmp<11> _n5d _n5c<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<12> tmp<12> _n5d _n5c<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<13> tmp<13> _n5d _n5c<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<14> tmp<14> _n5d _n5c<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<15> tmp<15> _n5d _n5c<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<16> tmp<16> _n5d _n5c<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<17> tmp<17> _n5d _n5c<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<18> tmp<18> _n5d _n5c<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<19> tmp<19> _n5d _n5c<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<20> tmp<20> _n5d _n5c<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<21> tmp<21> _n5d _n5c<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<22> tmp<22> _n5d _n5c<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<23> tmp<23> _n5d _n5c<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5b<24> tmp<24> _n5d _n5c<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names _n5c<0> numOut$numOut_n59$true<0> +- =_n5c<0> +.names _n5c<1> numOut$numOut_n59$true<1> +- =_n5c<1> +.names _n5c<2> numOut$numOut_n59$true<2> +- =_n5c<2> +.names _n5c<3> numOut$numOut_n59$true<3> +- =_n5c<3> +.names _n5c<4> numOut$numOut_n59$true<4> +- =_n5c<4> +.names _n5c<5> numOut$numOut_n59$true<5> +- =_n5c<5> +.names _n5c<6> numOut$numOut_n59$true<6> +- =_n5c<6> +.names _n5c<7> numOut$numOut_n59$true<7> +- =_n5c<7> +.names _n5c<8> numOut$numOut_n59$true<8> +- =_n5c<8> +.names _n5c<9> numOut$numOut_n59$true<9> +- =_n5c<9> +.names _n5c<10> numOut$numOut_n59$true<10> +- =_n5c<10> +.names _n5c<11> numOut$numOut_n59$true<11> +- =_n5c<11> +.names _n5c<12> numOut$numOut_n59$true<12> +- =_n5c<12> +.names _n5c<13> numOut$numOut_n59$true<13> +- =_n5c<13> +.names _n5c<14> numOut$numOut_n59$true<14> +- =_n5c<14> +.names _n5c<15> numOut$numOut_n59$true<15> +- =_n5c<15> +.names _n5c<16> numOut$numOut_n59$true<16> +- =_n5c<16> +.names _n5c<17> numOut$numOut_n59$true<17> +- =_n5c<17> +.names _n5c<18> numOut$numOut_n59$true<18> +- =_n5c<18> +.names _n5c<19> numOut$numOut_n59$true<19> +- =_n5c<19> +.names _n5c<20> numOut$numOut_n59$true<20> +- =_n5c<20> +.names _n5c<21> numOut$numOut_n59$true<21> +- =_n5c<21> +.names _n5c<22> numOut$numOut_n59$true<22> +- =_n5c<22> +.names _n5c<23> numOut$numOut_n59$true<23> +- =_n5c<23> +.names _n5c<24> numOut$numOut_n59$true<24> +- =_n5c<24> +# numOut = {'b0, numOut [24 : 1]} +.names numOut<1> _n78<0> +- =numOut<1> +.names numOut<2> _n78<1> +- =numOut<2> +.names numOut<3> _n78<2> +- =numOut<3> +.names numOut<4> _n78<3> +- =numOut<4> +.names numOut<5> _n78<4> +- =numOut<5> +.names numOut<6> _n78<5> +- =numOut<6> +.names numOut<7> _n78<6> +- =numOut<7> +.names numOut<8> _n78<7> +- =numOut<8> +.names numOut<9> _n78<8> +- =numOut<9> +.names numOut<10> _n78<9> +- =numOut<10> +.names numOut<11> _n78<10> +- =numOut<11> +.names numOut<12> _n78<11> +- =numOut<12> +.names numOut<13> _n78<12> +- =numOut<13> +.names numOut<14> _n78<13> +- =numOut<14> +.names numOut<15> _n78<14> +- =numOut<15> +.names numOut<16> _n78<15> +- =numOut<16> +.names numOut<17> _n78<16> +- =numOut<17> +.names numOut<18> _n78<17> +- =numOut<18> +.names numOut<19> _n78<18> +- =numOut<19> +.names numOut<20> _n78<19> +- =numOut<20> +.names numOut<21> _n78<20> +- =numOut<21> +.names numOut<22> _n78<21> +- =numOut<22> +.names numOut<23> _n78<22> +- =numOut<23> +.names numOut<24> _n78<23> +- =numOut<24> +.names _n79 +0 +.names _n79 _n78<24> +- =_n79 +.names _n7a +0 +.names _n78<0> numOut$numOut_n77$false<0> +- =_n78<0> +.names _n78<1> numOut$numOut_n77$false<1> +- =_n78<1> +.names _n78<2> numOut$numOut_n77$false<2> +- =_n78<2> +.names _n78<3> numOut$numOut_n77$false<3> +- =_n78<3> +.names _n78<4> numOut$numOut_n77$false<4> +- =_n78<4> +.names _n78<5> numOut$numOut_n77$false<5> +- =_n78<5> +.names _n78<6> numOut$numOut_n77$false<6> +- =_n78<6> +.names _n78<7> numOut$numOut_n77$false<7> +- =_n78<7> +.names _n78<8> numOut$numOut_n77$false<8> +- =_n78<8> +.names _n78<9> numOut$numOut_n77$false<9> +- =_n78<9> +.names _n78<10> numOut$numOut_n77$false<10> +- =_n78<10> +.names _n78<11> numOut$numOut_n77$false<11> +- =_n78<11> +.names _n78<12> numOut$numOut_n77$false<12> +- =_n78<12> +.names _n78<13> numOut$numOut_n77$false<13> +- =_n78<13> +.names _n78<14> numOut$numOut_n77$false<14> +- =_n78<14> +.names _n78<15> numOut$numOut_n77$false<15> +- =_n78<15> +.names _n78<16> numOut$numOut_n77$false<16> +- =_n78<16> +.names _n78<17> numOut$numOut_n77$false<17> +- =_n78<17> +.names _n78<18> numOut$numOut_n77$false<18> +- =_n78<18> +.names _n78<19> numOut$numOut_n77$false<19> +- =_n78<19> +.names _n78<20> numOut$numOut_n77$false<20> +- =_n78<20> +.names _n78<21> numOut$numOut_n77$false<21> +- =_n78<21> +.names _n78<22> numOut$numOut_n77$false<22> +- =_n78<22> +.names _n78<23> numOut$numOut_n77$false<23> +- =_n78<23> +.names _n78<24> numOut$numOut_n77$false<24> +- =_n78<24> +# if/else (numOut [0]) +.names numOut<0> _n7d +.def 1 +0 0 +.names numOut$numOut_n59$true<0> numOut$numOut_n77$false<0> _n7d numOut$numOut$raw_n7c<0> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<1> numOut$numOut_n77$false<1> _n7d numOut$numOut$raw_n7c<1> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<2> numOut$numOut_n77$false<2> _n7d numOut$numOut$raw_n7c<2> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<3> numOut$numOut_n77$false<3> _n7d numOut$numOut$raw_n7c<3> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<4> numOut$numOut_n77$false<4> _n7d numOut$numOut$raw_n7c<4> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<5> numOut$numOut_n77$false<5> _n7d numOut$numOut$raw_n7c<5> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<6> numOut$numOut_n77$false<6> _n7d numOut$numOut$raw_n7c<6> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<7> numOut$numOut_n77$false<7> _n7d numOut$numOut$raw_n7c<7> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<8> numOut$numOut_n77$false<8> _n7d numOut$numOut$raw_n7c<8> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<9> numOut$numOut_n77$false<9> _n7d numOut$numOut$raw_n7c<9> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<10> numOut$numOut_n77$false<10> _n7d numOut$numOut$raw_n7c<10> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<11> numOut$numOut_n77$false<11> _n7d numOut$numOut$raw_n7c<11> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<12> numOut$numOut_n77$false<12> _n7d numOut$numOut$raw_n7c<12> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<13> numOut$numOut_n77$false<13> _n7d numOut$numOut$raw_n7c<13> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<14> numOut$numOut_n77$false<14> _n7d numOut$numOut$raw_n7c<14> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<15> numOut$numOut_n77$false<15> _n7d numOut$numOut$raw_n7c<15> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<16> numOut$numOut_n77$false<16> _n7d numOut$numOut$raw_n7c<16> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<17> numOut$numOut_n77$false<17> _n7d numOut$numOut$raw_n7c<17> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<18> numOut$numOut_n77$false<18> _n7d numOut$numOut$raw_n7c<18> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<19> numOut$numOut_n77$false<19> _n7d numOut$numOut$raw_n7c<19> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<20> numOut$numOut_n77$false<20> _n7d numOut$numOut$raw_n7c<20> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<21> numOut$numOut_n77$false<21> _n7d numOut$numOut$raw_n7c<21> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<22> numOut$numOut_n77$false<22> _n7d numOut$numOut$raw_n7c<22> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<23> numOut$numOut_n77$false<23> _n7d numOut$numOut$raw_n7c<23> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +.names numOut$numOut_n59$true<24> numOut$numOut_n77$false<24> _n7d numOut$numOut$raw_n7c<24> +0 - 1 0 +1 - 1 1 +- 0 0 0 +- 1 0 1 +# conflict arbitrators +.names _n57 _n99 +.def 0 + 1 1 + 0 1 +.names _n99 numOut$numOut$raw_n7c<0> numOut$numOut$raw_n7c<1> numOut$numOut$raw_n7c<2> numOut$numOut$raw_n7c<3> numOut$numOut$raw_n7c<4> numOut$numOut$raw_n7c<5> numOut$numOut$raw_n7c<6> numOut$numOut$raw_n7c<7> numOut$numOut$raw_n7c<8> numOut$numOut$raw_n7c<9> numOut$numOut$raw_n7c<10> numOut$numOut$raw_n7c<11> numOut$numOut$raw_n7c<12> numOut$numOut$raw_n7c<13> numOut$numOut$raw_n7c<14> numOut$numOut$raw_n7c<15> numOut$numOut$raw_n7c<16> numOut$numOut$raw_n7c<17> numOut$numOut$raw_n7c<18> numOut$numOut$raw_n7c<19> numOut$numOut$raw_n7c<20> numOut$numOut$raw_n7c<21> numOut$numOut$raw_n7c<22> numOut$numOut$raw_n7c<23> numOut$numOut$raw_n7c<24> numOut<0> numOut<1> numOut<2> numOut<3> numOut<4> numOut<5> numOut<6> numOut<7> numOut<8> numOut<9> numOut<10> numOut<11> numOut<12> numOut<13> numOut<14> numOut<15> numOut<16> numOut<17> numOut<18> numOut<19> numOut<20> numOut<21> numOut<22> numOut<23> numOut<24> -> _n9a<0> _n9a<1> _n9a<2> _n9a<3> _n9a<4> _n9a<5> _n9a<6> _n9a<7> _n9a<8> _n9a<9> _n9a<10> _n9a<11> _n9a<12> _n9a<13> _n9a<14> _n9a<15> _n9a<16> _n9a<17> _n9a<18> _n9a<19> _n9a<20> _n9a<21> _n9a<22> _n9a<23> _n9a<24> +1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =numOut$numOut$raw_n7c<0> =numOut$numOut$raw_n7c<1> =numOut$numOut$raw_n7c<2> =numOut$numOut$raw_n7c<3> =numOut$numOut$raw_n7c<4> =numOut$numOut$raw_n7c<5> =numOut$numOut$raw_n7c<6> =numOut$numOut$raw_n7c<7> =numOut$numOut$raw_n7c<8> =numOut$numOut$raw_n7c<9> =numOut$numOut$raw_n7c<10> =numOut$numOut$raw_n7c<11> =numOut$numOut$raw_n7c<12> =numOut$numOut$raw_n7c<13> =numOut$numOut$raw_n7c<14> =numOut$numOut$raw_n7c<15> =numOut$numOut$raw_n7c<16> =numOut$numOut$raw_n7c<17> =numOut$numOut$raw_n7c<18> =numOut$numOut$raw_n7c<19> =numOut$numOut$raw_n7c<20> =numOut$numOut$raw_n7c<21> =numOut$numOut$raw_n7c<22> =numOut$numOut$raw_n7c<23> =numOut$numOut$raw_n7c<24> +0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - =numOut<0> =numOut<1> =numOut<2> =numOut<3> =numOut<4> =numOut<5> =numOut<6> =numOut<7> =numOut<8> =numOut<9> =numOut<10> =numOut<11> =numOut<12> =numOut<13> =numOut<14> =numOut<15> =numOut<16> =numOut<17> =numOut<18> =numOut<19> =numOut<20> =numOut<21> =numOut<22> =numOut<23> =numOut<24> +.names tmp$raw_n32<0> tmp<0> +- =tmp$raw_n32<0> +.names tmp$raw_n32<1> tmp<1> +- =tmp$raw_n32<1> +.names tmp$raw_n32<2> tmp<2> +- =tmp$raw_n32<2> +.names tmp$raw_n32<3> tmp<3> +- =tmp$raw_n32<3> +.names tmp$raw_n32<4> tmp<4> +- =tmp$raw_n32<4> +.names tmp$raw_n32<5> tmp<5> +- =tmp$raw_n32<5> +.names tmp$raw_n32<6> tmp<6> +- =tmp$raw_n32<6> +.names tmp$raw_n32<7> tmp<7> +- =tmp$raw_n32<7> +.names tmp$raw_n32<8> tmp<8> +- =tmp$raw_n32<8> +.names tmp$raw_n32<9> tmp<9> +- =tmp$raw_n32<9> +.names tmp$raw_n32<10> tmp<10> +- =tmp$raw_n32<10> +.names tmp$raw_n32<11> tmp<11> +- =tmp$raw_n32<11> +.names tmp$raw_n32<12> tmp<12> +- =tmp$raw_n32<12> +.names tmp$raw_n32<13> tmp<13> +- =tmp$raw_n32<13> +.names tmp$raw_n32<14> tmp<14> +- =tmp$raw_n32<14> +.names tmp$raw_n32<15> tmp<15> +- =tmp$raw_n32<15> +.names tmp$raw_n32<16> tmp<16> +- =tmp$raw_n32<16> +.names tmp$raw_n32<17> tmp<17> +- =tmp$raw_n32<17> +.names tmp$raw_n32<18> tmp<18> +- =tmp$raw_n32<18> +.names tmp$raw_n32<19> tmp<19> +- =tmp$raw_n32<19> +.names tmp$raw_n32<20> tmp<20> +- =tmp$raw_n32<20> +.names tmp$raw_n32<21> tmp<21> +- =tmp$raw_n32<21> +.names tmp$raw_n32<22> tmp<22> +- =tmp$raw_n32<22> +.names tmp$raw_n32<23> tmp<23> +- =tmp$raw_n32<23> +.names tmp$raw_n32<24> tmp<24> +- =tmp$raw_n32<24> +.names tmp$raw_n32<25> tmp<25> +- =tmp$raw_n32<25> +.names tmp$raw_n32<26> tmp<26> +- =tmp$raw_n32<26> +# non-blocking assignments +# latches +.r numOut$raw_n30<0> numOut<0> +.def 0 +1 1 +.r numOut$raw_n30<1> numOut<1> +.def 0 +1 1 +.r numOut$raw_n30<2> numOut<2> +.def 0 +1 1 +.r numOut$raw_n30<3> numOut<3> +.def 0 +1 1 +.r numOut$raw_n30<4> numOut<4> +.def 0 +1 1 +.r numOut$raw_n30<5> numOut<5> +.def 0 +1 1 +.r numOut$raw_n30<6> numOut<6> +.def 0 +1 1 +.r numOut$raw_n30<7> numOut<7> +.def 0 +1 1 +.r numOut$raw_n30<8> numOut<8> +.def 0 +1 1 +.r numOut$raw_n30<9> numOut<9> +.def 0 +1 1 +.r numOut$raw_n30<10> numOut<10> +.def 0 +1 1 +.r numOut$raw_n30<11> numOut<11> +.def 0 +1 1 +.r numOut$raw_n30<12> numOut<12> +.def 0 +1 1 +.r numOut$raw_n30<13> numOut<13> +.def 0 +1 1 +.r numOut$raw_n30<14> numOut<14> +.def 0 +1 1 +.r numOut$raw_n30<15> numOut<15> +.def 0 +1 1 +.r numOut$raw_n30<16> numOut<16> +.def 0 +1 1 +.r numOut$raw_n30<17> numOut<17> +.def 0 +1 1 +.r numOut$raw_n30<18> numOut<18> +.def 0 +1 1 +.r numOut$raw_n30<19> numOut<19> +.def 0 +1 1 +.r numOut$raw_n30<20> numOut<20> +.def 0 +1 1 +.r numOut$raw_n30<21> numOut<21> +.def 0 +1 1 +.r numOut$raw_n30<22> numOut<22> +.def 0 +1 1 +.r numOut$raw_n30<23> numOut<23> +.def 0 +1 1 +.r numOut$raw_n30<24> numOut<24> +.def 0 +1 1 +.latch _n9a<0> numOut<0> +.latch _n9a<1> numOut<1> +.latch _n9a<2> numOut<2> +.latch _n9a<3> numOut<3> +.latch _n9a<4> numOut<4> +.latch _n9a<5> numOut<5> +.latch _n9a<6> numOut<6> +.latch _n9a<7> numOut<7> +.latch _n9a<8> numOut<8> +.latch _n9a<9> numOut<9> +.latch _n9a<10> numOut<10> +.latch _n9a<11> numOut<11> +.latch _n9a<12> numOut<12> +.latch _n9a<13> numOut<13> +.latch _n9a<14> numOut<14> +.latch _n9a<15> numOut<15> +.latch _n9a<16> numOut<16> +.latch _n9a<17> numOut<17> +.latch _n9a<18> numOut<18> +.latch _n9a<19> numOut<19> +.latch _n9a<20> numOut<20> +.latch _n9a<21> numOut<21> +.latch _n9a<22> numOut<22> +.latch _n9a<23> numOut<23> +.latch _n9a<24> numOut<24> +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/restruct/check_result =================================================================== --- vis_dev/vis-2.1/examples/restruct/check_result (revision 11) +++ vis_dev/vis-2.1/examples/restruct/check_result (revision 11) @@ -0,0 +1,9 @@ +** restr info: Number of Equivalence Classes = 5 +** synth info: Total number of literals = 21 +Networks are sequentially equivalent. +** restr info: Number of Equivalence Classes = 254 +** synth info: Total number of literals = 71 +Networks are sequentially equivalent. +** restr info: Number of Equivalence Classes = 45 +** synth info: Total number of literals = 288 +Networks are sequentially equivalent. Index: vis_dev/vis-2.1/examples/restruct/check_script =================================================================== --- vis_dev/vis-2.1/examples/restruct/check_script (revision 11) +++ vis_dev/vis-2.1/examples/restruct/check_script (revision 11) @@ -0,0 +1,21 @@ +read_blif s27.blif +flatten_hierarchy +static_order +restruct_fsm -E -D s27 -s cproj +seq_verify -b s27.ml.blif + +read_blif tlc.blif +flatten_hierarchy +static_order +restruct_fsm -E -D tlc -s fanin +seq_verify -b tlc.ml.blif + +read_blif_mv ibuf.mv +flatten_hierarchy +static_order +restruct_fsm -E -D ibuf -s faninout +seq_verify -b ibuf.ml.blif + +!rm *.ml.blif + +quit -s Index: vis_dev/vis-2.1/examples/restruct/ibuf.mv =================================================================== --- vis_dev/vis-2.1/examples/restruct/ibuf.mv (revision 11) +++ vis_dev/vis-2.1/examples/restruct/ibuf.mv (revision 11) @@ -0,0 +1,677 @@ +# vl2mv ibuf.v +# version: 0.2 +# date: () +.model iqc +# I/O ports +.outputs load2<0> load2<1> +.outputs issue0<0> issue0<1> issue0<2> +.outputs load1<0> load1<1> +.inputs iqLoads<0> iqLoads<1> +.outputs issue1<0> issue1<1> issue1<2> +.outputs load0<0> load0<1> +.inputs exeReady<0> exeReady<1> +.outputs valid<0> valid<1> valid<2> +.inputs flush<0> flush<1> flush<2> +.inputs opsReady<0> opsReady<1> opsReady<2> +# qAge = 'b000 +.names _n1<0> +0 +.names _n1<1> +0 +.names _n1<2> +0 +.names _n1<0> qAge$raw_n0<0> +- =_n1<0> +.names _n1<1> qAge$raw_n0<1> +- =_n1<1> +.names _n1<2> qAge$raw_n0<2> +- =_n1<2> +# valid = 'b000 +.names _n3<0> +0 +.names _n3<1> +0 +.names _n3<2> +0 +.names _n3<0> valid$raw_n2<0> +- =_n3<0> +.names _n3<1> valid$raw_n2<1> +- =_n3<1> +.names _n3<2> valid$raw_n2<2> +- =_n3<2> +# non-blocking assignments for initial +# assign load0 [0] = ~valid [0] & iqLoads [0] +.names valid<0> _n5<0> +0 1 +1 0 +# ~valid [0] & iqLoads [0] +.names _n5<0> iqLoads<0> _n6<0> +.def 0 +1 1 1 +.names _n6<0> load0$raw_n4<0> +- =_n6<0> +# assign load0 [1] = ~valid [0] & ~iqLoads [0] & iqLoads [1] +.names valid<0> _n8<0> +0 1 +1 0 +.names iqLoads<0> _n9<0> +0 1 +1 0 +# ~valid [0] & ~iqLoads [0] +.names _n8<0> _n9<0> _na<0> +.def 0 +1 1 1 +# ~valid [0] & ~iqLoads [0] & iqLoads [1] +.names _na<0> iqLoads<1> _nb<0> +.def 0 +1 1 1 +.names _nb<0> load0$raw_n7<1> +- =_nb<0> +# assign load1 [0] = ~valid [1] & valid [0] & iqLoads [0] +.names valid<1> _nd<1> +0 1 +1 0 +# ~valid [1] & valid [0] +.names _nd<1> valid<0> _ne<0> +.def 0 +1 1 1 +# ~valid [1] & valid [0] & iqLoads [0] +.names _ne<0> iqLoads<0> _nf<0> +.def 0 +1 1 1 +.names _nf<0> load1$raw_nc<0> +- =_nf<0> +# assign load1 [1] = ~valid [1] & iqLoads [1] & ~(load0 [1] | load1 [0]) +.names valid<1> _n11<1> +0 1 +1 0 +# ~valid [1] & iqLoads [1] +.names _n11<1> iqLoads<1> _n12<0> +.def 0 +1 1 1 +# load0 [1] | load1 [0] +.names load0<1> load1<0> _n13<0> +.def 1 +0 0 0 +.names _n13<0> _n14<0> +0 1 +1 0 +# ~valid [1] & iqLoads [1] & ~(load0 [1] | load1 [0]) +.names _n12<0> _n14<0> _n15<0> +.def 0 +1 1 1 +.names _n15<0> load1$raw_n10<1> +- =_n15<0> +# assign load2 [0] = ~valid [2] & valid [1] & valid [0] & iqLoads [0] +.names valid<2> _n17<2> +0 1 +1 0 +# ~valid [2] & valid [1] +.names _n17<2> valid<1> _n18<0> +.def 0 +1 1 1 +# ~valid [2] & valid [1] & valid [0] +.names _n18<0> valid<0> _n19<0> +.def 0 +1 1 1 +# ~valid [2] & valid [1] & valid [0] & iqLoads [0] +.names _n19<0> iqLoads<0> _n1a<0> +.def 0 +1 1 1 +.names _n1a<0> load2$raw_n16<0> +- =_n1a<0> +# assign load2 [1] = ~valid [2] & iqLoads [1] & ~(load2 [0] | load0 [1] | load1 [1]) +.names valid<2> _n1c<2> +0 1 +1 0 +# ~valid [2] & iqLoads [1] +.names _n1c<2> iqLoads<1> _n1d<0> +.def 0 +1 1 1 +# load2 [0] | load0 [1] +.names load2<0> load0<1> _n1e<0> +.def 1 +0 0 0 +# load2 [0] | load0 [1] | load1 [1] +.names _n1e<0> load1<1> _n1f<0> +.def 1 +0 0 0 +.names _n1f<0> _n20<0> +0 1 +1 0 +# ~valid [2] & iqLoads [1] & ~(load2 [0] | load0 [1] | load1 [1]) +.names _n1d<0> _n20<0> _n21<0> +.def 0 +1 1 1 +.names _n21<0> load2$raw_n1b<1> +- =_n21<0> +# assign issue0 [0] = exeReady [0] & opsReady [0] & valid [0] & (qAge [0] | ~opsReady [1]) & (qAge [1] | ~opsReady [2]) +# exeReady [0] & opsReady [0] +.names exeReady<0> opsReady<0> _n23<0> +.def 0 +1 1 1 +# exeReady [0] & opsReady [0] & valid [0] +.names _n23<0> valid<0> _n24<0> +.def 0 +1 1 1 +.names opsReady<1> _n25<1> +0 1 +1 0 +# qAge [0] | ~opsReady [1] +.names qAge<0> _n25<1> _n26<0> +.def 1 +0 0 0 +# exeReady [0] & opsReady [0] & valid [0] & (qAge [0] | ~opsReady [1]) +.names _n24<0> _n26<0> _n27<0> +.def 0 +1 1 1 +.names opsReady<2> _n28<2> +0 1 +1 0 +# qAge [1] | ~opsReady [2] +.names qAge<1> _n28<2> _n29<0> +.def 1 +0 0 0 +# exeReady [0] & opsReady [0] & valid [0] & (qAge [0] | ~opsReady [1]) & (qAge [1] | ~opsReady [2]) +.names _n27<0> _n29<0> _n2a<0> +.def 0 +1 1 1 +.names _n2a<0> issue0$raw_n22<0> +- =_n2a<0> +# assign issue0 [1] = exeReady [0] & opsReady [1] & valid [1] & (~qAge [0] | ~opsReady [0]) & (qAge [2] | ~opsReady [2]) +# exeReady [0] & opsReady [1] +.names exeReady<0> opsReady<1> _n2c<0> +.def 0 +1 1 1 +# exeReady [0] & opsReady [1] & valid [1] +.names _n2c<0> valid<1> _n2d<0> +.def 0 +1 1 1 +.names qAge<0> _n2e<0> +0 1 +1 0 +.names opsReady<0> _n2f<0> +0 1 +1 0 +# ~qAge [0] | ~opsReady [0] +.names _n2e<0> _n2f<0> _n30<0> +.def 1 +0 0 0 +# exeReady [0] & opsReady [1] & valid [1] & (~qAge [0] | ~opsReady [0]) +.names _n2d<0> _n30<0> _n31<0> +.def 0 +1 1 1 +.names opsReady<2> _n32<2> +0 1 +1 0 +# qAge [2] | ~opsReady [2] +.names qAge<2> _n32<2> _n33<0> +.def 1 +0 0 0 +# exeReady [0] & opsReady [1] & valid [1] & (~qAge [0] | ~opsReady [0]) & (qAge [2] | ~opsReady [2]) +.names _n31<0> _n33<0> _n34<0> +.def 0 +1 1 1 +.names _n34<0> issue0$raw_n2b<1> +- =_n34<0> +# assign issue0 [2] = exeReady [0] & opsReady [2] & valid [2] & (~qAge [1] | ~opsReady [0]) & (qAge [2] | ~opsReady [1]) +# exeReady [0] & opsReady [2] +.names exeReady<0> opsReady<2> _n36<0> +.def 0 +1 1 1 +# exeReady [0] & opsReady [2] & valid [2] +.names _n36<0> valid<2> _n37<0> +.def 0 +1 1 1 +.names qAge<1> _n38<1> +0 1 +1 0 +.names opsReady<0> _n39<0> +0 1 +1 0 +# ~qAge [1] | ~opsReady [0] +.names _n38<1> _n39<0> _n3a<0> +.def 1 +0 0 0 +# exeReady [0] & opsReady [2] & valid [2] & (~qAge [1] | ~opsReady [0]) +.names _n37<0> _n3a<0> _n3b<0> +.def 0 +1 1 1 +.names opsReady<1> _n3c<1> +0 1 +1 0 +# qAge [2] | ~opsReady [1] +.names qAge<2> _n3c<1> _n3d<0> +.def 1 +0 0 0 +# exeReady [0] & opsReady [2] & valid [2] & (~qAge [1] | ~opsReady [0]) & (qAge [2] | ~opsReady [1]) +.names _n3b<0> _n3d<0> _n3e<0> +.def 0 +1 1 1 +.names _n3e<0> issue0$raw_n35<2> +- =_n3e<0> +# assign issue1 [0] = exeReady [1] & opsReady [0] & valid [0] & (qAge [0] | ~opsReady [1] | issue0 [1]) & (qAge [1] | ~opsReady [2] | issue0 [2]) & ~issue0 [0] +# exeReady [1] & opsReady [0] +.names exeReady<1> opsReady<0> _n40<0> +.def 0 +1 1 1 +# exeReady [1] & opsReady [0] & valid [0] +.names _n40<0> valid<0> _n41<0> +.def 0 +1 1 1 +.names opsReady<1> _n42<1> +0 1 +1 0 +# qAge [0] | ~opsReady [1] +.names qAge<0> _n42<1> _n43<0> +.def 1 +0 0 0 +# qAge [0] | ~opsReady [1] | issue0 [1] +.names _n43<0> issue0<1> _n44<0> +.def 1 +0 0 0 +# exeReady [1] & opsReady [0] & valid [0] & (qAge [0] | ~opsReady [1] | issue0 [1]) +.names _n41<0> _n44<0> _n45<0> +.def 0 +1 1 1 +.names opsReady<2> _n46<2> +0 1 +1 0 +# qAge [1] | ~opsReady [2] +.names qAge<1> _n46<2> _n47<0> +.def 1 +0 0 0 +# qAge [1] | ~opsReady [2] | issue0 [2] +.names _n47<0> issue0<2> _n48<0> +.def 1 +0 0 0 +# exeReady [1] & opsReady [0] & valid [0] & (qAge [0] | ~opsReady [1] | issue0 [1]) & (qAge [1] | ~opsReady [2] | issue0 [2]) +.names _n45<0> _n48<0> _n49<0> +.def 0 +1 1 1 +.names issue0<0> _n4a<0> +0 1 +1 0 +# exeReady [1] & opsReady [0] & valid [0] & (qAge [0] | ~opsReady [1] | issue0 [1]) & (qAge [1] | ~opsReady [2] | issue0 [2]) & ~issue0 [0] +.names _n49<0> _n4a<0> _n4b<0> +.def 0 +1 1 1 +.names _n4b<0> issue1$raw_n3f<0> +- =_n4b<0> +# assign issue1 [1] = exeReady [1] & opsReady [1] & valid [1] & (~qAge [0] | ~opsReady [0] | issue0 [0]) & (qAge [2] | ~opsReady [2] | issue0 [2]) & ~issue0 [1] +# exeReady [1] & opsReady [1] +.names exeReady<1> opsReady<1> _n4d<0> +.def 0 +1 1 1 +# exeReady [1] & opsReady [1] & valid [1] +.names _n4d<0> valid<1> _n4e<0> +.def 0 +1 1 1 +.names qAge<0> _n4f<0> +0 1 +1 0 +.names opsReady<0> _n50<0> +0 1 +1 0 +# ~qAge [0] | ~opsReady [0] +.names _n4f<0> _n50<0> _n51<0> +.def 1 +0 0 0 +# ~qAge [0] | ~opsReady [0] | issue0 [0] +.names _n51<0> issue0<0> _n52<0> +.def 1 +0 0 0 +# exeReady [1] & opsReady [1] & valid [1] & (~qAge [0] | ~opsReady [0] | issue0 [0]) +.names _n4e<0> _n52<0> _n53<0> +.def 0 +1 1 1 +.names opsReady<2> _n54<2> +0 1 +1 0 +# qAge [2] | ~opsReady [2] +.names qAge<2> _n54<2> _n55<0> +.def 1 +0 0 0 +# qAge [2] | ~opsReady [2] | issue0 [2] +.names _n55<0> issue0<2> _n56<0> +.def 1 +0 0 0 +# exeReady [1] & opsReady [1] & valid [1] & (~qAge [0] | ~opsReady [0] | issue0 [0]) & (qAge [2] | ~opsReady [2] | issue0 [2]) +.names _n53<0> _n56<0> _n57<0> +.def 0 +1 1 1 +.names issue0<1> _n58<1> +0 1 +1 0 +# exeReady [1] & opsReady [1] & valid [1] & (~qAge [0] | ~opsReady [0] | issue0 [0]) & (qAge [2] | ~opsReady [2] | issue0 [2]) & ~issue0 [1] +.names _n57<0> _n58<1> _n59<0> +.def 0 +1 1 1 +.names _n59<0> issue1$raw_n4c<1> +- =_n59<0> +# assign issue1 [2] = exeReady [1] & opsReady [2] & valid [2] & (~qAge [1] | ~opsReady [0] | issue0 [0]) & (qAge [2] | ~opsReady [1] | issue0 [1]) & ~issue0 [2] +# exeReady [1] & opsReady [2] +.names exeReady<1> opsReady<2> _n5b<0> +.def 0 +1 1 1 +# exeReady [1] & opsReady [2] & valid [2] +.names _n5b<0> valid<2> _n5c<0> +.def 0 +1 1 1 +.names qAge<1> _n5d<1> +0 1 +1 0 +.names opsReady<0> _n5e<0> +0 1 +1 0 +# ~qAge [1] | ~opsReady [0] +.names _n5d<1> _n5e<0> _n5f<0> +.def 1 +0 0 0 +# ~qAge [1] | ~opsReady [0] | issue0 [0] +.names _n5f<0> issue0<0> _n60<0> +.def 1 +0 0 0 +# exeReady [1] & opsReady [2] & valid [2] & (~qAge [1] | ~opsReady [0] | issue0 [0]) +.names _n5c<0> _n60<0> _n61<0> +.def 0 +1 1 1 +.names opsReady<1> _n62<1> +0 1 +1 0 +# qAge [2] | ~opsReady [1] +.names qAge<2> _n62<1> _n63<0> +.def 1 +0 0 0 +# qAge [2] | ~opsReady [1] | issue0 [1] +.names _n63<0> issue0<1> _n64<0> +.def 1 +0 0 0 +# exeReady [1] & opsReady [2] & valid [2] & (~qAge [1] | ~opsReady [0] | issue0 [0]) & (qAge [2] | ~opsReady [1] | issue0 [1]) +.names _n61<0> _n64<0> _n65<0> +.def 0 +1 1 1 +.names issue0<2> _n66<2> +0 1 +1 0 +# exeReady [1] & opsReady [2] & valid [2] & (~qAge [1] | ~opsReady [0] | issue0 [0]) & (qAge [2] | ~opsReady [1] | issue0 [1]) & ~issue0 [2] +.names _n65<0> _n66<2> _n67<0> +.def 0 +1 1 1 +.names _n67<0> issue1$raw_n5a<2> +- =_n67<0> +# assign nv0 = ~flush [0] & (valid [0] & ~(issue0 [0] | issue1 [0]) | load0 ) +.names flush<0> _n69<0> +0 1 +1 0 +# issue0 [0] | issue1 [0] +.names issue0<0> issue1<0> _n6a<0> +.def 1 +0 0 0 +.names _n6a<0> _n6b<0> +0 1 +1 0 +# valid [0] & ~(issue0 [0] | issue1 [0]) +.names valid<0> _n6b<0> _n6c<0> +.def 0 +1 1 1 +# valid [0] & ~(issue0 [0] | issue1 [0]) | load0 +.names _n6c<0> load0<0> _n6d<0> +.def 1 +0 0 0 +.names load0<1> _n6d<1> +0 0 +1 1 +# ~flush [0] & (valid [0] & ~(issue0 [0] | issue1 [0]) | load0 ) +.names _n69<0> _n6d<0> _n6e<0> +.def 0 +1 1 1 +.names _n6d<1> _n6e<1> +0 0 +1 1 +.names _n6e<0> nv0$raw_n68 +- =_n6e<0> +# assign nv1 = ~flush [1] & (valid [1] & ~(issue0 [1] | issue1 [1]) | load1 ) +.names flush<1> _n70<1> +0 1 +1 0 +# issue0 [1] | issue1 [1] +.names issue0<1> issue1<1> _n71<0> +.def 1 +0 0 0 +.names _n71<0> _n72<0> +0 1 +1 0 +# valid [1] & ~(issue0 [1] | issue1 [1]) +.names valid<1> _n72<0> _n73<0> +.def 0 +1 1 1 +# valid [1] & ~(issue0 [1] | issue1 [1]) | load1 +.names _n73<0> load1<0> _n74<0> +.def 1 +0 0 0 +.names load1<1> _n74<1> +0 0 +1 1 +# ~flush [1] & (valid [1] & ~(issue0 [1] | issue1 [1]) | load1 ) +.names _n70<1> _n74<0> _n75<0> +.def 0 +1 1 1 +.names _n74<1> _n75<1> +0 0 +1 1 +.names _n75<0> nv1$raw_n6f +- =_n75<0> +# assign nv2 = ~flush [2] & (valid [2] & ~(issue0 [2] | issue1 [2]) | load2 ) +.names flush<2> _n77<2> +0 1 +1 0 +# issue0 [2] | issue1 [2] +.names issue0<2> issue1<2> _n78<0> +.def 1 +0 0 0 +.names _n78<0> _n79<0> +0 1 +1 0 +# valid [2] & ~(issue0 [2] | issue1 [2]) +.names valid<2> _n79<0> _n7a<0> +.def 0 +1 1 1 +# valid [2] & ~(issue0 [2] | issue1 [2]) | load2 +.names _n7a<0> load2<0> _n7b<0> +.def 1 +0 0 0 +.names load2<1> _n7b<1> +0 0 +1 1 +# ~flush [2] & (valid [2] & ~(issue0 [2] | issue1 [2]) | load2 ) +.names _n77<2> _n7b<0> _n7c<0> +.def 0 +1 1 1 +.names _n7b<1> _n7c<1> +0 0 +1 1 +.names _n7c<0> nv2$raw_n76 +- =_n7c<0> +# valid [0] = nv0 +.names nv0 valid$raw_n7d<0> +- =nv0 +.names _n7e +0 +.names valid<1> valid$raw_n7d<1> +- =valid<1> +.names valid<2> valid$raw_n7d<2> +- =valid<2> +# valid [1] = nv1 +.names nv1 valid$raw_n7f<1> +- =nv1 +.names _n80 +0 +.names valid$raw_n7d<0> valid$raw_n7f<0> +- =valid$raw_n7d<0> +.names valid$raw_n7d<2> valid$raw_n7f<2> +- =valid$raw_n7d<2> +# valid [2] = nv2 +.names nv2 valid$raw_n81<2> +- =nv2 +.names _n82 +0 +.names valid$raw_n7f<0> valid$raw_n81<0> +- =valid$raw_n7f<0> +.names valid$raw_n7f<1> valid$raw_n81<1> +- =valid$raw_n7f<1> +# qAge [0] = nv0 & (~nv1 | qAge [0] | ~valid [1]) +.names nv1 _n84 +0 1 +1 0 +# ~nv1 | qAge [0] +.names _n84 qAge<0> _n85<0> +.def 1 +0 0 0 +.names valid$raw_n81<1> _n86<1> +0 1 +1 0 +# ~nv1 | qAge [0] | ~valid [1] +.names _n85<0> _n86<1> _n87<0> +.def 1 +0 0 0 +# nv0 & (~nv1 | qAge [0] | ~valid [1]) +.names nv0 _n87<0> _n88<0> +.def 0 +1 1 1 +.names _n88<0> qAge$raw_n83<0> +- =_n88<0> +.names qAge<1> qAge$raw_n83<1> +- =qAge<1> +.names qAge<2> qAge$raw_n83<2> +- =qAge<2> +# qAge [1] = nv0 & (~nv2 | qAge [1] | ~valid [2]) +.names nv2 _n8a +0 1 +1 0 +# ~nv2 | qAge [1] +.names _n8a qAge$raw_n83<1> _n8b<1> +.def 1 +0 0 0 +.names valid$raw_n81<2> _n8c<2> +0 1 +1 0 +# ~nv2 | qAge [1] | ~valid [2] +.names _n8b<1> _n8c<2> _n8d<0> +.def 1 +0 0 0 +# nv0 & (~nv2 | qAge [1] | ~valid [2]) +.names nv0 _n8d<0> _n8e<0> +.def 0 +1 1 1 +.names _n8e<0> qAge$raw_n89<1> +- =_n8e<0> +.names qAge$raw_n83<0> qAge$raw_n89<0> +- =qAge$raw_n83<0> +.names qAge$raw_n83<2> qAge$raw_n89<2> +- =qAge$raw_n83<2> +# qAge [2] = nv1 & (~nv2 | qAge [2] | ~valid [2]) +.names nv2 _n90 +0 1 +1 0 +# ~nv2 | qAge [2] +.names _n90 qAge$raw_n89<2> _n91<2> +.def 1 +0 0 0 +.names valid$raw_n81<2> _n92<2> +0 1 +1 0 +# ~nv2 | qAge [2] | ~valid [2] +.names _n91<2> _n92<2> _n93<0> +.def 1 +0 0 0 +# nv1 & (~nv2 | qAge [2] | ~valid [2]) +.names nv1 _n93<0> _n94<0> +.def 0 +1 1 1 +.names _n94<0> qAge$raw_n8f<2> +- =_n94<0> +.names qAge$raw_n89<0> qAge$raw_n8f<0> +- =qAge$raw_n89<0> +.names qAge$raw_n89<1> qAge$raw_n8f<1> +- =qAge$raw_n89<1> +# conflict arbitrators +.names load2$raw_n16<0> load2<0> +- =load2$raw_n16<0> +.names load2$raw_n1b<1> load2<1> +- =load2$raw_n1b<1> +.names issue0$raw_n22<0> issue0<0> +- =issue0$raw_n22<0> +.names issue0$raw_n2b<1> issue0<1> +- =issue0$raw_n2b<1> +.names issue0$raw_n35<2> issue0<2> +- =issue0$raw_n35<2> +.names load1$raw_nc<0> load1<0> +- =load1$raw_nc<0> +.names load1$raw_n10<1> load1<1> +- =load1$raw_n10<1> +.names issue1$raw_n3f<0> issue1<0> +- =issue1$raw_n3f<0> +.names issue1$raw_n4c<1> issue1<1> +- =issue1$raw_n4c<1> +.names issue1$raw_n5a<2> issue1<2> +- =issue1$raw_n5a<2> +.names load0$raw_n4<0> load0<0> +- =load0$raw_n4<0> +.names load0$raw_n7<1> load0<1> +- =load0$raw_n7<1> +.names _n95 +.def 0 + 1 + 1 + 1 +.names _n95 qAge$raw_n8f<0> qAge$raw_n8f<1> qAge$raw_n8f<2> -> _n96<0> _n96<1> _n96<2> +.def 0 0 0 +1 - - - =qAge$raw_n8f<0> =qAge$raw_n8f<1> =qAge$raw_n8f<2> +.names nv0$raw_n68 nv0 +0 0 +1 1 +.names nv1$raw_n6f nv1 +0 0 +1 1 +.names _n97 +.def 0 + 1 + 1 + 1 +.names _n97 valid$raw_n81<0> valid$raw_n81<1> valid$raw_n81<2> -> _n98<0> _n98<1> _n98<2> +.def 0 0 0 +1 - - - =valid$raw_n81<0> =valid$raw_n81<1> =valid$raw_n81<2> +.names nv2$raw_n76 nv2 +0 0 +1 1 +# non-blocking assignments +# latches +.r qAge$raw_n0<0> qAge<0> +.def 0 +1 1 +.r qAge$raw_n0<1> qAge<1> +.def 0 +1 1 +.r qAge$raw_n0<2> qAge<2> +.def 0 +1 1 +.latch _n96<0> qAge<0> +.latch _n96<1> qAge<1> +.latch _n96<2> qAge<2> +.r valid$raw_n2<0> valid<0> +.def 0 +1 1 +.r valid$raw_n2<1> valid<1> +.def 0 +1 1 +.r valid$raw_n2<2> valid<2> +.def 0 +1 1 +.latch _n98<0> valid<0> +.latch _n98<1> valid<1> +.latch _n98<2> valid<2> +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/restruct/s27.blif =================================================================== --- vis_dev/vis-2.1/examples/restruct/s27.blif (revision 11) +++ vis_dev/vis-2.1/examples/restruct/s27.blif (revision 11) @@ -0,0 +1,31 @@ +.model s27 +.inputs G0 G1 G2 G3 +.outputs G17 +.wire_load_slope 0.00 +.latch G10 G5 0 +.latch G11 G6 0 +.latch G13 G7 0 +.names G11 G17 +0 1 +.names G14 G11 G10 +00 1 +.names G5 G9 G11 +00 1 +.names G2 G12 G13 +00 1 +.names G0 G14 +0 1 +.names G14 G6 G8 +11 1 +.names G1 G7 G12 +00 1 +.names G12 G8 G15 +1- 1 +-1 1 +.names G3 G8 G16 +1- 1 +-1 1 +.names G16 G15 G9 +0- 1 +-0 1 +.end Index: vis_dev/vis-2.1/examples/restruct/tlc.blif =================================================================== --- vis_dev/vis-2.1/examples/restruct/tlc.blif (revision 11) +++ vis_dev/vis-2.1/examples/restruct/tlc.blif (revision 11) @@ -0,0 +1,172 @@ +.model tlc +.inputs in1 +.inputs in2 +#.inputs in3 +.outputs out11 +.outputs out12 +.outputs out13 +.outputs out14 +.outputs out15 +.latch out1 in4 0 +.latch out2 in5 0 +.latch out3 in6 0 +.latch out4 in7 0 +#.latch out5 in8 0 +.latch out6 in9 0 +.latch out7 in10 0 +.latch out8 in11 0 +.latch out9 in12 0 +.latch out10 in13 0 +.names in1 in1__ +0 1 +#.names in3 in3__ +#0 1 +.names in4 in4__ +0 1 +.names in5 in5__ +0 1 +.names in6 in6__ +0 1 +.names in7 in7__ +0 1 +#.names in8 in8__ +#0 1 +.names in1__ in4__ in5__ in6__ in7 g_1and1 +11111 1 +.names in1__ in4 in5 in6__ in7__ g_1and2 +11111 1 +.names in1__ in4 in5 in6 in7__ g_1and3 +11111 1 +#.names in1__ in3 in8__ g_1and4 +#111 1 +#.names in1__ in3__ in8 g_1and5 +#111 1 +.names in1__ in4 in5__ in7__ g_1and6 +1111 1 +.names in1__ in4__ in5 in7__ g_1and7 +1111 1 +.names in1__ in5__ in6 in7__ g_1and8 +1111 1 +.names in1__ in4__ in6 in7__ g_1and9 +1111 1 +.names in1__ in4__ in7__ g_1and10 +111 1 +.names g_1and1 g_1and10 out1 +00 0 +.names g_1and6 g_1and7 out2 +00 0 +.names g_1and2 g_1and8 g_1and9 out3 +000 0 +.names g_1and1 g_1and3 out4 +00 0 +#.names g_1and4 g_1and5 out5 +#00 0 +.names in1 gin1__ +0 1 +.names in2 gin2__ +0 1 +.names in4 gin4__ +0 1 +.names in5 gin5__ +0 1 +.names in6 gin6__ +0 1 +.names in7 gin7__ +0 1 +.names in9 gin9__ +0 1 +.names in10 gin10__ +0 1 +.names in11 gin11__ +0 1 +.names in12 gin12__ +0 1 +.names in13 gin13__ +0 1 +.names gin1__ gin4__ gin5__ gin6__ gin9__ in12 g_2and1 +111111 1 +.names gin1__ gin4__ gin5__ gin6__ gin9__ in11 g_2and2 +111111 1 +.names gin1__ gin4__ gin5__ gin6__ gin9__ in13 g_2and3 +111111 1 +.names gin1__ gin4__ gin5__ gin6__ gin9__ in10 g_2and4 +111111 1 +.names gin1__ in6 in7 in10 in11 gin12__ gin13__ g_2and5 +1111111 1 +.names gin1__ in5 in7 in10 in11 gin12__ gin13__ g_2and6 +1111111 1 +.names gin1__ in4 in7 in10 in11 gin12__ gin13__ g_2and7 +1111111 1 +.names gin1__ in6 in7 in10 in11 in12 gin13__ g_2and8 +1111111 1 +.names gin1__ in5 in7 in10 in11 in12 gin13__ g_2and9 +1111111 1 +.names gin1__ in4 in7 in10 in11 in12 gin13__ g_2and10 +1111111 1 +.names gin1__ in6 in7 gin10__ gin11__ gin12__ in13 g_2and11 +1111111 1 +.names gin1__ in5 in7 gin10__ gin11__ gin12__ in13 g_2and12 +1111111 1 +.names gin1__ in4 in7 gin10__ gin11__ gin12__ in13 g_2and13 +1111111 1 +.names gin1__ in9 in10 in11 gin12__ gin13__ g_2and14 +111111 1 +.names gin1__ in6 in7 in10 gin11__ gin13__ g_2and15 +111111 1 +.names gin1__ in5 in7 in10 gin11__ gin13__ g_2and16 +111111 1 +.names gin1__ in4 in7 in10 gin11__ gin13__ g_2and17 +111111 1 +.names gin1__ in9 in10 in11 in12 gin13__ g_2and18 +111111 1 +.names gin1__ in9 gin10__ gin11__ gin12__ in13 g_2and19 +111111 1 +.names gin1__ in9 in10 gin11__ gin13__ g_2and20 +11111 1 +.names gin1__ gin10__ in12 gin13__ g_2and21 +1111 1 +.names gin1__ in6 in7 gin10__ gin13__ g_2and22 +11111 1 +.names gin1__ in5 in7 gin10__ gin13__ g_2and23 +11111 1 +.names gin1__ in4 in7 gin10__ gin13__ g_2and24 +11111 1 +.names gin1__ gin7__ gin9__ in12 g_2and25 +1111 1 +.names gin1__ gin7__ gin9__ in11 g_2and26 +1111 1 +.names gin1__ gin7__ gin9__ in13 g_2and27 +1111 1 +.names gin1__ gin2__ in9 g_2and28 +111 1 +.names gin1__ in2 gin9__ g_2and29 +111 1 +.names gin1__ gin7__ gin9__ in10 g_2and30 +1111 1 +.names gin1__ gin11__ in12 gin13__ g_2and31 +1111 1 +.names gin1__ in9 gin10__ gin13__ g_2and32 +1111 1 +.names gin1__ gin10__ in11 gin13__ g_2and33 +1111 1 +.names g_2and28 g_2and29 out6 +00 0 +.names g_2and4 g_2and11 g_2and12 g_2and13 g_2and19 g_2and22 g_2and23 g_2and24 g_2and30 g_2and32 out7 +0000000000 0 +.names g_2and2 g_2and15 g_2and16 g_2and17 g_2and20 g_2and26 g_2and33 out8 +0000000 0 +.names g_2and1 g_2and5 g_2and6 g_2and7 g_2and14 g_2and21 g_2and25 g_2and31 out9 +00000000 0 +.names g_2and3 g_2and8 g_2and9 g_2and10 g_2and11 g_2and12 g_2and13 g_2and18 g_2and19 g_2and27 out10 +0000000000 0 +.names g_2and28 g_2and29 out11 +00 0 +.names g_2and4 g_2and11 g_2and12 g_2and13 g_2and19 g_2and22 g_2and23 g_2and24 g_2and30 g_2and32 out12 +0000000000 0 +.names g_2and2 g_2and15 g_2and16 g_2and17 g_2and20 g_2and26 g_2and33 out13 +0000000 0 +.names g_2and1 g_2and5 g_2and6 g_2and7 g_2and14 g_2and21 g_2and25 g_2and31 out14 +00000000 0 +.names g_2and3 g_2and8 g_2and9 g_2and10 g_2and11 g_2and12 g_2and13 g_2and18 g_2and19 g_2and27 out15 +0000000000 0 +.end Index: vis_dev/vis-2.1/examples/s1269/check_result =================================================================== --- vis_dev/vis-2.1/examples/s1269/check_result (revision 11) +++ vis_dev/vis-2.1/examples/s1269/check_result (revision 11) @@ -0,0 +1,2 @@ +computation depth = 22 +reachable states = 1.13134e+09 Index: vis_dev/vis-2.1/examples/s1269/check_script =================================================================== --- vis_dev/vis-2.1/examples/s1269/check_script (revision 11) +++ vis_dev/vis-2.1/examples/s1269/check_script (revision 11) @@ -0,0 +1,10 @@ +read_blif s1269.blif +flatten_hierarchy +static_order -s input_and_latch s1269.ord +#dvo -e sift +build_partition_mdds inout +set hd_partial_image_threshold 0 +set hd_partial_image_size 0 +compute_reach -v 1 -A 1 +time +quit -s Index: vis_dev/vis-2.1/examples/s1269/s1269.blif =================================================================== --- vis_dev/vis-2.1/examples/s1269/s1269.blif (revision 11) +++ vis_dev/vis-2.1/examples/s1269/s1269.blif (revision 11) @@ -0,0 +1,1185 @@ +# 18 inputs +# 10 outputs +# 37 D-type flipflops +# 132 inverters +# 437 gates (235 ANDs + 74 NANDs + 41 ORs + 87 NORs 0 XORs 0 XNORs) +.model unnamed +.inputs INS_2 INS_1 INS_0 LDAcc LDMQ LDDR STAcc STMQ STDR TESTMODE inBUS_7 inBUS_6 inBUS_5 inBUS_4 inBUS_3 inBUS_2 inBUS_1 inBUS_0 +.outputs outBUS_0 outBUS_1 outBUS_2 outBUS_3 outBUS_4 outBUS_5 outBUS_6 outBUS_7 RDY oLDALUout + +.latch I1_0 Acc_q_0 0 +.latch I1_1 Acc_q_1 0 +.latch I1_2 Acc_q_2 0 +.latch I1_3 Acc_q_3 0 +.latch I1_4 Acc_q_4 0 +.latch I1_5 Acc_q_5 0 +.latch I1_6 Acc_q_6 0 +.latch I1_7 Acc_q_7 0 +.latch I96_0 MQ_q_0 0 +.latch I96_1 MQ_q_1 0 +.latch I96_2 MQ_q_2 0 +.latch I96_3 MQ_q_3 0 +.latch I96_4 MQ_q_4 0 +.latch I96_5 MQ_q_5 0 +.latch I96_6 MQ_q_6 0 +.latch I96_7 MQ_q_7 0 +.latch I168_0 DR_q_0 0 +.latch I168_1 DR_q_1 0 +.latch I168_2 DR_q_2 0 +.latch I168_3 DR_q_3 0 +.latch I168_4 DR_q_4 0 +.latch I168_5 DR_q_5 0 +.latch I168_6 DR_q_6 0 +.latch I168_7 DR_q_7 0 +.latch I684 I679 0 +.latch I685 I680 0 +.latch I686 I681 0 +.latch I687 I682 0 +.latch I688 I683 0 +.latch LDALUout qLDALUout 0 +.latch mLDALUout oLDALUout 0 +.latch Pass1 qPass1 0 +.latch Pass2 qPass2 0 +.latch ShiftRight qShiftRight 0 +.latch INSo_0 qINSo_0 0 +.latch INSo_1 qINSo_1 0 +.latch INSo_2 qINSo_2 0 +.names INS_2 I704 +0 1 +.names INS_1 I705 +0 1 +.names MQ_q_0 I708 +0 1 +.names TESTMODE iTESTMODE +0 1 +.names I231_0 I234_0 +0 1 +.names I242_4 I298 I315_1 +11 1 +.names I231_1 I234_1 +0 1 +.names MQ_q_5 mShiftRight I136_1 +11 1 +.names I231_2 I234_2 +0 1 +.names inBUS_4 LDMQ I136_2 +11 1 +.names MQ_q_4 I102 I136_3 +11 1 +.names I744 I745 I791_1 +00 0 +.names I679 I710 +0 1 +.names I680 I711 +0 1 +.names I681 I712 +0 1 +.names I682 I713 +0 1 +.names I683 I714 +0 1 +.names I240_3 I230_1 I520_1 +11 1 +.names I246_0 I247_0 I243_0 +11 1 +.names I241_3 I233_1 I520_2 +11 1 +.names I242_3 I503_1 +0 1 +.names I246_1 I247_1 I243_1 +11 1 +.names I235_3 I503_2 +0 1 +.names I242_3 I503_2 I503_3 +11 1 +.names I246_2 I247_2 I243_2 +11 1 +.names I503_1 I235_3 I503_4 +11 1 +.names I246_3 I247_3 I243_3 +11 1 +.names MQ_q_4 mShiftRight I128_1 +11 1 +.names DR_q_5 I172 I209_1 +11 1 +.names I246_4 I247_4 I243_4 +11 1 +.names inBUS_3 LDMQ I128_2 +11 1 +.names inBUS_5 LDDR I209_2 +11 1 +.names I246_5 I247_5 I243_5 +11 1 +.names MQ_q_3 I102 I128_3 +11 1 +.names I246_6 I247_6 I243_6 +11 1 +.names I246_7 I247_7 I243_7 +11 1 +.names I753 I708 I683 I783_1 +000 0 +.names I705 I714 I783_2 +00 0 +.names I250_7 I230_0 I668_1 +11 1 +.names I249_7 I233_0 I668_2 +11 1 +.names I755 I757 I759 I765 F +1111 0 +.names Acc_q_6 I6 I78_1 +11 1 +.names ALUout_6 mLDALUout I78_2 +11 1 +.names INS_0 I714 I728 +00 1 +.names I730 I729 +0 1 +.names I246_6 I610_1 +0 1 +.names I243_3 I230_0 I512_1 +11 1 +.names I247_6 I610_2 +0 1 +.names I242_3 I233_0 I512_2 +11 1 +.names I246_6 I610_2 I610_3 +11 1 +.names I248_1 I414_1 +0 1 +.names imINSo_1 I235_0 +0 1 +.names I287 I261 I235_1 +11 0 +.names I610_1 I247_6 I610_4 +11 1 +.names I233_1 I414_2 +0 1 +.names I248_1 I414_2 I414_3 +11 1 +.names I275 I235_2 +0 1 +.names I259 I303 I235_3 +11 0 +.names I414_1 I233_1 I414_4 +11 1 +.names I273 I235_4 +0 1 +.names I272 I235_5 +0 1 +.names I256 I279 I310 I308 I235_6 +1111 0 +.names I311_1 I255 I235_7 +11 0 +.names TESTMODE qINSo_0 I873_1 +11 1 +.names iTESTMODE INSo_0 I873_2 +11 1 +.names I240_5 I230_1 I596_1 +11 1 +.names I241_5 I233_1 I596_2 +11 1 +.names I242_5 I579_1 +0 1 +.names I235_5 I579_2 +0 1 +.names I242_5 I579_2 I579_3 +11 1 +.names I579_1 I235_5 I579_4 +11 1 +.names I710 I788_1 I730 +00 1 +.names I791_1 I712 I731 +11 0 +.names INS_2 I705 I735 +11 0 +.names I679 I681 I737 +11 0 +.names INS_0 I764 I739 +11 0 +.names I250_1 I230_0 I440_1 +11 1 +.names I249_1 I233_0 I440_2 +11 1 +.names I240_0 I230_1 I406_1 +11 1 +.names I241_0 I233_1 I406_2 +11 1 +.names Acc_q_0 I6 I12_1 +11 1 +.names TESTMODE qShiftRight I865_1 +11 1 +.names ALUout_0 mLDALUout I12_2 +11 1 +.names iTESTMODE ShiftRight I865_2 +11 1 +.names I243_5 I230_0 I588_1 +11 1 +.names I242_5 I233_0 I588_2 +11 1 +.names I679 I682 I741 +11 0 +.names I741 I742 +0 1 +.names I744 I743 +0 1 +.names I97_0 I96_0 +0 1 +.names INS_0 I735 I744 +00 1 +.names I97_1 I96_1 +0 1 +.names I2_0 I3_0 I1_0 +11 0 +.names I710 I711 I745 +11 0 +.names I97_2 I96_2 +0 1 +.names I2_1 I3_1 I1_1 +11 0 +.names I97_3 I96_3 +0 1 +.names I2_2 I3_2 I1_2 +11 0 +.names I735 I764 I747 +11 0 +.names I97_4 I96_4 +0 1 +.names I2_3 I3_3 I1_3 +11 0 +.names I97_5 I96_5 +0 1 +.names I2_4 I3_4 I1_4 +11 0 +.names I710 I681 I749 +11 0 +.names I97_6 I96_6 +0 1 +.names I2_5 I3_5 I1_5 +11 0 +.names I97_7 I96_7 +0 1 +.names I2_6 I3_6 I1_6 +11 0 +.names I2_7 I3_7 I1_7 +11 0 +.names I389_3 I389_4 I236_0 +00 0 +.names I427_3 I427_4 I236_1 +00 0 +.names I465_3 I465_4 I236_2 +00 0 +.names I503_3 I503_4 I236_3 +00 0 +.names I541_3 I541_4 I236_4 +00 0 +.names I579_3 I579_4 I236_5 +00 0 +.names I617_3 I617_4 I236_6 +00 0 +.names I655_3 I655_4 I236_7 +00 0 +.names STMQ MQ_q_0 I891_1 +11 1 +.names STDR DR_q_0 I891_2 +11 1 +.names STAcc Acc_q_0 I891_3 +11 1 +.names I680 I712 I751 +11 0 +.names I754 I753 +0 1 +.names I711 I737 I754 +00 1 +.names I737 I762 I755 +11 0 +.names I808_1 I711 I757 +11 0 +.names I760 I759 +0 1 +.names DR_q_1 I172 I181_1 +11 1 +.names inBUS_1 LDDR I181_2 +11 1 +.names ALUout_3 mShiftRight I30_1 +11 1 +.names inBUS_2 LDAcc I30_2 +11 1 +.names I713 I811_1 I760 +00 1 +.names DR_q_7 MQ_q_0 I761 +11 0 +.names I104_1 I104_2 I104_3 I97_0 +000 1 +.names I761 I762 +0 1 +.names I112_1 I112_2 I112_3 I97_1 +000 1 +.names I8_1 I8_2 I2_0 +00 1 +.names I120_1 I120_2 I120_3 I97_2 +000 1 +.names I681 I745 I764 +00 1 +.names I19_1 I19_2 I2_1 +00 1 +.names I128_1 I128_2 I128_3 I97_3 +000 1 +.names I769_1 I729 I684 +11 0 +.names I816_1 I754 I761 I765 +111 0 +.names I30_1 I30_2 I2_2 +00 1 +.names I136_1 I136_2 I136_3 I97_4 +000 1 +.names I772_1 I751 I685 +11 0 +.names I41_1 I41_2 I2_3 +00 1 +.names I144_1 I144_2 I144_3 I97_5 +000 1 +.names I731 I686 +0 1 +.names I52_1 I52_2 I2_4 +00 1 +.names I152_1 I152_2 I152_3 I97_6 +000 1 +.names I704 I679 INS_0 I681 I768 +0000 1 +.names I755 I759 I757 I765 I687 +1111 0 +.names I63_1 I63_2 I2_5 +00 1 +.names I160_1 I160_2 I160_3 I97_7 +000 1 +.names I753 I739 I747 I688 +111 0 +.names I74_1 I74_2 I2_6 +00 1 +.names I85_1 I85_2 I2_7 +00 1 +.names I236_0 I233_2 I237_0 +11 0 +.names I236_1 I233_2 I237_1 +11 0 +.names I236_2 I233_2 I237_2 +11 0 +.names I236_3 I233_2 I237_3 +11 0 +.names I236_4 I233_2 I237_4 +11 0 +.names I236_5 I233_2 I237_5 +11 0 +.names I236_6 I233_2 I237_6 +11 0 +.names I236_7 I233_2 I237_7 +11 0 +.names I739 I747 I794_1 +11 1 +.names TESTMODE qPass2 I858_1 +11 1 +.names iTESTMODE Pass2 I858_2 +11 1 +.names Acc_q_7 I6 I89_1 +11 1 +.names ALUout_7 mLDALUout I89_2 +11 1 +.names I248_6 I604_1 +0 1 +.names I376_3 I376_4 I246_0 +00 0 +.names I233_1 I604_2 +0 1 +.names I414_3 I414_4 I246_1 +00 0 +.names I248_6 I604_2 I604_3 +11 1 +.names I452_3 I452_4 I246_2 +00 0 +.names I604_1 I233_1 I604_4 +11 1 +.names I490_3 I490_4 I246_3 +00 0 +.names I528_3 I528_4 I246_4 +00 0 +.names I566_3 I566_4 I246_5 +00 0 +.names I604_3 I604_4 I246_6 +00 0 +.names I642_3 I642_4 I246_7 +00 0 +.names I851_1 I851_2 imPass1 +00 1 +.names I858_1 I858_2 imPass2 +00 1 +.names I711 I749 I769_1 +00 0 +.names I12_1 I12_2 I3_0 +00 1 +.names I23_1 I23_2 I3_1 +00 1 +.names I34_1 I34_2 I3_2 +00 1 +.names I45_1 I45_2 I3_3 +00 1 +.names I56_1 I56_2 I3_4 +00 1 +.names I67_1 I67_2 I3_5 +00 1 +.names I78_1 I78_2 I3_6 +00 1 +.names I89_1 I89_2 I3_7 +00 1 +.names I250_6 I230_0 I630_1 +11 1 +.names I249_6 I233_0 I630_2 +11 1 +.names I406_1 I406_2 I238_0 +00 1 +.names DR_q_0 I172 I174_1 +11 1 +.names I444_1 I444_2 I238_1 +00 1 +.names inBUS_0 LDDR I174_2 +11 1 +.names I482_1 I482_2 I238_2 +00 1 +.names I520_1 I520_2 I238_3 +00 1 +.names I558_1 I558_2 I238_4 +00 1 +.names I596_1 I596_2 I238_5 +00 1 +.names I634_1 I634_2 I238_6 +00 1 +.names I672_1 I672_2 I238_7 +00 1 +.names Acc_q_1 I6 I23_1 +11 1 +.names ALUout_1 mLDALUout I23_2 +11 1 +.names I840_1 I840_2 imLDALUout +00 1 +.names LDAcc I794_1 LDALUout +00 1 +.names I242_4 I541_1 +0 1 +.names I235_4 I541_2 +0 1 +.names I242_4 I541_2 I541_3 +11 1 +.names Acc_q_0 I251 I247_0 +11 1 +.names I541_1 I235_4 I541_4 +11 1 +.names Acc_q_1 I251 I247_1 +11 1 +.names Acc_q_2 I251 I247_2 +11 1 +.names Acc_q_3 I251 I247_3 +11 1 +.names Acc_q_4 I251 I247_4 +11 1 +.names Acc_q_5 I251 I247_5 +11 1 +.names Acc_q_6 I251 I247_6 +11 1 +.names Acc_q_7 I251 I247_7 +11 1 +.names I711 I768 I705 Pass1 +111 0 +.names I728 INSo_0 +0 1 +.names I783_1 I783_2 INSo_1 +11 0 +.names I747 I708 I739 Pass2 +111 0 +.names I704 I683 INSo_2 +11 0 +.names I243_4 I230_0 I550_1 +11 1 +.names I242_4 I233_0 I550_2 +11 1 +.names I248_2 I452_1 +0 1 +.names I233_1 I452_2 +0 1 +.names I250_3 I230_0 I516_1 +11 1 +.names I238_0 I230_2 I239_0 +11 0 +.names I243_1 I294 I337_1 +00 0 +.names I248_2 I452_2 I452_3 +11 1 +.names I249_3 I233_0 I516_2 +11 1 +.names I238_1 I230_2 I239_1 +11 0 +.names I452_1 I233_1 I452_4 +11 1 +.names I238_2 I230_2 I239_2 +11 0 +.names I238_3 I230_2 I239_3 +11 0 +.names I238_4 I230_2 I239_4 +11 0 +.names I238_5 I230_2 I239_5 +11 0 +.names I238_6 I230_2 I239_6 +11 0 +.names I743 I711 I710 I712 ShiftRight +1111 0 +.names I238_7 I230_2 I239_7 +11 0 +.names ALUout_4 mShiftRight I41_1 +11 1 +.names inBUS_3 LDAcc I41_2 +11 1 +.names I240_1 I230_1 I444_1 +11 1 +.names I241_1 I233_1 I444_2 +11 1 +.names I242_1 I427_1 +0 1 +.names DR_q_0 I252 I248_0 +11 1 +.names I235_1 I427_2 +0 1 +.names DR_q_1 I252 I248_1 +11 1 +.names I242_1 I427_2 I427_3 +11 1 +.names DR_q_2 I252 I248_2 +11 1 +.names I427_1 I235_1 I427_4 +11 1 +.names DR_q_3 I252 I248_3 +11 1 +.names DR_q_4 I252 I248_4 +11 1 +.names DR_q_5 I252 I248_5 +11 1 +.names DR_q_6 I252 I248_6 +11 1 +.names DR_q_7 I252 I248_7 +11 1 +.names I680 I681 I788_1 +11 1 +.names I749 I751 I811_1 +11 1 +.names I246_4 I534_1 +0 1 +.names I243_1 I230_0 I436_1 +11 1 +.names I247_4 I534_2 +0 1 +.names I242_1 I233_0 I436_2 +11 1 +.names I246_4 I534_2 I534_3 +11 1 +.names I534_1 I247_4 I534_4 +11 1 +.names mShiftRight LDAcc mLDALUout I6 +000 1 +.names outBUSb_0 outBUS_0 +0 1 +.names outBUSb_1 outBUS_1 +0 1 +.names outBUSb_2 outBUS_2 +0 1 +.names outBUSb_3 outBUS_3 +0 1 +.names outBUSb_4 outBUS_4 +0 1 +.names outBUSb_5 outBUS_5 +0 1 +.names I247_0 I249_0 +0 1 +.names outBUSb_6 outBUS_6 +0 1 +.names I169_0 I168_0 +0 1 +.names I247_1 I249_1 +0 1 +.names outBUSb_7 outBUS_7 +0 1 +.names I169_1 I168_1 +0 1 +.names I247_2 I249_2 +0 1 +.names I169_2 I168_2 +0 1 +.names I247_3 I249_3 +0 1 +.names I169_3 I168_3 +0 1 +.names I247_4 I249_4 +0 1 +.names I169_4 I168_4 +0 1 +.names I247_5 I249_5 +0 1 +.names I169_5 I168_5 +0 1 +.names I247_6 I249_6 +0 1 +.names I169_6 I168_6 +0 1 +.names I247_7 I249_7 +0 1 +.names I169_7 I168_7 +0 1 +.names TESTMODE qINSo_2 I887_1 +11 1 +.names Acc_q_2 I6 I34_1 +11 1 +.names ALUout_2 mLDALUout I34_2 +11 1 +.names iTESTMODE INSo_2 I887_2 +11 1 +.names I753 I747 I739 RDY +111 0 +.names I248_7 I642_1 +0 1 +.names I246_0 I382_1 +0 1 +.names I233_1 I642_2 +0 1 +.names I248_7 I642_2 I642_3 +11 1 +.names I247_0 I382_2 +0 1 +.names I174_1 I174_2 I169_0 +00 1 +.names I246_0 I382_2 I382_3 +11 1 +.names I642_1 I233_1 I642_4 +11 1 +.names I181_1 I181_2 I169_1 +00 1 +.names I382_1 I247_0 I382_4 +11 1 +.names I188_1 I188_2 I169_2 +00 1 +.names I195_1 I195_2 I169_3 +00 1 +.names I202_1 I202_2 I169_4 +00 1 +.names I209_1 I209_2 I169_5 +00 1 +.names I216_1 I216_2 I169_6 +00 1 +.names I223_1 I223_2 I169_7 +00 1 +.names ALUout_5 mShiftRight I52_1 +11 1 +.names inBUS_4 LDAcc I52_2 +11 1 +.names imShiftRight mShiftRight +0 1 +.names I237_0 I239_0 ALUout_0 +11 0 +.names I237_1 I239_1 ALUout_1 +11 0 +.names I237_2 I239_2 ALUout_2 +11 0 +.names I237_3 I239_3 ALUout_3 +11 0 +.names I237_4 I239_4 ALUout_4 +11 0 +.names I237_5 I239_5 ALUout_5 +11 0 +.names I237_6 I239_6 ALUout_6 +11 0 +.names I237_7 I239_7 ALUout_7 +11 0 +.names I240_6 I230_1 I634_1 +11 1 +.names I242_6 I617_1 +0 1 +.names I241_6 I233_1 I634_2 +11 1 +.names I235_6 I617_2 +0 1 +.names DR_q_3 I172 I195_1 +11 1 +.names inBUS_3 LDDR I195_2 +11 1 +.names I242_6 I617_2 I617_3 +11 1 +.names I617_1 I235_6 I617_4 +11 1 +.names STMQ MQ_q_1 I897_1 +11 1 +.names STDR DR_q_1 I897_2 +11 1 +.names STAcc Acc_q_1 I897_3 +11 1 +.names MQ_q_3 mShiftRight I120_1 +11 1 +.names inBUS_2 LDMQ I120_2 +11 1 +.names MQ_q_2 I102 I120_3 +11 1 +.names STMQ MQ_q_2 I903_1 +11 1 +.names STDR DR_q_2 I903_2 +11 1 +.names STAcc Acc_q_2 I903_3 +11 1 +.names I243_6 I230_0 I626_1 +11 1 +.names I248_4 I528_1 +0 1 +.names I242_6 I233_0 I626_2 +11 1 +.names I233_1 I528_2 +0 1 +.names I248_4 I528_2 I528_3 +11 1 +.names I528_1 I233_1 I528_4 +11 1 +.names ALUout_2 mShiftRight I19_1 +11 1 +.names inBUS_1 LDAcc I19_2 +11 1 +.names MQ_q_2 mShiftRight I112_1 +11 1 +.names inBUS_1 LDMQ I112_2 +11 1 +.names MQ_q_1 I102 I112_3 +11 1 +.names ALUout_1 mShiftRight I8_1 +11 1 +.names inBUS_0 LDAcc I8_2 +11 1 +.names I248_3 I490_1 +0 1 +.names I233_1 I490_2 +0 1 +.names I250_4 I230_0 I554_1 +11 1 +.names I249_4 I233_0 I554_2 +11 1 +.names I248_3 I490_2 I490_3 +11 1 +.names I490_1 I233_1 I490_4 +11 1 +.names Acc_q_3 I6 I45_1 +11 1 +.names ALUout_3 mLDALUout I45_2 +11 1 +.names DR_q_4 I172 I202_1 +11 1 +.names inBUS_4 LDDR I202_2 +11 1 +.names MQ_q_1 mShiftRight I104_1 +11 1 +.names inBUS_0 LDMQ I104_2 +11 1 +.names MQ_q_0 I102 I104_3 +11 1 +.names TESTMODE qLDALUout I840_1 +11 1 +.names STMQ MQ_q_5 I921_1 +11 1 +.names STDR DR_q_5 I921_2 +11 1 +.names iTESTMODE LDALUout I840_2 +11 1 +.names STAcc Acc_q_5 I921_3 +11 1 +.names I240_2 I230_1 I482_1 +11 1 +.names I242_2 I465_1 +0 1 +.names I241_2 I233_1 I482_2 +11 1 +.names I235_2 I465_2 +0 1 +.names DR_q_2 I172 I188_1 +11 1 +.names I242_2 I465_2 I465_3 +11 1 +.names inBUS_2 LDDR I188_2 +11 1 +.names I465_1 I235_2 I465_4 +11 1 +.names LDMQ mShiftRight I102 +00 1 +.names I246_5 I572_1 +0 1 +.names imLDALUout mLDALUout +0 1 +.names I247_5 I572_2 +0 1 +.names I243_2 I230_0 I474_1 +11 1 +.names I248_0 I376_1 +0 1 +.names I246_5 I572_2 I572_3 +11 1 +.names I242_2 I233_0 I474_2 +11 1 +.names I233_1 I376_2 +0 1 +.names I572_1 I247_5 I572_4 +11 1 +.names I248_0 I376_2 I376_3 +11 1 +.names I376_1 I233_1 I376_4 +11 1 +.names ALUout_6 mShiftRight I63_1 +11 1 +.names inBUS_5 LDAcc I63_2 +11 1 +.names I865_1 I865_2 imShiftRight +00 1 +.names I891_1 I891_2 I891_3 outBUSb_0 +000 1 +.names I897_1 I897_2 I897_3 outBUSb_1 +000 1 +.names I903_1 I903_2 I903_3 outBUSb_2 +000 1 +.names I909_1 I909_2 I909_3 outBUSb_3 +000 1 +.names I915_1 I915_2 I915_3 outBUSb_4 +000 1 +.names DR_q_7 MQ_q_0 I816_1 +00 0 +.names I921_1 I921_2 I921_3 outBUSb_5 +000 1 +.names I927_1 I927_2 I927_3 outBUSb_6 +000 1 +.names I246_2 I458_1 +0 1 +.names I933_1 I933_2 I933_3 outBUSb_7 +000 1 +.names I247_2 I458_2 +0 1 +.names I246_2 I458_2 I458_3 +11 1 +.names I458_1 I247_2 I458_4 +11 1 +.names I762 I742 I808_1 +00 0 +.names I259 I265 I300 +00 1 +.names I283 I296 I285 I301 +111 0 +.names I301 I302 +0 1 +.names I337_1 I242_2 I303 +11 0 +.names I242_5 I242_3 I242_4 I242_2 I305 +1111 0 +.names I305 I306 +0 1 +.names I281 I285 I307 +11 0 +.names Acc_q_4 I6 I56_1 +11 1 +.names I307 I308 +0 1 +.names ALUout_4 mLDALUout I56_2 +11 1 +.names I283 I277 I309 +11 0 +.names I231_0 I230_0 +0 1 +.names I231_1 I230_1 +0 1 +.names I262 I302 I311_1 +00 0 +.names I231_2 I230_2 +0 1 +.names TESTMODE qPass1 I851_1 +11 1 +.names iTESTMODE Pass1 I851_2 +11 1 +.names STMQ MQ_q_4 I915_1 +11 1 +.names I240_7 I230_1 I672_1 +11 1 +.names STDR DR_q_4 I915_2 +11 1 +.names I242_7 I655_1 +0 1 +.names I241_7 I233_1 I672_2 +11 1 +.names STAcc Acc_q_4 I915_3 +11 1 +.names I235_7 I655_2 +0 1 +.names I242_7 I655_2 I655_3 +11 1 +.names I655_1 I235_7 I655_4 +11 1 +.names I309 I310 +0 1 +.names I243_7 I230_0 I664_1 +11 1 +.names I248_5 I566_1 +0 1 +.names I242_7 I233_0 I664_2 +11 1 +.names I233_1 I566_2 +0 1 +.names I248_5 I566_2 I566_3 +11 1 +.names I566_1 I233_1 I566_4 +11 1 +.names ALUout_7 mShiftRight I74_1 +11 1 +.names inBUS_6 LDAcc I74_2 +11 1 +.names imINSo_0 I231_0 +0 1 +.names imINSo_1 I231_1 +0 1 +.names imINSo_2 I231_2 +0 1 +.names STMQ MQ_q_7 I933_1 +11 1 +.names I250_5 I230_0 I592_1 +11 1 +.names STDR DR_q_7 I933_2 +11 1 +.names I249_5 I233_0 I592_2 +11 1 +.names STAcc Acc_q_7 I933_3 +11 1 +.names I240_4 I230_1 I558_1 +11 1 +.names I241_4 I233_1 I558_2 +11 1 +.names imPass1 I251 +0 1 +.names imPass2 I252 +0 1 +.names LDDR I172 +0 1 +.names I243_6 I255 +0 1 +.names I243_5 I256 +0 1 +.names I243_2 I259 +0 1 +.names I398_1 I398_2 I240_0 +00 1 +.names I436_1 I436_2 I240_1 +00 1 +.names I250_0 I230_0 I402_1 +11 1 +.names I474_1 I474_2 I240_2 +00 1 +.names I249_0 I233_0 I402_2 +11 1 +.names DR_q_7 I172 I223_1 +11 1 +.names I512_1 I512_2 I240_3 +00 1 +.names inBUS_7 LDDR I223_2 +11 1 +.names I550_1 I550_2 I240_4 +00 1 +.names I588_1 I588_2 I240_5 +00 1 +.names I626_1 I626_2 I240_6 +00 1 +.names I664_1 I664_2 I240_7 +00 1 +.names I246_7 I648_1 +0 1 +.names I247_7 I648_2 +0 1 +.names I246_7 I648_2 I648_3 +11 1 +.names I648_1 I247_7 I648_4 +11 1 +.names I243_0 I261 +0 1 +.names I242_6 I262 +0 1 +.names I242_3 I265 +0 1 +.names I242_1 I267 +0 1 +.names I261 I287 I330_1 +11 1 +.names I680 I712 I772_1 +00 0 +.names I250_2 I230_0 I478_1 +11 1 +.names I249_2 I233_0 I478_2 +11 1 +.names I315_1 I290 I243_4 I292 I272 +0000 1 +.names I243_3 I298 I300 I273 +000 1 +.names Acc_q_5 I6 I67_1 +11 1 +.names I243_1 I294 I275 +00 1 +.names ALUout_5 mLDALUout I67_2 +11 1 +.names I243_1 I306 I277 +11 0 +.names I242_5 I290 I279 +11 0 +.names I402_1 I402_2 I241_0 +00 1 +.names I246_1 I420_1 +0 1 +.names I440_1 I440_2 I241_1 +00 1 +.names I247_1 I420_2 +0 1 +.names ALUout_0 mShiftRight I160_1 +11 1 +.names I478_1 I478_2 I241_2 +00 1 +.names inBUS_7 LDMQ I160_2 +11 1 +.names I246_1 I420_2 I420_3 +11 1 +.names I516_1 I516_2 I241_3 +00 1 +.names MQ_q_7 I102 I160_3 +11 1 +.names I420_1 I247_1 I420_4 +11 1 +.names I554_1 I554_2 I241_4 +00 1 +.names I592_1 I592_2 I241_5 +00 1 +.names I630_1 I630_2 I241_6 +00 1 +.names I668_1 I668_2 I241_7 +00 1 +.names STMQ MQ_q_3 I909_1 +11 1 +.names STDR DR_q_3 I909_2 +11 1 +.names STAcc Acc_q_3 I909_3 +11 1 +.names I242_0 I389_1 +0 1 +.names I235_0 I389_2 +0 1 +.names I873_1 I873_2 imINSo_0 +00 1 +.names I242_0 I389_2 I389_3 +11 1 +.names I880_1 I880_2 imINSo_1 +00 1 +.names I389_1 I235_0 I389_4 +11 1 +.names I887_1 I887_2 imINSo_2 +00 1 +.names I242_5 I292 I281 +11 0 +.names I243_4 I242_5 I283 +11 0 +.names I294 I306 I285 +11 0 +.names I242_0 I235_0 I287 +11 0 +.names I242_4 I300 I289 +11 0 +.names I247_0 I248_0 I250_0 +00 0 +.names I234_0 I233_0 +0 1 +.names I247_1 I248_1 I250_1 +00 0 +.names MQ_q_7 mShiftRight I152_1 +11 1 +.names I234_1 I233_1 +0 1 +.names I247_2 I248_2 I250_2 +00 0 +.names DR_q_6 I172 I216_1 +11 1 +.names inBUS_6 LDMQ I152_2 +11 1 +.names I234_2 I233_2 +0 1 +.names I247_3 I248_3 I250_3 +00 0 +.names MQ_q_6 I102 I152_3 +11 1 +.names inBUS_6 LDDR I216_2 +11 1 +.names I247_4 I248_4 I250_4 +00 0 +.names I247_5 I248_5 I250_5 +00 0 +.names I247_6 I248_6 I250_6 +00 0 +.names I247_7 I248_7 I250_7 +00 0 +.names I246_3 I496_1 +0 1 +.names I247_3 I496_2 +0 1 +.names I243_0 I230_0 I398_1 +11 1 +.names I246_3 I496_2 I496_3 +11 1 +.names I242_0 I233_0 I398_2 +11 1 +.names I496_1 I247_3 I496_4 +11 1 +.names I289 I290 +0 1 +.names I243_3 I242_4 I291 +11 0 +.names F mShiftRight I85_1 +11 1 +.names I291 I292 +0 1 +.names inBUS_7 LDAcc I85_2 +11 1 +.names I267 I330_1 I294 +00 1 +.names I256 I279 I277 I281 I295 +1111 0 +.names I295 I296 +0 1 +.names I265 I303 I298 +00 1 +.names I382_3 I382_4 I242_0 +00 0 +.names I420_3 I420_4 I242_1 +00 0 +.names MQ_q_6 mShiftRight I144_1 +11 1 +.names I458_3 I458_4 I242_2 +00 0 +.names inBUS_5 LDMQ I144_2 +11 1 +.names I496_3 I496_4 I242_3 +00 0 +.names MQ_q_5 I102 I144_3 +11 1 +.names I534_3 I534_4 I242_4 +00 0 +.names I572_3 I572_4 I242_5 +00 0 +.names I610_3 I610_4 I242_6 +00 0 +.names I648_3 I648_4 I242_7 +00 0 +.names TESTMODE qINSo_1 I880_1 +11 1 +.names iTESTMODE INSo_1 I880_2 +11 1 +.names STMQ MQ_q_6 I927_1 +11 1 +.names STDR DR_q_6 I927_2 +11 1 +.names STAcc Acc_q_6 I927_3 +11 1 +.end Index: vis_dev/vis-2.1/examples/s1269/s1269.ord =================================================================== --- vis_dev/vis-2.1/examples/s1269/s1269.ord (revision 11) +++ vis_dev/vis-2.1/examples/s1269/s1269.ord (revision 11) @@ -0,0 +1,97 @@ +# vis release 1.4 (compiled 20-Jun-02 at 7:12 PM) +# network name: unnamed +# generated: Tue Jul 2 10:55:31 2002 +# +# name type mddId vals levs +TESTMODE primary-input 17 2 (0) +oLDALUout$NS shadow 1 2 (1) +oLDALUout latch 0 2 (2) +qLDALUout latch 90 2 (3) +qLDALUout$NS shadow 91 2 (4) +qShiftRight latch 64 2 (5) +qShiftRight$NS shadow 65 2 (6) +I681 latch 9 2 (7) +I681$NS shadow 10 2 (8) +I680 latch 3 2 (9) +I680$NS shadow 4 2 (10) +I679$NS shadow 8 2 (11) +I679 latch 7 2 (12) +qPass1$NS shadow 27 2 (13) +qPass1 latch 26 2 (14) +I683$NS shadow 15 2 (15) +I683 latch 14 2 (16) +INS_2 primary-input 21 2 (17) +qINSo_2$NS shadow 61 2 (18) +qINSo_2 latch 60 2 (19) +INS_1 primary-input 16 2 (20) +qINSo_1$NS shadow 19 2 (21) +qINSo_1 latch 18 2 (22) +qINSo_0 latch 62 2 (23) +qINSo_0$NS shadow 63 2 (24) +INS_0 primary-input 20 2 (25) +qPass2 latch 22 2 (26) +qPass2$NS shadow 23 2 (27) +I682 latch 5 2 (28) +I682$NS shadow 6 2 (29) +MQ_q_0 latch 11 2 (30) +MQ_q_0$NS shadow 12 2 (31) +LDAcc primary-input 81 2 (32) +DR_q_7 latch 56 2 (33) +DR_q_7$NS shadow 57 2 (34) +STDR primary-input 48 2 (35) +Acc_q_7 latch 58 2 (36) +Acc_q_7$NS shadow 59 2 (37) +LDMQ primary-input 78 2 (38) +inBUS_7 primary-input 88 2 (39) +inBUS_0 primary-input 82 2 (40) +DR_q_0 latch 46 2 (41) +DR_q_0$NS shadow 47 2 (42) +Acc_q_0 latch 49 2 (43) +Acc_q_0$NS shadow 50 2 (44) +MQ_q_7$NS shadow 80 2 (45) +MQ_q_7 latch 79 2 (46) +Acc_q_1 latch 44 2 (47) +Acc_q_1$NS shadow 45 2 (48) +DR_q_1 latch 42 2 (49) +DR_q_1$NS shadow 43 2 (50) +inBUS_1 primary-input 83 2 (51) +MQ_q_1 latch 76 2 (52) +MQ_q_1$NS shadow 77 2 (53) +Acc_q_2 latch 32 2 (54) +Acc_q_2$NS shadow 33 2 (55) +DR_q_2 latch 30 2 (56) +DR_q_2$NS shadow 31 2 (57) +inBUS_2 primary-input 84 2 (58) +MQ_q_2 latch 74 2 (59) +MQ_q_2$NS shadow 75 2 (60) +DR_q_3 latch 24 2 (61) +DR_q_3$NS shadow 25 2 (62) +Acc_q_3 latch 28 2 (63) +Acc_q_3$NS shadow 29 2 (64) +inBUS_3 primary-input 85 2 (65) +MQ_q_3 latch 72 2 (66) +MQ_q_3$NS shadow 73 2 (67) +LDDR primary-input 2 2 (68) +Acc_q_4$NS shadow 37 2 (69) +Acc_q_4 latch 36 2 (70) +DR_q_4 latch 34 2 (71) +DR_q_4$NS shadow 35 2 (72) +inBUS_4 primary-input 87 2 (73) +MQ_q_4 latch 70 2 (74) +MQ_q_4$NS shadow 71 2 (75) +DR_q_5 latch 38 2 (76) +DR_q_5$NS shadow 39 2 (77) +DR_q_6$NS shadow 53 2 (78) +DR_q_6 latch 52 2 (79) +inBUS_6 primary-input 89 2 (80) +inBUS_5 primary-input 86 2 (81) +Acc_q_5 latch 40 2 (82) +Acc_q_5$NS shadow 41 2 (83) +MQ_q_5 latch 68 2 (84) +MQ_q_5$NS shadow 69 2 (85) +STMQ primary-input 13 2 (86) +MQ_q_6 latch 66 2 (87) +MQ_q_6$NS shadow 67 2 (88) +STAcc primary-input 51 2 (89) +Acc_q_6 latch 54 2 (90) +Acc_q_6$NS shadow 55 2 (91) Index: vis_dev/vis-2.1/examples/synthesis/README =================================================================== --- vis_dev/vis-2.1/examples/synthesis/README (revision 11) +++ vis_dev/vis-2.1/examples/synthesis/README (revision 11) @@ -0,0 +1,4 @@ +$Id: README,v 1.3 1998/09/15 17:31:24 kumtheka Exp $ + +This directory contains a collection of circuits for the test of the +synthesize_network. Index: vis_dev/vis-2.1/examples/synthesis/check_result =================================================================== --- vis_dev/vis-2.1/examples/synthesis/check_result (revision 11) +++ vis_dev/vis-2.1/examples/synthesis/check_result (revision 11) @@ -0,0 +1,4 @@ +** synth info: Total number of literals = 148 +Networks are sequentially equivalent. +** synth info: Total number of literals = 103 +Networks are combinationally equivalent. Index: vis_dev/vis-2.1/examples/synthesis/check_script =================================================================== --- vis_dev/vis-2.1/examples/synthesis/check_script (revision 11) +++ vis_dev/vis-2.1/examples/synthesis/check_script (revision 11) @@ -0,0 +1,15 @@ +read_blif s298.blif +flatten_hierarchy +static_order +synthesize_network -o s298 +seq_verify -b s298.ml.blif + +read_blif vg2.blif +flatten_hierarchy +static_order +synthesize_network -o vg2 +comb_verify -b vg2.blif vg2.ml.blif + +!rm *.ml.blif + +quit -s Index: vis_dev/vis-2.1/examples/synthesis/s298.blif =================================================================== --- vis_dev/vis-2.1/examples/synthesis/s298.blif (revision 11) +++ vis_dev/vis-2.1/examples/synthesis/s298.blif (revision 11) @@ -0,0 +1,308 @@ +.model s298 +.inputs G0 G1 G2 +.outputs G117 G132 G66 G118 G133 G67 +.wire_load_slope 0.00 +.latch G29 G10 0 +.latch G30 G11 0 +.latch G34 G12 0 +.latch G39 G13 0 +.latch G44 G14 0 +.latch G56 G15 0 +.latch G86 G16 0 +.latch G92 G17 0 +.latch G98 G18 0 +.latch G102 G19 0 +.latch G107 G20 0 +.latch G113 G21 0 +.latch G119 G22 0 +.latch G125 G23 0 +.names II210 G117 +0 1 +.names II235 G132 +0 1 +.names II155 G66 +0 1 +.names II213 G118 +0 1 +.names II238 G133 +0 1 +.names II158 G67 +0 1 +.names G10 G130 G29 +00 1 +.names G31 G32 G33 G130 G30 +0000 1 +.names G35 G36 G37 G130 G34 +0000 1 +.names G42 G43 G39 +00 1 +.names G48 G49 G53 G44 +000 1 +.names G57 G58 G130 G56 +000 1 +.names G88 G89 G90 G112 G86 +0000 1 +.names G94 G95 G97 G92 +000 1 +.names G100 G101 G98 +00 1 +.names G105 G106 G102 +00 1 +.names G110 G111 G107 +00 1 +.names G115 G116 G113 +00 1 +.names G122 G123 G130 G119 +000 1 +.names G128 G129 G130 G125 +000 1 +.names II229 G130 +0 1 +.names G130 G28 +0 1 +.names G10 G38 +0 1 +.names G13 G40 +0 1 +.names G12 G45 +0 1 +.names G11 G46 +0 1 +.names G14 G50 +0 1 +.names G23 G51 +0 1 +.names G11 G54 +0 1 +.names G13 G55 +0 1 +.names G12 G59 +0 1 +.names G22 G60 +0 1 +.names G15 G64 +0 1 +.names G16 II155 +0 1 +.names G17 II158 +0 1 +.names G10 G76 +0 1 +.names G11 G82 +0 1 +.names G16 G87 +0 1 +.names G12 G91 +0 1 +.names G17 G93 +0 1 +.names G14 G96 +0 1 +.names G18 G99 +0 1 +.names G13 G103 +0 1 +.names G62 G63 G112 +00 1 +.names G112 G108 +0 1 +.names G21 G114 +0 1 +.names G18 II210 +0 1 +.names G19 II213 +0 1 +.names II221 G124 +0 1 +.names G124 G120 +0 1 +.names G22 G121 +0 1 +.names G2 II221 +0 1 +.names II232 G131 +0 1 +.names G131 G126 +0 1 +.names G23 G127 +0 1 +.names G0 II229 +0 1 +.names G1 II232 +0 1 +.names G20 II235 +0 1 +.names G21 II238 +0 1 +.names G28 G50 G26 +11 1 +.names G51 G28 G27 +11 1 +.names G10 G45 G13 G31 +111 1 +.names G10 G11 G32 +11 1 +.names G38 G46 G33 +11 1 +.names G10 G11 G12 G35 +111 1 +.names G38 G45 G36 +11 1 +.names G46 G45 G37 +11 1 +.names G12 G11 G10 G41 +0-- 1 +-0- 1 +--0 1 +.names G40 G41 G42 +11 1 +.names G50 G40 G47 +00 1 +.names G45 G46 G10 G47 G48 +1111 1 +.names G13 G45 G46 G10 G52 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G50 G51 G52 G49 +111 1 +.names G14 G55 G61 +00 1 +.names G59 G11 G60 G61 G57 +1111 1 +.names G59 G54 G22 G61 G65 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G64 G65 G58 +11 1 +.names G59 G11 G60 G61 G62 +1111 1 +.names G64 G65 G63 +11 1 +.names G12 G14 G19 G74 +111 1 +.names G82 G91 G14 G75 +111 1 +.names G14 G87 G88 +11 1 +.names G103 G96 G89 +11 1 +.names G91 G103 G90 +11 1 +.names G93 G13 G94 +11 1 +.names G96 G13 G95 +11 1 +.names G99 G14 G12 G100 +111 1 +.names G74 G75 G104 +00 1 +.names G103 G108 G104 G105 +111 1 +.names G71 G72 G73 G14 G109 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G108 G109 G110 +11 1 +.names G10 G112 G111 +11 1 +.names G114 G14 G115 +11 1 +.names G120 G121 G122 +11 1 +.names G124 G22 G123 +11 1 +.names G126 G127 G128 +11 1 +.names G131 G23 G129 +11 1 +.names G38 G46 G45 G40 G24 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names G38 G11 G12 G25 +1-- 1 +-1- 1 +--1 1 +.names G11 G12 G13 G96 G68 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names G103 G18 G69 +1- 1 +-1 1 +.names G103 G14 G70 +1- 1 +-1 1 +.names G82 G12 G13 G71 +1-- 1 +-1- 1 +--1 1 +.names G91 G20 G72 +1- 1 +-1 1 +.names G103 G20 G73 +1- 1 +-1 1 +.names G112 G103 G96 G19 G77 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names G108 G76 G78 +1- 1 +-1 1 +.names G103 G14 G79 +1- 1 +-1 1 +.names G11 G14 G80 +1- 1 +-1 1 +.names G12 G13 G81 +1- 1 +-1 1 +.names G11 G12 G13 G96 G83 +1--- 1 +-1-- 1 +--1- 1 +---1 1 +.names G82 G91 G14 G84 +1-- 1 +-1- 1 +--1 1 +.names G91 G96 G17 G85 +1-- 1 +-1- 1 +--1 1 +.names G24 G25 G28 G43 +0-- 1 +-0- 1 +--0 1 +.names G83 G84 G85 G108 G97 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G68 G69 G70 G108 G101 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G77 G78 G106 +0- 1 +-0 1 +.names G79 G80 G81 G108 G116 +0--- 1 +-0-- 1 +--0- 1 +---0 1 +.names G26 G27 G53 +00 1 +.end Index: vis_dev/vis-2.1/examples/synthesis/vg2.blif =================================================================== --- vis_dev/vis-2.1/examples/synthesis/vg2.blif (revision 11) +++ vis_dev/vis-2.1/examples/synthesis/vg2.blif (revision 11) @@ -0,0 +1,131 @@ +.model vg2 +.inputs i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20 i21 i22 i23 i24 +.outputs F0 F1 F2 F3 F4 F5 F6 F7 + +.names i0 i1 i2 i3 i5 i6 i7 i10 i11 i13 i14 i19 i20 i24 F0 +-0-0-01-010-01 1 +1000-0-00-0-00 1 +-0-0101-0-0-01 1 +-0-010--010100 1 +-0-000--00010- 1 + +.names i0 i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 i12 i13 i14 i15 i16 i17 i18 i19 i20 i21 i22 i23 i24 F1 +-1-11-1-11-1111-111-1-111 1 +10000-0-00000-0-00--0-000 1 +-0-0010100-00-0-00--0-001 1 +-0-0010-00-0010-00-10-000 1 +-1011-1-11011-1-11--11110 1 +-1-1111-11-11-1-111-1-111 1 +-1-1111-11-1111111--1-110 1 +-0-00-0100-0010-00--0-001 1 +-0-0000-00-0000-00-10-00- 1 +-1-1101-11-1101111--1-11- 1 + +.names i1 i2 i3 i5 i6 i10 i11 i13 i14 i15 i18 i20 i21 i24 F2 +1-1-1-111-11-1 1 +101-101-1--110 1 +1-111-1-1-11-1 1 +1-111-1111-1-0 1 +1-101-1011-1-- 1 + +.names i0 i1 i2 i3 i5 i6 i7 i8 i10 i11 i13 i14 i15 i18 i19 i20 i21 i24 F3 +-1-1-1-1-111-1-1-1 1 +1000-0-000-0---0-0 1 +-0-010-0-010--10-0 1 +-0-01010-0-0---0-1 1 +-101-1-101-1---110 1 +-1-111-1-1-1-1-1-1 1 +-1-111-1-1111--1-0 1 +-0-0-010-010---0-1 1 +-0-000-0-000--10-- 1 +-1-101-1-1011--1-- 1 + +.names i0 i2 i4 i5 i7 i8 i9 i10 i13 i15 i16 i17 i18 i19 i21 i22 i23 i24 F4 +----11--1--------1 1 +101----0--0----000 1 +-00----0--1---1110 1 +--01----111----110 1 +--111-----0----001 1 +--11----1-0--1-000 1 +--01------1-1--111 1 +--1-1---1-0----001 1 +--10----0-0--1-00- 1 +--00----011----11- 1 +--0-----1-1-1--111 1 +10-----0--01---0-0 1 +---1----1110---1-0 1 +-0-----0--10--11-0 1 +---1------101--1-1 1 +---1----1-01-1-0-0 1 +---11-----01---0-1 1 +----1---1-01---0-1 1 +---0----0110---1-- 1 +--------1-101--1-1 1 +---0----0-01-1-0-- 1 +10----10--0------0 1 +-0----00--1---1--0 1 +---1--1-1-0--1---0 1 +---1--0-111------0 1 +---11-1---0------1 1 +---1--0---1-1----1 1 +---0--0-011------- 1 +---0--1-0-0--1---- 1 +----1-1-1-0------1 1 +------0-1-1-1----1 1 +---1-0--11-------0 1 +-0---0-0------1--0 1 +10---1-0---------0 1 +---1-0------1----1 1 +---1-1--1----1---0 1 +---111-----------1 1 +---0-0--01-------- 1 +-----0--1---1----1 1 +---0-1--0----1---- 1 + +.names i0 i2 i5 i7 i10 i13 i19 i24 F5 +---1-1-1 1 +10--0--0 1 +--11---1 1 +--1--110 1 +--0--01- 1 + +.names i0 i2 i3 i5 i6 i7 i10 i11 i13 i14 i15 i18 i19 i20 i21 i24 F6 +--1--1--1------1 1 +-0----01-1---010 1 +10----00-0---1-0 1 +---1---1-1-1-0-1 1 +---1---1111--0-0 1 +---1---010--11-0 1 +---0---1011--0-- 1 +---0---000--11-- 1 +-----1-010---1-1 1 +-------111-1-0-1 1 +---1-1-0-0---1-1 1 +---10--1---1---1 1 +10--1-00-------0 1 +---10--11-1----0 1 +-0--0-01------10 1 +---11--01---1--0 1 +---01--00---1--- 1 +----11-01------1 1 +----0--11--1---1 1 +---00--10-1----- 1 +---111-0-------1 1 +--01----1-1----0 1 +--11----1---1--0 1 +--01-------1---1 1 +101---0--------0 1 +--11-1---------1 1 +-00---0-------10 1 +--00----0-1----- 1 +--0-----1--1---1 1 +--10----0---1--- 1 + +.names i2 i5 i10 i13 i15 i18 i21 i24 F7 +-1---1-1 1 +0-0---10 1 +-1-11--0 1 +---1-1-1 1 +-0-01--- 1 + +.end Index: vis_dev/vis-2.1/examples/tlc/check_result =================================================================== --- vis_dev/vis-2.1/examples/tlc/check_result (revision 11) +++ vis_dev/vis-2.1/examples/tlc/check_result (revision 11) @@ -0,0 +1,30 @@ +FSM depth = 7 +reachable states = 20 +--Total states covered by formula<1> = 6 , new = 6 +---States covered w.r.t. farm_light = 6, new = 6 +---States covered w.r.t. hwy_light = 0, new = 0 +# MC: formula passed --- AG(!((farm_light=GREEN * hwy_light=GREEN))) +--Total states covered by formula<2> = 5 , new = 4 +---States covered w.r.t. car_present = 1, new = 1 +---States covered w.r.t. timer.state = 0, new = 0 +---States covered w.r.t. farm_light = 4, new = 4 +# MC: formula passed --- AG(((car_present=YES * timer.state=LONG) -> AF(farm_light=GREEN))) +--Total states covered by formula<3> = 6 , new = 0 +---States covered w.r.t. hwy_light = 6, new = 6 +# MC: formula passed --- AG(AF(hwy_light=GREEN)) +--Total states covered by formula<4> = 0 , new = 0 +---States covered w.r.t. car_present = 0, new = 0 +---States covered w.r.t. farm_light = 0, new = 0 +# MC: formula passed --- !(AG((car_present=YES -> AF(farm_light=GREEN)))) +# MC: formula failed --- AG((car_present=YES -> AF(farm_light=GREEN))) +# States covered w.r.t. Neither Primary output nor input(farm_light) = 10, Percentage of Coverage = 50.000000 +# States covered w.r.t. Neither Primary output nor input(hwy_light) = 6, Percentage of Coverage = 30.000000 +# States covered w.r.t. Neither Primary output nor input(car_present) = 1, Percentage of Coverage = 5.000000 +# States covered w.r.t. Neither Primary output nor input(timer.state) = 0, Percentage of Coverage = 0.000000 +--There are 10 covered states (using improved coverage implementation) +--0 states covered by Primary Input Signals +--0 states covered by Primary Ouput Signals +--17 states covered by signals which are neither Primary input nor output Signals +Percentage of coverage (using improved coverage implementation)= 50.000000 + Average Percentage of coverage = 21.250000 +Average Percentage of coverage for signals which are not primary = 21.250000 Index: vis_dev/vis-2.1/examples/tlc/check_script =================================================================== --- vis_dev/vis-2.1/examples/tlc/check_script (revision 11) +++ vis_dev/vis-2.1/examples/tlc/check_script (revision 11) @@ -0,0 +1,7 @@ +read_blif_mv tlc.mv +init_verify +compute_reach -v 1 +read_fairness tlc.fair +model_check -I tlc.ctl +time +quit -s Index: vis_dev/vis-2.1/examples/tlc/tlc.ctl =================================================================== --- vis_dev/vis-2.1/examples/tlc/tlc.ctl (revision 11) +++ vis_dev/vis-2.1/examples/tlc/tlc.ctl (revision 11) @@ -0,0 +1,20 @@ +#PASS: Light is not green both directions at the same time +AG ( !((farm_light = GREEN) * (hwy_light = GREEN)) ); + +#PASS: If car is present on farm road, and timer is long, then eventually the +#farm light will turn green. +AG(((car_present = YES) * (timer.state = LONG)) -> AF(farm_light = GREEN)); + +#PASS: Regardless of what happens on the farm road, the highway will always be +#green in the future. +AG(AF(hwy_light = GREEN)); + +#PASS: Even if a car is present on farm road, this does not guarantee that +#eventually the farm light will turn green. It could be that a car approaches, +#and then backs away, all before the timer goes long. Having the system satisfy +#this property is not necessary for safety, it just maximizes the time that +#the highway light is green. +!(AG((car_present = YES) -> AF(farm_light = GREEN))); + +#FAIL: The opposite of the above formula. Demonstrates the fair CTL debugger. +AG((car_present = YES) -> AF(farm_light = GREEN)); Index: vis_dev/vis-2.1/examples/tlc/tlc.fair =================================================================== --- vis_dev/vis-2.1/examples/tlc/tlc.fair (revision 11) +++ vis_dev/vis-2.1/examples/tlc/tlc.fair (revision 11) @@ -0,0 +1,7 @@ +#The timer leaves state START non-deterministically. This constraint +#prevents it from staying in START forever, without leaving. +!(timer.state=START); + +#The timer leaves state SHORT non-deterministically. This constraint +#prevents it from staying in SHORT forever, without leaving. +!(timer.state=SHORT); Index: vis_dev/vis-2.1/examples/tlc/tlc.mv =================================================================== --- vis_dev/vis-2.1/examples/tlc/tlc.mv (revision 11) +++ vis_dev/vis-2.1/examples/tlc/tlc.mv (revision 11) @@ -0,0 +1,599 @@ +# vl2mv tlc.v +# version: 0.2 +# date: 13:31:53 12/11/95 (PST) +.model main +# I/O ports + +.mv car_present 2 YES NO +.mv farm_light 3 GREEN YELLOW RED +.mv hwy_light 3 GREEN YELLOW RED +# assign start_timer = farm_start_timer || hwy_start_timer +# farm_start_timer || hwy_start_timer +.names farm_start_timer hwy_start_timer _n1 +.def 1 +0 0 0 +.names _n1 start_timer$raw_n0 +- =_n1 +.subckt timer timer start=start_timer short=short_timer long=long_timer +.subckt sensor sensor car_present=car_present +.subckt farm_control farm_control car_present=car_present enable_farm=enable_farm short_timer=short_timer long_timer=long_timer farm_light=farm_light farm_start_timer=farm_start_timer enable_hwy=enable_hwy +.subckt hwy_control hwy_control car_present=car_present enable_hwy=enable_hwy short_timer=short_timer long_timer=long_timer hwy_light=hwy_light hwy_start_timer=hwy_start_timer enable_farm=enable_farm +# conflict arbitrators +.names start_timer$raw_n0 start_timer +0 0 +1 1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model timer +# I/O ports +.outputs short +.outputs long +.inputs start + +.mv state 3 START SHORT LONG +# state = 0 +.mv state$raw_n2 3 START SHORT LONG +.names state$raw_n2 +START +# non-blocking assignments for initial +# assign rand_choice = $NDset ( 0,1 ) +.names rand_choice +0 +1 +# assign short = ((state == SHORT ) || (state == LONG )) +.mv _n7 3 START SHORT LONG +.names _n7 +SHORT +# state == 1 +.names state _n7 _n6 +.def 0 +- =state 1 +.mv _n9 3 START SHORT LONG +.names _n9 +LONG +# state == 2 +.names state _n9 _n8 +.def 0 +- =state 1 +# (state == 1) || (state == 2) +.names _n6 _n8 _na +.def 1 +0 0 0 +.names _na short$raw_n5 +- =_na +# assign long = (state == LONG ) +.mv _nd 3 START SHORT LONG +.names _nd +LONG +# state == 2 +.names state _nd _nc +.def 0 +- =state 1 +.names _nc long$raw_nb +- =_nc +.names start _ne +- =start +# state = 0 +.mv state$start_nf$true 3 START SHORT LONG +.names state$start_nf$true +START +.mv _n12 3 START SHORT LONG +.names _n12 +START +.names state _n12 _n11 +.def 0 +- =state 1 +.names _n11 _n10 +1 1 +0 0 +.names _n14 +1 +# rand_choice == 1 +.names rand_choice _n14 _n15 +.def 0 +0 1 1 +1 0 1 +.names _n15 _n13 +0 1 +1 0 +.names _n13 _n17 +- =_n13 +# state = 1 +.mv state$_n13_n18$true 3 START SHORT LONG +.names state$_n13_n18$true +SHORT +# if/else (rand_choice == 1) +.mv state$_n13$raw_n1b 3 START SHORT LONG +.names state$_n13_n18$true state _n13 state$_n13$raw_n1b +- - 0 =state +- - 1 =state$_n13_n18$true +.mv _n1e 3 START SHORT LONG +.names _n1e +SHORT +.names state _n1e _n1d +.def 0 +- =state 1 +.names _n1d _n1c +1 1 +0 0 +.names _n20 +1 +# rand_choice == 1 +.names rand_choice _n20 _n21 +.def 0 +0 1 1 +1 0 1 +.names _n21 _n1f +0 1 +1 0 +.names _n1f _n23 +- =_n1f +# state = 2 +.mv state$_n1f_n24$true 3 START SHORT LONG +.names state$_n1f_n24$true +LONG +# if/else (rand_choice == 1) +.mv state$_n1f$raw_n27 3 START SHORT LONG +.names state$_n1f_n24$true state _n1f state$_n1f$raw_n27 +- - 0 =state +- - 1 =state$_n1f_n24$true +# case (state ) +.mv state$_n1c$raw_n2a 3 START SHORT LONG +.names state$_n1f$raw_n27 state _n1c state$_n1c$raw_n2a +- - 0 =state +- - 1 =state$_n1f$raw_n27 +.mv state$_n10$raw_n2b 3 START SHORT LONG +.names state$_n13$raw_n1b state$_n1c$raw_n2a _n10 state$_n10$raw_n2b +- - 0 =state$_n1c$raw_n2a +- - 1 =state$_n13$raw_n1b +# if/else (start ) +.mv state$start$raw_n30 3 START SHORT LONG +.names state$start_nf$true state$_n10$raw_n2b start state$start$raw_n30 +- - 0 =state$_n10$raw_n2b +- - 1 =state$start_nf$true +# conflict arbitrators +.names short$raw_n5 short +0 0 +1 1 +.names long$raw_nb long +0 0 +1 1 +.names _ne _n10 _n17 _n1c _n23 _n33 +.def 0 + 1 - - - - 1 + 0 1 1 - - 1 + 0 0 - 1 1 1 +.mv _n34 3 START SHORT LONG +.names _n33 state$start$raw_n30 state _n34 +1 - - =state$start$raw_n30 +0 - - =state +# non-blocking assignments +# latches +.r state$raw_n2 state +- =state$raw_n2 +.latch _n34 state +# quasi-continuous assignment +.end + + +.model sensor +# I/O ports +.outputs car_present + +.mv car_present 2 YES NO +# car_present = 1 +.mv car_present$raw_n3a 2 YES NO +.names car_present$raw_n3a +NO +# non-blocking assignments for initial +# assign rand_choice = $NDset ( 0,1 ) +.names rand_choice +0 +1 +.names _n3e +0 +# rand_choice == 0 +.names rand_choice _n3e _n3f +.def 0 +0 1 1 +1 0 1 +.names _n3f _n3d +0 1 +1 0 +.names _n3d _n41 +- =_n3d +# car_present = 1 +.mv car_present$_n3d_n42$true 2 YES NO +.names car_present$_n3d_n42$true +NO +# car_present = 0 +.mv car_present$_n3d_n43$false 2 YES NO +.names car_present$_n3d_n43$false +YES +# if/else (rand_choice == 0) +.mv car_present$_n3d$raw_n45 2 YES NO +.names car_present$_n3d_n42$true car_present$_n3d_n43$false _n3d car_present$_n3d$raw_n45 +- - 0 =car_present$_n3d_n43$false +- - 1 =car_present$_n3d_n42$true +# conflict arbitrators +.names _n41 _n48 +.def 0 + 1 1 + 0 1 +.mv _n49 2 YES NO +.names _n48 car_present$_n3d$raw_n45 car_present _n49 +1 - - =car_present$_n3d$raw_n45 +0 - - =car_present +# non-blocking assignments +# latches +.r car_present$raw_n3a car_present +- =car_present$raw_n3a +.latch _n49 car_present +# quasi-continuous assignment +.end + + +.model farm_control +# I/O ports +.inputs car_present +.outputs farm_light +.inputs enable_farm +.inputs long_timer +.inputs short_timer +.outputs farm_start_timer +.outputs enable_hwy + +.mv car_present 2 YES NO +.mv farm_light 3 GREEN YELLOW RED +# farm_light = 2 +.mv farm_light$raw_n4c 3 GREEN YELLOW RED +.names farm_light$raw_n4c +RED +# non-blocking assignments for initial +# assign farm_start_timer = (((farm_light == GREEN ) && ((car_present == NO ) || long_timer )) || (farm_light == RED ) && enable_farm ) +.mv _n4f 3 GREEN YELLOW RED +.names _n4f +GREEN +# farm_light == 0 +.names farm_light _n4f _n4e +.def 0 +- =farm_light 1 +.mv _n51 2 YES NO +.names _n51 +NO +# car_present == 1 +.names car_present _n51 _n50 +.def 0 +- =car_present 1 +# (car_present == 1) || long_timer +.names _n50 long_timer _n52 +.def 1 +0 0 0 +# (farm_light == 0) && ((car_present == 1) || long_timer ) +.names _n4e _n52 _n53 +.def 0 +1 1 1 +.mv _n55 3 GREEN YELLOW RED +.names _n55 +RED +# farm_light == 2 +.names farm_light _n55 _n54 +.def 0 +- =farm_light 1 +# (farm_light == 2) && enable_farm +.names _n54 enable_farm _n56 +.def 0 +1 1 1 +# ((farm_light == 0) && ((car_present == 1) || long_timer )) || (farm_light == 2) && enable_farm +.names _n53 _n56 _n57 +.def 1 +0 0 0 +.names _n57 farm_start_timer$raw_n4d +- =_n57 +# assign enable_hwy = ((farm_light == YELLOW ) && short_timer ) +.mv _n5a 3 GREEN YELLOW RED +.names _n5a +YELLOW +# farm_light == 1 +.names farm_light _n5a _n59 +.def 0 +- =farm_light 1 +# (farm_light == 1) && short_timer +.names _n59 short_timer _n5b +.def 0 +1 1 1 +.names _n5b enable_hwy$raw_n58 +- =_n5b +.mv _n5e 3 GREEN YELLOW RED +.names _n5e +GREEN +.names farm_light _n5e _n5d +.def 0 +- =farm_light 1 +.names _n5d _n5c +1 1 +0 0 +.mv _n60 2 YES NO +.names _n60 +NO +# car_present == 1 +.names car_present _n60 _n5f +.def 0 +- =car_present 1 +# (car_present == 1) || long_timer +.names _n5f long_timer _n61 +.def 1 +0 0 0 +.names _n61 _n62 +- =_n61 +# farm_light = 1 +.mv farm_light$_n61_n63$true 3 GREEN YELLOW RED +.names farm_light$_n61_n63$true +YELLOW +# if/else ((car_present == 1) || long_timer ) +.mv farm_light$_n61$raw_n66 3 GREEN YELLOW RED +.names farm_light$_n61_n63$true farm_light _n61 farm_light$_n61$raw_n66 +- - 0 =farm_light +- - 1 =farm_light$_n61_n63$true +.mv _n69 3 GREEN YELLOW RED +.names _n69 +YELLOW +.names farm_light _n69 _n68 +.def 0 +- =farm_light 1 +.names _n68 _n67 +1 1 +0 0 +.names short_timer _n6a +- =short_timer +# farm_light = 2 +.mv farm_light$short_timer_n6b$true 3 GREEN YELLOW RED +.names farm_light$short_timer_n6b$true +RED +# if/else (short_timer ) +.mv farm_light$short_timer$raw_n6e 3 GREEN YELLOW RED +.names farm_light$short_timer_n6b$true farm_light short_timer farm_light$short_timer$raw_n6e +- - 0 =farm_light +- - 1 =farm_light$short_timer_n6b$true +.mv _n71 3 GREEN YELLOW RED +.names _n71 +RED +.names farm_light _n71 _n70 +.def 0 +- =farm_light 1 +.names _n70 _n6f +1 1 +0 0 +.names enable_farm _n72 +- =enable_farm +# farm_light = 0 +.mv farm_light$enable_farm_n73$true 3 GREEN YELLOW RED +.names farm_light$enable_farm_n73$true +GREEN +# if/else (enable_farm ) +.mv farm_light$enable_farm$raw_n76 3 GREEN YELLOW RED +.names farm_light$enable_farm_n73$true farm_light enable_farm farm_light$enable_farm$raw_n76 +- - 0 =farm_light +- - 1 =farm_light$enable_farm_n73$true +# case (farm_light ) +.mv farm_light$_n6f$raw_n79 3 GREEN YELLOW RED +.names farm_light$enable_farm$raw_n76 farm_light _n6f farm_light$_n6f$raw_n79 +- - 0 =farm_light +- - 1 =farm_light$enable_farm$raw_n76 +.mv farm_light$_n67$raw_n7a 3 GREEN YELLOW RED +.names farm_light$short_timer$raw_n6e farm_light$_n6f$raw_n79 _n67 farm_light$_n67$raw_n7a +- - 0 =farm_light$_n6f$raw_n79 +- - 1 =farm_light$short_timer$raw_n6e +.mv farm_light$_n5c$raw_n7e 3 GREEN YELLOW RED +.names farm_light$_n61$raw_n66 farm_light$_n67$raw_n7a _n5c farm_light$_n5c$raw_n7e +- - 0 =farm_light$_n67$raw_n7a +- - 1 =farm_light$_n61$raw_n66 +# conflict arbitrators +.names _n5c _n62 _n67 _n6a _n6f _n72 _n82 +.def 0 + 1 1 - - - - 1 + 0 - 1 1 - - 1 + 0 - 0 - 1 1 1 +.mv _n83 3 GREEN YELLOW RED +.names _n82 farm_light$_n5c$raw_n7e farm_light _n83 +1 - - =farm_light$_n5c$raw_n7e +0 - - =farm_light +.names farm_start_timer$raw_n4d farm_start_timer +0 0 +1 1 +.names enable_hwy$raw_n58 enable_hwy +0 0 +1 1 +# non-blocking assignments +# latches +.r farm_light$raw_n4c farm_light +- =farm_light$raw_n4c +.latch _n83 farm_light +# quasi-continuous assignment +.end + + +.model hwy_control +# I/O ports +.inputs car_present +.outputs enable_farm +.inputs long_timer +.inputs short_timer +.outputs hwy_light +.outputs hwy_start_timer +.inputs enable_hwy + +.mv car_present 2 YES NO +.mv hwy_light 3 GREEN YELLOW RED +# hwy_light = 0 +.mv hwy_light$raw_n8b 3 GREEN YELLOW RED +.names hwy_light$raw_n8b +GREEN +# non-blocking assignments for initial +# assign hwy_start_timer = (((hwy_light == GREEN ) && ((car_present == YES ) && long_timer )) || (hwy_light == RED ) && enable_hwy ) +.mv _n8e 3 GREEN YELLOW RED +.names _n8e +GREEN +# hwy_light == 0 +.names hwy_light _n8e _n8d +.def 0 +- =hwy_light 1 +.mv _n90 2 YES NO +.names _n90 +YES +# car_present == 0 +.names car_present _n90 _n8f +.def 0 +- =car_present 1 +# (car_present == 0) && long_timer +.names _n8f long_timer _n91 +.def 0 +1 1 1 +# (hwy_light == 0) && ((car_present == 0) && long_timer ) +.names _n8d _n91 _n92 +.def 0 +1 1 1 +.mv _n94 3 GREEN YELLOW RED +.names _n94 +RED +# hwy_light == 2 +.names hwy_light _n94 _n93 +.def 0 +- =hwy_light 1 +# (hwy_light == 2) && enable_hwy +.names _n93 enable_hwy _n95 +.def 0 +1 1 1 +# ((hwy_light == 0) && ((car_present == 0) && long_timer )) || (hwy_light == 2) && enable_hwy +.names _n92 _n95 _n96 +.def 1 +0 0 0 +.names _n96 hwy_start_timer$raw_n8c +- =_n96 +# assign enable_farm = ((hwy_light == YELLOW ) && short_timer ) +.mv _n99 3 GREEN YELLOW RED +.names _n99 +YELLOW +# hwy_light == 1 +.names hwy_light _n99 _n98 +.def 0 +- =hwy_light 1 +# (hwy_light == 1) && short_timer +.names _n98 short_timer _n9a +.def 0 +1 1 1 +.names _n9a enable_farm$raw_n97 +- =_n9a +.mv _n9d 3 GREEN YELLOW RED +.names _n9d +GREEN +.names hwy_light _n9d _n9c +.def 0 +- =hwy_light 1 +.names _n9c _n9b +1 1 +0 0 +.mv _n9f 2 YES NO +.names _n9f +YES +# car_present == 0 +.names car_present _n9f _n9e +.def 0 +- =car_present 1 +# (car_present == 0) && long_timer +.names _n9e long_timer _na0 +.def 0 +1 1 1 +.names _na0 _na1 +- =_na0 +# hwy_light = 1 +.mv hwy_light$_na0_na2$true 3 GREEN YELLOW RED +.names hwy_light$_na0_na2$true +YELLOW +# if/else ((car_present == 0) && long_timer ) +.mv hwy_light$_na0$raw_na5 3 GREEN YELLOW RED +.names hwy_light$_na0_na2$true hwy_light _na0 hwy_light$_na0$raw_na5 +- - 0 =hwy_light +- - 1 =hwy_light$_na0_na2$true +.mv _na8 3 GREEN YELLOW RED +.names _na8 +YELLOW +.names hwy_light _na8 _na7 +.def 0 +- =hwy_light 1 +.names _na7 _na6 +1 1 +0 0 +.names short_timer _na9 +- =short_timer +# hwy_light = 2 +.mv hwy_light$short_timer_naa$true 3 GREEN YELLOW RED +.names hwy_light$short_timer_naa$true +RED +# if/else (short_timer ) +.mv hwy_light$short_timer$raw_nad 3 GREEN YELLOW RED +.names hwy_light$short_timer_naa$true hwy_light short_timer hwy_light$short_timer$raw_nad +- - 0 =hwy_light +- - 1 =hwy_light$short_timer_naa$true +.mv _nb0 3 GREEN YELLOW RED +.names _nb0 +RED +.names hwy_light _nb0 _naf +.def 0 +- =hwy_light 1 +.names _naf _nae +1 1 +0 0 +.names enable_hwy _nb1 +- =enable_hwy +# hwy_light = 0 +.mv hwy_light$enable_hwy_nb2$true 3 GREEN YELLOW RED +.names hwy_light$enable_hwy_nb2$true +GREEN +# if/else (enable_hwy ) +.mv hwy_light$enable_hwy$raw_nb5 3 GREEN YELLOW RED +.names hwy_light$enable_hwy_nb2$true hwy_light enable_hwy hwy_light$enable_hwy$raw_nb5 +- - 0 =hwy_light +- - 1 =hwy_light$enable_hwy_nb2$true +# case (hwy_light ) +.mv hwy_light$_nae$raw_nb8 3 GREEN YELLOW RED +.names hwy_light$enable_hwy$raw_nb5 hwy_light _nae hwy_light$_nae$raw_nb8 +- - 0 =hwy_light +- - 1 =hwy_light$enable_hwy$raw_nb5 +.mv hwy_light$_na6$raw_nb9 3 GREEN YELLOW RED +.names hwy_light$short_timer$raw_nad hwy_light$_nae$raw_nb8 _na6 hwy_light$_na6$raw_nb9 +- - 0 =hwy_light$_nae$raw_nb8 +- - 1 =hwy_light$short_timer$raw_nad +.mv hwy_light$_n9b$raw_nbd 3 GREEN YELLOW RED +.names hwy_light$_na0$raw_na5 hwy_light$_na6$raw_nb9 _n9b hwy_light$_n9b$raw_nbd +- - 0 =hwy_light$_na6$raw_nb9 +- - 1 =hwy_light$_na0$raw_na5 +# conflict arbitrators +.names enable_farm$raw_n97 enable_farm +0 0 +1 1 +.names _n9b _na1 _na6 _na9 _nae _nb1 _nc1 +.def 0 + 1 1 - - - - 1 + 0 - 1 1 - - 1 + 0 - 0 - 1 1 1 +.mv _nc2 3 GREEN YELLOW RED +.names _nc1 hwy_light$_n9b$raw_nbd hwy_light _nc2 +1 - - =hwy_light$_n9b$raw_nbd +0 - - =hwy_light +.names hwy_start_timer$raw_n8c hwy_start_timer +0 0 +1 1 +# non-blocking assignments +# latches +.r hwy_light$raw_n8b hwy_light +- =hwy_light$raw_n8b +.latch _nc2 hwy_light +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/tlc/tlc.v =================================================================== --- vis_dev/vis-2.1/examples/tlc/tlc.v (revision 11) +++ vis_dev/vis-2.1/examples/tlc/tlc.v (revision 11) @@ -0,0 +1,222 @@ +/************************************************************************** + Adaptation of Mead and Conway traffic light controller. + + A little used farm road intersects with a multi-lane highway; a traffic + light controls the traffic at the intersection. + The light controller is implemented to maximize the time the highway light + remains green. A submodule implements a timer, which outputs "short" and + "long" time outs. The highway light stays green for at least "long" time. + Any time after "long" time, if there is a car waiting on the farm road, then + the farm light turns green. The farm light remains green until there are no + more cars on the farm road, or until the long timer expires. The yellow + light for both directions stays yellow for "short" time. + + The timer has non-determinism in it. Liveness properties won't pass until + fairness constraints are placed on the timer, so that it can't pause + forever. + + Tom Shiple, 25 October 1995 + +***************************************************************************/ + +/* + * Symbolic variables. + */ +typedef enum {YES, NO} boolean; +typedef enum {START, SHORT, LONG} timer_state; +typedef enum {GREEN, YELLOW, RED} color; + +/* + * Module main ties together the underlying modules. In addition, it + * ORs together the start timer outputs of the farm road and highway + * controllers. Note that only a single timer is used for both the farm + * road and highway controllers. In theory, this could lead to conflicts; as + * implemented, such conflicts are avoided. + */ +module main(clk); +input clk; + +color wire farm_light, hwy_light; +wire start_timer, short_timer, long_timer; +boolean wire car_present; +wire enable_farm, farm_start_timer, enable_hwy, hwy_start_timer; + +assign start_timer = farm_start_timer || hwy_start_timer; + +timer timer(clk, start_timer, short_timer, long_timer); +sensor sensor(clk, car_present); +farm_control farm_control(clk, car_present, enable_farm, short_timer, long_timer, + farm_light, farm_start_timer, enable_hwy); +hwy_control hwy_control (clk, car_present, enable_hwy, short_timer, long_timer, + hwy_light, hwy_start_timer, enable_farm); + + +endmodule + + +/* + * There is a single, coupled sensor that detects the presence of a car + * in either direction of the farm road. At each clock tick, it non- + * deterministically reports that a car is present or not. + */ +module sensor(clk, car_present); +input clk; +output car_present; + +wire rand_choice; +boolean reg car_present; + +initial car_present = NO; + +assign rand_choice = $ND(0,1); + +always @(posedge clk) begin + if (rand_choice == 0) + car_present = NO; + else + car_present = YES; +end +endmodule + + +/* + * From the START state, the timer produces the signal "short" + * after a non-deterministic amount of time. The signal "short" + * remains asserted until the timer is reset (via the signal "start"). + * From the SHORT state, the timer produces the signal "long" + * after a non-deterministic amount of time. The signal "long" + * remains asserted until the timer is reset (via the signal "start"). + * The following Buchi fairness constraints should be used: + * + * !(timer.state=START); + * !(timer.state=SHORT); + */ +module timer(clk, start, short, long); +input clk; +input start; +output short; +output long; + +wire rand_choice; +wire start, short, long; +timer_state reg state; + +initial state = START; + +assign rand_choice = $ND(0,1); + +/* short could as well be assigned to be just (state == SHORT) */ +assign short = ((state == SHORT) || (state == LONG)); +assign long = (state == LONG); + +always @(posedge clk) begin + if (start) state = START; + else + begin + case (state) + START: + if (rand_choice == 1) state = SHORT; + SHORT: + if (rand_choice == 1) state = LONG; + /* if LONG, remains LONG until start signal received */ + endcase + end +end +endmodule + + +/* + * Farm light stays RED until it is enabled by the highway control. At + * this point, it resets the timer, and moves to GREEN. It stays in GREEN + * until there are no cars, or the long timer expires. At this point, it + * moves to YELLOW and resets the timer. It stays in YELLOW until the short + * timer expires. At this point, it moves to RED and enables the highway + * controller. + */ +module farm_control(clk, car_present, enable_farm, short_timer, long_timer, + farm_light, farm_start_timer, enable_hwy); +input clk; +input car_present; +input enable_farm; +input short_timer; +input long_timer; +output farm_light; +output farm_start_timer; +output enable_hwy; + +boolean wire car_present; +wire short_timer, long_timer; +wire farm_start_timer; +wire enable_hwy; +wire enable_farm; + +color reg farm_light; + +initial farm_light = RED; + +assign farm_start_timer = (((farm_light == GREEN) + && ((car_present == NO) || long_timer)) + || + (farm_light == RED) && enable_farm); +assign enable_hwy = ((farm_light == YELLOW) && short_timer); + +always @(posedge clk) begin + case (farm_light) + GREEN: + if ((car_present == NO) || long_timer) farm_light = YELLOW; + YELLOW: + if (short_timer) farm_light = RED; + RED: + if (enable_farm) farm_light = GREEN; + endcase +end +endmodule + + +/* + * Highway light stays RED until it is enabled by the farm control. At + * this point, it resets the timer, and moves to GREEN. It stays in GREEN + * until there are cars and the long timer expires. At this point, it + * moves to YELLOW and resets the timer. It stays in YELLOW until the short + * timer expires. At this point, it moves to RED and enables the farm + * controller. + */ +module hwy_control(clk, car_present, enable_hwy, short_timer, long_timer, + hwy_light, hwy_start_timer, enable_farm); +input clk; +input car_present; +input enable_hwy; +input short_timer; +input long_timer; +output hwy_light; +output hwy_start_timer; +output enable_farm; + +boolean wire car_present; +wire short_timer, long_timer; +wire hwy_start_timer; +wire enable_farm; +wire enable_hwy; + +color reg hwy_light; + +initial hwy_light = GREEN; + +assign hwy_start_timer = (((hwy_light == GREEN) + && ((car_present == YES) && long_timer)) + || + (hwy_light == RED) && enable_hwy); + +assign enable_farm = ((hwy_light == YELLOW) && short_timer); + +always @(posedge clk) begin + case (hwy_light) + GREEN: + if ((car_present == YES) && long_timer) hwy_light = YELLOW; + YELLOW: + if (short_timer) hwy_light = RED; + RED: + if (enable_hwy) hwy_light = GREEN; + endcase +end +endmodule Index: vis_dev/vis-2.1/examples/treearbiter/4-arbit.ctl =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/4-arbit.ctl (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/4-arbit.ctl (revision 11) @@ -0,0 +1,9 @@ +# never have both cells holding the token at the same time +AG ( ! ( ( C1.holdToken = myTRUE ) * ( C2.holdToken = myTRUE) ) ); + +# never have G1.P3 and G1.P2 holding the token; +# actually need a formula for each pair of procs... +AG ( ! ( ( P3.procState = lock ) * ( P2.procState = lock) ) ); + +# ensures liveness - needs fairness on the procs to pass +AG ( ( P3.procState = request ) -> AF ( P3.procState = lock) ); Index: vis_dev/vis-2.1/examples/treearbiter/4-arbit.fair =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/4-arbit.fair (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/4-arbit.fair (revision 11) @@ -0,0 +1,8 @@ +# P1 doesnt hold the token forever +!(P1.procState=lock); + +!(P2.procState=lock); + +!(P3.procState=lock); + +!(P4.procState=lock); Index: vis_dev/vis-2.1/examples/treearbiter/4-arbit.mv =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/4-arbit.mv (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/4-arbit.mv (revision 11) @@ -0,0 +1,1001 @@ +# /home/sharma/vl2mv/i586/bin/vl2mv 4-arbit.v +# version: 0.2 +# date: 20:34:06 07/21/96 (CDT) +.model main +# I/O ports + +.mv constFALSE 2 myTRUE myFALSE +.mv sa 2 myTRUE myFALSE +.mv ur1 4 idle request lock release +.mv xa 2 myTRUE myFALSE +.mv ur2 4 idle request lock release +.mv yr 4 idle request lock release +.mv ur3 4 idle request lock release +.mv ua1 2 myTRUE myFALSE +.mv ur4 4 idle request lock release +.mv ua2 2 myTRUE myFALSE +.mv sr 4 idle request lock release +.mv ua3 2 myTRUE myFALSE +.mv ua4 2 myTRUE myFALSE +.mv xr 4 idle request lock release +.mv ya 2 myTRUE myFALSE +.mv constTRUE 2 myTRUE myFALSE +# assign constTRUE = 0 +.mv constTRUE$raw_n0 2 myTRUE myFALSE +.names constTRUE$raw_n0 +myTRUE +# assign constFALSE = 1 +.mv constFALSE$raw_n1 2 myTRUE myFALSE +.names constFALSE$raw_n1 +myFALSE +# assign sa = constFALSE +.mv sa$raw_n2 2 myTRUE myFALSE +.names constFALSE sa$raw_n2 +- =constFALSE +.subckt arbitCell C0 topCell=constTRUE urLeft=xr urRight=yr uaLeft=xa uaRight=ya xr=sr xa=sa +.subckt arbitCell C1 topCell=constFALSE urLeft=ur1 urRight=ur2 uaLeft=ua1 uaRight=ua2 xr=xr xa=xa +.subckt arbitCell C2 topCell=constFALSE urLeft=ur3 urRight=ur4 uaLeft=ua3 uaRight=ua4 xr=yr xa=ya +.subckt procModel P1 ack=ua1 req=ur1 +.subckt procModel P2 ack=ua2 req=ur2 +.subckt procModel P3 ack=ua3 req=ur3 +.subckt procModel P4 ack=ua4 req=ur4 +# conflict arbitrators +.names constFALSE$raw_n1 constFALSE +- =constFALSE$raw_n1 +.names sa$raw_n2 sa +- =sa$raw_n2 +.names constTRUE$raw_n0 constTRUE +- =constTRUE$raw_n0 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model arbitCell +# I/O ports +.outputs uaLeft +.inputs topCell +.inputs xa +.inputs urRight +.inputs urLeft +.outputs xr +.outputs uaRight + +.mv processedLeft 2 myTRUE myFALSE +.mv prevLeft 2 myTRUE myFALSE +.mv holdToken 2 myTRUE myFALSE +.mv processedRight 2 myTRUE myFALSE +.mv uaLeft 2 myTRUE myFALSE +.mv topCell 2 myTRUE myFALSE +.mv xa 2 myTRUE myFALSE +.mv urRight 4 idle request lock release +.mv giveChild 2 myTRUE myFALSE +.mv urLeft 4 idle request lock release +.mv mustGiveParent 2 myTRUE myFALSE +.mv xr 4 idle request lock release +.mv uaRight 2 myTRUE myFALSE +.mv childOwns 2 myTRUE myFALSE +.mv prevRight 2 myTRUE myFALSE +# prevLeft = 1 +.mv prevLeft$raw_n3 2 myTRUE myFALSE +.names prevLeft$raw_n3 +myFALSE +# non-blocking assignments for initial +# prevRight = 0 +.mv prevRight$raw_n4 2 myTRUE myFALSE +.names prevRight$raw_n4 +myTRUE +# non-blocking assignments for initial +# processedLeft = 1 +.mv processedLeft$raw_n5 2 myTRUE myFALSE +.names processedLeft$raw_n5 +myFALSE +# non-blocking assignments for initial +# processedRight = 1 +.mv processedRight$raw_n6 2 myTRUE myFALSE +.names processedRight$raw_n6 +myFALSE +# non-blocking assignments for initial +# assign mustGiveParent = (processedLeft == 0) && (processedRight == 0) && (!(topCell == 0)) ? 0 : 1 +.mv mustGiveParent$raw_n7 2 myTRUE myFALSE +.mv _n9 2 myTRUE myFALSE +.names _n9 +myTRUE +# processedLeft == 0 +.names processedLeft _n9 _n8 +.def 0 +- =processedLeft 1 +.mv _nb 2 myTRUE myFALSE +.names _nb +myTRUE +# processedRight == 0 +.names processedRight _nb _na +.def 0 +- =processedRight 1 +# (processedLeft == 0) && (processedRight == 0) +.names _n8 _na _nc +.def 0 +1 1 1 +.mv _ne 2 myTRUE myFALSE +.names _ne +myTRUE +# topCell == 0 +.names topCell _ne _nd +.def 0 +- =topCell 1 +.names _nd _nf +0 1 +1 0 +# (processedLeft == 0) && (processedRight == 0) && (!(topCell == 0)) +.names _nc _nf _n10 +.def 0 +1 1 1 +.mv _n11 2 myTRUE myFALSE +.names _n11 +myTRUE +.mv _n12 2 myTRUE myFALSE +.names _n12 +myFALSE +# (processedLeft == 0) && (processedRight == 0) && (!(topCell == 0)) ? 0 : 1 +.mv _n13 2 myTRUE myFALSE +.names _n11 _n12 _n10 _n13 +- - 0 =_n12 +- - 1 =_n11 +.names _n13 mustGiveParent$raw_n7 +- =_n13 +# holdToken = topCell +.mv holdToken$raw_n14 2 myTRUE myFALSE +.names topCell holdToken$raw_n14 +- =topCell +# non-blocking assignments for initial +# assign childOwns = (urLeft == lock || urRight == lock ) ? 0 : 1 +.mv childOwns$raw_n15 2 myTRUE myFALSE +.mv _n17 4 idle request lock release +.names _n17 +lock +# urLeft == 2 +.names urLeft _n17 _n16 +.def 0 +- =urLeft 1 +.mv _n19 4 idle request lock release +.names _n19 +lock +# urRight == 2 +.names urRight _n19 _n18 +.def 0 +- =urRight 1 +# urLeft == 2 || urRight == 2 +.names _n16 _n18 _n1a +.def 1 +0 0 0 +.mv _n1b 2 myTRUE myFALSE +.names _n1b +myTRUE +.mv _n1c 2 myTRUE myFALSE +.names _n1c +myFALSE +# (urLeft == 2 || urRight == 2) ? 0 : 1 +.mv _n1d 2 myTRUE myFALSE +.names _n1b _n1c _n1a _n1d +- - 0 =_n1c +- - 1 =_n1b +.names _n1d childOwns$raw_n15 +- =_n1d +# assign giveChild = (uaLeft == 0 || uaRight == 0) ? 0 : 1 +.mv giveChild$raw_n1e 2 myTRUE myFALSE +.mv _n20 2 myTRUE myFALSE +.names _n20 +myTRUE +# uaLeft == 0 +.names uaLeft _n20 _n1f +.def 0 +- =uaLeft 1 +.mv _n22 2 myTRUE myFALSE +.names _n22 +myTRUE +# uaRight == 0 +.names uaRight _n22 _n21 +.def 0 +- =uaRight 1 +# uaLeft == 0 || uaRight == 0 +.names _n1f _n21 _n23 +.def 1 +0 0 0 +.mv _n24 2 myTRUE myFALSE +.names _n24 +myTRUE +.mv _n25 2 myTRUE myFALSE +.names _n25 +myFALSE +# (uaLeft == 0 || uaRight == 0) ? 0 : 1 +.mv _n26 2 myTRUE myFALSE +.names _n24 _n25 _n23 _n26 +- - 0 =_n25 +- - 1 =_n24 +.names _n26 giveChild$raw_n1e +- =_n26 +# assign uaLeft = (!(mustGiveParent == 0) && (holdToken == 0 && urLeft == request && (!(urRight == request ) || prevRight == 0))) ? 0 : 1 +.mv uaLeft$raw_n27 2 myTRUE myFALSE +.mv _n29 2 myTRUE myFALSE +.names _n29 +myTRUE +# mustGiveParent == 0 +.names mustGiveParent _n29 _n28 +.def 0 +- =mustGiveParent 1 +.names _n28 _n2a +0 1 +1 0 +.mv _n2c 2 myTRUE myFALSE +.names _n2c +myTRUE +# holdToken == 0 +.names holdToken _n2c _n2b +.def 0 +- =holdToken 1 +.mv _n2e 4 idle request lock release +.names _n2e +request +# urLeft == 1 +.names urLeft _n2e _n2d +.def 0 +- =urLeft 1 +# holdToken == 0 && urLeft == 1 +.names _n2b _n2d _n2f +.def 0 +1 1 1 +.mv _n31 4 idle request lock release +.names _n31 +request +# urRight == 1 +.names urRight _n31 _n30 +.def 0 +- =urRight 1 +.names _n30 _n32 +0 1 +1 0 +.mv _n34 2 myTRUE myFALSE +.names _n34 +myTRUE +# prevRight == 0 +.names prevRight _n34 _n33 +.def 0 +- =prevRight 1 +# !(urRight == 1) || prevRight == 0 +.names _n32 _n33 _n35 +.def 1 +0 0 0 +# holdToken == 0 && urLeft == 1 && (!(urRight == 1) || prevRight == 0) +.names _n2f _n35 _n36 +.def 0 +1 1 1 +# !(mustGiveParent == 0) && (holdToken == 0 && urLeft == 1 && (!(urRight == 1) || prevRight == 0)) +.names _n2a _n36 _n37 +.def 0 +1 1 1 +.mv _n38 2 myTRUE myFALSE +.names _n38 +myTRUE +.mv _n39 2 myTRUE myFALSE +.names _n39 +myFALSE +# (!(mustGiveParent == 0) && (holdToken == 0 && urLeft == 1 && (!(urRight == 1) || prevRight == 0))) ? 0 : 1 +.mv _n3a 2 myTRUE myFALSE +.names _n38 _n39 _n37 _n3a +- - 0 =_n39 +- - 1 =_n38 +.names _n3a uaLeft$raw_n27 +- =_n3a +# assign uaRight = (!(mustGiveParent == 0) && (holdToken == 0 && urRight == request && (!(urLeft == request ) || prevLeft == 0))) ? 0 : 1 +.mv uaRight$raw_n3b 2 myTRUE myFALSE +.mv _n3d 2 myTRUE myFALSE +.names _n3d +myTRUE +# mustGiveParent == 0 +.names mustGiveParent _n3d _n3c +.def 0 +- =mustGiveParent 1 +.names _n3c _n3e +0 1 +1 0 +.mv _n40 2 myTRUE myFALSE +.names _n40 +myTRUE +# holdToken == 0 +.names holdToken _n40 _n3f +.def 0 +- =holdToken 1 +.mv _n42 4 idle request lock release +.names _n42 +request +# urRight == 1 +.names urRight _n42 _n41 +.def 0 +- =urRight 1 +# holdToken == 0 && urRight == 1 +.names _n3f _n41 _n43 +.def 0 +1 1 1 +.mv _n45 4 idle request lock release +.names _n45 +request +# urLeft == 1 +.names urLeft _n45 _n44 +.def 0 +- =urLeft 1 +.names _n44 _n46 +0 1 +1 0 +.mv _n48 2 myTRUE myFALSE +.names _n48 +myTRUE +# prevLeft == 0 +.names prevLeft _n48 _n47 +.def 0 +- =prevLeft 1 +# !(urLeft == 1) || prevLeft == 0 +.names _n46 _n47 _n49 +.def 1 +0 0 0 +# holdToken == 0 && urRight == 1 && (!(urLeft == 1) || prevLeft == 0) +.names _n43 _n49 _n4a +.def 0 +1 1 1 +# !(mustGiveParent == 0) && (holdToken == 0 && urRight == 1 && (!(urLeft == 1) || prevLeft == 0)) +.names _n3e _n4a _n4b +.def 0 +1 1 1 +.mv _n4c 2 myTRUE myFALSE +.names _n4c +myTRUE +.mv _n4d 2 myTRUE myFALSE +.names _n4d +myFALSE +# (!(mustGiveParent == 0) && (holdToken == 0 && urRight == 1 && (!(urLeft == 1) || prevLeft == 0))) ? 0 : 1 +.mv _n4e 2 myTRUE myFALSE +.names _n4c _n4d _n4b _n4e +- - 0 =_n4d +- - 1 =_n4c +.names _n4e uaRight$raw_n3b +- =_n4e +# assign xr = (holdToken == myFALSE && (urLeft == 1 || urRight == 1)) ? 1 : (childOwns == myTRUE ) ? 2 : (holdToken == myTRUE && (((mustGiveParent == myTRUE ) || !((urLeft == 1 || urRight == 1))) && !(topCell == myTRUE ))) ? 3 : 0 +.mv xr$raw_n4f 4 idle request lock release +.mv _n51 2 myTRUE myFALSE +.names _n51 +myFALSE +# holdToken == 1 +.names holdToken _n51 _n50 +.def 0 +- =holdToken 1 +.mv _n53 4 idle request lock release +.names _n53 +request +# urLeft == 1 +.names urLeft _n53 _n52 +.def 0 +- =urLeft 1 +.mv _n55 4 idle request lock release +.names _n55 +request +# urRight == 1 +.names urRight _n55 _n54 +.def 0 +- =urRight 1 +# urLeft == 1 || urRight == 1 +.names _n52 _n54 _n56 +.def 1 +0 0 0 +# holdToken == 1 && (urLeft == 1 || urRight == 1) +.names _n50 _n56 _n57 +.def 0 +1 1 1 +.mv _n59 2 myTRUE myFALSE +.names _n59 +myTRUE +# childOwns == 0 +.names childOwns _n59 _n58 +.def 0 +- =childOwns 1 +.mv _n5b 2 myTRUE myFALSE +.names _n5b +myTRUE +# holdToken == 0 +.names holdToken _n5b _n5a +.def 0 +- =holdToken 1 +.mv _n5d 2 myTRUE myFALSE +.names _n5d +myTRUE +# mustGiveParent == 0 +.names mustGiveParent _n5d _n5c +.def 0 +- =mustGiveParent 1 +.mv _n5f 4 idle request lock release +.names _n5f +request +# urLeft == 1 +.names urLeft _n5f _n5e +.def 0 +- =urLeft 1 +.mv _n61 4 idle request lock release +.names _n61 +request +# urRight == 1 +.names urRight _n61 _n60 +.def 0 +- =urRight 1 +# urLeft == 1 || urRight == 1 +.names _n5e _n60 _n62 +.def 1 +0 0 0 +.names _n62 _n63 +0 1 +1 0 +# (mustGiveParent == 0) || !((urLeft == 1 || urRight == 1)) +.names _n5c _n63 _n64 +.def 1 +0 0 0 +.mv _n66 2 myTRUE myFALSE +.names _n66 +myTRUE +# topCell == 0 +.names topCell _n66 _n65 +.def 0 +- =topCell 1 +.names _n65 _n67 +0 1 +1 0 +# ((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0) +.names _n64 _n67 _n68 +.def 0 +1 1 1 +# holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0)) +.names _n5a _n68 _n69 +.def 0 +1 1 1 +.mv _n6a 4 idle request lock release +.names _n6a +release +.mv _n6b 4 idle request lock release +.names _n6b +idle +# (holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0))) ? 3 : 0 +.mv _n6c 4 idle request lock release +.names _n6a _n6b _n69 _n6c +- - 0 =_n6b +- - 1 =_n6a +.mv _n6d 4 idle request lock release +.names _n6d +lock +# (childOwns == 0) ? 2 : (holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0))) ? 3 : 0 +.mv _n6e 4 idle request lock release +.names _n6d _n6c _n58 _n6e +- - 0 =_n6c +- - 1 =_n6d +.mv _n6f 4 idle request lock release +.names _n6f +request +# (holdToken == 1 && (urLeft == 1 || urRight == 1)) ? 1 : (childOwns == 0) ? 2 : (holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0))) ? 3 : 0 +.mv _n70 4 idle request lock release +.names _n6f _n6e _n57 _n70 +- - 0 =_n6e +- - 1 =_n6f +.names _n70 xr$raw_n4f +- =_n70 +.mv _n72 2 myTRUE myFALSE +.names _n72 +myTRUE +# xa == 0 +.names xa _n72 _n71 +.def 0 +- =xa 1 +.names _n71 _n73 +- =_n71 +# holdToken = 0 +.mv holdToken$_n71_n74$true 2 myTRUE myFALSE +.names holdToken$_n71_n74$true +myTRUE +.mv _n76 2 myTRUE myFALSE +.names _n76 +myTRUE +# giveChild == 0 +.names giveChild _n76 _n75 +.def 0 +- =giveChild 1 +.names _n75 _n77 +- =_n75 +# holdToken = 1 +.mv holdToken$_n75_n78$true 2 myTRUE myFALSE +.names holdToken$_n75_n78$true +myFALSE +.mv _n7a 4 idle request lock release +.names _n7a +release +# urLeft == 3 +.names urLeft _n7a _n79 +.def 0 +- =urLeft 1 +.mv _n7c 4 idle request lock release +.names _n7c +release +# urRight == 3 +.names urRight _n7c _n7b +.def 0 +- =urRight 1 +# urLeft == 3 || urRight == 3 +.names _n79 _n7b _n7d +.def 1 +0 0 0 +.names _n7d _n7e +- =_n7d +# holdToken = 0 +.mv holdToken$_n7d_n7f$true 2 myTRUE myFALSE +.names holdToken$_n7d_n7f$true +myTRUE +.mv _n81 4 idle request lock release +.names _n81 +release +# xr == 3 +.names xr _n81 _n80 +.def 0 +- =xr 1 +.names _n80 _n82 +- =_n80 +# holdToken = 1 +.mv holdToken$_n80_n83$true 2 myTRUE myFALSE +.names holdToken$_n80_n83$true +myFALSE +# if/else (xr == 3) +.mv holdToken$_n80$raw_n86 2 myTRUE myFALSE +.names holdToken$_n80_n83$true holdToken _n80 holdToken$_n80$raw_n86 +- - 0 =holdToken +- - 1 =holdToken$_n80_n83$true +# if/else (urLeft == 3 || urRight == 3) +.mv holdToken$_n7d$raw_n88 2 myTRUE myFALSE +.names holdToken$_n7d_n7f$true holdToken$_n80$raw_n86 _n7d holdToken$_n7d$raw_n88 +- - 0 =holdToken$_n80$raw_n86 +- - 1 =holdToken$_n7d_n7f$true +# if/else (giveChild == 0) +.mv holdToken$_n75$raw_n8c 2 myTRUE myFALSE +.names holdToken$_n75_n78$true holdToken$_n7d$raw_n88 _n75 holdToken$_n75$raw_n8c +- - 0 =holdToken$_n7d$raw_n88 +- - 1 =holdToken$_n75_n78$true +# if/else (xa == 0) +.mv holdToken$_n71$raw_n90 2 myTRUE myFALSE +.names holdToken$_n71_n74$true holdToken$_n75$raw_n8c _n71 holdToken$_n71$raw_n90 +- - 0 =holdToken$_n75$raw_n8c +- - 1 =holdToken$_n71_n74$true +.mv _n94 2 myTRUE myFALSE +.names _n94 +myTRUE +# uaLeft == 0 +.names uaLeft _n94 _n93 +.def 0 +- =uaLeft 1 +.names _n93 _n95 +- =_n93 +# prevLeft = 0 +.mv prevLeft$_n93_n96$true 2 myTRUE myFALSE +.names prevLeft$_n93_n96$true +myTRUE +# prevRight = 1 +.mv prevRight$_n93_n97$true 2 myTRUE myFALSE +.names prevRight$_n93_n97$true +myFALSE +.mv _n99 2 myTRUE myFALSE +.names _n99 +myTRUE +# uaRight == 0 +.names uaRight _n99 _n98 +.def 0 +- =uaRight 1 +.names _n98 _n9a +- =_n98 +# prevLeft = 1 +.mv prevLeft$_n98_n9b$true 2 myTRUE myFALSE +.names prevLeft$_n98_n9b$true +myFALSE +# prevRight = 0 +.mv prevRight$_n98_n9c$true 2 myTRUE myFALSE +.names prevRight$_n98_n9c$true +myTRUE +# if/else (uaRight == 0) +.mv prevLeft$_n98$raw_na3 2 myTRUE myFALSE +.names prevLeft$_n98_n9b$true prevLeft _n98 prevLeft$_n98$raw_na3 +- - 0 =prevLeft +- - 1 =prevLeft$_n98_n9b$true +.mv prevRight$_n98$raw_na5 2 myTRUE myFALSE +.names prevRight$_n98_n9c$true prevRight _n98 prevRight$_n98$raw_na5 +- - 0 =prevRight +- - 1 =prevRight$_n98_n9c$true +# if/else (uaLeft == 0) +.mv prevLeft$_n93$raw_naa 2 myTRUE myFALSE +.names prevLeft$_n93_n96$true prevLeft$_n98$raw_na3 _n93 prevLeft$_n93$raw_naa +- - 0 =prevLeft$_n98$raw_na3 +- - 1 =prevLeft$_n93_n96$true +.mv prevRight$_n93$raw_nac 2 myTRUE myFALSE +.names prevRight$_n93_n97$true prevRight$_n98$raw_na5 _n93 prevRight$_n93$raw_nac +- - 0 =prevRight$_n98$raw_na5 +- - 1 =prevRight$_n93_n97$true +.mv _nb4 4 idle request lock release +.names _nb4 +release +# urLeft == 3 +.names urLeft _nb4 _nb3 +.def 0 +- =urLeft 1 +.names _nb3 _nb5 +- =_nb3 +# processedLeft = 0 +.mv processedLeft$_nb3_nb6$true 2 myTRUE myFALSE +.names processedLeft$_nb3_nb6$true +myTRUE +.mv _nb8 4 idle request lock release +.names _nb8 +release +# urRight == 3 +.names urRight _nb8 _nb7 +.def 0 +- =urRight 1 +.names _nb7 _nb9 +- =_nb7 +# processedRight = 0 +.mv processedRight$_nb7_nba$true 2 myTRUE myFALSE +.names processedRight$_nb7_nba$true +myTRUE +.mv _nbc 2 myTRUE myFALSE +.names _nbc +myTRUE +# processedLeft == 0 +.names processedLeft _nbc _nbb +.def 0 +- =processedLeft 1 +.mv _nbe 2 myTRUE myFALSE +.names _nbe +myTRUE +# processedRight == 0 +.names processedRight _nbe _nbd +.def 0 +- =processedRight 1 +# (processedLeft == 0) && (processedRight == 0) +.names _nbb _nbd _nbf +.def 0 +1 1 1 +.names _nbf _nc0 +- =_nbf +# processedLeft = 1 +.mv processedLeft$_nbf_nc1$true 2 myTRUE myFALSE +.names processedLeft$_nbf_nc1$true +myFALSE +# processedRight = 1 +.mv processedRight$_nbf_nc2$true 2 myTRUE myFALSE +.names processedRight$_nbf_nc2$true +myFALSE +# if/else ((processedLeft == 0) && (processedRight == 0)) +.mv processedLeft$_nbf$raw_ncd 2 myTRUE myFALSE +.names processedLeft$_nbf_nc1$true processedLeft _nbf processedLeft$_nbf$raw_ncd +- - 0 =processedLeft +- - 1 =processedLeft$_nbf_nc1$true +.mv processedRight$_nbf$raw_ncf 2 myTRUE myFALSE +.names processedRight$_nbf_nc2$true processedRight _nbf processedRight$_nbf$raw_ncf +- - 0 =processedRight +- - 1 =processedRight$_nbf_nc2$true +# if/else (urRight == 3) +.mv processedRight$_nb7$raw_nda 2 myTRUE myFALSE +.names processedRight$_nb7_nba$true processedRight$_nbf$raw_ncf _nb7 processedRight$_nb7$raw_nda +- - 0 =processedRight$_nbf$raw_ncf +- - 1 =processedRight$_nb7_nba$true +.mv processedLeft$_nb7$raw_ne1 2 myTRUE myFALSE +.names processedLeft processedLeft$_nbf$raw_ncd _nb7 processedLeft$_nb7$raw_ne1 +- - 0 =processedLeft$_nbf$raw_ncd +- - 1 =processedLeft +# if/else (urLeft == 3) +.mv processedLeft$_nb3$raw_nea 2 myTRUE myFALSE +.names processedLeft$_nb3_nb6$true processedLeft$_nb7$raw_ne1 _nb3 processedLeft$_nb3$raw_nea +- - 0 =processedLeft$_nb7$raw_ne1 +- - 1 =processedLeft$_nb3_nb6$true +.mv processedRight$_nb3$raw_nf4 2 myTRUE myFALSE +.names processedRight processedRight$_nb7$raw_nda _nb3 processedRight$_nb3$raw_nf4 +- - 0 =processedRight$_nb7$raw_nda +- - 1 =processedRight +# conflict arbitrators +.names _nb5 _nb9 _nc0 _nf7 +.def 0 + 1 - - 1 + 0 0 1 1 +.mv _nf8 2 myTRUE myFALSE +.names _nf7 processedLeft$_nb3$raw_nea processedLeft _nf8 +1 - - =processedLeft$_nb3$raw_nea +0 - - =processedLeft +.names _n95 _n9a _n105 +.def 0 + 1 - 1 + 0 1 1 +.mv _n106 2 myTRUE myFALSE +.names _n105 prevLeft$_n93$raw_naa prevLeft _n106 +1 - - =prevLeft$_n93$raw_naa +0 - - =prevLeft +.names _n73 _n77 _n7e _n82 _n113 +.def 0 + 1 - - - 1 + 0 1 - - 1 + 0 0 1 - 1 + 0 0 0 1 1 +.mv _n114 2 myTRUE myFALSE +.names _n113 holdToken$_n71$raw_n90 holdToken _n114 +1 - - =holdToken$_n71$raw_n90 +0 - - =holdToken +.names _nb5 _nb9 _nc0 _n121 +.def 0 + 0 1 - 1 + 0 0 1 1 +.mv _n122 2 myTRUE myFALSE +.names _n121 processedRight$_nb3$raw_nf4 processedRight _n122 +1 - - =processedRight$_nb3$raw_nf4 +0 - - =processedRight +.names uaLeft$raw_n27 uaLeft +- =uaLeft$raw_n27 +.names giveChild$raw_n1e giveChild +- =giveChild$raw_n1e +.names mustGiveParent$raw_n7 mustGiveParent +- =mustGiveParent$raw_n7 +.names xr$raw_n4f xr +- =xr$raw_n4f +.names uaRight$raw_n3b uaRight +- =uaRight$raw_n3b +.names childOwns$raw_n15 childOwns +- =childOwns$raw_n15 +.names _n95 _n9a _n12f +.def 0 + 1 - 1 + 0 1 1 +.mv _n130 2 myTRUE myFALSE +.names _n12f prevRight$_n93$raw_nac prevRight _n130 +1 - - =prevRight$_n93$raw_nac +0 - - =prevRight +# non-blocking assignments +# latches +.r prevLeft$raw_n3 prevLeft +- =prevLeft$raw_n3 +.latch _n106 prevLeft +.r processedLeft$raw_n5 processedLeft +- =processedLeft$raw_n5 +.latch _nf8 processedLeft +.r processedRight$raw_n6 processedRight +- =processedRight$raw_n6 +.latch _n122 processedRight +.r holdToken$raw_n14 holdToken +- =holdToken$raw_n14 +.latch _n114 holdToken +.r prevRight$raw_n4 prevRight +- =prevRight$raw_n4 +.latch _n130 prevRight +# quasi-continuous assignment +.end + + +.model procModel +# I/O ports +.outputs req +.inputs ack + +.mv req 4 idle request lock release +.mv procState 4 idle request lock release +.mv ack 2 myTRUE myFALSE +# assign req = procState +.mv req$raw_n13d 4 idle request lock release +.names procState req$raw_n13d +- =procState +# procState = 0 +.mv procState$raw_n13e 4 idle request lock release +.names procState$raw_n13e +idle +# non-blocking assignments for initial +# assign randChoice = $NDset ( 0,1,2,3,4,5,6,7 ) +.names -> randChoice<0> randChoice<1> randChoice<2> +0 0 0 +1 0 0 +0 1 0 +1 1 0 +0 0 1 +1 0 1 +0 1 1 +1 1 1 +.mv _n142 4 idle request lock release +.names _n142 +idle +# procState == 0 +.names procState _n142 _n141 +.def 0 +- =procState 1 +.names _n144<0> +1 +.names _n144<1> +1 +.names _n144<2> +1 +# randChoice == 7 +.names randChoice<0> _n144<0> _n145<0> +.def 0 +0 1 1 +1 0 1 +.names randChoice<1> _n144<1> _n145<1> +.def 0 +0 1 1 +1 0 1 +.names randChoice<2> _n144<2> _n145<2> +.def 0 +0 1 1 +1 0 1 +.names _n145<0> _n145<1> _n145<2> _n146 +.def 1 +0 0 0 0 +.names _n146 _n143 +0 1 +1 0 +# procState == 0 && (randChoice == 7) +.names _n141 _n143 _n147 +.def 0 +1 1 1 +.names _n147 _n148 +- =_n147 +# procState = 1 +.mv procState$_n147_n149$true 4 idle request lock release +.names procState$_n147_n149$true +request +.mv _n14b 4 idle request lock release +.names _n14b +request +# procState == 1 +.names procState _n14b _n14a +.def 0 +- =procState 1 +.mv _n14d 2 myTRUE myFALSE +.names _n14d +myTRUE +# ack == 0 +.names ack _n14d _n14c +.def 0 +- =ack 1 +# procState == 1 && ack == 0 +.names _n14a _n14c _n14e +.def 0 +1 1 1 +.names _n14e _n14f +- =_n14e +# procState = 2 +.mv procState$_n14e_n150$true 4 idle request lock release +.names procState$_n14e_n150$true +lock +.mv _n152 4 idle request lock release +.names _n152 +lock +# procState == 2 +.names procState _n152 _n151 +.def 0 +- =procState 1 +.names _n153<0> +1 +.names _n153<1> +1 +.names _n153<2> +0 +# randChoice > 3 +.names _n156 +0 +.names randChoice<0> _n153<0> _n156 _n155<0> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names _n158 +0 +.names randChoice<0> _n153<0> _n158 _n157 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names randChoice<1> _n153<1> _n157 _n155<1> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names randChoice<1> _n153<1> _n157 _n159 +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names randChoice<2> _n153<2> _n159 _n155<2> +.def 0 +0 0 1 1 +0 1 0 1 +1 0 0 1 +1 1 1 1 +# carry/borrow +.names randChoice<2> _n153<2> _n159 _n15a +.def 0 +0 0 1 1 +0 1 0 1 +0 1 1 1 +1 1 1 1 +.names _n155<0> _n155<1> _n155<2> _n15b +.def 0 +0 0 0 1 +.names _n15a _n15b _n15c +.def 1 +0 0 0 +.names _n15c _n154 +0 1 +1 0 +# procState == 2 && (randChoice > 3) +.names _n151 _n154 _n15d +.def 0 +1 1 1 +.names _n15d _n15e +- =_n15d +# procState = 3 +.mv procState$_n15d_n15f$true 4 idle request lock release +.names procState$_n15d_n15f$true +release +.mv _n161 4 idle request lock release +.names _n161 +release +# procState == 3 +.names procState _n161 _n160 +.def 0 +- =procState 1 +.names _n160 _n162 +- =_n160 +# procState = 0 +.mv procState$_n160_n163$true 4 idle request lock release +.names procState$_n160_n163$true +idle +# if/else (procState == 3) +.mv procState$_n160$raw_n166 4 idle request lock release +.names procState$_n160_n163$true procState _n160 procState$_n160$raw_n166 +- - 0 =procState +- - 1 =procState$_n160_n163$true +# if/else (procState == 2 && (randChoice > 3)) +.mv procState$_n15d$raw_n168 4 idle request lock release +.names procState$_n15d_n15f$true procState$_n160$raw_n166 _n15d procState$_n15d$raw_n168 +- - 0 =procState$_n160$raw_n166 +- - 1 =procState$_n15d_n15f$true +# if/else (procState == 1 && ack == 0) +.mv procState$_n14e$raw_n16c 4 idle request lock release +.names procState$_n14e_n150$true procState$_n15d$raw_n168 _n14e procState$_n14e$raw_n16c +- - 0 =procState$_n15d$raw_n168 +- - 1 =procState$_n14e_n150$true +# if/else (procState == 0 && (randChoice == 7)) +.mv procState$_n147$raw_n170 4 idle request lock release +.names procState$_n147_n149$true procState$_n14e$raw_n16c _n147 procState$_n147$raw_n170 +- - 0 =procState$_n14e$raw_n16c +- - 1 =procState$_n147_n149$true +# conflict arbitrators +.names req$raw_n13d req +- =req$raw_n13d +.names _n148 _n14f _n15e _n162 _n173 +.def 0 + 1 - - - 1 + 0 1 - - 1 + 0 0 1 - 1 + 0 0 0 1 1 +.mv _n174 4 idle request lock release +.names _n173 procState$_n147$raw_n170 procState _n174 +1 - - =procState$_n147$raw_n170 +0 - - =procState +# non-blocking assignments +# latches +.r procState$raw_n13e procState +- =procState$raw_n13e +.latch _n174 procState +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/treearbiter/4-arbit.v =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/4-arbit.v (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/4-arbit.v (revision 11) @@ -0,0 +1,237 @@ +/************************************************************************** + + This is a simple tree arbiter, adapted from Dills' thesis p 89. + There are four processors which + share a single resource. A token defines which processor has the + resource. The arbiter cells have two children and one parent. + An arbiter can request the token, release it, etc. + + Adnan Aziz + July 10, 1996 + UT Austin + +***************************************************************************/ + +/* + * Symbolic variables. + * + */ +typedef enum {myTRUE, myFALSE} boolean; +typedef enum {idle, request, lock, release} handShakeType; + +/* + * The inteconnections between the processors and the cells. + * + */ +module main( clk ); +input clk; + + +boolean wire ua1, ua2, ua3, ua4, xa, ya, sa; +handShakeType wire ur1, ur2, ur3, ur4, xr, yr, sr; + + +boolean wire constTRUE, constFALSE; + +assign constTRUE = myTRUE; +assign constFALSE = myFALSE; + +assign sa = constFALSE; + +arbitCell C0 ( clk, constTRUE, xr, yr, xa, ya, sr, sa ); +arbitCell C1 ( clk, constFALSE, ur1, ur2, ua1, ua2, xr, xa ); +arbitCell C2 ( clk, constFALSE, ur3, ur4, ua3, ua4, yr, ya ); + +procModel P1( clk, ua1, ur1 ); +procModel P2( clk, ua2, ur2 ); +procModel P3( clk, ua3, ur3 ); +procModel P4( clk, ua4, ur4 ); + +endmodule + + +/* + * The arbiter cell has two inputs from children and two outputs to chidren. + * One input from parent, and one output to parent. The latch holdToken corresponds + * to whether the cell holds the token. The latches prevLeft and prevRight are + * used to keep track of which way the token went last, to impart fairness + * in the scheduling of the children. + * + */ + +module arbitCell(clk, topCell, urLeft, urRight, uaLeft, uaRight, xr, xa); +input clk; +input topCell, urLeft, urRight, xa; +output uaLeft, uaRight, xr; + +boolean wire topCell, uaLeft, uaRight, xa; +handShakeType wire urLeft, urRight, xr; + +boolean wire uaLeft, uaRight; + +boolean reg prevLeft, prevRight; +initial prevLeft = myFALSE; +initial prevRight = myTRUE; + +boolean reg processedLeft, processedRight; +initial processedLeft = myFALSE; +initial processedRight = myFALSE; + +boolean wire mustGiveParent; /* essentially a macro for checking if must release the token to parent */ +assign mustGiveParent = ( processedLeft == myTRUE ) && ( processedRight == myTRUE ) + && ( !( topCell == myTRUE ) ) ? myTRUE : myFALSE; + +boolean reg holdToken; +initial holdToken = topCell; + +boolean wire childOwns; /* essentially a macro for checking if a descendant owns the token */ +assign childOwns = ( urLeft == lock || urRight == lock ) ? myTRUE : myFALSE; + +boolean wire giveChild; /* essentially a macro for checking if a child is being given the token */ +assign giveChild = ( uaLeft == myTRUE || uaRight == myTRUE ) ? myTRUE : myFALSE; + +/* + * Condition under which the token is given to the left child + * Must own token, have request from left, and either no request from right or if there is + * a request from the right it, should be lefts turn (since right went the last time + * + */ +assign uaLeft = ( !( mustGiveParent == myTRUE ) && ( holdToken == myTRUE && urLeft == request + && ( ! ( urRight == request ) || prevRight == myTRUE ) ) ) ? myTRUE : myFALSE; + +/* + * same as above for right + * + */ +assign uaRight = ( !( mustGiveParent == myTRUE ) && ( holdToken == myTRUE && urRight == request + && ( ! ( urLeft == request ) || prevLeft == myTRUE ) ) ) ? myTRUE : myFALSE; + +/* + * signal to parent: + * + * 1. request if dont own the token, + * 2. lock if descendant has locked the token + * 3. release if child has released token + * 4. idle otherwise + * + */ +assign xr = ( holdToken == myFALSE && ( urLeft == request || urRight == request ) ) + ? request : + ( childOwns == myTRUE ) + ? lock : + ( holdToken == myTRUE && ( ( ( mustGiveParent == myTRUE ) || + ! ( ( urLeft == request || urRight == request ) ) ) + && !( topCell == myTRUE ) ) ) + ? release : idle; + +always @(posedge clk) begin + +/* + * keep track of whether we hold the token or not + * + */ + + if ( xa == myTRUE ) + begin + holdToken = myTRUE; + end + else if ( giveChild == myTRUE ) + begin + holdToken = myFALSE; + end + else if ( urLeft == release || urRight == release ) + begin + holdToken = myTRUE; + end + else if ( xr == release ) + begin + holdToken = myFALSE; + end + +/* + * keep track of which child got the token last + * + */ + if ( uaLeft == myTRUE ) + begin + prevLeft = myTRUE; + prevRight = myFALSE; + end + else if ( uaRight == myTRUE ) + begin + prevLeft = myFALSE; + prevRight = myTRUE; + end + +/* + * child has finished processing the token + * + */ + + if ( urLeft == release ) + begin + processedLeft = myTRUE; + end + else if ( urRight == release ) + begin + processedRight = myTRUE; + end +/* + * if we have given the token to both children, must now give it up + * + */ + else if ( ( processedLeft == myTRUE ) && ( processedRight == myTRUE ) ) + begin + processedLeft = myFALSE; + processedRight = myFALSE; + end + +end + +endmodule + + +/* + * Simple model for a processor - can be in four states, + * idle, req, lock, release. Non-det variable randChoice + * governs generation of requests, and how long hold on + * to token. + */ +module procModel(clk, ack, req ); +input clk; +input ack; +output req; + +boolean wire ack; +handShakeType wire req; + +assign req = procState; + +wire[0:2] randChoice; +handShakeType reg procState; + +initial procState = idle; + +assign randChoice = $ND(0,1,2,3,4,5,6,7); + +always @(posedge clk) begin + + if ( procState == idle && (randChoice == 7) ) + begin + procState = request; + end + else if ( procState == request && ack == myTRUE ) + begin + procState = lock; + end + else if ( procState == lock && (randChoice > 3) ) + begin + procState = release; + end + else if ( procState == release ) + begin + procState = idle; + end +end + +endmodule Index: vis_dev/vis-2.1/examples/treearbiter/8-arbit.ctl =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/8-arbit.ctl (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/8-arbit.ctl (revision 11) @@ -0,0 +1,9 @@ +# never have both cells holding the token at the same time +AG ( ! ( ( G1.C1.holdToken = myTRUE ) * ( G1.C2.holdToken = myTRUE) ) ); + +# never have G1.P3 and G1.P2 holding the token; +# actually need a formula for each pair of procs... +AG ( ! ( ( G1.P3.procState = lock ) * ( G1.P2.procState = lock) ) ); + +# ensures liveness - needs fairness on the procs to pass +AG ( ( G1.P3.procState = request ) -> AF ( G1.P3.procState = lock) ); Index: vis_dev/vis-2.1/examples/treearbiter/8-arbit.fair =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/8-arbit.fair (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/8-arbit.fair (revision 11) @@ -0,0 +1,17 @@ +# G1.P1 doesnt lock the token forever +!(G1.P1.procState=lock); + +!(G1.P2.procState=lock); + +!(G1.P3.procState=lock); + +!(G1.P4.procState=lock); + +!(G2.P1.procState=lock); + +!(G2.P2.procState=lock); + +!(G2.P3.procState=lock); + +!(G2.P4.procState=lock); + Index: vis_dev/vis-2.1/examples/treearbiter/8-arbit.ltl =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/8-arbit.ltl (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/8-arbit.ltl (revision 11) @@ -0,0 +1,9 @@ +# never have both cells holding the token at the same time +G !(G1.C1.holdToken = myTRUE * G1.C2.holdToken = myTRUE); + +# never have G1.P3 and G1.P2 holding the token; +# actually need a formula for each pair of procs... +G !(G1.P3.procState = lock * G1.P2.procState = lock); + +# ensures liveness - needs fairness on the procs to pass +G (G1.P3.procState = request -> F(G1.P3.procState = lock)); Index: vis_dev/vis-2.1/examples/treearbiter/8-arbit.mv =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/8-arbit.mv (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/8-arbit.mv (revision 11) @@ -0,0 +1,955 @@ +# /projects/vl2mv/vl2mvt/mips/bin/vl2mv 8-arbit.v +# version: 0.2 +# date: 09:05:18 03/01/97 (PST) +.model main +# I/O ports +.mv sa 2 myTRUE myFALSE +.mv xa 2 myTRUE myFALSE +.mv yr 4 idle request lock release +.mv sr 4 idle request lock release +.mv xr 4 idle request lock release +.mv ya 2 myTRUE myFALSE +.mv constTRUE 2 myTRUE myFALSE +# assign sa = 1 +.mv sa$raw_n0 2 myTRUE myFALSE +.names sa$raw_n0 +myFALSE +# assign constTRUE = 0 +.mv constTRUE$raw_n1 2 myTRUE myFALSE +.names constTRUE$raw_n1 +myTRUE +.subckt arbitCell F0 topCell=constTRUE urLeft=xr urRight=yr uaLeft=xa uaRight=ya xr=sr xa=sa +.subckt fourCells G1 sa=xa sr=xr +.subckt fourCells G2 sa=ya sr=yr +# conflict arbitrators +.names sa$raw_n0 sa +- =sa$raw_n0 +.names constTRUE$raw_n1 constTRUE +- =constTRUE$raw_n1 +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model arbitCell +# I/O ports +.outputs uaLeft +.inputs topCell +.inputs xa +.inputs urRight +.inputs urLeft +.outputs xr +.outputs uaRight +.mv processedLeft 2 myTRUE myFALSE +.mv prevLeft 2 myTRUE myFALSE +.mv holdToken 2 myTRUE myFALSE +.mv processedRight 2 myTRUE myFALSE +.mv uaLeft 2 myTRUE myFALSE +.mv topCell 2 myTRUE myFALSE +.mv xa 2 myTRUE myFALSE +.mv urRight 4 idle request lock release +.mv giveChild 2 myTRUE myFALSE +.mv urLeft 4 idle request lock release +.mv mustGiveParent 2 myTRUE myFALSE +.mv xr 4 idle request lock release +.mv uaRight 2 myTRUE myFALSE +.mv childOwns 2 myTRUE myFALSE +.mv prevRight 2 myTRUE myFALSE +# prevLeft = 1 +.mv prevLeft$raw_n2 2 myTRUE myFALSE +.names prevLeft$raw_n2 +myFALSE +# non-blocking assignments for initial +# prevRight = 0 +.mv prevRight$raw_n3 2 myTRUE myFALSE +.names prevRight$raw_n3 +myTRUE +# non-blocking assignments for initial +# processedLeft = 1 +.mv processedLeft$raw_n4 2 myTRUE myFALSE +.names processedLeft$raw_n4 +myFALSE +# non-blocking assignments for initial +# processedRight = 1 +.mv processedRight$raw_n5 2 myTRUE myFALSE +.names processedRight$raw_n5 +myFALSE +# non-blocking assignments for initial +# assign mustGiveParent = (processedLeft == 0) && (processedRight == 0) && (!(topCell == 0)) ? 0 : 1 +.mv mustGiveParent$raw_n6 2 myTRUE myFALSE +.mv _n8 2 myTRUE myFALSE +.names _n8 +myTRUE +# processedLeft == 0 +.names processedLeft _n8 _n7 +.def 0 +- =processedLeft 1 +.mv _na 2 myTRUE myFALSE +.names _na +myTRUE +# processedRight == 0 +.names processedRight _na _n9 +.def 0 +- =processedRight 1 +# (processedLeft == 0) && (processedRight == 0) +.names _n7 _n9 _nb +.def 0 +1 1 1 +.mv _nd 2 myTRUE myFALSE +.names _nd +myTRUE +# topCell == 0 +.names topCell _nd _nc +.def 0 +- =topCell 1 +.names _nc _ne +0 1 +1 0 +# (processedLeft == 0) && (processedRight == 0) && (!(topCell == 0)) +.names _nb _ne _nf +.def 0 +1 1 1 +.mv _n10 2 myTRUE myFALSE +.names _n10 +myTRUE +.mv _n11 2 myTRUE myFALSE +.names _n11 +myFALSE +# (processedLeft == 0) && (processedRight == 0) && (!(topCell == 0)) ? 0 : 1 +.mv _n12 2 myTRUE myFALSE +.names _n10 _n11 _nf _n12 +- - 0 =_n11 +- - 1 =_n10 +.names _n12 mustGiveParent$raw_n6 +- =_n12 +# holdToken = topCell +.mv holdToken$raw_n13 2 myTRUE myFALSE +.names topCell holdToken$raw_n13 +- =topCell +# non-blocking assignments for initial +# assign childOwns = (urLeft == lock || urRight == lock ) ? 0 : 1 +.mv childOwns$raw_n14 2 myTRUE myFALSE +.mv _n16 4 idle request lock release +.names _n16 +lock +# urLeft == 2 +.names urLeft _n16 _n15 +.def 0 +- =urLeft 1 +.mv _n18 4 idle request lock release +.names _n18 +lock +# urRight == 2 +.names urRight _n18 _n17 +.def 0 +- =urRight 1 +# urLeft == 2 || urRight == 2 +.names _n15 _n17 _n19 +.def 1 +0 0 0 +.mv _n1a 2 myTRUE myFALSE +.names _n1a +myTRUE +.mv _n1b 2 myTRUE myFALSE +.names _n1b +myFALSE +# (urLeft == 2 || urRight == 2) ? 0 : 1 +.mv _n1c 2 myTRUE myFALSE +.names _n1a _n1b _n19 _n1c +- - 0 =_n1b +- - 1 =_n1a +.names _n1c childOwns$raw_n14 +- =_n1c +# assign giveChild = (uaLeft == 0 || uaRight == 0) ? 0 : 1 +.mv giveChild$raw_n1d 2 myTRUE myFALSE +.mv _n1f 2 myTRUE myFALSE +.names _n1f +myTRUE +# uaLeft == 0 +.names uaLeft _n1f _n1e +.def 0 +- =uaLeft 1 +.mv _n21 2 myTRUE myFALSE +.names _n21 +myTRUE +# uaRight == 0 +.names uaRight _n21 _n20 +.def 0 +- =uaRight 1 +# uaLeft == 0 || uaRight == 0 +.names _n1e _n20 _n22 +.def 1 +0 0 0 +.mv _n23 2 myTRUE myFALSE +.names _n23 +myTRUE +.mv _n24 2 myTRUE myFALSE +.names _n24 +myFALSE +# (uaLeft == 0 || uaRight == 0) ? 0 : 1 +.mv _n25 2 myTRUE myFALSE +.names _n23 _n24 _n22 _n25 +- - 0 =_n24 +- - 1 =_n23 +.names _n25 giveChild$raw_n1d +- =_n25 +# assign uaLeft = (!(mustGiveParent == 0) && (holdToken == 0 && urLeft == request && (!(urRight == request ) || prevRight == 0))) ? 0 : 1 +.mv uaLeft$raw_n26 2 myTRUE myFALSE +.mv _n28 2 myTRUE myFALSE +.names _n28 +myTRUE +# mustGiveParent == 0 +.names mustGiveParent _n28 _n27 +.def 0 +- =mustGiveParent 1 +.names _n27 _n29 +0 1 +1 0 +.mv _n2b 2 myTRUE myFALSE +.names _n2b +myTRUE +# holdToken == 0 +.names holdToken _n2b _n2a +.def 0 +- =holdToken 1 +.mv _n2d 4 idle request lock release +.names _n2d +request +# urLeft == 1 +.names urLeft _n2d _n2c +.def 0 +- =urLeft 1 +# holdToken == 0 && urLeft == 1 +.names _n2a _n2c _n2e +.def 0 +1 1 1 +.mv _n30 4 idle request lock release +.names _n30 +request +# urRight == 1 +.names urRight _n30 _n2f +.def 0 +- =urRight 1 +.names _n2f _n31 +0 1 +1 0 +.mv _n33 2 myTRUE myFALSE +.names _n33 +myTRUE +# prevRight == 0 +.names prevRight _n33 _n32 +.def 0 +- =prevRight 1 +# !(urRight == 1) || prevRight == 0 +.names _n31 _n32 _n34 +.def 1 +0 0 0 +# holdToken == 0 && urLeft == 1 && (!(urRight == 1) || prevRight == 0) +.names _n2e _n34 _n35 +.def 0 +1 1 1 +# !(mustGiveParent == 0) && (holdToken == 0 && urLeft == 1 && (!(urRight == 1) || prevRight == 0)) +.names _n29 _n35 _n36 +.def 0 +1 1 1 +.mv _n37 2 myTRUE myFALSE +.names _n37 +myTRUE +.mv _n38 2 myTRUE myFALSE +.names _n38 +myFALSE +# (!(mustGiveParent == 0) && (holdToken == 0 && urLeft == 1 && (!(urRight == 1) || prevRight == 0))) ? 0 : 1 +.mv _n39 2 myTRUE myFALSE +.names _n37 _n38 _n36 _n39 +- - 0 =_n38 +- - 1 =_n37 +.names _n39 uaLeft$raw_n26 +- =_n39 +# assign uaRight = (!(mustGiveParent == 0) && (holdToken == 0 && urRight == request && (!(urLeft == request ) || prevLeft == 0))) ? 0 : 1 +.mv uaRight$raw_n3a 2 myTRUE myFALSE +.mv _n3c 2 myTRUE myFALSE +.names _n3c +myTRUE +# mustGiveParent == 0 +.names mustGiveParent _n3c _n3b +.def 0 +- =mustGiveParent 1 +.names _n3b _n3d +0 1 +1 0 +.mv _n3f 2 myTRUE myFALSE +.names _n3f +myTRUE +# holdToken == 0 +.names holdToken _n3f _n3e +.def 0 +- =holdToken 1 +.mv _n41 4 idle request lock release +.names _n41 +request +# urRight == 1 +.names urRight _n41 _n40 +.def 0 +- =urRight 1 +# holdToken == 0 && urRight == 1 +.names _n3e _n40 _n42 +.def 0 +1 1 1 +.mv _n44 4 idle request lock release +.names _n44 +request +# urLeft == 1 +.names urLeft _n44 _n43 +.def 0 +- =urLeft 1 +.names _n43 _n45 +0 1 +1 0 +.mv _n47 2 myTRUE myFALSE +.names _n47 +myTRUE +# prevLeft == 0 +.names prevLeft _n47 _n46 +.def 0 +- =prevLeft 1 +# !(urLeft == 1) || prevLeft == 0 +.names _n45 _n46 _n48 +.def 1 +0 0 0 +# holdToken == 0 && urRight == 1 && (!(urLeft == 1) || prevLeft == 0) +.names _n42 _n48 _n49 +.def 0 +1 1 1 +# !(mustGiveParent == 0) && (holdToken == 0 && urRight == 1 && (!(urLeft == 1) || prevLeft == 0)) +.names _n3d _n49 _n4a +.def 0 +1 1 1 +.mv _n4b 2 myTRUE myFALSE +.names _n4b +myTRUE +.mv _n4c 2 myTRUE myFALSE +.names _n4c +myFALSE +# (!(mustGiveParent == 0) && (holdToken == 0 && urRight == 1 && (!(urLeft == 1) || prevLeft == 0))) ? 0 : 1 +.mv _n4d 2 myTRUE myFALSE +.names _n4b _n4c _n4a _n4d +- - 0 =_n4c +- - 1 =_n4b +.names _n4d uaRight$raw_n3a +- =_n4d +# assign xr = (holdToken == myFALSE && (urLeft == 1 || urRight == 1)) ? 1 : (childOwns == myTRUE ) ? 2 : (holdToken == myTRUE && (((mustGiveParent == myTRUE ) || !((urLeft == 1 || urRight == 1))) && !(topCell == myTRUE ))) ? 3 : 0 +.mv xr$raw_n4e 4 idle request lock release +.mv _n50 2 myTRUE myFALSE +.names _n50 +myFALSE +# holdToken == 1 +.names holdToken _n50 _n4f +.def 0 +- =holdToken 1 +.mv _n52 4 idle request lock release +.names _n52 +request +# urLeft == 1 +.names urLeft _n52 _n51 +.def 0 +- =urLeft 1 +.mv _n54 4 idle request lock release +.names _n54 +request +# urRight == 1 +.names urRight _n54 _n53 +.def 0 +- =urRight 1 +# urLeft == 1 || urRight == 1 +.names _n51 _n53 _n55 +.def 1 +0 0 0 +# holdToken == 1 && (urLeft == 1 || urRight == 1) +.names _n4f _n55 _n56 +.def 0 +1 1 1 +.mv _n58 2 myTRUE myFALSE +.names _n58 +myTRUE +# childOwns == 0 +.names childOwns _n58 _n57 +.def 0 +- =childOwns 1 +.mv _n5a 2 myTRUE myFALSE +.names _n5a +myTRUE +# holdToken == 0 +.names holdToken _n5a _n59 +.def 0 +- =holdToken 1 +.mv _n5c 2 myTRUE myFALSE +.names _n5c +myTRUE +# mustGiveParent == 0 +.names mustGiveParent _n5c _n5b +.def 0 +- =mustGiveParent 1 +.mv _n5e 4 idle request lock release +.names _n5e +request +# urLeft == 1 +.names urLeft _n5e _n5d +.def 0 +- =urLeft 1 +.mv _n60 4 idle request lock release +.names _n60 +request +# urRight == 1 +.names urRight _n60 _n5f +.def 0 +- =urRight 1 +# urLeft == 1 || urRight == 1 +.names _n5d _n5f _n61 +.def 1 +0 0 0 +.names _n61 _n62 +0 1 +1 0 +# (mustGiveParent == 0) || !((urLeft == 1 || urRight == 1)) +.names _n5b _n62 _n63 +.def 1 +0 0 0 +.mv _n65 2 myTRUE myFALSE +.names _n65 +myTRUE +# topCell == 0 +.names topCell _n65 _n64 +.def 0 +- =topCell 1 +.names _n64 _n66 +0 1 +1 0 +# ((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0) +.names _n63 _n66 _n67 +.def 0 +1 1 1 +# holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0)) +.names _n59 _n67 _n68 +.def 0 +1 1 1 +.mv _n69 4 idle request lock release +.names _n69 +release +.mv _n6a 4 idle request lock release +.names _n6a +idle +# (holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0))) ? 3 : 0 +.mv _n6b 4 idle request lock release +.names _n69 _n6a _n68 _n6b +- - 0 =_n6a +- - 1 =_n69 +.mv _n6c 4 idle request lock release +.names _n6c +lock +# (childOwns == 0) ? 2 : (holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0))) ? 3 : 0 +.mv _n6d 4 idle request lock release +.names _n6c _n6b _n57 _n6d +- - 0 =_n6b +- - 1 =_n6c +.mv _n6e 4 idle request lock release +.names _n6e +request +# (holdToken == 1 && (urLeft == 1 || urRight == 1)) ? 1 : (childOwns == 0) ? 2 : (holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0))) ? 3 : 0 +.mv _n6f 4 idle request lock release +.names _n6e _n6d _n56 _n6f +- - 0 =_n6d +- - 1 =_n6e +.names _n6f xr$raw_n4e +- =_n6f +.mv _n71 2 myTRUE myFALSE +.names _n71 +myTRUE +# xa == 0 +.names xa _n71 _n70 +.def 0 +- =xa 1 +.names _n70 _n72 +- =_n70 +# holdToken = 0 +.mv holdToken$_n70_n73$true 2 myTRUE myFALSE +.names holdToken$_n70_n73$true +myTRUE +.mv _n75 2 myTRUE myFALSE +.names _n75 +myTRUE +# giveChild == 0 +.names giveChild _n75 _n74 +.def 0 +- =giveChild 1 +.names _n74 _n76 +- =_n74 +# holdToken = 1 +.mv holdToken$_n74_n77$true 2 myTRUE myFALSE +.names holdToken$_n74_n77$true +myFALSE +.mv _n79 4 idle request lock release +.names _n79 +release +# urLeft == 3 +.names urLeft _n79 _n78 +.def 0 +- =urLeft 1 +.mv _n7b 4 idle request lock release +.names _n7b +release +# urRight == 3 +.names urRight _n7b _n7a +.def 0 +- =urRight 1 +# urLeft == 3 || urRight == 3 +.names _n78 _n7a _n7c +.def 1 +0 0 0 +.names _n7c _n7d +- =_n7c +# holdToken = 0 +.mv holdToken$_n7c_n7e$true 2 myTRUE myFALSE +.names holdToken$_n7c_n7e$true +myTRUE +.mv _n80 4 idle request lock release +.names _n80 +release +# xr == 3 +.names xr _n80 _n7f +.def 0 +- =xr 1 +.names _n7f _n81 +- =_n7f +# holdToken = 1 +.mv holdToken$_n7f_n82$true 2 myTRUE myFALSE +.names holdToken$_n7f_n82$true +myFALSE +# if/else (xr == 3) +.mv holdToken$_n7f$raw_n85 2 myTRUE myFALSE +.names holdToken$_n7f_n82$true holdToken _n7f holdToken$_n7f$raw_n85 +- - 0 =holdToken +- - 1 =holdToken$_n7f_n82$true +# if/else (urLeft == 3 || urRight == 3) +.mv holdToken$_n7c$raw_n87 2 myTRUE myFALSE +.names holdToken$_n7c_n7e$true holdToken$_n7f$raw_n85 _n7c holdToken$_n7c$raw_n87 +- - 0 =holdToken$_n7f$raw_n85 +- - 1 =holdToken$_n7c_n7e$true +# if/else (giveChild == 0) +.mv holdToken$_n74$raw_n8b 2 myTRUE myFALSE +.names holdToken$_n74_n77$true holdToken$_n7c$raw_n87 _n74 holdToken$_n74$raw_n8b +- - 0 =holdToken$_n7c$raw_n87 +- - 1 =holdToken$_n74_n77$true +# if/else (xa == 0) +.mv holdToken$_n70$raw_n8f 2 myTRUE myFALSE +.names holdToken$_n70_n73$true holdToken$_n74$raw_n8b _n70 holdToken$_n70$raw_n8f +- - 0 =holdToken$_n74$raw_n8b +- - 1 =holdToken$_n70_n73$true +.mv _n93 2 myTRUE myFALSE +.names _n93 +myTRUE +# uaLeft == 0 +.names uaLeft _n93 _n92 +.def 0 +- =uaLeft 1 +.names _n92 _n94 +- =_n92 +# prevLeft = 0 +.mv prevLeft$_n92_n95$true 2 myTRUE myFALSE +.names prevLeft$_n92_n95$true +myTRUE +# prevRight = 1 +.mv prevRight$_n92_n96$true 2 myTRUE myFALSE +.names prevRight$_n92_n96$true +myFALSE +.mv _n98 2 myTRUE myFALSE +.names _n98 +myTRUE +# uaRight == 0 +.names uaRight _n98 _n97 +.def 0 +- =uaRight 1 +.names _n97 _n99 +- =_n97 +# prevLeft = 1 +.mv prevLeft$_n97_n9a$true 2 myTRUE myFALSE +.names prevLeft$_n97_n9a$true +myFALSE +# prevRight = 0 +.mv prevRight$_n97_n9b$true 2 myTRUE myFALSE +.names prevRight$_n97_n9b$true +myTRUE +# if/else (uaRight == 0) +.mv prevLeft$_n97$raw_na2 2 myTRUE myFALSE +.names prevLeft$_n97_n9a$true prevLeft _n97 prevLeft$_n97$raw_na2 +- - 0 =prevLeft +- - 1 =prevLeft$_n97_n9a$true +.mv prevRight$_n97$raw_na4 2 myTRUE myFALSE +.names prevRight$_n97_n9b$true prevRight _n97 prevRight$_n97$raw_na4 +- - 0 =prevRight +- - 1 =prevRight$_n97_n9b$true +# if/else (uaLeft == 0) +.mv prevLeft$_n92$raw_na9 2 myTRUE myFALSE +.names prevLeft$_n92_n95$true prevLeft$_n97$raw_na2 _n92 prevLeft$_n92$raw_na9 +- - 0 =prevLeft$_n97$raw_na2 +- - 1 =prevLeft$_n92_n95$true +.mv prevRight$_n92$raw_nab 2 myTRUE myFALSE +.names prevRight$_n92_n96$true prevRight$_n97$raw_na4 _n92 prevRight$_n92$raw_nab +- - 0 =prevRight$_n97$raw_na4 +- - 1 =prevRight$_n92_n96$true +.mv _nb3 4 idle request lock release +.names _nb3 +release +# urLeft == 3 +.names urLeft _nb3 _nb2 +.def 0 +- =urLeft 1 +.names _nb2 _nb4 +- =_nb2 +# processedLeft = 0 +.mv processedLeft$_nb2_nb5$true 2 myTRUE myFALSE +.names processedLeft$_nb2_nb5$true +myTRUE +.mv _nb7 4 idle request lock release +.names _nb7 +release +# urRight == 3 +.names urRight _nb7 _nb6 +.def 0 +- =urRight 1 +.names _nb6 _nb8 +- =_nb6 +# processedRight = 0 +.mv processedRight$_nb6_nb9$true 2 myTRUE myFALSE +.names processedRight$_nb6_nb9$true +myTRUE +.mv _nbb 2 myTRUE myFALSE +.names _nbb +myTRUE +# processedLeft == 0 +.names processedLeft _nbb _nba +.def 0 +- =processedLeft 1 +.mv _nbd 2 myTRUE myFALSE +.names _nbd +myTRUE +# processedRight == 0 +.names processedRight _nbd _nbc +.def 0 +- =processedRight 1 +# (processedLeft == 0) && (processedRight == 0) +.names _nba _nbc _nbe +.def 0 +1 1 1 +.names _nbe _nbf +- =_nbe +# processedLeft = 1 +.mv processedLeft$_nbe_nc0$true 2 myTRUE myFALSE +.names processedLeft$_nbe_nc0$true +myFALSE +# processedRight = 1 +.mv processedRight$_nbe_nc1$true 2 myTRUE myFALSE +.names processedRight$_nbe_nc1$true +myFALSE +# if/else ((processedLeft == 0) && (processedRight == 0)) +.mv processedLeft$_nbe$raw_ncc 2 myTRUE myFALSE +.names processedLeft$_nbe_nc0$true processedLeft _nbe processedLeft$_nbe$raw_ncc +- - 0 =processedLeft +- - 1 =processedLeft$_nbe_nc0$true +.mv processedRight$_nbe$raw_nce 2 myTRUE myFALSE +.names processedRight$_nbe_nc1$true processedRight _nbe processedRight$_nbe$raw_nce +- - 0 =processedRight +- - 1 =processedRight$_nbe_nc1$true +# if/else (urRight == 3) +.mv processedRight$_nb6$raw_nd9 2 myTRUE myFALSE +.names processedRight$_nb6_nb9$true processedRight$_nbe$raw_nce _nb6 processedRight$_nb6$raw_nd9 +- - 0 =processedRight$_nbe$raw_nce +- - 1 =processedRight$_nb6_nb9$true +.mv processedLeft$_nb6$raw_ne0 2 myTRUE myFALSE +.names processedLeft processedLeft$_nbe$raw_ncc _nb6 processedLeft$_nb6$raw_ne0 +- - 0 =processedLeft$_nbe$raw_ncc +- - 1 =processedLeft +# if/else (urLeft == 3) +.mv processedLeft$_nb2$raw_ne9 2 myTRUE myFALSE +.names processedLeft$_nb2_nb5$true processedLeft$_nb6$raw_ne0 _nb2 processedLeft$_nb2$raw_ne9 +- - 0 =processedLeft$_nb6$raw_ne0 +- - 1 =processedLeft$_nb2_nb5$true +.mv processedRight$_nb2$raw_nf3 2 myTRUE myFALSE +.names processedRight processedRight$_nb6$raw_nd9 _nb2 processedRight$_nb2$raw_nf3 +- - 0 =processedRight$_nb6$raw_nd9 +- - 1 =processedRight +# conflict arbitrators +.names _nb4 _nb8 _nbf _nf6 +.def 0 + 1 - - 1 + 0 0 1 1 +.mv _nf7 2 myTRUE myFALSE +.names _nf6 processedLeft$_nb2$raw_ne9 processedLeft _nf7 +1 - - =processedLeft$_nb2$raw_ne9 +0 - - =processedLeft +.names _n94 _n99 _n104 +.def 0 + 1 - 1 + 0 1 1 +.mv _n105 2 myTRUE myFALSE +.names _n104 prevLeft$_n92$raw_na9 prevLeft _n105 +1 - - =prevLeft$_n92$raw_na9 +0 - - =prevLeft +.names _n72 _n76 _n7d _n81 _n112 +.def 0 + 1 - - - 1 + 0 1 - - 1 + 0 0 1 - 1 + 0 0 0 1 1 +.mv _n113 2 myTRUE myFALSE +.names _n112 holdToken$_n70$raw_n8f holdToken _n113 +1 - - =holdToken$_n70$raw_n8f +0 - - =holdToken +.names _nb4 _nb8 _nbf _n120 +.def 0 + 0 1 - 1 + 0 0 1 1 +.mv _n121 2 myTRUE myFALSE +.names _n120 processedRight$_nb2$raw_nf3 processedRight _n121 +1 - - =processedRight$_nb2$raw_nf3 +0 - - =processedRight +.names uaLeft$raw_n26 uaLeft +- =uaLeft$raw_n26 +.names giveChild$raw_n1d giveChild +- =giveChild$raw_n1d +.names mustGiveParent$raw_n6 mustGiveParent +- =mustGiveParent$raw_n6 +.names xr$raw_n4e xr +- =xr$raw_n4e +.names uaRight$raw_n3a uaRight +- =uaRight$raw_n3a +.names childOwns$raw_n14 childOwns +- =childOwns$raw_n14 +.names _n94 _n99 _n12e +.def 0 + 1 - 1 + 0 1 1 +.mv _n12f 2 myTRUE myFALSE +.names _n12e prevRight$_n92$raw_nab prevRight _n12f +1 - - =prevRight$_n92$raw_nab +0 - - =prevRight +# non-blocking assignments +# latches +.r prevLeft$raw_n2 prevLeft +- =prevLeft$raw_n2 +.latch _n105 prevLeft +.r processedLeft$raw_n4 processedLeft +- =processedLeft$raw_n4 +.latch _nf7 processedLeft +.r processedRight$raw_n5 processedRight +- =processedRight$raw_n5 +.latch _n121 processedRight +.r holdToken$raw_n13 holdToken +- =holdToken$raw_n13 +.latch _n113 holdToken +.r prevRight$raw_n3 prevRight +- =prevRight$raw_n3 +.latch _n12f prevRight +# quasi-continuous assignment +.end + + +.model fourCells +# I/O ports +.inputs sa +.outputs sr +.mv constFALSE 2 myTRUE myFALSE +.mv sa 2 myTRUE myFALSE +.mv ur1 4 idle request lock release +.mv xa 2 myTRUE myFALSE +.mv ur2 4 idle request lock release +.mv yr 4 idle request lock release +.mv ur3 4 idle request lock release +.mv ua1 2 myTRUE myFALSE +.mv ur4 4 idle request lock release +.mv ua2 2 myTRUE myFALSE +.mv ua3 2 myTRUE myFALSE +.mv sr 4 idle request lock release +.mv ua4 2 myTRUE myFALSE +.mv xr 4 idle request lock release +.mv ya 2 myTRUE myFALSE +.mv constTRUE 2 myTRUE myFALSE +# assign constTRUE = 0 +.mv constTRUE$raw_n13c 2 myTRUE myFALSE +.names constTRUE$raw_n13c +myTRUE +# assign constFALSE = 1 +.mv constFALSE$raw_n13d 2 myTRUE myFALSE +.names constFALSE$raw_n13d +myFALSE +.subckt arbitCell C0 topCell=constFALSE urLeft=xr urRight=yr uaLeft=xa uaRight=ya xr=sr xa=sa +.subckt arbitCell C1 topCell=constFALSE urLeft=ur1 urRight=ur2 uaLeft=ua1 uaRight=ua2 xr=xr xa=xa +.subckt arbitCell C2 topCell=constFALSE urLeft=ur3 urRight=ur4 uaLeft=ua3 uaRight=ua4 xr=yr xa=ya +.subckt procModel P1 ack=ua1 req=ur1 +.subckt procModel P2 ack=ua2 req=ur2 +.subckt procModel P3 ack=ua3 req=ur3 +.subckt procModel P4 ack=ua4 req=ur4 +# conflict arbitrators +.names constFALSE$raw_n13d constFALSE +- =constFALSE$raw_n13d +.names constTRUE$raw_n13c constTRUE +- =constTRUE$raw_n13c +# non-blocking assignments +# latches +# quasi-continuous assignment +.end + + +.model procModel +# I/O ports +.outputs req +.inputs ack +.mv req 4 idle request lock release +.mv procState 4 idle request lock release +.mv ack 2 myTRUE myFALSE +# assign req = procState +.mv req$raw_n13e 4 idle request lock release +.names procState req$raw_n13e +- =procState +# assign randChoice = $NDset ( 0,1 ) +.names randChoice +0 +1 +# procState = 0 +.mv procState$raw_n141 4 idle request lock release +.names procState$raw_n141 +idle +# non-blocking assignments for initial +.mv _n143 4 idle request lock release +.names _n143 +idle +# procState == 0 +.names procState _n143 _n142 +.def 0 +- =procState 1 +.names _n145 +1 +# randChoice == 1 +.names randChoice _n145 _n146 +.def 0 +0 1 1 +1 0 1 +.names _n146 _n144 +0 1 +1 0 +# procState == 0 && (randChoice == 1) +.names _n142 _n144 _n148 +.def 0 +1 1 1 +.names _n148 _n149 +- =_n148 +# procState = 1 +.mv procState$_n148_n14a$true 4 idle request lock release +.names procState$_n148_n14a$true +request +.mv _n14c 4 idle request lock release +.names _n14c +request +# procState == 1 +.names procState _n14c _n14b +.def 0 +- =procState 1 +.mv _n14e 2 myTRUE myFALSE +.names _n14e +myTRUE +# ack == 0 +.names ack _n14e _n14d +.def 0 +- =ack 1 +# procState == 1 && ack == 0 +.names _n14b _n14d _n14f +.def 0 +1 1 1 +.names _n14f _n150 +- =_n14f +# procState = 2 +.mv procState$_n14f_n151$true 4 idle request lock release +.names procState$_n14f_n151$true +lock +.mv _n153 4 idle request lock release +.names _n153 +lock +# procState == 2 +.names procState _n153 _n152 +.def 0 +- =procState 1 +.names _n155 +1 +# randChoice == 1 +.names randChoice _n155 _n156 +.def 0 +0 1 1 +1 0 1 +.names _n156 _n154 +0 1 +1 0 +# procState == 2 && (randChoice == 1) +.names _n152 _n154 _n158 +.def 0 +1 1 1 +.names _n158 _n159 +- =_n158 +# procState = 3 +.mv procState$_n158_n15a$true 4 idle request lock release +.names procState$_n158_n15a$true +release +.mv _n15c 4 idle request lock release +.names _n15c +release +# procState == 3 +.names procState _n15c _n15b +.def 0 +- =procState 1 +.names _n15b _n15d +- =_n15b +# procState = 0 +.mv procState$_n15b_n15e$true 4 idle request lock release +.names procState$_n15b_n15e$true +idle +# if/else (procState == 3) +.mv procState$_n15b$raw_n161 4 idle request lock release +.names procState$_n15b_n15e$true procState _n15b procState$_n15b$raw_n161 +- - 0 =procState +- - 1 =procState$_n15b_n15e$true +# if/else (procState == 2 && (randChoice == 1)) +.mv procState$_n158$raw_n163 4 idle request lock release +.names procState$_n158_n15a$true procState$_n15b$raw_n161 _n158 procState$_n158$raw_n163 +- - 0 =procState$_n15b$raw_n161 +- - 1 =procState$_n158_n15a$true +# if/else (procState == 1 && ack == 0) +.mv procState$_n14f$raw_n167 4 idle request lock release +.names procState$_n14f_n151$true procState$_n158$raw_n163 _n14f procState$_n14f$raw_n167 +- - 0 =procState$_n158$raw_n163 +- - 1 =procState$_n14f_n151$true +# if/else (procState == 0 && (randChoice == 1)) +.mv procState$_n148$raw_n16b 4 idle request lock release +.names procState$_n148_n14a$true procState$_n14f$raw_n167 _n148 procState$_n148$raw_n16b +- - 0 =procState$_n14f$raw_n167 +- - 1 =procState$_n148_n14a$true +# conflict arbitrators +.names req$raw_n13e req +- =req$raw_n13e +.names _n149 _n150 _n159 _n15d _n16e +.def 0 + 1 - - - 1 + 0 1 - - 1 + 0 0 1 - 1 + 0 0 0 1 1 +.mv _n16f 4 idle request lock release +.names _n16e procState$_n148$raw_n16b procState _n16f +1 - - =procState$_n148$raw_n16b +0 - - =procState +# non-blocking assignments +# latches +.r procState$raw_n141 procState +- =procState$raw_n141 +.latch _n16f procState +# quasi-continuous assignment +.end + + Index: vis_dev/vis-2.1/examples/treearbiter/8-arbit.v =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/8-arbit.v (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/8-arbit.v (revision 11) @@ -0,0 +1,254 @@ +/************************************************************************** + + This is a simple tree arbiter, adapted from Dills' thesis p 89. + There are four processors which + share a single resource. A token defines which processor has the + resource. The arbiter cells have two children and one parent. + An arbiter can request the token, release it, etc. + + Adnan Aziz + July 10, 1996 + UT Austin + +***************************************************************************/ + +/* + * Symbolic variables. + * + */ +typedef enum {myTRUE, myFALSE} boolean; +typedef enum {idle, request, lock, release} handShakeType; + +/* + * The inteconnections between the processors and the cells. + * + */ +module main( clk ); +input clk; + +boolean wire xa, ya, sa; +handShakeType wire xr, yr, sr; + +boolean wire constTRUE; + + +assign sa = myFALSE; +assign constTRUE = myTRUE; + +arbitCell F0( clk, constTRUE, xr, yr, xa, ya, sr, sa ); +fourCells G1( clk, xa, xr ); +fourCells G2( clk, ya, yr ); + +endmodule + + +module fourCells( clk, sa, sr ); +input clk; +input sa; +output sr; + +boolean wire ua1, ua2, ua3, ua4, xa, ya, sa; +handShakeType wire ur1, ur2, ur3, ur4, xr, yr, sr; + +wire[0:1] procChoice; + +boolean wire constTRUE, constFALSE; + +assign constTRUE = myTRUE; +assign constFALSE = myFALSE; + +arbitCell C0 ( clk, constFALSE, xr, yr, xa, ya, sr, sa ); +arbitCell C1 ( clk, constFALSE, ur1, ur2, ua1, ua2, xr, xa ); +arbitCell C2 ( clk, constFALSE, ur3, ur4, ua3, ua4, yr, ya ); + +procModel P1( clk, ua1, ur1 ); +procModel P2( clk, ua2, ur2 ); +procModel P3( clk, ua3, ur3 ); +procModel P4( clk, ua4, ur4 ); + +endmodule + + +/* + * The arbiter cell has two inputs from children and two outputs to chidren. + * One input from parent, and one output to parent. The latch holdToken corresponds + * to whether the cell holds the token. The latches prevLeft and prevRight are + * used to keep track of which way the token went last, to impart fairness + * in the scheduling of the children. + * + */ + + +/* + * Add comments + */ +module procModel(clk, ack, req ); +input clk; +input ack; +output req; + +boolean wire ack; +handShakeType wire req; +wire randChoice; + +assign req = procState; +assign randChoice = $ND(0,1); + +handShakeType reg procState; + +initial procState = idle; + +always @(posedge clk) begin + + if ( procState == idle && (randChoice == 1) ) + begin + procState = request; + end + else if ( procState == request && ack == myTRUE ) + begin + procState = lock; + end + else if ( procState == lock && (randChoice == 1 ) ) + begin + procState = release; + end + else if ( procState == release ) + begin + procState = idle; + end +end + +endmodule + + + +module arbitCell(clk, topCell, urLeft, urRight, uaLeft, uaRight, xr, xa); +input clk; +input topCell, urLeft, urRight, xa; +output uaLeft, uaRight, xr; + +boolean wire topCell, uaLeft, uaRight, xa; +handShakeType wire urLeft, urRight, xr; + +boolean wire uaLeft, uaRight; + +boolean reg prevLeft, prevRight; +initial prevLeft = myFALSE; +initial prevRight = myTRUE; + +boolean reg processedLeft, processedRight; +initial processedLeft = myFALSE; +initial processedRight = myFALSE; + +boolean wire mustGiveParent; /* essentially a macro for checking if must release the token to parent */ +assign mustGiveParent = ( processedLeft == myTRUE ) && ( processedRight == myTRUE ) + && ( !( topCell == myTRUE ) ) ? myTRUE : myFALSE; + +boolean reg holdToken; +initial holdToken = topCell; + +boolean wire childOwns; /* essentially a macro for checking if a descendant owns the token */ +assign childOwns = ( urLeft == lock || urRight == lock ) ? myTRUE : myFALSE; + +boolean wire giveChild; /* essentially a macro for checking if a child is being given the token */ +assign giveChild = ( uaLeft == myTRUE || uaRight == myTRUE ) ? myTRUE : myFALSE; + +/* + * Condition under which the token is given to the left child + * Must own token, have request from left, and either no request from right or if there is + * a request from the right it, should be lefts turn (since right went the last time + * + */ +assign uaLeft = ( !( mustGiveParent == myTRUE ) && ( holdToken == myTRUE && urLeft == request + && ( ! ( urRight == request ) || prevRight == myTRUE ) ) ) ? myTRUE : myFALSE; + +/* + * same as above for right + * + */ +assign uaRight = ( !( mustGiveParent == myTRUE ) && ( holdToken == myTRUE && urRight == request + && ( ! ( urLeft == request ) || prevLeft == myTRUE ) ) ) ? myTRUE : myFALSE; + +/* + * signal to parent: + * + * 1. request if dont own the token, + * 2. lock if descendant has locked the token + * 3. release if child has released token + * 4. idle otherwise + * + */ +assign xr = ( holdToken == myFALSE && ( urLeft == request || urRight == request ) ) + ? request : + ( childOwns == myTRUE ) + ? lock : + ( holdToken == myTRUE && ( ( ( mustGiveParent == myTRUE ) || + ! ( ( urLeft == request || urRight == request ) ) ) + && !( topCell == myTRUE ) ) ) + ? release : idle; + +always @(posedge clk) begin + +/* + * keep track of whether we hold the token or not + * + */ + + if ( xa == myTRUE ) + begin + holdToken = myTRUE; + end + else if ( giveChild == myTRUE ) + begin + holdToken = myFALSE; + end + else if ( urLeft == release || urRight == release ) + begin + holdToken = myTRUE; + end + else if ( xr == release ) + begin + holdToken = myFALSE; + end + +/* + * keep track of which child got the token last + * + */ + if ( uaLeft == myTRUE ) + begin + prevLeft = myTRUE; + prevRight = myFALSE; + end + else if ( uaRight == myTRUE ) + begin + prevLeft = myFALSE; + prevRight = myTRUE; + end + +/* + * child has finished processing the token + * + */ + + if ( urLeft == release ) + begin + processedLeft = myTRUE; + end + else if ( urRight == release ) + begin + processedRight = myTRUE; + end +/* + * if we have given the token to both children, must now give it up + * + */ + else if ( ( processedLeft == myTRUE ) && ( processedRight == myTRUE ) ) + begin + processedLeft = myFALSE; + processedRight = myFALSE; + end + +end + +endmodule Index: vis_dev/vis-2.1/examples/treearbiter/README =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/README (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/README (revision 11) @@ -0,0 +1,14 @@ + +[4,8]-arbit.v are instantiations of a tree based mutual +exclusion circuit. They are reasonably well documented, +and should be useful in illustrating how to code Verilog +for VIS, how to use fairness and nondeterminism for +to model the environment modules. There is no nondeterminisn +in the arbiter cells; they are synthesizable. I used +this example in my class (it was a HW problem, and this is +the model solution). + +FILES - 4-arbit.v = verilog source + 4-arbit.mv = compiled blif-mv + 4-arbit.fair = fairness constraints + 4-arbit.ctl = properties to be checked Index: vis_dev/vis-2.1/examples/treearbiter/check_result =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/check_result (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/check_result (revision 11) @@ -0,0 +1,3 @@ +# BMC: no counterexample found of length up to 5 +# BMC: no counterexample found of length up to 5 +# BMC: formula failed Index: vis_dev/vis-2.1/examples/treearbiter/check_script =================================================================== --- vis_dev/vis-2.1/examples/treearbiter/check_script (revision 11) +++ vis_dev/vis-2.1/examples/treearbiter/check_script (revision 11) @@ -0,0 +1,6 @@ +read_blif_mv 8-arbit.mv +flatten_hierarchy +build_partition_maigs +bounded_model_check -m1 -k5 -v1 8-arbit.ltl +time +quit -s Index: vis_dev/vis-2.1/helpers/config.guess =================================================================== --- vis_dev/vis-2.1/helpers/config.guess (revision 11) +++ vis_dev/vis-2.1/helpers/config.guess (revision 11) @@ -0,0 +1,1400 @@ +#! /bin/sh +# Attempt to guess a canonical system name. +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +# 2000, 2001, 2002 Free Software Foundation, Inc. + +timestamp='2002-11-30' + +# This file is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, but +# WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. +# +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# Originally written by Per Bothner . +# Please send patches to . Submit a context +# diff and a properly formatted ChangeLog entry. +# +# This script attempts to guess a canonical system name similar to +# config.sub. If it succeeds, it prints the system name on stdout, and +# exits with 0. Otherwise, it exits with 1. +# +# The plan is that this can be called by configure scripts if you +# don't specify an explicit build system type. + +me=`echo "$0" | sed -e 's,.*/,,'` + +usage="\ +Usage: $0 [OPTION] + +Output the configuration name of the system \`$me' is run on. + +Operation modes: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to ." + +version="\ +GNU config.guess ($timestamp) + +Originally written by Per Bothner. +Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 +Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit 0 ;; + --version | -v ) + echo "$version" ; exit 0 ;; + --help | --h* | -h ) + echo "$usage"; exit 0 ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" >&2 + exit 1 ;; + * ) + break ;; + esac +done + +if test $# != 0; then + echo "$me: too many arguments$help" >&2 + exit 1 +fi + +trap 'exit 1' 1 2 15 + +# CC_FOR_BUILD -- compiler used by this script. Note that the use of a +# compiler to aid in system detection is discouraged as it requires +# temporary files to be created and, as you can see below, it is a +# headache to deal with in a portable fashion. + +# Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. We still +# use `HOST_CC' if defined, but it is deprecated. + +# This shell variable is my proudest work .. or something. --bje + +set_cc_for_build='tmpdir=${TMPDIR-/tmp}/config-guess-$$ ; +(old=`umask` && umask 077 && mkdir $tmpdir && umask $old && unset old) + || (echo "$me: cannot create $tmpdir" >&2 && exit 1) ; +dummy=$tmpdir/dummy ; +files="$dummy.c $dummy.o $dummy.rel $dummy" ; +trap '"'"'rm -f $files; rmdir $tmpdir; exit 1'"'"' 1 2 15 ; +case $CC_FOR_BUILD,$HOST_CC,$CC in + ,,) echo "int x;" > $dummy.c ; + for c in cc gcc c89 c99 ; do + if ($c -c -o $dummy.o $dummy.c) >/dev/null 2>&1 ; then + CC_FOR_BUILD="$c"; break ; + fi ; + done ; + rm -f $files ; + if test x"$CC_FOR_BUILD" = x ; then + CC_FOR_BUILD=no_compiler_found ; + fi + ;; + ,,*) CC_FOR_BUILD=$CC ;; + ,*,*) CC_FOR_BUILD=$HOST_CC ;; +esac ; +unset files' + +# This is needed to find uname on a Pyramid OSx when run in the BSD universe. +# (ghazi@noc.rutgers.edu 1994-08-24) +if (test -f /.attbin/uname) >/dev/null 2>&1 ; then + PATH=$PATH:/.attbin ; export PATH +fi + +UNAME_MACHINE=`(uname -m) 2>/dev/null` || UNAME_MACHINE=unknown +UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown +UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown +UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown + +# Note: order is significant - the case branches are not exclusive. + +case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in + *:NetBSD:*:*) + # NetBSD (nbsd) targets should (where applicable) match one or + # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*, + # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently + # switched to ELF, *-*-netbsd* would select the old + # object file format. This provides both forward + # compatibility and a consistent mechanism for selecting the + # object file format. + # + # Note: NetBSD doesn't particularly care about the vendor + # portion of the name. We always set it to "unknown". + sysctl="sysctl -n hw.machine_arch" + UNAME_MACHINE_ARCH=`(/sbin/$sysctl 2>/dev/null || \ + /usr/sbin/$sysctl 2>/dev/null || echo unknown)` + case "${UNAME_MACHINE_ARCH}" in + armeb) machine=armeb-unknown ;; + arm*) machine=arm-unknown ;; + sh3el) machine=shl-unknown ;; + sh3eb) machine=sh-unknown ;; + *) machine=${UNAME_MACHINE_ARCH}-unknown ;; + esac + # The Operating System including object format, if it has switched + # to ELF recently, or will in the future. + case "${UNAME_MACHINE_ARCH}" in + arm*|i386|m68k|ns32k|sh3*|sparc|vax) + eval $set_cc_for_build + if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ + | grep __ELF__ >/dev/null + then + # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout). + # Return netbsd for either. FIX? + os=netbsd + else + os=netbsdelf + fi + ;; + *) + os=netbsd + ;; + esac + # The OS release + # Debian GNU/NetBSD machines have a different userland, and + # thus, need a distinct triplet. However, they do not need + # kernel version information, so it can be replaced with a + # suitable tag, in the style of linux-gnu. + case "${UNAME_VERSION}" in + Debian*) + release='-gnu' + ;; + *) + release=`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'` + ;; + esac + # Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM: + # contains redundant information, the shorter form: + # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. + echo "${machine}-${os}${release}" + exit 0 ;; + amiga:OpenBSD:*:*) + echo m68k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + arc:OpenBSD:*:*) + echo mipsel-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + hp300:OpenBSD:*:*) + echo m68k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + mac68k:OpenBSD:*:*) + echo m68k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + macppc:OpenBSD:*:*) + echo powerpc-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + mvme68k:OpenBSD:*:*) + echo m68k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + mvme88k:OpenBSD:*:*) + echo m88k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + mvmeppc:OpenBSD:*:*) + echo powerpc-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + pmax:OpenBSD:*:*) + echo mipsel-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + sgi:OpenBSD:*:*) + echo mipseb-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + sun3:OpenBSD:*:*) + echo m68k-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + wgrisc:OpenBSD:*:*) + echo mipsel-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + *:OpenBSD:*:*) + echo ${UNAME_MACHINE}-unknown-openbsd${UNAME_RELEASE} + exit 0 ;; + alpha:OSF1:*:*) + if test $UNAME_RELEASE = "V4.0"; then + UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'` + fi + # A Vn.n version is a released version. + # A Tn.n version is a released field test version. + # A Xn.n version is an unreleased experimental baselevel. + # 1.2 uses "1.2" for uname -r. + eval $set_cc_for_build + cat <$dummy.s + .data +\$Lformat: + .byte 37,100,45,37,120,10,0 # "%d-%x\n" + + .text + .globl main + .align 4 + .ent main +main: + .frame \$30,16,\$26,0 + ldgp \$29,0(\$27) + .prologue 1 + .long 0x47e03d80 # implver \$0 + lda \$2,-1 + .long 0x47e20c21 # amask \$2,\$1 + lda \$16,\$Lformat + mov \$0,\$17 + not \$1,\$18 + jsr \$26,printf + ldgp \$29,0(\$26) + mov 0,\$16 + jsr \$26,exit + .end main +EOF + $CC_FOR_BUILD -o $dummy $dummy.s 2>/dev/null + if test "$?" = 0 ; then + case `$dummy` in + 0-0) + UNAME_MACHINE="alpha" + ;; + 1-0) + UNAME_MACHINE="alphaev5" + ;; + 1-1) + UNAME_MACHINE="alphaev56" + ;; + 1-101) + UNAME_MACHINE="alphapca56" + ;; + 2-303) + UNAME_MACHINE="alphaev6" + ;; + 2-307) + UNAME_MACHINE="alphaev67" + ;; + 2-1307) + UNAME_MACHINE="alphaev68" + ;; + 3-1307) + UNAME_MACHINE="alphaev7" + ;; + esac + fi + rm -f $dummy.s $dummy && rmdir $tmpdir + echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[VTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` + exit 0 ;; + Alpha\ *:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # Should we change UNAME_MACHINE based on the output of uname instead + # of the specific Alpha model? + echo alpha-pc-interix + exit 0 ;; + 21064:Windows_NT:50:3) + echo alpha-dec-winnt3.5 + exit 0 ;; + Amiga*:UNIX_System_V:4.0:*) + echo m68k-unknown-sysv4 + exit 0;; + *:[Aa]miga[Oo][Ss]:*:*) + echo ${UNAME_MACHINE}-unknown-amigaos + exit 0 ;; + *:[Mm]orph[Oo][Ss]:*:*) + echo ${UNAME_MACHINE}-unknown-morphos + exit 0 ;; + *:OS/390:*:*) + echo i370-ibm-openedition + exit 0 ;; + arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) + echo arm-acorn-riscix${UNAME_RELEASE} + exit 0;; + SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) + echo hppa1.1-hitachi-hiuxmpp + exit 0;; + Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*) + # akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE. + if test "`(/bin/universe) 2>/dev/null`" = att ; then + echo pyramid-pyramid-sysv3 + else + echo pyramid-pyramid-bsd + fi + exit 0 ;; + NILE*:*:*:dcosx) + echo pyramid-pyramid-svr4 + exit 0 ;; + DRS?6000:UNIX_SV:4.2*:7*) + case `/usr/bin/uname -p` in + sparc) echo sparc-icl-nx7 && exit 0 ;; + esac ;; + sun4H:SunOS:5.*:*) + echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit 0 ;; + sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) + echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit 0 ;; + i86pc:SunOS:5.*:*) + echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit 0 ;; + sun4*:SunOS:6*:*) + # According to config.sub, this is the proper way to canonicalize + # SunOS6. Hard to guess exactly what SunOS6 will be like, but + # it's likely to be more like Solaris than SunOS4. + echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit 0 ;; + sun4*:SunOS:*:*) + case "`/usr/bin/arch -k`" in + Series*|S4*) + UNAME_RELEASE=`uname -v` + ;; + esac + # Japanese Language versions have a version number like `4.1.3-JL'. + echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'` + exit 0 ;; + sun3*:SunOS:*:*) + echo m68k-sun-sunos${UNAME_RELEASE} + exit 0 ;; + sun*:*:4.2BSD:*) + UNAME_RELEASE=`(sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null` + test "x${UNAME_RELEASE}" = "x" && UNAME_RELEASE=3 + case "`/bin/arch`" in + sun3) + echo m68k-sun-sunos${UNAME_RELEASE} + ;; + sun4) + echo sparc-sun-sunos${UNAME_RELEASE} + ;; + esac + exit 0 ;; + aushp:SunOS:*:*) + echo sparc-auspex-sunos${UNAME_RELEASE} + exit 0 ;; + # The situation for MiNT is a little confusing. The machine name + # can be virtually everything (everything which is not + # "atarist" or "atariste" at least should have a processor + # > m68000). The system name ranges from "MiNT" over "FreeMiNT" + # to the lowercase version "mint" (or "freemint"). Finally + # the system name "TOS" denotes a system which is actually not + # MiNT. But MiNT is downward compatible to TOS, so this should + # be no problem. + atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit 0 ;; + atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit 0 ;; + *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) + echo m68k-atari-mint${UNAME_RELEASE} + exit 0 ;; + milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) + echo m68k-milan-mint${UNAME_RELEASE} + exit 0 ;; + hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) + echo m68k-hades-mint${UNAME_RELEASE} + exit 0 ;; + *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) + echo m68k-unknown-mint${UNAME_RELEASE} + exit 0 ;; + powerpc:machten:*:*) + echo powerpc-apple-machten${UNAME_RELEASE} + exit 0 ;; + RISC*:Mach:*:*) + echo mips-dec-mach_bsd4.3 + exit 0 ;; + RISC*:ULTRIX:*:*) + echo mips-dec-ultrix${UNAME_RELEASE} + exit 0 ;; + VAX*:ULTRIX*:*:*) + echo vax-dec-ultrix${UNAME_RELEASE} + exit 0 ;; + 2020:CLIX:*:* | 2430:CLIX:*:*) + echo clipper-intergraph-clix${UNAME_RELEASE} + exit 0 ;; + mips:*:*:UMIPS | mips:*:*:RISCos) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c +#ifdef __cplusplus +#include /* for printf() prototype */ + int main (int argc, char *argv[]) { +#else + int main (argc, argv) int argc; char *argv[]; { +#endif + #if defined (host_mips) && defined (MIPSEB) + #if defined (SYSTYPE_SYSV) + printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_SVR4) + printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); + #endif + #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) + printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); + #endif + #endif + exit (-1); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c \ + && $dummy `echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` \ + && rm -f $dummy.c $dummy && rmdir $tmpdir && exit 0 + rm -f $dummy.c $dummy && rmdir $tmpdir + echo mips-mips-riscos${UNAME_RELEASE} + exit 0 ;; + Motorola:PowerMAX_OS:*:*) + echo powerpc-motorola-powermax + exit 0 ;; + Motorola:*:4.3:PL8-*) + echo powerpc-harris-powermax + exit 0 ;; + Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) + echo powerpc-harris-powermax + exit 0 ;; + Night_Hawk:Power_UNIX:*:*) + echo powerpc-harris-powerunix + exit 0 ;; + m88k:CX/UX:7*:*) + echo m88k-harris-cxux7 + exit 0 ;; + m88k:*:4*:R4*) + echo m88k-motorola-sysv4 + exit 0 ;; + m88k:*:3*:R3*) + echo m88k-motorola-sysv3 + exit 0 ;; + AViiON:dgux:*:*) + # DG/UX returns AViiON for all architectures + UNAME_PROCESSOR=`/usr/bin/uname -p` + if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] + then + if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ + [ ${TARGET_BINARY_INTERFACE}x = x ] + then + echo m88k-dg-dgux${UNAME_RELEASE} + else + echo m88k-dg-dguxbcs${UNAME_RELEASE} + fi + else + echo i586-dg-dgux${UNAME_RELEASE} + fi + exit 0 ;; + M88*:DolphinOS:*:*) # DolphinOS (SVR3) + echo m88k-dolphin-sysv3 + exit 0 ;; + M88*:*:R3*:*) + # Delta 88k system running SVR3 + echo m88k-motorola-sysv3 + exit 0 ;; + XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) + echo m88k-tektronix-sysv3 + exit 0 ;; + Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) + echo m68k-tektronix-bsd + exit 0 ;; + *:IRIX*:*:*) + echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` + exit 0 ;; + ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. + echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id + exit 0 ;; # Note that: echo "'`uname -s`'" gives 'AIX ' + i*86:AIX:*:*) + echo i386-ibm-aix + exit 0 ;; + ia64:AIX:*:*) + if [ -x /usr/bin/oslevel ] ; then + IBM_REV=`/usr/bin/oslevel` + else + IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} + fi + echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} + exit 0 ;; + *:AIX:2:3) + if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + + main() + { + if (!__power_pc()) + exit(1); + puts("powerpc-ibm-aix3.2.5"); + exit(0); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && rm -f $dummy.c $dummy && rmdir $tmpdir && exit 0 + rm -f $dummy.c $dummy && rmdir $tmpdir + echo rs6000-ibm-aix3.2.5 + elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then + echo rs6000-ibm-aix3.2.4 + else + echo rs6000-ibm-aix3.2 + fi + exit 0 ;; + *:AIX:*:[45]) + IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` + if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then + IBM_ARCH=rs6000 + else + IBM_ARCH=powerpc + fi + if [ -x /usr/bin/oslevel ] ; then + IBM_REV=`/usr/bin/oslevel` + else + IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} + fi + echo ${IBM_ARCH}-ibm-aix${IBM_REV} + exit 0 ;; + *:AIX:*:*) + echo rs6000-ibm-aix + exit 0 ;; + ibmrt:4.4BSD:*|romp-ibm:BSD:*) + echo romp-ibm-bsd4.4 + exit 0 ;; + ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and + echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to + exit 0 ;; # report: romp-ibm BSD 4.3 + *:BOSX:*:*) + echo rs6000-bull-bosx + exit 0 ;; + DPX/2?00:B.O.S.:*:*) + echo m68k-bull-sysv3 + exit 0 ;; + 9000/[34]??:4.3bsd:1.*:*) + echo m68k-hp-bsd + exit 0 ;; + hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) + echo m68k-hp-bsd4.4 + exit 0 ;; + 9000/[34678]??:HP-UX:*:*) + HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` + case "${UNAME_MACHINE}" in + 9000/31? ) HP_ARCH=m68000 ;; + 9000/[34]?? ) HP_ARCH=m68k ;; + 9000/[678][0-9][0-9]) + if [ -x /usr/bin/getconf ]; then + sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` + sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` + case "${sc_cpu_version}" in + 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 + 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 + 532) # CPU_PA_RISC2_0 + case "${sc_kernel_bits}" in + 32) HP_ARCH="hppa2.0n" ;; + 64) HP_ARCH="hppa2.0w" ;; + '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 + esac ;; + esac + fi + if [ "${HP_ARCH}" = "" ]; then + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + + #define _HPUX_SOURCE + #include + #include + + int main () + { + #if defined(_SC_KERNEL_BITS) + long bits = sysconf(_SC_KERNEL_BITS); + #endif + long cpu = sysconf (_SC_CPU_VERSION); + + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1"); break; + case CPU_PA_RISC2_0: + #if defined(_SC_KERNEL_BITS) + switch (bits) + { + case 64: puts ("hppa2.0w"); break; + case 32: puts ("hppa2.0n"); break; + default: puts ("hppa2.0"); break; + } break; + #else /* !defined(_SC_KERNEL_BITS) */ + puts ("hppa2.0"); break; + #endif + default: puts ("hppa1.0"); break; + } + exit (0); + } +EOF + (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` + if test -z "$HP_ARCH"; then HP_ARCH=hppa; fi + rm -f $dummy.c $dummy && rmdir $tmpdir + fi ;; + esac + echo ${HP_ARCH}-hp-hpux${HPUX_REV} + exit 0 ;; + ia64:HP-UX:*:*) + HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` + echo ia64-hp-hpux${HPUX_REV} + exit 0 ;; + 3050*:HI-UX:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + int + main () + { + long cpu = sysconf (_SC_CPU_VERSION); + /* The order matters, because CPU_IS_HP_MC68K erroneously returns + true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct + results, however. */ + if (CPU_IS_PA_RISC (cpu)) + { + switch (cpu) + { + case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; + case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; + case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; + default: puts ("hppa-hitachi-hiuxwe2"); break; + } + } + else if (CPU_IS_HP_MC68K (cpu)) + puts ("m68k-hitachi-hiuxwe2"); + else puts ("unknown-hitachi-hiuxwe2"); + exit (0); + } +EOF + $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && rm -f $dummy.c $dummy && rmdir $tmpdir && exit 0 + rm -f $dummy.c $dummy && rmdir $tmpdir + echo unknown-hitachi-hiuxwe2 + exit 0 ;; + 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) + echo hppa1.1-hp-bsd + exit 0 ;; + 9000/8??:4.3bsd:*:*) + echo hppa1.0-hp-bsd + exit 0 ;; + *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) + echo hppa1.0-hp-mpeix + exit 0 ;; + hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) + echo hppa1.1-hp-osf + exit 0 ;; + hp8??:OSF1:*:*) + echo hppa1.0-hp-osf + exit 0 ;; + i*86:OSF1:*:*) + if [ -x /usr/sbin/sysversion ] ; then + echo ${UNAME_MACHINE}-unknown-osf1mk + else + echo ${UNAME_MACHINE}-unknown-osf1 + fi + exit 0 ;; + parisc*:Lites*:*:*) + echo hppa1.1-hp-lites + exit 0 ;; + C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) + echo c1-convex-bsd + exit 0 ;; + C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) + if getsysinfo -f scalar_acc + then echo c32-convex-bsd + else echo c2-convex-bsd + fi + exit 0 ;; + C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) + echo c34-convex-bsd + exit 0 ;; + C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) + echo c38-convex-bsd + exit 0 ;; + C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) + echo c4-convex-bsd + exit 0 ;; + CRAY*Y-MP:*:*:*) + echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit 0 ;; + CRAY*[A-Z]90:*:*:*) + echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ + | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ + -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ + -e 's/\.[^.]*$/.X/' + exit 0 ;; + CRAY*TS:*:*:*) + echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit 0 ;; + CRAY*T3D:*:*:*) + echo alpha-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit 0 ;; + CRAY*T3E:*:*:*) + echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit 0 ;; + CRAY*SV1:*:*:*) + echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' + exit 0 ;; + F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) + FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` + FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` + FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` + echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" + exit 0 ;; + i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) + echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} + exit 0 ;; + sparc*:BSD/OS:*:*) + echo sparc-unknown-bsdi${UNAME_RELEASE} + exit 0 ;; + *:BSD/OS:*:*) + echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} + exit 0 ;; + *:FreeBSD:*:*) + # Determine whether the default compiler uses glibc. + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + #if __GLIBC__ >= 2 + LIBC=gnu + #else + LIBC= + #endif +EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^LIBC=` + rm -f $dummy.c && rmdir $tmpdir + echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`${LIBC:+-$LIBC} + exit 0 ;; + i*:CYGWIN*:*) + echo ${UNAME_MACHINE}-pc-cygwin + exit 0 ;; + i*:MINGW*:*) + echo ${UNAME_MACHINE}-pc-mingw32 + exit 0 ;; + i*:PW*:*) + echo ${UNAME_MACHINE}-pc-pw32 + exit 0 ;; + x86:Interix*:3*) + echo i586-pc-interix3 + exit 0 ;; + [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) + echo i${UNAME_MACHINE}-pc-mks + exit 0 ;; + i*:Windows_NT*:* | Pentium*:Windows_NT*:*) + # How do we know it's Interix rather than the generic POSIX subsystem? + # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we + # UNAME_MACHINE based on the output of uname instead of i386? + echo i586-pc-interix + exit 0 ;; + i*:UWIN*:*) + echo ${UNAME_MACHINE}-pc-uwin + exit 0 ;; + p*:CYGWIN*:*) + echo powerpcle-unknown-cygwin + exit 0 ;; + prep*:SunOS:5.*:*) + echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` + exit 0 ;; + *:GNU:*:*) + echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` + exit 0 ;; + i*86:Minix:*:*) + echo ${UNAME_MACHINE}-pc-minix + exit 0 ;; + arm*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit 0 ;; + ia64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit 0 ;; + m68*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit 0 ;; + mips:Linux:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #undef CPU + #undef mips + #undef mipsel + #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) + CPU=mipsel + #else + #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) + CPU=mips + #else + CPU= + #endif + #endif +EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` + rm -f $dummy.c && rmdir $tmpdir + test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 + ;; + mips64:Linux:*:*) + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #undef CPU + #undef mips64 + #undef mips64el + #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) + CPU=mips64el + #else + #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) + CPU=mips64 + #else + CPU= + #endif + #endif +EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` + rm -f $dummy.c && rmdir $tmpdir + test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 + ;; + ppc:Linux:*:*) + echo powerpc-unknown-linux-gnu + exit 0 ;; + ppc64:Linux:*:*) + echo powerpc64-unknown-linux-gnu + exit 0 ;; + alpha:Linux:*:*) + case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in + EV5) UNAME_MACHINE=alphaev5 ;; + EV56) UNAME_MACHINE=alphaev56 ;; + PCA56) UNAME_MACHINE=alphapca56 ;; + PCA57) UNAME_MACHINE=alphapca56 ;; + EV6) UNAME_MACHINE=alphaev6 ;; + EV67) UNAME_MACHINE=alphaev67 ;; + EV68*) UNAME_MACHINE=alphaev68 ;; + esac + objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null + if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi + echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} + exit 0 ;; + parisc:Linux:*:* | hppa:Linux:*:*) + # Look for CPU level + case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in + PA7*) echo hppa1.1-unknown-linux-gnu ;; + PA8*) echo hppa2.0-unknown-linux-gnu ;; + *) echo hppa-unknown-linux-gnu ;; + esac + exit 0 ;; + parisc64:Linux:*:* | hppa64:Linux:*:*) + echo hppa64-unknown-linux-gnu + exit 0 ;; + s390:Linux:*:* | s390x:Linux:*:*) + echo ${UNAME_MACHINE}-ibm-linux + exit 0 ;; + sh*:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit 0 ;; + sparc:Linux:*:* | sparc64:Linux:*:*) + echo ${UNAME_MACHINE}-unknown-linux-gnu + exit 0 ;; + x86_64:Linux:*:*) + echo x86_64-unknown-linux-gnu + exit 0 ;; + i*86:Linux:*:*) + # The BFD linker knows what the default object file format is, so + # first see if it will tell us. cd to the root directory to prevent + # problems with other programs or directories called `ld' in the path. + # Set LC_ALL=C to ensure ld outputs messages in English. + ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \ + | sed -ne '/supported targets:/!d + s/[ ][ ]*/ /g + s/.*supported targets: *// + s/ .*// + p'` + case "$ld_supported_targets" in + elf32-i386) + TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu" + ;; + a.out-i386-linux) + echo "${UNAME_MACHINE}-pc-linux-gnuaout" + exit 0 ;; + coff-i386) + echo "${UNAME_MACHINE}-pc-linux-gnucoff" + exit 0 ;; + "") + # Either a pre-BFD a.out linker (linux-gnuoldld) or + # one that does not give us useful --help. + echo "${UNAME_MACHINE}-pc-linux-gnuoldld" + exit 0 ;; + esac + # Determine whether the default compiler is a.out or elf + eval $set_cc_for_build + sed 's/^ //' << EOF >$dummy.c + #include + #ifdef __ELF__ + # ifdef __GLIBC__ + # if __GLIBC__ >= 2 + LIBC=gnu + # else + LIBC=gnulibc1 + # endif + # else + LIBC=gnulibc1 + # endif + #else + #ifdef __INTEL_COMPILER + LIBC=gnu + #else + LIBC=gnuaout + #endif + #endif +EOF + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^LIBC=` + rm -f $dummy.c && rmdir $tmpdir + test x"${LIBC}" != x && echo "${UNAME_MACHINE}-pc-linux-${LIBC}" && exit 0 + test x"${TENTATIVE}" != x && echo "${TENTATIVE}" && exit 0 + ;; + i*86:DYNIX/ptx:4*:*) + # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. + # earlier versions are messed up and put the nodename in both + # sysname and nodename. + echo i386-sequent-sysv4 + exit 0 ;; + i*86:UNIX_SV:4.2MP:2.*) + # Unixware is an offshoot of SVR4, but it has its own version + # number series starting with 2... + # I am not positive that other SVR4 systems won't match this, + # I just have to hope. -- rms. + # Use sysv4.2uw... so that sysv4* matches it. + echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} + exit 0 ;; + i*86:OS/2:*:*) + # If we were able to find `uname', then EMX Unix compatibility + # is probably installed. + echo ${UNAME_MACHINE}-pc-os2-emx + exit 0 ;; + i*86:XTS-300:*:STOP) + echo ${UNAME_MACHINE}-unknown-stop + exit 0 ;; + i*86:atheos:*:*) + echo ${UNAME_MACHINE}-unknown-atheos + exit 0 ;; + i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) + echo i386-unknown-lynxos${UNAME_RELEASE} + exit 0 ;; + i*86:*DOS:*:*) + echo ${UNAME_MACHINE}-pc-msdosdjgpp + exit 0 ;; + i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) + UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` + if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then + echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} + else + echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} + fi + exit 0 ;; + i*86:*:5:[78]*) + case `/bin/uname -X | grep "^Machine"` in + *486*) UNAME_MACHINE=i486 ;; + *Pentium) UNAME_MACHINE=i586 ;; + *Pent*|*Celeron) UNAME_MACHINE=i686 ;; + esac + echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} + exit 0 ;; + i*86:*:3.2:*) + if test -f /usr/options/cb.name; then + UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then + UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')` + (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 + (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ + && UNAME_MACHINE=i586 + (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ + && UNAME_MACHINE=i686 + (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ + && UNAME_MACHINE=i686 + echo ${UNAME_MACHINE}-pc-sco$UNAME_REL + else + echo ${UNAME_MACHINE}-pc-sysv32 + fi + exit 0 ;; + pc:*:*:*) + # Left here for compatibility: + # uname -m prints for DJGPP always 'pc', but it prints nothing about + # the processor, so we play safe by assuming i386. + echo i386-pc-msdosdjgpp + exit 0 ;; + Intel:Mach:3*:*) + echo i386-pc-mach3 + exit 0 ;; + paragon:*:*:*) + echo i860-intel-osf1 + exit 0 ;; + i860:*:4.*:*) # i860-SVR4 + if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then + echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 + else # Add other i860-SVR4 vendors below as they are discovered. + echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 + fi + exit 0 ;; + mini*:CTIX:SYS*5:*) + # "miniframe" + echo m68010-convergent-sysv + exit 0 ;; + mc68k:UNIX:SYSTEM5:3.51m) + echo m68k-convergent-sysv + exit 0 ;; + M680?0:D-NIX:5.3:*) + echo m68k-diab-dnix + exit 0 ;; + M68*:*:R3V[567]*:*) + test -r /sysV68 && echo 'm68k-motorola-sysv' && exit 0 ;; + 3[34]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0) + OS_REL='' + test -r /etc/.relid \ + && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && echo i486-ncr-sysv4.3${OS_REL} && exit 0 + /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ + && echo i586-ncr-sysv4.3${OS_REL} && exit 0 ;; + 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) + /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ + && echo i486-ncr-sysv4 && exit 0 ;; + m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) + echo m68k-unknown-lynxos${UNAME_RELEASE} + exit 0 ;; + mc68030:UNIX_System_V:4.*:*) + echo m68k-atari-sysv4 + exit 0 ;; + TSUNAMI:LynxOS:2.*:*) + echo sparc-unknown-lynxos${UNAME_RELEASE} + exit 0 ;; + rs6000:LynxOS:2.*:*) + echo rs6000-unknown-lynxos${UNAME_RELEASE} + exit 0 ;; + PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) + echo powerpc-unknown-lynxos${UNAME_RELEASE} + exit 0 ;; + SM[BE]S:UNIX_SV:*:*) + echo mips-dde-sysv${UNAME_RELEASE} + exit 0 ;; + RM*:ReliantUNIX-*:*:*) + echo mips-sni-sysv4 + exit 0 ;; + RM*:SINIX-*:*:*) + echo mips-sni-sysv4 + exit 0 ;; + *:SINIX-*:*:*) + if uname -p 2>/dev/null >/dev/null ; then + UNAME_MACHINE=`(uname -p) 2>/dev/null` + echo ${UNAME_MACHINE}-sni-sysv4 + else + echo ns32k-sni-sysv + fi + exit 0 ;; + PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort + # says + echo i586-unisys-sysv4 + exit 0 ;; + *:UNIX_System_V:4*:FTX*) + # From Gerald Hewes . + # How about differentiating between stratus architectures? -djm + echo hppa1.1-stratus-sysv4 + exit 0 ;; + *:*:*:FTX*) + # From seanf@swdc.stratus.com. + echo i860-stratus-sysv4 + exit 0 ;; + *:VOS:*:*) + # From Paul.Green@stratus.com. + echo hppa1.1-stratus-vos + exit 0 ;; + mc68*:A/UX:*:*) + echo m68k-apple-aux${UNAME_RELEASE} + exit 0 ;; + news*:NEWS-OS:6*:*) + echo mips-sony-newsos6 + exit 0 ;; + R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) + if [ -d /usr/nec ]; then + echo mips-nec-sysv${UNAME_RELEASE} + else + echo mips-unknown-sysv${UNAME_RELEASE} + fi + exit 0 ;; + BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. + echo powerpc-be-beos + exit 0 ;; + BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. + echo powerpc-apple-beos + exit 0 ;; + BePC:BeOS:*:*) # BeOS running on Intel PC compatible. + echo i586-pc-beos + exit 0 ;; + SX-4:SUPER-UX:*:*) + echo sx4-nec-superux${UNAME_RELEASE} + exit 0 ;; + SX-5:SUPER-UX:*:*) + echo sx5-nec-superux${UNAME_RELEASE} + exit 0 ;; + SX-6:SUPER-UX:*:*) + echo sx6-nec-superux${UNAME_RELEASE} + exit 0 ;; + Power*:Rhapsody:*:*) + echo powerpc-apple-rhapsody${UNAME_RELEASE} + exit 0 ;; + *:Rhapsody:*:*) + echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} + exit 0 ;; + *:Darwin:*:*) + echo `uname -p`-apple-darwin${UNAME_RELEASE} + exit 0 ;; + *:procnto*:*:* | *:QNX:[0123456789]*:*) + UNAME_PROCESSOR=`uname -p` + if test "$UNAME_PROCESSOR" = "x86"; then + UNAME_PROCESSOR=i386 + UNAME_MACHINE=pc + fi + echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} + exit 0 ;; + *:QNX:*:4*) + echo i386-pc-qnx + exit 0 ;; + NSR-[DGKLNPTVW]:NONSTOP_KERNEL:*:*) + echo nsr-tandem-nsk${UNAME_RELEASE} + exit 0 ;; + *:NonStop-UX:*:*) + echo mips-compaq-nonstopux + exit 0 ;; + BS2000:POSIX*:*:*) + echo bs2000-siemens-sysv + exit 0 ;; + DS/*:UNIX_System_V:*:*) + echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} + exit 0 ;; + *:Plan9:*:*) + # "uname -m" is not consistent, so use $cputype instead. 386 + # is converted to i386 for consistency with other x86 + # operating systems. + if test "$cputype" = "386"; then + UNAME_MACHINE=i386 + else + UNAME_MACHINE="$cputype" + fi + echo ${UNAME_MACHINE}-unknown-plan9 + exit 0 ;; + *:TOPS-10:*:*) + echo pdp10-unknown-tops10 + exit 0 ;; + *:TENEX:*:*) + echo pdp10-unknown-tenex + exit 0 ;; + KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) + echo pdp10-dec-tops20 + exit 0 ;; + XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) + echo pdp10-xkl-tops20 + exit 0 ;; + *:TOPS-20:*:*) + echo pdp10-unknown-tops20 + exit 0 ;; + *:ITS:*:*) + echo pdp10-unknown-its + exit 0 ;; +esac + +#echo '(No uname command or uname output not recognized.)' 1>&2 +#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 + +eval $set_cc_for_build +cat >$dummy.c < +# include +#endif +main () +{ +#if defined (sony) +#if defined (MIPSEB) + /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, + I don't know.... */ + printf ("mips-sony-bsd\n"); exit (0); +#else +#include + printf ("m68k-sony-newsos%s\n", +#ifdef NEWSOS4 + "4" +#else + "" +#endif + ); exit (0); +#endif +#endif + +#if defined (__arm) && defined (__acorn) && defined (__unix) + printf ("arm-acorn-riscix"); exit (0); +#endif + +#if defined (hp300) && !defined (hpux) + printf ("m68k-hp-bsd\n"); exit (0); +#endif + +#if defined (NeXT) +#if !defined (__ARCHITECTURE__) +#define __ARCHITECTURE__ "m68k" +#endif + int version; + version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; + if (version < 4) + printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); + else + printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); + exit (0); +#endif + +#if defined (MULTIMAX) || defined (n16) +#if defined (UMAXV) + printf ("ns32k-encore-sysv\n"); exit (0); +#else +#if defined (CMU) + printf ("ns32k-encore-mach\n"); exit (0); +#else + printf ("ns32k-encore-bsd\n"); exit (0); +#endif +#endif +#endif + +#if defined (__386BSD__) + printf ("i386-pc-bsd\n"); exit (0); +#endif + +#if defined (sequent) +#if defined (i386) + printf ("i386-sequent-dynix\n"); exit (0); +#endif +#if defined (ns32000) + printf ("ns32k-sequent-dynix\n"); exit (0); +#endif +#endif + +#if defined (_SEQUENT_) + struct utsname un; + + uname(&un); + + if (strncmp(un.version, "V2", 2) == 0) { + printf ("i386-sequent-ptx2\n"); exit (0); + } + if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ + printf ("i386-sequent-ptx1\n"); exit (0); + } + printf ("i386-sequent-ptx\n"); exit (0); + +#endif + +#if defined (vax) +# if !defined (ultrix) +# include +# if defined (BSD) +# if BSD == 43 + printf ("vax-dec-bsd4.3\n"); exit (0); +# else +# if BSD == 199006 + printf ("vax-dec-bsd4.3reno\n"); exit (0); +# else + printf ("vax-dec-bsd\n"); exit (0); +# endif +# endif +# else + printf ("vax-dec-bsd\n"); exit (0); +# endif +# else + printf ("vax-dec-ultrix\n"); exit (0); +# endif +#endif + +#if defined (alliant) && defined (i860) + printf ("i860-alliant-bsd\n"); exit (0); +#endif + + exit (1); +} +EOF + +$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && $dummy && rm -f $dummy.c $dummy && rmdir $tmpdir && exit 0 +rm -f $dummy.c $dummy && rmdir $tmpdir + +# Apollos put the system type in the environment. + +test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit 0; } + +# Convex versions that predate uname can use getsysinfo(1) + +if [ -x /usr/convex/getsysinfo ] +then + case `getsysinfo -f cpu_type` in + c1*) + echo c1-convex-bsd + exit 0 ;; + c2*) + if getsysinfo -f scalar_acc + then echo c32-convex-bsd + else echo c2-convex-bsd + fi + exit 0 ;; + c34*) + echo c34-convex-bsd + exit 0 ;; + c38*) + echo c38-convex-bsd + exit 0 ;; + c4*) + echo c4-convex-bsd + exit 0 ;; + esac +fi + +cat >&2 < in order to provide the needed +information to handle your system. + +config.guess timestamp = $timestamp + +uname -m = `(uname -m) 2>/dev/null || echo unknown` +uname -r = `(uname -r) 2>/dev/null || echo unknown` +uname -s = `(uname -s) 2>/dev/null || echo unknown` +uname -v = `(uname -v) 2>/dev/null || echo unknown` + +/usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` +/bin/uname -X = `(/bin/uname -X) 2>/dev/null` + +hostinfo = `(hostinfo) 2>/dev/null` +/bin/universe = `(/bin/universe) 2>/dev/null` +/usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` +/bin/arch = `(/bin/arch) 2>/dev/null` +/usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` +/usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` + +UNAME_MACHINE = ${UNAME_MACHINE} +UNAME_RELEASE = ${UNAME_RELEASE} +UNAME_SYSTEM = ${UNAME_SYSTEM} +UNAME_VERSION = ${UNAME_VERSION} +EOF + +exit 1 + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: Index: vis_dev/vis-2.1/helpers/config.sub =================================================================== --- vis_dev/vis-2.1/helpers/config.sub (revision 11) +++ vis_dev/vis-2.1/helpers/config.sub (revision 11) @@ -0,0 +1,1469 @@ +#! /bin/sh +# Configuration validation subroutine script. +# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, +# 2000, 2001, 2002 Free Software Foundation, Inc. + +timestamp='2002-11-30' + +# This file is (in principle) common to ALL GNU software. +# The presence of a machine in this file suggests that SOME GNU software +# can handle that machine. It does not imply ALL GNU software can. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, +# Boston, MA 02111-1307, USA. + +# As a special exception to the GNU General Public License, if you +# distribute this file as part of a program that contains a +# configuration script generated by Autoconf, you may include it under +# the same distribution terms that you use for the rest of that program. + +# Please send patches to . Submit a context +# diff and a properly formatted ChangeLog entry. +# +# Configuration subroutine to validate and canonicalize a configuration type. +# Supply the specified configuration type as an argument. +# If it is invalid, we print an error message on stderr and exit with code 1. +# Otherwise, we print the canonical config type on stdout and succeed. + +# This file is supposed to be the same for all GNU packages +# and recognize all the CPU types, system types and aliases +# that are meaningful with *any* GNU software. +# Each package is responsible for reporting which valid configurations +# it does not support. The user should be able to distinguish +# a failure to support a valid configuration from a meaningless +# configuration. + +# The goal of this file is to map all the various variations of a given +# machine specification into a single specification in the form: +# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM +# or in some cases, the newer four-part form: +# CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM +# It is wrong to echo any other type of specification. + +me=`echo "$0" | sed -e 's,.*/,,'` + +usage="\ +Usage: $0 [OPTION] CPU-MFR-OPSYS + $0 [OPTION] ALIAS + +Canonicalize a configuration name. + +Operation modes: + -h, --help print this help, then exit + -t, --time-stamp print date of last modification, then exit + -v, --version print version number, then exit + +Report bugs and patches to ." + +version="\ +GNU config.sub ($timestamp) + +Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 +Free Software Foundation, Inc. + +This is free software; see the source for copying conditions. There is NO +warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." + +help=" +Try \`$me --help' for more information." + +# Parse command line +while test $# -gt 0 ; do + case $1 in + --time-stamp | --time* | -t ) + echo "$timestamp" ; exit 0 ;; + --version | -v ) + echo "$version" ; exit 0 ;; + --help | --h* | -h ) + echo "$usage"; exit 0 ;; + -- ) # Stop option processing + shift; break ;; + - ) # Use stdin as input. + break ;; + -* ) + echo "$me: invalid option $1$help" + exit 1 ;; + + *local*) + # First pass through any local machine types. + echo $1 + exit 0;; + + * ) + break ;; + esac +done + +case $# in + 0) echo "$me: missing argument$help" >&2 + exit 1;; + 1) ;; + *) echo "$me: too many arguments$help" >&2 + exit 1;; +esac + +# Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). +# Here we must recognize all the valid KERNEL-OS combinations. +maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` +case $maybe_os in + nto-qnx* | linux-gnu* | freebsd*-gnu* | netbsd*-gnu* | storm-chaos* | os2-emx* | rtmk-nova*) + os=-$maybe_os + basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` + ;; + *) + basic_machine=`echo $1 | sed 's/-[^-]*$//'` + if [ $basic_machine != $1 ] + then os=`echo $1 | sed 's/.*-/-/'` + else os=; fi + ;; +esac + +### Let's recognize common machines as not being operating systems so +### that things like config.sub decstation-3100 work. We also +### recognize some manufacturers as not being operating systems, so we +### can provide default operating systems below. +case $os in + -sun*os*) + # Prevent following clause from handling this invalid input. + ;; + -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ + -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ + -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ + -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ + -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ + -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ + -apple | -axis) + os= + basic_machine=$1 + ;; + -sim | -cisco | -oki | -wec | -winbond) + os= + basic_machine=$1 + ;; + -scout) + ;; + -wrs) + os=-vxworks + basic_machine=$1 + ;; + -chorusos*) + os=-chorusos + basic_machine=$1 + ;; + -chorusrdb) + os=-chorusrdb + basic_machine=$1 + ;; + -hiux*) + os=-hiuxwe2 + ;; + -sco5) + os=-sco3.2v5 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco4) + os=-sco3.2v4 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2.[4-9]*) + os=`echo $os | sed -e 's/sco3.2./sco3.2v/'` + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco3.2v[4-9]*) + # Don't forget version if it is 3.2v4 or newer. + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -sco*) + os=-sco3.2v2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -udk*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -isc) + os=-isc2.2 + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -clix*) + basic_machine=clipper-intergraph + ;; + -isc*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` + ;; + -lynx*) + os=-lynxos + ;; + -ptx*) + basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'` + ;; + -windowsnt*) + os=`echo $os | sed -e 's/windowsnt/winnt/'` + ;; + -psos*) + os=-psos + ;; + -mint | -mint[0-9]*) + basic_machine=m68k-atari + os=-mint + ;; +esac + +# Decode aliases for certain CPU-COMPANY combinations. +case $basic_machine in + # Recognize the basic CPU types without company name. + # Some are omitted here because they have special meanings below. + 1750a | 580 \ + | a29k \ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr \ + | clipper \ + | d10v | d30v | dlx | dsp16xx \ + | fr30 | frv \ + | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ + | i370 | i860 | i960 | ia64 \ + | ip2k \ + | m32r | m68000 | m68k | m88k | mcore \ + | mips | mipsbe | mipseb | mipsel | mipsle \ + | mips16 \ + | mips64 | mips64el \ + | mips64vr | mips64vrel \ + | mips64orion | mips64orionel \ + | mips64vr4100 | mips64vr4100el \ + | mips64vr4300 | mips64vr4300el \ + | mips64vr5000 | mips64vr5000el \ + | mipsisa32 | mipsisa32el \ + | mipsisa64 | mipsisa64el \ + | mipsisa64sb1 | mipsisa64sb1el \ + | mipsisa64sr71k | mipsisa64sr71kel \ + | mipstx39 | mipstx39el \ + | mn10200 | mn10300 \ + | ns16k | ns32k \ + | openrisc | or32 \ + | pdp10 | pdp11 | pj | pjl \ + | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ + | pyramid \ + | sh | sh[1234] | sh3e | sh[34]eb | shbe | shle | sh[1234]le | sh3ele \ + | sh64 | sh64le \ + | sparc | sparc64 | sparc86x | sparclet | sparclite | sparcv9 | sparcv9b \ + | strongarm \ + | tahoe | thumb | tic80 | tron \ + | v850 | v850e \ + | we32k \ + | x86 | xscale | xstormy16 | xtensa \ + | z8k) + basic_machine=$basic_machine-unknown + ;; + m6811 | m68hc11 | m6812 | m68hc12) + # Motorola 68HC11/12. + basic_machine=$basic_machine-unknown + os=-none + ;; + m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) + ;; + + # We use `pc' rather than `unknown' + # because (1) that's what they normally are, and + # (2) the word "unknown" tends to confuse beginning users. + i*86 | x86_64) + basic_machine=$basic_machine-pc + ;; + # Object if more than one company name word. + *-*-*) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; + # Recognize the basic CPU types with company name. + 580-* \ + | a29k-* \ + | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ + | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ + | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ + | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ + | avr-* \ + | bs2000-* \ + | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* \ + | clipper-* | cydra-* \ + | d10v-* | d30v-* | dlx-* \ + | elxsi-* \ + | f30[01]-* | f700-* | fr30-* | frv-* | fx80-* \ + | h8300-* | h8500-* \ + | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ + | i*86-* | i860-* | i960-* | ia64-* \ + | ip2k-* \ + | m32r-* \ + | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ + | m88110-* | m88k-* | mcore-* \ + | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ + | mips16-* \ + | mips64-* | mips64el-* \ + | mips64vr-* | mips64vrel-* \ + | mips64orion-* | mips64orionel-* \ + | mips64vr4100-* | mips64vr4100el-* \ + | mips64vr4300-* | mips64vr4300el-* \ + | mips64vr5000-* | mips64vr5000el-* \ + | mipsisa32-* | mipsisa32el-* \ + | mipsisa64-* | mipsisa64el-* \ + | mipsisa64sb1-* | mipsisa64sb1el-* \ + | mipsisa64sr71k-* | mipsisa64sr71kel-* \ + | mipstx39 | mipstx39el \ + | none-* | np1-* | ns16k-* | ns32k-* \ + | orion-* \ + | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ + | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ + | pyramid-* \ + | romp-* | rs6000-* \ + | sh-* | sh[1234]-* | sh3e-* | sh[34]eb-* | shbe-* \ + | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ + | sparc-* | sparc64-* | sparc86x-* | sparclet-* | sparclite-* \ + | sparcv9-* | sparcv9b-* | strongarm-* | sv1-* | sx?-* \ + | tahoe-* | thumb-* | tic30-* | tic4x-* | tic54x-* | tic80-* | tron-* \ + | v850-* | v850e-* | vax-* \ + | we32k-* \ + | x86-* | x86_64-* | xps100-* | xscale-* | xstormy16-* \ + | xtensa-* \ + | ymp-* \ + | z8k-*) + ;; + # Recognize the various machine names and aliases which stand + # for a CPU type and a company and sometimes even an OS. + 386bsd) + basic_machine=i386-unknown + os=-bsd + ;; + 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) + basic_machine=m68000-att + ;; + 3b*) + basic_machine=we32k-att + ;; + a29khif) + basic_machine=a29k-amd + os=-udi + ;; + adobe68k) + basic_machine=m68010-adobe + os=-scout + ;; + alliant | fx80) + basic_machine=fx80-alliant + ;; + altos | altos3068) + basic_machine=m68k-altos + ;; + am29k) + basic_machine=a29k-none + os=-bsd + ;; + amdahl) + basic_machine=580-amdahl + os=-sysv + ;; + amiga | amiga-*) + basic_machine=m68k-unknown + ;; + amigaos | amigados) + basic_machine=m68k-unknown + os=-amigaos + ;; + amigaunix | amix) + basic_machine=m68k-unknown + os=-sysv4 + ;; + apollo68) + basic_machine=m68k-apollo + os=-sysv + ;; + apollo68bsd) + basic_machine=m68k-apollo + os=-bsd + ;; + aux) + basic_machine=m68k-apple + os=-aux + ;; + balance) + basic_machine=ns32k-sequent + os=-dynix + ;; + c90) + basic_machine=c90-cray + os=-unicos + ;; + convex-c1) + basic_machine=c1-convex + os=-bsd + ;; + convex-c2) + basic_machine=c2-convex + os=-bsd + ;; + convex-c32) + basic_machine=c32-convex + os=-bsd + ;; + convex-c34) + basic_machine=c34-convex + os=-bsd + ;; + convex-c38) + basic_machine=c38-convex + os=-bsd + ;; + cray | j90) + basic_machine=j90-cray + os=-unicos + ;; + crds | unos) + basic_machine=m68k-crds + ;; + cris | cris-* | etrax*) + basic_machine=cris-axis + ;; + da30 | da30-*) + basic_machine=m68k-da30 + ;; + decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) + basic_machine=mips-dec + ;; + decsystem10* | dec10*) + basic_machine=pdp10-dec + os=-tops10 + ;; + decsystem20* | dec20*) + basic_machine=pdp10-dec + os=-tops20 + ;; + delta | 3300 | motorola-3300 | motorola-delta \ + | 3300-motorola | delta-motorola) + basic_machine=m68k-motorola + ;; + delta88) + basic_machine=m88k-motorola + os=-sysv3 + ;; + dpx20 | dpx20-*) + basic_machine=rs6000-bull + os=-bosx + ;; + dpx2* | dpx2*-bull) + basic_machine=m68k-bull + os=-sysv3 + ;; + ebmon29k) + basic_machine=a29k-amd + os=-ebmon + ;; + elxsi) + basic_machine=elxsi-elxsi + os=-bsd + ;; + encore | umax | mmax) + basic_machine=ns32k-encore + ;; + es1800 | OSE68k | ose68k | ose | OSE) + basic_machine=m68k-ericsson + os=-ose + ;; + fx2800) + basic_machine=i860-alliant + ;; + genix) + basic_machine=ns32k-ns + ;; + gmicro) + basic_machine=tron-gmicro + os=-sysv + ;; + go32) + basic_machine=i386-pc + os=-go32 + ;; + h3050r* | hiux*) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + h8300hms) + basic_machine=h8300-hitachi + os=-hms + ;; + h8300xray) + basic_machine=h8300-hitachi + os=-xray + ;; + h8500hms) + basic_machine=h8500-hitachi + os=-hms + ;; + harris) + basic_machine=m88k-harris + os=-sysv3 + ;; + hp300-*) + basic_machine=m68k-hp + ;; + hp300bsd) + basic_machine=m68k-hp + os=-bsd + ;; + hp300hpux) + basic_machine=m68k-hp + os=-hpux + ;; + hp3k9[0-9][0-9] | hp9[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hp9k2[0-9][0-9] | hp9k31[0-9]) + basic_machine=m68000-hp + ;; + hp9k3[2-9][0-9]) + basic_machine=m68k-hp + ;; + hp9k6[0-9][0-9] | hp6[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hp9k7[0-79][0-9] | hp7[0-79][0-9]) + basic_machine=hppa1.1-hp + ;; + hp9k78[0-9] | hp78[0-9]) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) + # FIXME: really hppa2.0-hp + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][13679] | hp8[0-9][13679]) + basic_machine=hppa1.1-hp + ;; + hp9k8[0-9][0-9] | hp8[0-9][0-9]) + basic_machine=hppa1.0-hp + ;; + hppa-next) + os=-nextstep3 + ;; + hppaosf) + basic_machine=hppa1.1-hp + os=-osf + ;; + hppro) + basic_machine=hppa1.1-hp + os=-proelf + ;; + i370-ibm* | ibm*) + basic_machine=i370-ibm + ;; +# I'm not sure what "Sysv32" means. Should this be sysv3.2? + i*86v32) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv32 + ;; + i*86v4*) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv4 + ;; + i*86v) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-sysv + ;; + i*86sol2) + basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` + os=-solaris2 + ;; + i386mach) + basic_machine=i386-mach + os=-mach + ;; + i386-vsta | vsta) + basic_machine=i386-unknown + os=-vsta + ;; + iris | iris4d) + basic_machine=mips-sgi + case $os in + -irix*) + ;; + *) + os=-irix4 + ;; + esac + ;; + isi68 | isi) + basic_machine=m68k-isi + os=-sysv + ;; + m88k-omron*) + basic_machine=m88k-omron + ;; + magnum | m3230) + basic_machine=mips-mips + os=-sysv + ;; + merlin) + basic_machine=ns32k-utek + os=-sysv + ;; + mingw32) + basic_machine=i386-pc + os=-mingw32 + ;; + miniframe) + basic_machine=m68000-convergent + ;; + *mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*) + basic_machine=m68k-atari + os=-mint + ;; + mips3*-*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` + ;; + mips3*) + basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown + ;; + mmix*) + basic_machine=mmix-knuth + os=-mmixware + ;; + monitor) + basic_machine=m68k-rom68k + os=-coff + ;; + morphos) + basic_machine=powerpc-unknown + os=-morphos + ;; + msdos) + basic_machine=i386-pc + os=-msdos + ;; + mvs) + basic_machine=i370-ibm + os=-mvs + ;; + ncr3000) + basic_machine=i486-ncr + os=-sysv4 + ;; + netbsd386) + basic_machine=i386-unknown + os=-netbsd + ;; + netwinder) + basic_machine=armv4l-rebel + os=-linux + ;; + news | news700 | news800 | news900) + basic_machine=m68k-sony + os=-newsos + ;; + news1000) + basic_machine=m68030-sony + os=-newsos + ;; + news-3600 | risc-news) + basic_machine=mips-sony + os=-newsos + ;; + necv70) + basic_machine=v70-nec + os=-sysv + ;; + next | m*-next ) + basic_machine=m68k-next + case $os in + -nextstep* ) + ;; + -ns2*) + os=-nextstep2 + ;; + *) + os=-nextstep3 + ;; + esac + ;; + nh3000) + basic_machine=m68k-harris + os=-cxux + ;; + nh[45]000) + basic_machine=m88k-harris + os=-cxux + ;; + nindy960) + basic_machine=i960-intel + os=-nindy + ;; + mon960) + basic_machine=i960-intel + os=-mon960 + ;; + nonstopux) + basic_machine=mips-compaq + os=-nonstopux + ;; + np1) + basic_machine=np1-gould + ;; + nsr-tandem) + basic_machine=nsr-tandem + ;; + op50n-* | op60c-*) + basic_machine=hppa1.1-oki + os=-proelf + ;; + or32 | or32-*) + basic_machine=or32-unknown + os=-coff + ;; + OSE68000 | ose68000) + basic_machine=m68000-ericsson + os=-ose + ;; + os68k) + basic_machine=m68k-none + os=-os68k + ;; + pa-hitachi) + basic_machine=hppa1.1-hitachi + os=-hiuxwe2 + ;; + paragon) + basic_machine=i860-intel + os=-osf + ;; + pbd) + basic_machine=sparc-tti + ;; + pbb) + basic_machine=m68k-tti + ;; + pc532 | pc532-*) + basic_machine=ns32k-pc532 + ;; + pentium | p5 | k5 | k6 | nexgen | viac3) + basic_machine=i586-pc + ;; + pentiumpro | p6 | 6x86 | athlon | athlon_*) + basic_machine=i686-pc + ;; + pentiumii | pentium2) + basic_machine=i686-pc + ;; + pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) + basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumpro-* | p6-* | 6x86-* | athlon-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pentiumii-* | pentium2-*) + basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + pn) + basic_machine=pn-gould + ;; + power) basic_machine=power-ibm + ;; + ppc) basic_machine=powerpc-unknown + ;; + ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppcle | powerpclittle | ppc-le | powerpc-little) + basic_machine=powerpcle-unknown + ;; + ppcle-* | powerpclittle-*) + basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppc64) basic_machine=powerpc64-unknown + ;; + ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ppc64le | powerpc64little | ppc64-le | powerpc64-little) + basic_machine=powerpc64le-unknown + ;; + ppc64le-* | powerpc64little-*) + basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` + ;; + ps2) + basic_machine=i386-ibm + ;; + pw32) + basic_machine=i586-unknown + os=-pw32 + ;; + rom68k) + basic_machine=m68k-rom68k + os=-coff + ;; + rm[46]00) + basic_machine=mips-siemens + ;; + rtpc | rtpc-*) + basic_machine=romp-ibm + ;; + s390 | s390-*) + basic_machine=s390-ibm + ;; + s390x | s390x-*) + basic_machine=s390x-ibm + ;; + sa29200) + basic_machine=a29k-amd + os=-udi + ;; + sb1) + basic_machine=mipsisa64sb1-unknown + ;; + sb1el) + basic_machine=mipsisa64sb1el-unknown + ;; + sequent) + basic_machine=i386-sequent + ;; + sh) + basic_machine=sh-hitachi + os=-hms + ;; + sparclite-wrs | simso-wrs) + basic_machine=sparclite-wrs + os=-vxworks + ;; + sps7) + basic_machine=m68k-bull + os=-sysv2 + ;; + spur) + basic_machine=spur-unknown + ;; + st2000) + basic_machine=m68k-tandem + ;; + stratus) + basic_machine=i860-stratus + os=-sysv4 + ;; + sun2) + basic_machine=m68000-sun + ;; + sun2os3) + basic_machine=m68000-sun + os=-sunos3 + ;; + sun2os4) + basic_machine=m68000-sun + os=-sunos4 + ;; + sun3os3) + basic_machine=m68k-sun + os=-sunos3 + ;; + sun3os4) + basic_machine=m68k-sun + os=-sunos4 + ;; + sun4os3) + basic_machine=sparc-sun + os=-sunos3 + ;; + sun4os4) + basic_machine=sparc-sun + os=-sunos4 + ;; + sun4sol2) + basic_machine=sparc-sun + os=-solaris2 + ;; + sun3 | sun3-*) + basic_machine=m68k-sun + ;; + sun4) + basic_machine=sparc-sun + ;; + sun386 | sun386i | roadrunner) + basic_machine=i386-sun + ;; + sv1) + basic_machine=sv1-cray + os=-unicos + ;; + symmetry) + basic_machine=i386-sequent + os=-dynix + ;; + t3d) + basic_machine=alpha-cray + os=-unicos + ;; + t3e) + basic_machine=alphaev5-cray + os=-unicos + ;; + t90) + basic_machine=t90-cray + os=-unicos + ;; + tic4x | c4x*) + basic_machine=tic4x-unknown + os=-coff + ;; + tic54x | c54x*) + basic_machine=tic54x-unknown + os=-coff + ;; + tx39) + basic_machine=mipstx39-unknown + ;; + tx39el) + basic_machine=mipstx39el-unknown + ;; + toad1) + basic_machine=pdp10-xkl + os=-tops20 + ;; + tower | tower-32) + basic_machine=m68k-ncr + ;; + udi29k) + basic_machine=a29k-amd + os=-udi + ;; + ultra3) + basic_machine=a29k-nyu + os=-sym1 + ;; + v810 | necv810) + basic_machine=v810-nec + os=-none + ;; + vaxv) + basic_machine=vax-dec + os=-sysv + ;; + vms) + basic_machine=vax-dec + os=-vms + ;; + vpp*|vx|vx-*) + basic_machine=f301-fujitsu + ;; + vxworks960) + basic_machine=i960-wrs + os=-vxworks + ;; + vxworks68) + basic_machine=m68k-wrs + os=-vxworks + ;; + vxworks29k) + basic_machine=a29k-wrs + os=-vxworks + ;; + w65*) + basic_machine=w65-wdc + os=-none + ;; + w89k-*) + basic_machine=hppa1.1-winbond + os=-proelf + ;; + xps | xps100) + basic_machine=xps100-honeywell + ;; + ymp) + basic_machine=ymp-cray + os=-unicos + ;; + z8k-*-coff) + basic_machine=z8k-unknown + os=-sim + ;; + none) + basic_machine=none-none + os=-none + ;; + +# Here we handle the default manufacturer of certain CPU types. It is in +# some cases the only manufacturer, in others, it is the most popular. + w89k) + basic_machine=hppa1.1-winbond + ;; + op50n) + basic_machine=hppa1.1-oki + ;; + op60c) + basic_machine=hppa1.1-oki + ;; + romp) + basic_machine=romp-ibm + ;; + rs6000) + basic_machine=rs6000-ibm + ;; + vax) + basic_machine=vax-dec + ;; + pdp10) + # there are many clones, so DEC is not a safe bet + basic_machine=pdp10-unknown + ;; + pdp11) + basic_machine=pdp11-dec + ;; + we32k) + basic_machine=we32k-att + ;; + sh3 | sh4 | sh3eb | sh4eb | sh[1234]le | sh3ele) + basic_machine=sh-unknown + ;; + sh64) + basic_machine=sh64-unknown + ;; + sparc | sparcv9 | sparcv9b) + basic_machine=sparc-sun + ;; + cydra) + basic_machine=cydra-cydrome + ;; + orion) + basic_machine=orion-highlevel + ;; + orion105) + basic_machine=clipper-highlevel + ;; + mac | mpw | mac-mpw) + basic_machine=m68k-apple + ;; + pmac | pmac-mpw) + basic_machine=powerpc-apple + ;; + *-unknown) + # Make sure to match an already-canonicalized machine name. + ;; + *) + echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 + exit 1 + ;; +esac + +# Here we canonicalize certain aliases for manufacturers. +case $basic_machine in + *-digital*) + basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` + ;; + *-commodore*) + basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` + ;; + *) + ;; +esac + +# Decode manufacturer-specific aliases for certain operating systems. + +if [ x"$os" != x"" ] +then +case $os in + # First match some system type aliases + # that might get confused with valid system types. + # -solaris* is a basic system type, with this one exception. + -solaris1 | -solaris1.*) + os=`echo $os | sed -e 's|solaris1|sunos4|'` + ;; + -solaris) + os=-solaris2 + ;; + -svr4*) + os=-sysv4 + ;; + -unixware*) + os=-sysv4.2uw + ;; + -gnu/linux*) + os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` + ;; + # First accept the basic system types. + # The portable systems comes first. + # Each alternative MUST END IN A *, to match a version number. + # -sysv* is not here because it comes later, after sysvr4. + -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ + | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ + | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ + | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ + | -aos* \ + | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ + | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ + | -hiux* | -386bsd* | -netbsd* | -openbsd* | -freebsd* | -riscix* \ + | -lynxos* | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ + | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ + | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ + | -chorusos* | -chorusrdb* \ + | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ + | -mingw32* | -linux-gnu* | -uxpv* | -beos* | -mpeix* | -udk* \ + | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ + | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ + | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \ + | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ + | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ + | -powermax* | -dnix*) + # Remember, each alternative MUST END IN *, to match a version number. + ;; + -qnx*) + case $basic_machine in + x86-* | i*86-*) + ;; + *) + os=-nto$os + ;; + esac + ;; + -nto-qnx*) + ;; + -nto*) + os=`echo $os | sed -e 's|nto|nto-qnx|'` + ;; + -sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \ + | -windows* | -osx | -abug | -netware* | -os9* | -beos* \ + | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*) + ;; + -mac*) + os=`echo $os | sed -e 's|mac|macos|'` + ;; + -linux*) + os=`echo $os | sed -e 's|linux|linux-gnu|'` + ;; + -sunos5*) + os=`echo $os | sed -e 's|sunos5|solaris2|'` + ;; + -sunos6*) + os=`echo $os | sed -e 's|sunos6|solaris3|'` + ;; + -opened*) + os=-openedition + ;; + -wince*) + os=-wince + ;; + -osfrose*) + os=-osfrose + ;; + -osf*) + os=-osf + ;; + -utek*) + os=-bsd + ;; + -dynix*) + os=-bsd + ;; + -acis*) + os=-aos + ;; + -atheos*) + os=-atheos + ;; + -386bsd) + os=-bsd + ;; + -ctix* | -uts*) + os=-sysv + ;; + -nova*) + os=-rtmk-nova + ;; + -ns2 ) + os=-nextstep2 + ;; + -nsk*) + os=-nsk + ;; + # Preserve the version number of sinix5. + -sinix5.*) + os=`echo $os | sed -e 's|sinix|sysv|'` + ;; + -sinix*) + os=-sysv4 + ;; + -triton*) + os=-sysv3 + ;; + -oss*) + os=-sysv3 + ;; + -svr4) + os=-sysv4 + ;; + -svr3) + os=-sysv3 + ;; + -sysvr4) + os=-sysv4 + ;; + # This must come after -sysvr4. + -sysv*) + ;; + -ose*) + os=-ose + ;; + -es1800*) + os=-ose + ;; + -xenix) + os=-xenix + ;; + -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) + os=-mint + ;; + -none) + ;; + *) + # Get rid of the `-' at the beginning of $os. + os=`echo $os | sed 's/[^-]*-//'` + echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2 + exit 1 + ;; +esac +else + +# Here we handle the default operating systems that come with various machines. +# The value should be what the vendor currently ships out the door with their +# machine or put another way, the most popular os provided with the machine. + +# Note that if you're going to try to match "-MANUFACTURER" here (say, +# "-sun"), then you have to tell the case statement up towards the top +# that MANUFACTURER isn't an operating system. Otherwise, code above +# will signal an error saying that MANUFACTURER isn't an operating +# system, and we'll never get to this point. + +case $basic_machine in + *-acorn) + os=-riscix1.2 + ;; + arm*-rebel) + os=-linux + ;; + arm*-semi) + os=-aout + ;; + # This must come before the *-dec entry. + pdp10-*) + os=-tops20 + ;; + pdp11-*) + os=-none + ;; + *-dec | vax-*) + os=-ultrix4.2 + ;; + m68*-apollo) + os=-domain + ;; + i386-sun) + os=-sunos4.0.2 + ;; + m68000-sun) + os=-sunos3 + # This also exists in the configure program, but was not the + # default. + # os=-sunos4 + ;; + m68*-cisco) + os=-aout + ;; + mips*-cisco) + os=-elf + ;; + mips*-*) + os=-elf + ;; + or32-*) + os=-coff + ;; + *-tti) # must be before sparc entry or we get the wrong os. + os=-sysv3 + ;; + sparc-* | *-sun) + os=-sunos4.1.1 + ;; + *-be) + os=-beos + ;; + *-ibm) + os=-aix + ;; + *-wec) + os=-proelf + ;; + *-winbond) + os=-proelf + ;; + *-oki) + os=-proelf + ;; + *-hp) + os=-hpux + ;; + *-hitachi) + os=-hiux + ;; + i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) + os=-sysv + ;; + *-cbm) + os=-amigaos + ;; + *-dg) + os=-dgux + ;; + *-dolphin) + os=-sysv3 + ;; + m68k-ccur) + os=-rtu + ;; + m88k-omron*) + os=-luna + ;; + *-next ) + os=-nextstep + ;; + *-sequent) + os=-ptx + ;; + *-crds) + os=-unos + ;; + *-ns) + os=-genix + ;; + i370-*) + os=-mvs + ;; + *-next) + os=-nextstep3 + ;; + *-gould) + os=-sysv + ;; + *-highlevel) + os=-bsd + ;; + *-encore) + os=-bsd + ;; + *-sgi) + os=-irix + ;; + *-siemens) + os=-sysv4 + ;; + *-masscomp) + os=-rtu + ;; + f30[01]-fujitsu | f700-fujitsu) + os=-uxpv + ;; + *-rom68k) + os=-coff + ;; + *-*bug) + os=-coff + ;; + *-apple) + os=-macos + ;; + *-atari*) + os=-mint + ;; + *) + os=-none + ;; +esac +fi + +# Here we handle the case where we know the os, and the CPU type, but not the +# manufacturer. We pick the logical manufacturer. +vendor=unknown +case $basic_machine in + *-unknown) + case $os in + -riscix*) + vendor=acorn + ;; + -sunos*) + vendor=sun + ;; + -aix*) + vendor=ibm + ;; + -beos*) + vendor=be + ;; + -hpux*) + vendor=hp + ;; + -mpeix*) + vendor=hp + ;; + -hiux*) + vendor=hitachi + ;; + -unos*) + vendor=crds + ;; + -dgux*) + vendor=dg + ;; + -luna*) + vendor=omron + ;; + -genix*) + vendor=ns + ;; + -mvs* | -opened*) + vendor=ibm + ;; + -ptx*) + vendor=sequent + ;; + -vxsim* | -vxworks* | -windiss*) + vendor=wrs + ;; + -aux*) + vendor=apple + ;; + -hms*) + vendor=hitachi + ;; + -mpw* | -macos*) + vendor=apple + ;; + -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) + vendor=atari + ;; + -vos*) + vendor=stratus + ;; + esac + basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"` + ;; +esac + +echo $basic_machine$os +exit 0 + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "timestamp='" +# time-stamp-format: "%:y-%02m-%02d" +# time-stamp-end: "'" +# End: Index: vis_dev/vis-2.1/helpers/dependency.make =================================================================== --- vis_dev/vis-2.1/helpers/dependency.make (revision 11) +++ vis_dev/vis-2.1/helpers/dependency.make (revision 11) @@ -0,0 +1,32 @@ +# FileName [dependency.make] +# +# PackageName [vis] +# +# Synopsis [Makefile to automatically create the dependency files.] +# +# Description [This file is called from the main Makefile.] +# +# SeeAlso [Makefile.in] +# +# Author [Abelardo Pardo ] +# +# Copyright [This file was created at the University of Colorado at Boulder. +# The University of Colorado at Boulder makes no warranty about the suitability +# of this software for any purpose. It is presented on an AS IS basis.] +# +# Revision [$Id: dependency.make,v 1.3 1998/09/18 18:30:23 hsv Exp $] + +include $(PKGNAME).make + +ifdef DEPENDENCYFILES +$(PKGNAME).d : $(DEPENDENCYFILES) $(HEADERS) $(PKGNAME).make + @echo -n "Dependency file $(PKGNAME).d->" + @$(CC) -MM $(CFLAGS) $(AC_FLAGS) $(INCLUDEDIRS) \ + $(filter %.c, $^) | \ + sed 's/^[a-zA-Z0-9_]*\.o[ :]*/$(objectdir)\/&/g' > $@ + @echo "Created." +else +$(PKGNAME).d : + @echo "No dependency files given in $(PKGNAME).make" + @echo "Define the variable DEPENDENCYFILES to create the dependencies" +endif Index: vis_dev/vis-2.1/helpers/install-sh =================================================================== --- vis_dev/vis-2.1/helpers/install-sh (revision 11) +++ vis_dev/vis-2.1/helpers/install-sh (revision 11) @@ -0,0 +1,276 @@ +#!/bin/sh +# +# install - install a program, script, or datafile +# This comes from X11R5 (mit/util/scripts/install.sh). +# +# Copyright 1991 by the Massachusetts Institute of Technology +# +# Permission to use, copy, modify, distribute, and sell this software and its +# documentation for any purpose is hereby granted without fee, provided that +# the above copyright notice appear in all copies and that both that +# copyright notice and this permission notice appear in supporting +# documentation, and that the name of M.I.T. not be used in advertising or +# publicity pertaining to distribution of the software without specific, +# written prior permission. M.I.T. makes no representations about the +# suitability of this software for any purpose. It is provided "as is" +# without express or implied warranty. +# +# Calling this script install-sh is preferred over install.sh, to prevent +# `make' implicit rules from creating a file called install from it +# when there is no Makefile. +# +# This script is compatible with the BSD install script, but was written +# from scratch. It can only install one file at a time, a restriction +# shared with many OS's install programs. + + +# set DOITPROG to echo to test this script + +# Don't use :- since 4.3BSD and earlier shells don't like it. +doit="${DOITPROG-}" + + +# put in absolute paths if you don't have them in your path; or use env. vars. + +mvprog="${MVPROG-mv}" +cpprog="${CPPROG-cp}" +chmodprog="${CHMODPROG-chmod}" +chownprog="${CHOWNPROG-chown}" +chgrpprog="${CHGRPPROG-chgrp}" +stripprog="${STRIPPROG-strip}" +rmprog="${RMPROG-rm}" +mkdirprog="${MKDIRPROG-mkdir}" + +transformbasename="" +transform_arg="" +instcmd="$mvprog" +chmodcmd="$chmodprog 0755" +chowncmd="" +chgrpcmd="" +stripcmd="" +rmcmd="$rmprog -f" +mvcmd="$mvprog" +src="" +dst="" +dir_arg="" + +while [ x"$1" != x ]; do + case $1 in + -c) instcmd=$cpprog + shift + continue;; + + -d) dir_arg=true + shift + continue;; + + -m) chmodcmd="$chmodprog $2" + shift + shift + continue;; + + -o) chowncmd="$chownprog $2" + shift + shift + continue;; + + -g) chgrpcmd="$chgrpprog $2" + shift + shift + continue;; + + -s) stripcmd=$stripprog + shift + continue;; + + -t=*) transformarg=`echo $1 | sed 's/-t=//'` + shift + continue;; + + -b=*) transformbasename=`echo $1 | sed 's/-b=//'` + shift + continue;; + + *) if [ x"$src" = x ] + then + src=$1 + else + # this colon is to work around a 386BSD /bin/sh bug + : + dst=$1 + fi + shift + continue;; + esac +done + +if [ x"$src" = x ] +then + echo "$0: no input file specified" >&2 + exit 1 +else + : +fi + +if [ x"$dir_arg" != x ]; then + dst=$src + src="" + + if [ -d "$dst" ]; then + instcmd=: + chmodcmd="" + else + instcmd=$mkdirprog + fi +else + +# Waiting for this to be detected by the "$instcmd $src $dsttmp" command +# might cause directories to be created, which would be especially bad +# if $src (and thus $dsttmp) contains '*'. + + if [ -f "$src" ] || [ -d "$src" ] + then + : + else + echo "$0: $src does not exist" >&2 + exit 1 + fi + + if [ x"$dst" = x ] + then + echo "$0: no destination specified" >&2 + exit 1 + else + : + fi + +# If destination is a directory, append the input filename; if your system +# does not like double slashes in filenames, you may need to add some logic + + if [ -d "$dst" ] + then + dst=$dst/`basename "$src"` + else + : + fi +fi + +## this sed command emulates the dirname command +dstdir=`echo "$dst" | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'` + +# Make sure that the destination directory exists. +# this part is taken from Noah Friedman's mkinstalldirs script + +# Skip lots of stat calls in the usual case. +if [ ! -d "$dstdir" ]; then +defaultIFS=' + ' +IFS="${IFS-$defaultIFS}" + +oIFS=$IFS +# Some sh's can't handle IFS=/ for some reason. +IFS='%' +set - `echo "$dstdir" | sed -e 's@/@%@g' -e 's@^%@/@'` +IFS=$oIFS + +pathcomp='' + +while [ $# -ne 0 ] ; do + pathcomp=$pathcomp$1 + shift + + if [ ! -d "$pathcomp" ] ; + then + $mkdirprog "$pathcomp" + else + : + fi + + pathcomp=$pathcomp/ +done +fi + +if [ x"$dir_arg" != x ] +then + $doit $instcmd "$dst" && + + if [ x"$chowncmd" != x ]; then $doit $chowncmd "$dst"; else : ; fi && + if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd "$dst"; else : ; fi && + if [ x"$stripcmd" != x ]; then $doit $stripcmd "$dst"; else : ; fi && + if [ x"$chmodcmd" != x ]; then $doit $chmodcmd "$dst"; else : ; fi +else + +# If we're going to rename the final executable, determine the name now. + + if [ x"$transformarg" = x ] + then + dstfile=`basename "$dst"` + else + dstfile=`basename "$dst" $transformbasename | + sed $transformarg`$transformbasename + fi + +# don't allow the sed command to completely eliminate the filename + + if [ x"$dstfile" = x ] + then + dstfile=`basename "$dst"` + else + : + fi + +# Make a couple of temp file names in the proper directory. + + dsttmp=$dstdir/#inst.$$# + rmtmp=$dstdir/#rm.$$# + +# Trap to clean up temp files at exit. + + trap 'status=$?; rm -f "$dsttmp" "$rmtmp" && exit $status' 0 + trap '(exit $?); exit' 1 2 13 15 + +# Move or copy the file name to the temp name + + $doit $instcmd "$src" "$dsttmp" && + +# and set any options; do chmod last to preserve setuid bits + +# If any of these fail, we abort the whole thing. If we want to +# ignore errors from any of these, just make sure not to ignore +# errors from the above "$doit $instcmd $src $dsttmp" command. + + if [ x"$chowncmd" != x ]; then $doit $chowncmd "$dsttmp"; else :;fi && + if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd "$dsttmp"; else :;fi && + if [ x"$stripcmd" != x ]; then $doit $stripcmd "$dsttmp"; else :;fi && + if [ x"$chmodcmd" != x ]; then $doit $chmodcmd "$dsttmp"; else :;fi && + +# Now remove or move aside any old file at destination location. We try this +# two ways since rm can't unlink itself on some systems and the destination +# file might be busy for other reasons. In this case, the final cleanup +# might fail but the new file should still install successfully. + +{ + if [ -f "$dstdir/$dstfile" ] + then + $doit $rmcmd -f "$dstdir/$dstfile" 2>/dev/null || + $doit $mvcmd -f "$dstdir/$dstfile" "$rmtmp" 2>/dev/null || + { + echo "$0: cannot unlink or rename $dstdir/$dstfile" >&2 + (exit 1); exit + } + else + : + fi +} && + +# Now rename the file to the real destination. + + $doit $mvcmd "$dsttmp" "$dstdir/$dstfile" + +fi && + +# The final little trick to "correctly" pass the exit status to the exit trap. + +{ + (exit 0); exit +} Index: vis_dev/vis-2.1/helpers/mkinstalldirs =================================================================== --- vis_dev/vis-2.1/helpers/mkinstalldirs (revision 11) +++ vis_dev/vis-2.1/helpers/mkinstalldirs (revision 11) @@ -0,0 +1,111 @@ +#! /bin/sh +# mkinstalldirs --- make directory hierarchy +# Author: Noah Friedman +# Created: 1993-05-16 +# Public domain + +errstatus=0 +dirmode="" + +usage="\ +Usage: mkinstalldirs [-h] [--help] [-m mode] dir ..." + +# process command line arguments +while test $# -gt 0 ; do + case $1 in + -h | --help | --h*) # -h for help + echo "$usage" 1>&2 + exit 0 + ;; + -m) # -m PERM arg + shift + test $# -eq 0 && { echo "$usage" 1>&2; exit 1; } + dirmode=$1 + shift + ;; + --) # stop option processing + shift + break + ;; + -*) # unknown option + echo "$usage" 1>&2 + exit 1 + ;; + *) # first non-opt arg + break + ;; + esac +done + +for file +do + if test -d "$file"; then + shift + else + break + fi +done + +case $# in + 0) exit 0 ;; +esac + +case $dirmode in + '') + if mkdir -p -- . 2>/dev/null; then + echo "mkdir -p -- $*" + exec mkdir -p -- "$@" + fi + ;; + *) + if mkdir -m "$dirmode" -p -- . 2>/dev/null; then + echo "mkdir -m $dirmode -p -- $*" + exec mkdir -m "$dirmode" -p -- "$@" + fi + ;; +esac + +for file +do + set fnord `echo ":$file" | sed -ne 's/^:\//#/;s/^://;s/\// /g;s/^#/\//;p'` + shift + + pathcomp= + for d + do + pathcomp="$pathcomp$d" + case $pathcomp in + -*) pathcomp=./$pathcomp ;; + esac + + if test ! -d "$pathcomp"; then + echo "mkdir $pathcomp" + + mkdir "$pathcomp" || lasterr=$? + + if test ! -d "$pathcomp"; then + errstatus=$lasterr + else + if test ! -z "$dirmode"; then + echo "chmod $dirmode $pathcomp" + lasterr="" + chmod "$dirmode" "$pathcomp" || lasterr=$? + + if test ! -z "$lasterr"; then + errstatus=$lasterr + fi + fi + fi + fi + + pathcomp="$pathcomp/" + done +done + +exit $errstatus + +# Local Variables: +# mode: shell-script +# sh-indentation: 2 +# End: +# mkinstalldirs ends here Index: vis_dev/vis-2.1/man/man1/vis.1 =================================================================== --- vis_dev/vis-2.1/man/man1/vis.1 (revision 11) +++ vis_dev/vis-2.1/man/man1/vis.1 (revision 11) @@ -0,0 +1,121 @@ +.\" $Id: vis.1,v 1.3 2001/04/13 20:45:04 rbloem Exp $ +.\" +.TH vis 1 "April 11, 2001" "Release 1.4" +.LO 1 +.SH NAME +Vis \- Verification Interacting with Synthesis +.SH SYNOPSIS +.B vis +[\-c cmd] [\-f +.I script +] [\-h] [\-o +.I file +] [\-s] [\-t type] [\-T type] [\-x] [ +.I file +] +.SH DESCRIPTION +.B Vis +is a system for formal verification, synthesis, and simulation of finite state +systems. It has been developed jointly at the University of California at +Berkeley and the University of Colorado at Boulder. +.PP +Vis is primarily used interactively, using a prompt system. Most help on its +commands is given within vis: type +.B help +at the vis command prompt. The +.I examples +directory gives some examples of how +to use vis. The definitive documentation resides at the Vis Home Page. This +man page concentrates on the command options. +.PP +Vis works interactively if invoked without any options. Vis can also be called +in batch mode, using +.B -c +or +.B -f. +In this case, either +.B -x +needs to be specified, or the last argument needs to denote a file. +.PP +The case in which +.B -x +is not specified is only used in practice for synthesis. +.I File +is read before the script is executed, and after execution another file is +written. The details are determined by the +.B -t, -T, +and +.B -o +flags. It is probably easier to incorporate the reading and writing +of the file in the script. +.SH OPTIONS +.TP +.B \-\^c cmd + Execute VIS commands `cmd'. +.TP +.BR "\-\^f " file +Execute script containing vis commands +.TP +.B \-\^h +Print the command usage +.TP +.BR "-\^o " file +Specify output filename (default is -) +.TP +.B \-\^s +Do not read any initialization file. If not specified, the files +.I $VIS_LIBRARY_PATH/master.visrc, +and +.I $HOME/.visrc +are executed in that order. +.TP +.B \-\^t type + specify input type (blif_mv (default), blif, or none) +.TP +.B \-\^x +Equivalent to '-t none -T none' +.\" +.SH EXAMPLES +.TP +.B vis\^ +Calls vis interactively +.TP +.BI "vis -x -f " file\^ +Executes the named vis script. +.\" +.SH FILES +The scripts +.I $VIS_LIBRARY_PATH/master.visrc, +and +.I $HOME/.visrc +are read in that order before any other script executes. They are used to +define aliases and the like. +.\" +.SH ENVIRONMENT +.B $VIS_LIBRARY_PATH +determines the location of the master visrc file and the help files. +.\" +.SH NOTES +Vis will produce line-buffered output if you set vis_stdout and +vis_stderr from the vis prompt. In any case, you can force vis to +flush the output by sending it a USR1 signal, using kill. +.\" +.SH BUGS +For optimum performance, set the +.B datasize limit +to a reasonable size (such as something less than the amount of RAM +you have). +.\" +.SH "SEE ALSO" +The Vis Home Page: +.UR http://vlsi.colorado.edu/~vis +http://vlsi.colorado.edu/~vis +.UE +.PP +R. K. Brayton et al, +.I VIS: A system for verification and synthesis, +Eighth Conference on Computer Aided Verification (CAV'96), pp. 428-432, 1996. +.PP +.BR limit (1), +.BR kill(1). + Index: vis_dev/vis-2.1/script.vis =================================================================== --- vis_dev/vis-2.1/script.vis (revision 11) +++ vis_dev/vis-2.1/script.vis (revision 11) @@ -0,0 +1,2 @@ +rlmv models/atm/ATM-arch.mv +init Index: vis_dev/vis-2.1/semantic.cache =================================================================== --- vis_dev/vis-2.1/semantic.cache (revision 11) +++ vis_dev/vis-2.1/semantic.cache (revision 11) @@ -0,0 +1,25 @@ +;; Object vis-2.1/ +;; SEMANTICDB Tags save file +(semanticdb-project-database-file "vis-2.1/" + :tables (list + (semanticdb-table "Makefile" + :major-mode 'makefile-gmake-mode + :tags '((".PHONY" function (:arguments ("default")) nil [1694 1712]) ("default" function (:arguments ("all")) nil [1712 1727]) ("PKGS" variable (:default-value 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nil [33550 33701]) (".PHONY" function (:arguments ("rcs_ci_misc" "rcs_co_misc" "rcs_diff_misc")) nil [33960 34008]) ("rcs_ci_misc" function (:arguments ("$(RCSMISCFILES)")) nil [34079 34318]) ("rcs_co_misc" function (:arguments ("$(RCSMISCFILES)")) nil [34367 34534]) ("rcs_diff_misc" function (:arguments ("$(RCSMISCFILES)")) nil [34597 34768]) ("rcs_ident_misc" function (:arguments ("$(RCSMISCFILES)")) nil [34813 34959]) ("rcs_status_misc" function (:arguments ("$(RCSMISCFILES)")) nil [35022 35182]) (".PHONY" function (:arguments ("rcs_ci_share" "rcs_co_share" "rcs_diff_share")) nil [35365 35416]) ("rcs_ci_share" function (:arguments ("$(RCSSHAREFILES)")) nil [35475 35716]) ("rcs_co_share" function (:arguments ("$(RCSSHAREFILES)")) nil [35758 35927]) ("rcs_diff_share" function (:arguments ("$(RCSSHAREFILES)")) nil [35983 36156]) ("rcs_ident_share" function (:arguments ("$(RCSSHAREFILES)")) nil [36202 36350]) ("rcs_status_share" function (:arguments ("$(RCSSHAREFILES)")) nil [36414 36576]) (".PHONY" function (:arguments ("debug-make")) nil [36756 36777]) ("DEBUG_VARS" variable (:default-value ("ALL_PKGS" "PKGS" "MISSING_PKGS" "VPATH" "INCLUDEDIRS" "CSRC" "OBJECTS" "HEADERS" "MAKEINCLUDES" "CFLAGS" "AC_FLAGS" "master_srcdir" "local_srcdir" "RCSFILES" "RCSDIR" "LIBS" "VISLIBS" "DISTFILES" "EXAMPLEFILES")) nil [36777 37037]) ("debug-make" function nil nil [37094 37164])) + :file "Makefile" + :pointmax 37164 + ) + ) + :file "semantic.cache" + :semantic-tag-version "2.0beta3" + :semanticdb-version "2.0beta3" + ) Index: vis_dev/vis-2.1/share/createfunctionmap =================================================================== --- vis_dev/vis-2.1/share/createfunctionmap (revision 11) +++ vis_dev/vis-2.1/share/createfunctionmap (revision 11) @@ -0,0 +1,98 @@ +#!/usr/local/bin/perl +# +# Script to process the output of purify in terms of memory use. +# +# Abelardo Pardo +# +# Revision [$Id: createfunctionmap,v 1.4 1996/12/18 23:43:46 hsv Exp $] + +require 5.001; +use Getopt::Long; + +# Define default variables +# +$version = 1.3; + +# Initialize the different options +# +$opt_h = 0; +$opt_v = 0; + +# Read the options +# +$optionResult = GetOptions("h","v"); + +# Print the version if required +# +if ($opt_v) { + print < +ENDOFMESSAGE + exit; +} + +# Print the help message if required +# +if ($opt_h || !$optionResult) { + print < + +Options: + -h Print this message + -v Print the version + +Author: Abelardo Pardo + +ENDOFMESSAGE + exit; +} + +# Open the input files +# +foreach $filename (@ARGV) { + + if (open(INPUT, $filename)) { + + $indefinition = 0; + while() { + chop; + + if (/FileName\s+\[\s*(.+)\s*\]/) { + $cfilename = $1; + } + if (/PackageName\s+\[\s*(.+)\s*\]/) { + $pkgname = $1; + } + if (/^\/\*\*AutomaticStart\*+\/$/) { + $indefinition = 1; + } + if (/^\/\*\*AutomaticEnd\*+\/$/) { + $indefinition = 0; + } + + if ($indefinition == 1) { + if (/static\s*.*\s+([a-zA-Z0-9_]+\(.*\))/) { + $function = $1; + $function =~ /([a-zA-Z0-9_]+)\(.*\)/; + print "$pkgname $cfilename $1\n"; + } + } + } + close(INPUT); + } + else { + print "Unable to open $filename. Ignoring it.\n"; + } +} + +exit; Index: vis_dev/vis-2.1/share/help/Cmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/Cmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/Cmd.txt (revision 11) @@ -0,0 +1,6 @@ + + - + _________________________________________________________________ + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/_ctlp_testCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/_ctlp_testCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/_ctlp_testCmd.txt (revision 11) @@ -0,0 +1,29 @@ + + _ctlp_test - test the CTL parser + _________________________________________________________________ + + _ctlp_test [-h] + + Test the CTL parser. If the entire file of CTL formulas is + successfully parsed, then each formula is printed to stdout, followed + by the equivalent existential normal form formula. The formulas read + are not stored. For the input file containing: + AG(foo=bar); + + the following is produced: + original + formula: AG(foo=bar) => equivalent existential formula: !(E(TRUE U + !(foo=bar))) + + For the syntax of CTL formulas, refer to [1]the VIS CTL and LTL syntax + manual. Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/ctl/ctl/ctl.html Index: vis_dev/vis-2.1/share/help/_ctlsp_testCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/_ctlsp_testCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/_ctlsp_testCmd.txt (revision 11) @@ -0,0 +1,29 @@ + + _ctlsp_test - test the CTL* parser + _________________________________________________________________ + + _ctlsp_test [-h] + + Test the CTL* parser. If the entire file of CTL* formulas is + successfully parsed, then each formula is printed to stdout, followed + by the equivalent existential normal form formula. The formulas read + are not stored. For the input file containing: + AG(foo=bar); + + the following is produced: + original + formula: AG(foo=bar) => equivalent existential formula: !(E(TRUE U + !(foo=bar))) + + For the syntax of CTL formulas, refer to [1]the VIS CTL and LTL syntax + manual. Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/ctl/ctl/ctl.html Index: vis_dev/vis-2.1/share/help/_grab_testCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/_grab_testCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/_grab_testCmd.txt (revision 11) @@ -0,0 +1,117 @@ + + _grab_test - Performs invairant checking on a flattened network with the GRAB + abstraction refinement algorithm. + _________________________________________________________________ + + _grab_test [-a ] [-c ] [-d ] + [-F] [-M] [-i] [-m] [-t ] [-v ] [-f + ] [-h] + + Performs invairant checking on a flattened network with the GRAB + abstraction refinement algorithm. Before calling this command, the + user should have created the flattened netowrk by calling the commands + [1]flatten_hierarchy and [2]build_partition_maigs. The default BDD + manager and network partition are not mandatory for calling this + command, though they will be used if available. (In other words, the + user doesn't have to run the commands [3]static_order and + [4]build_partition_mdds before calling this command.) Regardless of + the options, no 'false positive' or 'false negatives' will occurs: the + result is correct for the given model. Properties to be verified + should be provided as invariant formulae in the file inv_file. Node + that the support of any wire referred to in a formula should consist + only of latches. For the precise syntax of CTL and LTL formulas, see + the [5]VIS CTL and LTL syntax manual. + + If a formula does not pass, a proof of failure (referred to as a + counter-example) is demonstrated. Whether demostrate the proof or not + can be specified (see option -d). + + Command options: + + -a + Specify the refinement variable selection algorithm. + + refine_algorithm must be one of the following: + + GRAB: the GRAB refinement method (Default). + + -c + Specify the type of abstract counter-examples used in the + analysis. + + cex_type must be one of the following: + + 0: minterm state counter-example. + + 1: cube state counter-example. + + 2: synchronous onion rings (Default). + + -d + Specify whether to demonstrate a counter-example when the + system fails a formula being checked. + + dbg_level must be one of the following: + + 0: No debugging performed. dbg_level=0 is the default. + + 1: Generate a counter-example (a path to a fair cycle). + + -F + Enable or disable the use of fine-grain abstraction. + + finegrain_flag must be one of the following: + + 0: disable fine-grain abstraction. + + 1: enable fine-grain abstraction (Default). + + -M + Enable or disable the use of greedy refinement minimization. + + refinemin_flag must be one of the following: + + 0: disable greedy refinement minimization. + + 1: enable greedy refinement minimization (Default). + + -i + Print input values causing transitions between states during + debugging. Both primary and pseudo inputs are printed. + + -m + Pipe debugger output through the UNIX utility more. + + -t + Specify the time out period (in seconds) after which the + command aborts. By default this option is set to infinity. + + -v + Specify verbosity level. This sets the amount of feedback on + CPU usage and code status. + verbosity_level must be one of the following: + + 0: No feedback provided. This is the default. + + 1: Feedback on code location. + + 2: Feedback on code location and CPU usage. + + -f + Specify the name of the file ot which error trace is written. + + -h + Print the command usage. + + See also commands : model_check, check_invariant + __________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/html/flatten_hierarchyCmd.html + 2. file://localhost/projects/development/hsv/vis/common/doc/html/build_partition_maigsCmd.html + 3. file://localhost/projects/development/hsv/vis/common/doc/html/static_orderCmd.html + 4. file://localhost/projects/development/hsv/vis/common/doc/html/build_partition_mddsCmd.html + 5. file://localhost/projects/development/hsv/vis/common/doc/ctl/ctl/ctl.html Index: vis_dev/vis-2.1/share/help/_init_state_formulaCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/_init_state_formulaCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/_init_state_formulaCmd.txt (revision 11) @@ -0,0 +1,11 @@ + + _init_state_formula - write resettability condition as a CTL formula + _________________________________________________________________ + + _init_state_formula [-h] [] + + Write resettability condition as a CTL formula. Writes to init_file is + specified, else stdout. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/_mAig_testCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/_mAig_testCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/_mAig_testCmd.txt (revision 11) @@ -0,0 +1,8 @@ + + _mAig_test - + _________________________________________________________________ + + _mAig_test + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/_memory_profileCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/_memory_profileCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/_memory_profileCmd.txt (revision 11) @@ -0,0 +1,59 @@ + + _memory_profile - It shows the amount of memory used by every pacakge. + _________________________________________________________________ + + _memory_profile [-f ] [-h] [-p] [-u ] + + This command intregrates the output from purify with a function map + generated by a perlscript plus another perlscript to generate a memory + profile of vis. + + This command relies on the output of purify to a file to call the + script "memoryaccount" and produce a summary of how much memory has + been allocated by each package. Although this command may appear + simple it requires the interaction of two scripts and three files, so + special care should be taken when attempting to modify it. + + Here is the way it works. The code in this command is conditionally + compiled depending on the definition of the symbol PURIFY. If the + symbol is not defined, the program prints a message notifying that the + command is not operative in this executable. If PURIFY has been + defined, there are certain things that are assumed. The executable has + been linked with purify. The output of purify is being redirected to a + file with name purify.log. The perl script memoryaccount is in + $VIS/common/share and it is executable. There exists a file mapping + function names to packages in the same place whose name is .fmap. + + The command then calls purify_all_inuse() to force purify to dump to + the file purify.log the information about the memory that is currently + visible to the program. This memory is not the total memory allocated + by the program since there may be leaked memory that is no longer + accessible. A temporary file is created and the script memoryaccount + is called to analyze the file purify.log and write in the temporary + file the memory profile obtained from it. Once the script is done, the + temporary file is dumped to vis_stdout and deleted. + + Since most of the computation in this command is done by the + pearlscript memoryaccount, for more information please refer to the + message printed when the script is invoked with the option -h. Command + options: + + -f + File to read the dump from. The default is purify.log. This + option should be used if and only if the option -log-file has + been used at the linking stage when building the executable. + + -h + Print the command usage. + + -p + Print also the packages that did not allocated any visible + memory + + -u + Units to print the memory usage in. It may be "b" for bytes, + "k" for kilobytes, "m" for megabytes and "g" for gigabytes. The + default is bytes. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/_ntm_testCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/_ntm_testCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/_ntm_testCmd.txt (revision 11) @@ -0,0 +1,22 @@ + + _ntm_test - test the ntm package + _________________________________________________________________ + + _ntm_test [-h] [-v] + + Test the ntm package. This package is responsible for building the + multi-valued functions (represented as MDDs) of the flattened network. + This command builds the multi-valued functions of the combinational + outputs in terms of the combinational inputs. The multi-valued + functions are then deleted. + + Command options: + + -h + Print the command usage. + + -v + Print the sizes of the MDDs built. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/_tbl_testCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/_tbl_testCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/_tbl_testCmd.txt (revision 11) @@ -0,0 +1,18 @@ + + _tbl_test - test the functionality of the tbl package. + _________________________________________________________________ + + _tbl_test [-h] [-v] + + Tests the functionality of the tbl package. + + Command options: + + -h + Print the command usage. + + -v + Verbose mode. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/_tst_testCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/_tst_testCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/_tst_testCmd.txt (revision 11) @@ -0,0 +1,19 @@ + + _tst_test - template for implementing commands + _________________________________________________________________ + + _tst_test [-h] [-v] + + This command does nothing useful. It merely serves as a template for + the implementation of new commands. + + Command options: + + -h + Print the command usage. + + -v + Verbose mode. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/aliasCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/aliasCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/aliasCmd.txt (revision 11) @@ -0,0 +1,62 @@ + + alias - provide an alias for a command + _________________________________________________________________ + + alias [-h] [ []] + + The "alias" command, if given no arguments, will print the definition + of all current aliases. + + Given a single argument, it will print the definition of that alias + (if any). Given two arguments, the keyword "name" becomes an alias for + the command string "string", replacing any other alias with the same + name. + + Command options: + + -h + Print the command usage. + + + Alias + + + Command string + + It is possible to create aliases that take arguments by using the + history substitution mechanism. To protect the history substitution + character `%' from immediate expansion, it must be preceded by a `\' + when entering the alias. + + For example: + + vis> alias read read_\%:1 \%:2.\%:1 + vis> read blif lion + + + will create an alias `read', execute "read_blif lion.blif". + + And... + + vis> alias echo2 "echo Hi ; echo \%* !" + vis> echo2 happy birthday + + + will print: + + Hi + happy birthday ! + + + CAVEAT: Currently there is no check to see if there is a circular + dependency in the alias definition. e.g. + + vis> alias foo "print_network_stats; print_network; foo" + + + creates an alias which refers to itself. Executing the command "foo" + will result an infinite loop during which the commands + "print_network_stats" and "print_network" will be executed. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/approximate_model_checkCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/approximate_model_checkCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/approximate_model_checkCmd.txt (revision 11) @@ -0,0 +1,184 @@ + + approximate_model_check - perform ACTL model checking on an abstracted and + flattened network + _________________________________________________________________ + + approximate_model_check [-h] [-v ] + + Performs ACTL model checking on an abstracted and flattened network. + Predefined abstractions are performed prior to model checking. Before + calling this command, the user should have initialized the design by + calling the command [1]init_verify. + + The command includes two dual algorithms. The user should set + appropriate environment parameters associated with the command to + execute proper algorithm. By default, the command makes its effort to + prove whether given ACTL formula is positive. To check whether the + ACTL formula is negative, user should set the environment parameter + amc_prove_false prior to executing the command. See [2]below for the + environment parameters associated with this command. + + Properties to be verified should be provided as ACTL formulas in the + file . The command only accepts ACTL formulas. Mixed, ECTL + expressions are not supported. ACTL formulas are those in which all + quantifiers are universal and negation is only allowed at the level of + atomic propositions. For the precise syntax of CTL formulas, see the + [3]VIS CTL and LTL syntax manual. + + The command is designed to tackle the state explosion problem we + encounter when dealing with large and complex circuits. Based on the + initial size of the group, the command constructs over- or + under-approximation of the transition relation of the system. A group + (subsystem) is a portion of the original circuit containing a subset + of the latches and their next state functions. The initial size of a + group can be set with the [4]amc_sizeof_group environment variable. + These initial approximations may not contain every detail of the exact + system. However they may contain enough information to determine + whether the formula is positive or negative. Starting from an initial + coarse approximation, the command makes its effort to prove whether + given ACTL formula is positive or negative. When the procedure fails + to prove correctness of the formula with initial approximations, it + automatically refines the approximations. It repeats the process until + the algorithm produces a reliable result or the available resources + are exhausted. + + Due to the overhead procedures, for some circuits, the exact + [5]model_check method may evaluate formulas faster with less + resources. If any formula evaluates to false, a debug trace is + reported. + + The command does not use fairness constraints even if they have been + read with the [6]read_fairness command. + + Command options: + + -h + Print the command usage. + + -v + Specify verbosity level. verbosity_level must be one of the + following: + + 0 : No feedback provided. This is the default. + 1 : Some feedback. + 2 : Lots of feedback. + + -t + Specify the time out period (in seconds) after which the + command aborts. By default this option is set to infinity. + + + File containing ACTL formulas to be model checked. + + Environment Parameters: + + Environment parameters should be set using the set command from the + VIS shell + (e.g. vis> set amc_prove_false). + + amc_prove_false + When the parameter is set, the command makes its effort to + prove whether given ACTL formula is negative. The command + constructs a set of under-approximations of the transition + relations of the system. When the formula evaluates to false, a + debug trace is reported by default. + + amc_grouping_method + Specifies grouping method. Grouping method is a method for + grouping number of latches into single subsystem. Two methods + are supported. + + Grouping based on hierarchy(default) : The method groups + latches based on the hierarchy of the system. Normally, complex + circuits are designed in multiple processes. Furthermore, + processes form a hierarchy. The method uses this information + provided by the original design. When a design described in + high level description language is transformed into low level + BLIF format, the processes are transformed into subcircuits. + The method groups those latches that are within same + subcircuit. + + Grouping based on latch dependencies(latch_dependency): The + method groups those latches that are closely related. Closely + related latches are those who has many (transitive) connections + between them. + + When the parameter is not specified, the command by default + uses hierarchical grouping method. + + amc_sizeof_group + Determines the number of latches in each group(subsystem). The + default value is 8. The initial size of the subsystem + determines the initial degree of approximations of the + transition relations. There's no proven rule of setting the + value. Some experimental results show that setting the value to + about 5-20% of overall number of latches is reasonable(e.g. if + the system contains 100 latches set the value to 5-20). + However, the suggested range may not work well with some + examples. + + amc_DC_level + Specifies don't care levels. Default level is 0. Absence of the + parameter sets the amc_DC_level to 0. + amc_DC_level must be one of the following: + + 0: No don't cares are used. This is the default. + + 1: Use unreachable states as don't cares. + + 2: Aggressively use DC's to simplify MDD's in model checking. + + Using don't cares may take more time for some examples since + the approximate model checker computes the reachable states for + each subsystem. For some large circuits it is undesirable to + set don't care level. + + Related "set" options: + + ctl_change_bracket + Vl2mv automatically converts "[]" to "<>" in node names, + therefore CTL parser does the same thing. However, in some + cases a user does not want to change node names in CTL parsing. + Then, use this set option by giving "no". Default is "yes". + + See also commands : model_check, incremental_ctl_verification + + Examples: + Here are some example sequences of the VIS executions using the + approximate model checker. + + read_blif_mv abp/abp.mv + flatten_hierarchy + static_order + build_partition_mdds + set amc_sizeof_group 4 + approximate_model_check abp/abpt.ctl + time + quit + + read_blif_mv coherence/coherence.mv + flatten_hierarchy + static_order + build_partition_mdds + set amc_sizeof_group 8 + set amc_prove_false + set amc_DC_level 0 + approximate_model_check coherence/coherence2.ctl + time + quit + + The algorithm used by approximate_model_check is described in detail + in [7]ftp://vlsi.colorado.edu/pub/iccad96.ps + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/html/init_verifyCmd.html + 2. file://localhost/projects/development/hsv/vis/common/doc/html/approximate_model_checkCmd.html#environment + 3. file://localhost/projects/development/hsv/vis/common/doc/ctl/ctl/ctl.html + 4. file://localhost/projects/development/hsv/vis/common/doc/html/approximate_model_checkCmd.html#sizeofgroup + 5. file://localhost/projects/development/hsv/vis/common/doc/html/model_checkCmd.html + 6. file://localhost/projects/development/hsv/vis/common/doc/html/read_fairnessCmd.html + 7. ftp://vlsi.colorado.edu/pub/iccad96.ps Index: vis_dev/vis-2.1/share/help/bdd_sat_bounded_model_checkCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/bdd_sat_bounded_model_checkCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/bdd_sat_bounded_model_checkCmd.txt (revision 11) @@ -0,0 +1,94 @@ + + bdd_sat_bounded_model_check - performs an LTL bounded model checking on a + flattened network + _________________________________________________________________ + + bdd_sat_bounded_model_check [-h] [-v ] [-d + ] [-i] -m -k -s + -o + + Performs an LTL bounded model checking on a flattened network. This + command looks for a counterexample of length >= minimum_length and =< + maximum_length. It increments the length by step_value. Before calling + this command, the user should have initialized the design by calling + the command [1]flatten_hierarchy, and then calling the command + [2]build_partition_maigs. + + The value of maximum length must be >= minimum length. + + Command options: + + -h + Print the command usage. + + -m + Minimum length of counterexample to be checked (default is 0). + + -k + Maximum length of counterexample to be checked (default is 1). + + -s + Incrementing value of counterexample length (default is 1). + + -r + Use inductive proof at each step_value to check if the property + passes (default is 0). 0 means don't use the inductive proof. + BMC will check using the indcution if the property passes if + the current length of the counterexample is a multiple of + inductive_Step. + + -F + Read fairness constraints from . Each formula in + the file is a condition that must hold infinitely often on a + fair path. + + -o Save the CNF formula in + -t + Specify the time out period (in seconds) after which the + command aborts. By default this option is set to infinity. + + -v + Specify verbosity level. This sets the amount of feedback on + CPU usage and code status. + verbosity_level must be one of the following: + + 0: No feedback provided. This is the default. + + 1: Feedback on code location. + + 2: Feedback on code location and CPU usage. + + -d + Specify the amount of debugging performed when the BMC models + check the LTL formula. + + dbg_level must be one of the following: + + 0: No debugging performed. dbg_level=0 is the default. + + 1: Debugging with minimal output: generate counter-example if + the LTL formula fails and the counterexample length. + + -h + Print the command usage. + + -i + Print input values causing transitions between states during + debugging. + + -o ; + File containing CNF of the counterexample if exist. If + specifies, the user can exam this file looking for information + about the generated path. This file will be the input to the + SAT solver. The contents of this file is in dimacs format. + + + File containing LTL formulas to be model checked. + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/html/flatten_hierarchyCmd.html + 2. file://localhost/projects/development/hsv/vis/common/doc/html/build_partition_maigsCmd.html Index: vis_dev/vis-2.1/share/help/bounded_model_checkCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/bounded_model_checkCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/bounded_model_checkCmd.txt (revision 11) @@ -0,0 +1,142 @@ + + bounded_model_check - Performs a SAT-based LTL model checking on a flattened + network + _________________________________________________________________ + + bounded_model_check [-h] [-v ] [-m ] + [-k ] [-s ] [-r ] + [-e] [-F ] [-S ] [-E ] [-C + ] [-I ] [-d ] [-t ] + [-o ] [-i] + + Performs a SAT-based LTL bounded model checking (BMC) on a flattened + network. This command looks for a counterexample of length k ( + minimum_length =< k =< maximum_length). If -r is specified, this + command performs check for termination after each + termination_check_step . If no counterexample is found, this command + increases k by step_value (specifies by the -s option) until a + counterexample is found, the search becomes intractable (timed out), + or k reaches a bound (determine by the check for termination), and + then we conclude that the LTL property passes. This command implements + the basic encoding of Bounded Model Checking (BMC) as descibed in the + paper "Symbolic Model Checking without BDDs". However, the -E option + can be used to select other encoding scheme. We also applied some of + the improvements in the BMC encoding described in the paper "Improving + the Encoding of LTL Model Checking into SAT". To prove that an LTL + property passes, we implement the termination methods that are + descirebed in the papers "Checking Safety Properties Using Induction + and a SAT-Solver" and "Proving More Properties with Bounded Model + Checking". Before calling this command, the user should have + initialized the design by calling the command [1]flatten_hierarchy. If + the user uses the -r option and the LTL property is a general LTL + property, the command [2]build_partition_maigs must be called. The aig + graph must be built by calling the command [3]build_partition_mdds + + Command options: + + -h + Print the command usage. + + -m + Minimum length of counterexample to be checked (default is 0). + + -k + Maximum length of counterexample to be checked (default is 1). + + -s + Incrementing value of counterexample length (default is 1). + + -r + Check for termination for each termination_check_step (default + is 0). 0 means don't check for termination. + + -e + Activate early termination check. Check if there is no simple + path starts from an initial state. Valid only for general LTL + and safety properties. Must be used with -r option. + + -S + Specify SAT solver + sat_solver must be one of the following: + + 0: CirCUs (Default) + + 1: zChaff + + -E + Specify encoding scheme + encoding must be one of the following: + + 0: The original BMC encoding (Default) + + 1: SNF encoding + + 2: Fixpoint encoding + + -C + Specify clause type + encoding must be one of the following: + + 0: Apply CirCUs SAT solver on circuit (Default) + + 1: Apply SAT solver on CNF generated form circuit + + 2: Apply SAT solver on CNF + + -I + Specify increment sat solver type + encoding must be one of the following: + + 1: Trace Objective (Default) + + 2: Distill + + 3: Trace Objective + Distill + + -F + Read fairness constraints from . Each formula in + the file is a condition that must hold infinitely often on a + fair path. + + -o Save CNF formula in + -t + Specify the time out period (in seconds) after which the + command aborts. By default this option is set to infinity. + + -v + Specify verbosity level. This sets the amount of feedback on + CPU usage and code status. + verbosity_level must be one of the following: + + 0: No feedback provided. This is the default. + + 1: Feedback on code location. + + 2: Feedback on code location and CPU usage. + + -d + Specify the amount of debugging performed when the BMC models + check the LTL formula. + + dbg_level must be one of the following: + + 0: No debugging performed. dbg_level=0 is the default. + + 1: Debugging with minimal output: generate counter-example if + the LTL formula fails and the counterexample length. + + -i + Print input values causing transitions between states during + debugging. + + + File containing LTL formulae to be checked. + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/html/flatten_hierarchyCmd.html + 2. file://localhost/projects/development/hsv/vis/common/doc/html/build_partition_maigsCmd.html + 3. file://localhost/projects/development/hsv/vis/common/doc/html/build_partition_mddsCmd.html Index: vis_dev/vis-2.1/share/help/build_partition_maigsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/build_partition_maigsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/build_partition_maigsCmd.txt (revision 11) @@ -0,0 +1,24 @@ + + build_partition_maigs - build a partition of MAIGs for the flattened network + _________________________________________________________________ + + build_partition_maigs [-h] [-d] [-n] + + Build the multi-valued AND/INVERTER graph (MAIG) of a flattened + network. It builds the MAIG for the combinational outputs (COs) in + terms of the combinational inputs (CIs). The pointer to this graph is + stored in the network to be used by other commands, such as + bounded_model_check. This command must be preceded by the commands + flatten_hierarchy. This command will remove any previous build to this + graph. + + Command options: + + -n + Disable BDD sweeping. + + -d + Build aig structure in depth first manner. + __________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/build_partition_mddsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/build_partition_mddsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/build_partition_mddsCmd.txt (revision 11) @@ -0,0 +1,86 @@ + + build_partition_mdds - build a partition of MDDs for the flattened network + _________________________________________________________________ + + build_partition_mdds [-h] [-i] [-n ] [-s ] [-t ] + [-v] [] + + Build the MDDs of a flattened network. Depending on the method + selected, the MDDs for the combinational outputs (COs) are built in + terms of either the combinational inputs (CIs) or in terms of some + subset of intermediate nodes of the network. The MDDs built are stored + in a DAG called a "partition". The vertices of a partition correspond + to the CIs, COs, and any intermediate nodes used. Each vertex has a + multi-valued function (represented by MDDs) expressing the function of + the corresponding network node in terms of the partition vertices in + its transitive fanin. Hence, the MDDs of the partition represent a + partial collapsing of the network. + + This command must be preceded by the commands flatten_hierarchy and + static_order. The partition built is stored with the network for use + by other commands, such as simulate, compute_reach, model_check, etc. + This command has no affect when invoked on a network that already has + a partition. To remove the existing partition of a network, reinvoke + flatten_hierarchy. + + The choice of method determines which intermediate nodes are used. The + inout method represents one extreme where no intermediate nodes are + used, and total represents the other extreme where every node in the + network has a corresponding vertex in the partition. If no method is + specified on the command line, then the value of the flag + partition_method is used (this flag is set by the command set + partition_method), unless it does not have a value, in which case the + forntier method is used. The different methods available are: + + inout Expresses the combinational outputs in terms of the + combinational inputs. + + total The partition built is isomorphic to the combinational part of + the network. The function of each node is expressed in terms of + its immediate fanins. If the -i is used the function attached + to each vertex is computed as a function of the combinational + inputs. + + partial Builds a partition using the intermediate nodes specified + with the -n option or the -f option. + + frontier (default) Builds a partition creating vertices for the + intermediate nodes as needed in order to control the BDD size. + The threshold value for the BDD size can be set by the + parameter "partition_threshold". This method encompasses both + "inout" (set partition_threshold parameter to infinity) and + "total" (set partition_threshold parameter to 0). + + boundary Builds a partition in a fashion that preserves all nodes + that are Input/Output nodes of any hnode in the hierarchy + rooted at the current hnode. + + Command options: + + -h + Print the command usage. + + -i + Build the multi-valued functions of each partition vertex in + terms of the combinational inputs, rather than in terms of its + transitive fanin vertices. + + -n + Used in conjunction with the partial method. List is a comma + separated list of network nodes to use as intermediate nodes in + the partition. + + -s + Level of severity of a post-computation check applied to the + partition data structure (0 by default, meaning no check). + + -t + Time in seconds allowed to build the partition. If the + computation time goes above that limit, the process of building + the partition is aborted. The default is no limit. + + -v + Turn on the verbosity. + __________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/cdCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/cdCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/cdCmd.txt (revision 11) @@ -0,0 +1,17 @@ + + cd - change the current node + _________________________________________________________________ + + cd [-h] or <..> + + Changes the current node in the existing hierarchy. The argument + should be either the name of a child node or .. meaning the parent + node. Note that cd ../foo is not allowed. + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/check_invariantCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/check_invariantCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/check_invariantCmd.txt (revision 11) @@ -0,0 +1,277 @@ + + check_invariant - check all states reachable in flattened network satisfy + specified invariants + _________________________________________________________________ + + check_invariant [-c] [-d ] [-g ] [-f] [-h] [-i] + [-m] [-r] [-t ] [-v ] [-A + ] [-D] + + Performs invariant checking on a flattened network. Before calling + this command, the user should have initialized the design by calling + the command [1]init_verify. + + If the option -A3 (abstraction refinement method GRAB) is used, the + command [2]build_partition_maigs should also have been executed. + However, in this case, the default BDD manager and network partition + are not mandatory, though they will be used if available. (In other + words, the user must run the commands [3]flatten_hierarchy and + [4]build_partition_maigs, but doesn't have to run the commands + [5]static_order and [6]build_partition_mdds before calling this + command.) For extremely large networks, it is actually favorable not + to build them for the entire concrete model, but let this procedure + assign bdd ids and construct the partition incrementally. + + Option -A4 means abstraction refinement approach using puresat + algorithm, which is entirely based on SAT solver. + + An invariant is a set of states. Checking the invariant is the process + of determining that all states reachable from the initial states lie + in the invariant. + + One way of defining an invariant is through a CTL formula which has no + path operators. Such formulas should be specified in the file + invar_file. Note that the support of any wire referred to in a formula + should consist only of latches. For the precise syntax of CTL + formulas, see the [7]VIS CTL and LTL syntax manual. + + check_invariant ignores all fairness conditions associated with the + FSM. + + check_invariant involves reachability analysis where at every step of + the reachability computation all the specified invariants are checked + in the reachable states computed thus far. If some invariant does not + hold, a proof of failure is demonstrated. This consists of a path + starting from an initial state to a state lying outside the invariant. + This path is made as short as possible. For the -A 0 option or default + -A option, it is the shortest path leading to a state outside the + invariant. If a set of invariants is specified, the failed formulas + are reported as soon as they are detected. The check is continued with + the remaining invariants. + + Command options: + + -d + Specify the amount of debugging performed when the system fails + a formula being checked. + + dbg_level must be one of the following: + + 0 : No debugging performed. This is the default. + + 1 : Generate a path from an initial state to a state lying + outside the invariant. This option stores the onion rings just + as specifying -f would have. Therefore, it may take more time + and memory if the formula passes. This option is incompatible + with -A 2 option. + + -f + Store the set of new states (onion rings) reached at each step + of invariant. This option is likely to use more memory but + possibly faster results for invariants that fail. Therefore, + the debug information for a failed invariant, if requested, may + be provided faster. This option is not compatible with -A 2 + options. + + -g + Use guided search. The file hints_file contains a series of + hints. A hint is a formula that does not contain any temporal + operators, so hints_file has the same syntax as a file of + invariants used for check_invariant. The hints are used in the + order given to change the transition relation. The transition + relation is conjoined with the hint to yield an + underapproximation of the transition relation. If the hints are + cleverly chosen, this may speed up the computation + considerably, because a search with the changed transition + relation may be much simpler than one with the original + transition relation, and results obtained can be reused, so + that we may never have to do an expensive search with the + original relation. See also: Ravi and Somenzi, Hints to + accelerate symbolic traversal. CHARME'99; Bloem, Ravi, and + Somenzi, Efficient Decision Procedures for Model Checking of + Linear Time Logic Properties, CAV'99; Bloem, Ravi, and Somenzi, + Symbolic Guided Search for CTL Model Checking, DAC'00. This + option is not compatible with -A 2 option. The description of + some options for guided search can be found in the help page + for print_guided_search_options. + + -h + Print the command usage. + + -c + Use the formula tree so that subformulae are not shared among + the CTL formulae in the input file. This option is useful in + the following scenario - formulae A, B and C are being checked + in order and there is sub-formula sharing between A and C. If + the BDDs corresponding to the shared sub-formula is huge then + computation for B might not be able to finish without using + this option. + + -i + Print input values causing transitions between states during + debugging. Both primary and pseudo inputs are printed. + + -m + Pipe debugger output through the UNIX utility more. + + -r + Reduce the FSM derived from the flattened network with respect + to each of the invariants in the input file. By default, the + FSM is reduced with respect to the conjunction of the + invariants in the input file. If this option is used and don't + cares are being used for simplification, then subformula + sharing is disabled (result might be incorrect otherwise). + + The truth of an invariant may be independant of parts of the + network (such as when wires have been abstracted; see + [8]flatten_hierarchy). These parts are effectively removed when + this option is invoked; this may result in more efficient + invariant checking. + + -t + Specify the time out period (in seconds) after which the + command aborts. By default this option is set to infinity. + + -v + Specify verbosity level. This sets the amount of feedback on + CPU usage and code status. + + verbosity_level must be one of the following: + + 0 : No feedback provided. This is the default. + + 1 : Feedback on code location. + + 2 : Feedback on code location and CPU usage. + + -A + This option allows specification of the type of reachability + computation. + + 0: (default) Breadth First Search. No approximate reachability + computation. + + 1: High Density Reachability Analysis (HD). Computes reachable + states in a manner that keeps BDD sizes under control. May be + faster than BFS in some cases. For larger circuits, this option + could compute more reachable states than the -A 0 option for + the same memory constraints, consequently may prove more + invariants false. For help on controlling options for HD, look + up help on the command: print_hd_options [9]print_hd_options. + Refer Ravi & Somenzi, ICCAD95. The path generated for a failed + invariant using this method may not be the shortest path. This + option is available only when compiled with the CUDD package. + + 2. Approximate Reachability Don't Cares(ARDC). Computes + over-approximated reachable states in the reachability analysis + step. This may be faster than the -A 0 option . The invariants + are checked in the over-approximation. This may produce false + negatives, but these are resolved internally using the exact + reachable states. The final results produced are the same as + those for exact reachable states. For help on controlling + options for ARDC, look up help on the command: + print_ardc_options. [10]print_ardc_options Refer 2 papers in + TCAD96 Dec. Cho et al, one is for State Space Decomposition and + the other is for Approximate FSM Traversal. This option is + incompatible with -d 1 and -g options. + + 3. The GRAB Abstraction Refinement Method. Conducts the + reachability analysis on an abstract model. If the invariants + are true in the abstract model, they are also true in the + original model. If the invariants are false, the abstract + counter-examples are used to refine the abstract model (since + it is still inconclusive). This procedure iterates until a + conclusive result is reached. Note that, with this option, + "build_partitioned_mdds" and "static_order" does not have to be + executed before calling "check_invariants," though the default + BDD partition and order will be reused if available. (When + checking extremely large models, skipping either or both + "static_order" and "build_partitioned_mdds" can often make the + verification much faster.) The grainularity of abstraction + refinement also depends on the parameter "partition_threshold", + which by default is 5000; one can use the VIS command "set + partition_threshold 1000" to change its value. For experienced + users who want to fine-tune the different parameters of GRAB, + please try the test command "_grab_test" ("_grab_test -h" + prints out its usage information). Refer to Wang et al., + ICCAD2003 and ICCD2004 for more information about the GRAB + algorithm. Note that this option is incompatible with the "-d + 1" and "-g" options. + + 4. Abstraction refinement approach using puresat algorithm, + which is entirely based on SAT solver. It has several parts: * + Localization base Abstraction * K-induction to prove the truth + of a property * Bounded Model Checking to find bugs * + Incremental concretization based methods to verify abstract + bugs * UNSAT proof based method to obtain refinement * + Refinement minization to guarrantee a minimal refinement For + more information, please check the BMC'03 and STTT'05 paper of + Li et al., "A satisfiability-based appraoch to abstraction + refinement in model checking", and " Abstraction in symbolic + model checking using satisfiability as the only decision + procedure" + + -D + First compute an overapproximation to the reachable states. + Minimize the transition relation using this approximation, and + then compute the set of reachable states exactly. This may + accelerate reachability analysis. Refer to the paper by Moon et + al, ICCAD98. The BDD minimizing method can be chosen by using + "set image_minimize_method " [11]set. This option is + incompatible with -g. + + -F + Write the debugger output to dbg_file. + + + File containing invariants to be checked. + + Related "set" options: + + rch_simulate <#> + The set option can be used to set this flag rch_simulate to specify + the number of random vectors to be simulated. Default value for this + number is 0. + + ctl_change_bracket + Vl2mv automatically converts "[]" to "<>" in node names, therefore CTL + parser does the same thing. However, in some cases a user does not + want to change node names in CTL parsing. Then, use this set option by + giving "no". Default is "yes". + + See also command : compute_reach + + -w This option invoked the algorithm to generate an error + trace divided into fated and free segements. Fate represents the + inevitability and free is asserted when there is no inevitability. + This can be formulated as a two-player concurrent reachability game. + The two players are the environment and the system. The node_file is + given To specify the variables the are controlled by the system. + + -W + This option represents the case that all input variables are + controlled by system. + + -G + We proposed two algorithm to generate segemented counter example. They + are general and restrcited algorithm. Bu default we use restricted + algorithm. We can invoke general algorithm with -G option. For more + information, please check the STTT'04 paper of Jin et al., "Fate and + Free Will in Error Traces" + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/html/init_verifyCmd.html + 2. file://localhost/projects/development/hsv/vis/common/doc/html/build_partition_maigsCmd.html + 3. file://localhost/projects/development/hsv/vis/common/doc/html/flatten_hierarchyCmd.html + 4. file://localhost/projects/development/hsv/vis/common/doc/html/build_partition_maigsCmd.html + 5. file://localhost/projects/development/hsv/vis/common/doc/html/static_orderCmd.html + 6. file://localhost/projects/development/hsv/vis/common/doc/html/build_partition_mddsCmd.html + 7. file://localhost/projects/development/hsv/vis/common/doc/ctl/ctl/ctl.html + 8. file://localhost/projects/development/hsv/vis/common/doc/html/flatten_hierarchyCmd.html + 9. file://localhost/projects/development/hsv/vis/common/doc/html/print_hd_optionsCmd.html + 10. file://localhost/projects/development/hsv/vis/common/doc/html/print_ardc_optionsCmd.html + 11. file://localhost/projects/development/hsv/vis/common/doc/html/setCmd.html Index: vis_dev/vis-2.1/share/help/cnf_satCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/cnf_satCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/cnf_satCmd.txt (revision 11) @@ -0,0 +1,25 @@ + + cnf_sat - Perform SAT solving with CNF input + _________________________________________________________________ + + cnf_sat [-h] [-a ] [-f ] [-t + ] [-v ] [-b] + + Perform SAT solving with CirCUs after reading CNF file + + -b + If the given CNF has small number of variables and clause then the BDD + is built from the CNF clauses. If the monolithic BDD is built then we + can conclude SAT or UNSAT, otherwise the normal SAT algorithm is + invoked. + + -t + Specify the time out period (in seconds) after which the command + aborts. By default this option is set to infinity. + + -f + Specify the output filename to save the satisfying assignments and the + statistics of SAT solving. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/collapse_childCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/collapse_childCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/collapse_childCmd.txt (revision 11) @@ -0,0 +1,42 @@ + + collapse_child - Collapses a parent (which is the current node) and a given + child node into the parent + _________________________________________________________________ + + collapse_child [-h] [-v] + + This command collapses the given child into the current node. After + this command, the number of children of the current node will decrease + by one. The variables in the child node will be renamed to reflect + their original name. For example, if the current node is named "foo" + and it has two children, "bar1" and "bar2", then after + + collapse_child bar1 + + is executed, the name of any variable occuring in bar1, say "xvar" + will be renamed "bar1$xvar". The new parent will have only the single + child "bar2" (which can be seen by typing "ls"). + + The user can use "cd" to traverse a hierarchy, go to a particular + node. When the user uses "write_blif" from a particular node, vis will + write the circuit in this node out. However, the user might want to do + synthesis on the entire circuit in the hierarchy. In that case, the + hierarchy can be collapsed into a single node, by repeatedly using + this command. + + Examples: + + collapse_child P1 + + Collapse P1 into the current node. + + Command options: + + -h + Print the command usage. + + -v + Verbose mode. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/comb_verifyCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/comb_verifyCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/comb_verifyCmd.txt (revision 11) @@ -0,0 +1,101 @@ + + comb_verify - verify the combinational equivalence of two flattened networks + _________________________________________________________________ + + comb_verify [-b] [-f ] [-h] [-o ] [-t + ] [-1 ] [-2 ] [-i] + [] + + This command verifies the combinational equivalence of two flattened + networks. In particular, any set of functions (the roots), defined + over any set of intermediate variables (the leaves), can be checked + for equivalence between the two networks. Roots and leaves are subsets + of the nodes of a network, with the restriction that the leaves should + form a complete support for the roots. The correspondence between the + roots and the leaves in the two networks is specified in a file given + by the option -f . The default option assumes that the roots are the + combinational outputs and the leaves are the combinational inputs. + + When there is a pseudo input in the set of leaves, the range of values + it can take should be the same as that of the multi-valued variable + corresponding to it, for comb_verify to function correctly. This + restriction will be removed in future. + + There are two ways to do combinational verification. In the first + mode, two BLIF-MV files are given as arguments to the command, e.g. + + vis> comb_verify foo.mv bar.mv + + + Verification is done for the flattened networks at the root nodes of + the two BLIF-MV hierarchies. In any error messages printed, "network1" + refers to the first file, and "network2" refers to the second. Both of + these networks are freed at the end of the command. This mode is + totally independent from any existing hierarchy previously read in. In + the second mode, it is assumed that a hierarchy has already been read + in. Then, comb_verify can be called with a single BLIF-MV file, and + this will do the comparison between the network present at the current + node ("network1") and the network corresponding to the root node of + the hierarchy in the BLIF-MV file("network2"). A typical sequence of + commands is: + + vis> read_blifmv foo.mv + vis> init_verify + vis> comb_verify bar.mv + + + If a hierarchy has been read in but a flattened network does not exist + at the current node (flatten_hierarchy has not been invoked), the + command does nothing. If a network exists at the current node, but the + variables haven't been ordered, then the variables are ordered and a + partition created. This partition is freed at the end. A side-effect + is that the variables are ordered. If a partition exists, then it is + used if the vertices corresponding to the roots specified are present + in it, otherwise a new partition is created with the current ordering. + The partition created for the new network read in is always freed at + the end. + + Command options: + + -b + Specifies that the files are BLIF files and not BLIF-MV files. + + -f + Provides the correspondence between the leaves and roots of + network1 and network2. If this option is not used, it is + assumed that the correspondence is by name, leaves are the + combinational inputs, and roots are the combinational outputs. + + -h + Print the command usage. + + -t + Time in seconds allowed to perform equivalence checking. The + default is infinity. + + -o + Specifies the ordering method to be used for assigning a common + ordering to the leaves of network1 and network2. If this option + is not used, ordering is done using a default method. + Currently, only the default method is available. + + -1 + Specifies the partitioning method to be used for network1. + Supported methods are "total", "partial", and "inout" (see the + command build_partition_mdds for more information). If this + option is not specified, then the default method "inout" is + used. + + -2 + Specifies the partitioning method to be used for network2. + Supported methods are "total", "partial", and "inout" (see the + command build_partition_mdds for more information). If this + option is not specified, then default method "inout" is used. + + -i + Print Bdd statistics. This is the only way to see bdd stastics + during this command. print_bdd_stats after this command doesn't + show information related to this command. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/compute_reachCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/compute_reachCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/compute_reachCmd.txt (revision 11) @@ -0,0 +1,164 @@ + + compute_reach - compute the set of reachable states of the FSM + _________________________________________________________________ + + compute_reach [-d ] [-f] [-g ] [-h] [-i] [-r + ] [-s ] [-t ] [-v #] [-A #] [-D] + [-F] + + Compute the set of reachable states of the FSM associated with the + flattened network. The command build_partition_mdds (or init_verify) + must have already been invoked on the flattened network, before this + command is called. On subsequent calls to compute_reach, the reachable + states will not be recomputed, but statistics can be printed using -v. + To force recomputation with a different set of options, for example a + depth value with -d, use -F option. + + The method used for image computation is displayed by the option -v 1. + To change the image computation method, use the command set + image_method, and then start again with the command flatten_hierarchy. + The reachability computation makes extensive use of image computation. + There are several user-settable options that can be used to affect the + performance of image computation. See the documentation for the set + command for these options. + + Command options: + + -d + Perform reachability for depthValue steps only - this option + specifies the number of unit operations (image computations) to + be performed in the reachability computation. The depthValue + used in successive calls proceeds from the previous state. For + example, compute_reach -d 3; compute_reach -d 4; will perform 7 + steps of reachability in total, the second call to + compute_reach proceeding from the result of the first. While + using only -A 0 option (default), this additionally corresponds + to the depth in the state graph, starting from the initial + state. For the -A 1 option, the above may not be true. This + option is not compatible with -A 2. + + -f + Store the set of new states (onion rings) reached at each step + of reachability. If this flag is specified, then the + computation proceeds with the previously set of onion rings, if + any exist (not any prior computation without onion rings). This + option is likely to use more memory during reachability + analysis. This is not compatible with -A 2. + + -g + Use guided search. The file hints_file contains a series of + hints. A hint is a formula that does not contain any temporal + operators, so hints_file has the same syntax as a file of + invariants used for check_invariant. The hints are used in the + order given to change the transition relation. The transition + relation is conjoined with the hint to yield an + underapproximation of the transition relation. If the hints are + cleverly chosen, this may speed up the computation + considerably, because a search with the changed transition + relation may be much simpler than one with the original + transition relation, and results obtained can be reused, so + that we may never have to do an expensive search with the + original relation. See also: Ravi and Somenzi, Hints to + accelerate symbolic traversal. CHARME'99; Bloem, Ravi, and + Somenzi, Efficient Decision Procedures for Model Checking of + Linear Time Logic Properties, CAV'99; Bloem, Ravi, and Somenzi, + Symbolic Guided Search for CTL Model Checking, DAC'00. Not + allowed with -A 2 or -i, and will only work with iwls95 or + monolithic image methods. The description of some options for + guided search can be found in the help page for + print_guided_search_options. + + -h + Print the command usage. + + -i + This option is useful when it's not possible to build the + complete transition relation. Using this option, the transition + relation is rebuilt at every itereation using the current + reached set of states as the care set. This option is not + compatible with the -A > 0 options, the -D option and the -g + option. + + -r + Dynamic reordering (with method sift) is invoked once when the + size of the reachable state set reaches the threshold value. + + -s + At every printStep of the reachability computation, print the + total number of states reached thus far, and the size of the + MDD representing this set. + + -t + Time allowed to perform reachability (in seconds). Default is + infinity. + + -v # + Print debug information. + 0: (default) Nothing is printed out. + + 1: Print a summary of reachability analysis and some + information about the image computation method (see + print_img_info) and summarizes results of reachability: + + FSM depth: the farthest reachable state + reachable states: the number of reachable states + MDD size: the size of the MDD representing the reachable states + analysis time: number of CPU seconds taken to compute the + reachable states + + 2: Prints the detailed information about reachability analysis. + For each printStep, it prints the MDD size of the reachable + state set and the number of states in the set. + + -A # + This option allows specification of approximate reachability + computation. + + 0: (default) Breadth First Search. No approximate reachability + computation. + + 1: High Density Reachability Analysis (HD). Computes reachable + states in a manner that keeps BDD sizes under control. May be + faster than BFS in some cases. For larger circuits, this option + should compute more reachable states. For help on controlling + options for HD, look up help on the command: print_hd_options + [1]print_hd_options. Refer to Ravi and Somenzi, ICCAD95. This + option is available only when VIS is linked with the CUDD + package. + + 2. Approximate Reachability Don't Cares(ARDC). Computes + over-approximate reachable states. For help on controlling + options for ARDC, look up help on the command: + print_ardc_options [2]print_ardc_options. Refer Moon's paper, + ICCAD98 and 2 papers by Cho et al, December TCAD96: one is for + State Space Decomposition and the other is for Approximate FSM + Traversal. The options -d, -g and -f are not compatible with + this option. + + -D + First compute an overapproximation to the reachable states. + Minimize transition relation using this approximation, and then + compute the set of reachable states exactly. This may + accelerate reachability analysis. Refer to the paper by Moon et + al, ICCAD98. The BDD minimizing method can be chosen by using + "set image_minimize_method " [3]set. This option is + incompatible with -i. + + -F + Force to recompute reachable states. + + Related "set" options: + + rch_simulate <#> + The set option can be used to set this flag rch_simulate to + specify the number of random vectors to be simulated. Default + value for this number is 0. + __________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/html/print_hd_optionsCmd.html + 2. file://localhost/projects/development/hsv/vis/common/doc/html/print_ardc_optionsCmd.html + 3. file://localhost/projects/development/hsv/vis/common/doc/html/setCmd.html Index: vis_dev/vis-2.1/share/help/decompose_childCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/decompose_childCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/decompose_childCmd.txt (revision 11) @@ -0,0 +1,57 @@ + + decompose_child - Partitions Node components into child nodes. + _________________________________________________________________ + + decompose_child -n [-f ] [-c] [-v] [-t] [-l] + [] + + This command partitions the current Node into several new children + nodes according to user-specified groups. The user may specify several + groups by name [-n] sequentially on the command line. Within each + group a list of components (either variables or child nodes) can be + placed. The flags [-c] [-v] toggle whether element names are + interpreted as child instances or variables (default is instances + [-c]). Element names can be loaded from a file as well using the [-f] + flag. + + By specifying a variable to be grouped, any object (e.g., Table, + Latch, Child) that PRODUCES that variable is included in the newly + created child node for that group. + + Command options: + + -n + Define new group + + -f + Load names from file + + -c + Interpret names that follow as child instances to group + + -v + Interpret names that follow as variables + + -l + Include all latch output nodes (and therefore latches) in group + + -t + Include all combinational tables in group. Examples: + + decompose_child -n c1 -v G1 G2 -n c2 IA IB + + Place variables G1 and G2 into a new child node c1 and child nodes IA + and IB into a new child node c2. + + Example: + + decompose_child -n ckt_inst child1 -f myinstances -v var1 -n + latch_inst -l + + This groups the subckts child1 and those listed in the file + myinstances, as well as the variable var1 into a subckt called + 'ckt_inst'. It also groups all the latches into a subckt called + 'latch_inst'. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/dynamic_var_orderingCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/dynamic_var_orderingCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/dynamic_var_orderingCmd.txt (revision 11) @@ -0,0 +1,132 @@ + + dynamic_var_ordering - control the application of dynamic variable ordering + _________________________________________________________________ + + dynamic_var_ordering [-d] [-e ] [-f ] [-h] + + Control the application of dynamic variable ordering to the flattened + network. Dynamic ordering is a technique to reorder the MDD variables + to reduce the size of the existing MDDs. When no options are + specified, the current status of dynamic ordering is displayed. At + most one of the options -e, -f, and -d should be specified. The + commands flatten_hierarchy and static_order must be invoked before + this command. + + Dynamic ordering may be time consuming, but can often reduce the size + of the MDDs dramatically. The good points to invoke dynamic ordering + explicitly (using the -f option) are after the commands + build_partition_mdds and print_img_info. If dynamic ordering finds a + good ordering, then you may wish to save this ordering (using + write_order) and reuse it (using static_order -s) in the future. A + common sequence used to get a good ordering is the following: + + init_verify + print_img_info + dynamic_var_ordering -f sift + write_order + flatten_hierarchy + static_order -s input_and_latch -f + build_partition_mdds + print_img_info + dynamic_var_ordering -f sift + + + For many large examples, there is no single best variable order, or + that order is hard to find. For example, the best ordering during + partitioning of the network may be different from the best ordering + during a model check. In that case you can use automatic reordering, + using the -e option. This will trigger reordering whenever the total + size of the MDD increases by a certain factor. Often, the init command + is replaced by the following sequence: + flatten_hierarchy + static_order + dynamic_var_ordering -e sift + build_partition_mdds + + + Command options: + + -d + Disable dynamic ordering from triggering automatically. + + -e + Enable dynamic ordering to trigger automatically whenever a + certain threshold on the overall MDD size is reached. "Method" + must be one of the following: + + window: Permutes the variables within windows of three adjacent + variables so as to minimize the overall MDD size. This process + is repeated until no more reduction in size occurs. + + sift: Moves each variable throughout the order to find an + optimal position for that variable (assuming all other + variables are fixed). This generally achieves greater size + reductions than the window method, but is slower. + + The following methods are only available if VIS has been linked + with the Bdd package from the University of Colorado (cuBdd). + + random: Pairs of variables are randomly chosen, and swapped in + the order. The swap is performed by a series of swaps of + adjacent variables. The best order among those obtained by the + series of swaps is retained. The number of pairs chosen for + swapping equals the number of variables in the diagram. + + random_pivot: Same as random, but the two variables are chosen + so that the first is above the variable with the largest number + of nodes, and the second is below that variable. In case there + are several variables tied for the maximum number of nodes, the + one closest to the root is used. + + sift_converge: The sift method is iterated until no further + improvement is obtained. + + symmetry_sift: This method is an implementation of symmetric + sifting. It is similar to sifting, with one addition: Variables + that become adjacent during sifting are tested for symmetry. If + they are symmetric, they are linked in a group. Sifting then + continues with a group being moved, instead of a single + variable. + + symmetry_sift_converge: The symmetry_sift method is iterated + until no further improvement is obtained. + + window{2,3,4}: Permutes the variables within windows of n + adjacent variables, where "n" can be either 2, 3 or 4, so as to + minimize the overall MDD size. + + window{2,3,4}_converge: The window{2,3,4} method is iterated + until no further improvement is obtained. + + group_sift: This method is similar to symmetry_sift, but uses + more general criteria to create groups. + + group_sift_converge: The group_sift method is iterated until no + further improvement is obtained. + + lazy_sift: This method is similar to group_sift, but the + creation of groups takes into account the pairing of present + and next state variables. + + annealing: This method is an implementation of simulated + annealing for variable ordering. This method is potentially + very slow. + + genetic: This method is an implementation of a genetic + algorithm for variable ordering. This method is potentially + very slow. + + -f + Force dynamic ordering to be invoked immediately. The values + for method are the same as in option -e. + + -h + Print the command usage. + + -v <#> + Verbosity level. Default is 0. For values greater than 0, + statistics pertaining to reordering will be printed whenever + reordering occurs. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/echoCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/echoCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/echoCmd.txt (revision 11) @@ -0,0 +1,15 @@ + + echo - merely echo the arguments + _________________________________________________________________ + + echo [-h] + + Echoes the arguments to standard output. + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/flatten_hierarchyCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/flatten_hierarchyCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/flatten_hierarchyCmd.txt (revision 11) @@ -0,0 +1,91 @@ + + flatten_hierarchy - create a flattened network + _________________________________________________________________ + + flatten_hierarchy [-a ] [-b] [-h] [-s] [-v #] + + Creates a flattened network from a hierarchical description. The + flattened network encompasses everything from the current node of the + hierarchy (reached by the command cd), down to and including the + leaves. It creates a view with the hierarchy removed, but retains the + multi-level logic structure. The resulting flattened network is stored + with the current node. Every table in the flattened network is checked + whether it is completely specified and deterministic. This is the + starting point for verification related commands. + + A limited form of abstraction can be done by providing a list of + variables to treat as primary inputs. See the information under + below. + + The verification part of VIS requires the functions specified by the + BLIF-MV tables to be completely specified and deterministic. These + conditions are checked during the flattening process; if a table is + found that is incompletely specified or is nondeterministic, then an + error message is written and a flattened network is not created. The + exception to this rule is tables specifying "pseudo inputs"; these are + tables with no inputs, and a single output that can take more than one + value. Such tables are generated by vl2mv to model the "$ND" construct + in Verilog. + + If this command is invoked a second time from the same point in the + hierarchy, the previous network is deleted and a new one is created. + This is the tactic to follow if you want to change some aspect of the + current network, such as MDD variable ordering or image_method. + + Command options: + + -a + A file containing names of variables, used to specify which + variables to abstract. The name of a variable is the full + hierarchical path name, starting from just after the current + hierarchy node (i.e., if the current node is foo, and you want + to refer to variable x in foo, then just use x). A variable + should appear at most once in the file. Each variable name + should appear at the beginning of a new line, with no white + space preceding it. The end of a variable name is marked by + white space, and any other text on the rest of the line is + ignored. Any line starting with "#" or white space is ignored. + A sample file is shown here. + + # variables to abstract to model check liveness property + choosing0 + p0.pc + + + For each variable x appearing in the file, a new primary input + node named x$ABS is created to drive all the nodes that were + previously driven by x. Hence, the node x will not have any + fanouts; however, x and its transitive fanins will remain in + the network. + + Abstracting a net effectively allows it to take any value in + its range, at every clock cycle. This mechanism can be used to + perform manual abstractions. The variables to abstract should + not affect the correctness of the property being checked. This + usually simplifies the network, and permits some verification + tasks to complete that would not otherwise. Note, however, that + by increasing the behavior of the system, false negatives are + possible when checking universal properties, and false + positives are possible when checking existential properties. + + A convenient way of generating the hierarchical variable names + is by using the write_order command. Note that abstracting next + state variables has no effect. + + -b + This option has no effect any longer. + + -h + Print the command usage. + + -s + Do not perform a sweep. + + -v # + Print debug information. + 0: (default) Nothing is printed out. + + >= 2: Prints the variables read from the input file. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/helpCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/helpCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/helpCmd.txt (revision 11) @@ -0,0 +1,21 @@ + + help - provide on-line information on commands + _________________________________________________________________ + + help [-a] [-h] [] + + Given no arguments, "help" prints a list of all commands known to the + command interpreter. If a command name is given, detailed information + for that command will be provided. + + Command options: + + -a + Provides a list of all internal commands, which by convention + begin with an underscore. + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/historyCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/historyCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/historyCmd.txt (revision 11) @@ -0,0 +1,73 @@ + + history - list previous commands and their event numbers + _________________________________________________________________ + + history [-h] [] + + Lists previous commands and their event numbers. This is a UNIX-like + history mechanism inside the VIS shell. + + Command options: + + -h + Print the command usage. + + + Lists the last events. Lists the last 30 events if + is not specified. + + History Substitution: + + The history substitution mechanism is a simpler version of the csh + history substitution mechanism. It enables you to reuse words from + previously typed commands. + + The default history substitution character is the `%' (`!' is default + for shell escapes, and `#' marks the beginning of a comment). This can + be changed using the "set" command. In this description '%' is used as + the history_char. The `%' can appear anywhere in a line. A line + containing a history substitution is echoed to the screen after the + substitution takes place. `%' can be preceded by a `\' in order to + escape the substitution, for example, to enter a `%' into an alias or + to set the prompt. + + Each valid line typed at the prompt is saved. If the "history" + variable is set (see help page for "set"), each line is also echoed to + the history file. You can use the "history" command to list the + previously typed commands. + + Substitutions: + + At any point in a line these history substitutions are available. + + %:0 + Initial word of last command. + + %:n + n-th argument of last command. + + %$ + Last argument of last command. + + %* + All but initial word of last command. + + %% + Last command. + + %stuf + Last command beginning with "stuf". + + %n + Repeat the n-th command. + + %-n + Repeat the n-th previous command. + + ^old^new + Replace "old" with "new" in previous command. Trailing spaces + are significant during substitution. Initial spaces are not + significant. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/incremental_ctl_verificationCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/incremental_ctl_verificationCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/incremental_ctl_verificationCmd.txt (revision 11) @@ -0,0 +1,170 @@ + + incremental_ctl_verification - Verify a set of CTL formulas by means of an + incremental model checking algorithm. + _________________________________________________________________ + + incremental_ctl_verification [-D ] [-e] [-h] [-n] \ [-s] [-t + ] [-v ] [-V ] [-x] + + Like model_check, incremental_ctl_verification verifies a set of CTL + formulas. It uses a system of abstraction and incremental refinement + that works for all of (fair)CTL, using over and underapproximations as + appropriate. See [1,2] for details. + + Incremental_ctl_verification (also known as Abs or Trasgo) works + especially well on large systems on which mc is too slow or runs out + of memory. Unlike amc, it can handle full CTL, not just the universal + or existential subsets of it. Also, fairness is supported with this + command, although it tends to be inefficient. Support for the + mu-calculus is not yet implemented. + + Before using incremental_ctl_verification, a flattened hierarchy + should be present. See `help init`. Using dynamic variable reordering + may be beneficial on large systems. See `help dynamic_var_ordering`. + + Fairness constraints can be applied using `read_fairness', as with mc. + When using incremental verification with fairness, there is no check + for unfair initial states. Please be aware that if there are no fair + initial states, all formulas starting with "A" will be trivially true. + Mc will tell you whether you have fair initial states. + + A typical use would be + incremental_ctl_verification -D2 + + For every formula, incremental verification will report whether it is + valid or invalid, or it returns an inconclusive result. A formula is + valid iff it holds for all initial states. An error trace is not + provided. For the people who are used to mc: The -r option is not + supported, incremental verification always reduces the fsm with + respect to individual formulas. The -c option is not supported either. + There is no sharing of subformulas between different formulas. + + Command options: + + -D + Specify extent to which don't cares are used to simplify the + MDDs. + + + 0: No Don't Cares used. + + 1: Use reachability information to compute the don't-care + set. Reachability is performed by formula. This is different + from mc, where reachability is performed only once. + + 2: Use reachability information, and minimize the transition + relation with respect to the `frontier set' (aggresive + minimization). + + The equivalent of mc -D3 is not implemented. + + -e + Compute the set of fair states (those satisfying the formula + EGfair TRUE) before the verification process and use the result + as care set. In certain cases this will speed up computation + when fairness constraints are present. In other cases it will + slow it down. + + -h + Print the command usage. + + -n + Try to prove the negation of every formula. In some cases it + may be easier to prove the negation of a formula than the + formula itself. For systems with only one initial state, a + formula is true iff its negation is false. Note that for + systems with multiple initial states a formula and its negation + can both be false. + + -s + Print a summary of statistics after the verification. + + -t + Time in seconds allowed to spend in the verification. The + default is infinity. + + -v + Specify verbosity level. Use 0 for no feedback (default), 1 for + more and 2 for maximum feedback. This option can not be used in + conjunction with -V. + + -V + Mask specifying type of information to be printed out while + verifying the formulas. This allows for a finer control than + -v. -V and -v cannot be used simultaneously. The mask is given + as a binary number, by taking the logical or of the following + binary values. One does not have to convert these numbers to + decimal. + + 1 number of primary inputs and flip-flops + + 10 labeled operational graph of the formulas + + 100 cpu-time for the computation in each vertex + + 1000 cubes of the function sat for each vertex + + 10000 cubes of the function goalSet for each vertex + + 100000 vertex data structure contents after evaluation + + 1000000 cubes in the care set for every evaluation + + 10000000 size of care set for every evaluation + + 100000000 number of states that satisfy every sub-formula + + 1000000000 number of overall reachable states + + 10000000000 cubes for every iteration of a fixed point + + 100000000000 size of the BDD in each iteration in a fix-point + + 1000000000000 labeled operational graph in dot format + + 10000000000000 number of envelope states + + 100000000000000 number of states to be refined + + 1000000000000000 size of the refinement operands + + 10000000000000000 cubes of the refinement operands + + 100000000000000000 Number of latches before and after + simplification + + 1000000000000000000 report partial progress (i.e. reach, + EG(true),...) + + 10000000000000000000 Begin/End refinement process + + 100000000000000000000 Size of goal set + + 1000000000000000000000 cubes of the goal set + + 10000000000000000000000 Contents of vertex after refinement + + -x + Perform the verification exactly. No approximation is done. + + + File containing the CTL formulas to be verified. + + Related "set" options: + + ctl_change_bracket + Vl2mv automatically converts "[]" to "<>" in node names, + therefore CTL parser does the same thing. However, in some + cases a user does not want to change node names in CTL parsing. + Then, use this set option by giving "no". Default is "yes". + + See also commands : model_check, incremental_ctl_verification + + 1. A. Pardo and G. Hachtel. Automatic abstraction techniques for + propositional mu-calculus model checking. In 9th Conference on + Computer Aided Verification (CAV'97). Springer-Verlag. Pages 12-23, + 1997. + + 2. A. Pardo and G. Hachtel. Incremental CTL model checking using BDD + subsetting. In 35th Design Automation Conference (DAC'98). pages + 457-462, 1998. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/init_verifyCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/init_verifyCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/init_verifyCmd.txt (revision 11) @@ -0,0 +1,30 @@ + + init_verify - create and initialize a flattened network for verification + _________________________________________________________________ + + init_verify [-b] [-h] + + This command initializes the system for verification, and is + equivalent to the command sequence flatten_hierarchy; static_order; + build_partition_mdds. If a command returns an error condition, then + the sequence is aborted. After init_verify has successfully executed, + various commands can be invoked, like model_check, compute_reach, + simulate, print_network_stats, and seq_verify. + + Please note that init_verify does not enable dynamic variable + reordering. Sometimes, though, this is needed to complete building the + partitions, and one has to initialize the verification by hand. + Similarly, it may be wise to turn on dynamic variable reordering after + init, so that further commands complete more easily. See the help page + for dynamic_var_ordering. + + Command options: + + -b + This option has no effect any longer. + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/iterative_model_checkCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/iterative_model_checkCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/iterative_model_checkCmd.txt (revision 11) @@ -0,0 +1,101 @@ + + iterative_model_check - Perform CTL model checking on an abstracted system + with automatic refinement algorithm. + _________________________________________________________________ + + iterative_model_check [-h] [-x] [-t ] [-v ]\ [-D + ] [-r ] [-i ] \ [-p ] [-g ] + + + Command options: + + -h + Print the command usage. + + -x + Perform the verification exactly. No approximation is done. + + -t + Time in seconds allowed for verification. The default is no + limit. + + -v + Specify verbosity level. Use 0 for no feedback (default), 1 for + more, and 2 for maximum feedback. + + -D + Specify extent to which don't cares are used to simplify the + MDDs. + + + 0: No don't cares used. This is the default. + + 1: Use reachability information to compute the don't-care + set. + + 2: Use reachability information, and minimize the transition + relation with respect to the `frontier set' (aggresive + minimization). + + 3: Use approximate reachability information. + + -r + Specify refinement method. + + + 0: Static scheduling by name sorting. Fast, easy, but less + accurate. + + 1: Static scheduling by latch affinity. Slow, but more + accurate. This is the default. + + -i + The number of state variables to be added for exact computation + at each iteration. The default is 4. + + -l + Type of lower-bound approximation method. + + + 0: Take a subset of each transition sub-relation by BDD + subsetting. + + 1: Take a subset by universal quantification. This is the + default. + + -p + Type of partition method. If 'build_partition_mdds' is already + invoked, this option is ignored. Notice that some next state + functions might not be available after iterative_model_checking + command is performed because of this option. + + + 0: Build all next state functions. Same as + 'build_partition_mdds'. This is the default. + + 1: Build the next state functions related to the formulas. + Build all next state functions that are necessary to prove + all formulas. + + 2: Build the next state functions incrementally. None of next + state functions are removed. + + -g + Type of operational graph. + + + 0: Negative Operational Graph. Good to prove a formula true. + + 1: Positive Operational Graph. Good to prove a formula false. + + 2: Mixed Operational Graph. Good to prove any formula, but it + may be slower. This is the default. + + + File containing the CTL formulas to be verified. + + Related "set" options: + + ctl_change_bracket + Vl2mv automatically converts "[]" to "<>" in node names, + therefore CTL parser does the same thing. However, in some + cases a user does not want to change node names in CTL parsing. + Then, use this set option by giving "no". Default is "yes". + + See also commands : model_check, incremental_ctl_verification + + 1. Jae-Young Jang, In-Ho Moon, and Gary D. Hachtel. Iterative + Abstraction-based CTL Model Checking. Design, Automation and Test in + Europe (DATE), 2000 + + 2. Jae-Young Jang. Iterative Abstraction-based CTL Model Checking. Ph. + D. Thesis. University of Colorado, 1999. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/lang_emptyCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/lang_emptyCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/lang_emptyCmd.txt (revision 11) @@ -0,0 +1,160 @@ + + lang_empty - perform language emptiness check on a flattened network + _________________________________________________________________ + + lang_empty [-b] [-d ] [-f ] [-h] [-i] [-s] [-t + ] [-v ] [-A ] [-D + ] [-S ] [-L ] + + Performs language emptiness check on a flattened network. The language + is not empty when there is a fair path starting at an initial state. + Before calling this command, the user should have initialized the + design by calling the command [1]init_verify. + + A fairness constraint can be read in by calling the [2]read_fairness + command; if none is specified, all paths are taken to be fair. + + The system is reduced automatically with respect to the set of + fairness constraints. If the language is not empty, a proof of this + fact is generated. A proof is a fair path starting at an initial + state. This is represented by a finite sequence of states starting at + an initial state (the stem) leading to a fair cycle, i.e., a cycle on + which there lies a state from each fairness condition. + + Command options: + + -b + Use backward analysis when performing debugging; the default is + to use forward analysis. This should be tried when the debugger + spends a large amount of time when creating a path to a fair + cycle. + + -d + Specify whether to demonstrate a proof of the language + non-emptiness + + dbg_level must be one of the following: + + 0 : No debugging performed. This is the default. + + 1 : Generate a path to a fair cycle. + + -f + Write the debugger output to dbg_file. + + -h + Print the command usage. + + -m + Pipe debugger output through the UNIX utility more. + + -i + Print input values causing transitions between states during + debugging. Both primary and pseudo inputs are printed. + + -s + Print debug output in the format accepted by the [3]simulate + command. + + -t + Specify the time out period (in seconds) after which the + command aborts. By default this option is set to infinity. + + -v + Specify verbosity level. This sets the amount of feedback on + CPU usage and code status. + + verbosity_level must be one of the following: + + 0 : No feedback provided. This is the default. + + 1 : Feedback on code location. + + 2 : Feedback on code location and CPU usage. + + -A + Specify whether the compositional SCC analysis algorithm, + Divide and Compose (DnC), is enabled for language emptiness + checking. The DnC algorithm first enumerates fair SCCs in an + over-approximated abstract model, and then successively refines + them in the more concrete models. Since non-fair SCCs can be + ignored in the more concrete models, a potentially large part + of the state space are pruned away early on when the + computations are cheap. + + le_method must be one of the following: + + 0 : no use of Divide and Compose (Default). + + 1 : use Divide and Compose. + + -D + Specify extent to which don't cares are used to simplify MDDs. + Don't cares are minterms on which the value taken by functions + does not affect the computation; potentially, these minterms + can be used to simplify MDDs and reduce time taken to perform + MDD computations. + + dc_level must be one of the following: + + 0 : No don't cares are used. + + 1 : Use unreachable states as don't cares. This is the default. + + -S + Specify schedule for GSH algorithm, which generalizes the + Emerson-Lei algorithm and is used to compute greatest + fixpoints. The choice of schedule affects the sequence in which + EX and EU operators are applied. It makes a difference only + when fairness constraints are specified. + must be one of the following: + + EL : EU and EX operators strictly alternate. This is the + default. + + EL1 : EX is applied once for every application of all EUs. + + EL2 : EX is applied repeatedly after each application of all + EUs. + + budget : a hybrid of EL and EL2. + + random : enabled operators are applied in (pseudo-)random + order. + + off : GSH is disabled, and the old algorithm is used instead. + The old algorithm uses the EL , but the termination checks are + less sophisticated than in GSH. + + -F + Use forward analysis in the computation of the greatest + fixpoint. This option is incompatible with -d 1 or higher and + can only be used with -D 1. + + -L + Use the lockstep algorithm, which is based on fair SCC + enumeration. + must be one of the following: + + off : Lockstep is disabled. This is the default. Language + emptiness is checked by computing a hull of the fair SCCs. + + on : Lockstep is enabled. + + all : Lockstep is enabled; all fair SCCs are enumerated instead + of terminating as soon as one is found. This can be used to + study the SCCs of a graph, but it is slower than the default + option. + + n : (n is a positive integer). Lockstep is enabled and up to n + fair SCCs are enumerated. This is less expensive than all , but + still less efficient than on , even when n = 1 . + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/html/init_verifyCmd.html + 2. file://localhost/projects/development/hsv/vis/common/doc/html/read_fairnessCmd.html + 3. file://localhost/projects/development/hsv/vis/common/doc/html/simulateCmd.html Index: vis_dev/vis-2.1/share/help/lsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/lsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/lsCmd.txt (revision 11) @@ -0,0 +1,18 @@ + + ls - list all the child nodes at the current node + _________________________________________________________________ + + ls [-h] [-R] + + Lists all the child nodes at the current node. + + Command options: + + -h + Print the command usage. + + -R + Call ls recursively all the way down to leaves. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/ltl2snfCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/ltl2snfCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/ltl2snfCmd.txt (revision 11) @@ -0,0 +1,16 @@ + + ltl2snf - Trnalate LTL formula into Separated Normal Form. + _________________________________________________________________ + + ltl2snf [-h] + + Command options: + + -f + The input file containing LTL formulae. + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/ltl_model_checkCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/ltl_model_checkCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/ltl_model_checkCmd.txt (revision 11) @@ -0,0 +1,228 @@ + + ltl_model_check - perform LTL model checking on a flattened network + _________________________________________________________________ + + ltl_model_check [-a ] [-b] [-d ] [-f + ] [-h] [-i] [-m] [-s] [-t ][-v + ] [-A ] [-D ] [-L + ] [-S ] [-F] [-X] [-Y] [-M] + + Performs LTL model checking on a flattened network. Before calling + this command, the user should have initialized the design by calling + the command [1]init_verify. Regardless of the options, no 'false + positives' or 'false negatives' will occur: the result is correct for + the given circuit. + + Properties to be verified should be provided as LTL formulae in the + file ltl_file. Note that the support of any wire referred to in a + formula should consist only of latches. For the precise syntax of LTL + formulas, see the [2]VIS CTL and LTL syntax manual. + + A formula passes iff it is true for all initial states of the system. + Therefore, in the presence of multiple initial states, if a formula + fails, the negation of the formula may also fail. + + If a formula does not pass, a (potentially partial) proof of failure + (referred to as a debug trace) is demonstrated. Fair paths are + represented by a finite sequence of states (the stem) leading to a + fair cycle, i.e. a cycle on which there is a state from each fairness + condition. Whether demostrate the proof or not can be specified (see + option -d). + + Command options: + + -a + Specify the algorithm used in LTL formula -> Buechi automaton + translation. + + ltl2aut_algorithm must be one of the following: + + 0: GPVW. + + 1: GPVW+. + + 2: LTL2AUT. + + 3: WRING (default). + + -b + Use boolean minimization during the LTL to Automaton + translation. + + -d + Specify whether to demonstrate a counter-example when the + system fails a formula being checked. + + dbg_level must be one of the following: + + 0: No debugging performed. dbg_level=0 is the default. + + 1: Generate a counter-example (a path to a fair cycle). + + -f + Write the debugger output to dbg_file. + + -h + Print the command usage. + + -i + Print input values causing transitions between states during + debugging. Both primary and pseudo inputs are printed. + + -m + Pipe debugger output through the UNIX utility more. + + -t + Specify the time out period (in seconds) after which the + command aborts. By default this option is set to infinity. + + -s + Print debug output in the format accepted by the [3]simulate + command. + + -v + Specify verbosity level. This sets the amount of feedback on + CPU usage and code status. + verbosity_level must be one of the following: + + 0: No feedback provided. This is the default. + + 1: Feedback on code location. + + 2: Feedback on code location and CPU usage. + + -A + Specify whether the compositional SCC analysis algorithm, + Divide and Compose (DnC), is enabled for language emptiness + checking. The DnC algorithm first enumerates fair SCCs in an + over-approximated abstract model, and then successively refines + them in the more concrete models. Since non-fair SCCs can be + ignored in the more concrete models, a potentially large part + of the state space are pruned away early on when the + computations are cheap. + + le_method must be one of the following: + + 0 : no use of Divide and Compose (Default). + + 1 : use Divide and Compose. + + -D + Specify extent to which don't cares are used to simplify MDDs + in model checking. Don't cares are minterms on which the value + taken by functions does not affect the computation; + potentially, these minterms can be used to simplify MDDs and + reduce the time taken to perform model checking. + dc_level must be one of the following: + + 0 : No don't cares are used. + + 1 : Use unreachable states as don't cares. This is the default. + + 2 : Use unreachable states as don't cares and in the EU + computation, use 'frontiers' for image computation. + + 3 : First compute an overapproximation of the reachable states + (ARDC), and use that as the cares set. Use `frontiers' for + image computation. For help on controlling options for ARDC, + look up help on the command: [4]print_ardc_options. Refer to + Moon, Jang, Somenzi, Pixley, Yuan, "Approximate Reachability + Don't Cares for {CTL} Model Checking", ICCAD98, and to two + papers by Cho et al, IEEE TCAD December 1996: one is for State + Space Decomposition and the other is for Approximate FSM + Traversal. + + -S + Specify schedule for GSH algorithm, which generalizes the + Emerson-Lei algorithm and is used to compute greatest + fixpoints. The choice of schedule affects the sequence in which + EX and EU operators are applied. It makes a difference only + when fairness constraints are specified. + must be one of the following: + + EL : EU and EX operators strictly alternate. This is the + default. + + EL1 : EX is applied once for every application of all EUs. + + EL2 : EX is applied repeatedly after each application of all + EUs. + + budget : a hybrid of EL and EL2 + + random : enabled operators are applied in (pseudo-)random + order. + + off : GSH is disabled, and the old algorithm is used instead. + The old algorithm uses the EL , but the termination checks are + less sophisticated than in GSH. + + -F + Use forward analysis in the computation of the greatest + fixpoint. This option is incompatible with -d 1 or higher and + can only be used with -D 1. + + -L + Use the lockstep algorithm, which is based on fair SCC + enumeration. + must be one of the following: + + off : Lockstep is disabled. This is the default. Language + emptiness is checked by computing a hull of the fair SCCs. + + on : Lockstep is enabled. + + all : Lockstep is enabled; all fair SCCs are enumerated instead + of terminating as soon as one is found. This can be used to + study the SCCs of a graph, but it is slower than the default + option. + + n : (n is a positive integer). Lockstep is enabled and up to n + fair SCCs are enumerated. This is less expensive than all , but + still less efficient than on , even when n = 1 . + + -X + Disable strength reduction (use different decision procedures + for strong, weak, and terminal automaton). Strength reduction + is the default. Refer to Bloem, Ravi, Somenzi, "Efficient + Decision Procedures for LTL Model Checking," CAV99. + + -Y + Disable incremental construction of the partition for (MxA). + Instead, build a new partition from the scratch. Incremental + construction of the partition is the default. + + -Z + Add arcs into the Buechi automaton by direct simulation + relation, to heuristically reduce the length of shortest + counter-example in model checking. Refer to Awedh and Somenze, + "Proving More Properties with Bounded Model Checking," CAV04. + + -M + Maximize (adding arcs to) Buechi automaton using Direct + Simulation. + + + File containing LTL formulas to be model checked. + + Related "set" options: + + ltl_change_bracket + Vl2mv automatically converts "[]" to "<>" in node names, + therefore CTL* parser does the same thing. However, in some + cases a user does not want to change node names in CTL* + parsing. Then, use this set option by giving "no". Default is + "yes". + + See also commands : model_check, approximate_model_check, + incremental_ctl_verification + __________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/html/init_verifyCmd.html + 2. file://localhost/projects/development/hsv/vis/common/doc/ctl/ctl/ctl.html + 3. file://localhost/projects/development/hsv/vis/common/doc/html/simulateCmd.html + 4. file://localhost/projects/development/hsv/vis/common/doc/html/print_ardc_optionsCmd.html Index: vis_dev/vis-2.1/share/help/ltl_to_autCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/ltl_to_autCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/ltl_to_autCmd.txt (revision 11) @@ -0,0 +1,88 @@ + + ltl_to_aut - translate LTL formulae into Buechi automata + _________________________________________________________________ + + ltl_to_aut [-f ] [-m ] [-o ] [-t + ] [-w] [-b] [-p] [-d] [-r] [-i] [-M] [-v ] + [-h] + + Translate the given LTL formulae into Buechi automata, and output the + automaton into a file. + + The translation algorithms are the same as the one used in + [1]ltl_model_check . However, more flexible combination of the options + can be used with this command. + + The automaton can be displayed on the screen and written into a file. + The format of the output can be dot, blifmv, verilog and smv. + + Command options: + + -f + The input file containing LTL formulae. + + -m + Specify the algorithm used in LTL formula -> Buechi automaton + translation algorithm. + + algorithm must be one of the following: + + 0: GPVW. + + 1: GPVW+. + + 2: LTL2AUT. + + 3: WRING (default). + + -o + Write the automata into this file. + + -t + Specify the output format of the automata. + + output_format must be one of the following: + + 0: dot. + + 1: blif_mv. + + 2: verilog. + + 3: all of the formats above (default). + + -w + Rewriting the formula before translation. + + -b + Boolean minimization during the translation. + + -p + Pruning the fair states in the Buechi automaton. + + -d + Direct-simulation minimization of the Buechi automaton. + + -r + Reverse-simulation minimization of the Buechi automaton. + + -i + Minimization based ont the I/O structural information. + + -M + Maximize (adding arcs to) Buechi automaton using Direct + Simulation. + + -v + Specify verbosity level. It must be one of the following: + 0,1,2,3. + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/html/ltl_model_checkCmd.html Index: vis_dev/vis-2.1/share/help/model_checkCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/model_checkCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/model_checkCmd.txt (revision 11) @@ -0,0 +1,340 @@ + + model_check - perform fair CTL model checking on a flattened network + _________________________________________________________________ + + model_check [-b] [-c] [-d ] [-f ] [-g + ] [-h] [-i] [-m] [-r] [-t ][-v + ] [-D ] [-F] [-S ] [-V] [-B] [-I] + [-C] + + Performs fair CTL model checking on a flattened network. Before + calling this command, the user should have initialized the design by + calling the command [1]init_verify. Regardless of the options, no + 'false positives' or 'false negatives' will occur: the result is + correct for the given circuit. + + Properties to be verified should be provided as CTL formulas in the + file ctl_file. Note that the support of any wire referred to in a + formula should consist only of latches. For the precise syntax of CTL + formulas, see the [2]VIS CTL and LTL syntax manual. + + Properties of the form AG f, where f is a formula not involving path + quantifiers are referred to as invariants; for such properties it may + be substantially faster to use the [3]check_invariant command. + + A fairness constraint can be specified by invoking the + [4]read_fairness command; if none is specified, all paths are taken to + be fair. If some initial states do not lie on a fair path, the model + checker prints a message to this effect. + + A formula passes iff it is true for all initial states of the system. + Therefore, in the presence of multiple initial states, if a formula + fails, the negation of the formula may also fail. + + If a formula does not pass, a (potentially partial) proof of failure + (referred to as a debug trace) is demonstrated. Fair paths are + represented by a finite sequence of states (the stem) leading to a + fair cycle, i.e. a cycle on which there is a state from each fairness + condition. The level of detail of the proof can be specified (see + option -d). + + Both backward (future tense CTL formulas) and forward (past tense CTL + formulas) model checking can be performed. Forward model checking is + based on Iwashita's ICCAD96 paper. Future tense CTL formulas are + automatically converted to past tense ones as much as possible in + forward model checking. + + Command options: + + -b + Use backward analysis when performing debugging; the default is + to use forward analysis. This should be tried when the debugger + spends a large amount of time when creating a path to a fair + cycle. This option is not compatible with forward model + checking option (-F). + + -c + Use the formula tree so that there is no sharing of + sub-formulae among the formulae in the input file. This option + is useful in the following scenario - formulae A, B and C are + being checked in order and there is sub-formula sharing between + A and C. If the BDDs corresponding to the shared sub-formula is + huge then computation for B might not be able to finish without + using this option. + + -d + Specify the amount of debugging performed when the system fails + a formula being checked. Note that it may not always be + possible to give a simple counter-example to show that a + formula is false, since this may require enumerating all paths + from a state. In such a case the model checker will print a + message to this effect. This option is incompatible with -F. + + dbg_level must be one of the following: + + 0: No debugging performed. dbg_level=0 is the default. + + 1: Debugging with minimal output: generate counter-examples for + universal formulas (formulas of the form AX|AF|AU|AG) and + witnesses for existential formulas (formulas of the form + EX|EF|EU|EG). States on a path are not further analyzed. + + 2: Same as dbg_level=1, but more verbose. (The subformulas are + printed, too.) + + 3: Maximal automatic debugging: as for level 1, except that + states occurring on paths will be recursively analyzed. + + 4: Manual debugging: at each state, the user is queried if more + feedback is desired. + + -f + Write the debugger output to dbg_file. This option is + incompatible with -F. Notes: when you use -d4 (interactive + mode), -f is not recommended, since you can't see the output of + vis on stdout. + + -g + Use guided search. The file hints_file contains a series of + hints. A hint is a formula that does not contain any temporal + operators, so hints_file has the same syntax as a file of + invariants used for check_invariant. The hints are used in the + order given to change the transition relation. In the case of + least fixpoints (EF, EU), the transition relation is conjoined + with the hint, whereas for greatest fixpoints the transition + relation is disjoined with the negation of the hint. If the + hints are cleverly chosen, this may speed up the computation + considerably, because a search with the changed transition + relation may be much simpler than one with the original + transition relation, and results obtained can be reused, so + that we may never have to do a complicated search with the + original relation. Note: hints in terms of primary inputs are + not useful for greatest fixpoints. See also: Ravi and Somenzi, + Hints to accelerate symbolic traversal. CHARME'99; Bloem, Ravi, + and Somenzi, Efficient Decision Procedures for Model Checking + of Linear Time Logic Properties, CAV'99; Bloem, Ravi, and + Somenzi, Symbolic Guided Search for CTL Model Checking, DAC'00. + + For formulae that contain both least and greatest fixpoints, + the behavior depends on the flag guided_search_hint_type. If it + is set to local (default) then every subformula is evaluated to + completion, using all hints in order, before the next + subformula is started. For pure ACTL or pure ECTL formulae, we + can also set guided_search_hint_type to global, in which case + the entire formula is evaluated for one hint before moving on + to the next hint, using underapproximations. The description of + the options for guided search can be found in the help page for + print_guided_search_options. + + model_check will call reachability without any guided search, + even if -g is used. If you want to perform reachability with + guided search, call rch directly. + + Incompatible with -F. + + -h + Print the command usage. + + -i + Print input values causing transitions between states during + debugging. Both primary and pseudo inputs are printed. This + option is incompatible with -F. + + -m + Pipe debugger output through the UNIX utility more. This option + is incompatible with -F. + + -r + Reduce the FSM derived from the flattened network with respect + to each formula being checked. By default, the FSM is reduced + with respect to the conjunction of the formulae in the input + file. If this option is used and don't cares are being used for + simplification, then subformula sharing is disabled (result + might be incorrect otherwise). + + The truth of a formula may be independent of parts of the + network (such as when wires have been abstracted; see + [5]flatten_hierarchy). These parts are effectively removed when + this option is invoked; this may result in more efficient model + checking. + + -t + Specify the time out period (in seconds) after which the + command aborts. By default this option is set to infinity. + + -v + Specify verbosity level. This sets the amount of feedback on + CPU usage and code status. + verbosity_level must be one of the following: + + 0: No feedback provided. This is the default. + + 1: Feedback on code location. + + 2: Feedback on code location and CPU usage. + + -B + Check for vacuously passing formulae using the algorithm of + Beer et al. (CAV97). The algorithm applies to a subset of ACTL + (w-ACTL) and replaces the smallest important subformula of a + passing property with either FALSE or TRUE depending on its + negation parity. It then applies model checking to the + resulting witness formula. If the witness formula also passes, + then the original formula is deemed to pass vacuously. If the + witness formula fails, a counterexample to it provides an + interesting witness to the original passing formula. See the + CAV97 paper for the definitions of w-ACTL, important + subformula, and interesting witness. In short, one of the + operands of a binary operator in a w-ACTL formula must be a + propositional formula. See also the -V option. + + -C + Compute coverage of all observable signals in a set of CTL + formulae using the algorithm of Hoskote, Kam, Ho, Zhao + (DAC'99). If the verbosity level (-v option) is equal to 0, + only the coverage stats are printed. If verbosity level is + greater than zero, then detailed information of the computation + at each step of the algorithm is also provided. Debug + information is provided in the form of states not covered for + each observable signal if the dbg_level (-d option) is greater + than 0. The number of states printed is set by the vis + environment variable 'nr_uncoveredstates'. By default the + number of states printed is 1. The value of nr_uncoveredstates + can be set using the set command. See also the -I option. + + -D + Specify extent to which don't cares are used to simplify MDDs + in model checking. Don't cares are minterms on which the values + taken by functions do not affect the computation; potentially, + these minterms can be used to simplify MDDs and reduce the time + taken to perform model checking. The -g flag for guided search + does not affect the way in which the don't-care conditions are + computed. + dc_level must be one of the following: + + 0 : No don't cares are used. + + 1 : Use unreachable states as don't cares. This is the default. + + 2 : Use unreachable states as don't cares and in the EU + computation, use 'frontiers' for image computation. + + 3 : First compute an overapproximation of the reachable states + (ARDC), and use that as the cares set. Use `frontiers' for + image computation. For help on controlling options for ARDC, + look up help on the command: [6]print_ardc_options. Refer to + Moon, Jang, Somenzi, Pixley, Yuan, "Approximate Reachability + Don't Cares for {CTL} Model Checking", ICCAD98, and to two + papers by Cho et al, IEEE TCAD December 1996: one is for State + Space Decomposition and the other is for Approximate FSM + Traversal. + + -F + Use forward model checking based on Iwashita's method in + ICCAD96. Future tense CTL formulas are automatically converted + to past tense ones as much as possible. Converted forward + formulas are printed when verbosity is greater than 0. Debug + options (-b, -d, -f, -i, and -m) are ignored with this option. + We have seen that forward model checking was much faster than + backward in many cases, also forward was much slower than + backward in many cases. + + -I + Compute coverage of all observable signals in a set of CTL + formulae using an improved algorithm of Jayakumar, Purandare, + Somenzi (DAC'03). If the verbosity level (-v option) is equal + to 0, only the coverage stats are printed. If verbosity level + is greater than zero, then detailed information of the + computation at each step of the algorithm is also provided. + Debug information is provided in the form of states not covered + for each observable signal if the dbg_level (-d option) is + greater than 0. The number of states printed is set by the vis + environment variable 'nr_uncoveredstates'. By default the + number of states printed is 1. The value of nr_uncoveredstates + can be set using the set command. Compared to the -C option, + this one produces more accurate results and deals with a larger + subset of CTL. + + -S + Specify schedule for GSH algorithm, which generalizes the + Emerson-Lei algorithm and is used to compute greatest + fixpoints. The choice of schedule affects the sequence in which + EX and EU operators are applied. It makes a difference only + when fairness constraints are specified. + must be one of the following: + + EL : EU and EX operators strictly alternate. This is the + default. + + EL1 : EX is applied once for every application of all EUs. + + EL2 : EX is applied repeatedly after each application of all + EUs. + + budget : a hybrid of EL and EL2. + + random : enabled operators are applied in (pseudo-)random + order. + + off : GSH is disabled, and the old algorithm is used instead. + The old algorithm uses the EL schedule, but the termination + checks are less sophisticated than in GSH. + + -V + Check for vacuously passing formulae with the algorithm of + Purandare and Somenzi (CAV2002). The algorithm applies to all + of CTL, and to both passing and failing properties. It says + whether a passing formula may be strengthened and still pass, + and whether a failing formula may be weakened and still fail. + It considers all leaves of a formula that are under one + negation parity (e.g., not descendants of a XOR or EQ node) for + replacement by either TRUE or FALSE. See also the -B option. + + -w This option invoked the algorithm to generate an error + trace divided into fated and free segements. Fate represents + the inevitability and free is asserted when there is no + inevitability. This can be formulated as a two-player + concurrent reachability game. The two players are the + environment and the system. The node_file is given To specify + the variables the are controlled by the system. + + -W + This option represents the case that all input variables are + controlled by system. + + -G + We proposed two algorithm to generate segemented counter example. They + are general and restrcited algorithm. Bu default we use + restricted algorithm. We can invoke general algorithm with -G + option. For more information, please check the STTT'04 paper of + Jin et al., "Fate and Free Will in Error Traces" + + + File containing CTL formulas to be model checked. + + Related "set" options: + + ctl_change_bracket + Vl2mv automatically converts "[]" to "<>" in node names, + therefore CTL parser does the same thing. However, in some + cases a user does not want to change node names in CTL parsing. + Then, use this set option by giving "no". Default is "yes". + + guided_search_hint_type + Switches between local and global hints (see the -g option, or + the help page for set). + + See also commands : approximate_model_check, + incremental_ctl_verification + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/html/init_verifyCmd.html + 2. file://localhost/projects/development/hsv/vis/common/doc/ctl/ctl/ctl.html + 3. file://localhost/projects/development/hsv/vis/common/doc/html/check_invariantCmd.html + 4. file://localhost/projects/development/hsv/vis/common/doc/html/read_fairnessCmd.html + 5. file://localhost/projects/development/hsv/vis/common/doc/html/flatten_hierarchyCmd.html + 6. file://localhost/projects/development/hsv/vis/common/doc/html/print_ardc_optionsCmd.html Index: vis_dev/vis-2.1/share/help/network_sweepCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/network_sweepCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/network_sweepCmd.txt (revision 11) @@ -0,0 +1,19 @@ + + network_sweep - sweeps the network to ensure that deterministic constants are + removed + _________________________________________________________________ + + network_sweep [-h][-v] + + This function performs a sweep on the given Ntk_Network_t. It + propagates all the deterministic constant nodes, and removes all + buffer nodes. It modifies the network. Command options: + + -h + Print the command usage. + + -v + Print debug information. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_aig_statsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_aig_statsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_aig_statsCmd.txt (revision 11) @@ -0,0 +1,26 @@ + + print_aig_stats - print statistics about the AND/INVERTER graph. + _________________________________________________________________ + + print_aig_stats [-h] [-n] + + Print the following statistics about the AND/INVERTER graph: + + Maximum number of nodes: the maximum number of nodes in the AND/ + INVERTER graph. + + Current number of nodes: the number of nodes in the AND/INVERTER + graph that are used. + + Note that build_partition_maigs must be called before this command. + + Command options: + + -n + Print the name of the nodes. + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_ardc_optionsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_ardc_optionsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_ardc_optionsCmd.txt (revision 11) @@ -0,0 +1,237 @@ + + print_ardc_options - print information about the ARDC options currently in + use + _________________________________________________________________ + + print_ardc_options [-h] [-H] + + Prints information about the current ARDC options. + + Command options: + + -h + Print the command usage. + + -H + Print the ARDC set command usage. + + Set parameters: The ARDC options are specified with the set command. + + ardc_traversal_method + Specify a method for approximate FSM traversal. + + method must be one of the following: + + 0 : MBM (machine by machine). + + 1 : RFBF(reached frame by frame). + + 2 : TFBF(to frame by frame). + + 3 : TMBM(combination of MBM and TFBF). + + 4 : LMBM(least fixpoint MBM, default). + + 5 : TLMBM(combination of LMBM and TFBF). + + ardc_group_size + Specify the number of latches per group for ARDCS. + + size must be a positive integer (default = 8). + + ardc_affinity_factor + Specify affinity factor to make a group for ARDCs. The + available factor is from 0.0(use only correlation) to 1.0(use + only dependency). + + affinity must be a positive real (default = 0.5). + + ardc_max_iteration + Specify the maximum iteration count during approximate FSM + traversal. Default is 0 which means infinite. + + iteration must be a positive integer or zero. + + ardc_constrain_target + Specify where image constraining will be applied to. + + target must be one of the following: + + 0 : constrain transition relation (default). + + 1 : constrain initial states. + + 2 : constrain both. + + ardc_constrain_method + Specify an image constraining method to compute ARDCs. + + method must be one of the following: + + 0 : restrict (default). + + 1 : constrain + + 2 : compact (currently supported by only CUDD) + + 3 : squeeze (currently supported by only CUDD) + + ardc_constrain_reorder + Specify whether to enable variable reorderings during + consecutive image constraining operations. + + method must be one of the following: + + yes : allow variable reorderings during consecutive image + constraining operations (default) + + no : don't allow variable reorderings during consecutive image + constraining operations + + ardc_abstract_pseudo_input + Specify when to abstract pseudo primary input variables out + from transition relation. + + method must be one of the following: + + 0 : do not abstract pseudo input variables + + 1 : abstract pseudo inputs before image computation (default) + + 2 : abstract pseudo inputs at every end of image computation + + 3 : abstract pseudo inputs at the end of approximate traversal + + ardc_decompose_flag + Specify whether to use decomposed approximate reachable states + or single conjuncted reachable states. + + method must be one of the following: + + yes : keep decomposed reachable stateses (default) + + no : make a conjunction of reachable states of all submachines + + ardc_projected_initial_flag + Specify which initial states is going to be used. + + method must be one of the following: + + yes : use projected initial states for submachine (default) + + no : use original initial states for submachine + + ardc_image_method + Specify image_mathod during computing reachable states of + submachines. + + method must be one of the following: + + monolithic : use monolithic image computation + + iwls95 : use iwls95 image computation (default) + + mlp : use mlp image computation + + tfm : use tfm image computation + + hybrid : use hybrid image computation + + ardc_use_high_density + Specify whether to use high density in computing reachable + states of submachines. + + method must be one of the following: + + yes : use High Density for reachable states of submachines + + no : use BFS for reachable states of submachines (default) + + ardc_reorder_ptr + Specify whether to reorder partitioned transition relation + after constraining fanin submachines. + + method must be one of the following: + + yes : whenever partitioned transition relation changes, + reorders partitioned transition relation + + no : no reordering of partitioned transition relation (default) + + ardc_fanin_constrain_mode + Specify which method will be used in constraining fanin + submachines. + + method must be one of the following: + + 0 : constrain w.r.t. the reachable states of fanin submachines + (default) + + 1 : constrain w.r.t. the reachable states of both fanin + submachines and itself + + ardc_create_pseudo_var_mode + Specify which method will be used to create pseudo input + variables of submachines. + + method must be one of the following: + + 0 : makes pseudo input variables with exact support (default) + + 1 : makes pseudo input variables from all state variables of + the other submachines + + 2 : makes pseudo input variables from all state variables of + fanin submachines + + ardc_lmbm_initial_mode + Specify which method will be used as initial states in LMBM + computation. + + method must be one of the following: + + 0 : use given initial states all the time + + 1 : use current reached states as initial states (default) + + 2 : use current frontier as initial states + + set ardc_mbm_reuse_tr + Specify whether to reuse already constrained transition + relation for next iteratrion in MBM. + + method must be one of the following: + + yes : use constrained transition relation for next iteration + + no : use original transition relation for next iteration + (default) + + ardc_read_group + Specify a filename containing grouping information + + filename containing grouping information + + ardc_write_group + Specify a filename to write grouping information + + filename to write grouping information + + ardc_verbosity + Specify the level of printing information during computing + ARDCs. + + verbosity must be 0 - 3 (default = 0). + + The default settings correspond to the fast variants of LMBM and MBM. + MBM never produces a more accurate approximation than LMBM for the + same state-space decomposition. However, the corresponding statement + does not hold for the fast versions. (That is, FastMBM will + occasionally outperform FastLMBM.) To get the slower, but more + accurate versions of LMBM and MBM use the following settings: + * set ardc_constrain_method 1 + * set ardc_constrain_reorder no + * set ardc_abstract_pseudo_input 0 + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_bdd_statsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_bdd_statsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_bdd_statsCmd.txt (revision 11) @@ -0,0 +1,22 @@ + + print_bdd_stats - print the BDD statistics for the flattened network + _________________________________________________________________ + + print_bdd_stats [-h] + + Print the BDD statistics for the flattened network. The MDDs + representing the functions of the network are themselves represented + by BDDs via an encoding of the multi-valued variables into binary + valued variables. The statistics given by this command depend on the + underlying BDD package with which VIS was linked. To get more + information about the statistics, consult the documentation for the + given BDD package. The commands flatten_hierarchy and static_order + must be invoked before this command. + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_fairnessCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_fairnessCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_fairnessCmd.txt (revision 11) @@ -0,0 +1,18 @@ + + print_fairness - print the fairness constraint of the flattened network + _________________________________________________________________ + + print_fairness [-h] + + Print the fairness constraint (i.e the set of Buchi conditions) + associated with the FSM of the flattened network. By default, the + flattened network has the single constraint TRUE, indicating that all + paths are fair. + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_guided_search_optionsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_guided_search_optionsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_guided_search_optionsCmd.txt (revision 11) @@ -0,0 +1,65 @@ + + print_guided_search_options - print information about guided_search_options + in use + _________________________________________________________________ + + print_guided_search_options [-h] + + Prints information about current Guided Search options. Guided search + is an alternate method to compute fixpoints by modifying the fixpoint + computation with restrictions. It is applicable to the compute_reach, + check_invariant and model_check commands (refer to their help pages on + the use of guided search). See also for details: Ravi and Somenzi, + Hints to accelerate symbolic traversal. CHARME'99; Bloem, Ravi, and + Somenzi, Efficient Decision Procedures for Model Checking of Linear + Time Logic Properties, CAV'99; Bloem, Ravi, and Somenzi, Symbolic + Guided Search for CTL Model Checking, DAC'00. Not allowed with -A 2 or + -i, and will only work with iwls95 or monolithic image methods. The + description of some options can be found in the help page for set. + + Command options: + + guided_search_hint_type + Choose from local (default) or global. If this flag is set to + local, then every subformula is evaluated to completion, using + all hints in order, before the next subformula is started. For + pure ACTL or pure ECTL formulae, we can also set + guided_search_hint_type to global, in which case the entire + formula is evaluated for one hint before moving on to the next + hint, using underapproximations. + + guided_search_underapprox_minimize_method + Choose from "constrain" and "and" (default). Sets the method + with which the transition relation is minimized when + underapproximations are used. The option constrain is + incompatible with hints that use signals other than inputs. + + guided_search_overapprox_minimize_method + Choose from "squeeze" and "ornot" (default). Sets the method + with which the transition relation is minimized when + underapproximations are used. The option squeeze is + incompatible with hints that use signals other than inputs. + Ornot implies that the transition relation will be disjoined + with the negation of the hint: T' = T + ~h, whereas squeeze + will find a small BDD between T and T'. + + guided_search_sequence + For compute_reach and check_invariant only. Set this flag to a + list of comma-separated integers i1,i2,...,in, with n at most + the number of hints that you specify . The k'th hint will be + used for ik iterations (images). A value of 0 causes the hint + to be applied to convergence. Not setting this option is like + setting it to 0,0,...,0. If length of the specified sequence is + less than the number of hints, the sequence is padded with + zeroes. + + Guided search also uses the High Density traversal options that are + germane to dead-ends. The relevant flags are hd_dead_end, + hd_dead_end_approx_method, hd_frontier_approx_threshold, + hd_approx_quality, hd_approx_bias_quality. Use help on the + print_hd_options command for explanation of these flags. If guided + search is used with HD using the -A 1 options in compute_reach and + check_invariant, the HD options are used by both HD and guided search. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_hd_optionsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_hd_optionsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_hd_optionsCmd.txt (revision 11) @@ -0,0 +1,181 @@ + + print_hd_options - print information about the HD options currently in use + _________________________________________________________________ + + print_hd_options [-h] + + Prints information about the current HD options. The HD method is an + alternate method to compute a least fixpoint and is provided with the + compute_reach and check_invariant commands. The method is described in + Ravi and Somenzi, ICCAD95. The command can be used only when compiled + with the CUDD package. + + Command options: + + -h + Print the command usage. + + Set parameters: The HD options are specified with the set command. + + hd_frontier_approx_method + This option specifes the method to approximate the frontier + set. + + Methods: + + remap_ua : (Default) The BDD approximation method of DAC98 + Ravi, Shiple, McMillan, Somenzi. + + biased_rua : Approximation method similar to remap_ua, but uses + a bias function. The bias function is set appropriate to the + context. + + under_approx : The BDD approximation method of Shiple's thesis. + + heavy_branch : The BDD approximation method of ICCAD95 Ravi, + Somenzi. + + short_paths : The BDD approximation method of ICCAD95 Ravi, + Somenzi. + + compress : An approximation method that runs short_paths first + and then remap_ua. + + hd_frontier_approx_threshold + This option specifes the size of the frontier to be used for + image computation. The threshold for the various methods is + approximate (not strictly adhered to). For the remap_ua and + biased_rua method, this threshold is a lower bound and the + default is 3500. For the short_paths and heavy_branch methods, + this threshold is an upper bound. Therefore, a default of 2000 + is set to obtain a meaningful result. Any value lower than 2000 + is corrected to this default. This value is also relevant for + dead-end computations. In a dead-end, the threshold for each + image computation (of a disjunct of Reached) is five times the + frontier approximation threshold. When the frontier + approximation threshold is 0, the threshold for each dead-end + image computation is 5000. + + hd_approx_quality + This option specifies the quality factor for the under_approx + and remap_ua methods. Default value is 1.0. The range is any + double value greater than 0. Smaller quality factors produce + smaller results. Meaningful values are between 1 and 2. + + hd_approx_bias_quality + This option specifies the quality factor for the biased_rua + method. Default value is 0.5. The range is any double value + greater than 0. Smaller quality factors produce smaller + results. Meaningful values are between 0 and 1. + + hd_dead_end + This option specifies the method used for dead-end computation. + A "dead-end" is characterized by an empty frontier. A dead-end + computation involves generating new states from the reached + set. + + Methods: + + brute_force : Computes the image of the entire reached set. May + be fatal if the reached set is very large. + + conjuncts : (Default) Computes the image of reached by + decomposing into parts. + + hybrid : Computes the image of a subset of reached. If no new + states, then the reaminder is decomposed in parts. + + hd_dead_end_approx_method + This option allows the specification of the approximation + method to use to compute the subset of Reached at the dead-end. + The threshold used is the same as hd_frontier_approx_threshold. + + For methods, refer hd_frontier_approx_method methods. Default + is remap_ua. + + hd_no_scrap_states + This allows the option of not adding the "scrap" states. Scrap + states are residues from the approximation of the frontier set. + Default is to add the scrap states. + + hd_new_only + This allows the option of adding considering only new states of + each iteration for image computation. The default is to take a + set in the interval of the new states and the reached set. + + hd_only_partial_image + This allows the option of HD with partial image computation + only (no approximation of the frontier set). Default is to + allow both partial images and approximation of the frontier + set. + + Partial Image options: + + hd_partial_image_method + This option allows the image computation to approximate the + image with the specified method. + + Methods: + + approx : (Default) Computes a partial image by + under-approximating the intermediate products of image + computation. + + clipping : Computes a partial image by "clipping" the depth of + recursion of the and-abstract computations during image + computation. + + hd_partial_image_threshold + This options allows the specification of a threshold (in terms + of bdd node size of the intermediate product) that will trigger + approximation of the intermediate product. Default is 200000. + This option has to be used in conjunction with + hd_partial_image_size. If the value of hd_partial_image_size is + larger than this option, then the approximation of the + intermediate size will be as large as the hd_partial_image_size + number. + + hd_partial_image_size + This options allows the specification of a size (in terms of + bdd node size of the intermediate product) that is the target + size of the approximated intermediate product. Default is + 100000. For the short_paths and heavy_branch methods, the size + of the approximation is corrected to 10000 if the size + specified is lower. This is because the short_paths and + heavy_branch methods consider this size as an upper bound on + the approximation. This option has to be used in conjunction + with hd_partial_image_threshold. If the value of + hd_partial_image_threshold is much larger than this option, + then the desired size will not be obtained as approximation may + not be triggered. + + hd_partial_image_approx + This options allows the specification of the method to be used + to approximate the intermediate product. + + For methods, refer hd_frontier_approx_method methods. Default + is remap_ua. + + hd_partial_image_approx_quality + This option specifies the quality factor for the under_approx + and remap_ua methods for partial image computation. Default + value is 1.0. Range of values is any double greater than 0. + Smaller quality factors produce smaller results. Meaningful + values are between 1 and 2. + + hd_partial_image_approx_bias_quality + This option specifies the quality factor for the biased_rua + method for partial image computation. Default value is 0.5. + Range of values is any double greater than 0. Smaller quality + factors produce smaller results. Meaningful values are between + 0 and 1. + + hd_partial_image_clipping_depth + This option allows the specification of the depth at which the + recursion can be clipped when _hd_partial_image_method_ is + clipping. Range of values is between 0 and 1. The clipping + depth is then calculated as the specified fraction of the + number of variables. Default is 0.4. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_hierarchy_statsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_hierarchy_statsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_hierarchy_statsCmd.txt (revision 11) @@ -0,0 +1,20 @@ + + print_hierarchy_stats - print the statistics of the current node + _________________________________________________________________ + + print_hierarchy_stats [-h] [-R] + + Prints the statistics of the current node. Note that it is not + necessary to invoke flatten_hierarchy first to create a network. + + Command options: + + -h + Print the command usage + + -R + Print statistics for nodes recursively all the way down to + leaves. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_hybrid_optionsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_hybrid_optionsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_hybrid_optionsCmd.txt (revision 11) @@ -0,0 +1,294 @@ + + print_hybrid_options - print information about the hybrid image computation + options currently in use + _________________________________________________________________ + + print_hybrid_options [-h] [-H] + + Prints information about the current hybrid image computation options. + + Command options: + + -h + Print the command usage. + + -H + Print the hybrid image computation set command usage. + + Set parameters: The hybrid image computation options are specified + with the set command. + + hybrid_mode + Specify a mode how to start hybrid computation. + + mode must be one of the following: + + 0 : start with only transition function and build transition + relation on demand + + 1 : start with both transition function and relation (default) + + 2 : start with only transition relation. Only this mode can + deal with nondeterminism. + + hybrid_tr_split_method + Specify a method to choose a splitting variable in hybrid mode + = 2. + + method must be one of the following: + + 0 : use support (default) + + 1 : use estimate BDD size + + hybrid_build_partial_tr + Specify whether to build full or partial transition relation in + hybrid mode = 2. This option is used to use less memory. When + we use partial transition relation, for the variables excluded + in the transition relation, we build each bit transition + relation on demand. When nondeterminism exists in the circuit, + this can not be used. + method must be one of the following: + + yes : build partial transition relation + + no : build full transition relation (default) + + hybrid_partial_num_vars + Specify how many variables are going to be excluded in building + partial transition relation. The default is 8. + + hybrid_partial_method + Specify a method to choose variables to be excluded in building + partial transition relation. + + method must be one of the following: + + 0 : use BDD size (default) + + 1 : use support + + hybrid_delayed_split + Specify a method whether to split transition relation + immediately or just all at once before AndExist. + + method must be one of the following: + + yes : apply splitting to transition relation at once + + no : do not apply (default) + + hybrid_split_min_depth + Specify the minimum depth to apply dynamic hybrid method. If a + depth is smaller than this minimum depth, just split. The + default is 1. + + hybrid_split_max_depth + Specify the maximum depth to apply dynamic hybrid method. If a + depth is bigger than this maximum depth, just conjoin. The + default is 5. + + hybrid_pre_split_min_depth + Specify the minimum depth to apply dynamic hybrid method in + preimage computation. If a depth is smaller than this minimum + depth, just split. The default is 0. + + hybrid_pre_split_max_depth + Specify the maximum depth to apply dynamic hybrid method in + preimage computation. If a depth is bigger than this maximum + depth, just conjoin. The default is 4. + + hybrid_lambda_threshold + Specify a threshold in floating between 0.0 and 1.0 to + determine to split or to conjoin after computing variable + lifetime lambda for image computation. If lambda is equal or + smaller than this threshold, we conjoin. Otherwise we split. + The default is 0.6 + + hybrid_pre_lambda_threshold + Specify a threshold in floating between 0.0 and 1.0 to + determine to split or to conjoin after computing variable + lifetime lambda for preimage computation. If lambda is equal or + smaller than this threshold, we conjoin. Otherwise we split. + The default is 0.65 + + hybrid_conjoin_vector_size + If the number of components in transition function vector is + equal or smaller than this threshold, we just conjoin. This + check is performed before computing lambda. The default is 10. + + hybrid_conjoin_relation_size + If the number of clusters in transition relation is equal or + smaller than this threshold, we just conjoin. This check is + performed before computing lambda. The default is 2. + + hybrid_conjoin_relation_bdd_size + If the shared BDD size of transition relation is equal or + smaller than this threshold, we conjoin. This check is + performed before computing lambda. The default is 200. + + hybrid_improve_lambda + When variable lifetime lambda is bigger than lambda threshold, + if the difference between previous and current lambda is equal + or smaller than this threshold, then we conjoin. The default is + 0.1. + + hybrid_improve_vector_size + When variable lifetime lambda is bigger than lambda threshold, + if the difference between the previous and current number of + components in transition function vector is equal or smaller + than this threshold, then we conjoin. The default is 3. + + hybrid_improve_vector_bdd_size + When variable lifetime lambda is bigger than lambda threshold, + if the difference between the previous and current shared BDD + size of transition function vector is equal or smaller than + this threshold, then we conjoin. The default is 30.0. + + hybrid_decide_mode + Specify a method to decide whether to split or to conjoin. + + method must be one of the following: + + 0 : use only lambda + + 1 : use lambda and also special checks to conjoin + + 2 : use lambda and also improvement + + 3 : use all (default) + + hybrid_reorder_with_from + Specify a method to reorder transition relation to conjoin in + image computation, whether to include from set in the + computation. + + method must be one of the following: + + yes : reorder relation array with from to conjoin (default) + + no : reorder relation array without from to conjoin + + hybrid_pre_reorder_with_from + Specify a method to reorder transition relation to conjoin in + preimage computation, whether to include from set in the + computation. + + method must be one of the following: + + yes : reorder relation array with from to conjoin + + no : reorder relation array without from to conjoin (default) + + hybrid_lambda_mode + Specify a method to decide which variable lifetime to be used + for image computation. + + method must be one of the following: + + 0 : total lifetime with ps/pi variables (default) + + 1 : active lifetime with ps/pi variables + + 2 : total lifetime with ps/ns/pi variables + + hybrid_pre_lambda_mode + Specify a method to decide which variable lifetime to be used + for preimage computation. + + method must be one of the following: + + 0 : total lifetime with ns/pi variables + + 1 : active lifetime with ps/pi variables + + 2 : total lifetime with ps/ns/pi variables (default) + + 3 : total lifetime with ps/pi variables + + hybrid_lambda_with_from + Specify a method to compute variable lifetime lambda, whether + to include from set in the computation. + + method must be one of the following: + + yes : include from set in lambda computation (default) + + no : do not include + + hybrid_lambda_with_tr + Specify a method to compute variable lifetime lambda, whether + to use transition relation or transition function vector, when + both exist. + + method must be one of the following: + + yes : use transition relation (default) + + no : use transition function vector + + hybrid_lambda_with_clustering + Specify a method whether to include clustering to compute + variable lifetime lambda. + + method must be one of the following: + + yes : compute lambda after clustering + + no : do not cluster (default) + + hybrid_synchronize_tr + Specify a method to keep transition relation. This option is + only for when hybrid mode is 1. + + method must be one of the following: + + yes : rebuild transition relation from function vector whenever + the function vector changes + + no : do not rebuild (default) + + hybrid_img_keep_pi + Specify a method to build forward transition relation. + + method must be one of the following: + + yes : keep all primary input variables in forward transition + relation. + + no : quantify out local primary input variables from the + transition relation. (default) + + hybrid_pre_keep_pi + Specify a method to build backward transition relation. + + method must be one of the following: + + yes : keep all primary input variables in backward transition + relation and preimages. + + no : quantify out local primary input variables from the + transition relation. (default) + + hybrid_pre_canonical + Specify a method whether to canonicalize the function vector + for preimage computation. + + method must be one of the following: + + yes : canonicalize the function vector + + no : do not canonicalize (default) + + hybrid_tr_method lt;methodgt; + Specify an image method for AndExist operation in hybrid + method. + + method must be one of the following: + + iwls95 (default) + + mlp + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_img_infoCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_img_infoCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_img_infoCmd.txt (revision 11) @@ -0,0 +1,28 @@ + + print_img_info - print information about the image method currently in use + _________________________________________________________________ + + print_img_info [-b] [-f] [-h] + + Prints information about the image computation method currently being + used by the FSM. This includes the particular values of parameters + used by the method for initialization. If the image information does + not exist, then this command forces the information to be computed. If + none of the flags (-b or -f) is set, forward transition relation is + computed. + + Command options: + + -b + Compute the transition relation for backward image computation + (if needed). + + -f + Compute the transition relation for forward image computation + (if needed). + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_ioCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_ioCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_ioCmd.txt (revision 11) @@ -0,0 +1,15 @@ + + print_io - print the names of inputs/outputs in the current node + _________________________________________________________________ + + print_io [-h] + + Prints the names of inputs/outputs in the current node. + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_latchesCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_latchesCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_latchesCmd.txt (revision 11) @@ -0,0 +1,15 @@ + + print_latches - print the names of latches in the current node + _________________________________________________________________ + + print_latches [-h] + + Prints the names of latches in the current node. + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_mlp_optionsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_mlp_optionsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_mlp_optionsCmd.txt (revision 11) @@ -0,0 +1,72 @@ + + print_mlp_options - print information about the MLP image computation options + currently in use + _________________________________________________________________ + + print_mlp_options [-h] [-H] + + Prints information about the current MLP image computation options. + + Command options: + + -h + Print the command usage. + + -H + Print the MLP image computation set command usage. + + Set parameters: The MLP image computation options are specified with + the set command. + + mlp_cluster + Specify a method for clustering. + + method must be one of the following: + + 0 : linear clustering + + 1 : affinity based tree clustering (default) + + mlp_reorder + Specify a method for reordering after clustering for image + computation. + + method must be one of the following: + + 0 : no reordering after clustering (default) + + 1 : reorder using MLP after clustering (inside) + + 2 : reorder using MLP after clustering (outside) + + 3 : reorder using IWLS95 after clustering + + mlp_pre_reorder + Specify a method for reordering after clustering for preimage + computation. + + method must be one of the following: + + 0 : no reordering after clustering (default) + + 1 : reorder using MLP after clustering (inside) + + 2 : reorder using MLP after clustering (outside) + + 3 : reorder using IWLS95 after clustering + + mlp_postprocess + Specify when to do postprocessing. + + method must be one of the following: + + 0 : no postprocessing (default) + + 1 : do postprocesing after ordering + + 2 : do postprocesing after clustering or reordering + + 3 : do both 1 and 2 + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_modelsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_modelsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_modelsCmd.txt (revision 11) @@ -0,0 +1,16 @@ + + print_models - list all the models and their statistics + _________________________________________________________________ + + print_models [-h] + + Lists all the models and prints information about the number of + variables, tables, latches etc. in them. + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_networkCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_networkCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_networkCmd.txt (revision 11) @@ -0,0 +1,41 @@ + + print_network - print information about the flattened network + _________________________________________________________________ + + print_network [-f] [-h] [-t] + + Prints the name of the flattened network, and information about each + node. For each node, prints the following: + + name: the name of the node + + mdd: MDD id (-1 is uninitialized) + + type: one of combinational, primary-input, pseudo-input, latch, or + shadow + + derived attributes: list of derived attributes of the node + + See the ntk documentation for more information on types and + attributes. The following is an example describing information + associated with a node. + small.latch_in: mdd=2, combinational; data-input comb-output + + + The flattened name of the node is "small.latch_in", its MDD id is 2, + it is of type combinational, and it is both a data input to a latch, + and a combinational output. + + Command options: + + -f + Print the fanins and fanouts of each node. + + -h + Print the command usage. + + -t + Print table statistics for those nodes having tables. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_network_dotCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_network_dotCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_network_dotCmd.txt (revision 11) @@ -0,0 +1,28 @@ + + print_network_dot - print a dot description of the flattened network + _________________________________________________________________ + + print_network_dot [-h] + + Write a file in the format taken by the tool dot depicting the + topology of the network. Dot is a tool that given a description of a + graph in a certain format it produces a postscript print of the graph. + For more information about dot look in + [1]http://www.research.att.com/orgs/ssr/book/reuse. Once a dot file is + produced with this command, the shell command dot -Tps >.ps will + produce the postscript file depicting the network. + + If no argument is specified on the command line, the description is + written to the standard output. + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. http://www.research.att.com/orgs/ssr/book/reuse Index: vis_dev/vis-2.1/share/help/print_network_statsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_network_statsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_network_statsCmd.txt (revision 11) @@ -0,0 +1,43 @@ + + print_network_stats - print statistics about the flattened network + _________________________________________________________________ + + print_network_stats [-h] + + Prints the following statistics about the flattened network: + + name: the name of the flattened network + + combinational: the number of nodes which have a table defining the + function of the node (excludes pseudo inputs) + + primary inputs: the number of primary input nodes of the flattened + network + + primary outputs: the number of primary output nodes of the flattened + network + + latches: the number of (multi-valued) latches + + pseudo inputs: the number of pseudo input nodes of the flattened + network + + constants: the number of combinational nodes that implement a + multi-valued constant + + edges: the number of fanouts in the network (e.g. if the output of a + node is used in two places, this contributes two to the sum) + + Note that flatten_hierarchy must be called before this command. + + Example output: + small combinational=2 pi=2 po=0 latches=1 pseudo=0 const=1 edges=4 + + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_partitionCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_partitionCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_partitionCmd.txt (revision 11) @@ -0,0 +1,29 @@ + + print_partition - print the "dot" format describing the partition graph + _________________________________________________________________ + + print_partition [-h] + + Write a file in the format taken by the tool dot. Dot is a tool that, + given a description of a graph in a certain format, produces a + postscript print of the graph. For more information about dot look in + [1]http://www.research.att.com/sw/tools/graphviz. + + If no argument is specified on the command line, the output is written + to the standard output. + + Command options: + + -h + Print the command usage. + + + Name of file where the partition is to be written in "dot" + format. + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. http://www.research.att.com/sw/tools/graphviz Index: vis_dev/vis-2.1/share/help/print_partition_aig_dotCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_partition_aig_dotCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_partition_aig_dotCmd.txt (revision 11) @@ -0,0 +1,29 @@ + + print_partition_aig_dot - print a dot description of the AND/INVERTER graph + that was built for the flattened network + _________________________________________________________________ + + print_partition_aig_dot [-h] + + Write a file in the format taken by the tool dot depicting the + topology of the AND/INVERTER graph. Dot is a tool that given a + description of a graph in a certain format it produces a postscript + print of the graph. For more information about dot look in + [1]http://www.research.att.com/orgs/ssr/book/reuse. Once a dot file is + produced with this command, the shell command dot -Tps >.ps will + produce the postscript file depicting the network. + + If no argument is specified on the command line, the description is + written to the standard output. + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. http://www.research.att.com/orgs/ssr/book/reuse Index: vis_dev/vis-2.1/share/help/print_partition_statsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_partition_statsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_partition_statsCmd.txt (revision 11) @@ -0,0 +1,30 @@ + + print_partition_stats - print statistics about the partition graph + _________________________________________________________________ + + print_partition_stats [-h] [-n] + + Print statistics about the partition currently attached to the + network, such as: + + Method used to build the partition. + + Number of sink vertices. + + Number of source vertices. + + Total number of vertices. + + Number of shared MDD nodes used to represent the functions. + + Command options: + + -h + Print the command usage. + + -n + Print the name of the network nodes represented by vertices in + the partition. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/print_tfm_optionsCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/print_tfm_optionsCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/print_tfm_optionsCmd.txt (revision 11) @@ -0,0 +1,320 @@ + + print_tfm_options - print information about the transition function based + image computation options currently in use + _________________________________________________________________ + + print_tfm_options [-h] [-H] + + Prints information about the current transition function based image + computation options. + + Command options: + + -h + Print the command usage. + + -H + Print the transition function based image computation set + command usage. + + Set parameters: The transition function based image computation + options are specified with the set command. + + tfm_split_method + Specify a splitting method. + + method must be one of the following: + + 0 : input splitting (default) + + 1 : output splitting + + 2 : mixed (input split + output split) + + tfm_input_split + Specify an input splitting method. + + method must be one of the following: + + 0 : support before splitting (default) + + 1 : support after splitting + + 2 : estimate BDD size after splitting + + 3 : top variable + + tfm_pi_split_flag + Specify whether to allow primary input variables to be chosen + as a splitting variable. + + method must be one of the following: + + yes : choose either state or input variable as splitting + variable (default) + + no : choose only state variable as splitting variable + + tfm_range_comp + Specify a method whether to convert image to range + computataion. + + method must be one of the following: + + 0 : do not convert to range computation + + 1 : convert image to range computation (default) + + 2 : use a threshold (tfm_range_threshold, default for hybrid) + + tfm_range_threshold + This option is valid only when the tfm_range_comp is set to 2. + This threshold is used to determine whether to convert to range + computation by comparing the shared BDD size of function vector + after constraining w.r.t. from set to its original size. If the + size is less than the origianl size * , then we convert to + range computation. The default value is 10. + + tfm_range_try_threshold + This option is valid only when the tfm_range_comp is set to 2. + This option is used to disable checking the condition if it + fails to convert consecutively times. The default value is 2. + + tfm_range_check_reorder + Specify whether to force to call variable reordering after + constraining function vector w.r.t. from set and before + checking the condition. + + method must be one of the following: + + yes : force to reorder before checking tfm_range_threshold + + no : do not reorder (default) + + tfm_tie_break_mode + Specify a tie breaking method when we have a tie in choosing a + splitting variable in input and output splitting method. + + method must be one of the following: + + 0 : the closest variable to top (default) + + 1 : the smallest BDD size after splitting + + tfm_output_split + Specify an output splitting method. + + method must be one of the following: + + 0 : smallest BDD size (default) + + 1 : largest BDD size + + 2 : top variable + + tfm_turn_depth + This option is valid only when mixed or hybrid method is + chosen. This is used to determine when to switch to the other + method at which depth of recursion. The default is 5 for tfm + and -1 for hybrid method. + + tfm_find_decomp_var + Specify a method whether to try to find a decomposable variable + (meaning articulation point) first if any. + + method must be one of the following: + + yes : try to find a decomposable variable (articulation point) + + no : do not try (default) + + tfm_sort_vector_flag + Specify a method whether to sort function vectors to increase + cache performance. + + method must be one of the following: + + yes : sort function vectors (default for tfm) + + no : do not sort (default for hybrid) + + tfm_print_stats + Specify a method whether to print statistics for cache and + recursions at the end of job. + + method must be one of the following: + + yes : print statistics + + no : do not print (default) + + tfm_print_bdd_size + Specify a method whether to print the BDD size of all + intermediate product. + + method must be one of the following: + + yes : print BDD size + + no : do not print (default) + + tfm_split_cube_func + Specify a method whether to try to find a cube in function + vector in input splitting, then perform output splitting once + w.r.t. the cube. + + method must be one of the following: + + yes : try cube splitting + + no : do not try (default) + + tfm_find_essential + Specify a method whether to try to find essential variables in + from set. If a variable occurs in all cubes of a BDD, the + variable is called essential. If exists, minimize both function + vector and the from set with the essential cube. + + method must be one of the following: + + 0 : do not try (default) + + 1 : try to find essential variables + + 2 : on and off dynamically + + tfm_print_essential + Specify a method whether to print information about essential + variables. + + method must be one of the following: + + 0 : do not print (default) + + 1 : print only at end + + 2 : print at every image computation + + tfm_use_cache + Specify whether to use an image cache. + + method must be one of the following: + + 0 : do not use cache (default for hybrid) + + 1 : use cache (default) + + 2 : store all intermediate results + + tfm_global_cache + Specify a method whether to use one global image cache, or one + image cache per each machine. + + method must be one of the following: + + yes : use only one global cache (default) + + no : use one cache per machine + + tfm_max_chain_length + This option is used to set the maximum number of items in a + slot for conflict. The default is 2. + + tfm_init_cache_size + This option is used to set the initial cache size. The number + is recommended to be a prime number. Currently, we do not + resize the cache size, but for the future extension, we named + initial. The default is 1001. + + tfm_auto_flush_cache + Specify a method to flush image cache. + + method must be one of the following: + + 0 : flush cache only when requested + + 1 : flush cache at the end of image computation (default) + + 2 : flush cache before reordering + + tfm_compose_intermediate_vars + Specify a method whether to compose all intermediate variables. + + method must be one of the following: + + yes : compose all + + no : do not compose (default) + + tfm_pre_split_method + Specify a splitting method for preimage computation. + + method must be one of the following: + + 0 : input splitting (domain cofactoring, default) + + 1 : output splitting (constraint cofactoring) + + 2 : mixed (input split + output split) + + 3 : substitution + + tfm_pre_input_split + Specify an input splitting method for preimage computation. + + method must be one of the following: + + 0 : support before splitting (default) + + 1 : support after splitting + + 2 : estimate BDD size after splitting + + 3 : top variable + + tfm_pre_output_split + Specify an output splitting method for preimage computation. + + method must be one of the following: + + 0 : smallest BDD size (default) + + 1 : largest BDD size + + 2 : top variable + + tfm_pre_dc_leaf_method + Specify a method to switch to another method to complete + preimage computation in domain cofactoring method when no more + splitting variable exist. + + method must be one of the following: + + 0 : substitution (default) + + 1 : constraint cofactoring + + 2 : hybrid + + tfm_pre_minimize + Specify a method whether to minimize transition function vector + w.r.t a chosen function in constraint cofactoring method. This + option is recommended to use when image cache is disabled, + because even though this option can minimize the BDD size of + function vector, this may degrade cache performance. + + method must be one of the following: + + yes : minimize function vector w.r.t. a chosen function in + constraint cofactoring + + no : do not minimize (default) + + tfm_verbosity + Specify the level of printing information related with + transition function method. + + verbosity must be 0 - 2 (default = 0). + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/pwdCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/pwdCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/pwdCmd.txt (revision 11) @@ -0,0 +1,15 @@ + + pwd - print out the full path of the current node from the root node + _________________________________________________________________ + + pwd [-h] + + Prints out the full path of the current node from the root node. + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/quitCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/quitCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/quitCmd.txt (revision 11) @@ -0,0 +1,19 @@ + + quit - exit VIS + _________________________________________________________________ + + quit [-h] [-s] + + Stops the program. Does not save the current network before exiting. + + Command options: + + -h + Print the command usage. + + -s + Free all the memory before quitting. This is slower, and is + used for finding memory leaks. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/read_blifCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/read_blifCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/read_blifCmd.txt (revision 11) @@ -0,0 +1,45 @@ + + read_blif - read a blif file + _________________________________________________________________ + + read_blif [-c] [-e ] [-h] [-v] + + Reads a file in blif format into VIS. All the synthesis-specific + constructs of blif are ignored. Internally the blif file is + automatically translated into an equivalent blif-mv file, which is + then read in with read_blif_mv. Note that, currently this command + cannot read blif files which describe mapped circuits. To get around + this problem, please use SIS synthesis tool to generate an ordinary + blif file. Command options: + + -c + Semi-canonicalize all the tables in each model. See the + documentation of [1]read_blif_mv for details. + + -e + If set, the program reads in a blif file using the encoding + information specified in the encoding_file_name. Only the + current hnode is altered in the process, and hence the read is + incremental. Typically the encoding file is written out by a + write_blif operation. Note that this option cannot be used if + no file has been read in. Internally, the encoding file is used + in combination with the blif file to create a blif-mv file + which is compatible with the I/O interface of the current node. + + -h + Print the command usage. + + -v + If set, the program prints out all the unused variables in the + blif file. + + + Name of a blif file to be read in. This can be the output + written by SIS. in the blif file. + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/html/read_blif_mvCmd.html Index: vis_dev/vis-2.1/share/help/read_blif_mvCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/read_blif_mvCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/read_blif_mvCmd.txt (revision 11) @@ -0,0 +1,53 @@ + + read_blif_mv - read a blif-mv file + _________________________________________________________________ + + read_blif_mv [-c] [-h] [-r] [-v] + + Reads a blif-mv file into VIS. The existing hierarchy for the blif-mv + file previously read in is overwritten upon a successful read. If an + error is detected while reading a file, the previous hierarchy is + preserved. + + Command options: + + -c + Semi-canonicalize all the tables in each model. The + canonicalization process, assigns a linear order to the table + rows and columns, based on the value of their entries. For a + table with binary valued entries, this value is exactly the + number of 1's in the row or column. Once this linear order is + assigned, the rows and columns of the table are swapped so as + to order rows and columns with higher value at the beginning of + the corresponding row or column order. It is called + semi-canonicalization because two tables representing the same + logic function need not have the same canonical form. + + -h + Print the command usage. + + -r + If set, the program replaces the subhierarchy rooted at the + current node with a new hierarchy specified by a blif-mv file. + The file to be read in has to be compatible with the i/o + interface of the current hnode (the same i/o names with the + same domains). Otherwise, the current hierarchy is kept intact. + If -r is not specified, the entire hierarchy is replaced, not + just the subhierarchy at the current node. + + -v + If set, the program prints out all the unused variables in the + blif-mv file. Otherwise, only a warning is printed that some + variables are not used. + + + blif-mv file to be read in. + + For more information on blif-mv, refer to the [1]blif-mv manual. + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. http://www-cad.eecs.berkeley.edu/Respep/Research/vis/doc/blifmv/blifmv/blifmv.html Index: vis_dev/vis-2.1/share/help/read_fairnessCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/read_fairnessCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/read_fairnessCmd.txt (revision 11) @@ -0,0 +1,53 @@ + + read_fairness - read a fairness constraint + _________________________________________________________________ + + read_fairness [-h] + + Read a fairness constraint, and associate this constraint with the FSM + of the flattened network. An existing constraint associated with the + FSM is lost. Subsequent verification procedures are performed relative + to the new constraint. Note that, by default, the flattened network + has the constraint TRUE, indicating that all paths are fair. The + command build_partition_mdds (or init_verify) must have already been + invoked on the flattened network, before this command is called. + + Currently, only Buchi constraints are supported. A Buchi fairness + constraint is given by a list of individual Buchi conditions, B1, B2, + ..., Bk, where Bi is a set of FSM states. A state is fair if there + exists an infinite path from that state that intersects each Bi + infinitely often. + + The conditions are specified by a file containing at least one CTL + formula (see the [1]VIS CTL and LTL syntax manual). In particular, Bi + is defined by a CTL formula, which represents the set of states that + makes the formula true (in the absence of any fairness constraint). + References to signal names in the network should be made using the + full hierarchical names. Note that the support of any wire referred to + in a formula should consist only of latches. Each CTL formula is + terminated by a semicolon. + + Example: In the three conditions below, B1 contains those states that + have a next state where cntr.out is RED, B2 contains those where + timer.active is 1, and B3 contains those states for which every path + from the state has tlc.request=1 until tlc.acknowledge=1. + + EX(cntr.out=RED); + (timer.active=1); + A(tlc.request=1 U tlc.acknowledge=1); + + + Command options: + + -h + Print the command usage. + + + File containing the set of Buchi conditions. + _________________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. file://localhost/projects/development/hsv/vis/common/doc/ctl/ctl/ctl.html Index: vis_dev/vis-2.1/share/help/read_orderCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/read_orderCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/read_orderCmd.txt (revision 11) @@ -0,0 +1,42 @@ + + read_order - Read and reorder variable order from a file. + _________________________________________________________________ + + read_order [-h] [-v] [] + + This command reads variable order from a file and reorder variable + order according to the order. This command can be used any time after + static_order command. However, the users should notice that there is a + possibility to get BDD blowups during this command. + + Command options: + + -h + Print the command usage. + + -g + Specify whether to group present and next state variables or + not. + + 0: Do not group. + + 1: Do group (default). + + -v + Print debug information. + + + A file containing names of network nodes, used to specify a + variable ordering. The name of a node is the full hierarchical + path name, starting from the current hierarchical node. A node + should appear at most once in the file. Each node name should + appear at the beginning of a new line, with no white space + preceeding it. The end of a node name is marked by white space, + and any other text on the rest of the line is ignored. Any line + starting with "#" or white space is ignored. See write_order + for a sample file. Note that the variable ordering cannot be + specified at the bit-level; it can only be specified at the + multi-valued variable level. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/read_verilogCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/read_verilogCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/read_verilogCmd.txt (revision 11) @@ -0,0 +1,31 @@ + + read_verilog - read a verilog file + _________________________________________________________________ + + read_verilog [-c] [-h] [-u] [-F] + + Reads a verilog file into VIS. Internally the file is transformed into + an equivalent blif-mv file, which is then read into VIS. The existing + hierarchy for the blif-mv file previously read in is overwritten upon + a successful read. If an error is detected while reading a file, the + previous hierarchy is preserved. + + Command options: + + -c + Use explicit clocking. + + -h + Print the command usage. + + -u + Turn off loop unroling. + + -F + Ignore all timing. + + + Verilog file to be read in. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/regression_testCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/regression_testCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/regression_testCmd.txt (revision 11) @@ -0,0 +1,362 @@ + + regression_test - perform regression test with the information given in + arguments file + _________________________________________________________________ + + regression_test [-s ] + + Invokes two set of execution of vis to compare the performance and to + check sanity of each execution. Then make a set of tables summarizing + results, such as CPU sec, memoty usage and fail/pass of model_check, + etc.. This command will read a description of the regression test to + be performed from the argument file, which is configuartion file. + Besides the configuration file, one needs to prepare two template + files and a design list. We now describe these in turn. As running + example we shall use a regression test that compares check_invariant + with and without guided search. + + The configuration file for our example is shown below, delimited by + lines of dashes (which are not part of the file). The order in which + the lines appear in the file is immaterial. A line beginning with '#' + is a comment, and is ignored by regression_test. + ---------------------------------------------------------------------- + DesignDirectory : /projects/development/hsv/vis/Regression + DesignList : ./DesignListInv + ReferenceVis : /usr/local/vis/i686-o/vis-cu + ReferenceVisNickName : BFS + ReferenceOutputDir : ./result_inv_bfs + RefCommandTemplate : ./TemplateRefInv + bRefRun : FALSE + NewVis : /usr/local/vis/i686-o/vis-cu + NewVisNickName : GS + NewOutputDir : ./result_inv_gs + bNewRun : FALSE + NewCommandTemplate : ./TemplateNewInv + bCompareCounterExample : TRUE + bDefaultInitCommand : FALSE + ResultForPerformance : ./BFSvsGS.tex + CompareItem : cpu : elapse: + CompareItem : mem : Memory in use: + CompareItem : bdd : Peak number of live nodes: + ---------------------------------------------------------------------- + + Each line defines a parameter of the regression test. + + * DesignDirectory gives the path to the directory where the input + files are stored. In this case, we are using the central repository + under ~hsv/vis/Regression. It's typically a good idea to store the + results of regression tests in a separate place from the input files. + In our examples, the results are stored in the current directory. + + * DesignList gives the name of the file containing the list of test + cases to run. Each line consists of several white space-separated + fields describing the files making up the test case. The first field + is a path to the files relative to DesignDirectory. The second field + is the test case name. The remaining fields are file names. More on + this later, when we talk about the design list file in detail. + + * ReferenceVis and NewVis give paths to the two versions of vis to be + compared in the regression test. They can be the same, as in this case + in which both are the "nightly build." + + * ReferenceVisNickName and NewVisNickName are two identifiers that + are used in the LaTeX tables to refer to the two versions that are + compared. Short mnemonics are preferable. Avoid using underscores, + because they currently cause trouble with LaTeX. + + * ReferenceOutputDir and NewOutputDir give the names of the + directories in which the results of the runs will be stored. In each + of these directories, vis_reg will create a directory for each test + case. The names of these directories are the test case names taken + from the design list. Therefore, these names must be unique. + + * RefCommandTemplate and NewCommandTemplate are the templates from + which vis_reg produces the scripts used to run the test cases. The + mechanism used to derive the scripts from the templates and the design + list is described in detail when we talk about the template files. The + two templates can be the same file. + + * bRefRun and bNewRun are flags that tell vis_reg which of the two + sets of experiments should be run (if any). If one set of results has + been already computed, the corresponding flag should be set to FALSE. + If both flags are FALSE, vis_reg simply regenerates the summary table. + + * bCompareCounterExample is a flag that instructs vis_reg to scan the + output files for counterexamples and record their lengths. For each + counterexample, stem and cycle length are found. If this flag is set + to FALSE, counterexamples are not analyzed and the corresponding table + is not produced. + + * bDefaultInitCommand is a flag that, if set to TRUE, instructs + vis_reg to generate a default set of commands to initialize each vis + run. This option allows one to save some time in preparing the + templates, at the expense of some flexibility. + + * ResultForPerformance is the name of the LaTeX file to which vis_reg + writes the summary of the experiments. Its format is described in + detail later. + + * CompareItem specifies one item to be monitored in the experiments. + Multiple CompareItem lines may appear in the configuration file. Each + one consists of two items: an identifier, and a pattern. The + identifier is used in the table to denote the item, whereas the + pattern is used to extract from the output files the information to be + put in the tables. + + In our example, we declare + + CompareItem : mem : Memory in use: + + We instruct regression_test to search for a line beginning with + "Memory in use:" in each section of the output file. The token + immediately following the occurrence of the pattern is the data item + to be put in the table under "mem." so that the resulting LaTeX table + contains data on the memmory usage. + + Since the output file is divided into sections delimited by strings + "CommandBegin" and "CommandEnd." (See below.), each section is + searched for the patterns specified by the CompareItem declarations. + If the pattern is matched, the item appears in the table for that + section. + + To run the regression_test we need configuration file, template file + and design list. In case of template file, we need a two template + files, since we want to compare two different run of vis. The syntax + of the two templates is identical. We describe the template for "new," + but all we say applies to "ref" as well. The "new" template for our + example is shown below. + ---------------------------------------------------------------------- + + echo CommandBegin init + read_model + flt + order_vars + part + time + print_bdd_stats + echo CommandEnd init + echo CommandBegin ci + set hd_frontier_approx_threshold 3500 + ci -t 3600 -g $HintFile $InvFile + time + print_bdd_stats + echo CommandEnd ci + echo CommandBegin ci_cex + ci -d 1 -i -t 3600 -g $HintFile $InvFile + time + print_bdd_stats + echo CommandEnd ci_cex + ---------------------------------------------------------------------- + + Before proceeding to its discussion, it is instructive to examine the + script that regression_test produces from it for one test case. + regression_test relies on vis's shell variables and aliases to + customize the script. The script consists of a preamble in which + variables and aliases are defined, followed by one or more sections, + each corresponding to a major step in the experiment. Statistics will + be collected for each step separately. Our example has three sections, + whose names are "init," "ci," and "ci_cex." The names of the sections + are arbitrary, except that the automatically generated initialization + section is always called "init." + ---------------------------------------------------------------------- + + set vis_stdout ./result_inv_gs/am2901/am2901.out + set vis_stderr ./result_inv_gs/am2901/am2901.err + set BlifFile /projects/development/hsv/vis/Regression/Am2901/am2901.mv + set OrdFile /projects/development/hsv/vis/Regression/Am2901/am2901.ord + set InvFile /projects/development/hsv/vis/Regression/Am2901/am2901.inv + set HintFile + /projects/development/hsv/vis/Regression/Am2901/am2901.hint + alias read_model "rlmv $BlifFile" + alias set_fairness " " + alias order_vars "so -s input_and_latch $OrdFile" + echo CommandBegin init + read_model + flt + order_vars + part + time + print_bdd_stats + echo CommandEnd init + echo CommandBegin ci + set hd_frontier_approx_threshold 3500 + ci -t 3600 -g $HintFile $InvFile + time + print_bdd_stats + echo CommandEnd ci + echo CommandBegin ci_cex + ci -d 1 -i -t 3600 -g $HintFile $InvFile + time + print_bdd_stats + echo CommandEnd ci_cex + quit + ---------------------------------------------------------------------- + + The variables and the aliases are defined by vis_reg by examining the + fields of the test case description in the design file. + regression_test uses file extensions to identify file types. (E.g., + .ord indicates an order file in "input_and_latch" format.) A full list + of extensions is given below. + + regression_test defines variables for all the file types actually + available for the experiment, and only for those. It also defines + three aliases that provide some flexibility in mixing different + experiments in the same batch. + + For instance, "read_model" is defined as either + + read_blif_mv $BlifFile + + or + + read_blif $BlifFile + + depending on whether the design list specifies a .mv file or a .blif + file as model file. + + The definition of "order_vars" takes into account whether an order + file is available or not. Finally, the definition of "set_fairness" + depends on whether a .fair file is available. This allows one to mix + model checking experiments for which no fairness condition is + specified to experiments that do require fairness conditions. + + When bDefaultInitCommand is FALSE, the script is simply the preamble, + followed by the unchanged template, follows by the "quit" command, + which is always automatically added. + + When bDefaultInitCommand is TRUE, regression_test also adds an + automatically generated "init" section between the preamble and the + template. This default section is equivalent to + + echo CommandBegin init + read_model + flt + order_vars + part + time + print_bdd_stats + echo CommandEnd init + + Notice that one has no control over dynamic reordering during the + initialization phase if bDefaultInitCommand is TRUE. + + The template should refer to the defined aliases and variables to + tailor itself to each test case. Notice, however, that one is not + forced to use "order_vars." If one wants to always use vis's static + ordering algorithm, (s)he can simply use "so" instead of "order_vars." + Likewise, one can decide to always ignore fairness constraints by not + including "set_fairness." + + On the other hand, it is usually a bad idea to explicitly include + commands like + + read_blif_mv + read_blif + so -s input_and_latch + read_fairness + + in the templates, because they limit the range of test cases to which + they can be applied. + + As we said, the templates, and hence the scripts, are divided in + sections. Each section begins and ends with an "echo" command. These + commands write delimiters to the output file, which are used by + vis_reg to define the scope of the pattern searches. It is important + that the tag specified in corresponding pairs of CommandBegin and + CommandEnd be the same. + + The calls to "print_bdd_stats" are typically used to add to the output + files the information requested by the CompareItem declarations. It is + a good idea to specify timeouts for potentially expensive steps. + + The design list file has one line for each test case. A master design + list is in ~hsv/vis/Regression/DesignList. Specific design lists can + be obtained by commenting out or deleting lines from this master list. + One can also create an entirely new list according to the following + rules. + + Lines starting with '#' are interpreted as comments and are skipped, + as in all files read by vis_reg. + + A test case is a named collection of related files that can be used to + run one or more experiments. As mentioned before, each line consists + of white space-separated fields. The first is a (relative) path, while + the second is the collection name. The remaining fields specify the + files in the collection. + + The smallest collection will specify one .mv or one .blif file. This + file is called the "model file," and should always appear in the third + field of the line. If the model file is the only file specified, one + can run reachability analysis, but not much more. Vis_reg understands + the file extensions shown in the following table. For each extension, + the variable bound to the file name and a short explanation are given. + + .mv $BlifFile model file to be read with rlmv + .blif $BlifFile model file to be read with rl + .ord $OrdFIle order file to be read with so -s input_and_latch + .inv $InvFile invariant file to be read with ci + .ctl $CtlFile property file to be read with mc + .fair $FairFile fairness file to be read with rf + .hint $HintFile hint file to be read with the -g option of mc, ci, and + rch + + Only one file of each type can appear in the collection defining one + test case. If multiple property files, or different order files are + available for one model file, one has to create two test cases for + that model. Different models, on the other hand, can share property + files, order files, and so on. The master design list provides + examples for both these situations. + + It is not possible to specify both a .mv file and a .blif file for one + test case. There must be exactly one model file per test case. + + As was mentioned before, it is important that the name of a test case + be unique in the entire batch used for a regression test. On the other + hand, several test cases may share the same directory, and often do + when they have some files in common. + + The result summary created by regression_test is a LaTeX file + consisting of several tables. There is one table with performance + stats for each section of the output file. In addition, there is an + optional counterexample comparison table that summarizes PASS/FAIL + information for the properties and the length of counterexamples. For + each failing property, the length of the stem and the length of the + cycle (if applicable) are reported. + + Each performance table consists of one column for the test case name, + followed by as many groups of three columns as there are CompareItem + declarations applicable to the section that the table summarizes. + + Each group of three columns gives the data for the reference run, the + data for the new run, and the improvement. Vis_reg regards smaller as + better. Hence, the improvement is positive if the CPU time, memory + occupation, and so on, have decreased from the reference run to the + new run. The improvement is computed as + + (value(ref) - value(new)) / value(ref) * 100. + + Notice that this formula tends to make "new" look bad. for instance, + if new is twice as fast as ref, the improvement is 50%. If ref is + twice as fast, however, the "improvement" is -100%. + + The results of each test case are stored in a separate directory, + whose name is obtained by concatenating ReferenceOutputDir (or + NewOutputDir) with the test case name. Each directory stores three + files, whose names are given by the test case name concatenated with + .src, .out, and .err. + + * test_case_name.src stores the script used to run vis. + * test_case_name.out stores what vis writes to vis_stdout. + * test_case_name.err stores what vis writes to vis_stderr. + + One has to be careful, because vis_reg will overwrite these results + directories without warning if run twice with the same + ReferenceOutputDir or NewOutputDir and bRefRun or bNewRun set to TRUE. + + With '-s' option, you can create c-shell script file to be able to run + experiments in shell. We add this option to solve the problem that are + happened when your template file contains child-process by system + call. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/res_verifyCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/res_verifyCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/res_verifyCmd.txt (revision 11) @@ -0,0 +1,250 @@ + + res_verify - Verifies a combinational circuit using residue arithmetic. + _________________________________________________________________ + + res_verify [-b] [-d ] [-h] -i [-m ] [-n + ] {-o | -O} [-s ] [-t ] + + This command performs residue verification between two networks. The + method used is based on residue arithmetic and the Chinese Remainder + theorem; it is described in [1] + ftp://vlsi.colorado.edu/pub/fmcad96.ps. Verification is performed by + interpreting the outputs of the circuits as integers and verifying the + residues of the outputs with respect to a set of moduli. The choice of + moduli is directed by the Chinese Remainder Theorem in order to prove + equivalence of the two circuits. This method works well with + multipliers and possibly other arithmetic circuits (due to its + dependence on residue arithmetic). For the same reason, it is + necessary to specify an output order which determines how the outputs + are interpreted as integers. Discretion should be exercised in + applying this method to general combinational circuits. + + Residue verification is available only if vis is linked with the cu + BDD package. (This is the default.) It reads both blif and blif-mv + files. However, it does NOT support multi-valued variables. Residue + verification is primarily for combinational verification, but may be + applied to sequential circuits with the same state encoding. The latch + outputs are then considered to be combinational inputs of the circuits + and the latch inputs and reset are considered to be combinational + outputs of the circuits. + + There are two ways to perform residue verification in this package. As + a first option, two files describing two networks, the specification + and the implementation, (in the same format, blif or blif-mv, see + option -b) are given in the command line; the procedure tries to + verify the equivalence of the combinational outputs as functions of + the combinational inputs. + + vis> res_verify -o network.order -i network1.blif -s network2.blif + + In this case both networks are read in, flattened and the verification + is performed between the combinational outputs of both networks. The + -i option denotes the implementation file and the -s option denotes + the specification file. The -o option specifies the order of outputs + for the circuits (See Command Options below for detailed explanation). + + A second way to perform the verification is as follows. The + specification network is taken from a hierarchy already read into VIS. + Then the res_verify command compares that specification against an + implementation network obtained from the file in the command line. Any + previous verification, performed with the specification, can be used + towards the next verification task only if the same implementation + circuit is being verified against and the same number of outputs have + been directly verified with sucess in the previous attempt. The + typical sequence of commands given to perform such task would be: + + vis> read_blifmv network1.mv + vis> flatten_hierarchy + vis> res_verify -o network.order -i network2.mv + + If the hierarchy has been read but no flattened network exists at the + current node, the command will return without doing anything. If one + of the networks used is the one in the current node in the hierarchy, + then the information regarding the verification process will be stored + in that network. + + Note: It is important to keep the specification distinct from the + implementation because most parameters specified for the res_verify + command are with respect to the specification. For example, the output + order is specified with respect to the specification. The file that is + read in first in the second format, is considered to be the + specification. + + There is an option to directly verify some outputs by building the + BDDs for the corresponding outputs of the 2 circuits. In that case, if + the user wants to use an initial ordering, the only way to do it is + the second method and reading in the network, one may specify the + initial order using static order. + + The command does not repeat residue verification if the same + specification-implementation pair have been verified with success and + the same number of directly verified outputs have been verified in the + previous attempt. + + Relevant flags to be set using the set command: + + residue_verbosity + Default is 0, turns on verbosity to the desired level between 0 + and 5. + + residue_ignore_direct_verified_outputs + Default 0 (FALSE). If 1, then ignores directly verified outputs + during residue verification. + + residue_top_var + Default "msb". The 2 possible values are "msb" and lsb"; this + puts the most/least significant bit near the top or bottom of + the residue decision diagram. + + residue_autodyn_residue_verif + Default 0 (FALSE). If 1, turns on dynamic reordering during + residue verification. + + residue_residue_dyn_method + Default "groupsift". Specifies the method for dynamic + reordering during residue verification. Other methods supported + are "same" (same as before), "none", "random", "randompivot", + "sift", "siftconverge", "symmsiftconverge", "symmsift", + "window2", "window3", "window4", "window2converge", + "window3converge", "window4converge", "groupsift", + "groupsiftconverge", "anneal", "genetic", "linear", + "linearconverge", "exact". + + residue_autodyn_direct_verif + Default 0 (FALSE). If 1, turns on dynamic reordering during + direct verification. + + residue_direct_dyn_method + Default "groupsift". Specifies the method for dynamic + reordering during direct verification. Other methods supported + are "same" (same as before), "none", "random", "randompivot", + "sift", "siftconverge", "symmsiftconverge", "symmsift", + "window2", "window3", "window4", "window2converge", + "window3converge", "window4converge", "groupsift", + "groupsiftconverge", "anneal", "genetic", "linear", + "linearconverge", "exact". + + residue_layer_schedule + Default "alap". This is a flag to specify the layering strategy + of the networks. The 2 options are "asap" (as soon as possible) + and "alap" (as late as possible). + + residue_layer_size + Default largest layer size in network. Specifies the maximum + layer size that can be composed in (relevant for vector + composition only). + + residue_composition_method + Default "vector". Specifies the composition method to be used + in composing the network into the residue ADD. The options are + "vector", "onegate", "preimage" and "superG". + + Command Options: + + -b + If this option is specified, the specification and the + implementation files read are considered to be in blif-mv + format. Default is blif format. + + -d n + This option specifies the number of outputs to be directly + verified. That is, for n least significant outputs of the + circuit, this command performs like comb_verify. The actual + outputs are read off the output order array. Since the output + order array is specified starting with the MSB, the number of + directly verified outputs will be a chunk of the bottom part of + the output order array. The option "-d all" sets the number of + directly verified outputs to the number of combinational + outputs in the circuit i.e., all outputs are directly verified. + The direct verification for small BDD sizes is faster and + overall reduces the number of primes to be used in residue + verification. In general, one output is checked at a time + against the corresponding output of the other network and + consequently , this method may be fast and use less memory + resources. + IMPORTANT: It is possible to specify an initial order for the + direct verification. This is done by reading in the + specification file and using static_order to specify the + initial order. The implementation will get the same order as + the specification. When specifying the initial order, one must + be careful not to specify the -s option in the res_verify + command. The -s option reads in the specification file again + and the initial order is lost. + + -h + Print the command usage. + + -i + Implementation network to perform verification against. The + file must be in blif format unless -b is specified, in which + case the file is taken to be in blif-mv format. The blif format + is the default. + + -m + Optional file name specifying the matching pair of output names + between the two networks. If not specified, it is assumed that + all outputs have identical names. This option is useful when + verifying two circuits whose output names do not match. The + file will give pairs of the form name1 name2 to be considered + as corresponding outputs in the verification process. In each + pair, name1 may belong to the specification and name2 to the + implementation or vice-versa. The matching procedure is not + capable of dealing with some special situations. For example, + when two outputs, one of each network have the same name, they + must correspond to the same output. Partial orders may not be + specified. + + -n + Optional file name specifying the matching pair of input names + between the two networks. If not specified, it is assumed that + all inputs have identical names. This option is useful when + verifying two circuits whose input names do not match. The file + will give pairs of the form name1 name2 to be considered as + corresponding inputs in the verification process. In each pair, + name1 may belong to the specification and name2 to the + implementation or vice-versa. The matching procedure is not + capable of dealing with some special situations. For example, + when two inputs, one of each network have the same name, they + must correspond to the same input. Partial orders may not be + specified. + + -o + Required file specifying output order, starting with the MSB. + The file must be a list of output names separated by spaces. + The list must belong to the specification network and must + contain a full order i.e., must contain all the combinational + output names. It is advisable to use the -o option as far as + possible to specify the order of the outputs.See also -O + option. + + -O + This option specifies whether the res_verify command should + generate a default order for the outputs. If the -o option is + not used, this option must be specified. The default order + generated is random and is NOT the same as the input files. The + set of outputs for the output order may be generated by using + the print_network command to write the network into a file and + extract the node name from the lines containing the word + "comb-output". The set of outputs can then be ordered as + required. + It is advisable to use the -o option as far as possible to + specify the order of the outputs. The -o option overrides the + -O option. See also -o option. + + -s + Specification network. This network will be taken as the + specification of the circuit. The result of the computation + will be stored in this network. If this network is not + provided, the current node of the hierarchy will be taken. The + file must contain a blif description of a circuit unless the + option -b is specified, in which case the file is considered in + blif-mv format. If two networks are specified in the command + line, both of them must have the same format, either blif or + blif-mv. The blif format is the default. + + -t + Execution time in seconds allowed for verification before + aborting. The default is no limit. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/reset_fairnessCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/reset_fairnessCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/reset_fairnessCmd.txt (revision 11) @@ -0,0 +1,17 @@ + + reset_fairness - reset the fairness constraint + _________________________________________________________________ + + reset_fairness [-h] + + Remove any existing fairness constraint associated with the FSM of the + flattened network, and impose a single constraint, TRUE, indicating + that all states are "accepting". + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/restruct_fsmCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/restruct_fsmCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/restruct_fsmCmd.txt (revision 11) @@ -0,0 +1,140 @@ + + restruct_fsm - Restructre the STG of a finite state machine to reduce power + dissipation. + _________________________________________________________________ + + restruct_fsm [-D ] [-d ] [-E] [-F ] + [-f ] [-h] [-N] [-o ] [-p ] [-s + ] [-t ] [-v] + + This command implements an STG restructuring algorithm that exploits + the existence of equivalent states to decrease power dissipation, not + necessarily by collapsing the equivalence states, but by redirecting + transitions in the state transition graph (STG). This algorithm is + based on monolitic transition relation. The complexity of the + algorithm in general increases with an increase in the size of the + STG. The number of states and edges in the STG are exponential in the + number of state variables and primary inputs. The memory utilization + is not necessarily exponential due to symbolic representation of the + STG. For more details see, "A Symbolic Algorithm for Low-Power + Sequential Synthesis", ISLPED 97. This command works only if VIS is + compiled with CUDD package. The algorithm can handle circuits + described in both BLIF and BLIF-MV format. However, multi-valued + variables are not supported. Also, the final synthesized circuit + (network implementation of the restructured STG) is available only in + BLIF format. The sequential circuit should have a single initial + state. A network should have been created for the circuit and its + primary inputs and state variables assigned BDD ids prior to the + invocation of this command. A network can be created by the command + flatten_hierarchy and command static_order assigns BDD ids to the + input and state variables. The command proceeds by creating BDDs for + the outputs and next state functions. An FSM data structure is then + created on which subsequent operations are performed. After the STG is + restructured a new circuit is synthesized by symbolic factorization + based on Zero-Suppressed Decision Diagrams (ZDDs). The final + synthesized circuit is a file in BLIF format with ".ml.blif" as the + extension. + + The typical command flow in vis is the following: + vis> read_blif foo.blif + vis> flatten_hierarchy + vis> static_order + vis> dynamic_var_ordering -e sift + vis> restruct_fsm + + In the above case example, the final synthesized circuit is + MODEL.ml.blif if the name of the design in foo.blif is MODEL. + Command options: + + -A + Allow realignment (during symbolic factorization) of ZDDs after + BDD reordering and vice versa. This option is effective when + only one of the BDD or ZDD variable reordering is enabled. + + -D + Specify the output file name for synthesized circuit. File + extension is not necessary. By default, the model name of the + circuit is used. For example, -D foobar, will result in + foobar.ml.blif + + -d + Choose a divisor. See synthesize_network for more details. + + -E + Print the number of equivalence classes in the FSM. + + -F + File with primary input probabilities, one per line. input_name + + + -f + Choose a method for factorization. See synthesize_network for + more details. + + -h + Print command usage. + + -i + Specify the prefix to be used to generate names for internal + nodes during synthesis. By default, the prefix is "_n". + + -N + Expand the reachable set R to include those states which are + equivalent to R but not reachable. The default is not to + include such states. + + -o + File to output BDD variable ordering after the restructured + circuit is synthesized. + + -R + Allow reordering in BDD and/or ZDD variables during symbolic + factorization stage. + + 0 : (default) No reordering neither in BDD nor in ZDD. + + 1 : Allows reordering only in BDD, not in ZDD. + + 2 : Allows reordering only in ZDD, not in BDD. + + 3 : Allows reordering both in BDD and in ZDD. + + -s + Heuristic to perform restructuring. Consider a fragment of an + STG containing states A,B and C and an edge from A to B. Let B + and C be equivalent. Since B and C are equivalent, it is + possible to change the transition between A and B to A and C. + In the more general case, the choice can be driven by different + cost constraints. The following are the heuristics: + ham : Hamming distance based heuristic. An edge is chosen that + reduces the Hamming distance (or state bit transitions) between + the states. + fanin : Fanin oriented heuristic. A representative from the + equivalence class is chosen that reduces the total average + state bit switching on the incoming edges. + faninout : Fanin-Fanout oriented heuristic. A representative + from the equivalence class is chosen that reduces the total + average state bit switching on the incoming as well as outgoing + edges. + cproj : A simple C-Projection. A representative from the + equivalence class is chosen which is closest to the initial + state. The distance d(x,y) is defined as: + sum_{i=0}^{N-1}(|x_i - y_i| cdot 2^{N-i-1}). + + -T + Try to share more nodes during symbolic factorization. Existing + divisors are checked for potential reuse before extracting + divisors from the current boolean function. + + -t + Time in seconds allowed to complete the command. If the + computation time goes above that limit, the process is aborted. + The default is no limit. + + -v + Turn on verbosity. + + See also command : synthesize_network + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/seq_verifyCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/seq_verifyCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/seq_verifyCmd.txt (revision 11) @@ -0,0 +1,84 @@ + + seq_verify - verify the sequential equivalence of two flattened networks + _________________________________________________________________ + + seq_verify [-b] [-f ] [-h] [-p ] [-t + ] [-B] [-i] [-r] [] + + Please read the documentation for the command comb_verify before + reading on. The concepts of roots and leaves in this command are the + same as for comb_verify, except for an added constraint: the set of + leaves has to be the set of all primary inputs. This obviously + produces the constraint that both networks have the same number of + primary inputs. Moreover, no pseudo inputs should be present in the + two networks being compared. The set of roots can be an arbitrary + subset of nodes. + + The command verifies whether any state, where the values of two + corresponding roots differ, can be reached from the set of initial + states of the product machine. If this happens, a debug trace is + provided. + + The sequential verification is done by building the product finite + state machine. + + The command has two execution modes, just as for comb_verify. In the + first mode, two BLIF-MV files are given as arguments to the command: + + vis> seq_verify foo.mv bar.mv + + + In the second mode, a single BLIF-MV file is taken. This is network2. + It is assumed that network1 is from a hierarchy that has already been + read in. If a network is present at the current node (i.e. + flatten_hierarchy has been executed), it is used for verification; + otherwise the command does nothing. + + vis> read_blifmv foo.mv + vis> flatten_hierarchy + vis> seq_verify bar.mv + + + Command options: + + -b + Specifies that the input files are BLIF files. + + -f + Provides the correspondence between the leaves and roots of + network1 and network2. leaves has to be the set of primary + inputs of the networks. roots can be any subset of nodes. If + this option is not used, it is assumed that the correspondence + is by name, and that the roots are the combinational outputs. + + -h + Print the command usage. + + -p + Specifies the partitioning method for the product machine. + Supported methods are "total", "partial", and "inout" (see the + command build_partition_mdds for more information). If this + option is not specified, then the default method "inout" is + used. + + -t + Time in seconds allowed to perform equivalence checking. The + default is infinity. + + -B + Use backward image computation to traverse the state space of + the product machine. By default, forward image computaion is + used. + + -i + Print BDD statistics. This is the only way to see BDD stastics + during this command. print_bdd_stats after this command doesn't + show information related to this command. + + -r + Enable DBB reordering during the equivalence check. Note that + dynamic_var_ordering has no effect on whether reordering is + enabled during the execution of seq_verify. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/setCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/setCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/setCmd.txt (revision 11) @@ -0,0 +1,227 @@ + + set - set an environment variable + _________________________________________________________________ + + set [-h] [] [] + + A variable environment is maintained by the command interpreter. The + "set" command sets a variable to a particular value, and the "unset" + command removes the definition of a variable. If "set" is given no + arguments, it prints the current value of all variables. + + Command options: + + -h + Print the command usage. + + + Variable name + + + Value to be assigned to the variable. + + Interpolation of variables is allowed when using the set command. The + variables are referred to with the prefix of '$'. So for example, the + following can be done to check the value of a set variable: + vis> set foo bar + vis> echo $foo + bar + The last line "bar" will the output produced by vis. + + Variables can be extended by using the character ':' to concatenate + values. For example : + vis> set foo bar + vis> set foo $foo:foobar + vis> echo $foo + bar:foobar + The variable foo is extended with the value foobar . + + Whitespace characters may be present within quotes. However, variable + interpolation lays the restriction that the characters ':' and '/' may + not be used within quotes. This is to allow for recursive + interpolation. So for example, the following is allowed + vis> set "foo bar" this + vis> echo $"foo bar" + this + The last line will be the output produced by vis. + But in the following, the value of the variable foo/bar will not be + interpreted correctly: + + vis> set "foo/bar" this + vis> echo $"foo/bar" + foo/bar + If a variable is not set by the "set" command, then the variable is + returned unchanged. + + Different commands use environment information for different purposes. + The command interpreter makes use of the following parameters: + + autoexec + Defines a command string to be automatically executed after + every command processed by the command interpreter. This is + useful for things like timing commands, or tracing the progress + of optimization. + + open_path + "open_path" (in analogy to the shell-variable PATH) is a list + of colon-separated strings giving directories to be searched + whenever a file is opened for read. Typically the current + directory (.) is first in this list. The standard system + library (typically $VIS_LIBRARY_PATH) is always implicitly + appended to the current path. This provides a convenient + short-hand mechanism for reaching standard library files. + + vis_stderr + Standard error (normally stderr) can be re-directed to a file + by setting the variable vis_stderr. + + vis_stdout + Standard output (normally stdout) can be re-directed to a file + by setting the variable vis_stdout. + + Building MDDs for the network makes use of following setting: + + partition_method + This parameter is used to select the method for creating the + partition. The vertices of a partition correspond to the + combinational inputs, combinational outputs, and any + intermediate nodes used. Each vertex has a multi-valued + function (represented by MDDs) expressing the function of the + corresponding network node in terms of the partition vertices + in its transitive fanin. Hence, the MDDs of the partition + represent a partial collapsing of the network. The possible + values of partition_method are: + + inout + Expresses the combinational outputs in terms of the + combinational inputs. This is the default partitioning + method. + + total + The partition built is isomorphic to the combinational + part of the network. The function of each node is + expressed in terms of its immediate fanins. + + frontier + The partition built contains the combinational part of + the network as well as vertices corresponding to some + intermediate nodes. These vertices are generated to + control the MDD sizes of the combinational outputs. The + number of intermediate variables can be controlled by the + parameter "partition_threshold". The method "inout" and + "total" are special cases of this method (corresponding + to a partition_threshold of infinity and 0 respectively). + + partition_threshold + This parameter is used in conjuction with the selection of + "frontier" as partition method. This determines the threshold + at which a new MDD variable is created in the partition. + + Image computation makes use of following settings: + + image_method + The "image_method" parameter is used to control the image + method used in various symbolic analysis techniques. Currently, + two image methods are implemented. Use "set image_method + " to choose the appropriate method. + + monolithic + This is the most naive approach possible. However, this + method is not suitable for circuits with more than 20 + latches. + + tfm + This is the pure transition function method. This method + is supposed not to be used in general fixpoint + computations. Approximate traversal is an application of + this method. Basically this method is made as a part of + hybrid method. For more detailed options, see the help of + print_tfm_options command. + + hybrid + This is a hybrid method combining transition relation and + function methods. Transition relation method is based on + conjunction of partitioned transition relation, whereas + transition function method is based on splitting on an + input or output variable recursively. The hybrid method + choose either splitting or conjunction at each recursion + dynamically using the dependence matrix. For details, + refer to the paper "To split or to Conjoin: The Question + in Image Computation" by In-Ho Moon, James Kukula, Kavita + Ravi, and Fabio Somenzi, DAC'00. Also for more detailed + options, see the help of print_hybrid_options command. + + iwls95 + This technique is based on the early variable + quantification and related heuristics of Ranjan, et al. + "Efficient BDD Algorithms for FSM Synthesis and + Verification", IWLS 1995. First, from the given + multivalued functions, bit level relations are created. + These relations are then clustered based on the value of + threshold value controlled by image_cluster_size + parameter. Next the relations are ordered for early + variable quantification. This ordering is controlled by + the parameters image_W1, image_W2, image_W3, and + image_W4. + + mlp + This technique is based on minimizing the variable + lifetime in the conjunctions of the partitioned + transition relation. The method is called MLP (Minimal + Lifetime Permutation). For details, refer to the paper + "Border-Block Triangular Form and Conjunction Schedule in + Image Computation" by In-Ho Moon, Gary Hachtel, and Fabio + Somenzi, FMCAD'00. Also for more detailed options, see + the help of print_mlp_options command. + + image_farside_method + This parameter is used in conjunction with the selection of + iwls95, mlp, orlinear as the image_method. When the value is 1, + the compositional far side image computation approach is + enabled; when the value is 0, this feature is disabled + (default). + + image_cluster_size + This parameter is used in conjunction with the selection of + iwls95 as the image_method. The value of this parameter is used + as threshold value for creating clusters. The default value of + this parameter is 5000 which has been empirically proved to be + an optimal value. + + image_W1, image_W2, image_W3, image_W4 + These parameters are used in conjunction with the selection of + iwls95 as the image_method. They control the weights associated + with various factors in ordering the clusters. The default + values are 6, 1, 1, and 2 respectively. For a detailed + description of these parameters, please refer to the paper in + IWLS'95 proceedings. + + image_verbosity + Sets the verbosity mode (0 minimum to 4 maximum), for the image + method iwls95. + + image_minimize_method + Sets a minimization method to minimize the transition relation + or an image/preimage computaion with a set of dont-care states. + + Methods: 0 : restrict (default). + + 1 : constrain + + 2 : compact (currently supported by only CUDD) + + 3 : squeeze (currently supported by only CUDD) + + scc_method + Sets the symbolic method to enumerate strongly connected + components (SCCs). Symbolic SCC enumeration is the core + computation in LTL and fair-CTL model checking. + + Methods: lockstep : the O(nlogn) time LockStep algorithm + (default). + + Methods: linearstep : the linear time symbolic algorithm + (default). + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/set_bdd_parametersCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/set_bdd_parametersCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/set_bdd_parametersCmd.txt (revision 11) @@ -0,0 +1,31 @@ + + set_bdd_parameters - Creates a table with the value of all the flags + currently active in VIS and calls the function bdd_set_parameters with the + manager of the current place in the hierarchy and the table. + _________________________________________________________________ + + set_bdd_parameters [-h][-s] + + The command obtains the bdd manager of the current point in the + hierarchy. Given this manager and the set of pairs (variable,value) of + the VIS environment, the function sets specific BDD parameters to the + given values. This command works in conjunction with print_bdd_stats. + + Print_bdd_stats first prints a report of the parameters and statistics + of the current bdd_manager. By using the command "set", the user may + modify the value of any of the parameters of the underlying bdd + package. The way to do it is by setting a value in the variable + BDD.parameter name where parameter name is the name of the parameter + exactly as printed by the print_bdd_stats command. In order to + "re-program" the underlying bdd package this command must be invoked. + + Command options: + + -h + Print the command usage. + + -s + Print the bdd parameter and statistics after the modification. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/simulateCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/simulateCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/simulateCmd.txt (revision 11) @@ -0,0 +1,135 @@ + + simulate - simulate the flattened network + _________________________________________________________________ + + simulate [ -I <0/1> ] [ -O <0/1> ] [ -P <0/1> ] [ -S <0/1> ] [ -h ] [ + -i ] [ -n ] [ -o ] [ -p + <0|1> ] [ -v ] + + Simulates a network with a set of input vectors. Before calling this + command, the user should create a partition (using the command + build_partition_mdds). The simulation vectors can be provided by the + user (using -i vectors_file), or generated randomly. + + Command options: + + -I <0/1> + This option controls the printing the primary input variables. + 0 implies printing is disabled, enabled otherwise. The default + value is 1. The output file generated with this flag set to 0 + may not be used as input file for simulation (if there are some + primary inputs to the system). + + -O <0/1> + This option controls the printing the primary output variables. + 0 implies printing is disabled, enabled otherwise. The default + value is 1. + + -P <0/1> + This option controls the printing the pseudo input variables. 0 + implies printing is disabled, enabled otherwise. The default + value is 1. The output file generated with this flag set to 0 + may not be used as input file for simulation (if there are some + pseudo-inputs to the system). + + -S <0/1> + This option controls the printing the state variables. 0 + implies printing is disabled, enabled otherwise. The default + value is 1. + + -h + Print a help message that details all options. + + -i + Give the simulation vector file name. If this option is not + used, vectors are generated randomly. + + -n + Simulate N vectors. This option should be used if vectors_file + is not specified. If a vectors_file is given, and if there are + more than N vectors in the file, only the first N vectors are + simulated. + + -o + Give the name of a file where the simulation result should be + written. If this option is not used, the simulation result is + directed to standard output. + + -p <0|1|2> + This option is available only with random vector generation + mode, and affects how values for pseudo-inputs + (non-deterministic constants) are generated. 0: pseudo-inputs + are treated by user. 1: pseudo-inputs are treated randomly. 2: + pseudo-inputs are treated by choosing the first possibility. + + -v + Enable verbose mode. Prints CPU time usage. + + The vectors_file has two main parts: + + Declarations: + + Inputs list: + Gives an ordering of the primary and pseudo inputs. Every + input must be reported in this field. + + Latches list: + Gives an ordering of the latches. Every latch must be + reported in this field. + + Outputs list: + Gives an ordering of the outputs. This list may be + incomplete. Simulation is performed only on outputs + present in this list. + + Initial state: + Value of an initial state. This value is given with + respect to the latch ordering. + + Simulation Vectors: + One vector per line according to the given order of inputs. + + Final State: + Prints the value of state variables after the last simulation + vector is applied. + + An example of a simulation vectors file is: + # ----> Declarations + .inputs X1 X2 + .latches L1 L2 + .outputs O + .initial green 0 + .start_vectors + # ----> Vectors + 0 1 + 1 0 + 1 1 + + Note the keywords: .inputs, .latches, .outputs, .initial, + .start_vectors. A line started by a '#' is a comment line. + + The simulation result is printed either in a file (using -o + output_file) or to standard output. It has the same format as + vectors_file with additional fields for latches and outputs. Here is + the result of simulation on last vectors_file example: + .inputs X1 X2 + .latches L1 L2 + .outputs O + .initial green 0 + .start_vectors + #input; current_state; output + 0 1 ; green 0 ; 0 + 1 0 ; blue 0 ; 1 + 1 1 ; red 1 ; 1 + #Final State : green 1 + + Note that each input line has been extended by its simulation result + with current states and outputs listed in order. The output_file can + be read by simulate as vectors_file (latches and outputs values are + ignored). When starting simulation a good trick is to run simulate + with random vectors generation mode; the resulting can be used as a + template to write a vectors_file. For example, executing "simulate -n + 1 -o foo.output" will generate a representative file. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/sourceCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/sourceCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/sourceCmd.txt (revision 11) @@ -0,0 +1,72 @@ + + source - execute commands from a file + _________________________________________________________________ + + source [-h] [-p] [-s] [-x] [] + + Reads and executes commands from a file. + + Command options: + + -h + Print the command usage. + + -p + Print a prompt before reading each command. + + -s + Silently ignore an attempt to execute commands from a + nonexistent file. + + -x + Echo each command before it is executed. + + + File name + + Arguments on the command line after the filename are remembered but + not evaluated. Commands in the script file can then refer to these + arguments using the history substitution mechanism. + + EXAMPLE: + + Contents of test.scr: + + read_blif_mv %:2 + init_verify + simulate -n 10 + + + Typing "source test.scr lion.mv" on the command line will execute the + sequence + + read_blif_mv lion.mv + init_verify + simulate -n 10 + + + (In this case %:0 gets "source", %:1 gets "test.scr", and %:2 gets + "lion.mv".) If you type "alias st source test.scr" and then type "st + lion.blif bozo", you will execute + + read_blif_mv bozo + init_verify + simulate -n 10 + + + because "bozo" was the second argument on the last command line typed. + In other words, command substitution in a script file depends on how + the script file was invoked. Switches passed to a command are also + counted as positional parameters. Therefore, if you type "st -x + lion.mv bozo", you will execute + read_blif_mv lion.mv + init_verify + simulate -n 10 + + + To pass the "-x" switch (or any other switch) to "source" when the + script uses positional parameters, you can define an alias. For + instance, "alias srcx source -x". + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/spfd_pdloCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/spfd_pdloCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/spfd_pdloCmd.txt (revision 11) @@ -0,0 +1,171 @@ + + spfd_pdlo - Perform SPFD-based simultaneous placement and logic optimization. + _________________________________________________________________ + + spfd_pdlo [-D ] [-h] [-n ] [-r] [-t ] [-v ] [-w + ] net_file arch_file place_file route_file + + This command performs SPFD-based combined logic and placement + optimization of combinational circuits mapped to LUT-based FPGAs to + improve circuit area and speed. The flexibilities in the circuit are + represented by SPFDs. The following references explain in detail the + theory behind SPFDs. + + S. Yamashita, H. Sawada, and A. Nagoya. A new method to express + functional permissibilities for LUT based FPGAs and its applications. + In International Conference on Computer Aided Design, pages 254-261, + 1996. + + Subarnarekha Sinha and Robert K. Brayton. Implementation and use of + SPFDs in optimizaing Boolean networks. In International Conference on + Computer Aided Design, 1998. + + The command implements a technique that tightly links the logic and + placement optimization steps. The algorithm is based on simulated + annealing. Two types of moves, directed towards global reduction in + the cost function (total wire length), are accepted by the simulated + annealing algorithm: (1) wire removal/replacement, and (2) swapping of + a pair of blocks in the FPGA. Feedback from placement is valuable in + making an informed choice of a target wire during logic optimization + moves. The logic optimization steps performed are similar to those of + spfd_pilo, except that the placement information is now used instead + of the fanout count. More information on this technique can be found + in : + + Balakrishna Kumthekar and Fabio Somenzi. Power and delay reduction via + simultaneous logic and placement optimization in FPGAs. In Design, + Automation and Test in Europe, 2000. + + The command produces a placement file which is used by VPR for + routing. + + This command can be used only if VIS is linked with VPR 4.22 + (Versatile Place and Route), the FPGA place and route tool [1]VPR, + from the University of Toronto. Please follow the instructions + provided in the release notes to use VPR with VIS. You can also + contact kumtheka@avanticorp.com if you need more help. + + Before calling this command a network should be created for the design + (use flatten_hierarchy) and MDD ids for every node in the network + should be created (static_order -o all -n append). Dynamic variable + ordering (dvo -e sift) can be enabled to reduce BDD sizes. + + Command options: + + -D + A cluster is computed which includes nodes within the specified + 'depth'. The default value is 1. + + -n + File to output the optimized circuit in VPR's .net format. + + -r + Do not reprogram LUTs if no structural changes have been + performed with in the cluster, i.e., if no nodes or wires have + been removed do not change the local implementation of LUTs + even if alternate implementations are availabe from SPFD + information. The default is to reprogram. + + -t + Time in seconds allowed to complete the command. If the + computation time goes above that limit, the process is is + aborted. The default is no limit. + + -v + Verbosity level. + + -w + File to output final optimized circuit. + + The following is needed by VPR: + + net_file + The description of the circuit in the .net format. Logic + optimization uses the circuit described in .BLIF format whereas + VPR needs the same circuit described in .net format. VPack + (which comes with VPR) converts a .BLIF format into a .net + format. + + arch_file + Architecture description file for FPGAs. More information can + be found in VPR's manual. + + place_file + File to dump placement information. + + route_file + File to dump routing information. + + Relevant flags to be set by the set command: + + spfd_pdlo_logic_move_freq "r1 m1 r2 m2 ..." + Perform m1 logic moves whenever the rate of acceptance + during simulated annealing is greater than or equal to + r1, and so on. r1, r2, r3 ... should be monotonically + decreasing, else the results would be unpredictable. 0 <= + ri <= 1.0. For example: + + set spfd_pdlo_logic_move_freq "0.8 0 0.5 5 0.2 10" + + In the above logic schedule, zero logic moves per + temperature will be performed when the rate of acceptance + is above 0.8, 5 logic moves between 0.8 and 0.5, 10 moves + between 0.5 and 0.2. As no value is specified for + acceptance rate close to 0.0, by default, 1 logic move + per temperature will be performed. In this example it + will be 1 logic move between 0.2 and 0.0. The quotes + around the schedule are necessary. + + spfd_repl_rem + If no, the logic optimization performs only wire removal. + If yes, both wire replacement and removal are performed. + + spfd_pdlo_timing + If set, use timing driven method to remove or replace + wires on the critical path. If not set, use bounding box + of the wires as the cost function. + + spfd_pdlo_timing_nodeorwire + Remove/replace all the wires belonging to the most + critical net. If not set, attempt to remove/replace only + the most critical wire. + + spfd_pdlo_out_crit_nets_first + Output the circuit in VPR's .net format with the nets + appearing in the increasing order of their slack. If not + set, the initial net order specified in the original + circuit's .net file is used. The file is specified with + -n option. This variable is valid only if + spfd_pdlo_timing is set. + + spfd_pdlo_remap_clb_array + During logic optimization, due to the removal of nodes in + the network, the current size of FPGA might be bigger + than it is necessary. In such cases, if this variable is + set, the size of the FPGA is reduced to fit the current + logic network. + + Relevant flags that are options to VPR: + + For detailed information on the following options please refer + to the manual that accompanies VPR source distribution. + + vpr_nodisp + vpr_fix_pins + vpr_nx + vpr_ny + vpr_fast + vpr_init_t + vpr_alpha_t + vpr_exit_t + vpr_inner_num + vpr_seet + vpr_place_cost_exp + vpr_place_chan_width + __________________________________________________________ + + Last updated on 20050519 10h16 + +References + + 1. http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html Index: vis_dev/vis-2.1/share/help/spfd_piloCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/spfd_piloCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/spfd_piloCmd.txt (revision 11) @@ -0,0 +1,120 @@ + + spfd_pilo - Perform SPFD-based placement independent logic optimization. + _________________________________________________________________ + + spfd_pilo [-a <[0,1]>] [-D ] [-f ] [-h] [-i ] [-p + ] [-r] [-S ] [-t ] [-v ] [-w ] + + This command performs SPFD-based wire removal/replacement and + reprogramming of combinational circuits mapped to LUT-based FPGAs to + reduce the number of wires and nodes in the circuit. The flexibilities + in the circuit are represented by SPFDs. The following references + explain in detail the theory behind SPFDs. + + S. Yamashita, H. Sawada, and A. Nagoya. A new method to express + functional permissibilities for LUT based FPGAs and its applications. + In International Conference on Computer Aided Design, pages 254-261, + 1996. + + Subarnarekha Sinha and Robert K. Brayton. Implementation and use of + SPFDs in optimizaing Boolean networks. In International Conference on + Computer Aided Design, 1998. + + Instead of computing the flexibilities for every node in the network + at once, the algorithm computes the flexibilities for one cluster at a + time. Working with clusters allows us to avoid the BDD explosion + problem and hence, handle large circuits. The SPFDs are computed for + the cluster and the cluster nodes are reprogrammed based on the + flexibility derived. Switching activity is used to drive the choice of + alternate function to be implemented at the node. In the absence of + switching activity information, the function that can reduce support + of the node can be chosen (not implemented). Currently, an arbitrary + choice is made from the flexibilities provided by SPFDs. (-S 0, -S 2, + and -S 4) + + Before calling this command a network should be created for the design + (use flatten_hierarchy) and MDD ids for every node in the network + should be created (static_order -o all -n append, for example). + Dynamic variable ordering (dvo -e sift) can be enabled to reduce BDD + sizes. + + Command options: + + -a + A convex combination of switched capacitance (switching + activity * fanout count, SWC) and topological depth is used to + sort the fanin nodes during SPFD computation. alpha is between + 0 and 1.0. The cost function is alpha*SWC + + (1.0-alpha)*topDepth. The default value is 0.5. + + -D + A cluster is computed which includes nodes within the specified + 'depth'. The default value is 1. + + -f + File with simulation vectors. The file format is as below. The + format is simple but strict and hence, few checks are made. + + .i c n d o e p f q g r h s i t j u k a l b m + .s + 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 ; + 0 1 1 0 0 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 1 ; + 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 1 ; + 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 ; + The .i statement specifies the primary inputs of the network. + The patterns start after .s key word. Each vector is a space + separated list of bits and ends in a semi-colon. The length of + any vector should be equal to the number of signals specified + in the .i statement. A line starting with # is a comment. + + -h + Print usage. + + -i + Number of iterations after which to update node switching + activity. This is valid only if patterns are provided in a file + using -f option. The default value is every 5 iterations. + + -m + Heuristics to optimize a selected node. + 0: Reduce the selected node's support. + 1: Reprogram the selected node. + 2: Reprogram the selected node's fanin nodes. (default) + 3: Reduce the selected node's fanout wires. + + -p + The percentage of vectors, specified via -f option, used to + perform simulation (to update switching activity) during logic + optimization. The default value is 10%. + + -r + Do not reprogram LUTs if no structural changes have been + performed with in the cluster, i.e., if no nodes or wires have + been removed do not change the local implementation of LUTs + even if alternate implementations are availabe from SPFD + information. The default is to reprogram. + + -S + Method used to sort nodes. The nodes are then optimized in that + order. + 0: Random node is chosen. (default) + 1: If switching activity is available, node with maximum SWC is + chosen. + 2: Node with maximum fanout is chosen. + 3: If switching activity is available, node with minimum SWC is + chosen. + 4: Node with minimum fanout is chosen. + + -t + Time in seconds allowed to complete the command. If the + computation time goes above that limit, the process is aborted. + The default is no limit. + + -v + Verbosity level. Default value is 0. + + -w + File to output final optimized circuit. + __________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/static_orderCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/static_orderCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/static_orderCmd.txt (revision 11) @@ -0,0 +1,190 @@ + + static_order - order the MDD variables of the flattened network + _________________________________________________________________ + + static_order [-a] [-h] [-n ] [-o ] [-r ] -s + [-t ] [-v #] + + Order the MDD variables of the flattened network. MDD variables must + be created before MDDs can be built. Networks with combinational + cycles cannot be ordered. If the MDD variables have already been + ordered, then this command does nothing. To undo the current ordering, + reinvoke the command flatten_hierarchy. + + Command options: + + -a + Order each next state variable immediately following the + variables in the support of the corresponding next state + function. By default, each next state variable is placed + immeadiately following the corresponding present state + variable. It has been observed experimentally that ordering the + NS variable after the PS variable is almost always better; + however, as a last b resort, you might want to try this option. + + Unless the -a flag is set, the PS and NS variables + corresponding to latches are grouped together and cannot be + separated by dynamic reordering. (This is done even when the + ordering is read from a file - adjacent PS/NS vars in the file + are grouped). + + -h + Print the command usage. + + -n + Specify which node ordering method to use. Node ordering is the + process of computing a total ordering on all the network nodes. + This ordering is then projected onto the set of nodes specified + by -o type. In the complexity measures below, n is the number + of network nodes, E is the number of network edges, and k is + the number of latches. "Method" must be one of the following: + + interleave: (default) Uses Algorithm 2 of Fujii et al., + "Interleaving Based Variable Ordering Methods for OBDDs", ICCAD + 1993. The complexity is O(E+nlog(n)). + + append: Uses the algorithm of Malik, et al. "Logic Verification + using Binary Decision Diagrams in a Logic Synthesis + Environment," ICCAD, 1988. Nodes are visited in DFS order, and + appended to a global order list in the order they are visited. + The fanins of a node are visited in order of decreasing depth. + The roots of the DFS are visited in the order determined by the + -r method. The complexity is O(E+nlog(n)). + + merge_left: Uses an algorithm alluded to in Fujii et al., + "Interleaving Based Variable Ordering Methods for OBDDs", ICCAD + 1993. Nodes are visited in DFS order. At a given node g, its + fanins are visited in order of decreasing depth. For each fanin + fi, a total order is computed for all the nodes in the + transitive fanin (TFI) of fi, including fi itself. This + ordering is merged into the combined ordering from fanins of + higher priority. After processing all of the fanins, the result + is a total ordering on all TFI nodes of g. Finally, g is + appended to the end of this ordering, yielding a topological + ordering. For example if the ordering for f1 is list1 = + (a,b,d,f1) and for f2 is list2=(c,d,e,f2), and f1 has greater + depth than f2, then the ordering for g is (c,a,b,d,e,f2,f1,g). + The merge is done by inserting into list1 those nodes in list2 + not already in list1, in such a way that the inserted nodes + remain as close as possible to their left neighbors in list2 + ("insert as far left as possible"). The roots of the DFS are + merged in the order determined by -r method. The complexity is + O(n^2) (currently, there is a bug which causes more memory to + be consumed than necessary). + + merge_right: Same as merge_left, except that the merge is done + in such a way that the inserted nodes remain as close as + possible to their right neighbors in list2 ("insert as far + right as possible"). For the example above, the ordering for g + is (a,b,c,d,f1,e,f2,g). It has been observed experimentally + that neither merge_left nor merge_right is superior to the + other; there are cases where verification times out with + merge_left but not merge_right, and vice versa. + + -o + Specify the network nodes for which MDD variables should be + created. Type can be one of the following: + + all: Order all the nodes of the network. This is normally not + used. + + input_and_latch: (default) Order the primary inputs, pseudo + inputs, latches, and next state variables. This is the minimum + set of nodes that need to be ordered to perform operations on + FSMs (e.g. model checking, reachability). For purely + combinational circuits, just the primary and pseudo inputs are + ordered. + + -r + Specify which root ordering method to use. The "roots" of a + network refer to the roots of the cones of logic driving the + combinational outputs (data latch inputs, initial state latch + inputs, and primary outputs) of a network. Root ordering is + used to determine in which order to visit the roots of the + network for the DFS carried out in node ordering (see -n). + "Method" must be one of the following: + + depth: (default for 30 or more latches) Roots are ordered based + on logic depth (i.e. longest path to a combinational input). + Greater depth roots appear earlier in the ordering. All data + latch inputs appear before all other combinational outputs. The + complexity is O(E+nlog(n)). It has been observed experimentally + that mincomm produces superior orderings to depth. However, the + complexity of the mincomm algorithm is such that it cannot + produce orderings for designs with more than a hundred or so + latches. Hence, for big designs, use depth, followed optionally + by dynamic_var_ordering. + + mincomm: (default for less than 30 latches) Uses the algorithm + of Aziz, et al. "BDD Variable Ordering for Interacting Finite + State Machines," DAC, 1994. First, the latches are ordered to + decrease a communication complexity bound (where backward edges + are more expensive than forward edges) on the latch + communication graph. This directly gives an ordering for the + data latch inputs. The remaining combinational outputs are + ordered after the data latch inputs, in decreasing order of + their depth. The total complexity is O(nlog(n)+E+k^3). + + -s + Used in conjunction with to specify which nodes are + supplied in the ordering file. Type can be one of the following + (there is no default): + + all: The ordering file supplies all the nodes of the network. + The ordering generated is the supplied order, projected onto + the set of nodes specified by -o. + + input_and_latch: The ordering file supplies the primary inputs, + pseudo inputs, latches, and next state variables. The ordering + generated is exactly what is supplied (in the case of -o + input_and_latch). -o all is incompatible with -s + input_and_latch. + + next_state_node: The ordering file supplies next state + variables. During the ordering algorithm, the next state + functions are visited in the order in which their corresponding + next state variables appear in the file. The order of the next + state variables in the ordering generated is not necessarily + maintained. + + partial: The ordering file supplies an arbitrary subset of + nodes of the network. The ordering algorithm works by finding a + total ordering on all the nodes (independent of the ordering + supplied), then merging the computed order into the supplied + order (maintaining the relative order of the supplied order), + and then projecting the resulting ordering onto the set of + nodes specified by -o. + + -t + Time in seconds allowed to perform static ordering. If the + flattened network has more than a couple hundred latches and + you are using option -r mincomm, then you might want to set a + timeOut to limit the allowed time. The default is no limit. + + -v # + Print debug information. + 0 Nothing is printed out. This is the default. + + >= 1 Prints the nodes read from the input file (satisfying the + supplied order type); prints the root order used for exploring + the network. + + >= 2 Prints the depth of nodes. + + >= 3 Prints the ordering computed at each node. + + + A file containing names of network nodes, used to specify a + variable ordering. The name of a node is the full hierarchical + path name, starting from the current hierarchical node. A node + should appear at most once in the file. Each node name should + appear at the beginning of a new line, with no white space + preceeding it. The end of a node name is marked by white space, + and any other text on the rest of the line is ignored. Any line + starting with "#" or white space is ignored. See write_order + for a sample file. Note that the variable ordering cannot be + specified at the bit-level; it can only be specified at the + multi-valued variable level. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/synthesize_networkCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/synthesize_networkCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/synthesize_networkCmd.txt (revision 11) @@ -0,0 +1,128 @@ + + synthesize_network - Synthesizes a network using ZDD factorization method. + _________________________________________________________________ + + synthesize_network [-d ] [-e] [-f ] [-h] [-i + ] [-o ] [-r ] [-t ] [-v] [-A] + [-O ] [-R ] [-T] + + This command synthesizes a network to have as few literals as possible + and outputs a blif file and an equation file. Those files are the + results of the synthesis. By default, the names of the files are + model_name.ml.blif and model_name.eq unless users specify the + model_name explicitly using -o option. But, when the output blif file + is read in sis, it may have slightly different number of literals. + This problem will be fixed in the later version. Currently, this + command can be used only with CUDD package. Designs described in BLIF + or BLIF-MV format can be synthesized by this command. However, + multiple valued variables are not supported. Hence, signals in the + designs described in BLIF-MV need to be restricted to binary values. + There are 4 divisor functions to find a good divisor of a function. + Neither of them consistently generates the best result. And, there are + 2 factoring methods: simple factoring and generic factoring. Also, + neither of two always does better than the other. + + Command options: + + -d + Choose a divisor. + + 0 : Fast divisor. We find a divisor on a ZDD graph. As soon as + any shared node(variable) is found, the variable is returned as + a divisor. + + 1 : (default) Least occuring literal divisor. If a variable + occurs the least frequently(but, should be more than one) in + cubes, it returns the variable as a divisor. + + 2 : Most occuring literal divisor. If a variable occurs the + most frequently in cubes, it returns the variable as a divisor. + + 3 : Level-0 divisor. It finds a divisor that is a level-0 + cokernel. + + -e + Dump the synthesized circuit in equation format also. Default + is not to. + + -f + Choose a factoring method. + + 0 : (default) Simple factoring. This method uses a simple + recursion. First, it finds a proper divisor of a function, then + divide the function by the divisor, then it gets a quotient and + a remainder. And, it does the same thing recursively for each + divisor, quotient, and remainder. + + 1 : Generic factoring. This method is quite similar to the + simple factoring, but it does more in terms of considering + cube-free and common divisor and literal factoring. But, it + does not always generate better results than the simple + factoring does. + + -h + Print the command usage. + + -i + Specify the prefix of internal node names. By default, the + prefix is "_n". + + -o + Specify the output file name (without extension). By default, + the model name in a blif file is used. + + -r + If the network is sequential, then use unreachable states as + dont cares in the optimization. By default no reachability + analysis is performed. See -A option of command compute_reach + for more details. The various options are: + + 0 : Do not use dont cares (default). + + 1 : Use normal breadth first search method for reachability + analysis. + + 2 : Use high density traversal method for reachablity analysis. + + 3 : Use approximate unreachable states(a subset of actual + unreachable states) as dont cares. + + -t + Time in seconds allowed to perform synthesize_network. The + default is no limit. + + -v + Print debug information. + + -A + Allow realignment to ZDD/BDD after BDD/ZDD reordering, + respectively. This option is effective when only one reordering + in BDD or ZDD is enabled. + + -O + Choose an output ordering method. + + 0 : No ordering. + + 1 : (default) Use support variable set of output functions. + + 2 : Use BDD size of output functions. + + -R + Allow reordering in BDD and/or ZDD. + + 0 or n : (default) No reordering neither in BDD nor in ZDD. + + 1 or b : Allows reordering only in BDD, not in ZDD. + + 2 or z : Allows reordering only in ZDD, not in BDD. + + 3 or a : Allows reordering both in BDD and in ZDD. + + -T + Try to share more nodes during symbolic factorization. Existing + divisors are checked for potential reuse before extracting + divisors from the current boolean function. + ____________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/test_network_acyclicCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/test_network_acyclicCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/test_network_acyclicCmd.txt (revision 11) @@ -0,0 +1,17 @@ + + test_network_acyclic - determine whether the network is acyclic + _________________________________________________________________ + + test_network_acyclic [-h] + + If the flattened network has a combinational cycle, then prints + information about one of the cycles. If no cycles are present, then it + prints a message to this effect. + + Command options: + + -h + Print the command usage. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/timeCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/timeCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/timeCmd.txt (revision 11) @@ -0,0 +1,23 @@ + + time - provide a simple elapsed time value + _________________________________________________________________ + + time [-h][-u] + + Prints the processor time used since the last time command, and the + total processor time used since VIS was started. + + By default, the time reported is the CPU time spent executing + instructions of the calling process and the time this process waited + for children that terminated. + + Command options: + + -h + Print the command usage. + + -u + Exclude child process time. + _________________________________________________________________ + + Last updated on 20050519 10h16 Index: vis_dev/vis-2.1/share/help/truesimCmd.txt =================================================================== --- vis_dev/vis-2.1/share/help/truesimCmd.txt (revision 11) +++ vis_dev/vis-2.1/share/help/truesimCmd.txt (revision 11) @@ -0,0 +1,83 @@ + + truesim - Simulate the flattened network + _________________________________________________________________ + + truesim [ -D ] [ -d ] [ -f ] [ -g ] [ + -h ] [ -n ] [ -p ] [ -r ] [ -t