Index: /biblio/biblio.bib =================================================================== --- /biblio/biblio.bib (revision 45) +++ /biblio/biblio.bib (revision 45) @@ -0,0 +1,3796 @@ +% This file was created with JabRef 2.5. +% Encoding: UTF8 + +@STRING{LICS04 = {LICS'04: Proceedings of the 19th IEEE Symposium on Logic in Computer + Science}} + +@STRING{LNCS = {}} + +@INPROCEEDINGS{aagaard03hazards, + author = {M.~Aagaard}, + title = {A {H}azards-{B}ased {C}orrectness {S}tatement for {P}ipelined {C}ircuits.}, + booktitle = {Proceedings of the 12th IFIP WG 10.5 Advanced Research Working Conference}, + year = {2003}, + pages = {66-80}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/charme/2003}, + ee = {http://springerlink.metapress.com/openurl.asp?genre=article{\&}issn=0302-9743{\&}volume=2860{\&}spage=66}, + file = {aagard.pdf:/dsk/l1/misc/doc/verif_archi/aagard.pdf:PDF}, + keywords = {pipeline} +} + +@INPROCEEDINGS{alder06ticc, + author = {B.T.~Adler and L.~de Alfaro and L.~Dias da Silva and M.~Faella and + A.~Legay and V.~Raman and P.~Roy}, + title = {Ticc: {A T}ool for {I}nterface {C}ompatibility and {C}omposition.}, + booktitle = {CAV'06: Proceedings of 18th International Conference of Computer + Aided Verification}, + year = {2006}, + pages = {59-62}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/2006}, + ee = {http://dx.doi.org/10.1007/11817963_8}, + file = {tiicctool.pdf:/dsk/l1/misc/doc/interface/tiicctool.pdf:PDF}, + keywords = {interface, wrapper} +} + +@INPROCEEDINGS{DBLP:conf/frocos/AlfaroSFLRS05, + author = {Luca de Alfaro and Leandro Dias da Silva and Marco Faella and Axel + Legay and Pritam Roy and Maria Sorea}, + title = {{Sociable Interfaces.}}, + booktitle = {FroCos'05: Proceedings of the 5th International Workshop on Frontiers + of Combining Systems}, + year = {2005}, + pages = {81-105}, + address = {Vienna, Austria}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/frocos/2005}, + ee = {http://dx.doi.org/10.1007/11559306_5} +} + +@INPROCEEDINGS{alur98alternatingtime, + author = {Rajeev Alur and Thomas A. Henzinger and Orna Kupferman}, + title = {{Alternating-Time Temporal Logic}}, + booktitle = {COMPOS}, + year = {1997}, + pages = {23-60}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/compos/1997}, + ee = {http://link.springer.de/link/service/series/0558/bibs/1536/15360023.htm}, + keywords = {atl} +} + +@INPROCEEDINGS{DBLP:conf/lpar/AndrausLS08, + author = {Zaher S. Andraus and Mark H. Liffiton and Karem A. Sakallah}, + title = {Reveal: A Formal Verification Tool for Verilog Designs}, + booktitle = {LPAR}, + year = {2008}, + pages = {343-352}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/lpar/2008}, + ee = {http://dx.doi.org/10.1007/978-3-540-89439-1_25}, + keywords = {CEGAR,Hardware, TOOLS} +} + +@INPROCEEDINGS{DBLP:conf/dac/AndrausS04, + author = {Zaher S. Andraus and Karem A. Sakallah}, + title = {Automatic abstraction and verification of verilog models}, + booktitle = {DAC}, + year = {2004}, + pages = {218-223}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/dac/2004}, + ee = {http://doi.acm.org/10.1145/996566.996629}, + file = {:Abstraction/Andraus_DAC_Vapor.pdf:PDF}, + keywords = {Abstraction, Hardware, Verilog, TOOLS, Vapor} +} + +@INPROCEEDINGS{Awhed04Proving, + author = {M.~Awedh and F.~Somenzi}, + title = {Proving More Properties with Bounded Model Checking}, + booktitle = {CAV'04: Proceedings of the 16th International Conference on Computer + Aided Verification}, + year = {2004}, + pages = {96-108}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/2004}, + ee = {http://springerlink.metapress.com/openurl.asp?genre=article{\&}issn=0302-9743{\&}volume=3114{\&}spage=96}, + file = {:BMC/ProvingMorePropwithBC04.pdf:PDF}, + keywords = {BMC, VIS} +} + +@INPROCEEDINGS{bmethod99meteor, + author = {P.~Behm and P.~Benoit and A.~Faivre and J-M.~Meynadier}, + title = {{M{\'e}t{\'e}or: A Successful Application of B in a Large Project}}, + booktitle = {World Congress on Formal Methods}, + year = {1999}, + pages = {369-387}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/fm/1999-1}, + ee = {http://link.springer.de/link/service/series/0558/bibs/1708/17080369.htm} +} + +@INPROCEEDINGS{DBLP:conf/vmcai/Bradley11, + author = {Aaron R. Bradley}, + title = {SAT-Based Model Checking without Unrolling}, + booktitle = {VMCAI}, + year = {2011}, + pages = {70-87}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/vmcai/2011}, + ee = {http://dx.doi.org/10.1007/978-3-642-18275-4_7} +} + +@INPROCEEDINGS{bruns00generalized, + author = {G.~Bruns and P.~Godefroid}, + title = {{Generalized Model Checking: Reasoning about Partial State Spaces}}, + booktitle = {CONCUR'2000: Proceedings of the 11th International Conference on + Concurrency Theory}, + year = {2000}, + editor = {Nicolas Halbwachs and Doron Peled}, + series = {Lecture Notes in Computer Science}, + pages = {168-182}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/concur/2000}, + ee = {http://link.springer.de/link/service/series/0558/bibs/1877/18770168.htm}, + file = {godefroid00.pdf:/dsk/l1/misc/doc/abstraction/godefroid00.pdf:PDF}, + keywords = {3-valued, Kripke structure, abstraction} +} + +@INPROCEEDINGS{burns99partial, + author = {G.~Bruns and P.~Godefroid}, + title = {{Model Checking Partial State Spaces with 3-Valued Temporal Logics}}, + booktitle = {CAV'99: Proceedings of the 11th conference on Computer Aided Verification}, + year = {1999}, + series = {Lecture Notes in Computer Science}, + pages = {274-287}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/1999}, + ee = {http://link.springer.de/link/service/series/0558/bibs/1633/16330274.htm}, + file = {burns99partial.pdf:/dsk/l1/misc/doc/abstraction/burns99partial.pdf:PDF}, + keywords = {tree automata, CTL, automata approach}, + owner = {cecile}, + timestamp = {2006.04.25} +} + +@INPROCEEDINGS{Buttner05isformal, + author = {W. B{\"u}ttner}, + title = {{Is Formal Verification Bound to Remain a Junior Partner of Simulation?}}, + booktitle = {CHARME'2005: Proceedings of the Correct Hardware Design and Verification + Methods, 13th IFIP WG 10.5 Advanced Research Working Conference}, + year = {2005}, + editor = {Dominique Borrione, Wolfgang J. Paul}, + volume = {3725}, + series = {Lecture Notes in Computer Science}, + pages = {1}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/charme/2005}, + ee = {http://dx.doi.org/10.1007/11560548_1}, + owner = {cecile}, + timestamp = {2006.06.27} +} + +@INPROCEEDINGS{DBLP:conf/fmcad/ChauhanCKSVW02, + author = {P.~Chauhan and E.M.~Clarke and J.H.~Kukula and S.~Sapra and H.~Veith + and D.~Wang}, + title = {Automated Abstraction Refinement for Model Checking Large State Spaces + Using SAT Based Conflict Analysis}, + booktitle = {FMCAD'02: Proceedings of the 4th International Conference on Formal + Methods in Computer-Aided Design }, + year = {2002}, + pages = {33-51}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/fmcad/2002}, + ee = {http://link.springer.de/link/service/series/0558/bibs/2517/25170033.htm}, + file = {:Cegar/AutomatedAbstractionRefinment02Chauchan.pdf:PDF}, + keywords = {Cegar, SAT} +} + +@INPROCEEDINGS{chechik05framework, + author = {Marsha Chechik and Arie Gurfinkel}, + title = {A Framework for Counterexample Generation and Exploration.}, + booktitle = {FASE}, + year = {2005}, + pages = {220-236}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/fase/2005}, + ee = {http://springerlink.metapress.com/openurl.asp?genre=article{\&}issn=0302-9743{\&}volume=3442{\&}spage=220}, + file = {chechik05a.pdf:/dsk/l1/misc/doc/abstraction/chechik05a.pdf:PDF} +} + +@INPROCEEDINGS{ChocklerKV01, + author = {H.~Chockler and O.~Kupferman and M.Y.~Vardi}, + title = {Coverage Metrics for Temporal Logic Model Checking}, + booktitle = {TACAS'01: 7th International Conference on Tools and Algorithms for + the Construction and Analysis of Systems}, + year = {2001}, + series = {LNCS}, + pages = {528-542}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/tacas/2001}, + ee = {http://link.springer.de/link/service/series/0558/bibs/2031/20310528.htm}, + file = {:Fault/Coverage_Metric_for_temporal_MC01.pdf:PDF}, + keywords = {coverage} +} + +@INPROCEEDINGS{DBLP:conf/fmcad/CimattiDJR09, + author = {Alessandro Cimatti and Jori Dubrovin and Tommi A. Junttila and Marco + Roveri}, + title = {Structure-aware computation of predicate abstraction}, + booktitle = {FMCAD}, + year = {2009}, + pages = {9-16}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/fmcad/2009}, + ee = {http://dx.doi.org/10.1109/FMCAD.2009.5351149}, + file = {:Cegar/StructureAwareComputationofPredicateAbstraction09.pdf:PDF}, + keywords = {Abstraction} +} + +@INPROCEEDINGS{DBLP:conf/sfm/ClaessenR06, + author = {Koen Claessen and Jan-Willem Roorda}, + title = {An Introduction to Symbolic Trajectory Evaluation}, + booktitle = {SFM}, + year = {2006}, + pages = {56-77}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/sfm/2006}, + ee = {http://dx.doi.org/10.1007/11757283_3} +} + +@INPROCEEDINGS{clarke03cegar, + author = {E.M.~Clarke}, + title = {Counterexample-Guided Abstraction Refinement}, + booktitle = {TIME}, + year = {2003}, + pages = {7}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/time/2003}, + ee = {http://csdl.computer.org/comp/proceedings/time-ictl/2003/1912/00/19120007.pdf}, + file = {ce03time.pdf:/dsk/l1/misc/doc/CEGAR/ce03time.pdf:PDF}, + keywords = {abstraction, CEGAR} +} + +@INPROCEEDINGS{clarkeE81design, + author = {E.M.~Clarke and E.A.~Emerson}, + title = {Design and Synthesis of Synchronization Skeletons Using Branching-Time + Temporal Logic.}, + booktitle = {Logic of Programs}, + year = {1981}, + pages = {52-71}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/lop/1981} +} + +@INPROCEEDINGS{ClarkeGJLV00, + author = {E.M.~Clarke and O.Grumberg and S.~Jha and Y.~Lu and H.~Veith}, + title = {{Counterexample-Guided Abstraction Refinement.}}, + booktitle = {CAV'00: Proceedings of the 12th International Conference on Computer + Aided Verification}, + year = {2000}, + pages = {154-169}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/2000} +} + +@INPROCEEDINGS{DBLP:conf/birthday/ClarkeKV10, + author = {Edmund M. Clarke and Robert P. Kurshan and Helmut Veith}, + title = {The Localization Reduction and Counterexample-Guided Abstraction + Refinement}, + booktitle = {Essays in Memory of Amir Pnueli}, + year = {2010}, + pages = {61-71}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/birthday/2010pnueli}, + ee = {http://dx.doi.org/10.1007/978-3-642-13754-9_4} +} + +@INPROCEEDINGS{DBLP:conf/lics/ClarkeLM89, + author = {E.~M.~Clarke and D.~E.~Long and K.~L.~McMillan}, + title = {Compositional Model Checking}, + booktitle = {LICS'89: Proceedings of the 4th Annual Symposium on Logic in Computer + Science}, + year = {1989}, + pages = {353-362}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/lics/LICS4}, + file = {clarke89compo.ps:/dsk/l1/misc/doc/model_check/clarke89compo.ps:PDF}, + keywords = {composition, model checking, Kripke structure, Moore machine, CTL} +} + +@INPROCEEDINGS{DBLP:conf/sat/ClarkeTVW03, + author = {Edmund M. Clarke and Muralidhar Talupur and Helmut Veith and Dong + Wang}, + title = {SAT Based Predicate Abstraction for Hardware Verification}, + booktitle = {SAT}, + year = {2003}, + pages = {78-92}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/sat/2003}, + ee = {http://springerlink.metapress.com/openurl.asp?genre=article{\&}issn=0302-9743{\&}volume=2919{\&}spage=78}, + file = {:Abstraction/SATBasedPredicateAbstactforHWVerif2004.pdf:PDF}, + keywords = {SAT, predicate abstraction, hardware} +} + +@INPROCEEDINGS{CouvreurEPPW02, + author = {J-M.~Couvreur and E.~Encrenaz and E.~Paviot-Adet and D.~Poitrenaud + and P-A.~Wacrenier}, + title = {Data Decision Diagrams for Petri Net Analysis.}, + booktitle = {ICATPN'02: Proceedings of the 23rd International Conference on Applications + and Theory of Petri Nets}, + year = {2002}, + pages = {101-120}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/apn/2002}, + ee = {http://link.springer.de/link/service/series/0558/bibs/2360/23600101.htm} +} + +@INPROCEEDINGS{couvreur05hierarchie, + author = {J-M.~Couvreur and Y.~Thierry-Mieg}, + title = {{Hierarchical Decision Diagrams to Exploit Model Structure.}}, + booktitle = {FORTE : Proceedings of the 25th IFIP WG 6.1 International Conference + on Formal Techniques for Networked and Distributed Systems}, + year = {2005}, + editor = {Farn Wang}, + volume = {3731}, + series = {Lecture Notes in Computer Science}, + pages = {443-457}, + address = {Taipei, Taiwan}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/forte/2005}, + ee = {http://dx.doi.org/10.1007/11562436_32} +} + +@INPROCEEDINGS{DBLP:conf/vmcai/DamsN05, + author = {D.~Dams and K.~S.~Namjoshi}, + title = {{Automata as Abstractions.}}, + booktitle = {VMCAI'05: Proceedings of the 6th International Conference on Verification, + Model Checking, and Abstract Interpretation}, + year = {2005}, + series = {Lecture Notes in Computer science}, + pages = {216-232}, + address = {Paris, France}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/vmcai/2005}, + ee = {http://springerlink.metapress.com/openurl.asp?genre=article{\&}issn=0302-9743{\&}volume=3385{\&}spage=216}, + file = {automata_aabstr.pdf:/dsk/l1/misc/doc/modular/abstraction/automata_aabstr.pdf:PDF}, + keywords = {tree automata, CTL, automata approach} +} + +@INPROCEEDINGS{DBLP:conf/lics/DamsN04, + author = {D.~Dams and K.~S.~Namjoshi}, + title = {The Existence of Finite Abstractions for Branching Time Model Checking.}, + booktitle = {LICS04}, + year = {2004}, + pages = {335-344}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/lics/2004}, + ee = {http://csdl.computer.org/comp/proceedings/lics/2004/2192/00/21920335abs.htm}, + file = {abstractforbtl.pdf:/dsk/l1/misc/doc/ctl_auto/abstractforbtl.pdf:PDF}, + keywords = {CTL, tree automata ,model checking, automata approach} +} + +@INPROCEEDINGS{DBLP:conf/icse/DwyerHJLPRZV01, + author = {Matthew B. Dwyer and John Hatcliff and Roby Joehanes and Shawn Laubach + and Corina S. Pasareanu and Robby and Hongjun Zheng and Willem Visser}, + title = {Tool-Supported Program Abstraction for Finite-State Verification.}, + booktitle = {ICSE}, + year = {2001}, + pages = {177-187}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/icse/2001}, + file = {bandera.pdf:/dsk/l1/misc/doc/softMC/bandera.pdf:PDF}, + keywords = {software, model-checking, CEGAR} +} + +@INPROCEEDINGS{DBLP:conf/icse/EasterbrookCDGLPTT03, + author = {S.M.~Easterbrook and M.~Chechik and B.~Devereux and A.~Gurfinkel + and A.~Lai and V.~Petrovykh and A.~Tafliovich and C.~Thompson-Walsh}, + title = {{$\chi$Chek: A Model Checker for Multi-Valued Reasoning.}}, + booktitle = {ICSE'03: Proceedings of the 25th International Conference on Software + Engineering}, + year = {2003}, + pages = {804-805}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/icse/2003}, + ee = {http://computer.org/proceedings/icse/1877/18770804.pdf} +} + +@INPROCEEDINGS{EasterbrookC01, + author = {Steve M. Easterbrook and Marsha Chechik}, + title = {A Framework for Multi-Valued Reasoning over Inconsistent Viewpoints.}, + booktitle = {ICSE}, + year = {2001}, + pages = {411-420}, + bibsource = {DBLP,http://dblp.uni-trier.de}, + crossref = {DBLP:conf/icse/2001}, + file = {easterbrook01a.pdf:/dsk/l1/misc/doc/multi_valued/easterbrook01a.pdf:PDF}, + keywords = {abstraction, 3-valued, 4-valued, logic, model checking} +} + +@INPROCEEDINGS{emerson82desision, + author = {E.A.~Emerson and J.Y.~Halpern}, + title = {Decision Procedures and Expressiveness in the Temporal Logic of Branching + Time}, + booktitle = {STOC}, + year = {1982}, + pages = {169-180}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/stoc/STOC14}, + file = {ctl_emerson82.pdf:/dsk/l1/misc/doc/model_check/ctl_emerson82.pdf:PDF}, + keywords = {CTL, model checking} +} + +@INPROCEEDINGS{DBLP:conf/date/GanaiGA05, + author = {Malay K. Ganai and Aarti Gupta and Pranav Ashar}, + title = {Verification of Embedded Memory Systems using Efficient Memory Modeling}, + booktitle = {DATE}, + year = {2005}, + pages = {1096-1101}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/date/2005}, + ee = {http://doi.ieeecomputersociety.org/10.1109/DATE.2005.325}, + file = {:Abstraction/VerifEmbededMemoryusingEMM09.pdf:PDF}, + keywords = {Abstraction, Memory,}, + owner = {cecile}, + timestamp = {2010.06.10} +} + +@INPROCEEDINGS{DBLP:conf/cav/GodefroidJ02, + author = {P.~Godefroid and R.~Jagadeesan}, + title = {Automatic Abstraction Using Generalized Model Checking.}, + booktitle = {CAV}, + year = {2002}, + pages = {137-150}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/2002}, + ee = {http://link.springer.de/link/service/series/0558/bibs/2404/24040137.htm} +} + +@INPROCEEDINGS{GrafS97pvs, + author = {S.~Graf and H.~Sa\"{\i}di}, + title = {{Construction of Abstract State Graphs with PVS.}}, + booktitle = {CAV}, + year = {1997}, + pages = {72-83}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/1997}, + file = {graf97cinstructionpvs.ps:/dsk/l1/misc/doc/abstraction/graf97cinstructionpvs.ps:PDF}, + keywords = {abstraction, CEGAR} +} + +@INPROCEEDINGS{grumberg05abstraction, + author = {Orna Grumberg}, + title = {{Abstraction and Refinement in Model Checking.}}, + booktitle = {FMCO'05: 4th International Symposium on Formal Methods for Components + and Objects,}, + year = {2005}, + pages = {219-242}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/fmco/2005}, + ee = {http://dx.doi.org/10.1007/11804192_11}, + keywords = {abstraction, refinement, CEGAR} +} + +@INPROCEEDINGS{DBLP:conf/sfm/GuptaGW06, + author = {Aarti Gupta and Malay K. Ganai and Chao Wang}, + title = {SAT-Based Verification Methods and Applications in Hardware Verification}, + booktitle = {SFM}, + year = {2006}, + pages = {108-143}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/sfm/2006}, + ee = {http://dx.doi.org/10.1007/11757283_5}, + file = {:BMC/SATBasedVerifMethodAndApplitoHdw2006.pdf:PDF}, + keywords = {SAT, verification,} +} + +@INPROCEEDINGS{gurfinkelC06waste, + author = {A.~Gurfinkel and M.~Chechik}, + title = {{Why Waste a Perfectly Good Abstraction?.}}, + booktitle = {T{ACAS}'06: {P}roceedings of the 12th international conference on + {T}ools and {A}lgorithms for the {C}onstruction and {A}nalysis of + {S}ystems}, + year = {2006}, + series = {Lecture Notes in Computer Science}, + pages = {212-226}, + address = {Vienna, Austria}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/tacas/2006}, + ee = {http://dx.doi.org/10.1007/11691372_14}, + file = {gurfinkel_tacas_06.pdf:/dsk/l1/misc/doc/abstraction/gurfinkel_tacas_06.pdf:PDF}, + keywords = {abstraction, 3-valued, 4-valued, logic, model checking} +} + +@INPROCEEDINGS{DBLP:conf/vmcai/GurfinkelWC06, + author = {Arie Gurfinkel and Ou Wei and Marsha Chechik}, + title = {Systematic Construction of Abstractions for Model-Checking}, + booktitle = {VMCAI}, + year = {2006}, + pages = {381-397}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/vmcai/2006}, + ee = {http://dx.doi.org/10.1007/11609773_25} +} + +@INPROCEEDINGS{GurfinkelWC06, + author = {Gurfinkel, A. and Wei, O. and Chechik, M.}, + title = {Systematic {C}onstruction of {A}bstractions for {M}odel-{C}hecking.}, + booktitle = {V{MCAI}'06: {P}roceedings of the 7th {I}nternational {C}onference + on {V}erification, {M}odel {C}hecking, and {A}bstract {I}nterpretation}, + year = {2006}, + pages = {381-397}, + address = {Charleston, USA}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/vmcai/2006}, + ee = {http://dx.doi.org/10.1007/11609773_25}, + keywords = {abstraction, abstract interpretation} +} + +@INPROCEEDINGS{JainKSC05, + author = {Jain, H. and Kroening, D. and Sharygina, N. and Clarke, E.M.}, + title = {Word {L}evel {P}redicate {A}bstraction and {R}efinement for {V}erifying + {RTL} {V}erilog.}, + booktitle = {D{AC}'05: {P}roceedings of the 42nd {D}esign {A}utomation {C}onference}, + year = {2005}, + editor = {William H. Joyner Jr., Grant Martin, Andrew B. Kahng}, + series = {ACM}, + pages = {445-450}, + address = {San Diego, USA}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/dac/2005}, + ee = {http://doi.acm.org/10.1145/1065579.1065697} +} + +@INPROCEEDINGS{jhala01microarchi, + author = {Jhala, R. and McMillan, K.L.}, + title = {Microarchitecture {V}erification by {C}ompositional {M}odel {C}hecking.}, + booktitle = {C{AV}'01: {P}roceedings of the 13th {I}nternational {C}onference + on {C}omputer {A}ided {V}erification}, + year = {2001}, + editor = {G\'erard Berry, Hubert Comon, Alain Finkel}, + series = {Lecture Notes in Computer Science}, + pages = {396-410}, + address = {Paris, France}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/2001}, + ee = {http://link.springer.de/link/service/series/0558/bibs/2102/21020396.htm} +} + +@INPROCEEDINGS{Somenzi04Circuscav, + author = {HoonSang Jin and Mohammad Awedh and Fabio Somenzi}, + title = {CirCUs: A Satisfiability Solver Geared towards Bounded Model Checking}, + booktitle = {CAV'04: Proceedings of the 16th International Conference onComputer + Aided Verification }, + year = {2004}, + pages = {519-522}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/2004}, + ee = {http://springerlink.metapress.com/openurl.asp?genre=article{\&}issn=0302-9743{\&}volume=3114{\&}spage=519}, + file = {:SAT/CirCUsToward.pdf:PDF}, + keywords = {SAT, SAT solver, VIS} +} + +@INPROCEEDINGS{DBLP:conf/tacas/JinHS05, + author = {HoonSang Jin and HyoJung Han and Fabio Somenzi}, + title = {Efficient Conflict Analysis for Finding All Satisfying Assignments + of a Boolean Circuit}, + booktitle = {TACAS'05: Proceedings of 11th International Conference on Tools and + Algorithms for the Construction and Analysis of Systems}, + year = {2005}, + pages = {287-300}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/tacas/2005}, + ee = {http://springerlink.metapress.com/openurl.asp?genre=article{\&}issn=0302-9743{\&}volume=3440{\&}spage=287}, + file = {:SAT/efficientConflict05Jin.pdf:PDF}, + keywords = {SAT, All-sat} +} + +@INPROCEEDINGS{somenzi04Circus, + author = {H*.~Jin and F.~Somenzi}, + title = {CirCUs: A Hybrid Satisfiability Solver}, + booktitle = {SAT'04: The 7th International Conference on Theory and Applications + of Satisfiability Testing}, + year = {2004}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/sat/2004}, + ee = {http://www.satisfiability.org/SAT04/programme/24.pdf}, + owner = {cecile}, + timestamp = {2009.01.27} +} + +@INPROCEEDINGS{larsen88modal, + author = {K.~G.~Larsen and B.~Thomsen}, + title = {A {M}odal {P}rocess {L}ogic}, + booktitle = {Third Annual Symposium on Logic in Computer Science}, + year = {1988}, + pages = {203-210}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/lics/LICS3} +} + +@INPROCEEDINGS{DBLP:conf/iccad/ManoliosSV06, + author = {Panagiotis Manolios and Sudarshan K. Srinivasan and Daron Vroon}, + title = {Automatic memory reductions for RTL model verification}, + booktitle = {ICCAD}, + year = {2006}, + pages = {786-793}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/iccad/2006}, + ee = {http://doi.acm.org/10.1145/1233501.1233663}, + file = {:Abstraction/AutomaticMemoryReductionforRTL06.pdf:PDF}, + keywords = {Abstraction, memory} +} + +@INPROCEEDINGS{mcmillan98tomasulo, + author = {K.L.~McMillan}, + title = {Verification of an {I}mplementation of {T}omasulo's {A}lgorithm by + {C}ompositional {M}odel {C}hecking.}, + booktitle = {C{AV}'98: {P}roceddings of the 10th {I}nternational {C}onference + on {C}omputer {A}ided {V}erification}, + year = {1998}, + editor = {Alan J. Hu, Moshe Y. Vardi}, + volume = {1427}, + series = {Lecture Notes in Computer Science}, + pages = {110-121}, + address = {Vancouver, Canada}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/1998} +} + +@INPROCEEDINGS{mcmillan02applyingSat, + author = {Kenneth L. McMillan}, + title = {Applying SAT Methods in Unbounded Symbolic Model Checking}, + booktitle = {CAV'02: Proceedings of the 14th International Conference on Computer + Aided vVrification}, + year = {2002}, + pages = {250-264}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/2002}, + ee = {http://link.springer.de/link/service/series/0558/bibs/2404/24040250.htm}, + file = {:BMC/Mcmillan02applyingSat.pdf:PDF} +} + +@INPROCEEDINGS{DBLP:conf/cav/McMillan97, + author = {Kenneth L. McMillan}, + title = {{A Compositional Rule for Hardware Design Refinement.}}, + booktitle = {CAV'97: Proceedings of the 9th International Conference on Computer + Aided Verification}, + year = {1997}, + volume = {1254}, + series = {Lecture Notes in Computer Science}, + pages = {24-35}, + adress = {Haifa, Israel}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/1997} +} + +@INPROCEEDINGS{Morin-AlloryB06, + author = {K.~Morin-Allory and D.~Borrione}, + title = {Proven {C}orrect {M}onitors from {PSL} {S}pecifications.}, + booktitle = {D{ATE}'06: {P}roceedings of the {C}onference on {D}esign, {A}utomation + and {T}est in {E}urope}, + year = {2006}, + editor = {{Georges G. E. Gielen}}, + pages = {1246-1251}, + address = {Munich, Germany}, + organization = {European Design and Automation Association}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/date/2006p}, + ee = {http://doi.acm.org/10.1145/1131827} +} + +@INPROCEEDINGS{DBLP:conf/dac/MoskewiczMZZM01, + author = {M.W.~Moskewicz and C.F.~Madigan and Y.~Zhao and L.~Zhang and S.~Malik}, + title = {Chaff: Engineering an Efficient SAT Solver}, + booktitle = {DAC'01: Proceedings of the 38th Design Automation Conference}, + year = {2001}, + pages = {530-535}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/dac/2001}, + ee = {http://jamaica.ee.pitt.edu/Archives/ProceedingArchives/Dac/Dac2001/papers/2001/dac01/pdffiles/33_1.pdf}, + file = {:SAT/4 - moskewicz01chaff.pdf:PDF} +} + +@INPROCEEDINGS{DBLP:conf/sbmf/MouraB09, + author = {Leonardo Mendon\c{c}a de Moura and Nikolaj Bj{\o}rner}, + title = {Satisfiability Modulo Theories: An Appetizer}, + booktitle = {SBMF}, + year = {2009}, + pages = {23-36}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/sbmf/2009}, + ee = {http://dx.doi.org/10.1007/978-3-642-10452-7_3} +} + +@INPROCEEDINGS{DBLP:conf/tacas/MouraB08, + author = {Leonardo Mendon\c{c}a de Moura and Nikolaj Bj{\o}rner}, + title = {Z3: An Efficient SMT Solver}, + booktitle = {TACAS}, + year = {2008}, + pages = {337-340}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/tacas/2008}, + ee = {http://dx.doi.org/10.1007/978-3-540-78800-3_24} +} + +@INPROCEEDINGS{DBLP:conf/cav/Namjoshi03, + author = {Kedar S. Namjoshi}, + title = {Abstraction for Branching Time Properties.}, + booktitle = {CAV}, + year = {2003}, + pages = {288-300}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/2003}, + ee = {http://springerlink.metapress.com/openurl.asp?genre=article{\&}issn=0302-9743{\&}volume=2725{\&}spage=288}, + file = {abstractforbtl.pdf:/dsk/l1/misc/doc/ctl_auto/abstractforbtl.pdf:PDF}, + keywords = {abstraction} +} + +@INPROCEEDINGS{DBLP:conf/date/NanshiS08, + author = {K.~Nanshi and F.~Somenzi}, + title = {Improved Visibility in One-to-Many Trace Concretization}, + booktitle = {DATE}, + year = {2008}, + pages = {819-824}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/date/2008}, + ee = {http://dx.doi.org/10.1109/DATE.2008.4484775} +} + +@INPROCEEDINGS{DBLP:conf/dac/NanshiS06, + author = {K.~Nanshi and F.~Somenzi}, + title = {Guiding simulation with increasingly refined abstract traces}, + booktitle = {DAC}, + year = {2006}, + pages = {737-742}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/dac/2006}, + ee = {http://doi.acm.org/10.1145/1146909.1147097} +} + +@INPROCEEDINGS{nejati05stutering, + author = {Shiva Nejati and Arie Gurfinkel and Marsha Chechik}, + title = {Stuttering Abstraction for Model Checking}, + booktitle = {SEFM}, + year = {2005}, + pages = {311-320}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/sefm/2005}, + ee = {http://doi.ieeecomputersociety.org/10.1109/SEFM.2005.44}, + file = {nejati05.pdf:/dsk/l1/misc/doc/abstraction/nejati05.pdf:PDF} +} + +@INPROCEEDINGS{DBLP:conf/tcs/Park81, + author = {D.~Park}, + title = {{Concurrency and Automata on Infinite Sequences.}}, + booktitle = {Proceedings of the 5th GI-Conference on Theoretical Computer Science}, + year = {1981}, + pages = {167-183}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/tcs/1981} +} + +@INPROCEEDINGS{peng02tableau, + author = {H.~Peng and Y.~Mokhtari and S.~Tahar}, + title = {Environment {S}ynthesis for {C}ompositional {M}odel {C}hecking.}, + booktitle = {I{CCD}'02: {P}roceedings of the 20th {I}nternational {C}onference + on {C}omputer {D}esign}, + year = {2002}, + pages = {70-}, + address = {Freiburg, Germany}, + publisher = {IEEE Computer Society}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/iccd/2002}, + ee = {http://csdl.computer.org/comp/proceedings/iccd/2002/1700/00/17000070abs.htm} +} + +@INPROCEEDINGS{RaviS04MinimalAssig, + author = {K.~Ravi and F.~Somenzi}, + title = {Minimal Assignments for Bounded Model Checking}, + booktitle = {TACAS'04: Proceedings of 10th International Conference on Tools and + Algorithms for the Construction and Analysis of Systems}, + year = {2004}, + series = {LNCS}, + pages = {31-45}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/tacas/2004}, + ee = {http://springerlink.metapress.com/openurl.asp?genre=article{\&}issn=0302-9743{\&}volume=2988{\&}spage=31}, + file = {:SAT/minimal_assignment_for_bmc.pdf:PDF} +} + +@INPROCEEDINGS{DBLP:conf/cav/RoordaC06, + author = {Jan-Willem Roorda and Koen Claessen}, + title = {SAT-Based Assistance in Abstraction Refinement for Symbolic Trajectory + Evaluation}, + booktitle = {CAV}, + year = {2006}, + pages = {175-189}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/2006}, + ee = {http://dx.doi.org/10.1007/11817963_19} +} + +@INPROCEEDINGS{roux03ctl, + author = {C.~Roux and E.~Encrenaz}, + title = {CTL May Be Ambiguous When Model Checking Moore Machines.}, + booktitle = {CHARME}, + year = {2003}, + pages = {164-169}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/charme/2003}, + ee = {http://springerlink.metapress.com/openurl.asp?genre=article{\&}issn=0302-9743{\&}volume=2860{\&}spage=164}, + file = {rouxctl.pdf:/dsk/l1/misc/doc/modular/model_checking/rouxctl.pdf:PDF}, + keywords = {CTL}, + owner = {cecile}, + timestamp = {2006.02.28}, + url = {http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=2860&spage=164} +} + +@INPROCEEDINGS{DBLP:conf/date/RoychoudhuryMK03, + author = {Abhik Roychoudhury and Tulika Mitra and S. R. Karri}, + title = {Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol.}, + booktitle = {DATE}, + year = {2003}, + pages = {10828-10833}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/date/2003}, + ee = {http://csdl.computer.org/comp/proceedings/date/2003/1870/01/187010828abs.htm}, + keywords = {AMBA} +} + +@INPROCEEDINGS{shohamG04monotonic, + author = {S.~Shoham and O.~Grumberg}, + title = {Monotonic {A}bstraction-{R}efinement for {CTL}.}, + booktitle = {T{ACAS}'04: {P}roceedings of the 10th {I}nternational {C}onference + on {T}ools and {A}lgorithms for the {C}onstruction and {A}nalysis + of {S}ystems}, + year = {2004}, + editor = {Kurt Jensen, Andreas Podelski}, + volume = {2988}, + series = {Lecture Notes in Computer Science}, + pages = {546-560}, + address = {Barcelona, Spain}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/tacas/2004}, + ee = {http://springerlink.metapress.com/openurl.asp?genre=article{\&}issn=0302-9743{\&}volume=2988{\&}spage=546}, + file = {monotone-abs-ref.ps:/dsk/l1/misc/doc/ctl_auto/monotone-abs-ref.ps:PDF}, + keywords = {CTL , abstraction , 3-valued , refinment loop} +} + +@INPROCEEDINGS{somenzi00efficient, + author = {F.~Somenzi and R.~Bloem}, + title = {Efficient B{\"u}chi Automata from LTL Formulae.}, + booktitle = {CAV}, + year = {2000}, + pages = {248-263}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/cav/2000}, + file = {wring.ps:/dsk/l1/misc/doc/ltl_auto/wring.ps:PDF}, + keywords = {LTL, automata approach,}, + owner = {cecile}, + timestamp = {2006.02.13} +} + +@INPROCEEDINGS{StaberFBD06, + author = {Stefan Staber and G{\"o}rschwin Fey and Roderick Bloem and Rolf Drechsler}, + title = {Automatic Fault Localization for Property Checking}, + booktitle = {Haifa Verification Conference}, + year = {2006}, + pages = {50-64}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/hvc/2006}, + ee = {http://dx.doi.org/10.1007/978-3-540-70889-6_4}, + file = {:Debug/FaultLocalizationforpropertychecking-CAD06.pdf:PDF}, + keywords = {Debug, SAT} +} + +@INPROCEEDINGS{DBLP:conf/date/SulflowFBKD09, + author = {Andr{\'e} S{\"u}lflow and G{\"o}rschwin Fey and C{\'e}cile Braunstein + and Ulrich K{\"u}hne and Rolf Drechsler}, + title = {Increasing the accuracy of SAT-based debugging}, + booktitle = {DATE}, + year = {2009}, + pages = {1326-1331}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/date/2009}, + ee = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=5090609{\&}arnumber=5090870{\&}count=326{\&}index=256}, + file = {:Debug/increasingaccuracy-DATE09.pdf:PDF}, + keywords = {Debug, SAT, localization reduction, abstraction} +} + +@INPROCEEDINGS{DBLP:conf/tacas/VelevB98, + author = {Miroslav N. Velev and Randal E. Bryant}, + title = {Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation}, + booktitle = {TACAS}, + year = {1998}, + pages = {136-150}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + crossref = {DBLP:conf/tacas/1998}, + ee = {http://link.springer.de/link/service/series/0558/bibs/1384/13840136.htm}, + file = {:Abstraction/EfficientModelingMemoryArraySymbolicTernarySimulation98.pdf:PDF}, + keywords = {Abstraction, Memory, STE} +} + +@PROCEEDINGS{DBLP:conf/charme/2003, + title = {Correct Hardware Design and Verification Methods CHARME 2003}, + year = {2003}, + editor = {Daniel Geist and Enrico Tronci}, + volume = {2860}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + crossref = {DBLP:conf/charme/2003}, + owner = {cecile}, + timestamp = {2006.02.02} +} + +@MANUAL{rulebase06userguide, + title = {RuleBase Parallel Edition,User's Guide}, + author = {Model Checking Systems group}, + organization = {IBM Labs}, + address = {Haifa, Israel}, + year = {2005}, + note = {verion 1.26}, + owner = {cecile}, + timestamp = {2007.03.07} +} + +@INPROCEEDINGS{Vis, + author = {The {VIS} group}, + title = {{VIS} : {A} {S}ystem for {V}erification and {S}ynthesis}, + booktitle = {CAV'96: Proceedings of the 8th International Conference on Computer + Aided Verification}, + year = {1996}, + editor = {{Rajeev Alur} and {Thomas A. Henzinger}}, + volume = {1102}, + series = {Lecture Notes in Computer Science}, + pages = {428--432}, + address = {New Brunswick, NJ, USA}, + publisher = {Springer-Verlag}, + abstract = {Manual abstraction can be performed by giving a file containing the + names of variables to abstract. For each variable appearing in the + file, a new primary input node is created to drive all the nodes + that were previously driven by the variable. Abstracting a net effectively + allows it to take any value in its range, at every clock cycle. Fair + CTL model checking and language emptiness check VIS performs fair + CTL model checking under Buchi fairness constraints. In addition, + VIS can perform ...}, + citeseerurl = {citeseer.ist.psu.edu/brayton96vis.html}, + comment = {Proceedings of the Eighth International Conference on Computer Aided + Verification}, + keywords = {model checker}, + url = {citeseer.ist.psu.edu/brayton96vis.html} +} + +@ARTICLE{DBLP:journals/fmsd/CohenN09, + author = {Ariel Cohen 0002 and Kedar S. Namjoshi}, + title = {Local proofs for global safety properties}, + journal = {Formal Methods in System Design}, + year = {2009}, + volume = {34}, + pages = {104-125}, + number = {2}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://dx.doi.org/10.1007/s10703-008-0063-8}, + keywords = {Refinement} +} + +@ARTICLE{akers78, + author = {B.~Akers}, + title = {Binary Decision Diagrams}, + journal = {IEEE Transactions on Computers}, + year = {1978}, + volume = {27}, + pages = {509--516}, + number = {6}, + abstract = { The seminal paper in which BDD's were introduced. Note that none + of the today implementation techniques for BDD package is given in + this paper. }, + keywords = {BDD description} +} + +@INPROCEEDINGS{alfaro01interface, + author = {L.~de Alfaro and T.A.~Henzinger}, + title = {Interface automata}, + booktitle = {ESEC/FSE-9: Proceedings of the 8th European software engineering + conference held jointly with 9th ACM SIGSOFT international symposium + on Foundations of software engineering}, + year = {2001}, + pages = {109--120}, + address = {New York, NY, USA}, + publisher = {ACM Press}, + doi = {http://doi.acm.org/10.1145/503209.503226}, + isbn = {1-58113-390-1}, + location = {Vienna, Austria} +} + +@INPROCEEDINGS{bhdl03, + author = {A.~Aljer and P.~Devienne and S.~Tison and J-L.~Boulanger and G.~Mariano}, + title = {{BHDL: Circuit Design in B}}, + booktitle = {ACSD '03: Proceedings of the Third International Conference on Application + of Concurrency to System Design}, + year = {2003}, + editor = {IEEE Computer Society}, + pages = {241}, + address = {Washington, DC, USA}, + isbn = {0-7695-1887-7} +} + +@INPROCEEDINGS{alur99automating, + author = {R. Alur and L.~de Alfaro and T. A. Henzinger and F.~Y.C. Mang}, + title = {Automating Modular Verification}, + booktitle = {CONCUR '99: Concurrency Theory, 10th International Conference, Eindhoven, + The Netherlands, August 24-27, 1999, Proceedings}, + year = {1999}, + editor = {Jos C. M. Baeten and Sjouke Mauw}, + volume = {1664}, + series = {Lecture Notes in Computer Science}, + pages = {82-97}, + address = {Eindhoven, The Netherlands}, + publisher = {Springer}, + abstract = {Modular techniques for automatic verification attempt to overcome + the state-explosion problem by exploiting the modular structure naturally + present in many system designs. Unlike other tasks in the verification + of finite-state systems, current modular techniques rely heavily + on user guidance. In particular, the user is typically required to + construct module abstractions that are neither too detailed as to + render insufficient benefits in state exploration, nor too coarse + as to invalidate the desired system properties. In this paper, we + construct abstract modules automatically, using reachability and + controllability information about the concrete modules. This allows + us to leverage automatic verification techniques by applying them + in layers: first we compute on the state spaces of system components, + then we use the results for constructing abstractions, and finally + we compute on the abstract state space of the system. Our experimental + results indicate that if reachability and controllabil ity information + is used in the construction of abstractions, the resulting abstract + modules are often significantly smaller than the concrete modules + and can drastically reduce the space and time requirements for verification.}, + file = {automatic_modular.pdf:/dsk/l1/misc/doc/modular/modular/automatic_modular.pdf:PDF}, + keywords = {modular, abstraction, refinment loop, case study}, + owner = {cecile}, + timestamp = {2006.02.06}, + url = {http://link.springer.de/link/service/series/0558/bibs/1664/16640082.htm} +} + +@ARTICLE{DBLP:journals/fmsd/AlurH99b, + author = {R.~Alur and T.A.~Henzinger}, + title = {Reactive Modules.}, + journal = {Formal Methods in System Design}, + year = {1999}, + volume = {15}, + pages = {7-48}, + number = {1}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + publisher = {Springer} +} + +@INPROCEEDINGS{alur98mocha, + author = {R.~Alur and T.A.~Henzinger and F.Y. C.~Mang and S.~Qadeer and S.K.~Rajamani + and S.~Tasiran}, + title = {{MOCHA}: {M}odularity in {M}odel {C}hecking}, + booktitle = {CAV'98: Proceedings of the 10th International Conference on Computer + Aided Verification}, + year = {1998}, + volume = {1427}, + series = {Lecture Notes in Computer Science}, + pages = {521-525}, + address = {London, UK}, + abstract = {We describe a new interactive verification environment called Mocha + for modular verification of heterogeneous systems. Mocha differs + from existing model checkers in three important ways. First, instead + of manipulating unstructured statetransition graphs, it supports + the heterogeneous modeling framework of Reactive Modules. Second, + instead of traditional temporal logics such as CTL, it uses Alternating + Temporal Logic (ATL), a temporal logic that is designed to specify + collaborative as ...}, + file = {alur98mocha.ps.gz:/dsk/l1/misc/doc/modular/mocha/alur98mocha.ps.gz:PDF}, + keywords = {model checker, atl, modular} +} + +@INPROCEEDINGS{amla01assume, + author = {N.~Amla and E.~A.~Emerson and K.~S.~Namjoshi and R.~J.~Trefler}, + title = {Assume-Guarantee Based Compositional Reasoning for Synchronous Timing + Diagrams}, + booktitle = {TACAS 2001: Proceedings of the 7th International Conference on Tools + and Algorithms for the Construction and Analysis of Systems}, + year = {2001}, + pages = {465--479}, + address = {London, UK}, + publisher = {Springer-Verlag}, + isbn = {3-540-41865-2} +} + +@ARTICLE{arieliA98value, + author = {Ofer Arieli and Arnon Avron}, + title = {The Value of the Four Values.}, + journal = {Artif. Intell.}, + year = {1998}, + volume = {102}, + pages = {97-141}, + number = {1}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://dx.doi.org/10.1016/S0004-3702(98)00032-0}, + file = {arieli98four.ps:/dsk/l1/misc/doc/logique/arieli98four.ps:PDF}, + keywords = {4-valued, logic} +} + +@BOOK{arnold94finite, + title = {Finite {T}ransition {S}ystems: {S}emantics of {C}ommunicating {S}ystems}, + publisher = {Prentice Hall International Ltd.}, + year = {1994}, + editor = {Translator-John Plaice}, + author = {A.~Arnold}, + address = {Hertfordshire,UK}, + isbn = {0-13-092990-5}, + keywords = {simulation} +} + +@ARTICLE{DBLP:journals/entcs/AwedhS06, + author = {M.~Awedh and F.~Somenzi}, + title = {Termination Criteria for Bounded Model Checking: Extensions and Comparison}, + journal = {Electronic Notes in Theoritical Computer Science.}, + year = {2006}, + volume = {144}, + pages = {51-66}, + number = {1}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://dx.doi.org/10.1016/j.entcs.2005.07.019}, + file = {:BMC/TerminationCriteriaForBMC06.pdf:PDF}, + keywords = {BMC, VIS} +} + +@MANUAL{bmanual, + title = {{B-Toolkit User's Manual}}, + author = {{B-Core(UK) Ltd.}}, + edition = {release 3.7}, + year = {1997}, + keywords = {b method}, + owner = {cecile}, + timestamp = {2006.07.31}, + url = {http://www.b-core.com/downloading.html} +} + +@INPROCEEDINGS{BP-msr03, + author = {M.~Baclet and R.~Pacalet}, + title = {V{\'e}rifications du protocole~{VCI}}, + booktitle = {{A}ctes du 4{\`e}me {C}olloque sur la {M}od{\'e}lisation des {S}yst{\`e}mes + {R}{\'e}actifs ({MSR}'03)}, + year = {2003}, + editor = {M{\'e}ry, Dominique and Rezg, Nidhal and Xie, Xiaolan}, + pages = {431-445}, + address = {Metz, France}, + month = oct, + publisher = {Herm{\`e}s}, + keywords = {protocol}, + url = {http://www.lsv.ens-cachan.fr/Publis/PAPERS/PS/vci-msr03.ps} +} + +@INPROCEEDINGS{broissyval, + author = {F.~Badeau and A.~Amelot}, + title = {{Using B as a High Level Programming Language in an Industrial Project: + Roissy VAL}}, + booktitle = {ZB 2005: Formal Specification and Development in Z and B}, + year = {2005}, + volume = {3455/2005}, + series = {Lecture Notes in Computer Science}, + pages = {334-354}, + publisher = {Springer Berlin / Heidelberg}, + doi = {10.1007/11415787_20}, + keywords = {b method}, + owner = {cecile}, + timestamp = {2007.01.31}, + url = {http://www.springerlink.com/content/x8mcgk2p8r82e2gl/} +} + +@INPROCEEDINGS{503274, + author = {T.~Ball and S.K.~Rajamani}, + title = {The {SLAM} project: debugging system software via static analysis}, + booktitle = {POPL '02: Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on + Principles of programming languages}, + year = {2002}, + pages = {1--3}, + address = {New York, NY, USA}, + doi = {http://doi.acm.org/10.1145/503272.503274}, + isbn = {1-58113-450-9}, + keywords = {CEGAR, refinment loop, model checking software}, + location = {Portland, Oregon}, + owner = {cecile}, + timestamp = {2007.01.14} +} + +@INPROCEEDINGS{rulebase96, + author = {I.~Beer and S.~Ben-David and C.~Eisner and A.~Landver}, + title = {{RuleBase: an industry-oriented formal verification tool}}, + booktitle = {DAC '96: Proceedings of the 33rd annual conference on Design automation}, + year = {1996}, + series = {ACM Press}, + pages = {655--660}, + address = {New York, NY, USA}, + doi = {http://doi.acm.org/10.1145/240518.240642}, + isbn = {0-89791-779-0}, + location = {Las Vegas, Nevada, United States}, + owner = {cecile}, + timestamp = {2007.01.31} +} + +@INPROCEEDINGS{1517440, + author = {Bjesse, Per}, + title = {Word-level sequential memory abstraction for model checking}, + booktitle = {FMCAD '08: Proceedings of the 2008 International Conference on Formal + Methods in Computer-Aided Design}, + year = {2008}, + pages = {1--9}, + address = {Piscataway, NJ, USA}, + publisher = {IEEE Press}, + file = {:Cegar/worllevelSeqMemAbstrforMCbjesse08.pdf:PDF}, + isbn = {978-1-4244-2735-2}, + keywords = {Abstractions, Model-checking}, + location = {Portland, Oregon} +} + +@TECHREPORT{prosyd05, + author = {R. Bloem and B. Jobstmann and A. Pnueli.}, + title = {{Property-based Logic Synthesis for Rapid Design Prototyping}}, + institution = {Prosyd Deliverable D2.2/1}, + year = {2005}, + owner = {cecile}, + timestamp = {2007.02.07} +} + +@ARTICLE{bozga97protocol, + author = {M.~Bozga and J-C.~Fernandez and A.~Kerbrat and L.~Mounier}, + title = {Protocol {V}erification with the {ALD{\'E}BARAN} {T}oolset.}, + journal = {STTT}, + year = {1997}, + volume = {1}, + pages = {166-184}, + number = {1-2}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://link.springer.de/link/service/journals/10009/bibs/7001001/70010166.htm}, + keywords = {model checking, model checker}, + publisher = {Springer} +} + +@TECHREPORT{Brady:EECS-2008-136, + author = {Brady, Bryan and Bryant, Randal and Seshia, Sanjit A.}, + title = {Abstracting RTL Designs to the Term Level}, + institution = {EECS Department, University of California, Berkeley}, + year = {2008}, + number = {UCB/EECS-2008-136}, + month = {Oct}, + abstract = {Term-level verification is a formal technique that seeks to verify + RTL hardware descriptions by abstracting away details of data representations + and operations. The key to making term-level verification automatic + and efficient is in deciding what to abstract. We investigate this + question in this paper and propose a solution based on the use of + type qualifiers. First, we demonstrate through case studies that + only selective term-level abstraction can be very effective in reducing + the run-time of formal tools while still retaining precision of analysis. + Second, the term-level abstraction process can be guided using lightweight + type qualifiers. We present an annotation language and type inference + scheme that is applied to the formal verification of the Verilog + implementation of a chip multiprocessor router. Experimental results + indicate type-based selective term-level abstraction is effective + at scaling up verification with minimal designer guidance.}, + file = {:Abstraction/abstractingRTLtoTermLevel.pdf:PDF}, + keywords = {Abstraction, memory}, + owner = {cecile}, + timestamp = {2010.06.10}, + url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-136.html} +} + +@PHDTHESIS{braunstein_phd07, + author = {C.~Braunstein}, + title = {"Conception Incrémentale, Vérification de Composants Matériels et + Méthode d'abstraction pour la Vérification de SystÚmes Intégrés sur + Puce"}, + school = {{Universitée Pierre et Marie Curie (Paris 6)}}, + year = {2007}, + address = {LIP6/SOC}, + owner = {cecile}, + timestamp = {2007.04.16} +} + +@TECHREPORT{cecile03dea, + author = {C.~Braunstein}, + title = {{Transformation de propri\'et\'es CTL lors d'une m\'ethode de conception + incr\'ementale des wrappers {VCI/PI}}}, + institution = {LIP6/ASIM}, + year = {2003}, + type = {Rapport de {DEA}}, + owner = {cecile}, + timestamp = {2006.09.07} +} + +@ARTICLE{braunstein06sttt, + author = {C.~Braunstein and E.~Encrenaz}, + title = {{CTL}-property {T}ransformations along an {I}ncremental {D}esign + {P}rocess}, + journal = {International Journal on Software Tools for Technology Transfer (STTT)}, + year = {2007}, + volume = {9}, + pages = {77--88}, + number = {1}, + note = {A long version including the proof is available at www-asim.lip6.fr/~cecile}, + owner = {cecile}, + publisher = {Springer}, + timestamp = {2006.09.05} +} + +@INPROCEEDINGS{braunstein07acsd, + author = {C.~Braunstein and E.~Encrenaz}, + title = {Using CTL formulae as Component Abstraction in a Design and Verification + Flow}, + booktitle = {ACSD'07: Proceedings of the 7th International Conference on Application + of Concurrency to System Design}, + year = {2007}, + note = {accepted}, + owner = {cecile}, + timestamp = {2007.03.27} +} + +@INPROCEEDINGS{braunstein06lpar, + author = {C.~Braunstein and E.~Encrenaz}, + title = {A Further Step in the Incremental Design Process: Incorporation of + an Increment Specification}, + booktitle = {LPAR'06: Proceeding of the 13th International Conference on Logic + for Programming, Artificial Intelligence, and Reasoning}, + year = {2006}, + note = {{\it short paper}, proceedings online \url{http://www.lix.polytechnique.fr/~hermann/LPAR2006/}}, + owner = {cecile}, + timestamp = {2007.03.27} +} + +@TECHREPORT{Braunstein_Encrenaz_RR_LIP6_07_2006, + author = {C.~Braunstein and E.~Encrenaz}, + title = {Using CTL formulae as component abstraction}, + institution = {UPMC/LIP6}, + year = {2006}, + type = {Research report}, + owner = {cecile}, + timestamp = {2006.09.29} +} + +@INPROCEEDINGS{pipeline06, + author = {C.~Braunstein and E.~Encrenaz}, + title = {Formalizing the Incremental Design and Verification Process of a + Pipelined Protocol Converter}, + booktitle = {RSP '06: Proceedings of the Seventeenth IEEE International Workshop + on Rapid System Prototyping (RSP'06)}, + year = {2006}, + pages = {103--109}, + address = {Washington, DC, USA}, + publisher = {IEEE Computer Society}, + doi = {http://dx.doi.org/10.1109/RSP.2006.19}, + isbn = {0-7695-2580-6}, + owner = {cecile}, + timestamp = {2006.08.31} +} + +@ARTICLE{avocs_incr, + author = {C.~Braunstein and E.~Encrenaz}, + title = {{CTL}-{P}roperty {T}ransformations along an {I}ncremental {D}esign + {P}rocess}, + journal = {Electronic Notes in Theoretical Computer Science}, + year = {2005}, + volume = {128}, + pages = {263--278}, + number = {6}, + file = {braunstein_avocs_o4.pdf:/dsk/l1/misc/Article/Concep_incr/Avocs/Avocs_paper/braunstein_avocs_o4.pdf:PDF}, + issue = {6}, + publisher = {Elsevier}, + series = {AVOCS'04~-~Proceedings of the 4th International Workshop on Automated + Verification of Critical Systems} +} + +@ARTICLE{browneclarkegrum88, + author = {M.C.~Browne and E.M.~Clarke and O.~Grumberg}, + title = {Characterizing {F}inite {K}ripke {S}tructures in {P}ropositional + {T}emporal {L}ogic}, + journal = {Theoritical Computer Science}, + year = {1988}, + volume = {59}, + pages = {115--131}, + number = {1-2}, + doi = {http://dx.doi.org/10.1016/0304-3975(88)90098-9}, + issn = {0304-3975}, + publisher = {Elsevier Science Publishers Ltd.} +} + +@ARTICLE{Bryant86, + author = {R.E.~Bryant}, + title = {{Graph-Based Algorithms for Boolean Function Manipulation}}, + journal = {IEEE Transactions on Computers}, + year = {1986}, + volume = {35}, + pages = {677-691}, + number = {8}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + keywords = {BDD}, + owner = {cecile}, + timestamp = {2006.11.07} +} + +@INPROCEEDINGS{bunker:idpt02, + author = {A.~Bunker and G.~Gopalakrishnan}, + title = {{Verifying a VCI Bus Interface Model Using an LSC-based Specification}}, + booktitle = {Proceedings of the Sixth Biennial World Conference on Integrated + Design and Process Technology}, + year = {2002}, + editor = {H. Ehrig and B. J. Kr\"amer and A. Ertas}, + pages = {48}, + month = {June}, + organization = {Society of Design and Process Science}, + keywords = {protocol}, + url = {http://www.engineering.usu.edu/ece/faculty/bunker/pubs/idpt02.pdf} +} + +@ARTICLE{macmillan, + author = {J.R.~Burch and E.M.~Clarke and K.L.~McMillan and D.L.~Dill and L.J.~Hwang}, + title = {Symbolic {M}odel {C}hecking: $10^{20}$ {S}tates and {B}eyond}, + journal = {{I}nformation and {C}omputation }, + year = {1992}, + volume = {98}, + pages = {142--170}, + number = {2}, + note = {Special issue for best papers from LICS'90}, + address = {Duluth, MN, USA}, + publisher = {Academic Press, Inc.} +} + +@INPROCEEDINGS{burch94automatic, + author = {J.R.~Burch and D.L.~Dill}, + title = {Automatic {V}erification of {P}ipelined {M}icroprocessors {C}ontrol}, + booktitle = {Proceedings of the sixth International Conference on Computer-Aided + Verification {CAV'94}}, + year = {1994}, + editor = {{D.L.~Dill}}, + volume = {LNCS 818}, + pages = {68--80}, + address = {Standford, California, USA}, + publisher = {Springer-Verlag}, + citeseerurl = {citeseer.ist.psu.edu/burch94automatic.html}, + keywords = {model checking, pipeline, archi}, + url = {citeseer.ist.psu.edu/burch94automatic.html} +} + +@ARTICLE{bryant82, + author = {J.R.~Burch and D.L.~Dill}, + title = {Graph-Based Algorithms for Boolean Function Manipulation}, + journal = {IEEE Transactions on Computers}, + year = {1982}, + volume = {35}, + pages = {677--691}, + number = {8}, + month = {August}, + abstract = {Available} +} + +@INPROCEEDINGS{Cabodi09Speeding, + author = {G. Cabodi and P. Camurati and L. Garcia and M. Murciano and S. Nocco + and S. Quer}, + title = {Speeding up Model Checking by Exploiting Explicit and Hidden Verification + Constraints}, + booktitle = {DATE '09: Proceedings of the conference on Design, Automation and + Test in Europe}, + year = {2009}, + pages = {1686-1691}, + file = {:Composition/Speeding up MC by exploiting Explicit09.PDF:PDF}, + owner = {cecile}, + timestamp = {2009.04.30} +} + +@INCOLLECTION{Cansell2001AbstractionandRefinementofFeatures, + author = {D.~Cansell and D.~M{\'e}ry}, + title = {Abstraction and {R}efinement of {F}eatures}, + booktitle = {{Language Constructs for Designing Features}}, + publisher = {Springer-Verlag}, + year = {2001}, + editor = {S.~Gilmore and M.~Ryan}, + pages = {65--84}, + abstract = {The composition of services and features often leads to unwanted situations, + because it is a non-monotonic operation over services and features. + When a new service is added to an existing system, conditions have + to be checked to ensure that the resulting system satisfies a list + of required properties. Following the system approach of Abrial, + we develop services and features in an incremental way and use refinement + to model the composition of services and features. Proof obligations + state the preservation or the non-preservation of properties, namely + invariant or more generally safety properties. The method helps us + in understanding when a service is interfering with another, and + allows us to give multiple views of each service according to the + level of its refinement. Finally, we validate our method with the + Atelier B tool.} +} + +@INCOLLECTION{cassez-proving, + author = {F.~Cassez and M.~Ryan and P-Y.~Schobbens}, + title = {Proving {F}eature {N}on-{I}nteraction with {A}lternating-{T}ime {T}emporal + {L}ogic}, + booktitle = {{Language Constructs for Describing Features}}, + publisher = {Springer Verlag}, + year = {2001}, + editor = {S.~Gilmore and M.~Ryan}, + pages = {85--104} +} + +@ARTICLE{chechik03multi, + author = {M.~Chechik and B.~Devereux and S.~M.~Easterbrook and A.~Gurfinkel}, + title = {{Multi-Valued Symbolic Model-Checking}}, + journal = {ACM Transactions on Software Engineering and Methodology}, + year = {2003}, + volume = {12}, + pages = {371-408}, + number = {4}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://doi.acm.org/10.1145/990010.990011}, + file = {chechik03a.pdf:/dsk/l1/misc/doc/abstraction/chechik03a.pdf:PDF}, + keywords = {abstraction, 3-valued, 4-valued, logic, model checking} +} + +@INPROCEEDINGS{846816, + author = {Hoon Choi and Myung-Kyoon Yim and Jae-Young Lee and Byeong-Whee Yun + and Yun-Tae Lee}, + title = {Formal Verification of an Industrial System-on-a-Chip}, + booktitle = {ICCD '00: Proceedings of the 2000 IEEE International Conference on + Computer Design}, + year = {2000}, + pages = {453}, + address = {Washington, DC, USA}, + publisher = {IEEE Computer Society}, + isbn = {0-7695-0801-4}, + keywords = {AMBA} +} + +@INPROCEEDINGS{CLS00, + author = {G. Ciardo and G. L\"uttgen and R. Siminiceanu}, + title = {Efficient Symbolic State-Space Construction for Asynchronous Systems}, + booktitle = {Proc. of ICATPN'2000}, + year = {2000}, + volume = {1825}, + series = {Lecture Notes in Computer Science}, + pages = {103--122}, + publisher = {Springer Verlag} +} + +@ARTICLE{cimatti00nusmv, + author = {A.~Cimatti and E.M.~Clarke and F.~Giunchiglia and M.~Roveri}, + title = {NUSMV: A New Symbolic Model Checker.}, + journal = {STTT}, + year = {2000}, + volume = {2}, + pages = {410-425}, + number = {4}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://link.springer.de/link/service/journals/10009/bibs/0002004/00020410.htm} +} + +@ARTICLE{DBLP:journals/tocl/CimattiGS10, + author = {Alessandro Cimatti and Alberto Griggio and Roberto Sebastiani}, + title = {Efficient generation of craig interpolants in satisfiability modulo + theories}, + journal = {ACM Trans. Comput. Log.}, + year = {2010}, + volume = {12}, + pages = {7}, + number = {1}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://doi.acm.org/10.1145/1838552.1838559} +} + +@ARTICLE{Clarke1986, + author = {E.M.~Clarke and E.A.~Emerson and A.P.~Sistla}, + title = {Automatic verification of finite-state concurrent systems using temporal + logic specifications}, + journal = {ACM Transactions on Programming Languages and Systems}, + year = {1986}, + volume = {8}, + pages = {244--263}, + number = {2}, + booktitle = {ICATPN'02: Proceedings of the 23rd International Conference on Applications + and Theory of Petri Nets}, + doi = {http://doi.acm.org/10.1145/5397.5399}, + issn = {0164-0925}, + publisher = {ACM Press} +} + +@ARTICLE{clarke94model, + author = {E.M.~Clarke and O.~Grumberg and D.E.~Long}, + title = {{Model Checking and Abstraction}}, + journal = {ACM Transactions on Programming Languages and Systems}, + year = {1994}, + volume = {16}, + pages = {1512--1542}, + number = {5}, + address = {New York, NY, USA}, + doi = {http://doi.acm.org/10.1145/186025.186051}, + issn = {0164-0925}, + keywords = {model cheking, abstraction, CTL, preservation}, + publisher = {ACM Press} +} + +@BOOK{clarke99model, + title = {Model Checking}, + publisher = {The {MIT} {P}ress}, + year = {1999}, + author = {E.M.~Clarke and O.~Grumberg and D.A.~Peled}, + address = {Cambridge, Massachusetts}, + isbn = {0-262-03270-8}, + keywords = {CTL,LTL, model checking,kripke structure, simulation} +} + +@ARTICLE{Clarke03cegarsymbolic, + author = {E.~M. Clarke and O. Grumberg and S. Jha and Y. Lu and H. Veith}, + title = {Counterexample-guided bstraction refinement for symbolic model checking.}, + journal = {Journal of the ACM}, + year = {2003}, + volume = {50}, + pages = {752-794}, + number = {5}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://doi.acm.org/10.1145/876638.876643}, + file = {:Cegar/Counterexample-guided abstraction refinement.pdf:PDF}, + keywords = {abstraction, CEGAR}, + owner = {cecile}, + timestamp = {2006.06.27} +} + +@INPROCEEDINGS{DBLP:conf/dac/ClarkeGMZ95, + author = {Edmund M. Clarke and Orna Grumberg and Kenneth L. McMillan and Xudong + Zhao}, + title = {Efficient Generation of Counterexamples and Witnesses in Symbolic + Model Checking}, + booktitle = {DAC}, + year = {1995}, + pages = {427-432}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://doi.acm.org/10.1145/217474.217565} +} + +@ARTICLE{DBLP:journals/tcad/ClarkeGS04, + author = {Edmund M. Clarke and Anubhav Gupta and Ofer Strichman}, + title = {SAT-based counterexample-guided abstraction refinement}, + journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, + year = {2004}, + volume = {23}, + pages = {1113-1123}, + number = {7}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://doi.ieeecomputersociety.org/10.1109/TCAD.2004.829807}, + file = {:Cegar/SATBasedCegar2004Clarke.pdf:PDF}, + keywords = {CEGAR,SAT}, + owner = {cecile}, + timestamp = {2010.06.03} +} + +@MISC{tata97, + author = {H. Comon and M. Dauchet and R. Gilleron and F. Jacquemard and D. + Lugiez and S. Tison and M. Tommasi}, + title = {Tree Automata Techniques and Applications}, + howpublished = {Available on: \url{http://www.grappa.univ-lille3.fr/tata}}, + year = {1997}, + note = {release October, 1rst 2002}, + file = {tata.pdf:/dsk/l1/misc/doc/automate/tata.pdf:PDF}, + keywords = {tree automata} +} + +@INPROCEEDINGS{madre, + author = {O.~Coudert and J.-C.~Madre}, + title = {A New Method to Compute Prime and Essential Prime Implicants of Boolean + Functions}, + booktitle = {Advanced Research in VLSI and Parallel Systems}, + year = {1992}, + editor = {T.~Knight and J.~Savage}, + pages = {113--128}, + month = {March}, + abstract = { This paper presents how prime implicants and essential prime implicants + can be computed by means of meta-products encoded with of BDD's. + It gives the equations that mimic the definitions, but it does not + propose a recursive algorithm. The variable ordering is discussed + and experimental results are provided that come from a benchmark + of circuits. }, + keywords = {Prime Implicants} +} + +@INPROCEEDINGS{DBLP:conf/popl/CousotC77, + author = {P.~Cousot and R.~Cousot}, + title = {Abstract Interpretation: A Unified Lattice Model for Static Analysis + of Programs by Construction or Approximation of Fixpoints.}, + booktitle = {POPL'77: Proceedings of the 14th Annual ACM Symposium on Principles + of Programming Languages}, + year = {1977}, + pages = {238-252}, + address = {Munich, Germany}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + keywords = {abstraction}, + owner = {cecile}, + timestamp = {2007.01.13} +} + +@INPROCEEDINGS{jmc-ag-djs:ddd, + author = {J.M.~Couvreur and A.~Griffault and D.J.~Sherman}, + title = {Diagrammes de d\'ecision pour la v\'erification de r\'eseaux \`a + files}, + booktitle = {Mod\'elisation de syst\`emes r\'eactifs (MSR'99)}, + year = {1999}, + address = {ENS Cachan}, + month = {March} +} + +@INPROCEEDINGS{CA94, + author = {J.M. Couvreur and E. Paviot-Adet}, + title = {New Structural Invariants for {P}etri Nets Analysis}, + booktitle = {Proc. of ICATPN'94}, + year = {1994}, + volume = {815}, + series = {Lecture Notes in Computer Science}, + pages = {199--218}, + publisher = {Springer Verlag} +} + +@ARTICLE{dams97abstract, + author = {D.~Dams and R.~Gerth and O.~Grumberg}, + title = {Abstract interpretation of reactive systems}, + journal = {ACM Transactions on Programming Languages and Systems}, + year = {1997}, + volume = {19}, + pages = {253--291}, + number = {2}, + address = {New York, NY, USA}, + doi = {http://doi.acm.org/10.1145/244795.244800}, + issn = {0164-0925}, + keywords = {abstraction}, + publisher = {ACM Press} +} + +@INPROCEEDINGS{Darbari08transient, + author = {Darbari, A. and Al Hashimi, B. and Harrod, P. and Bradley, D.}, + title = {A New Approach for Transient Fault Injection Using Symbolic Simulation}, + booktitle = {IEEE International Symposium On-line Testing Symposium}, + year = {2008}, + pages = {93-98}, + month = {July}, + doi = {10.1109/IOLTS.2008.59}, + journal = {On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International}, + keywords = {fault tolerance, fault trees, reduced instruction set computing, temporal + logicbinary image, multicycle RISC processor, program image. shadow, + symbolic simulation, transient fault injection} +} + +@MISC{duret03dea, + author = {A.~Duret-Lutz and R.~Rebiha}, + title = {SPOT : Une bibliothÚque de vérificaion de propriétés de logique + temporelle à temps linéaire}, + year = {2003}, + file = {rap_stage_duret_lutz_2003.pdf:/dsk/l1/misc/doc/ltl_auto/rap_stage_duret_lutz_2003.pdf:PDF}, + keywords = {LTL, automata approach}, + owner = {cecile}, + timestamp = {2006.02.13} +} + +@INPROCEEDINGS{dwyer99patterns, + author = {M. B. Dwyer and G. S. Avrunin and J. C. Corbett}, + title = {{Patterns in Property Specifications for Finite-State Verification.}}, + booktitle = {ICSE' 99. Proceedings of the 1999 International Conference on Software + Engineering}, + year = {1999}, + editor = {ACM}, + pages = {411-420}, + address = {Los Angeles, CA, USA}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://portal.acm.org/citation.cfm?id=302405.302672}, + keywords = {CTL , patterns , Specification}, + url = {http://patterns.projects.cis.ksu.edu/collaborations/papers.shtml} +} + +@ARTICLE{DBLP:journals/tcad/FeySBD08, + author = {G{\"o}rschwin Fey and Stefan Staber and Roderick Bloem and Rolf Drechsler}, + title = {Automatic Fault Localization for Property Checking}, + journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, + year = {2008}, + volume = {27}, + pages = {1138-1149}, + number = {6}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://dx.doi.org/10.1109/TCAD.2008.923234} +} + +@ARTICLE{fitting91bilattices, + author = {M.~Fitting}, + title = {{Bilattices and the Semantics of Logic Programming.}}, + journal = {Journal of Logic Programming}, + year = {1991}, + volume = {11}, + pages = {91-116}, + number = {1{\&}2}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + file = {BilSemLP.pdf:/dsk/l1/misc/doc/logique/BilSemLP.pdf:PDF}, + keywords = {4-valued, logic, 3-valued}, + owner = {cecile}, + timestamp = {2006.04.05} +} + +@INPROCEEDINGS{godefroid03expressiveness, + author = {Patrice Godefroid and Radha Jagadeesan}, + title = {On the Expressiveness of 3-Valued Models}, + booktitle = {VMCAI 2003: Proceedings of the 4th International Conference on Verification, + Model Checking, and Abstract Interpretation}, + year = {2003}, + pages = {206--222}, + address = {London, UK}, + publisher = {Springer-Verlag}, + file = {vmcai2003.ps:/dsk/l1/misc/doc/logique/vmcai2003.ps:PDF}, + isbn = {3-540-00348-7}, + keywords = {3-valued, logic, model checking, Kripke structure} +} + +@INPROCEEDINGS{goelL00formal, + author = {A.~Goel and W.~R.~Lee}, + title = {{{F}ormal {V}erification of an {IBM} {C}ore{C}onnect {P}rocessor + {L}ocal {B}us {A}rbiter {C}ore}}, + booktitle = {DAC'00: Proceedings of the 37th Conference on Design Automation}, + year = {2000}, + editor = {ACM}, + pages = {196-200}, + address = {Los Angeles, CA, USA}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://doi.acm.org/10.1145/337292.337384}, + file = {p196-goel.pdf:/dsk/l1/misc/doc/verif_archi/rulebase/p196-goel.pdf:PDF}, + keywords = {CTL, model checking, Rulebase}, + owner = {cecile}, + timestamp = {2006.06.29} +} + +@INPROCEEDINGS{GL91, + author = {O.~Grumberg and D.E.~Long}, + title = {Model {C}hecking and {M}odular {V}erification}, + booktitle = {International Conference on Concurrency Theory}, + year = {1991}, + volume = {527}, + series = {Lecture Notes in Computer Science}, + pages = {250--263}, + publisher = {Springer Verlag}, + file = {p843-grumberg.pdf:/dsk/l1/misc/doc/modular/model_checking/p843-grumberg.pdf:PDF}, + keywords = {simulation,CTL, modular} +} + +@ARTICLE{Gupta92syrvey, + author = {A.~Gupta}, + title = {{Formal Hardware Verification Methods: A Survey.}}, + journal = {Formal Methods in System Design}, + year = {1992}, + volume = {1}, + pages = {151-238}, + number = {2/3}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + keywords = {survey, hardware, formal verification} +} + +@INPROCEEDINGS{henzinger99dsp, + author = {T.~A.~Henzinger and X.~Liu and S.~Qadeer and S.~K.~Rajamani}, + title = {Formal {S}pecification and {V}erification of a {D}ataflow {P}rocessor + {A}rray.}, + booktitle = {I{CCAD}'99: {P}roceedings of the 1999 {IEEE}/{ACM} {I}nternational + {C}onference on {C}omputer-{A}ided {D}esign}, + year = {1999}, + editor = {Jacob K. White, Ellen Sentovich}, + pages = {494-499}, + address = {San Jose, USA}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://portal.acm.org/citation.cfm?id=339492.340066}, + file = {formal_specification_and_verification_of_a_dataflow_processor_array.pdf:/dsk/l1/misc/doc/modular/mocha/formal_specification_and_verification_of_a_dataflow_processor_array.pdf:PDF}, + keywords = {abstraction, assume-guarantee, ATL, modular, archi, MOCHA} +} + +@INPROCEEDINGS{henzinger00decomposing, + author = {Thomas A. Henzinger and Shaz Qadeer and Sriram K. Rajamani}, + title = {Decomposing refinement proofs using assume-guarantee reasoning}, + booktitle = {ICCAD '00: Proceedings of the 2000 IEEE/ACM international conference + on Computer-aided design}, + year = {2000}, + pages = {245--253}, + address = {San Jose, California}, + publisher = {IEEE Press}, + file = {decomposing00henzinger.pdf:/dsk/l1/misc/doc/modular/assume/decomposing00henzinger.pdf:PDF}, + isbn = {0-7803-6448-1} +} + +@INPROCEEDINGS{C:HJMS03, + author = {Henzinger, T.A. and Jhala, R. and Majumdar, R. and Sutre, G.}, + title = {Software {V}erification with {BLAST}}, + booktitle = {SPIN'2003: Proceedings of the 10th International SPIN Workshop}, + year = {2003}, + volume = {2648}, + series = {Lecture Notes in Computer Science}, + pages = {235--239}, + address = {USA}, + publisher = {Springer}, + note = {Tool paper}, + keywords = {software, model-checking}, + url = {http://www.labri.fr/publications/mvtsi/2003/HJMS03} +} + +@INPROCEEDINGS{henzinger98you, + author = {T.A.~Henzinger and S.~Qadeer and S.K.~Rajamani}, + title = {{Y}ou {A}ssume, {W}e {G}uarantee: {M}ethodology and {C}ase {S}tudies}, + booktitle = {C{AV}'98: {P}roceedings of the 10th {I}nternational {C}onference + on {C}omputer {A}ided {V}erification}, + year = {1998}, + editor = {Alan J. Hu, Moshe Y. Vardi}, + volume = {1427}, + series = {Lecture Notes in Computer Science}, + pages = {440--451}, + address = {Vancouver, Canada}, + publisher = {Springer-Verlag}, + file = {henzinger98you.ps.gz:/dsk/l1/misc/doc/modular/assume/henzinger98you.ps.gz:PDF} +} + +@ARTICLE{henzinger02anassume, + author = {T.A.~Henzinger and S.~Qadeer and S.K.~Rajamani and S.~Tasiran}, + title = {An {A}ssume-{G}uarantee {R}ule for {C}hecking {S}imulation}, + journal = {ACM Transactions on Programming Languages Systems}, + year = {2002}, + volume = {24}, + pages = {51--64}, + number = {1}, + address = {New York, NY, USA}, + doi = {http://doi.acm.org/10.1145/509705.509707}, + file = {henzinger98assumeguarantee.ps:/dsk/l1/misc/doc/modular/assume/henzinger98assumeguarantee.ps:PDF}, + issn = {0164-0925}, + publisher = {ACM Press} +} + +@ARTICLE{Holzmann97e, + author = {G.J.~Holzmann}, + title = {{The Model Checker Spin}}, + journal = {IEEE Transactions on Software Engineering}, + year = {1997}, + volume = {23}, + pages = {279--295}, + number = {5}, + month = {May}, + note = {Special issue on Formal Methods in Software Practice} +} + +@INPROCEEDINGS{hosabettu98decomposing, + author = {R.~Hosabettu and M.~Srivas and G.~Gopalakrishnan}, + title = {Decomposing the {P}roof of {C}orrectness of {P}ipelined {M}icroprocessors}, + booktitle = {Computer-Aided Verification, {CAV'98}}, + year = {1998}, + editor = {Alan J. Hu and Moshe Y. Vardi}, + volume = {1427}, + pages = {122--134}, + address = {Vancouver, Canada}, + publisher = {Springer-Verlag}, + url = {citeseer.ist.psu.edu/208243.html} +} + +@ARTICLE{huggins98spec, + author = {J.K.~Huggins and D.~Van Campenhout}, + title = {Specification and {V}erification of {P}ipelining in the {ARM2 RISC} + {M}icroprocessor}, + journal = {ACM Transactions on Design Automation of Electronic Systems}, + year = {1998}, + volume = {3}, + pages = {563--580}, + number = {4}, + address = {New York, NY, USA}, + doi = {http://doi.acm.org/10.1145/296333.296345}, + issn = {1084-4309}, + publisher = {ACM Press} +} + +@ARTICLE{HWA99, + author = {H.~Hulgaard and P.~F.~Williams and H.~R.~Andersen}, + title = {Equivalence Checking of Combinational Circuits using Boolean Expression + Diagrams}, + journal = {{IEEE} Transactions of Computer-Aided Design}, + year = {1999}, + volume = {18}, + pages = {903-917}, + number = {7}, + month = {July} +} + +@ARTICLE{DBLP:journals/tcad/JainKSC08, + author = {H.~Jain and D.~Kroening and N.~Sharygina and E.M.~Clarke}, + title = {Word-Level Predicate-Abstraction and Refinement Techniques for Verifying + RTL Verilog}, + journal = {IEEE Transaction on CAD of Integrated Circuits and Systems}, + year = {2008}, + volume = {27}, + pages = {366-379}, + number = {2}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://dx.doi.org/10.1109/TCAD.2007.907270}, + file = {:Cegar/WLPredicateAbstractionRefinment08.pdf:PDF}, + keywords = {Cegar, predicate abstraction, SAT} +} + +@INPROCEEDINGS{kroening07vcegar, + author = {H.~Jain and D.~Kroening and N.~Sharygina and E.~Clarke}, + title = {{{VCEGAR}: Verilog CounterExample Guided Abstraction Refinement}}, + booktitle = {T{ACAS}'07: {P}roceedings of the 13th {I}nternational {C}onference + on {T}ools and {A}lgorithms for the {C}onstruction and {A}nalysis + of {S}ystems}, + year = {2007}, + note = {Accepted paper}, + owner = {cecile}, + timestamp = {2007.02.07} +} + +@INPROCEEDINGS{JainNFS97survey, + author = {J.~Jain and A.~Narayan and M.~Fujita and A.L.~Sangiovanni-Vincentelli}, + title = {A Survey of Techniques for Formal Verification of Combinational Circuits.}, + booktitle = {ICCD}, + year = {1997}, + pages = {445-454}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + keywords = {survey, hadware, formal veriication} +} + +@ARTICLE{kalushy93knowledge, + author = {Yuri Kaluzhny and Alexei Yu. Muravitsky}, + title = {A knowledge representation based on the Belnap's four-valued logic}, + journal = {Journal of Applied Non-Classical Logics}, + year = {1993}, + volume = {3}, + pages = {189-203}, + number = {2}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + file = {kaluzhny93knowledge.pdf:/dsk/l1/misc/doc/logique/kaluzhny93knowledge.pdf:PDF}, + keywords = {CTL , abstraction , 3-valued , refinment loop}, + owner = {cecile}, + timestamp = {2006.04.03} +} + +@INPROCEEDINGS{park03satunbounded, + author = {H.-J.~Kang and I.-C.~Park}, + title = {SAT-based Unbounded Symbolic Model Checking}, + booktitle = {DAC'03: Proceedings of the 40th conference on Design automation}, + year = {2003}, + pages = {840--843}, + address = {New York,USA}, + publisher = {ACM}, + doi = {http://doi.acm.org/10.1145/775832.776043}, + file = {:BMC/kang03satunbounded.pdf:PDF;:BMC/Park05satUnbound.pdf:PDF}, + isbn = {1-58113-688-9}, + keywords = {SAT, all-sat}, + location = {Anaheim, CA, USA} +} + +@ARTICLE{Kern99survey, + author = {C.~Kern and M.R.~Greenstreet}, + title = {Formal {V}erification in {H}ardware {D}esign: a {S}urvey}, + journal = {ACM Transactions on Design Automation of Electronic Systems}, + year = {1999}, + volume = {4}, + pages = {123--193}, + number = {2}, + address = {New York, NY, USA}, + doi = {http://doi.acm.org/10.1145/307988.307989}, + issn = {1084-4309}, + keywords = {survey, hadware, formal veriication}, + publisher = {ACM Press} +} + +@BOOK{kleene52introduction, + title = {Introduction to Metamathematics}, + publisher = {North-Holland}, + year = {1952}, + author = {Kleene, S.}, + series = {Bibliotheca mathematica}, + owner = {cecile}, + timestamp = {2006.04.27} +} + +@INPROCEEDINGS{KLM93, + author = {T. Kolks and B. Lin and H. De Man}, + title = {Sizing and Verification of Communication Buffers for Communicating + Processes}, + booktitle = {Proc. of IEEE International Conference on Computer-Aided Design}, + year = {1993}, + volume = {1825}, + pages = {660--664}, + address = {Santa Clara, USA} +} + +@INPROCEEDINGS{kroening01automated, + author = {D.~Kroening and W.J.~Paul}, + title = {Automated {P}ipeline {D}esign}, + booktitle = {DAC '01: Proceedings of the 38th conference on Design Automation}, + year = {2001}, + pages = {810--815}, + publisher = {ACM Press}, + doi = {http://doi.acm.org/10.1145/378239.379071}, + isbn = {1-58113-297-2}, + location = {Las Vegas, Nevada, United States} +} + +@BOOK{kropf99introduction, + title = {Introduction to Formal Hardware Verification}, + publisher = {Springer Verlag}, + year = {1999}, + author = {T.~Kropf}, + address = {Secaucus, NJ, USA}, + isbn = {3540654453}, + keywords = {survey, hardware}, + owner = {cecile}, + timestamp = {2006.11.07} +} + +@ARTICLE{KupfermanG96branching, + author = {O.~Kupferman and O.~Grumberg}, + title = {Branching-Time Temporal Logic and Tree Automata.}, + journal = {Information and Computation}, + year = {1996}, + volume = {125}, + pages = {62-69}, + number = {1}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + file = {branchingand automata.ps:/dsk/l1/misc/doc/ctl_auto/branchingand automata.ps:PDF}, + keywords = {CTL, tree automata ,model checking, automata approach} +} + +@ARTICLE{KupfermanVW00automata, + author = {O.~Kupferman and M.Y.~Vardi and P.~Wolper}, + title = {An {A}utomata-{T}heoretic {A}pproach to {B}ranching-{T}ime {M}odel + {C}hecking.}, + journal = {Journal of the ACM}, + year = {2000}, + volume = {47}, + pages = {312-360}, + number = {2}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://doi.acm.org/10.1145/333979.333987}, + file = {an-automata-theoretic-approach.pdf:/dsk/l1/misc/doc/automate/an-automata-theoretic-approach.pdf:PDF}, + keywords = {tree automata, CTL, automata approach}, + owner = {cecile}, + timestamp = {2006.06.27} +} + +@INPROCEEDINGS{lamp83, + author = {L.~Lamport}, + title = {Information Processing}, + booktitle = {What good is in temporal logic}, + year = {1983}, + pages = {657--668}, + publisher = {Elsevier} +} + +@BOOK{Lano, + title = {The {B} {L}anguage and {M}ethod, {A} {G}uide to {P}ractical {F}ormal + {D}evelopment}, + publisher = {Springer-Verlag}, + year = {1996}, + author = {K.~Lano}, + series = {FACIT}, + address = {UK}, + keywords = {b method} +} + +@INPROCEEDINGS{693769, + author = {K.G~Larsen and B.~Steffen and C.~Weise}, + title = {A Constraint Oriented Proof Methodology Based on Modal Transition + Systems}, + booktitle = {TACAS '95: Proceedings of the First International Workshop on Tools + and Algorithms for Construction and Analysis of Systems}, + year = {1995}, + pages = {17--40}, + address = {London, UK}, + publisher = {Springer-Verlag}, + isbn = {3-540-60630-0} +} + +@ARTICLE{LiWS05PureSat, + author = {B.~Li and C.~Wang and F.~Somenzi}, + title = {Abstraction Refinement in Symbolic Model Checking using Satisfiability + as the Only Decision Procedure}, + journal = {STTT}, + year = {2005}, + volume = {7}, + pages = {143-155}, + number = {2}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://dx.doi.org/10.1007/s10009-004-0169-2}, + file = {:Cegar/Li04PureSatSTTT.pdf:PDF}, + keywords = {CEGAR, SAT} +} + +@INPROCEEDINGS{lin91implicit, + author = {B.~Lin and A.R.~Newton}, + title = {Implicit Manipulation of Equivalence Classes Using Binary Decision + Diagrams}, + booktitle = {ICCD '91: Proceedings of the 1991 IEEE International Conference on + Computer Design on VLSI in Computer \& Processors}, + year = {1991}, + pages = {81--85}, + address = {Washington, DC, USA}, + publisher = {IEEE Computer Society}, + isbn = {0-8186-2270-9} +} + +@ARTICLE{Loiseaux, + author = {C.~Loiseaux and S.~Graf and J.~Sifakis and A.~Bouajjani and S.~Bensalem}, + title = {Property {P}reserving {A}bstractions for the {V}erification of {C}oncurrent + {S}ystems}, + journal = {Formal Methods in System Design}, + year = {1995}, + volume = {6}, + pages = {11--44}, + number = {1}, + address = {Hingham, MA, USA}, + publisher = {Kluwer Academic Publisher} +} + +@PHDTHESIS{long93thesis, + author = {D.~E.~Long}, + title = {Model {C}hecking, {A}bstraction, and {C}ompositional {V}erification}, + school = {Carnegie Mellon University}, + year = {1993}, + file = {long93model.ps.gz:/dsk/l1/misc/doc/modular/model_checking/long93model.ps.gz:PDF}, + keywords = {abstraction, CTL, modular, simulation, model checking}, + owner = {cecile}, + timestamp = {2006.03.08} +} + +@INPROCEEDINGS{santo, + author = {S.~Malik and A.R.~Wang and R.K~Brayton and A.~Sangiovanni-Vincentelli}, + title = {Logic Verification using Binary Decision Diagrams in Logic Synthesis + Environment}, + booktitle = {Proceedings of the IEEE International Conference on Computer Aided + Design, ICCAD'88}, + year = {1988}, + pages = {6--9}, + month = {November}, + note = {Santa Clara CA, USA}, + abstract = { This paper proposes two heuristics for variable ordering based on + the topology of the circuit under study. \begin{enumerate} \item + One defines the level of a variable or a gate as follows: $level(root)=0$ + and $level(f)=max(level(g))+1$, where the $g$'s are the fathers of + $f$. The first heuristics consists in indexing the variables according + to the decreasing order of their levels. The justification is that + the influence of variables high in the circuit must be computed as + soon as possible. \item Same as the previous heuristics but respecting + modules. Modules are treated in the decreasing order of their depths. + The depth of a formula being the maximum depth of its variables. + \end{enumerate} Experimental results are reported, showing that the + second heuristics is very good (on the ICSAS'85 benchmark). Lu }, + keywords = {Variable ordering heuristics, Combinatorial Circuits} +} + +@INPROCEEDINGS{manolios00correctness, + author = {P.~Manolios}, + title = {Correctness of Pipelined Machines}, + booktitle = {FMCAD '00: Proceedings of the Third International Conference on Formal + Methods in Computer-Aided Design}, + year = {2000}, + pages = {161--178}, + publisher = {Springer-Verlag}, + url = {citeseer.ist.psu.edu/426677.html} +} + +@INPROCEEDINGS{manolios04web, + author = {P.~Manolios and S.K.~Srinivasan}, + title = {Automatic {V}erification of {S}afety and {L}iveness for {XS}cale-{L}ike + {P}rocessor {M}odels {U}sing {WEB} Refinements}, + booktitle = {DATE '04: Proceedings of the conference on Design, Automation and + Test in Europe}, + year = {2004}, + pages = {168-174}, + address = {Washington, DC, USA}, + publisher = {IEEE Computer Society}, + isbn = {0-7695-2085-5-1} +} + +@INPROCEEDINGS{Mariano2002formalization, + author = {G.~Mariano and J-L.~Boulanger and A. Aljer}, + title = {Formalization of {D}igital {C}ircuits {U}sing the {B} {M}ethod}, + booktitle = {Comp{R}ail {VIII}: 8th {I}nternational {C}onference on {C}omputer + {A}ided {D}esign, {M}anufacture and {O}peration in the {R}ailway + and other {A}dvanced {M}ass {T}ransit {S}ystems}, + year = {2002}, + address = {Lemnos, Greece}, + month = {12 - 14 } # jun, + keywords = {B method, formal development, software verification, safety-critical + applications, VHDL, BHDL, Hardware}, + url = {http://www.wessex.ac.uk/conferences/2002/cr02/} +} + +@INPROCEEDINGS{Silva00Sat, + author = {Marques-Silva, Jo\, {a}o P. and Sakallah, Karem A.}, + title = {Boolean satisfiability in electronic design automation}, + booktitle = {DAC '00: Proceedings of the 37th Annual Design Automation Conference}, + year = {2000}, + pages = {675--680}, + address = {New York, NY, USA}, + publisher = {ACM}, + doi = {http://doi.acm.org/10.1145/337292.337611}, + file = {:SAT/p675-marques-silva.pdf:PDF}, + isbn = {1-58113-187-9}, + keywords = {SAT, circuit}, + location = {Los Angeles, California, United States}, + owner = {cecile}, + timestamp = {2009.11.30} +} + +@ARTICLE{mcmillan00methodology, + author = {K.L. McMillan}, + title = {A {M}ethodology for {H}ardware {V}erification {U}sing {C}ompositional + {M}odel {C}hecking}, + journal = {Science of Computer Programming}, + year = {2000}, + volume = {37}, + pages = {279--309}, + number = {1--3}, + file = {mcmillan99methodology.pdf:/dsk/l1/misc/doc/modular/assume/mcmillan99methodology.pdf:PDF}, + keywords = {CTL, LTL, model checking, modular, composition, assume-guarantee}, + url = {citeseer.ist.psu.edu/mcmillan99methodology.html} +} + +@BOOK{mcmillanSMV, + title = {Symbolic Model Checking}, + publisher = {Kluwer Academics Publishers}, + year = {1993}, + author = {K.L.~McMillan} +} + +@PHDTHESIS{memmi:thesis, + author = {G.~Memmi}, + title = {M\'ethodes d'analyse des r\'eseaux de Petri, r\'eseaux \`a files + et application aux syst\`emes temps-r\'eel}, + school = {Universit\'e Paris-6}, + year = {1983} +} + +@BOOK{Mil89, + title = {Communication and {C}oncurrency}, + publisher = {Prentice Hall}, + year = {1989}, + author = {R.~Milner}, + series = {International series in computer science}, + address = {Upper Saddle River, USA}, + isbn = {0-13-115007-3} +} + +@INPROCEEDINGS{DBLP:conf/ijcai/Milner71, + author = {R.~Milner}, + title = {{An Algebraic Definition of Simulation Between + + Programs.}}, + booktitle = {IJCAI'71: Proceedings of the 2nd International Joint Conference on + Artificial Intelligence}, + year = {1971}, + pages = {481-489}, + adress = {London, UK}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + editors = {D. C. Cooper}, + keywords = {simulation, bisimulation} +} + +@INPROCEEDINGS{minato, + author = {S.~Minato and N.~Ishiura and S.~Yajima}, + title = {Shared Binary Decision Diagrams with Attributed Edges for Efficient + Boolean Function Manipulation}, + booktitle = {Proceedings of the 27th ACM/IEEE Design Automation Conference, DAC'90}, + year = {1990}, + editor = {L.J.M Claesen}, + pages = {52--57}, + month = {June}, + abstract = { This paper is the first one in which management of BDD nodes via + a hash table is proposed (and thus the reduction operation is suppressed). + Then, various labelling of edges are discussed: first, the flag $+/-$ + already proposed by Billon and Madre \cite{Bil87,MB88}. Second, another + flag so-called input inverter, is proposed. It transforms $ite(x,F,G)$ + into $ite(\neg x,F,G)=ite(x,G,F)$. Canonicity is maintained by keeping + only nodes such that $F
*Uses + standard 32-bit MIPS 32 as the primary teaching ISA.
*Presents + the assembler-to-HLL translations in both C and Java.
*Highlights + the latest developments in architecture in Real Stuff sections:

+ + Intel IA-32
+ Power PC 604
+ Googles PC cluster
+ Pentium + P4
+ SPEC CPU2000 benchmark suite for processors
+ SPEC Web99 + benchmark for web servers
+ EEMBC benchmark for embedded systems
+ + AMD Opteron memory hierarchy
+ AMD vs. 1A-64


New + support for distinct course goals

Many of the adopters + who have used our book throughout its two editions are refining their + courses with a greater hardware or software focus. We have provided + new material to support these course goals:

New material + to support a Hardware Focus

+Using logic design conventions
+Designing + with hardware description languages
+Advanced pipelining
+Designing + with FPGAs
+HDL simulators and tutorials
+Xilinx CAD tools

New + material to support a Software Focus

+How compilers Work
+How + to optimize compilers
+How to implement object oriented languages
+MIPS + simulator and tutorial
+History sections on programming languages, + compilers, operating systems and databases

Whats New + in the Third Edition

New pedagogical features

Understanding + Program Performance
-Analyzes key performance issues from + the programmers perspective

Check Yourself Questions +
-Helps students assess their understanding of key points of a + section

Computers In the Real World
-Illustrates + the diversity of applications of computing technology beyond traditional + desktop and servers

For More Practice
-Provides + students with additional problems they can tackle

In More + Depth
-Presents new information and challenging exercises + for the advanced student


New reference features

Highlighted + glossary terms and definitions appear on the book page, as bold-faced + entries in the index, and as a separate and searchable reference + on the CD.

A complete index of the material in the book and + on the CD appears in the printed index and the CD includes a fully + searchable version of the same index.

Historical Perspectives + and Further Readings have been updated and expanded to include the + history of software R\&D.

CD-Library provides materials collected + from the web which directly support the text.

On the CD

CD-Bars: + Full length sections that are introduced in the book and presented + on the CD

CD-Appendixes: The entire set of appendixes

CD-Library: + Materials collected from the web which directly support the text

CD-Exercises: + For More Practice provides exercises and solutions for self-study
In + More Depth presents new information and challenging exercises + for the advanced or curious student

Glossary: Terms that + are defined in the text are collected in this searchable reference

Further + Reading: References are organized by the chapter they support

Software: + HDL simulators, MIPS simulators, and FPGA design tools

Tutorials: + SPIM, Verilog, and VHDL

Additional Support: Processor Models, + Labs, Homeworks, Index covering the book and CD contents

Instructor + Support

+ Instructor Support is provided in a password-protected + site to adopters who request the password from our sales representative
+ + Solutions to all the exercises
+ Figures from the book in a number + of formats
+ Lecture slides prepared by the authors and other + instructors
+ Lecture notes

For instructor resources + click on the grey "companion site" button found on the right side + of this page.
This new edition represents a major revision. +
New to this edition:

* Entire Text has been updated to + reflect new technology
* 70% new exercises.
* Includes a CD + loaded with software, projects and exercises to support courses using + a number of tools
* A new interior design presents defined terms + in the margin for quick reference
* A new feature, Understanding + Program Performance focuses on performance from the programmers perspective +
* Two sets of exercises and solutions, For More Practice and + In More Depth, are included on the CD
* Check Yourself questions + help students check their understanding of major concepts
* Computers + In the Real World feature illustrates the diversity of uses for information + technology
*More detail below...}}, + citeulike-article-id = {808853}, + howpublished = {Paperback}, + isbn = {1558606041}, + keywords = {pipeline,processor}, + priority = {2}, + url = {http://www.amazon.co.uk/exec/obidos/ASIN/1558606041/citeulike-21} +} + +@PHDTHESIS{peng02thesis, + author = {H.~Peng}, + title = {Improving Compositional Verification through Environment Synthesis + and Syntactic Model Reduction}, + school = {Dept. of Electrical and Computer Engenering, Concordia University, + Montreal, Quebec, Canada}, + year = {2002}, + owner = {cecile}, + timestamp = {2007.01.09} +} + +@ARTICLE{peng03comparison, + author = {H.~Peng and S.~Tahar and F.~Khendek}, + title = {Comparison of {SPIN} and {VIS} for {P}rotocol {V}erification.}, + journal = {International Journal on Software Tools for Technology Transfer (STTT)}, + year = {2003}, + volume = {4}, + pages = {234-245}, + number = {2}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://dx.doi.org/10.1007/s100090200073}, + publisher = {Springer} +} + +@INPROCEEDINGS{omi95rsp, + author = {V. Pevtschin}, + title = {The {O}pen {M}icroprocessor {S}ystems {I}nitiative: {A} {S}trategy + {T}owards {I}ntegrated {S}ystem {D}esign}, + booktitle = {R{SP}'95: {P}roceddings of the 6th {IEEE} {I}nternational {W}orkshop + on {R}apid {S}ystem {P}rototyping}, + year = {1995}, + pages = {2--11}, + doi = {http://doi.ieeecomputersociety.org/10.1109/IWRSP.1995.518564}, + owner = {cecile}, + timestamp = {2007.02.19} +} + +@INPROCEEDINGS{plath99sfi, + author = {M.C.~Plath and M.D.~Ryan}, + title = {S{FI}: a {F}eature {I}ntegration {T}ool}, + booktitle = {Tool Support for System Specification, Development and Verification}, + year = {1999}, + editor = {R. Berghammer and Y. Lakhnech}, + series = {Advances in Computing Science}, + pages = {201--216}, + publisher = {Springer}, + file = {plath99sfi.ps:/dsk/l1/misc/doc/telecom/plath99sfi.ps:PDF}, + keywords = {feature} +} + +@ARTICLE{plath01feature, + author = {M.~Plath and M.~Ryan}, + title = {Feature {I}ntegration using a {F}eature {C}onstruct}, + journal = {Science of Computer Programming}, + year = {2001}, + volume = {41}, + pages = {53--84}, + number = {1}, + address = {Amsterdam, The Netherlands}, + doi = {http://dx.doi.org/10.1016/S0167-6423(00)00018-6}, + issn = {0167-6423}, + publisher = {Elsevier North-Holland, Inc.} +} + +@INPROCEEDINGS{plath98feature, + author = {M.C.~Plath and M.D.~Ryan}, + title = {A feature construct for Promela}, + booktitle = {SPIN'98: Proceedings of the 4th SPIN workshop}, + year = {1998}, + url = {citeseer.ist.psu.edu/plath98feature.html} +} + +@INPROCEEDINGS{Purandare09Strengthening, + author = {M. Purandare and T. Wahl and D. Kroening}, + title = {Strengthening Properties Using on Refinement}, + booktitle = {DATE '09: Proceedings of the conference on Design, Automation and + Test in Europe}, + year = {2009}, + pages = {1692-1697}, + file = {:Cegar/Strenghtening Properties Using AR 09.PDF:PDF}, + owner = {cecile}, + timestamp = {2009.04.30} +} + +@MASTERSTHESIS{fredHDR, + author = {P{\'e}trot, F.}, + title = {Int{\'e}gration des syst{\`e}mes mat{\'e}riel/logiciel}, + school = {Universit{\'e}e Pierre et Marie Curie}, + year = {2003}, + type = {Habilitation {\`a} Diriger des Recherches}, + owner = {cecile}, + timestamp = {2007.02.03} +} + +@BOOK{rasiowa78algebra, + title = {An Algebraic Approach to Non-Classicals Logis}, + year = {1978}, + editor = {Studies in Logics and the Foundations of Mathematics}, + author = {H.~Rasiowa}, + address = {Amsterdam}, + owner = {cecile}, + timestamp = {2006.05.15} +} + +@INPROCEEDINGS{sawada97trace, + author = {J.~Sawada and W.A.~Hunt}, + title = {Trace {T}able {B}ased {A}pproach for {P}ipeline {M}icroprocessor + {V}erification}, + booktitle = {CAV'97: Proceedings of the 9th International Conference on Computer + Aided Verification}, + year = {1997}, + pages = {364--375}, + address = {London, UK}, + publisher = {Springer-Verlag LNCS 1254}, + isbn = {3-540-63166-6} +} + +@INPROCEEDINGS{eveking06fdl, + author = {M.~Schickel and V.~Nimbler and M.~Braun and H.~Eveking}, + title = {On {C}onsistency and {C}ompletness of {P}roperty-{S}ets~: {Exploiting + the {P}roperty-{B}ased {D}esign {P}rocess}}, + booktitle = {FDL'06: Proceeding of Forum on specification and Design Languages}, + year = {2006}, + keywords = {Property-based design} +} + +@ARTICLE{DBLP:journals/fmsd/SegerB95, + author = {Carl-Johan H. Seger and Randal E. Bryant}, + title = {Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories}, + journal = {Formal Methods in System Design}, + year = {1995}, + volume = {6}, + pages = {147-189}, + number = {2}, + bibsource = {DBLP, http://dblp.uni-trier.de} +} + +@ARTICLE{Sharygin2012, + author = {Natasha Sharygina and Stefano Tonetta and Aliaksei Tsitovich}, + title = {An abstraction refinement approach combining precise and approximated + techniques}, + journal = {International Journal on Software Tools for Technology Transfer (STTT)}, + year = {2012}, + volume = {14}, + pages = {1-14}, + file = {:/users/outil/verif/biblio/Cegar/A_framework_forCVofMVviaAR-ATVA09.pdf:PDF}, + keywords = {Predicate abstraction, Precise abstraction, Approximated abstraction, + CEGAR}, + publisher = {Springer}, + url = {http://dx.doi.org/10.1007/s10009-011-0185-y} +} + +@INPROCEEDINGS{magnier-sherman:factotum, + author = {D.J Sherman and N. Magnier}, + title = {Factotum: Automatic and Systematic Sharing Support for Systems Analyzers}, + booktitle = {Tools and Algorithms for the Construction and Analysis of Systems + (TACAS'98)}, + year = {1982}, + editor = {Bernhard Steffen}, + address = {Lisbon, Portugal}, + month = {March-April}, + publisher = {Springer-Verlag LNCS 1384} +} + +@INPROCEEDINGS{shoham06precision, + author = {S.~Shoham and O.~Grumberg}, + title = {3-Valued Abstraction: More Precision at Less Cost}, + booktitle = {LICS '06: proceedings of the 21st Annual IEEE Symposium on Logic + in Computer Science}, + year = {2006}, + pages = {399--410}, + address = {Washington, DC, USA}, + publisher = {IEEE Computer Society}, + doi = {http://dx.doi.org/10.1109/LICS.2006.5}, + owner = {cecile}, + timestamp = {2007.01.14} +} + +@ARTICLE{DBLP:journals/tcad/SmithVAV05, + author = {Alexander Smith and Andreas G. Veneris and Moayad Fahim Ali and Anastasios + Viglas}, + title = {Fault diagnosis and logic debugging using Boolean satisfiability}, + journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, + year = {2005}, + volume = {24}, + pages = {1606-1621}, + number = {10}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + ee = {http://dx.doi.org/10.1109/TCAD.2005.852031} +} + +@INCOLLECTION{IMM2001-0855, + author = {J. Spars{\o}}, + title = {Asynchronous {C}ircuit {D}esign - {A} {T}utorial}, + booktitle = {Chapters {1-}8 in {''}Principles of asynchronous circuit design - + A systems Perspective''}, + publisher = {Kluwer Academic Publishers}, + year = {2001}, + pages = {1-152}, + address = {London}, + month = {dec}, + isbn_issn = {0-7923-7613-7}, + url = {http://www2.imm.dtu.dk/pubdb/p.php?855} +} + +@MANUAL{AtelierB, + title = {{A}telier {B}, {M}anuel {U}tilisateur}, + author = {{{STERIA} Technologie de l'information}}, + address = {Aix-en-Provence, France}, + year = {1998}, + keywords = {theorem prover, b}, + series = {version 3.5} +} + +@PHDTHESIS{turk05thesis, + author = {T\"urk, T.}, + title = {A Hierarchy for Accellera's Property Specification Language}, + school = {University of Kaiserslautern}, + year = {2005}, + comment = {Je l'ai en papier}, + keywords = {automata approach, PSL}, + owner = {cecile}, + timestamp = {2006.02.13}, + url = {http://thomas-tuerk.de/dokumente/Diplomarbeit.pdf} +} + +@MANUAL{vismanual, + title = {VIS User's Manual}, + author = {{The VIS Group}}, + year = {1996}, + file = {vis_user.ps:/dsk/l1/misc/doc/checker/vis_user.ps:PDF}, + key = VIS, + keywords = {model checker}, + owner = {cecile}, + timestamp = {2006.02.09} +} + +@MISC{m106archi, + author = {{Universit\'e Pierre et Marie Curie (UPMC), Paris 6}}, + title = {{{UE} : Achitecture des syst\`emes int\'egr\'es, {M1}}}, + note = {\url{http://www-master.ufr-info-p6.jussieu.fr/ue/archi/}}, + owner = {cecile}, + timestamp = {2006.10.05} +} + +@ARTICLE{fms, + author = {D.M.~Upton}, + title = {A {F}lexible {S}tructure for {C}omputer-{C}ontrolled {M}anufacturing + {S}ystems}, + journal = {Manufacturing Review}, + year = {1992}, + volume = {5}, + pages = {58--74}, + number = {1}, + keywords = {FMS}, + owner = {cecile}, + timestamp = {2007.01.22} +} + +@INPROCEEDINGS{Valk93, + author = {R. Valk}, + title = {Bridging the Gap between Place- and Floyd-Invariants with Applications + to Preemptive Scheduling}, + booktitle = {Proc. of ICATPN'93}, + year = {1993}, + volume = {691}, + series = {Lecture Notes in Computer Science}, + pages = {432--452}, + publisher = {Springer Verlag} +} + +@INPROCEEDINGS{xie03verified, + author = {F.~Xie and J.C.~Browne}, + title = {Verified {S}ystems by {C}omposition from {V}erified {C}omponents}, + booktitle = {E{SEC}/{FSE} 2003 : {P}roceedings of the 11th {ACM} {SIGSOFT} {S}ymposium + on {F}oundations of {S}oftware {E}ngineering 2003 held jointly with + 9th {E}uropean {S}oftware {E}ngineering {C}onference}, + year = {2003}, + pages = {277--286}, + address = {Helsinki, Finland}, + publisher = {ACM Press}, + comment = {: Proceedings of the 9th European software engineering conference + held jointly with 11th ACM SIGSOFT international symposium on Foundations + of software engineering}, + doi = {http://doi.acm.org/10.1145/940071.940109}, + isbn = {1-58113-743-5}, + location = {Helsinki, Finland} +} + +@PHDTHESIS{Yadgar10thesis, + author = {Avi Yadgar}, + title = {New Approaches to Model Checking and to 3-Valued Abstraction and + Refinement}, + school = {Technion - Israel Institute of Technology}, + year = {2010}, + file = {:/users/outil/verif/biblio/Cegar/AviYadgarPhDThesisReport.pdf:PDF}, + keywords = {Cegar, BMC, 3-valued, Abstraction}, + owner = {verif}, + timestamp = {2010.06.15} +} + +@TECHREPORT{cegarhwcasestudy07, + author = {Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah}, + title = {CEGAR-Based Formal Hardware Verification: A Case Study}, + institution = {Department of Electrical Engineering and Computer Science + + University of Michigan}, + year = {2007}, + file = {:Cegar/CEGARHWVerifCaseStudy07.pdf:PDF}, + keywords = {CEGAR,hardware}, + owner = {cecile}, + timestamp = {2010.06.10} +} + +@ARTICLE{Zaki08analogformalsurvey, + author = {M.H~Zaki and S.~Tahar and G.~Bois}, + title = {Formal verification of analog and mixed signal designs: A survey}, + journal = {Microelectronics Journal}, + year = {2008}, + volume = {39}, + pages = {1395--1404}, + number = {12}, + address = {Amsterdam, The Netherlands, The Netherlands}, + doi = {http://dx.doi.org/10.1016/j.mejo.2008.05.013}, + file = {:Analog/surveyZaki08.pdf:PDF}, + issn = {0026-2692}, + publisher = {Elsevier Science Publishers B. V.} +} + +@PROCEEDINGS{DBLP:conf/fmcad/2002, + title = {Formal Methods in Computer-Aided Design, 4th International Conference, + FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings}, + year = {2002}, + editor = {Mark Aagaard and John W. O'Leary}, + volume = {2517}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {FMCAD}, + isbn = {3-540-00116-6} +} + +@PROCEEDINGS{DBLP:conf/sefm/2005, + title = {Third IEEE International Conference on Software Engineering and Formal + Methods (SEFM 2005), 7-9 September 2005, Koblenz, Germany}, + year = {2005}, + editor = {Bernhard K. Aichernig and Bernhard Beckert}, + publisher = {IEEE Computer Society}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {SEFM}, + isbn = {0-7695-2435-4} +} + +@PROCEEDINGS{DBLP:conf/cav/2004, + title = {Computer Aided Verification, 16th International Conference, CAV 2004, + Boston, MA, USA, July 13-17, 2004, Proceedings}, + year = {2004}, + editor = {Rajeev Alur and Doron Peled}, + volume = {3114}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {CAV}, + isbn = {3-540-22342-8} +} + +@PROCEEDINGS{DBLP:conf/cav/2006, + title = {CAV'06: Proceedings of 18th International Conference of Computer + Aided Verification}, + year = {2006}, + editor = {Thomas Ball and Robert B. Jones}, + volume = {4144}, + series = {Lecture Notes in Computer Science}, + address = {Seattle, WA, USA}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {CAV}, + isbn = {3-540-37406-X} +} + +@PROCEEDINGS{DBLP:conf/sfm/2006, + title = {Formal Methods for Hardware Verification, 6th International School + on Formal Methods for the Design of Computer, Communication, and + Software Systems, SFM 2006, Bertinoro, Italy, May 22-27, 2006, Advanced + Lectures}, + year = {2006}, + editor = {Marco Bernardo and Alessandro Cimatti}, + volume = {3965}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {SFM}, + isbn = {978-3-540-34304-2} +} + +@PROCEEDINGS{DBLP:conf/cav/2001, + title = {Computer Aided Verification, 13th International Conference, CAV 2001, + Paris, France, July 18-22, 2001, Proceedings}, + year = {2001}, + editor = {G{\'e}rard Berry and Hubert Comon and Alain Finkel}, + volume = {2102}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {CAV}, + isbn = {3-540-42345-1} +} + +@PROCEEDINGS{DBLP:conf/hvc/2006, + title = {Hardware and Software, Verification and Testing, Second International + Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, + 2006. Revised Selected Papers}, + year = {2007}, + editor = {Eyal Bin and Avi Ziv and Shmuel Ur}, + volume = {4383}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {Haifa Verification Conference}, + isbn = {978-3-540-70888-9} +} + +@PROCEEDINGS{DBLP:conf/fmco/2005, + title = {Formal Methods for Components and Objects, 4th International Symposium, + FMCO 2005, Amsterdam, The Netherlands, November 1-4, 2005, Revised + Lectures}, + year = {2006}, + editor = {Frank S. de Boer and Marcello M. Bonsangue and Susanne Graf and Willem + P. de Roever}, + volume = {4111}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {FMCO}, + isbn = {3-540-36749-7} +} + +@PROCEEDINGS{DBLP:conf/charme/2005, + title = {Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 + Advanced Research Working Conference, CHARME 2005, Saarbr{\"u}cken, + Germany, October 3-6, 2005, Proceedings}, + year = {2005}, + editor = {Dominique Borrione and Wolfgang J. Paul}, + volume = {3725}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {CHARME}, + isbn = {3-540-29105-9}, + owner = {cecile}, + timestamp = {2006.06.27} +} + +@PROCEEDINGS{DBLP:conf/cav/2002, + title = {Computer Aided Verification, 14th International Conference, CAV 2002,Copenhagen, + Denmark, July 27-31, 2002, Proceedings}, + year = {2002}, + editor = {Ed Brinksma and Kim Guldstrand Larsen}, + volume = {2404}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {CAV}, + isbn = {3-540-43997-8} +} + +@PROCEEDINGS{DBLP:conf/fase/2005, + title = {Fundamental Approaches to Software Engineering, 8th International + Conference, FASE 2005, Held as Part of the Joint European Conferences + on Theory and Practice of Software, ETAPS 2005, Edinburgh, UK, April + 4-8, 2005, Proceedings}, + year = {2005}, + editor = {Maura Cerioli}, + volume = {3442}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {FASE}, + isbn = {3-540-25420-X} +} + +@PROCEEDINGS{DBLP:conf/lpar/2008, + title = {Logic for Programming, Artificial Intelligence, and Reasoning, 15th + International Conference, LPAR 2008, Doha, Qatar, November 22-27, + 2008. Proceedings}, + year = {2008}, + editor = {Iliano Cervesato and Helmut Veith and Andrei Voronkov}, + volume = {5330}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {LPAR}, + isbn = {978-3-540-89438-4} +} + +@PROCEEDINGS{DBLP:conf/vmcai/2005, + title = {Verification, Model Checking, and Abstract Interpretation, 6th International + Conference, VMCAI 2005, Paris, France, January 17-19, 2005, Proceedings}, + year = {2005}, + editor = {Radhia Cousot}, + volume = {3385}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {VMCAI}, + isbn = {3-540-24297-X} +} + +@PROCEEDINGS{DBLP:conf/tcs/1981, + title = {Theoretical Computer Science, 5th GI-Conference, Karlsruhe, Germany, + March 23-25, 1981, Proceedings}, + year = {1981}, + editor = {Peter Deussen}, + volume = {104}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {Theoretical Computer Science}, + isbn = {3-540-10576-X} +} + +@PROCEEDINGS{DBLP:conf/vmcai/2006, + title = {Verification, Model Checking, and Abstract Interpretation, 7th International + Conference, VMCAI 2006, Charleston, SC, USA, January 8-10, 2006, + Proceedings}, + year = {2006}, + editor = {E. Allen Emerson and Kedar S. Namjoshi}, + volume = {3855}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {VMCAI}, + isbn = {3-540-31139-4} +} + +@PROCEEDINGS{DBLP:conf/cav/2000, + title = {Computer Aided Verification, 12th International Conference, CAV 2000, + Chicago, IL, USA, July 15-19, 2000, Proceedings}, + year = {2000}, + editor = {E.A.~Emerson and A.P.~Sistla}, + volume = {1855}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {CAV}, + isbn = {3-540-67770-4}, + owner = {cecile}, + timestamp = {2006.02.13} +} + +@PROCEEDINGS{DBLP:conf/apn/2002, + title = {Applications and Theory of Petri Nets 2002, 23rd International Conference, + ICATPN 2002, Adelaide, Australia, June 24-30, 2002, Proceedings}, + year = {2002}, + editor = {Javier Esparza and Charles Lakos}, + volume = {2360}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {ICATPN}, + isbn = {3-540-43787-8} +} + +@PROCEEDINGS{DBLP:conf/date/2006p, + title = {Proceedings of the Conference on Design, Automation and Test in Europe, + DATE 2006, Munich, Germany, March 6-10, 2006}, + year = {2006}, + editor = {Georges G. E. Gielen}, + publisher = {European Design and Automation Association, Leuven, Belgium}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {DATE}, + isbn = {3-9810801-0-6} +} + +@PROCEEDINGS{DBLP:conf/sat/2003, + title = {Theory and Applications of Satisfiability Testing, 6th International + Conference, SAT 2003. Santa Margherita Ligure, Italy, May 5-8, 2003 + Selected Revised Papers}, + year = {2004}, + editor = {Enrico Giunchiglia and Armando Tacchella}, + volume = {2919}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {SAT}, + isbn = {3-540-20851-8} +} + +@PROCEEDINGS{DBLP:conf/frocos/2005, + title = {Frontiers of Combining Systems, 5th International Workshop, FroCoS + 2005, Vienna, Austria, September 19-21, 2005, Proceedings}, + year = {2005}, + editor = {Bernhard Gramlich}, + volume = {3717}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {FroCoS}, + isbn = {3-540-29051-6} +} + +@PROCEEDINGS{DBLP:conf/cav/1997, + title = {Computer Aided Verification, 9th International Conference, CAV '97, + Haifa, Israel, June 22-25, 1997, Proceedings}, + year = {1997}, + editor = {Orna Grumberg}, + volume = {1254}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {CAV}, + isbn = {3-540-63166-6} +} + +@PROCEEDINGS{DBLP:conf/cav/1999, + title = {Computer Aided Verification, 11th International Conference, CAV '99, + Trento, Italy, July 6-10, 1999, Proceedings}, + year = {1999}, + editor = {Nicolas Halbwachs and Doron Peled}, + volume = {1633}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {CAV}, + isbn = {3-540-66202-2}, + owner = {cecile}, + timestamp = {2006.04.25} +} + +@PROCEEDINGS{DBLP:conf/tacas/2005, + title = {Tools and Algorithms for the Construction and Analysis of Systems, + 11th International Conference, TACAS 2005, Held as Part of the Joint + European Conferences on Theory and Practice of Software, ETAPS 2005, + Edinburgh, UK, April 4-8, 2005, Proceedings}, + year = {2005}, + editor = {Nicolas Halbwachs and Lenore D. Zuck}, + volume = {3440}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {TACAS}, + isbn = {3-540-25333-5} +} + +@PROCEEDINGS{DBLP:conf/iccad/2006, + title = {2006 International Conference on Computer-Aided Design (ICCAD'06), + November 5-9, 2006, San Jose, CA, USA}, + year = {2006}, + editor = {Soha Hassoun}, + publisher = {ACM}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {ICCAD}, + isbn = {1-59593-389-1} +} + +@PROCEEDINGS{DBLP:conf/tacas/2006, + title = {Tools and Algorithms for the Construction and Analysis of Systems, + 12th International Conference, TACAS 2006 Held as Part of the Joint + European Conferences on Theory and Practice of Software, ETAPS 2006, + Vienna, Austria, March 25 - April 2, 2006, Proceedings}, + year = {2006}, + editor = {Holger Hermanns and Jens Palsberg}, + volume = {3920}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {TACAS}, + isbn = {3-540-33056-9} +} + +@PROCEEDINGS{DBLP:conf/cav/1998, + title = {Computer Aided Verification, 10th International Conference, CAV '98, + Vancouver, BC, Canada, June 28 - July 2, 1998, Proceedings}, + year = {1998}, + editor = {Alan J. Hu and Moshe Y. Vardi}, + volume = {1427}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {CAV}, + isbn = {3-540-64608-6} +} + +@PROCEEDINGS{DBLP:conf/tacas/2004, + title = {Tools and Algorithms for the Construction and Analysis of Systems, + 10th International Conference, TACAS 2004, Held as Part of the Joint + European Conferences on Theory and Practice of Software, ETAPS 2004, + Barcelona, Spain, March 29 - April 2, 2004, Proceedings}, + year = {2004}, + editor = {Kurt Jensen and Andreas Podelski}, + volume = {2988}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {TACAS}, + isbn = {3-540-21299-X} +} + +@PROCEEDINGS{DBLP:conf/vmcai/2011, + title = {Verification, Model Checking, and Abstract Interpretation - 12th + International Conference, VMCAI 2011, Austin, TX, USA, January 23-25, + 2011. Proceedings}, + year = {2011}, + editor = {Ranjit Jhala and David A. Schmidt}, + volume = {6538}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {VMCAI}, + ee = {http://dx.doi.org/10.1007/978-3-642-18275-4}, + isbn = {978-3-642-18274-7} +} + +@PROCEEDINGS{DBLP:conf/cav/2003, + title = {Computer Aided Verification, 15th International Conference, CAV 2003, + Boulder, CO, USA, July 8-12, 2003, Proceedings}, + year = {2003}, + editor = {Warren A. Hunt Jr. and Fabio Somenzi}, + volume = {2725}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {CAV}, + isbn = {3-540-40524-0} +} + +@PROCEEDINGS{DBLP:conf/dac/2005, + title = {Proceedings of the 42nd Design Automation Conference, DAC 2005, San + Diego, CA, USA, June 13-17, 2005}, + year = {2005}, + editor = {William H. Joyner Jr. and Grant Martin and Andrew B. Kahng}, + publisher = {ACM}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {DAC}, + isbn = {1-59593-058-2} +} + +@PROCEEDINGS{DBLP:conf/lop/1981, + title = {Logic of Programs, Workshop}, + year = {1982}, + editor = {Dexter Kozen}, + volume = {131}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {Logic of Programs}, + isbn = {3-540-11212-X} +} + +@PROCEEDINGS{DBLP:conf/dac/2004, + title = {Proceedings of the 41th Design Automation Conference, DAC 2004, San + Diego, CA, USA, June 7-11, 2004}, + year = {2004}, + editor = {Sharad Malik and Limor Fix and Andrew B. Kahng}, + publisher = {ACM}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {DAC}, + isbn = {1-58113-828-8} +} + +@PROCEEDINGS{DBLP:conf/birthday/2010pnueli, + title = {Time for Verification, Essays in Memory of Amir Pnueli}, + year = {2010}, + editor = {Zohar Manna and Doron Peled}, + volume = {6200}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {Essays in Memory of Amir Pnueli}, + ee = {http://dx.doi.org/10.1007/978-3-642-13754-9}, + isbn = {978-3-642-13753-2} +} + +@PROCEEDINGS{DBLP:conf/tacas/2001, + title = {Tools and Algorithms for the Construction and Analysis of Systems, + 7th International Conference, TACAS 2001 Held as Part of the Joint + European Conferences on Theory and Practice of Software, ETAPS 2001 + Genova, Italy, April 2-6, 2001, Proceedings}, + year = {2001}, + editor = {Tiziana Margaria and Wang Yi}, + volume = {2031}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {TACAS}, + isbn = {3-540-41865-2} +} + +@PROCEEDINGS{DBLP:conf/sbmf/2009, + title = {Formal Methods: Foundations and Applications, 12th Brazilian Symposium + on Formal Methods, SBMF 2009, Gramado, Brazil, August 19-21, 2009, + Revised Selected Papers}, + year = {2009}, + editor = {Marcel Vinicius Medeiros Oliveira and Jim Woodcock}, + volume = {5902}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {SBMF}, + ee = {http://dx.doi.org/10.1007/978-3-642-10452-7}, + isbn = {978-3-642-10451-0} +} + +@PROCEEDINGS{DBLP:conf/concur/2000, + title = {CONCUR 2000 - Concurrency Theory, 11th International Conference, + University Park, PA, USA, August 22-25, 2000, Proceedings}, + year = {2000}, + editor = {Catuscia Palamidessi}, + volume = {1877}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {CONCUR}, + isbn = {3-540-67897-2} +} + +@PROCEEDINGS{DBLP:conf/tacas/2008, + title = {Tools and Algorithms for the Construction and Analysis of Systems, + 14th International Conference, TACAS 2008, Held as Part of the Joint + European Conferences on Theory and Practice of Software, ETAPS 2008, + Budapest, Hungary, March 29-April 6, 2008. Proceedings}, + year = {2008}, + editor = {C. R. Ramakrishnan and Jakob Rehof}, + volume = {4963}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {TACAS}, + isbn = {978-3-540-78799-0} +} + +@PROCEEDINGS{DBLP:conf/compos/1997, + title = {Compositionality: The Significant Difference, International Symposium, + COMPOS'97, Bad Malente, Germany, September 8-12, 1997. Revised Lectures}, + year = {1998}, + editor = {Willem P. de Roever and Hans Langmaack and Amir Pnueli}, + volume = {1536}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {COMPOS}, + isbn = {3-540-65493-3} +} + +@PROCEEDINGS{DBLP:conf/dac/2006, + title = {Proceedings of the 43rd Design Automation Conference, DAC 2006, San + Francisco, CA, USA, July 24-28, 2006}, + year = {2006}, + editor = {Ellen Sentovich}, + publisher = {ACM}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {DAC}, + isbn = {1-59593-381-6} +} + +@PROCEEDINGS{DBLP:conf/tacas/1998, + title = {Tools and Algorithms for Construction and Analysis of Systems, 4th + International Conference, TACAS '98, Held as Part of the European + Joint Conferences on the Theory and Practice of Software, ETAPS'98, + Lisbon, Portugal, March 28 - April 4, 1998, Proceedings}, + year = {1998}, + editor = {Bernhard Steffen}, + volume = {1384}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {TACAS}, + isbn = {3-540-64356-7} +} + +@PROCEEDINGS{DBLP:conf/forte/2005, + title = {Formal Techniques for Networked and Distributed Systems - FORTE 2005, + 25th IFIP WG 6.1 International Conference, Taipei, Taiwan, October + 2-5, 2005, Proceedings}, + year = {2005}, + editor = {Farn Wang}, + volume = {3731}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {FORTE}, + isbn = {3-540-29189-X} +} + +@PROCEEDINGS{DBLP:conf/fm/1999-1, + title = {FM'99 - Formal Methods, World Congress on Formal Methods in the Development + of Computing Systems, Toulouse, France, September 20-24, 1999, Proceedings, + Volume I}, + year = {1999}, + editor = {Jeannette M. Wing and Jim Woodcock and Jim Davies}, + volume = {1708}, + series = {Lecture Notes in Computer Science}, + publisher = {Springer}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {World Congress on Formal Methods}, + isbn = {3-540-66587-0} +} + +@MISC{alliance, + title = {Alliance, a free {VLSI} cad system}, + note = {\\\url{http://www-asim.lip6.fr/recherche/alliance/}}, + owner = {cecile}, + timestamp = {2007.02.01} +} + +@MISC{onespin, + title = {OneSpin Solutions}, + note = {\url{http://www.onespin-solutions.com/}}, + key = OneS, + owner = {cecile}, + timestamp = {2007.03.07} +} + +@MISC{prosyd, + title = {The Prosyd Project on Property-Based System Design}, + note = {{\url{http://www.prosyd.org/}}}, + owner = {cecile}, + timestamp = {2007.02.07} +} + +@MISC{soclib, + title = {The {S}o{CL}ib {P}roject}, + note = {\url{http://soclib.lip6.fr/}}, + key = SoC, + owner = {cecile}, + timestamp = {2006.09.07}, + url = {http://soclib.lip6.fr/} +} + +@MISC{texas97bench, + title = {Texas-97 {V}erification {B}enchmarks}, + note = {\\\url{http://www.cad.eecs.berkeley.edu/Respep/Research/vis/texas-97/}}, + key = TEXAS, + keywords = {protocol, PIbus}, + owner = {cecile}, + timestamp = {2006.11.30} +} + +@MISC{vsia, + title = {{VSI A}lliance}, + note = {\url{http://www.vsi.org/}}, + key = VSI, + owner = {cecile}, + timestamp = {2006.09.13} +} + +@PROCEEDINGS{DBLP:conf/date/2009, + title = {Design, Automation and Test in Europe, DATE 2009, Nice, France, April + 20-24, 2009}, + year = {2009}, + publisher = {IEEE}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {DATE} +} + +@PROCEEDINGS{DBLP:conf/fmcad/2009, + title = {Proceedings of 9th International Conference on Formal Methods in + Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, + USA}, + year = {2009}, + publisher = {IEEE}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {FMCAD}, + isbn = {978-1-4244-4966-8} +} + +@PROCEEDINGS{DBLP:conf/lics/2004, + title = {19th IEEE Symposium on Logic in Computer Science (LICS 2004), 14-17 + July 2004, Turku, Finland, Proceedings}, + year = {2004}, + publisher = {IEEE Computer Society}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {LICS}, + isbn = {0-7695-2192-4} +} + +@PROCEEDINGS{DBLP:conf/sat/2004, + title = {SAT 2004 - The Seventh International Conference on Theory and Applications + of Satisfiability Testing, 10-13 May 2004, Vancouver, BC, Canada, + Online Proceedings}, + year = {2004}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {SAT}, + owner = {cecile}, + timestamp = {2009.01.27} +} + +@PROCEEDINGS{DBLP:conf/date/2003, + title = {2003 Design, Automation and Test in Europe Conference and Exposition + (DATE 2003), 3-7 March 2003, Munich, Germany}, + year = {2003}, + publisher = {IEEE Computer Society}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {DATE}, + isbn = {0-7695-1870-2} +} + +@PROCEEDINGS{DBLP:conf/icse/2003, + title = {Proceedings of the 25th International Conference on Software Engineering, + May 3-10, 2003, Portland, Oregon, USA}, + year = {2003}, + publisher = {IEEE Computer Society}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {ICSE} +} + +@PROCEEDINGS{DBLP:conf/time/2003, + title = {10th International Symposium on Temporal Representation and Reasoning + / 4th International Conference on Temporal Logic (TIME-ICTL 2003), + 8-10 July 2003, Cairns, Queensland, Australia}, + year = {2003}, + publisher = {IEEE Computer Society}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {TIME}, + isbn = {0-7695-1912-1} +} + +@PROCEEDINGS{DBLP:conf/iccd/2002, + title = {20th International Conference on Computer Design (ICCD 2002), VLSI + in Computers and Processors, 16-18 September 2002, Freiburg, Germany, + Proceedings}, + year = {2002}, + publisher = {IEEE Computer Society}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {ICCD}, + isbn = {0-7695-1700-5}, + keywords = {3-valued, logic, model checking, Kripke structure} +} + +@PROCEEDINGS{DBLP:conf/dac/2001, + title = {Proceedings of the 38th Design Automation Conference, DAC 2001, Las + Vegas, NV, USA, June 18-22, 2001}, + year = {2001}, + publisher = {ACM}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {DAC}, + isbn = {1-58113-297-2} +} + +@PROCEEDINGS{DBLP:conf/icse/2001, + title = {Proceedings of the 23rd International Conference on Software Engineering, + ICSE 2001, 12-19 May 2001, Toronto, Ontario, Canada}, + year = {2001}, + publisher = {IEEE Computer Society}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {ICSE}, + isbn = {0-7695-1050-7} +} + +@MANUAL{amba, + title = {AMBA Specification}, + organization = {ARM limited}, + edition = {2.0}, + year = {1999}, + note = {ARM Limited \copyright. All right reserved}, + file = {IHI0011A_AMBA_SPEC.pdf:/dsk/l1/misc/doc/amba/IHI0011A_AMBA_SPEC.pdf:PDF}, + key = AMBA, + owner = {cecile}, + timestamp = {2006.09.07} +} + +@MANUAL{formalcheck, + title = {Formal Verification Using Affirma {FormalCheck}}, + organization = {Cadence}, + month = {October}, + year = {1999} +} + +@PROCEEDINGS{DBLP:conf/lics/LICS4, + title = {Proceedings, Fourth Annual Symposium on Logic in Computer Science, + 5-8 June, 1989, Asilomar Conference Center, Pacific Grove, California, + USA}, + year = {1989}, + publisher = {IEEE Computer Society}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {LICS} +} + +@PROCEEDINGS{DBLP:conf/lics/LICS3, + title = {Proceedings, Third Annual Symposium on Logic in Computer Science}, + year = {1988}, + address = {Edinburgh, Scotland, UK}, + publisher = {IEEE Computer Society}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {LICS} +} + +@PROCEEDINGS{DBLP:conf/stoc/STOC14, + title = {Proceedings of the Fourteenth Annual ACM Symposium on Theory of Computing, + 5-7 May 1982, San Francisco, California, USA}, + year = {1982}, + publisher = {ACM}, + bibsource = {DBLP, http://dblp.uni-trier.de}, + booktitle = {STOC} +} + Index: /biblio/verif_biblio.html =================================================================== --- /biblio/verif_biblio.html (revision 45) +++ /biblio/verif_biblio.html (revision 45) @@ -0,0 +1,6903 @@ + + + +JabRef References output + + + + + + + + +
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    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    AuthorTitleYearJournal/ProceedingsReftypeDOI/URLPDF
    group, M.C.S. RuleBase Parallel Edition,User's Guide

    [BibTeX]

    		2005 manual  
    BibTeX: +
    +@manual{rulebase06userguide,
+  author = {Model Checking Systems group},
+  title = {RuleBase Parallel Edition,User's Guide},
+  year = {2005},
+  note = {verion 1.26}
+}
+
    group, T. VIS. Rajeev Alur and Thomas A. Henzinger (Ed.)VIS : A System for Verification and Synthesis

    [Abstract] [BibTeX]

    		1996
    Vol. 1102CAV'96: Proceedings of the 8th International Conference on Computer Aided Verification, pp. 428-432     		inproceedingsURL  
    Abstract: Manual abstraction can be performed by giving a file containing the names of variables to abstract. For each variable appearing in the file, a new primary input node is created to drive all the nodes that were previously driven by the variable. Abstracting a net effectively allows it to take any value in its range, at every clock cycle. Fair CTL model checking and language emptiness check VIS performs fair CTL model checking under Buchi fairness constraints. In addition, VIS can perform ...
    BibTeX: +
    +@inproceedings{Vis,
+  author = {The VIS group},
+  title = {VIS : A System for Verification and Synthesis},
+  booktitle = {CAV'96: Proceedings of the 8th International Conference on Computer Aided Verification},
+  publisher = {Springer-Verlag},
+  year = {1996},
+  volume = {1102},
+  pages = {428--432},
+  url = {citeseer.ist.psu.edu/brayton96vis.html}
+}
+
    0002, A.C. & Namjoshi, K.S. Local proofs for global safety properties

    [BibTeX]

    		2009Formal Methods in System Design
    Vol. 34(2), pp. 104-125     		article  
    BibTeX: +
    +@article{DBLP:journals/fmsd/CohenN09,
+  author = {Ariel Cohen 0002 and Kedar S. Namjoshi},
+  title = {Local proofs for global safety properties},
+  journal = {Formal Methods in System Design},
+  year = {2009},
+  volume = {34},
+  number = {2},
+  pages = {104-125}
+}
+
    Aagaard, M. Daniel Geist and Enrico Tronci (Ed.)A Hazards-Based Correctness Statement for Pipelined Circuits.

    [BibTeX]

    		2003
    Vol. 2860Proceedings of the 12th IFIP WG 10.5 Advanced Research Working Conference, pp. 66-80     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{aagaard03hazards,
+  author = {M.~Aagaard},
+  title = {A Hazards-Based Correctness Statement for Pipelined Circuits.},
+  booktitle = {Proceedings of the 12th IFIP WG 10.5 Advanced Research Working Conference},
+  publisher = {Springer},
+  year = {2003},
+  volume = {2860},
+  pages = {66-80}
+}
+
    Adler, B., de Alfaro, L., da Silva, L.D., Faella, M., Legay, A., Raman, V. & Roy, P. Thomas Ball and Robert B. Jones (Ed.)Ticc: A Tool for Interface Compatibility and Composition.

    [BibTeX]

    		2006
    Vol. 4144CAV'06: Proceedings of 18th International Conference of Computer Aided Verification, pp. 59-62     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{alder06ticc,
+  author = {B.T.~Adler and L.~de Alfaro and L.~Dias da Silva and M.~Faella and A.~Legay and V.~Raman and P.~Roy},
+  title = {Ticc: A Tool for Interface Compatibility and Composition.},
+  booktitle = {CAV'06: Proceedings of 18th International Conference of Computer Aided Verification},
+  year = {2006},
+  volume = {4144},
+  pages = {59-62}
+}
+
    Akers, B. Binary Decision Diagrams

    [Abstract] [BibTeX]

    		1978IEEE Transactions on Computers
    Vol. 27(6), pp. 509-516     		article  
    Abstract: The seminal paper in which BDD's were introduced. Note that none of the today implementation techniques for BDD package is given in this paper.
    BibTeX: +
    +@article{akers78,
+  author = {B.~Akers},
+  title = {Binary Decision Diagrams},
+  journal = {IEEE Transactions on Computers},
+  year = {1978},
+  volume = {27},
+  number = {6},
+  pages = {509--516}
+}
+
    de Alfaro, L. & Henzinger, T. Interface automata

    [BibTeX]

    		2001ESEC/FSE-9: Proceedings of the 8th European software engineering conference held jointly with 9th ACM SIGSOFT international symposium on Foundations of software engineering, pp. 109-120 inproceedingsDOI   
    BibTeX: +
    +@inproceedings{alfaro01interface,
+  author = {L.~de Alfaro and T.A.~Henzinger},
+  title = {Interface automata},
+  booktitle = {ESEC/FSE-9: Proceedings of the 8th European software engineering conference held jointly with 9th ACM SIGSOFT international symposium on Foundations of software engineering},
+  publisher = {ACM Press},
+  year = {2001},
+  pages = {109--120},
+  doi = {http://doi.acm.org/10.1145/503209.503226}
+}
+
    de Alfaro, L., da Silva, L.D., Faella, M., Legay, A., Roy, P. & Sorea, M. Bernhard Gramlich (Ed.)Sociable Interfaces.

    [BibTeX]

    		2005
    Vol. 3717FroCos'05: Proceedings of the 5th International Workshop on Frontiers of Combining Systems, pp. 81-105     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/frocos/AlfaroSFLRS05,
+  author = {Luca de Alfaro and Leandro Dias da Silva and Marco Faella and Axel Legay and Pritam Roy and Maria Sorea},
+  title = {Sociable Interfaces.},
+  booktitle = {FroCos'05: Proceedings of the 5th International Workshop on Frontiers of Combining Systems},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3717},
+  pages = {81-105}
+}
+
    Aljer, A., Devienne, P., Tison, S., Boulanger, J.-L. & Mariano, G. IEEE Computer Society (Ed.)BHDL: Circuit Design in B

    [BibTeX]

    		2003ACSD '03: Proceedings of the Third International Conference on Application of Concurrency to System Design, pp. 241 inproceedings  
    BibTeX: +
    +@inproceedings{bhdl03,
+  author = {A.~Aljer and P.~Devienne and S.~Tison and J-L.~Boulanger and G.~Mariano},
+  title = {BHDL: Circuit Design in B},
+  booktitle = {ACSD '03: Proceedings of the Third International Conference on Application of Concurrency to System Design},
+  year = {2003},
+  pages = {241}
+}
+
    Alur, R., de Alfaro, L., Henzinger, T.A. & Mang, F.Y. Jos C. M. Baeten and Sjouke Mauw (Ed.)Automating Modular Verification

    [Abstract] [BibTeX]

    		1999
    Vol. 1664CONCUR '99: Concurrency Theory, 10th International Conference, Eindhoven, The Netherlands, August 24-27, 1999, Proceedings, pp. 82-97     		inproceedingsURL 
    + PDF +
     
    Abstract: Modular techniques for automatic verification attempt to overcome the state-explosion problem by exploiting the modular structure naturally present in many system designs. Unlike other tasks in the verification of finite-state systems, current modular techniques rely heavily on user guidance. In particular, the user is typically required to construct module abstractions that are neither too detailed as to render insufficient benefits in state exploration, nor too coarse as to invalidate the desired system properties. In this paper, we construct abstract modules automatically, using reachability and controllability information about the concrete modules. This allows us to leverage automatic verification techniques by applying them in layers: first we compute on the state spaces of system components, then we use the results for constructing abstractions, and finally we compute on the abstract state space of the system. Our experimental results indicate that if reachability and controllabil ity information is used in the construction of abstractions, the resulting abstract modules are often significantly smaller than the concrete modules and can drastically reduce the space and time requirements for verification.
    BibTeX: +
    +@inproceedings{alur99automating,
+  author = {R. Alur and L.~de Alfaro and T. A. Henzinger and F.~Y.C. Mang},
+  title = {Automating Modular Verification},
+  booktitle = {CONCUR '99: Concurrency Theory, 10th International Conference, Eindhoven, The Netherlands, August 24-27, 1999, Proceedings},
+  publisher = {Springer},
+  year = {1999},
+  volume = {1664},
+  pages = {82-97},
+  url = {http://link.springer.de/link/service/series/0558/bibs/1664/16640082.htm}
+}
+
    Alur, R. & Henzinger, T. Reactive Modules.

    [BibTeX]

    		1999Formal Methods in System Design
    Vol. 15(1), pp. 7-48     		article  
    BibTeX: +
    +@article{DBLP:journals/fmsd/AlurH99b,
+  author = {R.~Alur and T.A.~Henzinger},
+  title = {Reactive Modules.},
+  journal = {Formal Methods in System Design},
+  publisher = {Springer},
+  year = {1999},
+  volume = {15},
+  number = {1},
+  pages = {7-48}
+}
+
    Alur, R., Henzinger, T.A. & Kupferman, O. Willem P. de Roever and Hans Langmaack and Amir Pnueli (Ed.)Alternating-Time Temporal Logic

    [BibTeX]

    		1997
    Vol. 1536COMPOS, pp. 23-60     		inproceedings  
    BibTeX: +
    +@inproceedings{alur98alternatingtime,
+  author = {Rajeev Alur and Thomas A. Henzinger and Orna Kupferman},
+  title = {Alternating-Time Temporal Logic},
+  booktitle = {COMPOS},
+  publisher = {Springer},
+  year = {1997},
+  volume = {1536},
+  pages = {23-60}
+}
+
    Alur, R., Henzinger, T., Mang, F.C., Qadeer, S., Rajamani, S. & Tasiran, S. MOCHA: Modularity in Model Checking

    [Abstract] [BibTeX]

    		1998
    Vol. 1427CAV'98: Proceedings of the 10th International Conference on Computer Aided Verification, pp. 521-525     		inproceedings 
    + PDF +
     
    Abstract: We describe a new interactive verification environment called Mocha for modular verification of heterogeneous systems. Mocha differs from existing model checkers in three important ways. First, instead of manipulating unstructured statetransition graphs, it supports the heterogeneous modeling framework of Reactive Modules. Second, instead of traditional temporal logics such as CTL, it uses Alternating Temporal Logic (ATL), a temporal logic that is designed to specify collaborative as ...
    BibTeX: +
    +@inproceedings{alur98mocha,
+  author = {R.~Alur and T.A.~Henzinger and F.Y. C.~Mang and S.~Qadeer and S.K.~Rajamani and S.~Tasiran},
+  title = {MOCHA: Modularity in Model Checking},
+  booktitle = {CAV'98: Proceedings of the 10th International Conference on Computer Aided Verification},
+  year = {1998},
+  volume = {1427},
+  pages = {521-525}
+}
+
    Amla, N., Emerson, E.A., Namjoshi, K.S. & Trefler, R.J. Assume-Guarantee Based Compositional Reasoning for Synchronous Timing Diagrams

    [BibTeX]

    		2001TACAS 2001: Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, pp. 465-479 inproceedings  
    BibTeX: +
    +@inproceedings{amla01assume,
+  author = {N.~Amla and E.~A.~Emerson and K.~S.~Namjoshi and R.~J.~Trefler},
+  title = {Assume-Guarantee Based Compositional Reasoning for Synchronous Timing Diagrams},
+  booktitle = {TACAS 2001: Proceedings of the 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems},
+  publisher = {Springer-Verlag},
+  year = {2001},
+  pages = {465--479}
+}
+
    Andraus, Z.S., Liffiton, M.H. & Sakallah, K.A. Iliano Cervesato and Helmut Veith and Andrei Voronkov (Ed.)Reveal: A Formal Verification Tool for Verilog Designs

    [BibTeX]

    		2008
    Vol. 5330LPAR, pp. 343-352     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/lpar/AndrausLS08,
+  author = {Zaher S. Andraus and Mark H. Liffiton and Karem A. Sakallah},
+  title = {Reveal: A Formal Verification Tool for Verilog Designs},
+  booktitle = {LPAR},
+  publisher = {Springer},
+  year = {2008},
+  volume = {5330},
+  pages = {343-352}
+}
+
    Andraus, Z.S. & Sakallah, K.A. Sharad Malik and Limor Fix and Andrew B. Kahng (Ed.)Automatic abstraction and verification of verilog models

    [BibTeX]

    		2004DAC, pp. 218-223 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/dac/AndrausS04,
+  author = {Zaher S. Andraus and Karem A. Sakallah},
+  title = {Automatic abstraction and verification of verilog models},
+  booktitle = {DAC},
+  publisher = {ACM},
+  year = {2004},
+  pages = {218-223}
+}
+
    Arieli, O. & Avron, A. The Value of the Four Values.

    [BibTeX]

    		1998Artif. Intell.
    Vol. 102(1), pp. 97-141     		article 
    + PDF +
     
    BibTeX: +
    +@article{arieliA98value,
+  author = {Ofer Arieli and Arnon Avron},
+  title = {The Value of the Four Values.},
+  journal = {Artif. Intell.},
+  year = {1998},
+  volume = {102},
+  number = {1},
+  pages = {97-141}
+}
+
    Arnold, A. Translator-John Plaice (Ed.)Finite Transition Systems: Semantics of Communicating Systems

    [BibTeX]

    		1994 book  
    BibTeX: +
    +@book{arnold94finite,
+  author = {A.~Arnold},
+  title = {Finite Transition Systems: Semantics of Communicating Systems},
+  publisher = {Prentice Hall International Ltd.},
+  year = {1994}
+}
+
    Awedh, M. & Somenzi, F. Termination Criteria for Bounded Model Checking: Extensions and Comparison

    [BibTeX]

    		2006Electronic Notes in Theoritical Computer Science.
    Vol. 144(1), pp. 51-66     		article 
    + PDF +
     
    BibTeX: +
    +@article{DBLP:journals/entcs/AwedhS06,
+  author = {M.~Awedh and F.~Somenzi},
+  title = {Termination Criteria for Bounded Model Checking: Extensions and Comparison},
+  journal = {Electronic Notes in Theoritical Computer Science.},
+  year = {2006},
+  volume = {144},
+  number = {1},
+  pages = {51-66}
+}
+
    Awedh, M. & Somenzi, F. Rajeev Alur and Doron Peled (Ed.)Proving More Properties with Bounded Model Checking

    [BibTeX]

    		2004
    Vol. 3114CAV'04: Proceedings of the 16th International Conference on Computer Aided Verification, pp. 96-108     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{Awhed04Proving,
+  author = {M.~Awedh and F.~Somenzi},
+  title = {Proving More Properties with Bounded Model Checking},
+  booktitle = {CAV'04: Proceedings of the 16th International Conference on Computer Aided Verification},
+  publisher = {Springer},
+  year = {2004},
+  volume = {3114},
+  pages = {96-108}
+}
+
    B-Core(UK) Ltd. B-Toolkit User's Manual

    [BibTeX]

    		1997 manualURL  
    BibTeX: +
    +@manual{bmanual,
+  author = {B-Core(UK) Ltd.},
+  title = {B-Toolkit User's Manual},
+  year = {1997},
+  edition = {release 3.7},
+  url = {http://www.b-core.com/downloading.html}
+}
+
    Baclet, M. & Pacalet, R. Dominique Méry and Nidhal Rezg and Xiaolan Xie (Ed.)Vérifications du protocole~VCI

    [BibTeX]

    		2003Actes du 4ème Colloque sur la Modélisation des Systèmes Réactifs (MSR'03), pp. 431-445 inproceedingsURL  
    BibTeX: +
    +@inproceedings{BP-msr03,
+  author = {M.~Baclet and R.~Pacalet},
+  title = {Vérifications du protocole~VCI},
+  booktitle = {Actes du 4ème Colloque sur la Modélisation des Systèmes Réactifs (MSR'03)},
+  publisher = {Hermès},
+  year = {2003},
+  pages = {431-445},
+  url = {http://www.lsv.ens-cachan.fr/Publis/PAPERS/PS/vci-msr03.ps}
+}
+
    Badeau, F. & Amelot, A. Using B as a High Level Programming Language in an Industrial Project: Roissy VAL

    [BibTeX]

    		2005
    Vol. 3455/2005ZB 2005: Formal Specification and Development in Z and B, pp. 334-354     		inproceedingsDOI URL  
    BibTeX: +
    +@inproceedings{broissyval,
+  author = {F.~Badeau and A.~Amelot},
+  title = {Using B as a High Level Programming Language in an Industrial Project: Roissy VAL},
+  booktitle = {ZB 2005: Formal Specification and Development in Z and B},
+  publisher = {Springer Berlin / Heidelberg},
+  year = {2005},
+  volume = {3455/2005},
+  pages = {334-354},
+  url = {http://www.springerlink.com/content/x8mcgk2p8r82e2gl/},
+  doi = {http://dx.doi.org/10.1007/11415787_20}
+}
+
    Ball, T. & Rajamani, S. The SLAM project: debugging system software via static analysis

    [BibTeX]

    		2002POPL '02: Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, pp. 1-3 inproceedingsDOI   
    BibTeX: +
    +@inproceedings{503274,
+  author = {T.~Ball and S.K.~Rajamani},
+  title = {The SLAM project: debugging system software via static analysis},
+  booktitle = {POPL '02: Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages},
+  year = {2002},
+  pages = {1--3},
+  doi = {http://doi.acm.org/10.1145/503272.503274}
+}
+
    Beer, I., Ben-David, S., Eisner, C. & Landver, A. RuleBase: an industry-oriented formal verification tool

    [BibTeX]

    		1996DAC '96: Proceedings of the 33rd annual conference on Design automation, pp. 655-660 inproceedingsDOI   
    BibTeX: +
    +@inproceedings{rulebase96,
+  author = {I.~Beer and S.~Ben-David and C.~Eisner and A.~Landver},
+  title = {RuleBase: an industry-oriented formal verification tool},
+  booktitle = {DAC '96: Proceedings of the 33rd annual conference on Design automation},
+  year = {1996},
+  pages = {655--660},
+  doi = {http://doi.acm.org/10.1145/240518.240642}
+}
+
    Behm, P., Benoit, P., Faivre, A. & Meynadier, J.-M. Jeannette M. Wing and Jim Woodcock and Jim Davies (Ed.)Météor: A Successful Application of B in a Large Project

    [BibTeX]

    		1999
    Vol. 1708World Congress on Formal Methods, pp. 369-387     		inproceedings  
    BibTeX: +
    +@inproceedings{bmethod99meteor,
+  author = {P.~Behm and P.~Benoit and A.~Faivre and J-M.~Meynadier},
+  title = {Météor: A Successful Application of B in a Large Project},
+  booktitle = {World Congress on Formal Methods},
+  publisher = {Springer},
+  year = {1999},
+  volume = {1708},
+  pages = {369-387}
+}
+
    Bjesse, P. Word-level sequential memory abstraction for model checking

    [BibTeX]

    		2008FMCAD '08: Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design, pp. 1-9 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{1517440,
+  author = {Bjesse, Per},
+  title = {Word-level sequential memory abstraction for model checking},
+  booktitle = {FMCAD '08: Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design},
+  publisher = {IEEE Press},
+  year = {2008},
+  pages = {1--9}
+}
+
    Bloem, R., Jobstmann, B. & Pnueli., A. Property-based Logic Synthesis for Rapid Design Prototyping

    [BibTeX]

    		2005 techreport  
    BibTeX: +
    +@techreport{prosyd05,
+  author = {R. Bloem and B. Jobstmann and A. Pnueli.},
+  title = {Property-based Logic Synthesis for Rapid Design Prototyping},
+  year = {2005}
+}
+
    Bozga, M., Fernandez, J.-C., Kerbrat, A. & Mounier, L. Protocol Verification with the ALDÉBARAN Toolset.

    [BibTeX]

    		1997STTT
    Vol. 1(1-2), pp. 166-184     		article  
    BibTeX: +
    +@article{bozga97protocol,
+  author = {M.~Bozga and J-C.~Fernandez and A.~Kerbrat and L.~Mounier},
+  title = {Protocol Verification with the ALDÉBARAN Toolset.},
+  journal = {STTT},
+  publisher = {Springer},
+  year = {1997},
+  volume = {1},
+  number = {1-2},
+  pages = {166-184}
+}
+
    Bradley, A.R. Ranjit Jhala and David A. Schmidt (Ed.)SAT-Based Model Checking without Unrolling

    [BibTeX]

    		2011
    Vol. 6538VMCAI, pp. 70-87     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/vmcai/Bradley11,
+  author = {Aaron R. Bradley},
+  title = {SAT-Based Model Checking without Unrolling},
+  booktitle = {VMCAI},
+  publisher = {Springer},
+  year = {2011},
+  volume = {6538},
+  pages = {70-87}
+}
+
    Brady, B., Bryant, R. & Seshia, S.A. Abstracting RTL Designs to the Term Level

    [Abstract] [BibTeX]

    		2008(UCB/EECS-2008-136) techreportURL 
    + PDF +
     
    Abstract: Term-level verification is a formal technique that seeks to verify RTL hardware descriptions by abstracting away details of data representations and operations. The key to making term-level verification automatic and efficient is in deciding what to abstract. We investigate this question in this paper and propose a solution based on the use of type qualifiers. First, we demonstrate through case studies that only selective term-level abstraction can be very effective in reducing the run-time of formal tools while still retaining precision of analysis. Second, the term-level abstraction process can be guided using lightweight type qualifiers. We present an annotation language and type inference scheme that is applied to the formal verification of the Verilog implementation of a chip multiprocessor router. Experimental results indicate type-based selective term-level abstraction is effective at scaling up verification with minimal designer guidance.
    BibTeX: +
    +@techreport{Brady:EECS-2008-136,
+  author = {Brady, Bryan and Bryant, Randal and Seshia, Sanjit A.},
+  title = {Abstracting RTL Designs to the Term Level},
+  year = {2008},
+  number = {UCB/EECS-2008-136},
+  url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-136.html}
+}
+
    Braunstein, C. "Conception Incrémentale, Vérification de Composants Matériels et Méthode d'abstraction pour la Vérification de SystÚmes Intégrés sur Puce"

    [BibTeX]

    		2007School: Universitée Pierre et Marie Curie (Paris 6) phdthesis  
    BibTeX: +
    +@phdthesis{braunstein_phd07,
+  author = {C.~Braunstein},
+  title = {"Conception Incrémentale, Vérification de Composants Matériels et Méthode d'abstraction pour la Vérification de SystÚmes Intégrés sur Puce"},
+  school = {Universitée Pierre et Marie Curie (Paris 6)},
+  year = {2007}
+}
+
    Braunstein, C. Transformation de propriétés CTL lors d'une méthode de conception incrémentale des wrappers VCI/PI

    [BibTeX]

    		2003 techreport  
    BibTeX: +
    +@techreport{cecile03dea,
+  author = {C.~Braunstein},
+  title = {Transformation de propriétés CTL lors d'une méthode de conception incrémentale des wrappers VCI/PI},
+  year = {2003}
+}
+
    Braunstein, C. & Encrenaz, E. CTL-property Transformations along an Incremental Design Process

    [BibTeX]

    		2007International Journal on Software Tools for Technology Transfer (STTT)
    Vol. 9(1), pp. 77-88     		article  
    BibTeX: +
    +@article{braunstein06sttt,
+  author = {C.~Braunstein and E.~Encrenaz},
+  title = {CTL-property Transformations along an Incremental Design Process},
+  journal = {International Journal on Software Tools for Technology Transfer (STTT)},
+  publisher = {Springer},
+  year = {2007},
+  volume = {9},
+  number = {1},
+  pages = {77--88},
+  note = {A long version including the proof is available at www-asim.lip6.fr/~cecile}
+}
+
    Braunstein, C. & Encrenaz, E. Using CTL formulae as Component Abstraction in a Design and Verification Flow

    [BibTeX]

    		2007ACSD'07: Proceedings of the 7th International Conference on Application of Concurrency to System Design inproceedings  
    BibTeX: +
    +@inproceedings{braunstein07acsd,
+  author = {C.~Braunstein and E.~Encrenaz},
+  title = {Using CTL formulae as Component Abstraction in a Design and Verification Flow},
+  booktitle = {ACSD'07: Proceedings of the 7th International Conference on Application of Concurrency to System Design},
+  year = {2007},
+  note = {accepted}
+}
+
    Braunstein, C. & Encrenaz, E. A Further Step in the Incremental Design Process: Incorporation of an Increment Specification

    [BibTeX]

    		2006LPAR'06: Proceeding of the 13th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning inproceedings  
    BibTeX: +
    +@inproceedings{braunstein06lpar,
+  author = {C.~Braunstein and E.~Encrenaz},
+  title = {A Further Step in the Incremental Design Process: Incorporation of an Increment Specification},
+  booktitle = {LPAR'06: Proceeding of the 13th International Conference on Logic for Programming, Artificial Intelligence, and Reasoning},
+  year = {2006},
+  note = {it short paper, proceedings online http://www.lix.polytechnique.fr/~hermann/LPAR2006/}
+}
+
    Braunstein, C. & Encrenaz, E. Using CTL formulae as component abstraction

    [BibTeX]

    		2006 techreport  
    BibTeX: +
    +@techreport{Braunstein_Encrenaz_RR_LIP6_07_2006,
+  author = {C.~Braunstein and E.~Encrenaz},
+  title = {Using CTL formulae as component abstraction},
+  year = {2006}
+}
+
    Braunstein, C. & Encrenaz, E. Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter

    [BibTeX]

    		2006RSP '06: Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), pp. 103-109 inproceedingsDOI   
    BibTeX: +
    +@inproceedings{pipeline06,
+  author = {C.~Braunstein and E.~Encrenaz},
+  title = {Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter},
+  booktitle = {RSP '06: Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)},
+  publisher = {IEEE Computer Society},
+  year = {2006},
+  pages = {103--109},
+  doi = {http://dx.doi.org/10.1109/RSP.2006.19}
+}
+
    Braunstein, C. & Encrenaz, E. CTL-Property Transformations along an Incremental Design Process

    [BibTeX]

    		2005Electronic Notes in Theoretical Computer Science
    Vol. 128(6), pp. 263-278     		article 
    + PDF +
     
    BibTeX: +
    +@article{avocs_incr,
+  author = {C.~Braunstein and E.~Encrenaz},
+  title = {CTL-Property Transformations along an Incremental Design Process},
+  journal = {Electronic Notes in Theoretical Computer Science},
+  publisher = {Elsevier},
+  year = {2005},
+  volume = {128},
+  number = {6},
+  pages = {263--278}
+}
+
    Browne, M., Clarke, E. & Grumberg, O. Characterizing Finite Kripke Structures in Propositional Temporal Logic

    [BibTeX]

    		1988Theoritical Computer Science
    Vol. 59(1-2), pp. 115-131     		articleDOI   
    BibTeX: +
    +@article{browneclarkegrum88,
+  author = {M.C.~Browne and E.M.~Clarke and O.~Grumberg},
+  title = {Characterizing Finite Kripke Structures in Propositional Temporal Logic},
+  journal = {Theoritical Computer Science},
+  publisher = {Elsevier Science Publishers Ltd.},
+  year = {1988},
+  volume = {59},
+  number = {1-2},
+  pages = {115--131},
+  doi = {http://dx.doi.org/10.1016/0304-3975(88)90098-9}
+}
+
    Bruns, G. & Godefroid, P. Nicolas Halbwachs and Doron Peled (Ed.)Generalized Model Checking: Reasoning about Partial State Spaces

    [BibTeX]

    		2000
    Vol. 1877CONCUR'2000: Proceedings of the 11th International Conference on Concurrency Theory, pp. 168-182     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{bruns00generalized,
+  author = {G.~Bruns and P.~Godefroid},
+  title = {Generalized Model Checking: Reasoning about Partial State Spaces},
+  booktitle = {CONCUR'2000: Proceedings of the 11th International Conference on Concurrency Theory},
+  publisher = {Springer},
+  year = {2000},
+  volume = {1877},
+  pages = {168-182}
+}
+
    Bruns, G. & Godefroid, P. Nicolas Halbwachs and Doron Peled (Ed.)Model Checking Partial State Spaces with 3-Valued Temporal Logics

    [BibTeX]

    		1999
    Vol. 1633CAV'99: Proceedings of the 11th conference on Computer Aided Verification, pp. 274-287     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{burns99partial,
+  author = {G.~Bruns and P.~Godefroid},
+  title = {Model Checking Partial State Spaces with 3-Valued Temporal Logics},
+  booktitle = {CAV'99: Proceedings of the 11th conference on Computer Aided Verification},
+  publisher = {Springer},
+  year = {1999},
+  volume = {1633},
+  pages = {274-287}
+}
+
    Bryant, R. Graph-Based Algorithms for Boolean Function Manipulation

    [BibTeX]

    		1986IEEE Transactions on Computers
    Vol. 35(8), pp. 677-691     		article  
    BibTeX: +
    +@article{Bryant86,
+  author = {R.E.~Bryant},
+  title = {Graph-Based Algorithms for Boolean Function Manipulation},
+  journal = {IEEE Transactions on Computers},
+  year = {1986},
+  volume = {35},
+  number = {8},
+  pages = {677-691}
+}
+
    Bunker, A. & Gopalakrishnan, G. H. Ehrig and B. J. Krämer and A. Ertas (Ed.)Verifying a VCI Bus Interface Model Using an LSC-based Specification

    [BibTeX]

    		2002Proceedings of the Sixth Biennial World Conference on Integrated Design and Process Technology, pp. 48 inproceedingsURL  
    BibTeX: +
    +@inproceedings{bunker:idpt02,
+  author = {A.~Bunker and G.~Gopalakrishnan},
+  title = {Verifying a VCI Bus Interface Model Using an LSC-based Specification},
+  booktitle = {Proceedings of the Sixth Biennial World Conference on Integrated Design and Process Technology},
+  year = {2002},
+  pages = {48},
+  url = {http://www.engineering.usu.edu/ece/faculty/bunker/pubs/idpt02.pdf}
+}
+
    Burch, J., Clarke, E., McMillan, K., Dill, D. & Hwang, L. Symbolic Model Checking: $10^20$ States and Beyond

    [BibTeX]

    		1992Information and Computation
    Vol. 98(2), pp. 142-170     		article  
    BibTeX: +
    +@article{macmillan,
+  author = {J.R.~Burch and E.M.~Clarke and K.L.~McMillan and D.L.~Dill and L.J.~Hwang},
+  title = {Symbolic Model Checking: $10^20$ States and Beyond},
+  journal = {Information and Computation },
+  publisher = {Academic Press, Inc.},
+  year = {1992},
+  volume = {98},
+  number = {2},
+  pages = {142--170},
+  note = {Special issue for best papers from LICS'90}
+}
+
    Burch, J. & Dill, D. D.L. Dill (Ed.)Automatic Verification of Pipelined Microprocessors Control

    [BibTeX]

    		1994
    Vol. LNCS 818Proceedings of the sixth International Conference on Computer-Aided Verification CAV'94, pp. 68-80     		inproceedingsURL  
    BibTeX: +
    +@inproceedings{burch94automatic,
+  author = {J.R.~Burch and D.L.~Dill},
+  title = {Automatic Verification of Pipelined Microprocessors Control},
+  booktitle = {Proceedings of the sixth International Conference on Computer-Aided Verification CAV'94},
+  publisher = {Springer-Verlag},
+  year = {1994},
+  volume = {LNCS 818},
+  pages = {68--80},
+  url = {citeseer.ist.psu.edu/burch94automatic.html}
+}
+
    Burch, J. & Dill, D. Graph-Based Algorithms for Boolean Function Manipulation

    [Abstract] [BibTeX]

    		1982IEEE Transactions on Computers
    Vol. 35(8), pp. 677-691     		article  
    Abstract: Available
    BibTeX: +
    +@article{bryant82,
+  author = {J.R.~Burch and D.L.~Dill},
+  title = {Graph-Based Algorithms for Boolean Function Manipulation},
+  journal = {IEEE Transactions on Computers},
+  year = {1982},
+  volume = {35},
+  number = {8},
+  pages = {677--691}
+}
+
    Büttner, W. Wolfgang J. Paul Dominique Borrione (Ed.)Is Formal Verification Bound to Remain a Junior Partner of Simulation?

    [BibTeX]

    		2005
    Vol. 3725CHARME'2005: Proceedings of the Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, pp. 1     		inproceedings  
    BibTeX: +
    +@inproceedings{Buttner05isformal,
+  author = {W. Büttner},
+  title = {Is Formal Verification Bound to Remain a Junior Partner of Simulation?},
+  booktitle = {CHARME'2005: Proceedings of the Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3725},
+  pages = {1}
+}
+
    Cabodi, G., Camurati, P., Garcia, L., Murciano, M., Nocco, S. & Quer, S. Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints

    [BibTeX]

    		2009DATE '09: Proceedings of the conference on Design, Automation and Test in Europe, pp. 1686-1691 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{Cabodi09Speeding,
+  author = {G. Cabodi and P. Camurati and L. Garcia and M. Murciano and S. Nocco and S. Quer},
+  title = {Speeding up Model Checking by Exploiting Explicit and Hidden Verification Constraints},
+  booktitle = {DATE '09: Proceedings of the conference on Design, Automation and Test in Europe},
+  year = {2009},
+  pages = {1686-1691}
+}
+
    Cansell, D. & Méry, D. S. Gilmore and M. Ryan (Ed.)Abstraction and Refinement of Features

    [Abstract] [BibTeX]

    		2001Language Constructs for Designing Features, pp. 65-84 incollection  
    Abstract: The composition of services and features often leads to unwanted situations, because it is a non-monotonic operation over services and features. When a new service is added to an existing system, conditions have to be checked to ensure that the resulting system satisfies a list of required properties. Following the system approach of Abrial, we develop services and features in an incremental way and use refinement to model the composition of services and features. Proof obligations state the preservation or the non-preservation of properties, namely invariant or more generally safety properties. The method helps us in understanding when a service is interfering with another, and allows us to give multiple views of each service according to the level of its refinement. Finally, we validate our method with the Atelier B tool.
    BibTeX: +
    +@incollection{Cansell2001AbstractionandRefinementofFeatures,
+  author = {D.~Cansell and D.~Méry},
+  title = {Abstraction and Refinement of Features},
+  booktitle = {Language Constructs for Designing Features},
+  publisher = {Springer-Verlag},
+  year = {2001},
+  pages = {65--84}
+}
+
    Cassez, F., Ryan, M. & Schobbens, P.-Y. S. Gilmore and M. Ryan (Ed.)Proving Feature Non-Interaction with Alternating-Time Temporal Logic

    [BibTeX]

    		2001Language Constructs for Describing Features, pp. 85-104 incollection  
    BibTeX: +
    +@incollection{cassez-proving,
+  author = {F.~Cassez and M.~Ryan and P-Y.~Schobbens},
+  title = {Proving Feature Non-Interaction with Alternating-Time Temporal Logic},
+  booktitle = {Language Constructs for Describing Features},
+  publisher = {Springer Verlag},
+  year = {2001},
+  pages = {85--104}
+}
+
    Chauhan, P., Clarke, E., Kukula, J., Sapra, S., Veith, H. & Wang, D. Mark Aagaard and John W. O'Leary (Ed.)Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis

    [BibTeX]

    		2002
    Vol. 2517FMCAD'02: Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design , pp. 33-51     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/fmcad/ChauhanCKSVW02,
+  author = {P.~Chauhan and E.M.~Clarke and J.H.~Kukula and S.~Sapra and H.~Veith and D.~Wang},
+  title = {Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis},
+  booktitle = {FMCAD'02: Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design },
+  publisher = {Springer},
+  year = {2002},
+  volume = {2517},
+  pages = {33-51}
+}
+
    Chechik, M., Devereux, B., Easterbrook, S.M. & Gurfinkel, A. Multi-Valued Symbolic Model-Checking

    [BibTeX]

    		2003ACM Transactions on Software Engineering and Methodology
    Vol. 12(4), pp. 371-408     		article 
    + PDF +
     
    BibTeX: +
    +@article{chechik03multi,
+  author = {M.~Chechik and B.~Devereux and S.~M.~Easterbrook and A.~Gurfinkel},
+  title = {Multi-Valued Symbolic Model-Checking},
+  journal = {ACM Transactions on Software Engineering and Methodology},
+  year = {2003},
+  volume = {12},
+  number = {4},
+  pages = {371-408}
+}
+
    Chechik, M. & Gurfinkel, A. Maura Cerioli (Ed.)A Framework for Counterexample Generation and Exploration.

    [BibTeX]

    		2005
    Vol. 3442FASE, pp. 220-236     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{chechik05framework,
+  author = {Marsha Chechik and Arie Gurfinkel},
+  title = {A Framework for Counterexample Generation and Exploration.},
+  booktitle = {FASE},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3442},
+  pages = {220-236}
+}
+
    Chockler, H., Kupferman, O. & Vardi, M. Tiziana Margaria and Wang Yi (Ed.)Coverage Metrics for Temporal Logic Model Checking

    [BibTeX]

    		2001
    Vol. 2031TACAS'01: 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, pp. 528-542     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{ChocklerKV01,
+  author = {H.~Chockler and O.~Kupferman and M.Y.~Vardi},
+  title = {Coverage Metrics for Temporal Logic Model Checking},
+  booktitle = {TACAS'01: 7th International Conference on Tools and Algorithms for the Construction and Analysis of Systems},
+  publisher = {Springer},
+  year = {2001},
+  volume = {2031},
+  pages = {528-542}
+}
+
    Choi, H., Yim, M.-K., Lee, J.-Y., Yun, B.-W. & Lee, Y.-T. Formal Verification of an Industrial System-on-a-Chip

    [BibTeX]

    		2000ICCD '00: Proceedings of the 2000 IEEE International Conference on Computer Design, pp. 453 inproceedings  
    BibTeX: +
    +@inproceedings{846816,
+  author = {Hoon Choi and Myung-Kyoon Yim and Jae-Young Lee and Byeong-Whee Yun and Yun-Tae Lee},
+  title = {Formal Verification of an Industrial System-on-a-Chip},
+  booktitle = {ICCD '00: Proceedings of the 2000 IEEE International Conference on Computer Design},
+  publisher = {IEEE Computer Society},
+  year = {2000},
+  pages = {453}
+}
+
    Ciardo, G., Lüttgen, G. & Siminiceanu, R. Efficient Symbolic State-Space Construction for Asynchronous Systems

    [BibTeX]

    		2000
    Vol. 1825Proc. of ICATPN'2000, pp. 103-122     		inproceedings  
    BibTeX: +
    +@inproceedings{CLS00,
+  author = {G. Ciardo and G. Lüttgen and R. Siminiceanu},
+  title = {Efficient Symbolic State-Space Construction for Asynchronous Systems},
+  booktitle = {Proc. of ICATPN'2000},
+  publisher = {Springer Verlag},
+  year = {2000},
+  volume = {1825},
+  pages = {103--122}
+}
+
    Cimatti, A., Clarke, E., Giunchiglia, F. & Roveri, M. NUSMV: A New Symbolic Model Checker.

    [BibTeX]

    		2000STTT
    Vol. 2(4), pp. 410-425     		article  
    BibTeX: +
    +@article{cimatti00nusmv,
+  author = {A.~Cimatti and E.M.~Clarke and F.~Giunchiglia and M.~Roveri},
+  title = {NUSMV: A New Symbolic Model Checker.},
+  journal = {STTT},
+  year = {2000},
+  volume = {2},
+  number = {4},
+  pages = {410-425}
+}
+
    Cimatti, A., Dubrovin, J., Junttila, T.A. & Roveri, M. Structure-aware computation of predicate abstraction

    [BibTeX]

    		2009FMCAD, pp. 9-16 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/fmcad/CimattiDJR09,
+  author = {Alessandro Cimatti and Jori Dubrovin and Tommi A. Junttila and Marco Roveri},
+  title = {Structure-aware computation of predicate abstraction},
+  booktitle = {FMCAD},
+  publisher = {IEEE},
+  year = {2009},
+  pages = {9-16}
+}
+
    Cimatti, A., Griggio, A. & Sebastiani, R. Efficient generation of craig interpolants in satisfiability modulo theories

    [BibTeX]

    		2010ACM Trans. Comput. Log.
    Vol. 12(1), pp. 7     		article  
    BibTeX: +
    +@article{DBLP:journals/tocl/CimattiGS10,
+  author = {Alessandro Cimatti and Alberto Griggio and Roberto Sebastiani},
+  title = {Efficient generation of craig interpolants in satisfiability modulo theories},
+  journal = {ACM Trans. Comput. Log.},
+  year = {2010},
+  volume = {12},
+  number = {1},
+  pages = {7}
+}
+
    Claessen, K. & Roorda, J.-W. Marco Bernardo and Alessandro Cimatti (Ed.)An Introduction to Symbolic Trajectory Evaluation

    [BibTeX]

    		2006
    Vol. 3965SFM, pp. 56-77     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/sfm/ClaessenR06,
+  author = {Koen Claessen and Jan-Willem Roorda},
+  title = {An Introduction to Symbolic Trajectory Evaluation},
+  booktitle = {SFM},
+  publisher = {Springer},
+  year = {2006},
+  volume = {3965},
+  pages = {56-77}
+}
+
    Clarke, E. Counterexample-Guided Abstraction Refinement

    [BibTeX]

    		2003TIME, pp. 7 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{clarke03cegar,
+  author = {E.M.~Clarke},
+  title = {Counterexample-Guided Abstraction Refinement},
+  booktitle = {TIME},
+  publisher = {IEEE Computer Society},
+  year = {2003},
+  pages = {7}
+}
+
    Clarke, E. & Emerson, E. Dexter Kozen (Ed.)Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic.

    [BibTeX]

    		1981
    Vol. 131Logic of Programs, pp. 52-71     		inproceedings  
    BibTeX: +
    +@inproceedings{clarkeE81design,
+  author = {E.M.~Clarke and E.A.~Emerson},
+  title = {Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic.},
+  booktitle = {Logic of Programs},
+  publisher = {Springer},
+  year = {1981},
+  volume = {131},
+  pages = {52-71}
+}
+
    Clarke, E., Emerson, E. & Sistla, A. Automatic verification of finite-state concurrent systems using temporal logic specifications

    [BibTeX]

    		1986ACM Transactions on Programming Languages and Systems
    Vol. 8(2)ICATPN'02: Proceedings of the 23rd International Conference on Applications and Theory of Petri Nets, pp. 244-263     		articleDOI   
    BibTeX: +
    +@article{Clarke1986,
+  author = {E.M.~Clarke and E.A.~Emerson and A.P.~Sistla},
+  title = {Automatic verification of finite-state concurrent systems using temporal logic specifications},
+  booktitle = {ICATPN'02: Proceedings of the 23rd International Conference on Applications and Theory of Petri Nets},
+  journal = {ACM Transactions on Programming Languages and Systems},
+  publisher = {ACM Press},
+  year = {1986},
+  volume = {8},
+  number = {2},
+  pages = {244--263},
+  doi = {http://doi.acm.org/10.1145/5397.5399}
+}
+
    Clarke, E., Grumberg, O. & Long, D. Model Checking and Abstraction

    [BibTeX]

    		1994ACM Transactions on Programming Languages and Systems
    Vol. 16(5), pp. 1512-1542     		articleDOI   
    BibTeX: +
    +@article{clarke94model,
+  author = {E.M.~Clarke and O.~Grumberg and D.E.~Long},
+  title = {Model Checking and Abstraction},
+  journal = {ACM Transactions on Programming Languages and Systems},
+  publisher = {ACM Press},
+  year = {1994},
+  volume = {16},
+  number = {5},
+  pages = {1512--1542},
+  doi = {http://doi.acm.org/10.1145/186025.186051}
+}
+
    Clarke, E., Grumberg, O. & Peled, D. Model Checking

    [BibTeX]

    		1999 book  
    BibTeX: +
    +@book{clarke99model,
+  author = {E.M.~Clarke and O.~Grumberg and D.A.~Peled},
+  title = {Model Checking},
+  publisher = {The MIT Press},
+  year = {1999}
+}
+
    Clarke, E., O.Grumberg, Jha, S., Lu, Y. & Veith, H. E.A. Emerson and A.P. Sistla (Ed.)Counterexample-Guided Abstraction Refinement.

    [BibTeX]

    		2000
    Vol. 1855CAV'00: Proceedings of the 12th International Conference on Computer Aided Verification, pp. 154-169     		inproceedings  
    BibTeX: +
    +@inproceedings{ClarkeGJLV00,
+  author = {E.M.~Clarke and O.Grumberg and S.~Jha and Y.~Lu and H.~Veith},
+  title = {Counterexample-Guided Abstraction Refinement.},
+  booktitle = {CAV'00: Proceedings of the 12th International Conference on Computer Aided Verification},
+  publisher = {Springer},
+  year = {2000},
+  volume = {1855},
+  pages = {154-169}
+}
+
    Clarke, E.M., Grumberg, O., Jha, S., Lu, Y. & Veith, H. Counterexample-guided bstraction refinement for symbolic model checking.

    [BibTeX]

    		2003Journal of the ACM
    Vol. 50(5), pp. 752-794     		article 
    + PDF +
     
    BibTeX: +
    +@article{Clarke03cegarsymbolic,
+  author = {E.~M. Clarke and O. Grumberg and S. Jha and Y. Lu and H. Veith},
+  title = {Counterexample-guided bstraction refinement for symbolic model checking.},
+  journal = {Journal of the ACM},
+  year = {2003},
+  volume = {50},
+  number = {5},
+  pages = {752-794}
+}
+
    Clarke, E.M., Grumberg, O., McMillan, K.L. & Zhao, X. Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking

    [BibTeX]

    		1995DAC, pp. 427-432 inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/dac/ClarkeGMZ95,
+  author = {Edmund M. Clarke and Orna Grumberg and Kenneth L. McMillan and Xudong Zhao},
+  title = {Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking},
+  booktitle = {DAC},
+  year = {1995},
+  pages = {427-432}
+}
+
    Clarke, E.M., Gupta, A. & Strichman, O. SAT-based counterexample-guided abstraction refinement

    [BibTeX]

    		2004IEEE Trans. on CAD of Integrated Circuits and Systems
    Vol. 23(7), pp. 1113-1123     		article 
    + PDF +
     
    BibTeX: +
    +@article{DBLP:journals/tcad/ClarkeGS04,
+  author = {Edmund M. Clarke and Anubhav Gupta and Ofer Strichman},
+  title = {SAT-based counterexample-guided abstraction refinement},
+  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
+  year = {2004},
+  volume = {23},
+  number = {7},
+  pages = {1113-1123}
+}
+
    Clarke, E.M., Kurshan, R.P. & Veith, H. Zohar Manna and Doron Peled (Ed.)The Localization Reduction and Counterexample-Guided Abstraction Refinement

    [BibTeX]

    		2010
    Vol. 6200Essays in Memory of Amir Pnueli, pp. 61-71     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/birthday/ClarkeKV10,
+  author = {Edmund M. Clarke and Robert P. Kurshan and Helmut Veith},
+  title = {The Localization Reduction and Counterexample-Guided Abstraction Refinement},
+  booktitle = {Essays in Memory of Amir Pnueli},
+  publisher = {Springer},
+  year = {2010},
+  volume = {6200},
+  pages = {61-71}
+}
+
    Clarke, E.M., Long, D.E. & McMillan, K.L. Compositional Model Checking

    [BibTeX]

    		1989LICS'89: Proceedings of the 4th Annual Symposium on Logic in Computer Science, pp. 353-362 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/lics/ClarkeLM89,
+  author = {E.~M.~Clarke and D.~E.~Long and K.~L.~McMillan},
+  title = {Compositional Model Checking},
+  booktitle = {LICS'89: Proceedings of the 4th Annual Symposium on Logic in Computer Science},
+  publisher = {IEEE Computer Society},
+  year = {1989},
+  pages = {353-362}
+}
+
    Clarke, E.M., Talupur, M., Veith, H. & Wang, D. Enrico Giunchiglia and Armando Tacchella (Ed.)SAT Based Predicate Abstraction for Hardware Verification

    [BibTeX]

    		2003
    Vol. 2919SAT, pp. 78-92     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/sat/ClarkeTVW03,
+  author = {Edmund M. Clarke and Muralidhar Talupur and Helmut Veith and Dong Wang},
+  title = {SAT Based Predicate Abstraction for Hardware Verification},
+  booktitle = {SAT},
+  publisher = {Springer},
+  year = {2003},
+  volume = {2919},
+  pages = {78-92}
+}
+
    Comon, H., Dauchet, M., Gilleron, R., Jacquemard, F., Lugiez, D., Tison, S. & Tommasi, M. Tree Automata Techniques and Applications

    [BibTeX]

    		1997Available on: http://www.grappa.univ-lille3.fr/tata misc 
    + PDF +
     
    BibTeX: +
    +@misc{tata97,
+  author = {H. Comon and M. Dauchet and R. Gilleron and F. Jacquemard and D. Lugiez and S. Tison and M. Tommasi},
+  title = {Tree Automata Techniques and Applications},
+  year = {1997},
+  note = {release October, 1rst 2002}
+}
+
    Coudert, O. & Madre, J.-C. T. Knight and J. Savage (Ed.)A New Method to Compute Prime and Essential Prime Implicants of Boolean Functions

    [Abstract] [BibTeX]

    		1992Advanced Research in VLSI and Parallel Systems, pp. 113-128 inproceedings  
    Abstract: This paper presents how prime implicants and essential prime implicants can be computed by means of meta-products encoded with of BDD's. It gives the equations that mimic the definitions, but it does not propose a recursive algorithm. The variable ordering is discussed and experimental results are provided that come from a benchmark of circuits.
    BibTeX: +
    +@inproceedings{madre,
+  author = {O.~Coudert and J.-C.~Madre},
+  title = {A New Method to Compute Prime and Essential Prime Implicants of Boolean Functions},
+  booktitle = {Advanced Research in VLSI and Parallel Systems},
+  year = {1992},
+  pages = {113--128}
+}
+
    Cousot, P. & Cousot, R. Abstract Interpretation: A Unified Lattice Model for Static Analysis of Programs by Construction or Approximation of Fixpoints.

    [BibTeX]

    		1977POPL'77: Proceedings of the 14th Annual ACM Symposium on Principles of Programming Languages, pp. 238-252 inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/popl/CousotC77,
+  author = {P.~Cousot and R.~Cousot},
+  title = {Abstract Interpretation: A Unified Lattice Model for Static Analysis of Programs by Construction or Approximation of Fixpoints.},
+  booktitle = {POPL'77: Proceedings of the 14th Annual ACM Symposium on Principles of Programming Languages},
+  year = {1977},
+  pages = {238-252}
+}
+
    Couvreur, J., Griffault, A. & Sherman, D. Diagrammes de décision pour la vérification de réseaux à files

    [BibTeX]

    		1999Modélisation de systèmes réactifs (MSR'99) inproceedings  
    BibTeX: +
    +@inproceedings{jmc-ag-djs:ddd,
+  author = {J.M.~Couvreur and A.~Griffault and D.J.~Sherman},
+  title = {Diagrammes de décision pour la vérification de réseaux à files},
+  booktitle = {Modélisation de systèmes réactifs (MSR'99)},
+  year = {1999}
+}
+
    Couvreur, J. & Paviot-Adet, E. New Structural Invariants for Petri Nets Analysis

    [BibTeX]

    		1994
    Vol. 815Proc. of ICATPN'94, pp. 199-218     		inproceedings  
    BibTeX: +
    +@inproceedings{CA94,
+  author = {J.M. Couvreur and E. Paviot-Adet},
+  title = {New Structural Invariants for Petri Nets Analysis},
+  booktitle = {Proc. of ICATPN'94},
+  publisher = {Springer Verlag},
+  year = {1994},
+  volume = {815},
+  pages = {199--218}
+}
+
    Couvreur, J.-M., Encrenaz, E., Paviot-Adet, E., Poitrenaud, D. & Wacrenier, P.-A. Javier Esparza and Charles Lakos (Ed.)Data Decision Diagrams for Petri Net Analysis.

    [BibTeX]

    		2002
    Vol. 2360ICATPN'02: Proceedings of the 23rd International Conference on Applications and Theory of Petri Nets, pp. 101-120     		inproceedings  
    BibTeX: +
    +@inproceedings{CouvreurEPPW02,
+  author = {J-M.~Couvreur and E.~Encrenaz and E.~Paviot-Adet and D.~Poitrenaud and P-A.~Wacrenier},
+  title = {Data Decision Diagrams for Petri Net Analysis.},
+  booktitle = {ICATPN'02: Proceedings of the 23rd International Conference on Applications and Theory of Petri Nets},
+  publisher = {Springer},
+  year = {2002},
+  volume = {2360},
+  pages = {101-120}
+}
+
    Couvreur, J.-M. & Thierry-Mieg, Y. Farn Wang (Ed.)Hierarchical Decision Diagrams to Exploit Model Structure.

    [BibTeX]

    		2005
    Vol. 3731FORTE : Proceedings of the 25th IFIP WG 6.1 International Conference on Formal Techniques for Networked and Distributed Systems, pp. 443-457     		inproceedings  
    BibTeX: +
    +@inproceedings{couvreur05hierarchie,
+  author = {J-M.~Couvreur and Y.~Thierry-Mieg},
+  title = {Hierarchical Decision Diagrams to Exploit Model Structure.},
+  booktitle = {FORTE : Proceedings of the 25th IFIP WG 6.1 International Conference on Formal Techniques for Networked and Distributed Systems},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3731},
+  pages = {443-457}
+}
+
    Dams, D., Gerth, R. & Grumberg, O. Abstract interpretation of reactive systems

    [BibTeX]

    		1997ACM Transactions on Programming Languages and Systems
    Vol. 19(2), pp. 253-291     		articleDOI   
    BibTeX: +
    +@article{dams97abstract,
+  author = {D.~Dams and R.~Gerth and O.~Grumberg},
+  title = {Abstract interpretation of reactive systems},
+  journal = {ACM Transactions on Programming Languages and Systems},
+  publisher = {ACM Press},
+  year = {1997},
+  volume = {19},
+  number = {2},
+  pages = {253--291},
+  doi = {http://doi.acm.org/10.1145/244795.244800}
+}
+
    Dams, D. & Namjoshi, K.S. Radhia Cousot (Ed.)Automata as Abstractions.

    [BibTeX]

    		2005
    Vol. 3385VMCAI'05: Proceedings of the 6th International Conference on Verification, Model Checking, and Abstract Interpretation, pp. 216-232     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/vmcai/DamsN05,
+  author = {D.~Dams and K.~S.~Namjoshi},
+  title = {Automata as Abstractions.},
+  booktitle = {VMCAI'05: Proceedings of the 6th International Conference on Verification, Model Checking, and Abstract Interpretation},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3385},
+  pages = {216-232}
+}
+
    Dams, D. & Namjoshi, K.S. The Existence of Finite Abstractions for Branching Time Model Checking.

    [BibTeX]

    		2004LICS04, pp. 335-344 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/lics/DamsN04,
+  author = {D.~Dams and K.~S.~Namjoshi},
+  title = {The Existence of Finite Abstractions for Branching Time Model Checking.},
+  booktitle = {LICS04},
+  publisher = {IEEE Computer Society},
+  year = {2004},
+  pages = {335-344}
+}
+
    Darbari, A., Al Hashimi, B., Harrod, P. & Bradley, D. A New Approach for Transient Fault Injection Using Symbolic Simulation

    [BibTeX]

    		2008On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE InternationalIEEE International Symposium On-line Testing Symposium, pp. 93-98 inproceedingsDOI   
    BibTeX: +
    +@inproceedings{Darbari08transient,
+  author = {Darbari, A. and Al Hashimi, B. and Harrod, P. and Bradley, D.},
+  title = {A New Approach for Transient Fault Injection Using Symbolic Simulation},
+  booktitle = {IEEE International Symposium On-line Testing Symposium},
+  journal = {On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International},
+  year = {2008},
+  pages = {93-98},
+  doi = {http://dx.doi.org/10.1109/IOLTS.2008.59}
+}
+
    Duret-Lutz, A. & Rebiha, R. SPOT : Une bibliothÚque de vérificaion de propriétés de logique temporelle à temps linéaire

    [BibTeX]

    		2003 misc 
    + PDF +
     
    BibTeX: +
    +@misc{duret03dea,
+  author = {A.~Duret-Lutz and R.~Rebiha},
+  title = {SPOT : Une bibliothÚque de vérificaion de propriétés de logique temporelle à temps linéaire},
+  year = {2003}
+}
+
    Dwyer, M.B., Avrunin, G.S. & Corbett, J.C. ACM (Ed.)Patterns in Property Specifications for Finite-State Verification.

    [BibTeX]

    		1999ICSE' 99. Proceedings of the 1999 International Conference on Software Engineering, pp. 411-420 inproceedingsURL  
    BibTeX: +
    +@inproceedings{dwyer99patterns,
+  author = {M. B. Dwyer and G. S. Avrunin and J. C. Corbett},
+  title = {Patterns in Property Specifications for Finite-State Verification.},
+  booktitle = {ICSE' 99. Proceedings of the 1999 International Conference on Software Engineering},
+  year = {1999},
+  pages = {411-420},
+  url = {http://patterns.projects.cis.ksu.edu/collaborations/papers.shtml}
+}
+
    Dwyer, M.B., Hatcliff, J., Joehanes, R., Laubach, S., Pasareanu, C.S., Robby, Zheng, H. & Visser, W. Tool-Supported Program Abstraction for Finite-State Verification.

    [BibTeX]

    		2001ICSE, pp. 177-187 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/icse/DwyerHJLPRZV01,
+  author = {Matthew B. Dwyer and John Hatcliff and Roby Joehanes and Shawn Laubach and Corina S. Pasareanu and Robby and Hongjun Zheng and Willem Visser},
+  title = {Tool-Supported Program Abstraction for Finite-State Verification.},
+  booktitle = {ICSE},
+  publisher = {IEEE Computer Society},
+  year = {2001},
+  pages = {177-187}
+}
+
    Easterbrook, S., Chechik, M., Devereux, B., Gurfinkel, A., Lai, A., Petrovykh, V., Tafliovich, A. & Thompson-Walsh, C. $i$Chek: A Model Checker for Multi-Valued Reasoning.

    [BibTeX]

    		2003ICSE'03: Proceedings of the 25th International Conference on Software Engineering, pp. 804-805 inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/icse/EasterbrookCDGLPTT03,
+  author = {S.M.~Easterbrook and M.~Chechik and B.~Devereux and A.~Gurfinkel and A.~Lai and V.~Petrovykh and A.~Tafliovich and C.~Thompson-Walsh},
+  title = {$i$Chek: A Model Checker for Multi-Valued Reasoning.},
+  booktitle = {ICSE'03: Proceedings of the 25th International Conference on Software Engineering},
+  publisher = {IEEE Computer Society},
+  year = {2003},
+  pages = {804-805}
+}
+
    Easterbrook, S.M. & Chechik, M. A Framework for Multi-Valued Reasoning over Inconsistent Viewpoints.

    [BibTeX]

    		2001ICSE, pp. 411-420 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{EasterbrookC01,
+  author = {Steve M. Easterbrook and Marsha Chechik},
+  title = {A Framework for Multi-Valued Reasoning over Inconsistent Viewpoints.},
+  booktitle = {ICSE},
+  publisher = {IEEE Computer Society},
+  year = {2001},
+  pages = {411-420}
+}
+
    Emerson, E. & Halpern, J. Decision Procedures and Expressiveness in the Temporal Logic of Branching Time

    [BibTeX]

    		1982STOC, pp. 169-180 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{emerson82desision,
+  author = {E.A.~Emerson and J.Y.~Halpern},
+  title = {Decision Procedures and Expressiveness in the Temporal Logic of Branching Time},
+  booktitle = {STOC},
+  publisher = {ACM},
+  year = {1982},
+  pages = {169-180}
+}
+
    Fey, Gö., Staber, S., Bloem, R. & Drechsler, R. Automatic Fault Localization for Property Checking

    [BibTeX]

    		2008IEEE Trans. on CAD of Integrated Circuits and Systems
    Vol. 27(6), pp. 1138-1149     		article  
    BibTeX: +
    +@article{DBLP:journals/tcad/FeySBD08,
+  author = {Görschwin Fey and Stefan Staber and Roderick Bloem and Rolf Drechsler},
+  title = {Automatic Fault Localization for Property Checking},
+  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
+  year = {2008},
+  volume = {27},
+  number = {6},
+  pages = {1138-1149}
+}
+
    Fitting, M. Bilattices and the Semantics of Logic Programming.

    [BibTeX]

    		1991Journal of Logic Programming
    Vol. 11(1{\&}2), pp. 91-116     		article 
    + PDF +
     
    BibTeX: +
    +@article{fitting91bilattices,
+  author = {M.~Fitting},
+  title = {Bilattices and the Semantics of Logic Programming.},
+  journal = {Journal of Logic Programming},
+  year = {1991},
+  volume = {11},
+  number = {1&2},
+  pages = {91-116}
+}
+
    Ganai, M.K., Gupta, A. & Ashar, P. Verification of Embedded Memory Systems using Efficient Memory Modeling

    [BibTeX]

    		2005DATE, pp. 1096-1101 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/date/GanaiGA05,
+  author = {Malay K. Ganai and Aarti Gupta and Pranav Ashar},
+  title = {Verification of Embedded Memory Systems using Efficient Memory Modeling},
+  booktitle = {DATE},
+  year = {2005},
+  pages = {1096-1101}
+}
+
    Godefroid, P. & Jagadeesan, R. On the Expressiveness of 3-Valued Models

    [BibTeX]

    		2003VMCAI 2003: Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation, pp. 206-222 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{godefroid03expressiveness,
+  author = {Patrice Godefroid and Radha Jagadeesan},
+  title = {On the Expressiveness of 3-Valued Models},
+  booktitle = {VMCAI 2003: Proceedings of the 4th International Conference on Verification, Model Checking, and Abstract Interpretation},
+  publisher = {Springer-Verlag},
+  year = {2003},
+  pages = {206--222}
+}
+
    Godefroid, P. & Jagadeesan, R. Ed Brinksma and Kim Guldstrand Larsen (Ed.)Automatic Abstraction Using Generalized Model Checking.

    [BibTeX]

    		2002
    Vol. 2404CAV, pp. 137-150     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/cav/GodefroidJ02,
+  author = {P.~Godefroid and R.~Jagadeesan},
+  title = {Automatic Abstraction Using Generalized Model Checking.},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {2002},
+  volume = {2404},
+  pages = {137-150}
+}
+
    Goel, A. & Lee, W.R. ACM (Ed.)Formal Verification of an IBM CoreConnect Processor Local Bus Arbiter Core

    [BibTeX]

    		2000DAC'00: Proceedings of the 37th Conference on Design Automation, pp. 196-200 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{goelL00formal,
+  author = {A.~Goel and W.~R.~Lee},
+  title = {Formal Verification of an IBM CoreConnect Processor Local Bus Arbiter Core},
+  booktitle = {DAC'00: Proceedings of the 37th Conference on Design Automation},
+  year = {2000},
+  pages = {196-200}
+}
+
    Graf, S. & Sadi, H. Orna Grumberg (Ed.)Construction of Abstract State Graphs with PVS.

    [BibTeX]

    		1997
    Vol. 1254CAV, pp. 72-83     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{GrafS97pvs,
+  author = {S.~Graf and H.~Sadi},
+  title = {Construction of Abstract State Graphs with PVS.},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {1997},
+  volume = {1254},
+  pages = {72-83}
+}
+
    Grumberg, O. Frank S. de Boer and Marcello M. Bonsangue and Susanne Graf and Willem P. de Roever (Ed.)Abstraction and Refinement in Model Checking.

    [BibTeX]

    		2005
    Vol. 4111FMCO'05: 4th International Symposium on Formal Methods for Components and Objects,, pp. 219-242     		inproceedings  
    BibTeX: +
    +@inproceedings{grumberg05abstraction,
+  author = {Orna Grumberg},
+  title = {Abstraction and Refinement in Model Checking.},
+  booktitle = {FMCO'05: 4th International Symposium on Formal Methods for Components and Objects,},
+  publisher = {Springer},
+  year = {2005},
+  volume = {4111},
+  pages = {219-242}
+}
+
    Grumberg, O. & Long, D. Model Checking and Modular Verification

    [BibTeX]

    		1991
    Vol. 527International Conference on Concurrency Theory, pp. 250-263     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{GL91,
+  author = {O.~Grumberg and D.E.~Long},
+  title = {Model Checking and Modular Verification},
+  booktitle = {International Conference on Concurrency Theory},
+  publisher = {Springer Verlag},
+  year = {1991},
+  volume = {527},
+  pages = {250--263}
+}
+
    Gupta, A. Formal Hardware Verification Methods: A Survey.

    [BibTeX]

    		1992Formal Methods in System Design
    Vol. 1(2/3), pp. 151-238     		article  
    BibTeX: +
    +@article{Gupta92syrvey,
+  author = {A.~Gupta},
+  title = {Formal Hardware Verification Methods: A Survey.},
+  journal = {Formal Methods in System Design},
+  year = {1992},
+  volume = {1},
+  number = {2/3},
+  pages = {151-238}
+}
+
    Gupta, A., Ganai, M.K. & Wang, C. Marco Bernardo and Alessandro Cimatti (Ed.)SAT-Based Verification Methods and Applications in Hardware Verification

    [BibTeX]

    		2006
    Vol. 3965SFM, pp. 108-143     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/sfm/GuptaGW06,
+  author = {Aarti Gupta and Malay K. Ganai and Chao Wang},
+  title = {SAT-Based Verification Methods and Applications in Hardware Verification},
+  booktitle = {SFM},
+  publisher = {Springer},
+  year = {2006},
+  volume = {3965},
+  pages = {108-143}
+}
+
    Gurfinkel, A. & Chechik, M. Holger Hermanns and Jens Palsberg (Ed.)Why Waste a Perfectly Good Abstraction?.

    [BibTeX]

    		2006
    Vol. 3920TACAS'06: Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems, pp. 212-226     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{gurfinkelC06waste,
+  author = {A.~Gurfinkel and M.~Chechik},
+  title = {Why Waste a Perfectly Good Abstraction?.},
+  booktitle = {TACAS'06: Proceedings of the 12th international conference on Tools and Algorithms for the Construction and Analysis of Systems},
+  publisher = {Springer},
+  year = {2006},
+  volume = {3920},
+  pages = {212-226}
+}
+
    Gurfinkel, A., Wei, O. & Chechik, M. E. Allen Emerson and Kedar S. Namjoshi (Ed.)Systematic Construction of Abstractions for Model-Checking

    [BibTeX]

    		2006
    Vol. 3855VMCAI, pp. 381-397     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/vmcai/GurfinkelWC06,
+  author = {Arie Gurfinkel and Ou Wei and Marsha Chechik},
+  title = {Systematic Construction of Abstractions for Model-Checking},
+  booktitle = {VMCAI},
+  publisher = {Springer},
+  year = {2006},
+  volume = {3855},
+  pages = {381-397}
+}
+
    Gurfinkel, A., Wei, O. & Chechik, M. E. Allen Emerson and Kedar S. Namjoshi (Ed.)Systematic Construction of Abstractions for Model-Checking.

    [BibTeX]

    		2006
    Vol. 3855VMCAI'06: Proceedings of the 7th International Conference on Verification, Model Checking, and Abstract Interpretation, pp. 381-397     		inproceedings  
    BibTeX: +
    +@inproceedings{GurfinkelWC06,
+  author = {Gurfinkel, A. and Wei, O. and Chechik, M.},
+  title = {Systematic Construction of Abstractions for Model-Checking.},
+  booktitle = {VMCAI'06: Proceedings of the 7th International Conference on Verification, Model Checking, and Abstract Interpretation},
+  publisher = {Springer},
+  year = {2006},
+  volume = {3855},
+  pages = {381-397}
+}
+
    Henzinger, T.A., Liu, X., Qadeer, S. & Rajamani, S.K. Ellen Sentovich Jacob K. White (Ed.)Formal Specification and Verification of a Dataflow Processor Array.

    [BibTeX]

    		1999ICCAD'99: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, pp. 494-499 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{henzinger99dsp,
+  author = {T.~A.~Henzinger and X.~Liu and S.~Qadeer and S.~K.~Rajamani},
+  title = {Formal Specification and Verification of a Dataflow Processor Array.},
+  booktitle = {ICCAD'99: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design},
+  year = {1999},
+  pages = {494-499}
+}
+
    Henzinger, T.A., Qadeer, S. & Rajamani, S.K. Decomposing refinement proofs using assume-guarantee reasoning

    [BibTeX]

    		2000ICCAD '00: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, pp. 245-253 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{henzinger00decomposing,
+  author = {Thomas A. Henzinger and Shaz Qadeer and Sriram K. Rajamani},
+  title = {Decomposing refinement proofs using assume-guarantee reasoning},
+  booktitle = {ICCAD '00: Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design},
+  publisher = {IEEE Press},
+  year = {2000},
+  pages = {245--253}
+}
+
    Henzinger, T., Jhala, R., Majumdar, R. & Sutre, G. Software Verification with BLAST

    [BibTeX]

    		2003
    Vol. 2648SPIN'2003: Proceedings of the 10th International SPIN Workshop, pp. 235-239     		inproceedingsURL  
    BibTeX: +
    +@inproceedings{C:HJMS03,
+  author = {Henzinger, T.A. and Jhala, R. and Majumdar, R. and Sutre, G.},
+  title = {Software Verification with BLAST},
+  booktitle = {SPIN'2003: Proceedings of the 10th International SPIN Workshop},
+  publisher = {Springer},
+  year = {2003},
+  volume = {2648},
+  pages = {235--239},
+  note = {Tool paper},
+  url = {http://www.labri.fr/publications/mvtsi/2003/HJMS03}
+}
+
    Henzinger, T., Qadeer, S. & Rajamani, S. Moshe Y. Vardi Alan J. Hu (Ed.)You Assume, We Guarantee: Methodology and Case Studies

    [BibTeX]

    		1998
    Vol. 1427CAV'98: Proceedings of the 10th International Conference on Computer Aided Verification, pp. 440-451     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{henzinger98you,
+  author = {T.A.~Henzinger and S.~Qadeer and S.K.~Rajamani},
+  title = {You Assume, We Guarantee: Methodology and Case Studies},
+  booktitle = {CAV'98: Proceedings of the 10th International Conference on Computer Aided Verification},
+  publisher = {Springer-Verlag},
+  year = {1998},
+  volume = {1427},
+  pages = {440--451}
+}
+
    Henzinger, T., Qadeer, S., Rajamani, S. & Tasiran, S. An Assume-Guarantee Rule for Checking Simulation

    [BibTeX]

    		2002ACM Transactions on Programming Languages Systems
    Vol. 24(1), pp. 51-64     		articleDOI  
    + PDF +
     
    BibTeX: +
    +@article{henzinger02anassume,
+  author = {T.A.~Henzinger and S.~Qadeer and S.K.~Rajamani and S.~Tasiran},
+  title = {An Assume-Guarantee Rule for Checking Simulation},
+  journal = {ACM Transactions on Programming Languages Systems},
+  publisher = {ACM Press},
+  year = {2002},
+  volume = {24},
+  number = {1},
+  pages = {51--64},
+  doi = {http://doi.acm.org/10.1145/509705.509707}
+}
+
    Holzmann, G. The Model Checker Spin

    [BibTeX]

    		1997IEEE Transactions on Software Engineering
    Vol. 23(5), pp. 279-295     		article  
    BibTeX: +
    +@article{Holzmann97e,
+  author = {G.J.~Holzmann},
+  title = {The Model Checker Spin},
+  journal = {IEEE Transactions on Software Engineering},
+  year = {1997},
+  volume = {23},
+  number = {5},
+  pages = {279--295},
+  note = {Special issue on Formal Methods in Software Practice}
+}
+
    Hosabettu, R., Srivas, M. & Gopalakrishnan, G. Alan J. Hu and Moshe Y. Vardi (Ed.)Decomposing the Proof of Correctness of Pipelined Microprocessors

    [BibTeX]

    		1998
    Vol. 1427Computer-Aided Verification, CAV'98, pp. 122-134     		inproceedingsURL  
    BibTeX: +
    +@inproceedings{hosabettu98decomposing,
+  author = {R.~Hosabettu and M.~Srivas and G.~Gopalakrishnan},
+  title = {Decomposing the Proof of Correctness of Pipelined Microprocessors},
+  booktitle = {Computer-Aided Verification, CAV'98},
+  publisher = {Springer-Verlag},
+  year = {1998},
+  volume = {1427},
+  pages = {122--134},
+  url = {citeseer.ist.psu.edu/208243.html}
+}
+
    Huggins, J. & Campenhout, D.V. Specification and Verification of Pipelining in the ARM2 RISC Microprocessor

    [BibTeX]

    		1998ACM Transactions on Design Automation of Electronic Systems
    Vol. 3(4), pp. 563-580     		articleDOI   
    BibTeX: +
    +@article{huggins98spec,
+  author = {J.K.~Huggins and D.~Van Campenhout},
+  title = {Specification and Verification of Pipelining in the ARM2 RISC Microprocessor},
+  journal = {ACM Transactions on Design Automation of Electronic Systems},
+  publisher = {ACM Press},
+  year = {1998},
+  volume = {3},
+  number = {4},
+  pages = {563--580},
+  doi = {http://doi.acm.org/10.1145/296333.296345}
+}
+
    Hulgaard, H., Williams, P.F. & Andersen, H.R. Equivalence Checking of Combinational Circuits using Boolean Expression Diagrams

    [BibTeX]

    		1999IEEE Transactions of Computer-Aided Design
    Vol. 18(7), pp. 903-917     		article  
    BibTeX: +
    +@article{HWA99,
+  author = {H.~Hulgaard and P.~F.~Williams and H.~R.~Andersen},
+  title = {Equivalence Checking of Combinational Circuits using Boolean Expression Diagrams},
+  journal = {IEEE Transactions of Computer-Aided Design},
+  year = {1999},
+  volume = {18},
+  number = {7},
+  pages = {903-917}
+}
+
    Jain, H., Kroening, D., Sharygina, N. & Clarke, E. Andrew B. Kahng William H. Joyner Jr., Grant Martin (Ed.)Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog.

    [BibTeX]

    		2005DAC'05: Proceedings of the 42nd Design Automation Conference, pp. 445-450 inproceedings  
    BibTeX: +
    +@inproceedings{JainKSC05,
+  author = {Jain, H. and Kroening, D. and Sharygina, N. and Clarke, E.M.},
+  title = {Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog.},
+  booktitle = {DAC'05: Proceedings of the 42nd Design Automation Conference},
+  publisher = {ACM},
+  year = {2005},
+  pages = {445-450}
+}
+
    Jain, H., Kroening, D., Sharygina, N. & Clarke, E. Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog

    [BibTeX]

    		2008IEEE Transaction on CAD of Integrated Circuits and Systems
    Vol. 27(2), pp. 366-379     		article 
    + PDF +
     
    BibTeX: +
    +@article{DBLP:journals/tcad/JainKSC08,
+  author = {H.~Jain and D.~Kroening and N.~Sharygina and E.M.~Clarke},
+  title = {Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog},
+  journal = {IEEE Transaction on CAD of Integrated Circuits and Systems},
+  year = {2008},
+  volume = {27},
+  number = {2},
+  pages = {366-379}
+}
+
    Jain, H., Kroening, D., Sharygina, N. & Clarke, E. VCEGAR: Verilog CounterExample Guided Abstraction Refinement

    [BibTeX]

    		2007TACAS'07: Proceedings of the 13th International Conference on Tools and Algorithms for the Construction and Analysis of Systems inproceedings  
    BibTeX: +
    +@inproceedings{kroening07vcegar,
+  author = {H.~Jain and D.~Kroening and N.~Sharygina and E.~Clarke},
+  title = {VCEGAR: Verilog CounterExample Guided Abstraction Refinement},
+  booktitle = {TACAS'07: Proceedings of the 13th International Conference on Tools and Algorithms for the Construction and Analysis of Systems},
+  year = {2007},
+  note = {Accepted paper}
+}
+
    Jain, J., Narayan, A., Fujita, M. & Sangiovanni-Vincentelli, A. A Survey of Techniques for Formal Verification of Combinational Circuits.

    [BibTeX]

    		1997ICCD, pp. 445-454 inproceedings  
    BibTeX: +
    +@inproceedings{JainNFS97survey,
+  author = {J.~Jain and A.~Narayan and M.~Fujita and A.L.~Sangiovanni-Vincentelli},
+  title = {A Survey of Techniques for Formal Verification of Combinational Circuits.},
+  booktitle = {ICCD},
+  year = {1997},
+  pages = {445-454}
+}
+
    Jhala, R. & McMillan, K. Alain Finkel Gérard Berry, Hubert Comon (Ed.)Microarchitecture Verification by Compositional Model Checking.

    [BibTeX]

    		2001
    Vol. 2102CAV'01: Proceedings of the 13th International Conference on Computer Aided Verification, pp. 396-410     		inproceedings  
    BibTeX: +
    +@inproceedings{jhala01microarchi,
+  author = {Jhala, R. and McMillan, K.L.},
+  title = {Microarchitecture Verification by Compositional Model Checking.},
+  booktitle = {CAV'01: Proceedings of the 13th International Conference on Computer Aided Verification},
+  publisher = {Springer},
+  year = {2001},
+  volume = {2102},
+  pages = {396-410}
+}
+
    Jin, H., Awedh, M. & Somenzi, F. Rajeev Alur and Doron Peled (Ed.)CirCUs: A Satisfiability Solver Geared towards Bounded Model Checking

    [BibTeX]

    		2004
    Vol. 3114CAV'04: Proceedings of the 16th International Conference onComputer Aided Verification , pp. 519-522     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{Somenzi04Circuscav,
+  author = {HoonSang Jin and Mohammad Awedh and Fabio Somenzi},
+  title = {CirCUs: A Satisfiability Solver Geared towards Bounded Model Checking},
+  booktitle = {CAV'04: Proceedings of the 16th International Conference onComputer Aided Verification },
+  publisher = {Springer},
+  year = {2004},
+  volume = {3114},
+  pages = {519-522}
+}
+
    Jin, H., Han, H. & Somenzi, F. Nicolas Halbwachs and Lenore D. Zuck (Ed.)Efficient Conflict Analysis for Finding All Satisfying Assignments of a Boolean Circuit

    [BibTeX]

    		2005
    Vol. 3440TACAS'05: Proceedings of 11th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, pp. 287-300     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/tacas/JinHS05,
+  author = {HoonSang Jin and HyoJung Han and Fabio Somenzi},
+  title = {Efficient Conflict Analysis for Finding All Satisfying Assignments of a Boolean Circuit},
+  booktitle = {TACAS'05: Proceedings of 11th International Conference on Tools and Algorithms for the Construction and Analysis of Systems},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3440},
+  pages = {287-300}
+}
+
    Jin, H. & Somenzi, F. CirCUs: A Hybrid Satisfiability Solver

    [BibTeX]

    		2004SAT'04: The 7th International Conference on Theory and Applications of Satisfiability Testing inproceedings  
    BibTeX: +
    +@inproceedings{somenzi04Circus,
+  author = {H*.~Jin and F.~Somenzi},
+  title = {CirCUs: A Hybrid Satisfiability Solver},
+  booktitle = {SAT'04: The 7th International Conference on Theory and Applications of Satisfiability Testing},
+  year = {2004}
+}
+
    Kaluzhny, Y. & Muravitsky, A.Y. A knowledge representation based on the Belnap's four-valued logic

    [BibTeX]

    		1993Journal of Applied Non-Classical Logics
    Vol. 3(2), pp. 189-203     		article 
    + PDF +
     
    BibTeX: +
    +@article{kalushy93knowledge,
+  author = {Yuri Kaluzhny and Alexei Yu. Muravitsky},
+  title = {A knowledge representation based on the Belnap's four-valued logic},
+  journal = {Journal of Applied Non-Classical Logics},
+  year = {1993},
+  volume = {3},
+  number = {2},
+  pages = {189-203}
+}
+
    Kang, H.-J. & Park, I.-C. SAT-based Unbounded Symbolic Model Checking

    [BibTeX]

    		2003DAC'03: Proceedings of the 40th conference on Design automation, pp. 840-843 inproceedingsDOI  
    + PDF +
     
    BibTeX: +
    +@inproceedings{park03satunbounded,
+  author = {H.-J.~Kang and I.-C.~Park},
+  title = {SAT-based Unbounded Symbolic Model Checking},
+  booktitle = {DAC'03: Proceedings of the 40th conference on Design automation},
+  publisher = {ACM},
+  year = {2003},
+  pages = {840--843},
+  doi = {http://doi.acm.org/10.1145/775832.776043}
+}
+
    Kern, C. & Greenstreet, M. Formal Verification in Hardware Design: a Survey

    [BibTeX]

    		1999ACM Transactions on Design Automation of Electronic Systems
    Vol. 4(2), pp. 123-193     		articleDOI   
    BibTeX: +
    +@article{Kern99survey,
+  author = {C.~Kern and M.R.~Greenstreet},
+  title = {Formal Verification in Hardware Design: a Survey},
+  journal = {ACM Transactions on Design Automation of Electronic Systems},
+  publisher = {ACM Press},
+  year = {1999},
+  volume = {4},
+  number = {2},
+  pages = {123--193},
+  doi = {http://doi.acm.org/10.1145/307988.307989}
+}
+
    Kleene, S. Introduction to Metamathematics

    [BibTeX]

    		1952 book  
    BibTeX: +
    +@book{kleene52introduction,
+  author = {Kleene, S.},
+  title = {Introduction to Metamathematics},
+  publisher = {North-Holland},
+  year = {1952}
+}
+
    Kolks, T., Lin, B. & Man, H.D. Sizing and Verification of Communication Buffers for Communicating Processes

    [BibTeX]

    		1993
    Vol. 1825Proc. of IEEE International Conference on Computer-Aided Design, pp. 660-664     		inproceedings  
    BibTeX: +
    +@inproceedings{KLM93,
+  author = {T. Kolks and B. Lin and H. De Man},
+  title = {Sizing and Verification of Communication Buffers for Communicating Processes},
+  booktitle = {Proc. of IEEE International Conference on Computer-Aided Design},
+  year = {1993},
+  volume = {1825},
+  pages = {660--664}
+}
+
    Kroening, D. & Paul, W. Automated Pipeline Design

    [BibTeX]

    		2001DAC '01: Proceedings of the 38th conference on Design Automation, pp. 810-815 inproceedingsDOI   
    BibTeX: +
    +@inproceedings{kroening01automated,
+  author = {D.~Kroening and W.J.~Paul},
+  title = {Automated Pipeline Design},
+  booktitle = {DAC '01: Proceedings of the 38th conference on Design Automation},
+  publisher = {ACM Press},
+  year = {2001},
+  pages = {810--815},
+  doi = {http://doi.acm.org/10.1145/378239.379071}
+}
+
    Kropf, T. Introduction to Formal Hardware Verification

    [BibTeX]

    		1999 book  
    BibTeX: +
    +@book{kropf99introduction,
+  author = {T.~Kropf},
+  title = {Introduction to Formal Hardware Verification},
+  publisher = {Springer Verlag},
+  year = {1999}
+}
+
    Kupferman, O. & Grumberg, O. Branching-Time Temporal Logic and Tree Automata.

    [BibTeX]

    		1996Information and Computation
    Vol. 125(1), pp. 62-69     		article 
    + PDF +
     
    BibTeX: +
    +@article{KupfermanG96branching,
+  author = {O.~Kupferman and O.~Grumberg},
+  title = {Branching-Time Temporal Logic and Tree Automata.},
+  journal = {Information and Computation},
+  year = {1996},
+  volume = {125},
+  number = {1},
+  pages = {62-69}
+}
+
    Kupferman, O., Vardi, M. & Wolper, P. An Automata-Theoretic Approach to Branching-Time Model Checking.

    [BibTeX]

    		2000Journal of the ACM
    Vol. 47(2), pp. 312-360     		article 
    + PDF +
     
    BibTeX: +
    +@article{KupfermanVW00automata,
+  author = {O.~Kupferman and M.Y.~Vardi and P.~Wolper},
+  title = {An Automata-Theoretic Approach to Branching-Time Model Checking.},
+  journal = {Journal of the ACM},
+  year = {2000},
+  volume = {47},
+  number = {2},
+  pages = {312-360}
+}
+
    Lamport, L. Information Processing

    [BibTeX]

    		1983What good is in temporal logic, pp. 657-668 inproceedings  
    BibTeX: +
    +@inproceedings{lamp83,
+  author = {L.~Lamport},
+  title = {Information Processing},
+  booktitle = {What good is in temporal logic},
+  publisher = {Elsevier},
+  year = {1983},
+  pages = {657--668}
+}
+
    Lano, K. The B Language and Method, A Guide to Practical Formal Development

    [BibTeX]

    		1996 book  
    BibTeX: +
    +@book{Lano,
+  author = {K.~Lano},
+  title = {The B Language and Method, A Guide to Practical Formal Development},
+  publisher = {Springer-Verlag},
+  year = {1996}
+}
+
    Larsen, K., Steffen, B. & Weise, C. A Constraint Oriented Proof Methodology Based on Modal Transition Systems

    [BibTeX]

    		1995TACAS '95: Proceedings of the First International Workshop on Tools and Algorithms for Construction and Analysis of Systems, pp. 17-40 inproceedings  
    BibTeX: +
    +@inproceedings{693769,
+  author = {K.G~Larsen and B.~Steffen and C.~Weise},
+  title = {A Constraint Oriented Proof Methodology Based on Modal Transition Systems},
+  booktitle = {TACAS '95: Proceedings of the First International Workshop on Tools and Algorithms for Construction and Analysis of Systems},
+  publisher = {Springer-Verlag},
+  year = {1995},
+  pages = {17--40}
+}
+
    Larsen, K.G. & Thomsen, B. A Modal Process Logic

    [BibTeX]

    		1988Third Annual Symposium on Logic in Computer Science, pp. 203-210 inproceedings  
    BibTeX: +
    +@inproceedings{larsen88modal,
+  author = {K.~G.~Larsen and B.~Thomsen},
+  title = {A Modal Process Logic},
+  booktitle = {Third Annual Symposium on Logic in Computer Science},
+  publisher = {IEEE Computer Society},
+  year = {1988},
+  pages = {203-210}
+}
+
    Li, B., Wang, C. & Somenzi, F. Abstraction Refinement in Symbolic Model Checking using Satisfiability as the Only Decision Procedure

    [BibTeX]

    		2005STTT
    Vol. 7(2), pp. 143-155     		article 
    + PDF +
     
    BibTeX: +
    +@article{LiWS05PureSat,
+  author = {B.~Li and C.~Wang and F.~Somenzi},
+  title = {Abstraction Refinement in Symbolic Model Checking using Satisfiability as the Only Decision Procedure},
+  journal = {STTT},
+  year = {2005},
+  volume = {7},
+  number = {2},
+  pages = {143-155}
+}
+
    Lin, B. & Newton, A. Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams

    [BibTeX]

    		1991ICCD '91: Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, pp. 81-85 inproceedings  
    BibTeX: +
    +@inproceedings{lin91implicit,
+  author = {B.~Lin and A.R.~Newton},
+  title = {Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams},
+  booktitle = {ICCD '91: Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors},
+  publisher = {IEEE Computer Society},
+  year = {1991},
+  pages = {81--85}
+}
+
    Loiseaux, C., Graf, S., Sifakis, J., Bouajjani, A. & Bensalem, S. Property Preserving Abstractions for the Verification of Concurrent Systems

    [BibTeX]

    		1995Formal Methods in System Design
    Vol. 6(1), pp. 11-44     		article  
    BibTeX: +
    +@article{Loiseaux,
+  author = {C.~Loiseaux and S.~Graf and J.~Sifakis and A.~Bouajjani and S.~Bensalem},
+  title = {Property Preserving Abstractions for the Verification of Concurrent Systems},
+  journal = {Formal Methods in System Design},
+  publisher = {Kluwer Academic Publisher},
+  year = {1995},
+  volume = {6},
+  number = {1},
+  pages = {11--44}
+}
+
    Long, D.E. Model Checking, Abstraction, and Compositional Verification

    [BibTeX]

    		1993School: Carnegie Mellon University phdthesis 
    + PDF +
     
    BibTeX: +
    +@phdthesis{long93thesis,
+  author = {D.~E.~Long},
+  title = {Model Checking, Abstraction, and Compositional Verification},
+  school = {Carnegie Mellon University},
+  year = {1993}
+}
+
    Malik, S., Wang, A., Brayton, R. & Sangiovanni-Vincentelli, A. Logic Verification using Binary Decision Diagrams in Logic Synthesis Environment

    [Abstract] [BibTeX]

    		1988Proceedings of the IEEE International Conference on Computer Aided Design, ICCAD'88, pp. 6-9 inproceedings  
    Abstract: This paper proposes two heuristics for variable ordering based on the topology of the circuit under study. enumerate item One defines the level of a variable or a gate as follows: $level(root)=0$ and $level(f)=max(level(g))+1$, where the $g$'s are the fathers of $f$. The first heuristics consists in indexing the variables according to the decreasing order of their levels. The justification is that the influence of variables high in the circuit must be computed as soon as possible. item Same as the previous heuristics but respecting modules. Modules are treated in the decreasing order of their depths. The depth of a formula being the maximum depth of its variables. enumerate Experimental results are reported, showing that the second heuristics is very good (on the ICSAS'85 benchmark). Lu
    BibTeX: +
    +@inproceedings{santo,
+  author = {S.~Malik and A.R.~Wang and R.K~Brayton and A.~Sangiovanni-Vincentelli},
+  title = {Logic Verification using Binary Decision Diagrams in Logic Synthesis Environment},
+  booktitle = {Proceedings of the IEEE International Conference on Computer Aided Design, ICCAD'88},
+  year = {1988},
+  pages = {6--9},
+  note = {Santa Clara CA, USA}
+}
+
    Manolios, P. Correctness of Pipelined Machines

    [BibTeX]

    		2000FMCAD '00: Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design, pp. 161-178 inproceedingsURL  
    BibTeX: +
    +@inproceedings{manolios00correctness,
+  author = {P.~Manolios},
+  title = {Correctness of Pipelined Machines},
+  booktitle = {FMCAD '00: Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design},
+  publisher = {Springer-Verlag},
+  year = {2000},
+  pages = {161--178},
+  url = {citeseer.ist.psu.edu/426677.html}
+}
+
    Manolios, P. & Srinivasan, S. Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements

    [BibTeX]

    		2004DATE '04: Proceedings of the conference on Design, Automation and Test in Europe, pp. 168-174 inproceedings  
    BibTeX: +
    +@inproceedings{manolios04web,
+  author = {P.~Manolios and S.K.~Srinivasan},
+  title = {Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements},
+  booktitle = {DATE '04: Proceedings of the conference on Design, Automation and Test in Europe},
+  publisher = {IEEE Computer Society},
+  year = {2004},
+  pages = {168-174}
+}
+
    Manolios, P., Srinivasan, S.K. & Vroon, D. Soha Hassoun (Ed.)Automatic memory reductions for RTL model verification

    [BibTeX]

    		2006ICCAD, pp. 786-793 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/iccad/ManoliosSV06,
+  author = {Panagiotis Manolios and Sudarshan K. Srinivasan and Daron Vroon},
+  title = {Automatic memory reductions for RTL model verification},
+  booktitle = {ICCAD},
+  publisher = {ACM},
+  year = {2006},
+  pages = {786-793}
+}
+
    Mariano, G., Boulanger, J.-L. & Aljer, A. Formalization of Digital Circuits Using the B Method

    [BibTeX]

    		2002CompRail VIII: 8th International Conference on Computer Aided Design, Manufacture and Operation in the Railway and other Advanced Mass Transit Systems inproceedingsURL  
    BibTeX: +
    +@inproceedings{Mariano2002formalization,
+  author = {G.~Mariano and J-L.~Boulanger and A. Aljer},
+  title = {Formalization of Digital Circuits Using the B Method},
+  booktitle = {CompRail VIII: 8th International Conference on Computer Aided Design, Manufacture and Operation in the Railway and other Advanced Mass Transit Systems},
+  year = {2002},
+  url = {http://www.wessex.ac.uk/conferences/2002/cr02/}
+}
+
    Marques-Silva, Jo a.P. & Sakallah, K.A. Boolean satisfiability in electronic design automation

    [BibTeX]

    		2000DAC '00: Proceedings of the 37th Annual Design Automation Conference, pp. 675-680 inproceedingsDOI  
    + PDF +
     
    BibTeX: +
    +@inproceedings{Silva00Sat,
+  author = {Marques-Silva, Jo ao P. and Sakallah, Karem A.},
+  title = {Boolean satisfiability in electronic design automation},
+  booktitle = {DAC '00: Proceedings of the 37th Annual Design Automation Conference},
+  publisher = {ACM},
+  year = {2000},
+  pages = {675--680},
+  doi = {http://doi.acm.org/10.1145/337292.337611}
+}
+
    McMillan, K. Moshe Y. Vardi Alan J. Hu (Ed.)Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking.

    [BibTeX]

    		1998
    Vol. 1427CAV'98: Proceddings of the 10th International Conference on Computer Aided Verification, pp. 110-121     		inproceedings  
    BibTeX: +
    +@inproceedings{mcmillan98tomasulo,
+  author = {K.L.~McMillan},
+  title = {Verification of an Implementation of Tomasulo's Algorithm by Compositional Model Checking.},
+  booktitle = {CAV'98: Proceddings of the 10th International Conference on Computer Aided Verification},
+  publisher = {Springer},
+  year = {1998},
+  volume = {1427},
+  pages = {110-121}
+}
+
    McMillan, K. A Methodology for Hardware Verification Using Compositional Model Checking

    [BibTeX]

    		2000Science of Computer Programming
    Vol. 37(1-3), pp. 279-309     		articleURL 
    + PDF +
     
    BibTeX: +
    +@article{mcmillan00methodology,
+  author = {K.L. McMillan},
+  title = {A Methodology for Hardware Verification Using Compositional Model Checking},
+  journal = {Science of Computer Programming},
+  year = {2000},
+  volume = {37},
+  number = {1--3},
+  pages = {279--309},
+  url = {citeseer.ist.psu.edu/mcmillan99methodology.html}
+}
+
    McMillan, K. Symbolic Model Checking

    [BibTeX]

    		1993 book  
    BibTeX: +
    +@book{mcmillanSMV,
+  author = {K.L.~McMillan},
+  title = {Symbolic Model Checking},
+  publisher = {Kluwer Academics Publishers},
+  year = {1993}
+}
+
    McMillan, K.L. Ed Brinksma and Kim Guldstrand Larsen (Ed.)Applying SAT Methods in Unbounded Symbolic Model Checking

    [BibTeX]

    		2002
    Vol. 2404CAV'02: Proceedings of the 14th International Conference on Computer Aided vVrification, pp. 250-264     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{mcmillan02applyingSat,
+  author = {Kenneth L. McMillan},
+  title = {Applying SAT Methods in Unbounded Symbolic Model Checking},
+  booktitle = {CAV'02: Proceedings of the 14th International Conference on Computer Aided vVrification},
+  publisher = {Springer},
+  year = {2002},
+  volume = {2404},
+  pages = {250-264}
+}
+
    McMillan, K.L. Orna Grumberg (Ed.)A Compositional Rule for Hardware Design Refinement.

    [BibTeX]

    		1997
    Vol. 1254CAV'97: Proceedings of the 9th International Conference on Computer Aided Verification, pp. 24-35     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/cav/McMillan97,
+  author = {Kenneth L. McMillan},
+  title = {A Compositional Rule for Hardware Design Refinement.},
+  booktitle = {CAV'97: Proceedings of the 9th International Conference on Computer Aided Verification},
+  publisher = {Springer},
+  year = {1997},
+  volume = {1254},
+  pages = {24-35}
+}
+
    Memmi, G. Méthodes d'analyse des réseaux de Petri, réseaux à files et application aux systèmes temps-réel

    [BibTeX]

    		1983School: Université Paris-6 phdthesis  
    BibTeX: +
    +@phdthesis{memmi:thesis,
+  author = {G.~Memmi},
+  title = {Méthodes d'analyse des réseaux de Petri, réseaux à files et application aux systèmes temps-réel},
+  school = {Université Paris-6},
+  year = {1983}
+}
+
    Milner, R. Communication and Concurrency

    [BibTeX]

    		1989 book  
    BibTeX: +
    +@book{Mil89,
+  author = {R.~Milner},
+  title = {Communication and Concurrency},
+  publisher = {Prentice Hall},
+  year = {1989}
+}
+
    Milner, R. An Algebraic Definition of Simulation Between

    Programs.

    [BibTeX]

    		1971IJCAI'71: Proceedings of the 2nd International Joint Conference on Artificial Intelligence, pp. 481-489 inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/ijcai/Milner71,
+  author = {R.~Milner},
+  title = {An Algebraic Definition of Simulation Between
     Programs.},
+  booktitle = {IJCAI'71: Proceedings of the 2nd International Joint Conference on Artificial Intelligence},
+  year = {1971},
+  pages = {481-489}
+}
+
    Minato, S., Ishiura, N. & Yajima, S. L.J.M Claesen (Ed.)Shared Binary Decision Diagrams with Attributed Edges for Efficient Boolean Function Manipulation

    [Abstract] [BibTeX]

    		1990Proceedings of the 27th ACM/IEEE Design Automation Conference, DAC'90, pp. 52-57 inproceedings  
    Abstract: This paper is the first one in which management of BDD nodes via a hash table is proposed (and thus the reduction operation is suppressed). Then, various labelling of edges are discussed: first, the flag $+/-$ already proposed by Billon and Madre teBil87,MB88. Second, another flag so-called input inverter, is proposed. It transforms $ite(x,F,G)$ into $ite(neg x,F,G)=ite(x,G,F)$. Canonicity is maintained by keeping only nodes such that $Fdon't care parts of circuits is proposed. It consists in using a second variable $neg x_1 wedge neg x_2 rightarrow neg x$, $x_1 wedge x_2 rightarrow x$, otherwise don't care. Finally, experimental results are reported.
    BibTeX: +
    +@inproceedings{minato,
+  author = {S.~Minato and N.~Ishiura and S.~Yajima},
+  title = {Shared Binary Decision Diagrams with Attributed Edges for Efficient Boolean Function Manipulation},
+  booktitle = {Proceedings of the 27th ACM/IEEE Design Automation Conference, DAC'90},
+  year = {1990},
+  pages = {52--57}
+}
+
    Miner, A. & Ciardo, G. Efficient Reachability Set Generation and Storage Using Decision Diagrams

    [BibTeX]

    		1999
    Vol. 1639Proc. of ICATPN'99, pp. 6-25     		inproceedings  
    BibTeX: +
    +@inproceedings{MC99,
+  author = {A.S. Miner and G. Ciardo},
+  title = {Efficient Reachability Set Generation and Storage Using Decision Diagrams},
+  booktitle = {Proc. of ICATPN'99},
+  publisher = {Springer Verlag},
+  year = {1999},
+  volume = {1639},
+  pages = {6--25}
+}
+
    Miskov-Zivanov, N. & Marculescu, D. Circuit Reliability Analysis Using Symbolic Techniques

    [BibTeX]

    		2006IEEE Transaction on CAD of Integrated Circuits and Systems
    Vol. 25(12), pp. 2638-2649     		article  
    BibTeX: +
    +@article{Miskov-ZivanovM06,
+  author = {N.~Miskov-Zivanov and D.~Marculescu},
+  title = {Circuit Reliability Analysis Using Symbolic Techniques},
+  journal = {IEEE Transaction on CAD of Integrated Circuits and Systems},
+  year = {2006},
+  volume = {25},
+  number = {12},
+  pages = {2638-2649}
+}
+
    Moore, E. Gedanken-experiments on Sequential Machines

    [BibTeX]

    		1956Automata Studies, Annals of Mathematical Studies
    Vol. 34, pp. 129 – 153     		article  
    BibTeX: +
    +@article{mooremachine,
+  author = {E.F.~Moore},
+  title = {Gedanken-experiments on Sequential Machines},
+  journal = {Automata Studies, Annals of Mathematical Studies},
+  year = {1956},
+  volume = {34},
+  pages = {129 – 153}
+}
+
    Morin-Allory, K. & Borrione, D. Georges G. E. Gielen (Ed.)Proven Correct Monitors from PSL Specifications.

    [BibTeX]

    		2006DATE'06: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1246-1251 inproceedings  
    BibTeX: +
    +@inproceedings{Morin-AlloryB06,
+  author = {K.~Morin-Allory and D.~Borrione},
+  title = {Proven Correct Monitors from PSL Specifications.},
+  booktitle = {DATE'06: Proceedings of the Conference on Design, Automation and Test in Europe},
+  publisher = {European Design and Automation Association, Leuven, Belgium},
+  year = {2006},
+  pages = {1246-1251}
+}
+
    Moskewicz, M., Madigan, C., Zhao, Y., Zhang, L. & Malik, S. Chaff: Engineering an Efficient SAT Solver

    [BibTeX]

    		2001DAC'01: Proceedings of the 38th Design Automation Conference, pp. 530-535 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/dac/MoskewiczMZZM01,
+  author = {M.W.~Moskewicz and C.F.~Madigan and Y.~Zhao and L.~Zhang and S.~Malik},
+  title = {Chaff: Engineering an Efficient SAT Solver},
+  booktitle = {DAC'01: Proceedings of the 38th Design Automation Conference},
+  publisher = {ACM},
+  year = {2001},
+  pages = {530-535}
+}
+
    Moundanos, D., Abraham, J. & Hoskote, Y. Abstraction Techniques for Validation Coverage Analysis and Test Generation

    [BibTeX]

    		1998IEEE Trans. Computers
    Vol. 47(1), pp. 2-14     		article  
    BibTeX: +
    +@article{DBLP:journals/tc/MoundanosAH98,
+  author = {D.~Moundanos and J.A.~Abraham and Y.V.~Hoskote},
+  title = {Abstraction Techniques for Validation Coverage Analysis and Test Generation},
+  journal = {IEEE Trans. Computers},
+  year = {1998},
+  volume = {47},
+  number = {1},
+  pages = {2-14}
+}
+
    de Moura, L.M. & Bjørner, N. Marcel Vinicius Medeiros Oliveira and Jim Woodcock (Ed.)Satisfiability Modulo Theories: An Appetizer

    [BibTeX]

    		2009
    Vol. 5902SBMF, pp. 23-36     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/sbmf/MouraB09,
+  author = {Leonardo Mendonça de Moura and Nikolaj Bjørner},
+  title = {Satisfiability Modulo Theories: An Appetizer},
+  booktitle = {SBMF},
+  publisher = {Springer},
+  year = {2009},
+  volume = {5902},
+  pages = {23-36}
+}
+
    de Moura, L.M. & Bjørner, N. C. R. Ramakrishnan and Jakob Rehof (Ed.)Z3: An Efficient SMT Solver

    [BibTeX]

    		2008
    Vol. 4963TACAS, pp. 337-340     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/tacas/MouraB08,
+  author = {Leonardo Mendonça de Moura and Nikolaj Bjørner},
+  title = {Z3: An Efficient SMT Solver},
+  booktitle = {TACAS},
+  publisher = {Springer},
+  year = {2008},
+  volume = {4963},
+  pages = {337-340}
+}
+
    Moy, M., Maraninchi, F. & Maillet, L. LusSy: An open tool for the analysis of systems-on-a-chip at the transaction level

    [BibTeX]

    		2006Design Automation for Embedded Systems
    Vol. 10(2-3), pp. 73-104     		articleDOI   
    BibTeX: +
    +@article{moy06lussy,
+  author = {M.~Moy and F.~Maraninchi and L.~Maillet},
+  title = {LusSy: An open tool for the analysis of systems-on-a-chip at the transaction level},
+  journal = {Design Automation for Embedded Systems},
+  year = {2006},
+  volume = {10},
+  number = {2-3},
+  pages = {73--104},
+  doi = {http://dx.doi.org/10.1007/s10617-006-9044-6}
+}
+
    Namjoshi, K. A Simple Characterization of Stuttering Bisimulation

    [BibTeX]

    		1997LNCS, Proceedings of the 17th Conference on Foundations of Software Technology an Theoretical Computer Science
    Vol. 1346, pp. 284-296     		articleURL  
    BibTeX: +
    +@article{namjoshi97simple,
+  author = {K.S.~Namjoshi},
+  title = {A Simple Characterization of Stuttering Bisimulation},
+  journal = {LNCS, Proceedings of the 17th Conference on Foundations of Software Technology an Theoretical Computer Science},
+  year = {1997},
+  volume = {1346},
+  pages = {284--296},
+  url = {citeseer.ist.psu.edu/namjoshi97simple.html}
+}
+
    Namjoshi, K.S. Warren A. Hunt Jr. and Fabio Somenzi (Ed.)Abstraction for Branching Time Properties.

    [BibTeX]

    		2003
    Vol. 2725CAV, pp. 288-300     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/cav/Namjoshi03,
+  author = {Kedar S. Namjoshi},
+  title = {Abstraction for Branching Time Properties.},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {2003},
+  volume = {2725},
+  pages = {288-300}
+}
+
    Namjoshi, K.S. & Kurshan, R.P. Syntactic Program Transformations for Automatic Abstraction

    [BibTeX]

    		2000
    Vol. 1855Proceedings of the 12th International Conference on Computer Aided Verification, pp. 435-449     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{namjoshiK00syntactic,
+  author = {K.~S.~Namjoshi and R.~P.~Kurshan},
+  title = {Syntactic Program Transformations for Automatic Abstraction},
+  booktitle = {Proceedings of the 12th International Conference on Computer Aided Verification},
+  publisher = {Springer-Verlag},
+  year = {2000},
+  volume = {1855},
+  pages = {435--449}
+}
+
    Nanshi, K. & Somenzi, F. Improved Visibility in One-to-Many Trace Concretization

    [BibTeX]

    		2008DATE, pp. 819-824 inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/date/NanshiS08,
+  author = {K.~Nanshi and F.~Somenzi},
+  title = {Improved Visibility in One-to-Many Trace Concretization},
+  booktitle = {DATE},
+  year = {2008},
+  pages = {819-824}
+}
+
    Nanshi, K. & Somenzi, F. Ellen Sentovich (Ed.)Guiding simulation with increasingly refined abstract traces

    [BibTeX]

    		2006DAC, pp. 737-742 inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/dac/NanshiS06,
+  author = {K.~Nanshi and F.~Somenzi},
+  title = {Guiding simulation with increasingly refined abstract traces},
+  booktitle = {DAC},
+  publisher = {ACM},
+  year = {2006},
+  pages = {737-742}
+}
+
    Nejati, S., Gurfinkel, A. & Chechik, M. Bernhard K. Aichernig and Bernhard Beckert (Ed.)Stuttering Abstraction for Model Checking

    [BibTeX]

    		2005SEFM, pp. 311-320 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{nejati05stutering,
+  author = {Shiva Nejati and Arie Gurfinkel and Marsha Chechik},
+  title = {Stuttering Abstraction for Model Checking},
+  booktitle = {SEFM},
+  publisher = {IEEE Computer Society},
+  year = {2005},
+  pages = {311-320}
+}
+
    Nicola, R.D. & Vaandrager, F. Three Logics for Branching Bisimulation.

    [BibTeX]

    		1995Journal of the ACM
    Vol. 42(2), pp. 458-487     		article  
    BibTeX: +
    +@article{nicolaV95,
+  author = {R.~De~Nicola and F.W.~Vaandrager},
+  title = {Three Logics for Branching Bisimulation.},
+  journal = {Journal of the ACM},
+  year = {1995},
+  volume = {42},
+  number = {2},
+  pages = {458-487}
+}
+
    On-Chip Bus Development Working Group Virtual Component Interface Standard (VCI).

    [BibTeX]

    		2000
    Vol. version 2     		manual  
    BibTeX: +
    +@manual{VCI_spec,
+  author = {On-Chip Bus Development Working Group},
+  title = {Virtual Component Interface Standard (VCI).},
+  year = {2000},
+  volume = {version 2}
+}
+
    Open Microprocessors System Initiatives OMI324: PI-Bus Standard Specification

    [BibTeX]

    		1994 manual 
    + PDF +
     
    BibTeX: +
    +@manual{PI_proto,
+  author = {Open Microprocessors System Initiatives},
+  title = {OMI324: PI-Bus Standard Specification},
+  year = {1994}
+}
+
    Ossima Khéba, J. Spécification des Wrappers AHB/VCI

    [BibTeX]

    		2003School: Universitée Pierre et Marie Curie techreport  
    BibTeX: +
    +@techreport{specamba03,
+  author = {J.~Ossima Khéba},
+  title = {Spécification des Wrappers AHB/VCI},
+  school = {Universitée Pierre et Marie Curie},
+  year = {2003}
+}
+
    Ossima Khéba, J. Les Wrappers PI/VCI et Etude de Faisabilité des Wrappers AMBA/VCI

    [BibTeX]

    		2002School: Universitée Pierre et Marie Curie techreport  
    BibTeX: +
    +@techreport{joel02,
+  author = {J.~Ossima Khéba},
+  title = {Les Wrappers PI/VCI et Etude de Faisabilité des Wrappers AMBA/VCI},
+  school = {Universitée Pierre et Marie Curie},
+  year = {2002}
+}
+
    Owre, S.., Rushby, J.. M.. & Shankar, N.. Deepak Kapur (Ed.)PVS: A Prototype Verification System

    [BibTeX]

    		1992
    Vol. 60711th International Conference on Automated Deduction (CADE), pp. 748-752     		inproceedingsURL  
    BibTeX: +
    +@inproceedings{cade92-pvs,
+  author = {S. Owre and J. M. Rushby and and N. Shankar},
+  title = {PVS: A Prototype Verification System},
+  booktitle = {11th International Conference on Automated Deduction (CADE)},
+  publisher = {Springer-Verlag},
+  year = {1992},
+  volume = {607},
+  pages = {748--752},
+  url = {http://www.csl.sri.com/papers/cade92-pvs/}
+}
+
    Park, D. Peter Deussen (Ed.)Concurrency and Automata on Infinite Sequences.

    [BibTeX]

    		1981
    Vol. 104Proceedings of the 5th GI-Conference on Theoretical Computer Science, pp. 167-183     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/tcs/Park81,
+  author = {D.~Park},
+  title = {Concurrency and Automata on Infinite Sequences.},
+  booktitle = {Proceedings of the 5th GI-Conference on Theoretical Computer Science},
+  publisher = {Springer},
+  year = {1981},
+  volume = {104},
+  pages = {167-183}
+}
+
    Pasareanu, C., Dwyer, M. & Huth, M. Assume-Guarantee Model Checking of Software: A Comparative Case Study

    [BibTeX]

    		1999Proceedings of the 5th and 6th International SPIN Workshops on Theoretical and Practical Aspects of SPIN Model Checking, pp. 168-183 inproceedings  
    BibTeX: +
    +@inproceedings{pasareanu99assume,
+  author = {C.S.~Pasareanu and M.B.~Dwyer and M.~Huth},
+  title = {Assume-Guarantee Model Checking of Software: A Comparative Case Study},
+  booktitle = {Proceedings of the 5th and 6th International SPIN Workshops on Theoretical and Practical Aspects of SPIN Model Checking},
+  publisher = {Springer-Verlag},
+  year = {1999},
+  pages = {168--183}
+}
+
    Passerone, R., de Alfaro, L., Henzinger, T. & Sangiovanni-Vincentelli, A. Convertibility Verification and Converter Synthesis: Two Faces of The Same Coin

    [BibTeX]

    		2002ICCAD '02: Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design, pp. 132-139 inproceedingsDOI  
    + PDF +
     
    BibTeX: +
    +@inproceedings{passerone02convertibility,
+  author = {R.~Passerone and L.~de Alfaro and T.A.~Henzinger and A.L.~Sangiovanni-Vincentelli},
+  title = {Convertibility Verification and Converter Synthesis: Two Faces of The Same Coin},
+  booktitle = {ICCAD '02: Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design},
+  publisher = {ACM Press},
+  year = {2002},
+  pages = {132--139},
+  doi = {http://doi.acm.org/10.1145/774572.774592}
+}
+
    Passerone, R., Rowson, J. & Sangiovanni-Vincentelli, A. Automatic Synthesis of Interfaces Between

    Incompatible Protocols.

    [BibTeX]

    		1998DAC'98: Proceedings of the 35th Conference on Design Automation, pp. 8-13 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/dac/PasseroneRS98,
+  author = {R.~Passerone and J.A.~Rowson and A.L.~Sangiovanni-Vincentelli},
+  title = {Automatic Synthesis of Interfaces Between
     Incompatible Protocols.},
+  booktitle = {DAC'98: Proceedings of the 35th Conference on Design Automation},
+  year = {1998},
+  pages = {8-13}
+}
+
    Pastor, E., Roig, O., Cortadella, J. & Badia, R. Petri Net analysis using Boolean manipulation

    [BibTeX]

    		1994
    Vol. 815Proc. of ICATPN'94, pp. 416-435     		inproceedings  
    BibTeX: +
    +@inproceedings{PRCB94,
+  author = {E. Pastor and O. Roig and J. Cortadella and R.M. Badia},
+  title = {Petri Net analysis using Boolean manipulation},
+  booktitle = {Proc. of ICATPN'94},
+  publisher = {Springer Verlag},
+  year = {1994},
+  volume = {815},
+  pages = {416--435}
+}
+
    Patterson, D. & Hennessy, J. Computer Organization and Design: The Hardware/Software Interface, Third Edition (The Morgan Kaufmann Series in Computer Architecture and Design) (The ... Series in Computer Architecture and Design)

    [Abstract] [BibTeX]

    		2004Paperback bookURL  
    Abstract: In addition to thoroughly updating every aspect of the text to reflect the most current computing technology, the third edition

    *Uses standard 32-bit MIPS 32 as the primary teaching ISA.
    *Presents the assembler-to-HLL translations in both C and Java.
    *Highlights the latest developments in architecture in Real Stuff sections:

    + Intel IA-32
    + Power PC 604
    + Googles PC cluster
    + Pentium P4
    + SPEC CPU2000 benchmark suite for processors
    + SPEC Web99 benchmark for web servers
    + EEMBC benchmark for embedded systems
    + AMD Opteron memory hierarchy
    + AMD vs. 1A-64


    New support for distinct course goals

    Many of the adopters who have used our book throughout its two editions are refining their courses with a greater hardware or software focus. We have provided new material to support these course goals:

    New material to support a Hardware Focus

    +Using logic design conventions
    +Designing with hardware description languages
    +Advanced pipelining
    +Designing with FPGAs
    +HDL simulators and tutorials
    +Xilinx CAD tools

    New material to support a Software Focus

    +How compilers Work
    +How to optimize compilers
    +How to implement object oriented languages
    +MIPS simulator and tutorial
    +History sections on programming languages, compilers, operating systems and databases

    Whats New in the Third Edition

    New pedagogical features

    Understanding Program Performance
    -Analyzes key performance issues from the programmers perspective

    Check Yourself Questions
    -Helps students assess their understanding of key points of a section

    Computers In the Real World
    -Illustrates the diversity of applications of computing technology beyond traditional desktop and servers

    For More Practice
    -Provides students with additional problems they can tackle

    In More Depth
    -Presents new information and challenging exercises for the advanced student


    New reference features

    Highlighted glossary terms and definitions appear on the book page, as bold-faced entries in the index, and as a separate and searchable reference on the CD.

    A complete index of the material in the book and on the CD appears in the printed index and the CD includes a fully searchable version of the same index.

    Historical Perspectives and Further Readings have been updated and expanded to include the history of software R&D.

    CD-Library provides materials collected from the web which directly support the text.

    On the CD

    CD-Bars: Full length sections that are introduced in the book and presented on the CD

    CD-Appendixes: The entire set of appendixes

    CD-Library: Materials collected from the web which directly support the text

    CD-Exercises: For More Practice provides exercises and solutions for self-study
    In More Depth presents new information and challenging exercises for the advanced or curious student

    Glossary: Terms that are defined in the text are collected in this searchable reference

    Further Reading: References are organized by the chapter they support

    Software: HDL simulators, MIPS simulators, and FPGA design tools

    Tutorials: SPIM, Verilog, and VHDL

    Additional Support: Processor Models, Labs, Homeworks, Index covering the book and CD contents

    Instructor Support

    + Instructor Support is provided in a password-protected site to adopters who request the password from our sales representative
    + Solutions to all the exercises
    + Figures from the book in a number of formats
    + Lecture slides prepared by the authors and other instructors
    + Lecture notes

    For instructor resources click on the grey "companion site" button found on the right side of this page.
    This new edition represents a major revision.
    New to this edition:

    * Entire Text has been updated to reflect new technology
    * 70% new exercises.
    * Includes a CD loaded with software, projects and exercises to support courses using a number of tools
    * A new interior design presents defined terms in the margin for quick reference
    * A new feature, Understanding Program Performance focuses on performance from the programmers perspective
    * Two sets of exercises and solutions, For More Practice and In More Depth, are included on the CD
    * Check Yourself questions help students check their understanding of major concepts
    * Computers In the Real World feature illustrates the diversity of uses for information technology
    *More detail below...
    BibTeX: +
    +@book{hennessypattersonbook,
+  author = {D.A.~Patterson and J.L~Hennessy},
+  title = {Computer Organization and Design: The Hardware/Software Interface, Third Edition (The Morgan Kaufmann Series in Computer Architecture and Design) (The ... Series in Computer Architecture and Design)},
+  publisher = {Morgan Kaufmann},
+  year = {2004},
+  edition = {third},
+  url = {http://www.amazon.co.uk/exec/obidos/ASIN/1558606041/citeulike-21}
+}
+
    Peng, H. Improving Compositional Verification through Environment Synthesis and Syntactic Model Reduction

    [BibTeX]

    		2002School: Dept. of Electrical and Computer Engenering, Concordia University, Montreal, Quebec, Canada phdthesis  
    BibTeX: +
    +@phdthesis{peng02thesis,
+  author = {H.~Peng},
+  title = {Improving Compositional Verification through Environment Synthesis and Syntactic Model Reduction},
+  school = {Dept. of Electrical and Computer Engenering, Concordia University, Montreal, Quebec, Canada},
+  year = {2002}
+}
+
    Peng, H., Mokhtari, Y. & Tahar, S. Environment Synthesis for Compositional Model Checking.

    [BibTeX]

    		2002ICCD'02: Proceedings of the 20th International Conference on Computer Design, pp. 70- inproceedings  
    BibTeX: +
    +@inproceedings{peng02tableau,
+  author = {H.~Peng and Y.~Mokhtari and S.~Tahar},
+  title = {Environment Synthesis for Compositional Model Checking.},
+  booktitle = {ICCD'02: Proceedings of the 20th International Conference on Computer Design},
+  publisher = {IEEE Computer Society},
+  year = {2002},
+  pages = {70-}
+}
+
    Peng, H., Tahar, S. & Khendek, F. Comparison of SPIN and VIS for Protocol Verification.

    [BibTeX]

    		2003International Journal on Software Tools for Technology Transfer (STTT)
    Vol. 4(2), pp. 234-245     		article  
    BibTeX: +
    +@article{peng03comparison,
+  author = {H.~Peng and S.~Tahar and F.~Khendek},
+  title = {Comparison of SPIN and VIS for Protocol Verification.},
+  journal = {International Journal on Software Tools for Technology Transfer (STTT)},
+  publisher = {Springer},
+  year = {2003},
+  volume = {4},
+  number = {2},
+  pages = {234-245}
+}
+
    Pevtschin, V. The Open Microprocessor Systems Initiative: A Strategy Towards Integrated System Design

    [BibTeX]

    		1995RSP'95: Proceddings of the 6th IEEE International Workshop on Rapid System Prototyping, pp. 2-11 inproceedingsDOI   
    BibTeX: +
    +@inproceedings{omi95rsp,
+  author = {V. Pevtschin},
+  title = {The Open Microprocessor Systems Initiative: A Strategy Towards Integrated System Design},
+  booktitle = {RSP'95: Proceddings of the 6th IEEE International Workshop on Rapid System Prototyping},
+  year = {1995},
+  pages = {2--11},
+  doi = {http://doi.ieeecomputersociety.org/10.1109/IWRSP.1995.518564}
+}
+
    Plath, M. & Ryan, M. R. Berghammer and Y. Lakhnech (Ed.)SFI: a Feature Integration Tool

    [BibTeX]

    		1999Tool Support for System Specification, Development and Verification, pp. 201-216 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{plath99sfi,
+  author = {M.C.~Plath and M.D.~Ryan},
+  title = {SFI: a Feature Integration Tool},
+  booktitle = {Tool Support for System Specification, Development and Verification},
+  publisher = {Springer},
+  year = {1999},
+  pages = {201--216}
+}
+
    Plath, M. & Ryan, M. Feature Integration using a Feature Construct

    [BibTeX]

    		2001Science of Computer Programming
    Vol. 41(1), pp. 53-84     		articleDOI   
    BibTeX: +
    +@article{plath01feature,
+  author = {M.~Plath and M.~Ryan},
+  title = {Feature Integration using a Feature Construct},
+  journal = {Science of Computer Programming},
+  publisher = {Elsevier North-Holland, Inc.},
+  year = {2001},
+  volume = {41},
+  number = {1},
+  pages = {53--84},
+  doi = {http://dx.doi.org/10.1016/S0167-6423(00)00018-6}
+}
+
    Plath, M. & Ryan, M. A feature construct for Promela

    [BibTeX]

    		1998SPIN'98: Proceedings of the 4th SPIN workshop inproceedingsURL  
    BibTeX: +
    +@inproceedings{plath98feature,
+  author = {M.C.~Plath and M.D.~Ryan},
+  title = {A feature construct for Promela},
+  booktitle = {SPIN'98: Proceedings of the 4th SPIN workshop},
+  year = {1998},
+  url = {citeseer.ist.psu.edu/plath98feature.html}
+}
+
    Purandare, M., Wahl, T. & Kroening, D. Strengthening Properties Using on Refinement

    [BibTeX]

    		2009DATE '09: Proceedings of the conference on Design, Automation and Test in Europe, pp. 1692-1697 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{Purandare09Strengthening,
+  author = {M. Purandare and T. Wahl and D. Kroening},
+  title = {Strengthening Properties Using on Refinement},
+  booktitle = {DATE '09: Proceedings of the conference on Design, Automation and Test in Europe},
+  year = {2009},
+  pages = {1692-1697}
+}
+
    Pétrot, F. Intégration des systèmes matériel/logiciel

    [BibTeX]

    		2003School: Universitée Pierre et Marie Curie mastersthesis  
    BibTeX: +
    +@mastersthesis{fredHDR,
+  author = {Pétrot, F.},
+  title = {Intégration des systèmes matériel/logiciel},
+  school = {Universitée Pierre et Marie Curie},
+  year = {2003}
+}
+
    Rasiowa, H. Studies in Logics and the Foundations of Mathematics (Ed.)An Algebraic Approach to Non-Classicals Logis

    [BibTeX]

    		1978 book  
    BibTeX: +
    +@book{rasiowa78algebra,
+  author = {H.~Rasiowa},
+  title = {An Algebraic Approach to Non-Classicals Logis},
+  year = {1978}
+}
+
    Ravi, K. & Somenzi, F. Kurt Jensen and Andreas Podelski (Ed.)Minimal Assignments for Bounded Model Checking

    [BibTeX]

    		2004
    Vol. 2988TACAS'04: Proceedings of 10th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, pp. 31-45     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{RaviS04MinimalAssig,
+  author = {K.~Ravi and F.~Somenzi},
+  title = {Minimal Assignments for Bounded Model Checking},
+  booktitle = {TACAS'04: Proceedings of 10th International Conference on Tools and Algorithms for the Construction and Analysis of Systems},
+  publisher = {Springer},
+  year = {2004},
+  volume = {2988},
+  pages = {31-45}
+}
+
    Roorda, J.-W. & Claessen, K. Thomas Ball and Robert B. Jones (Ed.)SAT-Based Assistance in Abstraction Refinement for Symbolic Trajectory Evaluation

    [BibTeX]

    		2006
    Vol. 4144CAV, pp. 175-189     		inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/cav/RoordaC06,
+  author = {Jan-Willem Roorda and Koen Claessen},
+  title = {SAT-Based Assistance in Abstraction Refinement for Symbolic Trajectory Evaluation},
+  booktitle = {CAV},
+  year = {2006},
+  volume = {4144},
+  pages = {175-189}
+}
+
    Roux, C. & Encrenaz, E. Daniel Geist and Enrico Tronci (Ed.)CTL May Be Ambiguous When Model Checking Moore Machines.

    [BibTeX]

    		2003
    Vol. 2860CHARME, pp. 164-169     		inproceedingsURL 
    + PDF +
     
    BibTeX: +
    +@inproceedings{roux03ctl,
+  author = {C.~Roux and E.~Encrenaz},
+  title = {CTL May Be Ambiguous When Model Checking Moore Machines.},
+  booktitle = {CHARME},
+  publisher = {Springer},
+  year = {2003},
+  volume = {2860},
+  pages = {164-169},
+  url = {http://springerlink.metapress.com/openurl.asp?genre=article&issn=0302-9743&volume=2860&spage=164}
+}
+
    Roychoudhury, A., Mitra, T. & Karri, S.R. Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol.

    [BibTeX]

    		2003DATE, pp. 10828-10833 inproceedings  
    BibTeX: +
    +@inproceedings{DBLP:conf/date/RoychoudhuryMK03,
+  author = {Abhik Roychoudhury and Tulika Mitra and S. R. Karri},
+  title = {Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol.},
+  booktitle = {DATE},
+  publisher = {IEEE Computer Society},
+  year = {2003},
+  pages = {10828-10833}
+}
+
    Sawada, J. & Hunt, W. Trace Table Based Approach for Pipeline Microprocessor Verification

    [BibTeX]

    		1997CAV'97: Proceedings of the 9th International Conference on Computer Aided Verification, pp. 364-375 inproceedings  
    BibTeX: +
    +@inproceedings{sawada97trace,
+  author = {J.~Sawada and W.A.~Hunt},
+  title = {Trace Table Based Approach for Pipeline Microprocessor Verification},
+  booktitle = {CAV'97: Proceedings of the 9th International Conference on Computer Aided Verification},
+  publisher = {Springer-Verlag LNCS 1254},
+  year = {1997},
+  pages = {364--375}
+}
+
    Schickel, M., Nimbler, V., Braun, M. & Eveking, H. On Consistency and Completness of Property-Sets~: Exploiting the Property-Based Design Process

    [BibTeX]

    		2006FDL'06: Proceeding of Forum on specification and Design Languages inproceedings  
    BibTeX: +
    +@inproceedings{eveking06fdl,
+  author = {M.~Schickel and V.~Nimbler and M.~Braun and H.~Eveking},
+  title = {On Consistency and Completness of Property-Sets~: Exploiting the Property-Based Design Process},
+  booktitle = {FDL'06: Proceeding of Forum on specification and Design Languages},
+  year = {2006}
+}
+
    Seger, C.-J.H. & Bryant, R.E. Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories

    [BibTeX]

    		1995Formal Methods in System Design
    Vol. 6(2), pp. 147-189     		article  
    BibTeX: +
    +@article{DBLP:journals/fmsd/SegerB95,
+  author = {Carl-Johan H. Seger and Randal E. Bryant},
+  title = {Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories},
+  journal = {Formal Methods in System Design},
+  year = {1995},
+  volume = {6},
+  number = {2},
+  pages = {147-189}
+}
+
    Sharygina, N., Tonetta, S. & Tsitovich, A. An abstraction refinement approach combining precise and approximated techniques

    [BibTeX]

    		2012International Journal on Software Tools for Technology Transfer (STTT)
    Vol. 14, pp. 1-14     		articleURL 
    + PDF +
     
    BibTeX: +
    +@article{Sharygin2012,
+  author = {Natasha Sharygina and Stefano Tonetta and Aliaksei Tsitovich},
+  title = {An abstraction refinement approach combining precise and approximated techniques},
+  journal = {International Journal on Software Tools for Technology Transfer (STTT)},
+  publisher = {Springer},
+  year = {2012},
+  volume = {14},
+  pages = {1-14},
+  url = {http://dx.doi.org/10.1007/s10009-011-0185-y}
+}
+
    Sherman, D. & Magnier, N. Bernhard Steffen (Ed.)Factotum: Automatic and Systematic Sharing Support for Systems Analyzers

    [BibTeX]

    		1982Tools and Algorithms for the Construction and Analysis of Systems (TACAS'98) inproceedings  
    BibTeX: +
    +@inproceedings{magnier-sherman:factotum,
+  author = {D.J Sherman and N. Magnier},
+  title = {Factotum: Automatic and Systematic Sharing Support for Systems Analyzers},
+  booktitle = {Tools and Algorithms for the Construction and Analysis of Systems (TACAS'98)},
+  publisher = {Springer-Verlag LNCS 1384},
+  year = {1982}
+}
+
    Shoham, S. & Grumberg, O. Andreas Podelski Kurt Jensen (Ed.)Monotonic Abstraction-Refinement for CTL.

    [BibTeX]

    		2004
    Vol. 2988TACAS'04: Proceedings of the 10th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, pp. 546-560     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{shohamG04monotonic,
+  author = {S.~Shoham and O.~Grumberg},
+  title = {Monotonic Abstraction-Refinement for CTL.},
+  booktitle = {TACAS'04: Proceedings of the 10th International Conference on Tools and Algorithms for the Construction and Analysis of Systems},
+  publisher = {Springer},
+  year = {2004},
+  volume = {2988},
+  pages = {546-560}
+}
+
    Shoham, S. & Grumberg, O. 3-Valued Abstraction: More Precision at Less Cost

    [BibTeX]

    		2006LICS '06: proceedings of the 21st Annual IEEE Symposium on Logic in Computer Science, pp. 399-410 inproceedingsDOI   
    BibTeX: +
    +@inproceedings{shoham06precision,
+  author = {S.~Shoham and O.~Grumberg},
+  title = {3-Valued Abstraction: More Precision at Less Cost},
+  booktitle = {LICS '06: proceedings of the 21st Annual IEEE Symposium on Logic in Computer Science},
+  publisher = {IEEE Computer Society},
+  year = {2006},
+  pages = {399--410},
+  doi = {http://dx.doi.org/10.1109/LICS.2006.5}
+}
+
    Smith, A., Veneris, A.G., Ali, M.F. & Viglas, A. Fault diagnosis and logic debugging using Boolean satisfiability

    [BibTeX]

    		2005IEEE Trans. on CAD of Integrated Circuits and Systems
    Vol. 24(10), pp. 1606-1621     		article  
    BibTeX: +
    +@article{DBLP:journals/tcad/SmithVAV05,
+  author = {Alexander Smith and Andreas G. Veneris and Moayad Fahim Ali and Anastasios Viglas},
+  title = {Fault diagnosis and logic debugging using Boolean satisfiability},
+  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
+  year = {2005},
+  volume = {24},
+  number = {10},
+  pages = {1606-1621}
+}
+
    Somenzi, F. & Bloem, R. E.A. Emerson and A.P. Sistla (Ed.)Efficient Büchi Automata from LTL Formulae.

    [BibTeX]

    		2000
    Vol. 1855CAV, pp. 248-263     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{somenzi00efficient,
+  author = {F.~Somenzi and R.~Bloem},
+  title = {Efficient Büchi Automata from LTL Formulae.},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {2000},
+  volume = {1855},
+  pages = {248-263}
+}
+
    Sparsø, J. Asynchronous Circuit Design - A Tutorial

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    		2001Chapters 1-8 in ''Principles of asynchronous circuit design - A systems Perspective'', pp. 1-152 incollectionURL  
    BibTeX: +
    +@incollection{IMM2001-0855,
+  author = {J. Sparsø},
+  title = {Asynchronous Circuit Design - A Tutorial},
+  booktitle = {Chapters 1-8 in ''Principles of asynchronous circuit design - A systems Perspective''},
+  publisher = {Kluwer Academic Publishers},
+  year = {2001},
+  pages = {1-152},
+  url = {http://www2.imm.dtu.dk/pubdb/p.php?855}
+}
+
    Staber, S., Fey, Gö., Bloem, R. & Drechsler, R. Eyal Bin and Avi Ziv and Shmuel Ur (Ed.)Automatic Fault Localization for Property Checking

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    		2006
    Vol. 4383Haifa Verification Conference, pp. 50-64     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{StaberFBD06,
+  author = {Stefan Staber and Görschwin Fey and Roderick Bloem and Rolf Drechsler},
+  title = {Automatic Fault Localization for Property Checking},
+  booktitle = {Haifa Verification Conference},
+  publisher = {Springer},
+  year = {2006},
+  volume = {4383},
+  pages = {50-64}
+}
+
    STERIA Technologie de l'information Atelier B, Manuel Utilisateur

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    BibTeX: +
    +@manual{AtelierB,
+  author = {STERIA Technologie de l'information},
+  title = {Atelier B, Manuel Utilisateur},
+  year = {1998}
+}
+
    Sülflow, A., Fey, Gö., Braunstein, Cé., Kühne, U. & Drechsler, R. Increasing the accuracy of SAT-based debugging

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    		2009DATE, pp. 1326-1331 inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/date/SulflowFBKD09,
+  author = {André Sülflow and Görschwin Fey and Cécile Braunstein and Ulrich Kühne and Rolf Drechsler},
+  title = {Increasing the accuracy of SAT-based debugging},
+  booktitle = {DATE},
+  publisher = {IEEE},
+  year = {2009},
+  pages = {1326-1331}
+}
+
    Türk, T. A Hierarchy for Accellera's Property Specification Language

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    		2005School: University of Kaiserslautern phdthesisURL  
    BibTeX: +
    +@phdthesis{turk05thesis,
+  author = {Türk, T.},
+  title = {A Hierarchy for Accellera's Property Specification Language},
+  school = {University of Kaiserslautern},
+  year = {2005},
+  url = {http://thomas-tuerk.de/dokumente/Diplomarbeit.pdf}
+}
+
    The VIS Group VIS User's Manual

    [BibTeX]

    		1996 manual 
    + PDF +
     
    BibTeX: +
    +@manual{vismanual,
+  author = {The VIS Group},
+  title = {VIS User's Manual},
+  year = {1996}
+}
+
    Université Pierre et Marie Curie (UPMC), Paris 6 UE : Achitecture des systèmes intégrés, M1

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    		 misc  
    BibTeX: +
    +@misc{m106archi,
+  author = {Université Pierre et Marie Curie (UPMC), Paris 6},
+  title = {UE : Achitecture des systèmes intégrés, M1},
+  note = {http://www-master.ufr-info-p6.jussieu.fr/ue/archi/}
+}
+
    Upton, D. A Flexible Structure for Computer-Controlled Manufacturing Systems

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    		1992Manufacturing Review
    Vol. 5(1), pp. 58-74     		article  
    BibTeX: +
    +@article{fms,
+  author = {D.M.~Upton},
+  title = {A Flexible Structure for Computer-Controlled Manufacturing Systems},
+  journal = {Manufacturing Review},
+  year = {1992},
+  volume = {5},
+  number = {1},
+  pages = {58--74}
+}
+
    Valk, R. Bridging the Gap between Place- and Floyd-Invariants with Applications to Preemptive Scheduling

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    		1993
    Vol. 691Proc. of ICATPN'93, pp. 432-452     		inproceedings  
    BibTeX: +
    +@inproceedings{Valk93,
+  author = {R. Valk},
+  title = {Bridging the Gap between Place- and Floyd-Invariants with Applications to Preemptive Scheduling},
+  booktitle = {Proc. of ICATPN'93},
+  publisher = {Springer Verlag},
+  year = {1993},
+  volume = {691},
+  pages = {432--452}
+}
+
    Velev, M.N. & Bryant, R.E. Bernhard Steffen (Ed.)Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation

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    		1998
    Vol. 1384TACAS, pp. 136-150     		inproceedings 
    + PDF +
     
    BibTeX: +
    +@inproceedings{DBLP:conf/tacas/VelevB98,
+  author = {Miroslav N. Velev and Randal E. Bryant},
+  title = {Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation},
+  booktitle = {TACAS},
+  publisher = {Springer},
+  year = {1998},
+  volume = {1384},
+  pages = {136-150}
+}
+
    Xie, F. & Browne, J. Verified Systems by Composition from Verified Components

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    		2003ESEC/FSE 2003 : Proceedings of the 11th ACM SIGSOFT Symposium on Foundations of Software Engineering 2003 held jointly with 9th European Software Engineering Conference, pp. 277-286 inproceedingsDOI   
    BibTeX: +
    +@inproceedings{xie03verified,
+  author = {F.~Xie and J.C.~Browne},
+  title = {Verified Systems by Composition from Verified Components},
+  booktitle = {ESEC/FSE 2003 : Proceedings of the 11th ACM SIGSOFT Symposium on Foundations of Software Engineering 2003 held jointly with 9th European Software Engineering Conference},
+  publisher = {ACM Press},
+  year = {2003},
+  pages = {277--286},
+  doi = {http://doi.acm.org/10.1145/940071.940109}
+}
+
    Yadgar, A. New Approaches to Model Checking and to 3-Valued Abstraction and Refinement

    [BibTeX]

    		2010School: Technion - Israel Institute of Technology phdthesis 
    + PDF +
     
    BibTeX: +
    +@phdthesis{Yadgar10thesis,
+  author = {Avi Yadgar},
+  title = {New Approaches to Model Checking and to 3-Valued Abstraction and Refinement},
+  school = {Technion - Israel Institute of Technology},
+  year = {2010}
+}
+
    Zaher S. Andraus, Mark H. Liffiton, K.A.S. CEGAR-Based Formal Hardware Verification: A Case Study

    [BibTeX]

    		2007 techreport 
    + PDF +
     
    BibTeX: +
    +@techreport{cegarhwcasestudy07,
+  author = {Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah},
+  title = {CEGAR-Based Formal Hardware Verification: A Case Study},
+  year = {2007}
+}
+
    Zaki, M., Tahar, S. & Bois, G. Formal verification of analog and mixed signal designs: A survey

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    		2008Microelectronics Journal
    Vol. 39(12), pp. 1395-1404     		articleDOI  
    + PDF +
     
    BibTeX: +
    +@article{Zaki08analogformalsurvey,
+  author = {M.H~Zaki and S.~Tahar and G.~Bois},
+  title = {Formal verification of analog and mixed signal designs: A survey},
+  journal = {Microelectronics Journal},
+  publisher = {Elsevier Science Publishers B. V.},
+  year = {2008},
+  volume = {39},
+  number = {12},
+  pages = {1395--1404},
+  doi = {http://dx.doi.org/10.1016/j.mejo.2008.05.013}
+}
+
     Mark Aagaard and John W. O'Leary (Ed.)Formal Methods in Computer-Aided Design, 4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings

    [BibTeX]

    		2002
    Vol. 2517FMCAD     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/fmcad/2002,,
+  title = {Formal Methods in Computer-Aided Design, 4th International Conference, FMCAD 2002, Portland, OR, USA, November 6-8, 2002, Proceedings},
+  booktitle = {FMCAD},
+  publisher = {Springer},
+  year = {2002},
+  volume = {2517}
+}
+
     Bernhard K. Aichernig and Bernhard Beckert (Ed.)Third IEEE International Conference on Software Engineering and Formal Methods (SEFM 2005), 7-9 September 2005, Koblenz, Germany

    [BibTeX]

    		2005SEFM proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/sefm/2005,,
+  title = {Third IEEE International Conference on Software Engineering and Formal Methods (SEFM 2005), 7-9 September 2005, Koblenz, Germany},
+  booktitle = {SEFM},
+  publisher = {IEEE Computer Society},
+  year = {2005}
+}
+
     Rajeev Alur and Doron Peled (Ed.)Computer Aided Verification, 16th International Conference, CAV 2004, Boston, MA, USA, July 13-17, 2004, Proceedings

    [BibTeX]

    		2004
    Vol. 3114CAV     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/cav/2004,,
+  title = {Computer Aided Verification, 16th International Conference, CAV 2004, Boston, MA, USA, July 13-17, 2004, Proceedings},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {2004},
+  volume = {3114}
+}
+
     Thomas Ball and Robert B. Jones (Ed.)CAV'06: Proceedings of 18th International Conference of Computer Aided Verification

    [BibTeX]

    		2006
    Vol. 4144CAV     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/cav/2006,,
+  title = {CAV'06: Proceedings of 18th International Conference of Computer Aided Verification},
+  booktitle = {CAV},
+  year = {2006},
+  volume = {4144}
+}
+
     Marco Bernardo and Alessandro Cimatti (Ed.)Formal Methods for Hardware Verification, 6th International School on Formal Methods for the Design of Computer, Communication, and Software Systems, SFM 2006, Bertinoro, Italy, May 22-27, 2006, Advanced Lectures

    [BibTeX]

    		2006
    Vol. 3965SFM     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/sfm/2006,,
+  title = {Formal Methods for Hardware Verification, 6th International School on Formal Methods for the Design of Computer, Communication, and Software Systems, SFM 2006, Bertinoro, Italy, May 22-27, 2006, Advanced Lectures},
+  booktitle = {SFM},
+  publisher = {Springer},
+  year = {2006},
+  volume = {3965}
+}
+
     Gérard Berry and Hubert Comon and Alain Finkel (Ed.)Computer Aided Verification, 13th International Conference, CAV 2001, Paris, France, July 18-22, 2001, Proceedings

    [BibTeX]

    		2001
    Vol. 2102CAV     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/cav/2001,,
+  title = {Computer Aided Verification, 13th International Conference, CAV 2001, Paris, France, July 18-22, 2001, Proceedings},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {2001},
+  volume = {2102}
+}
+
     Eyal Bin and Avi Ziv and Shmuel Ur (Ed.)Hardware and Software, Verification and Testing, Second International Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, 2006. Revised Selected Papers

    [BibTeX]

    		2007
    Vol. 4383Haifa Verification Conference     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/hvc/2006,,
+  title = {Hardware and Software, Verification and Testing, Second International Haifa Verification Conference, HVC 2006, Haifa, Israel, October 23-26, 2006. Revised Selected Papers},
+  booktitle = {Haifa Verification Conference},
+  publisher = {Springer},
+  year = {2007},
+  volume = {4383}
+}
+
     Frank S. de Boer and Marcello M. Bonsangue and Susanne Graf and Willem P. de Roever (Ed.)Formal Methods for Components and Objects, 4th International Symposium, FMCO 2005, Amsterdam, The Netherlands, November 1-4, 2005, Revised Lectures

    [BibTeX]

    		2006
    Vol. 4111FMCO     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/fmco/2005,,
+  title = {Formal Methods for Components and Objects, 4th International Symposium, FMCO 2005, Amsterdam, The Netherlands, November 1-4, 2005, Revised Lectures},
+  booktitle = {FMCO},
+  publisher = {Springer},
+  year = {2006},
+  volume = {4111}
+}
+
     Dominique Borrione and Wolfgang J. Paul (Ed.)Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings

    [BibTeX]

    		2005
    Vol. 3725CHARME     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/charme/2005,,
+  title = {Correct Hardware Design and Verification Methods, 13th IFIP WG 10.5 Advanced Research Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings},
+  booktitle = {CHARME},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3725}
+}
+
     Ed Brinksma and Kim Guldstrand Larsen (Ed.)Computer Aided Verification, 14th International Conference, CAV 2002,Copenhagen, Denmark, July 27-31, 2002, Proceedings

    [BibTeX]

    		2002
    Vol. 2404CAV     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/cav/2002,,
+  title = {Computer Aided Verification, 14th International Conference, CAV 2002,Copenhagen, Denmark, July 27-31, 2002, Proceedings},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {2002},
+  volume = {2404}
+}
+
     Maura Cerioli (Ed.)Fundamental Approaches to Software Engineering, 8th International Conference, FASE 2005, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2005, Edinburgh, UK, April 4-8, 2005, Proceedings

    [BibTeX]

    		2005
    Vol. 3442FASE     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/fase/2005,,
+  title = {Fundamental Approaches to Software Engineering, 8th International Conference, FASE 2005, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2005, Edinburgh, UK, April 4-8, 2005, Proceedings},
+  booktitle = {FASE},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3442}
+}
+
     Iliano Cervesato and Helmut Veith and Andrei Voronkov (Ed.)Logic for Programming, Artificial Intelligence, and Reasoning, 15th International Conference, LPAR 2008, Doha, Qatar, November 22-27, 2008. Proceedings

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    		2008
    Vol. 5330LPAR     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/lpar/2008,,
+  title = {Logic for Programming, Artificial Intelligence, and Reasoning, 15th International Conference, LPAR 2008, Doha, Qatar, November 22-27, 2008. Proceedings},
+  booktitle = {LPAR},
+  publisher = {Springer},
+  year = {2008},
+  volume = {5330}
+}
+
     Radhia Cousot (Ed.)Verification, Model Checking, and Abstract Interpretation, 6th International Conference, VMCAI 2005, Paris, France, January 17-19, 2005, Proceedings

    [BibTeX]

    		2005
    Vol. 3385VMCAI     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/vmcai/2005,,
+  title = {Verification, Model Checking, and Abstract Interpretation, 6th International Conference, VMCAI 2005, Paris, France, January 17-19, 2005, Proceedings},
+  booktitle = {VMCAI},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3385}
+}
+
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    		1981
    Vol. 104Theoretical Computer Science     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/tcs/1981,,
+  title = {Theoretical Computer Science, 5th GI-Conference, Karlsruhe, Germany, March 23-25, 1981, Proceedings},
+  booktitle = {Theoretical Computer Science},
+  publisher = {Springer},
+  year = {1981},
+  volume = {104}
+}
+
     E. Allen Emerson and Kedar S. Namjoshi (Ed.)Verification, Model Checking, and Abstract Interpretation, 7th International Conference, VMCAI 2006, Charleston, SC, USA, January 8-10, 2006, Proceedings

    [BibTeX]

    		2006
    Vol. 3855VMCAI     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/vmcai/2006,,
+  title = {Verification, Model Checking, and Abstract Interpretation, 7th International Conference, VMCAI 2006, Charleston, SC, USA, January 8-10, 2006, Proceedings},
+  booktitle = {VMCAI},
+  publisher = {Springer},
+  year = {2006},
+  volume = {3855}
+}
+
     E.A. Emerson and A.P. Sistla (Ed.)Computer Aided Verification, 12th International Conference, CAV 2000, Chicago, IL, USA, July 15-19, 2000, Proceedings

    [BibTeX]

    		2000
    Vol. 1855CAV     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/cav/2000,,
+  title = {Computer Aided Verification, 12th International Conference, CAV 2000, Chicago, IL, USA, July 15-19, 2000, Proceedings},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {2000},
+  volume = {1855}
+}
+
     Javier Esparza and Charles Lakos (Ed.)Applications and Theory of Petri Nets 2002, 23rd International Conference, ICATPN 2002, Adelaide, Australia, June 24-30, 2002, Proceedings

    [BibTeX]

    		2002
    Vol. 2360ICATPN     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/apn/2002,,
+  title = {Applications and Theory of Petri Nets 2002, 23rd International Conference, ICATPN 2002, Adelaide, Australia, June 24-30, 2002, Proceedings},
+  booktitle = {ICATPN},
+  publisher = {Springer},
+  year = {2002},
+  volume = {2360}
+}
+
     Daniel Geist and Enrico Tronci (Ed.)Correct Hardware Design and Verification Methods CHARME 2003

    [BibTeX]

    		2003
    Vol. 2860     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/charme/2003,,
+  title = {Correct Hardware Design and Verification Methods CHARME 2003},
+  publisher = {Springer},
+  year = {2003},
+  volume = {2860}
+}
+
     Georges G. E. Gielen (Ed.)Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006

    [BibTeX]

    		2006DATE proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/date/2006p,,
+  title = {Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006},
+  booktitle = {DATE},
+  publisher = {European Design and Automation Association, Leuven, Belgium},
+  year = {2006}
+}
+
     Enrico Giunchiglia and Armando Tacchella (Ed.)Theory and Applications of Satisfiability Testing, 6th International Conference, SAT 2003. Santa Margherita Ligure, Italy, May 5-8, 2003 Selected Revised Papers

    [BibTeX]

    		2004
    Vol. 2919SAT     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/sat/2003,,
+  title = {Theory and Applications of Satisfiability Testing, 6th International Conference, SAT 2003. Santa Margherita Ligure, Italy, May 5-8, 2003 Selected Revised Papers},
+  booktitle = {SAT},
+  publisher = {Springer},
+  year = {2004},
+  volume = {2919}
+}
+
     Bernhard Gramlich (Ed.)Frontiers of Combining Systems, 5th International Workshop, FroCoS 2005, Vienna, Austria, September 19-21, 2005, Proceedings

    [BibTeX]

    		2005
    Vol. 3717FroCoS     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/frocos/2005,,
+  title = {Frontiers of Combining Systems, 5th International Workshop, FroCoS 2005, Vienna, Austria, September 19-21, 2005, Proceedings},
+  booktitle = {FroCoS},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3717}
+}
+
     Orna Grumberg (Ed.)Computer Aided Verification, 9th International Conference, CAV '97, Haifa, Israel, June 22-25, 1997, Proceedings

    [BibTeX]

    		1997
    Vol. 1254CAV     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/cav/1997,,
+  title = {Computer Aided Verification, 9th International Conference, CAV '97, Haifa, Israel, June 22-25, 1997, Proceedings},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {1997},
+  volume = {1254}
+}
+
     Nicolas Halbwachs and Doron Peled (Ed.)Computer Aided Verification, 11th International Conference, CAV '99, Trento, Italy, July 6-10, 1999, Proceedings

    [BibTeX]

    		1999
    Vol. 1633CAV     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/cav/1999,,
+  title = {Computer Aided Verification, 11th International Conference, CAV '99, Trento, Italy, July 6-10, 1999, Proceedings},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {1999},
+  volume = {1633}
+}
+
     Nicolas Halbwachs and Lenore D. Zuck (Ed.)Tools and Algorithms for the Construction and Analysis of Systems, 11th International Conference, TACAS 2005, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2005, Edinburgh, UK, April 4-8, 2005, Proceedings

    [BibTeX]

    		2005
    Vol. 3440TACAS     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/tacas/2005,,
+  title = {Tools and Algorithms for the Construction and Analysis of Systems, 11th International Conference, TACAS 2005, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2005, Edinburgh, UK, April 4-8, 2005, Proceedings},
+  booktitle = {TACAS},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3440}
+}
+
     Soha Hassoun (Ed.)2006 International Conference on Computer-Aided Design (ICCAD'06), November 5-9, 2006, San Jose, CA, USA

    [BibTeX]

    		2006ICCAD proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/iccad/2006,,
+  title = {2006 International Conference on Computer-Aided Design (ICCAD'06), November 5-9, 2006, San Jose, CA, USA},
+  booktitle = {ICCAD},
+  publisher = {ACM},
+  year = {2006}
+}
+
     Holger Hermanns and Jens Palsberg (Ed.)Tools and Algorithms for the Construction and Analysis of Systems, 12th International Conference, TACAS 2006 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2006, Vienna, Austria, March 25 - April 2, 2006, Proceedings

    [BibTeX]

    		2006
    Vol. 3920TACAS     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/tacas/2006,,
+  title = {Tools and Algorithms for the Construction and Analysis of Systems, 12th International Conference, TACAS 2006 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2006, Vienna, Austria, March 25 - April 2, 2006, Proceedings},
+  booktitle = {TACAS},
+  publisher = {Springer},
+  year = {2006},
+  volume = {3920}
+}
+
     Alan J. Hu and Moshe Y. Vardi (Ed.)Computer Aided Verification, 10th International Conference, CAV '98, Vancouver, BC, Canada, June 28 - July 2, 1998, Proceedings

    [BibTeX]

    		1998
    Vol. 1427CAV     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/cav/1998,,
+  title = {Computer Aided Verification, 10th International Conference, CAV '98, Vancouver, BC, Canada, June 28 - July 2, 1998, Proceedings},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {1998},
+  volume = {1427}
+}
+
     Kurt Jensen and Andreas Podelski (Ed.)Tools and Algorithms for the Construction and Analysis of Systems, 10th International Conference, TACAS 2004, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2004, Barcelona, Spain, March 29 - April 2, 2004, Proceedings

    [BibTeX]

    		2004
    Vol. 2988TACAS     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/tacas/2004,,
+  title = {Tools and Algorithms for the Construction and Analysis of Systems, 10th International Conference, TACAS 2004, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2004, Barcelona, Spain, March 29 - April 2, 2004, Proceedings},
+  booktitle = {TACAS},
+  publisher = {Springer},
+  year = {2004},
+  volume = {2988}
+}
+
     Ranjit Jhala and David A. Schmidt (Ed.)Verification, Model Checking, and Abstract Interpretation - 12th International Conference, VMCAI 2011, Austin, TX, USA, January 23-25, 2011. Proceedings

    [BibTeX]

    		2011
    Vol. 6538VMCAI     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/vmcai/2011,,
+  title = {Verification, Model Checking, and Abstract Interpretation - 12th International Conference, VMCAI 2011, Austin, TX, USA, January 23-25, 2011. Proceedings},
+  booktitle = {VMCAI},
+  publisher = {Springer},
+  year = {2011},
+  volume = {6538}
+}
+
     Warren A. Hunt Jr. and Fabio Somenzi (Ed.)Computer Aided Verification, 15th International Conference, CAV 2003, Boulder, CO, USA, July 8-12, 2003, Proceedings

    [BibTeX]

    		2003
    Vol. 2725CAV     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/cav/2003,,
+  title = {Computer Aided Verification, 15th International Conference, CAV 2003, Boulder, CO, USA, July 8-12, 2003, Proceedings},
+  booktitle = {CAV},
+  publisher = {Springer},
+  year = {2003},
+  volume = {2725}
+}
+
     William H. Joyner Jr. and Grant Martin and Andrew B. Kahng (Ed.)Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005

    [BibTeX]

    		2005DAC proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/dac/2005,,
+  title = {Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005},
+  booktitle = {DAC},
+  publisher = {ACM},
+  year = {2005}
+}
+
     Dexter Kozen (Ed.)Logic of Programs, Workshop

    [BibTeX]

    		1982
    Vol. 131Logic of Programs     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/lop/1981,,
+  title = {Logic of Programs, Workshop},
+  booktitle = {Logic of Programs},
+  publisher = {Springer},
+  year = {1982},
+  volume = {131}
+}
+
     Sharad Malik and Limor Fix and Andrew B. Kahng (Ed.)Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004

    [BibTeX]

    		2004DAC proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/dac/2004,,
+  title = {Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004},
+  booktitle = {DAC},
+  publisher = {ACM},
+  year = {2004}
+}
+
     Zohar Manna and Doron Peled (Ed.)Time for Verification, Essays in Memory of Amir Pnueli

    [BibTeX]

    		2010
    Vol. 6200Essays in Memory of Amir Pnueli     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/birthday/2010pnueli,,
+  title = {Time for Verification, Essays in Memory of Amir Pnueli},
+  booktitle = {Essays in Memory of Amir Pnueli},
+  publisher = {Springer},
+  year = {2010},
+  volume = {6200}
+}
+
     Tiziana Margaria and Wang Yi (Ed.)Tools and Algorithms for the Construction and Analysis of Systems, 7th International Conference, TACAS 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings

    [BibTeX]

    		2001
    Vol. 2031TACAS     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/tacas/2001,,
+  title = {Tools and Algorithms for the Construction and Analysis of Systems, 7th International Conference, TACAS 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings},
+  booktitle = {TACAS},
+  publisher = {Springer},
+  year = {2001},
+  volume = {2031}
+}
+
     Marcel Vinicius Medeiros Oliveira and Jim Woodcock (Ed.)Formal Methods: Foundations and Applications, 12th Brazilian Symposium on Formal Methods, SBMF 2009, Gramado, Brazil, August 19-21, 2009, Revised Selected Papers

    [BibTeX]

    		2009
    Vol. 5902SBMF     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/sbmf/2009,,
+  title = {Formal Methods: Foundations and Applications, 12th Brazilian Symposium on Formal Methods, SBMF 2009, Gramado, Brazil, August 19-21, 2009, Revised Selected Papers},
+  booktitle = {SBMF},
+  publisher = {Springer},
+  year = {2009},
+  volume = {5902}
+}
+
     Catuscia Palamidessi (Ed.)CONCUR 2000 - Concurrency Theory, 11th International Conference, University Park, PA, USA, August 22-25, 2000, Proceedings

    [BibTeX]

    		2000
    Vol. 1877CONCUR     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/concur/2000,,
+  title = {CONCUR 2000 - Concurrency Theory, 11th International Conference, University Park, PA, USA, August 22-25, 2000, Proceedings},
+  booktitle = {CONCUR},
+  publisher = {Springer},
+  year = {2000},
+  volume = {1877}
+}
+
     C. R. Ramakrishnan and Jakob Rehof (Ed.)Tools and Algorithms for the Construction and Analysis of Systems, 14th International Conference, TACAS 2008, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2008, Budapest, Hungary, March 29-April 6, 2008. Proceedings

    [BibTeX]

    		2008
    Vol. 4963TACAS     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/tacas/2008,,
+  title = {Tools and Algorithms for the Construction and Analysis of Systems, 14th International Conference, TACAS 2008, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2008, Budapest, Hungary, March 29-April 6, 2008. Proceedings},
+  booktitle = {TACAS},
+  publisher = {Springer},
+  year = {2008},
+  volume = {4963}
+}
+
     Willem P. de Roever and Hans Langmaack and Amir Pnueli (Ed.)Compositionality: The Significant Difference, International Symposium, COMPOS'97, Bad Malente, Germany, September 8-12, 1997. Revised Lectures

    [BibTeX]

    		1998
    Vol. 1536COMPOS     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/compos/1997,,
+  title = {Compositionality: The Significant Difference, International Symposium, COMPOS'97, Bad Malente, Germany, September 8-12, 1997. Revised Lectures},
+  booktitle = {COMPOS},
+  publisher = {Springer},
+  year = {1998},
+  volume = {1536}
+}
+
     Ellen Sentovich (Ed.)Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006

    [BibTeX]

    		2006DAC proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/dac/2006,,
+  title = {Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006},
+  booktitle = {DAC},
+  publisher = {ACM},
+  year = {2006}
+}
+
     Bernhard Steffen (Ed.)Tools and Algorithms for Construction and Analysis of Systems, 4th International Conference, TACAS '98, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'98, Lisbon, Portugal, March 28 - April 4, 1998, Proceedings

    [BibTeX]

    		1998
    Vol. 1384TACAS     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/tacas/1998,,
+  title = {Tools and Algorithms for Construction and Analysis of Systems, 4th International Conference, TACAS '98, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'98, Lisbon, Portugal, March 28 - April 4, 1998, Proceedings},
+  booktitle = {TACAS},
+  publisher = {Springer},
+  year = {1998},
+  volume = {1384}
+}
+
     Farn Wang (Ed.)Formal Techniques for Networked and Distributed Systems - FORTE 2005, 25th IFIP WG 6.1 International Conference, Taipei, Taiwan, October 2-5, 2005, Proceedings

    [BibTeX]

    		2005
    Vol. 3731FORTE     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/forte/2005,,
+  title = {Formal Techniques for Networked and Distributed Systems - FORTE 2005, 25th IFIP WG 6.1 International Conference, Taipei, Taiwan, October 2-5, 2005, Proceedings},
+  booktitle = {FORTE},
+  publisher = {Springer},
+  year = {2005},
+  volume = {3731}
+}
+
     Jeannette M. Wing and Jim Woodcock and Jim Davies (Ed.)FM'99 - Formal Methods, World Congress on Formal Methods in the Development of Computing Systems, Toulouse, France, September 20-24, 1999, Proceedings, Volume I

    [BibTeX]

    		1999
    Vol. 1708World Congress on Formal Methods     		proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/fm/1999-1,,
+  title = {FM'99 - Formal Methods, World Congress on Formal Methods in the Development of Computing Systems, Toulouse, France, September 20-24, 1999, Proceedings, Volume I},
+  booktitle = {World Congress on Formal Methods},
+  publisher = {Springer},
+  year = {1999},
+  volume = {1708}
+}
+
     Alliance, a free VLSI cad system

    [BibTeX]

    		 misc  
    BibTeX: +
    +@misc{alliance,,
+  title = {Alliance, a free VLSI cad system},
+  note = {\http://www-asim.lip6.fr/recherche/alliance/}
+}
+
     OneSpin Solutions

    [BibTeX]

    		 misc  
    BibTeX: +
    +@misc{onespin,,
+  title = {OneSpin Solutions},
+  note = {http://www.onespin-solutions.com/}
+}
+
     The Prosyd Project on Property-Based System Design

    [BibTeX]

    		 misc  
    BibTeX: +
    +@misc{prosyd,,
+  title = {The Prosyd Project on Property-Based System Design},
+  note = {http://www.prosyd.org/}
+}
+
     The SoCLib Project

    [BibTeX]

    		 miscURL  
    BibTeX: +
    +@misc{soclib,,
+  title = {The SoCLib Project},
+  note = {http://soclib.lip6.fr/},
+  url = {http://soclib.lip6.fr/}
+}
+
     Texas-97 Verification Benchmarks

    [BibTeX]

    		 misc  
    BibTeX: +
    +@misc{texas97bench,,
+  title = {Texas-97 Verification Benchmarks},
+  note = {\http://www.cad.eecs.berkeley.edu/Respep/Research/vis/texas-97/}
+}
+
     VSI Alliance

    [BibTeX]

    		 misc  
    BibTeX: +
    +@misc{vsia,,
+  title = {VSI Alliance},
+  note = {http://www.vsi.org/}
+}
+
     Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009

    [BibTeX]

    		2009DATE proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/date/2009,,
+  title = {Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009},
+  booktitle = {DATE},
+  publisher = {IEEE},
+  year = {2009}
+}
+
     Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA

    [BibTeX]

    		2009FMCAD proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/fmcad/2009,,
+  title = {Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA},
+  booktitle = {FMCAD},
+  publisher = {IEEE},
+  year = {2009}
+}
+
     19th IEEE Symposium on Logic in Computer Science (LICS 2004), 14-17 July 2004, Turku, Finland, Proceedings

    [BibTeX]

    		2004LICS proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/lics/2004,,
+  title = {19th IEEE Symposium on Logic in Computer Science (LICS 2004), 14-17 July 2004, Turku, Finland, Proceedings},
+  booktitle = {LICS},
+  publisher = {IEEE Computer Society},
+  year = {2004}
+}
+
     SAT 2004 - The Seventh International Conference on Theory and Applications of Satisfiability Testing, 10-13 May 2004, Vancouver, BC, Canada, Online Proceedings

    [BibTeX]

    		2004SAT proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/sat/2004,,
+  title = {SAT 2004 - The Seventh International Conference on Theory and Applications of Satisfiability Testing, 10-13 May 2004, Vancouver, BC, Canada, Online Proceedings},
+  booktitle = {SAT},
+  year = {2004}
+}
+
     2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany

    [BibTeX]

    		2003DATE proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/date/2003,,
+  title = {2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany},
+  booktitle = {DATE},
+  publisher = {IEEE Computer Society},
+  year = {2003}
+}
+
     Proceedings of the 25th International Conference on Software Engineering, May 3-10, 2003, Portland, Oregon, USA

    [BibTeX]

    		2003ICSE proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/icse/2003,,
+  title = {Proceedings of the 25th International Conference on Software Engineering, May 3-10, 2003, Portland, Oregon, USA},
+  booktitle = {ICSE},
+  publisher = {IEEE Computer Society},
+  year = {2003}
+}
+
     10th International Symposium on Temporal Representation and Reasoning / 4th International Conference on Temporal Logic (TIME-ICTL 2003), 8-10 July 2003, Cairns, Queensland, Australia

    [BibTeX]

    		2003TIME proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/time/2003,,
+  title = {10th International Symposium on Temporal Representation and Reasoning / 4th International Conference on Temporal Logic (TIME-ICTL 2003), 8-10 July 2003, Cairns, Queensland, Australia},
+  booktitle = {TIME},
+  publisher = {IEEE Computer Society},
+  year = {2003}
+}
+
     20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings

    [BibTeX]

    		2002ICCD proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/iccd/2002,,
+  title = {20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings},
+  booktitle = {ICCD},
+  publisher = {IEEE Computer Society},
+  year = {2002}
+}
+
     Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001

    [BibTeX]

    		2001DAC proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/dac/2001,,
+  title = {Proceedings of the 38th Design Automation Conference, DAC 2001, Las Vegas, NV, USA, June 18-22, 2001},
+  booktitle = {DAC},
+  publisher = {ACM},
+  year = {2001}
+}
+
     Proceedings of the 23rd International Conference on Software Engineering, ICSE 2001, 12-19 May 2001, Toronto, Ontario, Canada

    [BibTeX]

    		2001ICSE proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/icse/2001,,
+  title = {Proceedings of the 23rd International Conference on Software Engineering, ICSE 2001, 12-19 May 2001, Toronto, Ontario, Canada},
+  booktitle = {ICSE},
+  publisher = {IEEE Computer Society},
+  year = {2001}
+}
+
     AMBA Specification

    [BibTeX]

    		1999 manual 
    + PDF +
     
    BibTeX: +
    +@manual{amba,,
+  title = {AMBA Specification},
+  year = {1999},
+  edition = {2.0},
+  note = {ARM Limited pyright. All right reserved}
+}
+
     Formal Verification Using Affirma FormalCheck

    [BibTeX]

    		1999 manual  
    BibTeX: +
    +@manual{formalcheck,,
+  title = {Formal Verification Using Affirma FormalCheck},
+  year = {1999}
+}
+
     Proceedings, Fourth Annual Symposium on Logic in Computer Science, 5-8 June, 1989, Asilomar Conference Center, Pacific Grove, California, USA

    [BibTeX]

    		1989LICS proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/lics/LICS4,,
+  title = {Proceedings, Fourth Annual Symposium on Logic in Computer Science, 5-8 June, 1989, Asilomar Conference Center, Pacific Grove, California, USA},
+  booktitle = {LICS},
+  publisher = {IEEE Computer Society},
+  year = {1989}
+}
+
     Proceedings, Third Annual Symposium on Logic in Computer Science

    [BibTeX]

    		1988LICS proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/lics/LICS3,,
+  title = {Proceedings, Third Annual Symposium on Logic in Computer Science},
+  booktitle = {LICS},
+  publisher = {IEEE Computer Society},
+  year = {1988}
+}
+
     Proceedings of the Fourteenth Annual ACM Symposium on Theory of Computing, 5-7 May 1982, San Francisco, California, USA

    [BibTeX]

    		1982STOC proceedings  
    BibTeX: +
    +@proceedings{DBLP:conf/stoc/STOC14,,
+  title = {Proceedings of the Fourteenth Annual ACM Symposium on Theory of Computing, 5-7 May 1982, San Francisco, California, USA},
+  booktitle = {STOC},
+  publisher = {ACM},
+  year = {1982}
+}
+
    + +

    + Created by JabRef on 20/02/2012. +

    + + + + + Index: /vis_dev/vis-2.3/models/debug/and2.v =================================================================== --- /vis_dev/vis-2.3/models/debug/and2.v (revision 44) +++ /vis_dev/vis-2.3/models/debug/and2.v (revision 45) @@ -1,9 +1,9 @@ module andgate(clk,a,b); input clk; -input a; -input b; +input [1:0]a; +input [1:0]b; -reg c; -reg d; +reg [1:0]c; +reg [1:0]d; initial c = 0; Index: /vis_dev/vis-2.3/src/debug/debug.c =================================================================== --- /vis_dev/vis-2.3/src/debug/debug.c (revision 44) +++ /vis_dev/vis-2.3/src/debug/debug.c (revision 45) @@ -66,4 +66,5 @@ static int CommandCreateAbnormal(Hrc_Manager_t ** hmgr,int argc, char ** argv); static int CommandGenerateNetworkCNF(Hrc_Manager_t ** hmgr,int argc, char ** argv); +static int CommandBuildCexBdd(Hrc_Manager_t ** hmgr,int argc, char ** argv); @@ -95,4 +96,5 @@ Cmd_CommandAdd("_sat_debug", CommandSatDebug, 0); Cmd_CommandAdd("_createAbn", CommandCreateAbnormal, 1); + Cmd_CommandAdd("_cexbdd", CommandBuildCexBdd, 0); Cmd_CommandAdd("print_network_cnf", CommandGenerateNetworkCNF, 0); @@ -700,5 +702,52 @@ return rel; } - +mdd_t * buildDummy2(mdd_manager * mddManager) +{ + mdd_t * rel = NIL(mdd_t); + mdd_t * state0 = mdd_one(mddManager); + mdd_t * state2 = mdd_one(mddManager); + mdd_t * state3 = mdd_one(mddManager); + // state0 = s0 + mdd_t * s0 = mdd_eq_c(mddManager,0, 0); + mdd_t * s1 = mdd_eq_c(mddManager,2, 0); + state0 = mdd_and(s0,s1,1,1); + // state2 = s2 + s0 = mdd_eq_c(mddManager,0, 0); + s1 = mdd_eq_c(mddManager,2, 1); + state2 = mdd_and(s0,s1,1,1); + // state3 = s3 + s0 = mdd_eq_c(mddManager,0, 1); + s1 = mdd_eq_c(mddManager,2, 1); + state3 = mdd_and(s0,s1,1,1); +// Build transition relation + + array_t * mvarVal = array_alloc(int,0); + array_insert_last(int, mvarVal,2); + array_t * val = array_alloc(int,0); + array_t * mvarName = array_alloc(char*,0); + array_insert_last(char*, mvarName,"S1"); + int e1Id = mdd_create_variables(mddManager,mvarVal,mvarName,NIL(array_t)); + array_insert(char*, mvarName,0,"I"); + int e0Id = mdd_create_variables(mddManager,mvarVal,mvarName,NIL(array_t)); + array_insert_last(int, val,1); + mdd_t * e1 = mdd_literal(mddManager, e1Id,val); + mdd_t * e0 = mdd_literal(mddManager, e0Id,val); + mdd_t * tmp2 = mdd_and(e1,e0,0,0); +mdd_t * ne2_1 = mdd_or(e1,tmp2,1,1); +mdd_t * ne2_0 = mdd_and(e1,e0,0,1); + +array_insert(char*, mvarName,0,"Next_SI"); +int id = mdd_create_variables(mddManager,mvarVal,mvarName,NIL(array_t)); +Mvf_Function_t * mvf = Mvf_FunctionAlloc(mddManager, 2); +Mvf_FunctionAddMintermsToComponent(mvf,1,ne2_1); +Mvf_FunctionAddMintermsToComponent(mvf,0,ne2_0); +mdd_t *relation = Mvf_FunctionBuildRelationWithVariable(mvf, id); + +//bdd_print(relation); +mdd_FunctionPrintMain (mddManager ,relation,"news",vis_stdout); + //bdd_ite + return rel; + +} /**Function******************************************************************** @@ -713,5 +762,5 @@ CommandDescription [This command create a new transition relation that is a - and of the Bdd of the old one and an other bdd. + and of the Bdd of the old one and another bdd.

    @@ -780,8 +829,8 @@ /* with the transtion relation */ /***********************************/ -rel = buildDummyBdd(mddManager); +rel = buildDummy3(mddManager,network); if(rel == NIL(mdd_t)) { - fprintf(vis_stdout,"Problem when building the new relation bdd"); + fprintf(vis_stdout,"Problem when building the new relation bdd\n"); return 1; } @@ -809,4 +858,6 @@ int mddId = array_fetch(int, rangeVarMddIdArray, i); mdd_t *relation = Mvf_FunctionBuildRelationWithVariable(mvf, mddId); + mdd_FunctionPrintMain (mddManager ,relation,"MVF",vis_stdout); + mdd_t * n_relation = mdd_and(relation,rel,1,1); /* Build for each possible value */ @@ -820,4 +871,5 @@ mdd_t * n_relation_s1 = mdd_cofactor_minterm(n_rel_s1,n_s1); Mvf_FunctionAddMintermsToComponent(newMvf,v,n_relation_s1); + } @@ -857,3 +909,99 @@ } - +static int +CommandBuildCexBdd(Hrc_Manager_t ** hmgr, + int argc, char ** argv){ +int c; +int verbose = 0; /* default value */ + +/* + * Parse command line options. + */ +util_getopt_reset(); +while ((c = util_getopt(argc, argv, "vh")) != EOF) { + switch(c) { + case 'v': + verbose = 1; + break; + case 'h': + goto usage; + default: + goto usage; + } +} + +if (verbose) { + (void) fprintf(vis_stdout, "The _cexBdd is under construction.\n"); +} + +Fsm_Fsm_t *fsm = NIL(Fsm_Fsm_t); +Ntk_Network_t *network = NIL(Ntk_Network_t); +mdd_manager *mddManager; +mdd_t *rel = NIL(mdd_t); +int i; +/******************/ +network = Ntk_HrcManagerReadCurrentNetwork(*hmgr); +if(network == NIL(Ntk_Network_t)) + return 1; +fsm = Fsm_HrcManagerReadCurrentFsm(*hmgr); +if(fsm == NIL(Fsm_Fsm_t)) + return 1; +mddManager = Fsm_FsmReadMddManager(fsm); + + + +/********** Build cex ***********/ +/* Here add the function */ +/* that build the Bdd to and */ +/* with the transtion relation */ +/***********************************/ +//rel = buildDummyBdd(mddManager); +array_t * nextNames = Fsm_FsmReadNextStateFunctionNames(fsm); +array_t * nextIds = Fsm_FsmReadNextStateVars(fsm); + +/** state0 = s0 **/ + mdd_t * s0 = mdd_eq_c(mddManager,0, 0); + mdd_t * s1 = mdd_eq_c(mddManager,2, 0); + mdd_t * state0 = mdd_one(mddManager); + state0 = mdd_and(s0,s1,1,1); +/** Next state1 = s2 + !s2 **/ + + mdd_t * ns0 = mdd_eq_c(mddManager,1, 1); + mdd_t * ns1 = mdd_eq_c(mddManager,3, 0); + mdd_t * state1 = mdd_one(mddManager); + state1 = mdd_and(ns0,ns1,1,1); + state1 = mdd_or(state1,state1,1,0); + +/** state = s0) -> !(Nextstate = s2) + (Nextstae = s2) **/ + rel = mdd_one(mddManager); + rel = mdd_or(state0,state1,0,0); +/**********/ +/** state0 = s2 **/ + mdd_t * s02 = mdd_eq_c(mddManager,0, 0); + mdd_t * s12 = mdd_eq_c(mddManager,2, 1); + mdd_t * state02 = mdd_one(mddManager); + state02 = mdd_and(s02,s12,1,1); +/** Next state1 = s3 **/ + + mdd_t * ns02 = mdd_eq_c(mddManager,1, 1); + mdd_t * ns12 = mdd_eq_c(mddManager,3, 1); + mdd_t * state12 = mdd_one(mddManager); + state12 = mdd_and(ns02,ns12,1,1); + +/** state = s0) -> !(Nextstate = s3) **/ + mdd_t * new_rel = mdd_one(mddManager); + new_rel = mdd_or(state02,state12,0,0); + rel = mdd_and(new_rel,rel,1,1); + mdd_FunctionPrintMain (mddManager ,rel,"REL",vis_stdout); + +return 0; /* normal exit */ + +usage: +(void) fprintf(vis_stderr, "usage: _BddCex [-h] [-v]\n"); +(void) fprintf(vis_stderr, " -h\t\tprint the command usage\n"); +(void) fprintf(vis_stderr, " -v\t\tverbose\n"); +return 1; /* error exit */ + +} + + Index: /vis_dev/vis-2.3/src/debug/debug.make =================================================================== --- /vis_dev/vis-2.3/src/debug/debug.make (revision 44) +++ /vis_dev/vis-2.3/src/debug/debug.make (revision 45) @@ -1,3 +1,3 @@ -CSRC += debug.c debugUtilities.c debugAbnormal.c +CSRC += debug.c debugUtilities.c debugAbnormal.c debugNewBdd.c HEADERS += debug.h debugInt.h Index: /vis_dev/vis-2.3/src/debug/debugAbnormal.c =================================================================== --- /vis_dev/vis-2.3/src/debug/debugAbnormal.c (revision 44) +++ /vis_dev/vis-2.3/src/debug/debugAbnormal.c (revision 45) @@ -5,5 +5,5 @@ Description [Create new primary input in the current network at a given - output node. Return the variable created] + output node. Return the node created] SideEffects [Modify the network] @@ -12,5 +12,5 @@ ******************************************************************************/ -Ntk_Node_t * Dbg_CreateNewNode(Ntk_Network_t * ntk,Ntk_Node_t* +Ntk_Node_t * Dbg_CreateNewNode(Ntk_Network_t * ntk, Ntk_Node_t* node, char * varName ) { Index: /vis_dev/vis-2.3/src/debug/debugInt.h =================================================================== --- /vis_dev/vis-2.3/src/debug/debugInt.h (revision 44) +++ /vis_dev/vis-2.3/src/debug/debugInt.h (revision 45) @@ -87,4 +87,5 @@ void printNodeArray(array_t * nodeArray); boolean Dbg_TestNodeInSubs(char* nodeName,array_t * subsName); +mdd_t * buildDummy3(mdd_manager * mddManager,Ntk_Network_t * ntk); /**AutomaticEnd***************************************************************/