Index: /vis_dev/vis-2.3/models/transition/cex.ctl
===================================================================
--- /vis_dev/vis-2.3/models/transition/cex.ctl	(revision 99)
+++ /vis_dev/vis-2.3/models/transition/cex.ctl	(revision 99)
@@ -0,0 +1,2 @@
+(((cex.state[2:0] = 7  * cex.s2 = 1 ) )  * S.state[1:0] = 0)  * 
+EX( S.state[1:0] = 1 ) ; 
Index: /vis_dev/vis-2.3/models/transition/cex.v
===================================================================
--- /vis_dev/vis-2.3/models/transition/cex.v	(revision 99)
+++ /vis_dev/vis-2.3/models/transition/cex.v	(revision 99)
@@ -0,0 +1,91 @@
+module cex(ck,j);
+input ck;
+input j;
+wire nd_1;
+wire nd_2;
+wire nd_3;
+
+
+reg [2:0]state;
+reg s2;
+reg s3;
+reg s4;
+
+initial 
+  begin
+    state[0] = 1;
+    state[1] = 1;
+    state[2] = $ND(0,1);
+    if(state == 3)
+      s2 = 0;
+    else
+      s2 = 1;
+  s3 = $ND(0,1);
+  s4 = $ND(0,1);
+  end
+
+assign nd_1 = $ND(0,1);
+assign nd_2 = $ND(0,1);
+assign nd_3 = $ND(0,1);
+always @(posedge ck)
+begin
+case (state)
+  7 :
+    if(j == 1)
+    begin
+      s2 = 1;
+      s3 = 0;
+      s4 = 0;
+      state = 1;
+    end
+    else
+    begin
+      s2 = 0;
+      s3 = nd_1;
+      s4 = nd_2;
+      state = 2;
+    end
+
+  3:
+    begin
+      s2 = nd_3;
+      s3 = nd_1;
+      s4 = nd_2;
+      state = 0;
+    end
+  1:
+    begin
+      s2 = nd_3;
+      s3 = 0;
+      s4 = nd_2;
+      state = 4;
+    end
+  2:
+    begin
+      s2 = nd_3;
+      s3 = nd_1;
+      s4 = nd_2;
+      state = 0;
+    end
+  4:
+    begin
+      s2 = nd_3;
+      s3 = nd_1;
+      s4 = nd_2;
+      state = 0;
+    end
+  0:
+    begin
+      s2 = nd_3;
+      s3 = nd_1;
+      s4 = nd_2;
+      state = 0;
+    end
+
+
+endcase
+end
+
+endmodule
+
+
Index: /vis_dev/vis-2.3/models/transition/compostion.v
===================================================================
--- /vis_dev/vis-2.3/models/transition/compostion.v	(revision 99)
+++ /vis_dev/vis-2.3/models/transition/compostion.v	(revision 99)
@@ -0,0 +1,11 @@
+module compo(ck,i,t);
+input ck;
+input i;
+input j;
+output t;
+simple S(ck,i,t);
+cex cex(ck,j);
+
+endmodule
+`include "modele.v"
+`include "cex.v"
Index: /vis_dev/vis-2.3/models/transition/modele.v
===================================================================
--- /vis_dev/vis-2.3/models/transition/modele.v	(revision 99)
+++ /vis_dev/vis-2.3/models/transition/modele.v	(revision 99)
@@ -0,0 +1,38 @@
+module simple(ck,i,t);
+input ck;
+input i;
+output t;
+
+wire nd_t;
+
+assign nd_t = $ND(0,1);
+
+reg [1:0]state;
+reg t;
+
+initial state = 0;
+initial t = $ND(0,1);
+
+always @(posedge ck)
+begin
+case (state)
+  0 :
+    begin
+      t = (i == 0)?nd_t:1;
+      state = (i == 0)?0:1;
+    end
+  1:
+    begin
+      t =nd_t;
+      state = 2;
+    end
+   2: begin
+      t = nd_t;
+      state = 2;
+    end
+endcase
+end
+
+endmodule
+
+
Index: /vis_dev/vis-2.3/models/transition/script
===================================================================
--- /vis_dev/vis-2.3/models/transition/script	(revision 98)
+++ /vis_dev/vis-2.3/models/transition/script	(revision 99)
@@ -1,4 +1,3 @@
-rlmv simple.mv
+rlmv compostion.mv
 init
-compute_reach -v 1 
-_transition -v 1
+_cexbdd