# vl2mv environment2.v # version: 2.4 # date: 17:32:27 07/20/2012 (CEST) .model environment # I/O ports .outputs addr<0> addr<1> addr<2> addr<3> addr<4> .outputs val .inputs i_val .inputs i_addr<0> i_addr<1> i_addr<2> i_addr<3> i_addr<4> .inputs ack # addr = 0 .names addr$raw_n0<0> 0 .names addr$raw_n0<1> 0 .names addr$raw_n0<2> 0 .names addr$raw_n0<3> 0 .names addr$raw_n0<4> 0 # non-blocking assignments for initial # val = 1 .names val$raw_n1 1 # non-blocking assignments for initial # r_val = 1 .names r_val$raw_n2 1 # non-blocking assignments for initial # val = 0 .names val$raw_n3 0 .names _n5 1 # ack == 1 .names ack _n5 _n6 .def 0 0 1 1 1 0 1 .names _n6 _n4 0 1 1 0 .names _n4 _n8 - =_n4 # val = (r_val == 1) ? 0 : i_val .names _nb 1 # r_val == 1 .names r_val _nb _nc .def 0 0 1 1 1 0 1 .names _nc _na 0 1 1 0 .names _ne 0 # (r_val == 1) ? 0 : i_val .names _na _ne i_val _nf .def 0 1 1 - 1 0 - 1 1 .names _nf val$_n4_n9$true - =_nf # addr = i_addr .names i_addr<0> addr$_n4_n11$true<0> - =i_addr<0> .names i_addr<1> addr$_n4_n11$true<1> - =i_addr<1> .names i_addr<2> addr$_n4_n11$true<2> - =i_addr<2> .names i_addr<3> addr$_n4_n11$true<3> - =i_addr<3> .names i_addr<4> addr$_n4_n11$true<4> - =i_addr<4> # if/else (ack == 1) .names _n4 val$_n4_n9$true val$raw_n3 val$_n4$raw_n13 .def 0 1 1 - 1 0 - 1 1 .names _n4 addr$_n4_n11$true<0> addr<0> addr$_n4$raw_n17<0> .def 0 1 1 - 1 0 - 1 1 .names _n4 addr$_n4_n11$true<1> addr<1> addr$_n4$raw_n17<1> .def 0 1 1 - 1 0 - 1 1 .names _n4 addr$_n4_n11$true<2> addr<2> addr$_n4$raw_n17<2> .def 0 1 1 - 1 0 - 1 1 .names _n4 addr$_n4_n11$true<3> addr<3> addr$_n4$raw_n17<3> .def 0 1 1 - 1 0 - 1 1 .names _n4 addr$_n4_n11$true<4> addr<4> addr$_n4$raw_n17<4> .def 0 1 1 - 1 0 - 1 1 # r_val = i_val .names i_val r_val$raw_n1f - =i_val # conflict arbitrators .names _n8 _n20 .def 0 1 1 .names _n20 addr$_n4$raw_n17<0> addr$_n4$raw_n17<1> addr$_n4$raw_n17<2> addr$_n4$raw_n17<3> addr$_n4$raw_n17<4> addr<0> addr<1> addr<2> addr<3> addr<4> -> _n21<0> _n21<1> _n21<2> _n21<3> _n21<4> 1 - - - - - - - - - - =addr$_n4$raw_n17<0> =addr$_n4$raw_n17<1> =addr$_n4$raw_n17<2> =addr$_n4$raw_n17<3> =addr$_n4$raw_n17<4> 0 - - - - - - - - - - =addr<0> =addr<1> =addr<2> =addr<3> =addr<4> .names _n22 .def 0 1 .names _n22 r_val$raw_n1f _n23 .def 0 1 0 0 1 1 1 .names _n8 _n24 .def 0 - 1 1 1 .names _n24 val$_n4$raw_n13 _n25 .def 0 1 0 0 1 1 1 # non-blocking assignments # latches .r addr$raw_n0<0> addr<0> .def 0 1 1 .r addr$raw_n0<1> addr<1> .def 0 1 1 .r addr$raw_n0<2> addr<2> .def 0 1 1 .r addr$raw_n0<3> addr<3> .def 0 1 1 .r addr$raw_n0<4> addr<4> .def 0 1 1 .latch _n21<0> addr<0> .latch _n21<1> addr<1> .latch _n21<2> addr<2> .latch _n21<3> addr<3> .latch _n21<4> addr<4> .r val$raw_n1 val 0 0 1 1 .latch _n25 val .r r_val$raw_n2 r_val 0 0 1 1 .latch _n23 r_val # quasi-continuous assignment .end