# vis release 1.1 (compiled 25-Apr-96 at 11:35 AM)
# network name: COHERANCE
# generated: Tue May 14 18:26:43 1996
#
# name                       type            mddId vals levs
proc1.proc_state            latch                1    3 (0, 1)
proc1.proc_state$NS         shadow               2    3 (2, 3)
inst1                       primary-input        0    3 (4, 5)
cc1.cache_state             latch                3    5 (6, 7, 8)
cc1.cache_state$NS          shadow               4    5 (9, 10, 11)
cache_req1                  latch               10    4 (12, 13)
cache_req1$NS               shadow              11    4 (14, 15)
cc1.block_state             latch               31    3 (20, 21)
cc1.block_state$NS          shadow              32    3 (22, 23)
direc.arbiter_state         latch               46    6 (24, 25, 26)
direc.arbiter_state$NS      shadow              47    6 (27, 28, 29)
any_address1<0>             primary-input        7    2 (30)
blk_add1<0>                 latch                8    2 (31)
blk_add1<0>$NS              shadow               9    2 (32)
direc.cache_Wlist1<*1*>     latch               20    2 (33)
direc.cache_Wlist1<*1*>$NS  shadow              21    2 (34)
cc1.block_add<0>            latch                5    2 (35)
cc1.block_add<0>$NS         shadow               6    2 (36)
direc.cache_Wlist1<*0*>     latch               22    2 (37)
direc.cache_Wlist1<*0*>$NS  shadow              23    2 (38)
direc.cache_Rlist1<*1*>     latch               24    2 (39)
direc.cache_Rlist1<*1*>$NS  shadow              25    2 (40)
direc.cache_Rlist1<*0*>     latch               26    2 (41)
direc.cache_Rlist1<*0*>$NS  shadow              27    2 (42)
direc.cache_Rlist2<*0*>     latch               16    2 (43)
direc.cache_Rlist2<*0*>$NS  shadow              17    2 (44)
cc1.block_val               latch               28    2 (45)
cc1.block_val$NS            shadow              29    2 (46)
any_value1                  primary-input       30    2 (47)
direc.main_mem<*0*>         latch               42    2 (48)
direc.main_mem<*0*>$NS      shadow              43    2 (49)
direc.main_mem<*1*>         latch               40    2 (50)
direc.main_mem<*1*>$NS      shadow              41    2 (51)
cc2.block_val               latch               37    2 (52)
cc2.block_val$NS            shadow              38    2 (53)
any_value2                  primary-input       39    2 (54)
cc2.block_add<0>            latch               53    2 (55)
cc2.block_add<0>$NS         shadow              54    2 (56)
direc.cache_Rlist2<*1*>     latch               18    2 (57)
direc.cache_Rlist2<*1*>$NS  shadow              19    2 (58)
any_address2<0>             primary-input       55    2 (59)
cc2.block_state             latch               44    3 (60, 61)
cc2.block_state$NS          shadow              45    3 (62, 63)
direc.cache_Wlist2<*0*>     latch               14    2 (64)
direc.cache_Wlist2<*0*>$NS  shadow              15    2 (65)
direc.cache_Wlist2<*1*>     latch               12    2 (66)
direc.cache_Wlist2<*1*>$NS  shadow              13    2 (67)
blk_add2<0>                 latch               33    2 (68)
blk_add2<0>$NS              shadow              34    2 (69)
proc2.proc_state            latch               49    3 (70, 71)
proc2.proc_state$NS         shadow              50    3 (72, 73)
inst2                       primary-input       48    3 (74, 75)
cc2.cache_state             latch               51    5 (80, 81, 82)
cc2.cache_state$NS          shadow              52    5 (83, 84, 85)
cache_req2                  latch               35    4 (86, 87)
cache_req2$NS               shadow              36    4 (88, 89)