# vis release 1.4 (compiled 1-Jan-01 at 4:07 AM)
# network name: daio_receiver
# generated: Mon Jan  1 18:50:14 2001
#
# name                type            mddId vals levs
rx_control<3>        primary-input      120    2 (0)
rx_control<1>        primary-input        1    2 (1)
rx_control<0>        primary-input        0    2 (2)
xtal<0>              primary-input        7    2 (3)
xtal<2>              primary-input        5    2 (4)
xtal<1>              primary-input        6    2 (5)
xtal<3>              primary-input        2    2 (6)
clock_out$NS         shadow               4    2 (7)
clock_out            latch                3    2 (8)
rx_status_3          latch               93    2 (9)
rx_status_3$NS       shadow              94    2 (10)
reset                primary-input       92    2 (11)
biphase_violation    primary-input       95    2 (12)
carrier_loss         primary-input       96    2 (13)
bit_count_B<4>$NS    shadow              15    2 (14)
bit_count_B<4>       latch               14    2 (15)
bit_count_B<3>$NS    shadow              13    2 (16)
bit_count_B<3>       latch               12    2 (17)
bit_count_B<2>$NS    shadow              11    2 (18)
bit_count_B<2>       latch               10    2 (19)
bit_count_B<5>$NS    shadow              17    2 (20)
bit_count_B<5>       latch               16    2 (21)
bit_count_B<6>$NS    shadow              19    2 (22)
bit_count_B<6>       latch               18    2 (23)
bit_count_B<1>$NS    shadow               9    2 (24)
bit_count_B<1>       latch                8    2 (25)
rx_control<2>        primary-input       91    2 (26)
pc                   latch               64   11 (27, 32, 33, 34)
pc$NS                shadow              65   11 (28, 29, 30, 31)
bit_in               primary-input       99    2 (35)
bit_count_A<5>$NS    shadow              60    2 (36)
bit_count_A<5>       latch               59    2 (37)
bit_count_A<6>$NS    shadow              62    2 (38)
bit_count_A<6>       latch               61    2 (39)
load_A$NS            shadow              26    2 (40)
load_A               latch               25    2 (41)
bit_count_A<4>$NS    shadow              58    2 (42)
bit_count_A<4>       latch               57    2 (43)
bit_count_A<3>$NS    shadow              56    2 (44)
bit_count_A<3>       latch               55    2 (45)
bit_count_B<0>$NS    shadow              28    2 (46)
bit_count_B<0>       latch               27    2 (47)
rx_status_2$NS       shadow              24    2 (48)
rx_status_2          latch               23    2 (49)
load_B$NS            shadow              21    2 (50)
load_B               latch               20    2 (51)
bit_count_A<2>$NS    shadow              54    2 (52)
bit_count_A<2>       latch               53    2 (53)
bit_count_A<1>$NS    shadow              52    2 (54)
bit_count_A<1>       latch               51    2 (55)
bit_count_A<0>$NS    shadow              50    2 (56)
bit_count_A<0>       latch               49    2 (57)
frame_counter<0>$NS  shadow              30    2 (58)
frame_counter<0>     latch               29    2 (59)
frame_counter<1>$NS  shadow              32    2 (60)
frame_counter<1>     latch               31    2 (61)
frame_counter<2>$NS  shadow              36    2 (62)
frame_counter<2>     latch               35    2 (63)
frame_counter<4>$NS  shadow              40    2 (64)
frame_counter<4>     latch               39    2 (65)
frame_counter<3>$NS  shadow              38    2 (66)
frame_counter<3>     latch               37    2 (67)
frame_counter<5>$NS  shadow              42    2 (68)
frame_counter<5>     latch               41    2 (69)
frame_counter<6>$NS  shadow              44    2 (70)
frame_counter<6>     latch               43    2 (71)
frame_counter<7>$NS  shadow              46    2 (72)
frame_counter<7>     latch               45    2 (73)
frame_counter<8>$NS  shadow              48    2 (74)
frame_counter<8>     latch               47    2 (75)
load_buff            latch               33    2 (76)
load_buff$NS         shadow              34    2 (77)
shift_reg<11>$NS     shadow              73    2 (78)
shift_reg<11>        latch               72    2 (79)
shift_reg<12>$NS     shadow              75    2 (80)
shift_reg<12>        latch               74    2 (81)
shift_reg<13>$NS     shadow              77    2 (82)
shift_reg<13>        latch               76    2 (83)
shift_reg<14>$NS     shadow              79    2 (84)
shift_reg<14>        latch               78    2 (85)
shift_reg<15>$NS     shadow              81    2 (86)
shift_reg<15>        latch               80    2 (87)
shift_reg<16>$NS     shadow              83    2 (88)
shift_reg<16>        latch               82    2 (89)
shift_reg<17>$NS     shadow              85    2 (90)
shift_reg<17>        latch               84    2 (91)
shift_reg<18>$NS     shadow              87    2 (92)
shift_reg<18>        latch               86    2 (93)
shift_reg<19>$NS     shadow              89    2 (94)
shift_reg<19>        latch               88    2 (95)
shift_reg<10>$NS     shadow              71    2 (96)
shift_reg<10>        latch               70    2 (97)
shift_reg<9>         latch               68    2 (98)
shift_reg<9>$NS      shadow              69    2 (99)
shift_reg<8>         latch              116    2 (100)
shift_reg<8>$NS      shadow             117    2 (101)
shift_reg<7>$NS      shadow             115    2 (102)
shift_reg<7>         latch              114    2 (103)
parity$NS            shadow             119    2 (104)
parity               latch              118    2 (105)
shift_reg<0>$NS      shadow             101    2 (106)
shift_reg<0>         latch              100    2 (107)
shift_reg<1>$NS      shadow             103    2 (108)
shift_reg<1>         latch              102    2 (109)
shift_reg<2>$NS      shadow             105    2 (110)
shift_reg<2>         latch              104    2 (111)
shift_reg<3>$NS      shadow             107    2 (112)
shift_reg<3>         latch              106    2 (113)
shift_reg<4>$NS      shadow             109    2 (114)
shift_reg<4>         latch              108    2 (115)
shift_reg<5>$NS      shadow             111    2 (116)
shift_reg<5>         latch              110    2 (117)
shift_reg<6>$NS      shadow             113    2 (118)
shift_reg<6>         latch              112    2 (119)
rx_status_0$NS       shadow              98    2 (120)
rx_status_0          latch               97    2 (121)
rx_status_1$NS       shadow              67    2 (122)
rx_status_1          latch               66    2 (123)
preamble_2           primary-input       63    2 (124)
preamble_3           primary-input       22    2 (125)
preamble_1           primary-input       90    2 (126)