# /projects/vl2mv/vl2mvt/mips/bin/vl2mv 8-arbit.v # version: 0.2 # date: 09:05:18 03/01/97 (PST) .model main # I/O ports .mv sa 2 myTRUE myFALSE .mv xa 2 myTRUE myFALSE .mv yr 4 idle request lock release .mv sr 4 idle request lock release .mv xr 4 idle request lock release .mv ya 2 myTRUE myFALSE .mv constTRUE 2 myTRUE myFALSE # assign sa = 1 .mv sa$raw_n0 2 myTRUE myFALSE .names sa$raw_n0 myFALSE # assign constTRUE = 0 .mv constTRUE$raw_n1 2 myTRUE myFALSE .names constTRUE$raw_n1 myTRUE .subckt arbitCell F0 topCell=constTRUE urLeft=xr urRight=yr uaLeft=xa uaRight=ya xr=sr xa=sa .subckt fourCells G1 sa=xa sr=xr .subckt fourCells G2 sa=ya sr=yr # conflict arbitrators .names sa$raw_n0 sa - =sa$raw_n0 .names constTRUE$raw_n1 constTRUE - =constTRUE$raw_n1 # non-blocking assignments # latches # quasi-continuous assignment .end .model arbitCell # I/O ports .outputs uaLeft .inputs topCell .inputs xa .inputs urRight .inputs urLeft .outputs xr .outputs uaRight .mv processedLeft 2 myTRUE myFALSE .mv prevLeft 2 myTRUE myFALSE .mv holdToken 2 myTRUE myFALSE .mv processedRight 2 myTRUE myFALSE .mv uaLeft 2 myTRUE myFALSE .mv topCell 2 myTRUE myFALSE .mv xa 2 myTRUE myFALSE .mv urRight 4 idle request lock release .mv giveChild 2 myTRUE myFALSE .mv urLeft 4 idle request lock release .mv mustGiveParent 2 myTRUE myFALSE .mv xr 4 idle request lock release .mv uaRight 2 myTRUE myFALSE .mv childOwns 2 myTRUE myFALSE .mv prevRight 2 myTRUE myFALSE # prevLeft = 1 .mv prevLeft$raw_n2 2 myTRUE myFALSE .names prevLeft$raw_n2 myFALSE # non-blocking assignments for initial # prevRight = 0 .mv prevRight$raw_n3 2 myTRUE myFALSE .names prevRight$raw_n3 myTRUE # non-blocking assignments for initial # processedLeft = 1 .mv processedLeft$raw_n4 2 myTRUE myFALSE .names processedLeft$raw_n4 myFALSE # non-blocking assignments for initial # processedRight = 1 .mv processedRight$raw_n5 2 myTRUE myFALSE .names processedRight$raw_n5 myFALSE # non-blocking assignments for initial # assign mustGiveParent = (processedLeft == 0) && (processedRight == 0) && (!(topCell == 0)) ? 0 : 1 .mv mustGiveParent$raw_n6 2 myTRUE myFALSE .mv _n8 2 myTRUE myFALSE .names _n8 myTRUE # processedLeft == 0 .names processedLeft _n8 _n7 .def 0 - =processedLeft 1 .mv _na 2 myTRUE myFALSE .names _na myTRUE # processedRight == 0 .names processedRight _na _n9 .def 0 - =processedRight 1 # (processedLeft == 0) && (processedRight == 0) .names _n7 _n9 _nb .def 0 1 1 1 .mv _nd 2 myTRUE myFALSE .names _nd myTRUE # topCell == 0 .names topCell _nd _nc .def 0 - =topCell 1 .names _nc _ne 0 1 1 0 # (processedLeft == 0) && (processedRight == 0) && (!(topCell == 0)) .names _nb _ne _nf .def 0 1 1 1 .mv _n10 2 myTRUE myFALSE .names _n10 myTRUE .mv _n11 2 myTRUE myFALSE .names _n11 myFALSE # (processedLeft == 0) && (processedRight == 0) && (!(topCell == 0)) ? 0 : 1 .mv _n12 2 myTRUE myFALSE .names _n10 _n11 _nf _n12 - - 0 =_n11 - - 1 =_n10 .names _n12 mustGiveParent$raw_n6 - =_n12 # holdToken = topCell .mv holdToken$raw_n13 2 myTRUE myFALSE .names topCell holdToken$raw_n13 - =topCell # non-blocking assignments for initial # assign childOwns = (urLeft == lock || urRight == lock ) ? 0 : 1 .mv childOwns$raw_n14 2 myTRUE myFALSE .mv _n16 4 idle request lock release .names _n16 lock # urLeft == 2 .names urLeft _n16 _n15 .def 0 - =urLeft 1 .mv _n18 4 idle request lock release .names _n18 lock # urRight == 2 .names urRight _n18 _n17 .def 0 - =urRight 1 # urLeft == 2 || urRight == 2 .names _n15 _n17 _n19 .def 1 0 0 0 .mv _n1a 2 myTRUE myFALSE .names _n1a myTRUE .mv _n1b 2 myTRUE myFALSE .names _n1b myFALSE # (urLeft == 2 || urRight == 2) ? 0 : 1 .mv _n1c 2 myTRUE myFALSE .names _n1a _n1b _n19 _n1c - - 0 =_n1b - - 1 =_n1a .names _n1c childOwns$raw_n14 - =_n1c # assign giveChild = (uaLeft == 0 || uaRight == 0) ? 0 : 1 .mv giveChild$raw_n1d 2 myTRUE myFALSE .mv _n1f 2 myTRUE myFALSE .names _n1f myTRUE # uaLeft == 0 .names uaLeft _n1f _n1e .def 0 - =uaLeft 1 .mv _n21 2 myTRUE myFALSE .names _n21 myTRUE # uaRight == 0 .names uaRight _n21 _n20 .def 0 - =uaRight 1 # uaLeft == 0 || uaRight == 0 .names _n1e _n20 _n22 .def 1 0 0 0 .mv _n23 2 myTRUE myFALSE .names _n23 myTRUE .mv _n24 2 myTRUE myFALSE .names _n24 myFALSE # (uaLeft == 0 || uaRight == 0) ? 0 : 1 .mv _n25 2 myTRUE myFALSE .names _n23 _n24 _n22 _n25 - - 0 =_n24 - - 1 =_n23 .names _n25 giveChild$raw_n1d - =_n25 # assign uaLeft = (!(mustGiveParent == 0) && (holdToken == 0 && urLeft == request && (!(urRight == request ) || prevRight == 0))) ? 0 : 1 .mv uaLeft$raw_n26 2 myTRUE myFALSE .mv _n28 2 myTRUE myFALSE .names _n28 myTRUE # mustGiveParent == 0 .names mustGiveParent _n28 _n27 .def 0 - =mustGiveParent 1 .names _n27 _n29 0 1 1 0 .mv _n2b 2 myTRUE myFALSE .names _n2b myTRUE # holdToken == 0 .names holdToken _n2b _n2a .def 0 - =holdToken 1 .mv _n2d 4 idle request lock release .names _n2d request # urLeft == 1 .names urLeft _n2d _n2c .def 0 - =urLeft 1 # holdToken == 0 && urLeft == 1 .names _n2a _n2c _n2e .def 0 1 1 1 .mv _n30 4 idle request lock release .names _n30 request # urRight == 1 .names urRight _n30 _n2f .def 0 - =urRight 1 .names _n2f _n31 0 1 1 0 .mv _n33 2 myTRUE myFALSE .names _n33 myTRUE # prevRight == 0 .names prevRight _n33 _n32 .def 0 - =prevRight 1 # !(urRight == 1) || prevRight == 0 .names _n31 _n32 _n34 .def 1 0 0 0 # holdToken == 0 && urLeft == 1 && (!(urRight == 1) || prevRight == 0) .names _n2e _n34 _n35 .def 0 1 1 1 # !(mustGiveParent == 0) && (holdToken == 0 && urLeft == 1 && (!(urRight == 1) || prevRight == 0)) .names _n29 _n35 _n36 .def 0 1 1 1 .mv _n37 2 myTRUE myFALSE .names _n37 myTRUE .mv _n38 2 myTRUE myFALSE .names _n38 myFALSE # (!(mustGiveParent == 0) && (holdToken == 0 && urLeft == 1 && (!(urRight == 1) || prevRight == 0))) ? 0 : 1 .mv _n39 2 myTRUE myFALSE .names _n37 _n38 _n36 _n39 - - 0 =_n38 - - 1 =_n37 .names _n39 uaLeft$raw_n26 - =_n39 # assign uaRight = (!(mustGiveParent == 0) && (holdToken == 0 && urRight == request && (!(urLeft == request ) || prevLeft == 0))) ? 0 : 1 .mv uaRight$raw_n3a 2 myTRUE myFALSE .mv _n3c 2 myTRUE myFALSE .names _n3c myTRUE # mustGiveParent == 0 .names mustGiveParent _n3c _n3b .def 0 - =mustGiveParent 1 .names _n3b _n3d 0 1 1 0 .mv _n3f 2 myTRUE myFALSE .names _n3f myTRUE # holdToken == 0 .names holdToken _n3f _n3e .def 0 - =holdToken 1 .mv _n41 4 idle request lock release .names _n41 request # urRight == 1 .names urRight _n41 _n40 .def 0 - =urRight 1 # holdToken == 0 && urRight == 1 .names _n3e _n40 _n42 .def 0 1 1 1 .mv _n44 4 idle request lock release .names _n44 request # urLeft == 1 .names urLeft _n44 _n43 .def 0 - =urLeft 1 .names _n43 _n45 0 1 1 0 .mv _n47 2 myTRUE myFALSE .names _n47 myTRUE # prevLeft == 0 .names prevLeft _n47 _n46 .def 0 - =prevLeft 1 # !(urLeft == 1) || prevLeft == 0 .names _n45 _n46 _n48 .def 1 0 0 0 # holdToken == 0 && urRight == 1 && (!(urLeft == 1) || prevLeft == 0) .names _n42 _n48 _n49 .def 0 1 1 1 # !(mustGiveParent == 0) && (holdToken == 0 && urRight == 1 && (!(urLeft == 1) || prevLeft == 0)) .names _n3d _n49 _n4a .def 0 1 1 1 .mv _n4b 2 myTRUE myFALSE .names _n4b myTRUE .mv _n4c 2 myTRUE myFALSE .names _n4c myFALSE # (!(mustGiveParent == 0) && (holdToken == 0 && urRight == 1 && (!(urLeft == 1) || prevLeft == 0))) ? 0 : 1 .mv _n4d 2 myTRUE myFALSE .names _n4b _n4c _n4a _n4d - - 0 =_n4c - - 1 =_n4b .names _n4d uaRight$raw_n3a - =_n4d # assign xr = (holdToken == myFALSE && (urLeft == 1 || urRight == 1)) ? 1 : (childOwns == myTRUE ) ? 2 : (holdToken == myTRUE && (((mustGiveParent == myTRUE ) || !((urLeft == 1 || urRight == 1))) && !(topCell == myTRUE ))) ? 3 : 0 .mv xr$raw_n4e 4 idle request lock release .mv _n50 2 myTRUE myFALSE .names _n50 myFALSE # holdToken == 1 .names holdToken _n50 _n4f .def 0 - =holdToken 1 .mv _n52 4 idle request lock release .names _n52 request # urLeft == 1 .names urLeft _n52 _n51 .def 0 - =urLeft 1 .mv _n54 4 idle request lock release .names _n54 request # urRight == 1 .names urRight _n54 _n53 .def 0 - =urRight 1 # urLeft == 1 || urRight == 1 .names _n51 _n53 _n55 .def 1 0 0 0 # holdToken == 1 && (urLeft == 1 || urRight == 1) .names _n4f _n55 _n56 .def 0 1 1 1 .mv _n58 2 myTRUE myFALSE .names _n58 myTRUE # childOwns == 0 .names childOwns _n58 _n57 .def 0 - =childOwns 1 .mv _n5a 2 myTRUE myFALSE .names _n5a myTRUE # holdToken == 0 .names holdToken _n5a _n59 .def 0 - =holdToken 1 .mv _n5c 2 myTRUE myFALSE .names _n5c myTRUE # mustGiveParent == 0 .names mustGiveParent _n5c _n5b .def 0 - =mustGiveParent 1 .mv _n5e 4 idle request lock release .names _n5e request # urLeft == 1 .names urLeft _n5e _n5d .def 0 - =urLeft 1 .mv _n60 4 idle request lock release .names _n60 request # urRight == 1 .names urRight _n60 _n5f .def 0 - =urRight 1 # urLeft == 1 || urRight == 1 .names _n5d _n5f _n61 .def 1 0 0 0 .names _n61 _n62 0 1 1 0 # (mustGiveParent == 0) || !((urLeft == 1 || urRight == 1)) .names _n5b _n62 _n63 .def 1 0 0 0 .mv _n65 2 myTRUE myFALSE .names _n65 myTRUE # topCell == 0 .names topCell _n65 _n64 .def 0 - =topCell 1 .names _n64 _n66 0 1 1 0 # ((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0) .names _n63 _n66 _n67 .def 0 1 1 1 # holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0)) .names _n59 _n67 _n68 .def 0 1 1 1 .mv _n69 4 idle request lock release .names _n69 release .mv _n6a 4 idle request lock release .names _n6a idle # (holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0))) ? 3 : 0 .mv _n6b 4 idle request lock release .names _n69 _n6a _n68 _n6b - - 0 =_n6a - - 1 =_n69 .mv _n6c 4 idle request lock release .names _n6c lock # (childOwns == 0) ? 2 : (holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0))) ? 3 : 0 .mv _n6d 4 idle request lock release .names _n6c _n6b _n57 _n6d - - 0 =_n6b - - 1 =_n6c .mv _n6e 4 idle request lock release .names _n6e request # (holdToken == 1 && (urLeft == 1 || urRight == 1)) ? 1 : (childOwns == 0) ? 2 : (holdToken == 0 && (((mustGiveParent == 0) || !((urLeft == 1 || urRight == 1))) && !(topCell == 0))) ? 3 : 0 .mv _n6f 4 idle request lock release .names _n6e _n6d _n56 _n6f - - 0 =_n6d - - 1 =_n6e .names _n6f xr$raw_n4e - =_n6f .mv _n71 2 myTRUE myFALSE .names _n71 myTRUE # xa == 0 .names xa _n71 _n70 .def 0 - =xa 1 .names _n70 _n72 - =_n70 # holdToken = 0 .mv holdToken$_n70_n73$true 2 myTRUE myFALSE .names holdToken$_n70_n73$true myTRUE .mv _n75 2 myTRUE myFALSE .names _n75 myTRUE # giveChild == 0 .names giveChild _n75 _n74 .def 0 - =giveChild 1 .names _n74 _n76 - =_n74 # holdToken = 1 .mv holdToken$_n74_n77$true 2 myTRUE myFALSE .names holdToken$_n74_n77$true myFALSE .mv _n79 4 idle request lock release .names _n79 release # urLeft == 3 .names urLeft _n79 _n78 .def 0 - =urLeft 1 .mv _n7b 4 idle request lock release .names _n7b release # urRight == 3 .names urRight _n7b _n7a .def 0 - =urRight 1 # urLeft == 3 || urRight == 3 .names _n78 _n7a _n7c .def 1 0 0 0 .names _n7c _n7d - =_n7c # holdToken = 0 .mv holdToken$_n7c_n7e$true 2 myTRUE myFALSE .names holdToken$_n7c_n7e$true myTRUE .mv _n80 4 idle request lock release .names _n80 release # xr == 3 .names xr _n80 _n7f .def 0 - =xr 1 .names _n7f _n81 - =_n7f # holdToken = 1 .mv holdToken$_n7f_n82$true 2 myTRUE myFALSE .names holdToken$_n7f_n82$true myFALSE # if/else (xr == 3) .mv holdToken$_n7f$raw_n85 2 myTRUE myFALSE .names holdToken$_n7f_n82$true holdToken _n7f holdToken$_n7f$raw_n85 - - 0 =holdToken - - 1 =holdToken$_n7f_n82$true # if/else (urLeft == 3 || urRight == 3) .mv holdToken$_n7c$raw_n87 2 myTRUE myFALSE .names holdToken$_n7c_n7e$true holdToken$_n7f$raw_n85 _n7c holdToken$_n7c$raw_n87 - - 0 =holdToken$_n7f$raw_n85 - - 1 =holdToken$_n7c_n7e$true # if/else (giveChild == 0) .mv holdToken$_n74$raw_n8b 2 myTRUE myFALSE .names holdToken$_n74_n77$true holdToken$_n7c$raw_n87 _n74 holdToken$_n74$raw_n8b - - 0 =holdToken$_n7c$raw_n87 - - 1 =holdToken$_n74_n77$true # if/else (xa == 0) .mv holdToken$_n70$raw_n8f 2 myTRUE myFALSE .names holdToken$_n70_n73$true holdToken$_n74$raw_n8b _n70 holdToken$_n70$raw_n8f - - 0 =holdToken$_n74$raw_n8b - - 1 =holdToken$_n70_n73$true .mv _n93 2 myTRUE myFALSE .names _n93 myTRUE # uaLeft == 0 .names uaLeft _n93 _n92 .def 0 - =uaLeft 1 .names _n92 _n94 - =_n92 # prevLeft = 0 .mv prevLeft$_n92_n95$true 2 myTRUE myFALSE .names prevLeft$_n92_n95$true myTRUE # prevRight = 1 .mv prevRight$_n92_n96$true 2 myTRUE myFALSE .names prevRight$_n92_n96$true myFALSE .mv _n98 2 myTRUE myFALSE .names _n98 myTRUE # uaRight == 0 .names uaRight _n98 _n97 .def 0 - =uaRight 1 .names _n97 _n99 - =_n97 # prevLeft = 1 .mv prevLeft$_n97_n9a$true 2 myTRUE myFALSE .names prevLeft$_n97_n9a$true myFALSE # prevRight = 0 .mv prevRight$_n97_n9b$true 2 myTRUE myFALSE .names prevRight$_n97_n9b$true myTRUE # if/else (uaRight == 0) .mv prevLeft$_n97$raw_na2 2 myTRUE myFALSE .names prevLeft$_n97_n9a$true prevLeft _n97 prevLeft$_n97$raw_na2 - - 0 =prevLeft - - 1 =prevLeft$_n97_n9a$true .mv prevRight$_n97$raw_na4 2 myTRUE myFALSE .names prevRight$_n97_n9b$true prevRight _n97 prevRight$_n97$raw_na4 - - 0 =prevRight - - 1 =prevRight$_n97_n9b$true # if/else (uaLeft == 0) .mv prevLeft$_n92$raw_na9 2 myTRUE myFALSE .names prevLeft$_n92_n95$true prevLeft$_n97$raw_na2 _n92 prevLeft$_n92$raw_na9 - - 0 =prevLeft$_n97$raw_na2 - - 1 =prevLeft$_n92_n95$true .mv prevRight$_n92$raw_nab 2 myTRUE myFALSE .names prevRight$_n92_n96$true prevRight$_n97$raw_na4 _n92 prevRight$_n92$raw_nab - - 0 =prevRight$_n97$raw_na4 - - 1 =prevRight$_n92_n96$true .mv _nb3 4 idle request lock release .names _nb3 release # urLeft == 3 .names urLeft _nb3 _nb2 .def 0 - =urLeft 1 .names _nb2 _nb4 - =_nb2 # processedLeft = 0 .mv processedLeft$_nb2_nb5$true 2 myTRUE myFALSE .names processedLeft$_nb2_nb5$true myTRUE .mv _nb7 4 idle request lock release .names _nb7 release # urRight == 3 .names urRight _nb7 _nb6 .def 0 - =urRight 1 .names _nb6 _nb8 - =_nb6 # processedRight = 0 .mv processedRight$_nb6_nb9$true 2 myTRUE myFALSE .names processedRight$_nb6_nb9$true myTRUE .mv _nbb 2 myTRUE myFALSE .names _nbb myTRUE # processedLeft == 0 .names processedLeft _nbb _nba .def 0 - =processedLeft 1 .mv _nbd 2 myTRUE myFALSE .names _nbd myTRUE # processedRight == 0 .names processedRight _nbd _nbc .def 0 - =processedRight 1 # (processedLeft == 0) && (processedRight == 0) .names _nba _nbc _nbe .def 0 1 1 1 .names _nbe _nbf - =_nbe # processedLeft = 1 .mv processedLeft$_nbe_nc0$true 2 myTRUE myFALSE .names processedLeft$_nbe_nc0$true myFALSE # processedRight = 1 .mv processedRight$_nbe_nc1$true 2 myTRUE myFALSE .names processedRight$_nbe_nc1$true myFALSE # if/else ((processedLeft == 0) && (processedRight == 0)) .mv processedLeft$_nbe$raw_ncc 2 myTRUE myFALSE .names processedLeft$_nbe_nc0$true processedLeft _nbe processedLeft$_nbe$raw_ncc - - 0 =processedLeft - - 1 =processedLeft$_nbe_nc0$true .mv processedRight$_nbe$raw_nce 2 myTRUE myFALSE .names processedRight$_nbe_nc1$true processedRight _nbe processedRight$_nbe$raw_nce - - 0 =processedRight - - 1 =processedRight$_nbe_nc1$true # if/else (urRight == 3) .mv processedRight$_nb6$raw_nd9 2 myTRUE myFALSE .names processedRight$_nb6_nb9$true processedRight$_nbe$raw_nce _nb6 processedRight$_nb6$raw_nd9 - - 0 =processedRight$_nbe$raw_nce - - 1 =processedRight$_nb6_nb9$true .mv processedLeft$_nb6$raw_ne0 2 myTRUE myFALSE .names processedLeft processedLeft$_nbe$raw_ncc _nb6 processedLeft$_nb6$raw_ne0 - - 0 =processedLeft$_nbe$raw_ncc - - 1 =processedLeft # if/else (urLeft == 3) .mv processedLeft$_nb2$raw_ne9 2 myTRUE myFALSE .names processedLeft$_nb2_nb5$true processedLeft$_nb6$raw_ne0 _nb2 processedLeft$_nb2$raw_ne9 - - 0 =processedLeft$_nb6$raw_ne0 - - 1 =processedLeft$_nb2_nb5$true .mv processedRight$_nb2$raw_nf3 2 myTRUE myFALSE .names processedRight processedRight$_nb6$raw_nd9 _nb2 processedRight$_nb2$raw_nf3 - - 0 =processedRight$_nb6$raw_nd9 - - 1 =processedRight # conflict arbitrators .names _nb4 _nb8 _nbf _nf6 .def 0 1 - - 1 0 0 1 1 .mv _nf7 2 myTRUE myFALSE .names _nf6 processedLeft$_nb2$raw_ne9 processedLeft _nf7 1 - - =processedLeft$_nb2$raw_ne9 0 - - =processedLeft .names _n94 _n99 _n104 .def 0 1 - 1 0 1 1 .mv _n105 2 myTRUE myFALSE .names _n104 prevLeft$_n92$raw_na9 prevLeft _n105 1 - - =prevLeft$_n92$raw_na9 0 - - =prevLeft .names _n72 _n76 _n7d _n81 _n112 .def 0 1 - - - 1 0 1 - - 1 0 0 1 - 1 0 0 0 1 1 .mv _n113 2 myTRUE myFALSE .names _n112 holdToken$_n70$raw_n8f holdToken _n113 1 - - =holdToken$_n70$raw_n8f 0 - - =holdToken .names _nb4 _nb8 _nbf _n120 .def 0 0 1 - 1 0 0 1 1 .mv _n121 2 myTRUE myFALSE .names _n120 processedRight$_nb2$raw_nf3 processedRight _n121 1 - - =processedRight$_nb2$raw_nf3 0 - - =processedRight .names uaLeft$raw_n26 uaLeft - =uaLeft$raw_n26 .names giveChild$raw_n1d giveChild - =giveChild$raw_n1d .names mustGiveParent$raw_n6 mustGiveParent - =mustGiveParent$raw_n6 .names xr$raw_n4e xr - =xr$raw_n4e .names uaRight$raw_n3a uaRight - =uaRight$raw_n3a .names childOwns$raw_n14 childOwns - =childOwns$raw_n14 .names _n94 _n99 _n12e .def 0 1 - 1 0 1 1 .mv _n12f 2 myTRUE myFALSE .names _n12e prevRight$_n92$raw_nab prevRight _n12f 1 - - =prevRight$_n92$raw_nab 0 - - =prevRight # non-blocking assignments # latches .r prevLeft$raw_n2 prevLeft - =prevLeft$raw_n2 .latch _n105 prevLeft .r processedLeft$raw_n4 processedLeft - =processedLeft$raw_n4 .latch _nf7 processedLeft .r processedRight$raw_n5 processedRight - =processedRight$raw_n5 .latch _n121 processedRight .r holdToken$raw_n13 holdToken - =holdToken$raw_n13 .latch _n113 holdToken .r prevRight$raw_n3 prevRight - =prevRight$raw_n3 .latch _n12f prevRight # quasi-continuous assignment .end .model fourCells # I/O ports .inputs sa .outputs sr .mv constFALSE 2 myTRUE myFALSE .mv sa 2 myTRUE myFALSE .mv ur1 4 idle request lock release .mv xa 2 myTRUE myFALSE .mv ur2 4 idle request lock release .mv yr 4 idle request lock release .mv ur3 4 idle request lock release .mv ua1 2 myTRUE myFALSE .mv ur4 4 idle request lock release .mv ua2 2 myTRUE myFALSE .mv ua3 2 myTRUE myFALSE .mv sr 4 idle request lock release .mv ua4 2 myTRUE myFALSE .mv xr 4 idle request lock release .mv ya 2 myTRUE myFALSE .mv constTRUE 2 myTRUE myFALSE # assign constTRUE = 0 .mv constTRUE$raw_n13c 2 myTRUE myFALSE .names constTRUE$raw_n13c myTRUE # assign constFALSE = 1 .mv constFALSE$raw_n13d 2 myTRUE myFALSE .names constFALSE$raw_n13d myFALSE .subckt arbitCell C0 topCell=constFALSE urLeft=xr urRight=yr uaLeft=xa uaRight=ya xr=sr xa=sa .subckt arbitCell C1 topCell=constFALSE urLeft=ur1 urRight=ur2 uaLeft=ua1 uaRight=ua2 xr=xr xa=xa .subckt arbitCell C2 topCell=constFALSE urLeft=ur3 urRight=ur4 uaLeft=ua3 uaRight=ua4 xr=yr xa=ya .subckt procModel P1 ack=ua1 req=ur1 .subckt procModel P2 ack=ua2 req=ur2 .subckt procModel P3 ack=ua3 req=ur3 .subckt procModel P4 ack=ua4 req=ur4 # conflict arbitrators .names constFALSE$raw_n13d constFALSE - =constFALSE$raw_n13d .names constTRUE$raw_n13c constTRUE - =constTRUE$raw_n13c # non-blocking assignments # latches # quasi-continuous assignment .end .model procModel # I/O ports .outputs req .inputs ack .mv req 4 idle request lock release .mv procState 4 idle request lock release .mv ack 2 myTRUE myFALSE # assign req = procState .mv req$raw_n13e 4 idle request lock release .names procState req$raw_n13e - =procState # assign randChoice = $NDset ( 0,1 ) .names randChoice 0 1 # procState = 0 .mv procState$raw_n141 4 idle request lock release .names procState$raw_n141 idle # non-blocking assignments for initial .mv _n143 4 idle request lock release .names _n143 idle # procState == 0 .names procState _n143 _n142 .def 0 - =procState 1 .names _n145 1 # randChoice == 1 .names randChoice _n145 _n146 .def 0 0 1 1 1 0 1 .names _n146 _n144 0 1 1 0 # procState == 0 && (randChoice == 1) .names _n142 _n144 _n148 .def 0 1 1 1 .names _n148 _n149 - =_n148 # procState = 1 .mv procState$_n148_n14a$true 4 idle request lock release .names procState$_n148_n14a$true request .mv _n14c 4 idle request lock release .names _n14c request # procState == 1 .names procState _n14c _n14b .def 0 - =procState 1 .mv _n14e 2 myTRUE myFALSE .names _n14e myTRUE # ack == 0 .names ack _n14e _n14d .def 0 - =ack 1 # procState == 1 && ack == 0 .names _n14b _n14d _n14f .def 0 1 1 1 .names _n14f _n150 - =_n14f # procState = 2 .mv procState$_n14f_n151$true 4 idle request lock release .names procState$_n14f_n151$true lock .mv _n153 4 idle request lock release .names _n153 lock # procState == 2 .names procState _n153 _n152 .def 0 - =procState 1 .names _n155 1 # randChoice == 1 .names randChoice _n155 _n156 .def 0 0 1 1 1 0 1 .names _n156 _n154 0 1 1 0 # procState == 2 && (randChoice == 1) .names _n152 _n154 _n158 .def 0 1 1 1 .names _n158 _n159 - =_n158 # procState = 3 .mv procState$_n158_n15a$true 4 idle request lock release .names procState$_n158_n15a$true release .mv _n15c 4 idle request lock release .names _n15c release # procState == 3 .names procState _n15c _n15b .def 0 - =procState 1 .names _n15b _n15d - =_n15b # procState = 0 .mv procState$_n15b_n15e$true 4 idle request lock release .names procState$_n15b_n15e$true idle # if/else (procState == 3) .mv procState$_n15b$raw_n161 4 idle request lock release .names procState$_n15b_n15e$true procState _n15b procState$_n15b$raw_n161 - - 0 =procState - - 1 =procState$_n15b_n15e$true # if/else (procState == 2 && (randChoice == 1)) .mv procState$_n158$raw_n163 4 idle request lock release .names procState$_n158_n15a$true procState$_n15b$raw_n161 _n158 procState$_n158$raw_n163 - - 0 =procState$_n15b$raw_n161 - - 1 =procState$_n158_n15a$true # if/else (procState == 1 && ack == 0) .mv procState$_n14f$raw_n167 4 idle request lock release .names procState$_n14f_n151$true procState$_n158$raw_n163 _n14f procState$_n14f$raw_n167 - - 0 =procState$_n158$raw_n163 - - 1 =procState$_n14f_n151$true # if/else (procState == 0 && (randChoice == 1)) .mv procState$_n148$raw_n16b 4 idle request lock release .names procState$_n148_n14a$true procState$_n14f$raw_n167 _n148 procState$_n148$raw_n16b - - 0 =procState$_n14f$raw_n167 - - 1 =procState$_n148_n14a$true # conflict arbitrators .names req$raw_n13e req - =req$raw_n13e .names _n149 _n150 _n159 _n15d _n16e .def 0 1 - - - 1 0 1 - - 1 0 0 1 - 1 0 0 0 1 1 .mv _n16f 4 idle request lock release .names _n16e procState$_n148$raw_n16b procState _n16f 1 - - =procState$_n148$raw_n16b 0 - - =procState # non-blocking assignments # latches .r procState$raw_n141 procState - =procState$raw_n141 .latch _n16f procState # quasi-continuous assignment .end