# vl2mv and2.v 
# version: 2.1
# date:    16:50:59 12/22/2011 (CET)
.model andgate 
# I/O ports
.inputs a
.inputs b
# c  = 0
.names c$raw_n0
0
# non-blocking assignments for initial
# assign x  = a  & b 
# a  & b 
.names a b _n2
.def 0
1 1 1
.names _n2 x$raw_n1
- =_n2
# assign y  = (a ) ? b  : x 
# (a ) ? b  : x 
.names a b x _n4
.def 0
1 1 - 1
0 - 1 1
.names _n4 y$raw_n3
- =_n4
# c  = ~x  + c 
.names x _n7
0 1  
1 0  
# ~x  + c 
.names _n9
0
.names _n7 c _n9 _n8
.def 0
0 0 1 1
0 1 0 1
1 0 0 1
1 1 1 1
# carry/borrow
.names _nb
0
.names _n7 c _nb _na
.def 0
- 1 1 1
1 - 1 1
1 1 - 1
.names _n8 c$raw_n6
- =_n8
# conflict arbitrators
.names y$raw_n3  y
0 0
1 1
.names _nc
.def 0
 1
.names _nc c$raw_n6 _nd 
.def 0
1 0 0
1 1 1
.names x$raw_n1  x
0 0
1 1
# non-blocking assignments 
# latches
.r c$raw_n0 c
0 0
1 1
.latch _nd c
# quasi-continuous assignment
.end