# vl2mv counter.v 
# version: 2.1
# date:    14:50:04 01/27/2010 (CET)
.model counter 
# I/O ports
.names _n0
1
.subckt counter_cell bit0 carry_in=_n0 carry_out=out0  
.subckt counter_cell bit1 carry_in=out0  carry_out=out1  
.subckt counter_cell bit2 carry_in=out1  carry_out=out2  
# conflict arbitrators
# non-blocking assignments 
# latches
# quasi-continuous assignment
.end
.model counter_cell 
# I/O ports
.inputs carry_in
.outputs carry_out
# assign carry_out  = value  & carry_in 
# value  & carry_in 
.names value carry_in _n2
.def 0
1 1 1
.names _n2 carry_out$raw_n1
- =_n2
# value  = 0
.names value$raw_n3
0
# non-blocking assignments for initial
.names _n6
0
.names value _n6 _n7
.def 0
0 1 1
1 0 1
.names _n7 _n5
0 1  
1 0  
.names _n5  _n4
.def 1
0 0
# value  = carry_in 
.names carry_in value$_n4_n9$true
- =carry_in
.names _nc
1
.names value _nc _nd
.def 0
0 1 1
1 0 1
.names _nd _nb
0 1  
1 0  
.names _nb  _na
.def 1
0 0
.names _n10
0
# carry_in  == 0
.names carry_in _n10 _n11
.def 0
0 1 1
1 0 1
.names _n11 _nf
0 1  
1 0  
.names _nf _n13
- =_nf
# value  = 1
.names value$_nf_n14$true
1
# value  = 0
.names value$_nf_n15$false
0
# if/else (carry_in  == 0)
.names _nf value$_nf_n14$true value$_nf_n15$false value$_nf$raw_n17
.def 0
1 1 - 1
0 - 1 1
# case (value )
.names _na value$_nf$raw_n17 value value$_na$raw_n1d
.def 0
1 1 - 1
0 - 1 1
.names _n4 value$_n4_n9$true value$_na$raw_n1d value$_n4$raw_n1f
.def 0
1 1 - 1
0 - 1 1
# conflict arbitrators
.names _n4 _na _n13 _n24
.def 0
 1 - - 1
 0 1 1 1
 0 1 0 1
.names _n24 value$_n4$raw_n1f value _n25 
1 0 - 0
1 1 - 1
0 - 0 0
0 - 1 1
.names carry_out$raw_n1  carry_out
0 0
1 1
# non-blocking assignments 
# latches
.r value$raw_n3 value
0 0
1 1
.latch _n25 value
# quasi-continuous assignment
.end