.\" SCCSID: @(#)verilog.1     8.1     9/11/90
.TH vl2mv 1
.SH Name
vl2mv \- Compile the synthesizable subset of Verilog Programs into BLIF-MV
.SH Syntax
.B vl2mv [\fIoptions\fR] filename
.SH Description
The
.B vl2mv
command compiles programs in the synthesizable subset of Verilog into 
BLIF-MV. It is not able to handle full set Verilog language now due to 
its dynamic nature. The output file, if not specified, is inferred by 
removing everything after the last . and appending mv.
.SH Options
.IP \fB\-a\fR 0.3i
Use .subcircuits/.macros to abstract all behavioral operators. All integers
and bit vectors are abstracted as symbolic variables and expanded in
subcircuits using \fI.bundle\fR construct.
.IP \fB\-A\fR 0.3i
Send output to \fBstdout\fR.
.IP \fB\-c\fR 0.3i
Explicit clocking scheme, clocking wires and auxiliary circuits are 
generated in resulting BLIF-MV file in order to emulate edge triggerred
latches and level sensitive latches.
.IP \fB\-g\fR 0.3i
Put source debugging information in the BLIF-MV target. All debugging 
information begins with '##'.
.IP \fB\-h\fR 0.3i
Generate HSIS system calls instead of real subcircuits/flattened tables for 
\fIand\fR, \fInand\fR, \fIor\fR, \fInor\fR, \fIxor\fR, \fIxnor\fR,
\fIadd\fR, and \fIminus\fR.
.IP \fB\-m\fR 0.3i
Use .macro in place of abstracted behavioral operators. This option is 
effective only when \fB\-a\fR is provided.
.IP \fB\-o\ \fIfile\fR 0.3i
Send output to \fIfile.\fR
.IP \fB\-p\fR 0.3i
Dump out the internal representations for input programs.
.IP \fB\-S\fR 0.3i
Do not use set notation in BLIF-MV.
In general, set abbreviation notation (=, .default, []) in BLIF-MV can result
in a more compact target file.
.IP \fB\-T\ \fIwidth\fR 0.3i
Decompose tables for nonblocking assignments when number of control
variables plus that of temporary variables for assignments is greater than
\fIwidth\fR.

.SH Authors
Szu-Tsung Cheng, Gary York
.SH See Also
For the synthesizable subset of Verilog and how it is compiled into BLIF-MV, 
please refer to the related documentations and examples.