Adrien Cassagne
Associate Professor in Computer Science
Sorbonne Université, LIP6
4 Place Jussieu, 75005 Paris, France
Office 24-25/403
+33 1 44 27 65 61
adrien.cassagne@lip6.fr
Short Bio
Since 2021, I hold an Associate Professor position (Maître de Conférences in french) at Sorbonne University (Paris, France) . For my research work, I'm attached to the LIP6 laboratory (Laboratoire d'Informatique de Paris 6) in the ALSoC (Hardware and Software for Embedded System) team .
In 2020, I completed my Ph.D. thesis under the co-supervision of Prof. Denis Barthou (Inria Lab. ) and Prof. Christophe Jégo (IMS Lab. ) in Bordeaux, France. In 2013, I graduated from the Master's degree in Computer Science at University of Bordeaux.
My main research concern is about providing efficient implementations of parallel algorithms for multi-core and heterogeneous programmable architectures. Recently, I've been focusing on low power Systems-on-a-Chip (SoCs) as the energy efficiency is becoming increasingly crucial. In general, I am interested in everything related to efficient software implementations. Here are some of the domains I'm working on (or have worked on in the past):
- Computer Vision on embedded heterogeneous SoCs
- Software-Defined Radio on multi-core & SIMD CPUs
- Inference of Deep Neural Networks on CPUs, GPUs & NPUs
- Computational Fluid Dynamics on Supercomputers (CPUs & discrete GPUs)
Announcements
MSc Internship Offer (Feb. to Aug. 2025) - Support for RISC-V Vector Extension in MIPP Wrapper @ LIP6
Currently, the RISC-V open instruction set architecture, developed by UC Berkeley, is gaining significant traction. In Europe, where there is a dependency on American processors, RISC-V offers an opportunity to create European processors that could rival market leaders like Intel, AMD, ARM, and Nvidia. While Europe has lagged behind in AI hardware, especially for deep neural networks, developing RISC-V processors with specialized AI accelerators could help close this gap. The RISC-V IME is an example of specialized instructions under standardization that builds on the "V" vector extension. Studies show that RVV (RISC-V Vector Extension) could be an effective starting point for adding AI-focused instructions. Although version 1.0 of RVV is now standardized and implemented in various SoCs. However its software support remains limited.
The objective of this internship is to bridge the gap between high-level applications and low-level code by targeting the RISC-V "V" extension. This will involve designing a higher-level abstraction than assembler code or intrinsic functions. Previous wrappers, like MIPP, have achieved similar goals but on SIMD instructions (non-agnostic). Here, the main task will be to enhance the MIPP wrapper to support RVV. This includes understanding the RISC-V instruction set and its vector extension, modifying and integrating these changes into MIPP, and testing contributions on a modern RVV-enabled architecture.
The full internship subject can be downloaded here . If you wish to candidate please follow the instructions given in the PDF document.
Open Source Research Software
AFF3CT 
A Fast Forward Error Correction Toolbox or AFF3CT is a simulator and a library dedicated to the Forward Error Correction (FEC or channel coding). It is written in C++ and it supports a large range of codes: from the well-spread Turbo codes to the new Polar codes including the Low-Density Parity-Check (LDPC) codes. AFF3CT can be used as a command line program and it simulates communication chains based on a Monte Carlo method.
AFF3CT was first intended to be a simulator but as it developed, the need to reuse sub-parts of the code intensified: the library was born. Below is a list of possible applications for the library:
- Build custom communication chains that are not possible with the simulator
- Facilitate hardware prototyping
- Enable various modules to be used in Software-Defined Radio contexts
MIPP 
My Intrinsics++ or MIPP is a portable wrapper for vector intrinsic functions (SIMD) written in C++11. It works for SSE, AVX, AVX-512, ARM NEON and SVE (work in progress) instructions. MIPP wrapper supports simple/double precision floating-point numbers and also signed integer arithmetic (64-bit, 32-bit, 16-bit and 8-bit).
With the MIPP wrapper you do not need to write a specific intrinsic code anymore. Just use provided functions and the wrapper will automatically generates the right intrisic calls for your specific architecture.
Source code »StreamPU 
StreamPU is a Domain Specific Embedded Language (DSEL) for streaming applications. It comes in the form of a C++11 library to link with. Its main features are:
- Definition of dataflow components: modules, tasks and sockets
- Elementary modules and tasks implementations
- Multi-threaded runtime with replication and pipeline parallel constructs
The DSEL is suitable for SDR systems, audio/video processing and more generally it matches single-rate Synchronous DataFlow (SDF) streaming applications. It is used as the multi-threaded runtime of AFF3CT and FMDT.
Source code » Documentation »FMDT 
Fast Meteor Detection Toolbox or FMDT is a software designed to detect meteors. FMDT is foreseen to be applied to airborne camera systems, e.g. in atmospheric balloons or aircraft. It is robust to camera movements by a motion compensation algorithm.
FMDT is ready for real-time processing on small boards like Raspberry Pi 4 or Nvidia Jetson Nano for embedded systems. For instance, on the Raspberry Pi 4 (@ 1.5 GHz), FMDT is able to compute 30 frames per second on a HD video sequence while the instant power is only around 4 Watts.
Source code » Documentation »Teaching
I'm affected to Sorbonne University (UFR d'Ingénierie 919) and to the Polytech Sorbonne engineering school (UFR 933). I am mainly teaching about parallel programming, computers architecture and operating systems.
- MU5IN160 - Parallel Programming for Embedded Architectures (M2) (Moodle 2024 link )
- MU5IN166 - Hot Topics: Evolution of the SIMD ISAs on General Purpose CPUs (M2)
- LU3IN029 - Computer Architecture (L3) (Moodle 2024 link , ressources for the second part of the class )
- LU3IN010 - Principles of Operating Systems (L3)
- EPU-I9-ICH - High Performance Computing (M2) (Moodle 2024 link )
- EPU-N6-IPS - Operating System Fundamentals (L3) (Moodle 2024 link )
Publications
Supervision
Ph.D. Students
- Yacine Idouar (from 2024) - Task scheduling for applications embedded in a nano-satellite and on heterogeneous SoCs. (co-supervised by Prof. Dimitri Galayko and Prof. Lionel Lacassagne )
- Maxime Millet (from 2020) - Approximate optical flow computing on low power SoCs for meteor detection from a nano-satellite. (supervised by Prof. Lionel Lacassagne )
Engineers
Kun He (2019, 1 year) - Development of a MATLAB interface for the AFF3CT C++ library.
Master Internships
- Johannes Laute (2024, 6 months) - Vectorizing PyTorch for RISC-V Vector extension (RVV).
- Yacine Idouar (2024, 6 months) - Heterogeneous tasks for streaming applications running on SoCs with unified memory.
- Enrique Galvez (2024, 5 months) - Study of convolutions for efficient inference of deep neural networks on embedded processors.
- Mathuran Kandeepan (2023, 6 months) - Execution of streaming tasks graph on heterogeneous CPU/GPU architectures with shared memory.
- Clara Ciocan (2023, 6 months) - Improving the robustness of a meteor detection application with a moving camera.
- Nourdinne Hammachi (2023, 2 months) - AFF3CT DSEL extension: support for control flow in a multi-threaded context (pipeline and replication).
- Yacine Idouar (2023, 2 months) - AFF3CT DSEL extension: implement a new type of read & write data ("forward socket").
- Michaël Baudeur (2023, 2 months) - Implementation of an acquisition system for an Ethernet camera using the Aravis API.
- Clara Ciocan & Mathuran Kandeepan (2022, 2 months) - Development of a computer vision application for meteor detection.
- Maël Keryell (2021, 6 months) - Semi-automatic exploration of computational expressions, finding compromise between efficiency and precision.
Bachelor Internships
- Enrique Galvez (2022, 2 months) - Optimizing the execution of an optical flow application on a heterogeneous & parallel architecture.
- Edgar Baucher (2021, 2 months) - Development of a header only C++ library for the RISC-V Vector extension instruction set (RVV).
- Mehdi Naciri (2019, 4 months) - Development of a web application dedicated to displaying, comparing and searching in a database of scientific results.
- Enrique Galvez (2022, 2 months) - Optimizing the execution of an optical flow application on a heterogeneous & parallel architecture.
- Edgar Baucher (2021, 2 months) - Development of a header only C++ library for the RISC-V Vector extension instruction set (RVV).
- Mehdi Naciri (2019, 4 months) - Development of a web application dedicated to displaying, comparing and searching in a database of scientific results.