Sujets de recherche et centres d'intérêt scientifiques

• Sécurité du code face aux attaques par canaux cachés, masquage et tests statistiques
• Calcul haute-performance et algorithmes parallèles
• Architectures Manycore et systèmes d'exploitation associés

Outils

• VerifMSI: Scalable and Efficient Leakage Verification in Masking Scheme Implementations
• MaskedVerifBench: Verification of Benchmarks Composed of Masked Programs
• FastCPA: Fast and Efficient Correlation Power Analysis Computation with a Large Number of Traces

Publications

Journaux Internationaux

• Q. L. Meunier, E. Pons, K. Heydemann, LeakageVerif: Efficient and Scalable Formal Verification of Leakage in Symbolic Expressions, IEEE Transactions on Software Engineering (TSE), 2023
• T. Romera et al., Optical flow algorithms optimized for speed, energy and accuracy on embedded GPUs, in Journal of Real-Time Image Processing (JRTIP), 2023
• A. de Grandmaison, K. Heydemann, Q. L. Meunier, Armistice: Micro-Architectural Leakage Modelling for Masked Software Formal Verification, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022
• P. Vivet et al., IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management, IEEE Journal of Solid-State Circuits, Décembre 2020
• N. Belleville, D. Couroussé, K. Heydemann, Q. Meunier, I. Ben El Ouahma, Maskara: Compilation of a Masking Countermeasure With Optimized Polynomial Interpolation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Juillet 2020
• I. B. E. Ouahma, Q. L. Meunier, K. Heydemann, E. Encrenaz, Side-channel robustness analysis of masked assembly codes using a symbolic approach, Journal of Cryptographic Engineering (JCEN), Mars 2019
• C. Dévigne, J.-B. Bréjon, Q. L. Meunier, F. Wajsbürt, Executing Secured Virtual Machines within a Manycore Architecture, Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Septembre 2016
• Q. L. Meunier and F. Pétrot, Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies, Journal of Parallel and Distributed Computing (JPDC), Octobre 2010
• Q. L. Meunier, F. Pétrot and J.-L. Roch, Hardware/Software Support for Adaptive Work-Stealing in On-Chip Multiprocessor, Journal of Systems Architecture (JSA), Août 2010

Conférences Internationales

• Q. L. Meunier, A. R. Taleb, VerifMSI: Practical Verification of Masking Scheme Implementations, in SECRYPT'23, Rome, Italie
• A. de Grandmaison, K. Heydemann, Q. L. Meunier, Armistice: Micro-Architectural Leakage Modelling for Masked Software Formal Verification, CASES'22, Shanghai, Chine
• N. Belleville, D. Couroussé, E. Encrenaz, K. Heydemann, Q. Meunier, PROSECCO: Formally-Proven Secure Compiled Code, C&ESAR'21
• T. Romera, A. Petreto, F. Lemaitre, M. Bouyer, Q. Meunier, L. Lacassagne, Implementations Impact on Iterative Image Processing for Embedded GPU, EUSIPCO'21
• A. Petreto et al., Real-time embedded video denoiser prototype, Optro'20
• P. Vivet et al., 2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer [...], ISSCC'20, San Francisco, USA
• A. Petreto et al., A New Real-Time Embedded Video Denoising Algorithm, DASIP'19, Montréal, Canada
• A. Hennequin, L. Lacassagne, L. Cabaret, Q. Meunier, A new Direct Connected Component Labeling and Analysis Algorithms for GPUs, DASIP'18, Porto, Portugal
• A. Petreto et al., Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU Architectures, DASIP'18, Porto, Portugal
• E. Guthmüller et al., A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches, ESSCIRC'18, Dresden, Allemagne
• H. Liu, Q. L. Meunier, A. Greiner, Decoupling Translation Lookaside Buffer Coherence from Cache Coherence, ISVLSI'17, Bochum, Allemagne
• M. Karaoui, P.‑Y. Péneau, Q. L. Meunier, F. Wajsbürt, A. Greiner, Exploiting Large Memory using 32-bit Energy-Efficient Manycore Architectures, MCSoC'16, Lyon, France
• C. Dévigne, J.-B. Bréjon, Q. Meunier, F. Wajsbürt, Executing Secured Virtual Machines within a Manycore Architecture, NORCAS'15, Oslo, Norvège
• H. Liu, C. Dévigne, L. Garcia, Q. Meunier, F. Wajsbürt, A. Greiner, RWT: Suppressing Write-Through Cost When Coherence is Not Needed, ISVLSI'15, Montpellier, France
• J.-C. Naud, Q. Meunier, D. Ménard, O. Sentieys, Fixed-point Accuracy Evaluation in the Context of Conditional Structures, EUSIPCO '11, Barcelone, Espagne
• Q. Meunier and F. Pétrot, Lightweight Transactional Memory Systems for Large Scale Shared Memory MPSoCs, NEWCAS'09, Toulouse, France

Workshops Internationaux

• Q. L. Meunier, I. B. E. Ouahma, K. Heydemann, SELA: a Symbolic Expression Leakage Analyzer, in PROOFS'20
• Q. L. Meunier, FastCPA: Efficient Correlation Power Analysis Computation with a Large Number of Traces, in CS2'19, Valence, Espagne
• J.-B. Bréjon, K. Heydemann, E. Encrenaz, Q. Meunier, S. T. Vu, Fault attack vulnerability assessment of binary code, in CS2'19, Valence, Espagne
• Q. L. Meunier, Y. Thierry-Mieg, E. Encrenaz, Modeling a Cache Coherence Protocol with the Guarded Action Language, in MARS'18, Thessalonique, Grèce
  
• I. B. E. Ouahma, Q. L. Meunier, K. Heydemann, E. Encrenaz, Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes, in PROOFS'17 Taipei, Taiwan

Journaux Nationaux

• M. L. Karaoui, Q. L. Meunier, F. Wajsbürt and A. Greiner, GECOS : Mécanisme de synchronisation passant à l’échelle à plusieurs lecteurs et un écrivain pour structures chaînées, in: Technique et Science Informatiques (TSI), 2015
• Q. L. Meunier and F. Pétrot, Systèmes de mémoire transactionnelle pour les architectures à base de NoCs : conception, implémentation et comparaison de deux politiques, in Technique et Science Informatiques (TSI), 2011

Conférences Nationales

• A. Petreto et al., Débruitage vidéo temps réel sur systèmes embarqués pour caméras hautes performances, in ComPAS'19 Anglet, France
• A. Petreto et al., Comparaison de la consommation énergétique et du temps d'exécution d'un algorithme de traitement d'images optimisé sur des architectures SIMD et GPU, in ComPAS'18, Toulouse, France
• M. L. Karaoui, Q. L. Meunier, F. Wajsbürt and A. Greiner, Mécanisme de synchronisation scalable à plusieurs lecteurs et un écrivain, in ComPAS'14, Neuchatel, Suisse
• J.-C. Naud, Q. Meunier, D. Ménard and Olivier Sentieys, Évaluation de la précision en virgule fixe dans le cas des structures conditionnelles, in SympA'11, Saint-Malo, France
• Q. Meunier and F. Pétrot, LightTM : une Mémoire Transactionnelle conçue pour les MPSoCs, in SympA'09, Toulouse