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Free and Open Source Standard Cell Existing Libraries

Date: 31 august 2023 initial version
Authors: Marie-Minerve Louerat
Contact: <Marie-Minerve.Louerat@lip6.fr>
Version: v.07.02.2024

FOSS Standard Cells

In this page, LIP6, CIAN Team, wishes to present a survey of the existing open-source standard-cell libraries Wikipedia page on Standard Cells . This study is part of the GoIT project. The GoIT project has received funding from the European Union’s Horizon Europe research and innovation programme under grant agreement No 101070660.

This page will be regularly updated, since new Open PDK projects are ongoing Wikipedia page on PDK.

Different formats and views

A library of Standard Cells provides different descriptions (or views) of each cell. These descriptions are based on different formats and languages. To be compliant with a digital design flow, a cell has to provide at least 3 views:

  • Logical level model. It is the model of the functional behaviour represented by a boolean logic function. The model uses the VHDL or the Verilog language. The cell's logic function, with timing characterization, is used for logic synthesis of a digital circuit. The behavioural model is compatible with event driven simulator for functional verification of a digital circuit. The interface of the cell model (input, output) is used by the place and root operation in the circuit design flow (i.e. circuit layout);
  • Transistor level netlist. It is the description of the interconnection of the set of transistors required to generate the logic behavior. It is written in spice format. This model is compatible with transistor-level simulation with ngspice, which may be used for timing characterization of the cell;
  • Layout description. It is written according to the GDSII format. It is used by place and route software tools to create the layout of the digital circuit that will be sent by the designer for fabrication in a foundry.

Depending on the cell use, other descriptions may also be required:

  • Schematic representation of the boolean logic function, for circuit schematic capture;
  • Layout and design abstract information (Lef, Def), used by place and route software tools;
  • Timing information, Liberty file (lib), used by logic synthesizers and static timing analyzers;
  • Post-layout transistor spice netlist including parasitics, used by static timing analyzer and performance estimation (power, timing, area) tools.
Symbol nand2 nq <= not (i0 and i1);

.subckt nand2_x0 vdd vss nq i0 i1

Mn0 int0 i0 vss vss sky130_fd_pr__nfet_01v8__model l=0.15um w=2.0um

Mp0 nq i0 vdd vdd sky130_fd_pr__pfet_01v8__model l=0.15um w=2.0um

Mn1 nq i1 int0 vss sky130_fd_pr__nfet_01v8__model l=0.15um w=2.0um

Mp1 nq i1 vdd vdd sky130_fd_pr__pfet_01v8__model l=0.15um w=2.0um

.ends nand2_x0

 Layout nand2
Icon Nand2 Boolean Function Nand2 Transistor Level Netlist (spice) example of a Nand2 (SkyWater130 PDK) Nand2 Layout example

Nand2 different views

Layout Design approaches

Different approaches are used to generate the layout of standard cells, which are:

  • Custom design. For each target process, the layout is edited from scratch with the help of a layout editor and a Design Rule Checker (DRC), such as KLayout. See Real column in the figure below.
  • Scalable design. The layout is generated for each target process. The designer of the cell provides a procedural description of the layout (Python scripts can be used). See PDKMaster column in the figure below.
  • Symbolic approach. Symbolic Layout is a way of making the layout of a chip independent of the target technological node. Symbolic layout is created by drawing the polygons in a blank unit called the lambda. Then, the value of the lambda is calculated for the target technology so that the layout fits its particular design rules. The symbolic layout is translated to real layout, according to the lambda value. This approach was first introduced by Mead and Conway. The symbolic layout allows the designer to show a physical view even when the PDK, and its associated Design Rules Manual (DRM), are distributed subject to NDA. Note that to be used for logical synthesis, and static timing-analysis, a timing-characterization operation of the standard cells has to be performed for the target process. See LSXlib at cell level or Symbolic column at chip level in the figure below.
Different approaches
The different approaches, from left to right, whole symbolic design, LSXLiB: using a simple transformation to go to real sizes at cell level, PDKMaster: scalable approach, layout generated from stick diagram, Real: cell layout edited as real, custom design

References

Books

  • Carver Mead and Lynn Conway (1980). Introduction to VLSI systems. Reading, Mass.: Addison-Wesley. ISBN 0201043580. OCLC 4641561.
  • Computer Aids for VLSI Design, Steven M. Rubin, 1994,
  • Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits, Analysis and Design, Mac Graw Hill, 2003.
  • Yannis Tsividis and Colin McAndrew, Operation and Modeling of the MOS Transistor, Third edition, Oxford University Press, 2011.
  • Yuhua Cheng and Chenming Hu, MOSFET modeling and BSIM3 User's guide, Kluwer Academic Publisher, 1999.
  • Jan M. Rabey, Anantha Chandrakasan and Borivoje Nikolic, Digital Integrated Circuits, A design perspective, Prentice Hall, 2003
  • Naveed Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publisher, 2004
  • Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, (2001)
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