| | 1 | {{{ |
| | 2 | -- Additionneur 4 bits avec report entrant et sortant |
| | 3 | |
| | 4 | ENTITY adder IS |
| | 5 | PORT ( |
| | 6 | i0 : IN BIT_VECTOR(3 DOWNTO 0); |
| | 7 | i1 : IN BIT_VECTOR(3 DOWNTO 0); |
| | 8 | q : OUT BIT_VECTOR(3 DOWNTO 0); |
| | 9 | cin : IN BIT; |
| | 10 | cout : OUT BIT; |
| | 11 | vdd : IN BIT; |
| | 12 | vss : IN BIT |
| | 13 | ); |
| | 14 | END adder; |
| | 15 | |
| | 16 | ARCHITECTURE vbe OF adder IS |
| | 17 | |
| | 18 | SIGNAL carry : BIT_VECTOR(4 DOWNTO 0) ; |
| | 19 | |
| | 20 | BEGIN |
| | 21 | |
| | 22 | carry(0) <= cin; |
| | 23 | carry(4 DOWNTO 1) <= ( ( i1(3 DOWNTO 0) AND i0(3 DOWNTO 0) ) OR |
| | 24 | ( i0(3 DOWNTO 0) AND carry(3 DOWNTO 0) ) OR |
| | 25 | ( carry(3 DOWNTO 0) AND i1(3 DOWNTO 0) ) ) ; |
| | 26 | q <= i0 XOR i1 XOR carry(3 DOWNTO 0) ; |
| | 27 | cout <= carry(2); |
| | 28 | |
| | 29 | END; |
| | 30 | }}} |