Cours Methodologie de Conception VLSI
Transparents des cours (téléchargeables en format .pdf)
- C1: Modélisation comportementale
- C2: Schémas hiérarchiques multi-niveaux
- C3: Automates synchrones
- C4: Outils de synthèse et bibliothèques
- C5: Placement & routage
- C6: Contrôle du placement
- C7: Test des circuits intégrés VLSI
- C8: Evolutions actuelles
Textes des TP
- TP1 : Modélisation comportementale VHDL data-flow
- TP2 : Modélisation structurelle VHDL
- TP3 : Bibliothèque de cellules pré-caractérisées
- TP4 : Débogage du modèle comportemental du composant Am2901
Annales d'examen (téléchargeables en format .pdf)
Last modified
18 years ago
Last modified on Nov 4, 2007, 11:53:40 AM
Attachments (12)
- C4_libraries.pdf (276.0 KB ) - added by 18 years ago.
- C6_floor-plan.pdf (752.5 KB ) - added by 18 years ago.
- C5_clock_alim.pdf (728.3 KB ) - added by 18 years ago.
- C7_test.pdf (494.0 KB ) - added by 18 years ago.
- C8_tendances.pdf (90.1 KB ) - added by 18 years ago.
- examen-METHO-2005-jan.pdf (70.3 KB ) - added by 18 years ago.
- examen-METHO-2006-jan.pdf (68.7 KB ) - added by 18 years ago.
- examen-METHO-2006-nov.pdf (53.0 KB ) - added by 18 years ago.
- examen-METHO-2007-mars.pdf (93.0 KB ) - added by 18 years ago.
- C1_vbe.pdf (2.4 MB ) - added by 17 years ago.
- C2_vst.pdf (129.2 KB ) - added by 17 years ago.
- C3_automates.pdf (148.8 KB ) - added by 17 years ago.
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