CEA-LETI
LETI (Laboratory for Electronics & Information Technology) is operated by the Technology Department of CEA (DRT "Direction de la Recherche Technologique"), the French Atomic Energy Commission. LETI is one of the largest European applied research laboratories in the field of electronics: permanent staff is approximately 1200 people. The main activities of CEA/LETI are dealing with electronics, microelectronics, microsystems and IC design.
Its corporate goal is to bring technological innovation to the European industry, and to create added value through an active Intellectual Property policy based on the management of strong patent portfolio (> 500 active patents, and more than 140 filings/year) and the licensing of its technologies. For more than ten years, LETI has been working on wireless systems for several applications fields: medical (indoor), military (outdoor), robotics, mobiles phones and communications with mobiles (cars, trains, underground, etc.). LETI is currently involved in several R&D telecom project of the 6th Framework.
The DCIS Department (DCIS: "Conception et Intégration des Systèmes") at LETI is in charge of the IC design activities, and is currently addressing the following topics:
- digital and mixed chip design for telecom, smart cards, RFID, image processing, smart devices, etc.
- architecture exploration (HW/SW partitioning, performance evaluation, etc.)
- design flow methodology (SystemC/TLM methodology, XML/Spirit, Matlab/Simulink? co simulation, etc).
An important concern at LETI is the design of mixed signal, multi-physics systems with sensors/activators (MEMS, MOEMS, etc.), RF front-end and complex SOC design and architecture.
LETI is now reference as a world wide key actor in the field of network on chip (NOC) architecture: refer to LETI papers at the ISSCC'07 conference. An innovative Software Defined Radio platform based on fully distributed communication and control system has been designed. This architecture framework is targeting complex data flow applications. The backbone of the architecture is a layered asynchronous NOC that brings scalability at architecture level and flexibility at the application level. Silicon proves these concepts, and is currently used for complex Radio Access technology experimentation.
LETI is developing a new complex MPSoC architecture for data streaming applications. This architecture will be designed on advanced CMOS 65nm technology. For this MPSoC, LETI we will have to answer issues of dynamic application mapping and power optimisation under real time constraints. LETI expect to take benefit from the ADAM project and partnership on the following points:
- applying programming models for distributed and parallel architectures,based on LIP6 experience
- taking benefit from dynamic mapping strategies to support dynamic reconfiguration for interoperability, and power optimisation by tasks allocation and voltage/frequency scaling, based on LIP6 and LIRMM experiences
- evaluating the applicability on realistic application scenarios of distributed adaptive and recursive mapping strategies for parallel MPSoC architectures
Fabien CLERMIDY was born in Bourg-en-Bresse, France, in 1971. He received the Electronic Engineering Diploma from ENSIMEV in 1994 and his Ph.D. Degree in Microelectronics from the National Polytechnic Institute of Grenoble, France, in 1999.In 2000, he joined the CEA-LIST laboratory in Paris. He was involved in the design of an application specific parallel computer as designer. In 2003, he moved to the CEA-LETI in the Center for Innovation in micro & nanotechnology (MINATEC), Grenoble. From 2003 to 2006, he was the architect of the FAUST NoC structure and was in charge of chip verification. In 2006, he took the lead of the FAUST2 project for software and cognitive radio. He has published 11 papers in conferences. He holds 8 patents in the fields of fault-tolerant architectures, cryptography, NoC architectures, GALS structures and molecular electronics.
Edith BEIGNE was born in Lamastre, France, in 1975. She received the Electronic Engineering Diploma from the National Polytechnic Institute of Grenoble, France, in 1998. In 1998, she joined the CEA/LETI laboratory in the Center for Innovation in micro & nanotechnology (MINATEC), Grenoble. She was first involved in contactless RFID mixed signal systems. In 2001, she began the asynchronous logic design activity in cryptographic and contactless systems. As regards the development of the FAUST project, she designed a part of the asynchronous Network-On-Chip. Since 2006, she has been in charge of ALPIN project, a power aware GALS SoC implementing dynamic and static low power techniques based on an asynchronous NoC.
Christian BERNARD was born in 1956, and received its engineer degree at ENSIMAG (Ecole Nationale Superieure d’Informatique et Mathematiques appliquées de Grenoble) in 1979. He was formerly designer and architect at Bull (Les Clayes sous Bois, France) and participated to the design of the Bull Mainframes during 19 years. He joined MINATEC-LETI in October 2001, and was project leader and designed several chips and reconfigurables blocks for telecom applications.
François BERTRAND received a PhD degree in Microelectronics and Integrated Circuits Design from INPG (Polytechnics Institute at Grenoble). He worked as a researcher at the INPG/TIMA laboratory, as a senior project engineer in a private company for the design of very complex integrated circuits (BULL mainframe), and joined CEA/LETI in 1988. At CEA/LETI, he has successively the head of the Architecture and Integrated Programs of LETI, Director of JESSI programs on microelectronics for SMEs, and the head of the IAN laboratory at MINATEC/LETI since 1996. The IAN laboratory (30 permanent staff members) is developing digital integrated
LIP6
Université Pierre et Marie Curie – Paris 6 (UPMC) is one of the largest universities teaching science and medicine in France, and indeed in Europe, with 4000 researchers and teaching academics/researchers, 180 laboratories, and some 30 000 students including 8000 in postgraduate studies. UPMC is based in the Latin Quarter in Paris. The LIP6 Laboratory is part of UPMC and is one of the most important centers of Computer Science in France (450 permanent researchers and Phd). The SoC & Embedded Systems Department of LIP6 has about 60 employees (25 permanent researchers) working on all the main areas of research in the domain of Massively Parallel Multiprocessor Systems on Chips including analogue components for multimedia/telecom applications.
The reference hardware architecture at LIP6, SMARTIS (Shared Memory Architecture with Reconfiguration and Testability Integrated Services), is based on a two-level interconnect and relies on shared memory for IPs intercommunications. The first interconnect level, called global interconnect, is a two-dimensional mesh of subsystems. A subsystem contains a local interconnect (bus or crossbar) that connects up to 4 pipelined scalar 32-bit processors with integrated caches, up to 4 local memories (100Kbytes per susbsystem), and all the necessary peripherals. A key point in this architecture is the presence in a subsystem of an embedded test processor, which function is to fetch test instruction and data from memory (eventually outside the SoC) and execute them at SoC speed. This feature allows for online self-test and prevents the need from costly external test equipments.
All the components of SMARTIS belong to the SoCLib library, a collection of interoperable simulation models for the design of MP2SoCs. SocLib? is supported by an ANR platform project since December 2006. Interoperability is ensured by means of the VCI/OCP protocol used to interconnect initiators and targets.
To answer the issues of permanent failures in a MP2SoC, LIP6 intends to take the opportunity of the ADAM project to work on two key issues:
- Extensive use of the embedded test processor in each subsystem to trigger a thorough test of the MP2SoC on a periodic scheme or in reaction to a failed CRC test in the running application
- Embed the remapping functionality onto the SoC. This implies the development of a static task placement algorithm, the modification of the routing parameters in the global routers and local interconnects, as well as an embedded application linker. With this approach, it is possible for the MP2SoC to self adapt the application to its downgraded architecture without any modification of the original firmware, considered as a collection and precompiled object files and link directives.
François PECHEUX is an Assistant Professor at the « University Pierre et Marie Curie », in Paris. He received a PhD in Electronic Engineering and Computer Science in 1992, and since 2002 is member of the LIP6 Laboratory, in the « Embedded Systems » team. His main research activity focuses on the efficient modelling and simulation of very complex Massively Parallel MultiProcessor? Systems on Chip. In particular, he participates in the development of a promising parallelizable simulation technique for Transaction Level Modeling with Timing (TLM/T) platforms (speedup x 20). He is also an active member of the SoCLib project, funded by ANR 2006, and works on power consumption and securized IPs in SoCs?.
Mounir BENABDENBI is an Assistant Professor at the « University Pierre et Marie Curie », in Paris. He received a PhD in Electronic Engineering and Computer Science in 2002, and since 2003 is member of the LIP6 Laboratory, in the « Embedded Systems » team. He heads the test and reliability research group, and has developed an innovative method for online MPSoC testing. He is also working on specific MP2SoC systems for automotive (obstacle detection), containing more than 30 32-bit processors
Franck WAJSBURT is an Assistant Professor at the « University Pierre et Marie Curie », in Paris. He has a PhD in Electronic Engineering and Computer Science, and is member of the LIP6 Laboratory, in the « Embedded Systems » team. He has experience in the design of high performance superscalar processors and in the design of real time operating systems and heterogeneous micro-kernels involving DSPs and different brands of processors.
Alain GREINER is a Professor at the « University Pierre et Marie Curie », in Paris. He is vice-director of the LIP6 Laboratory, and runs the « Embedded Systems » team. He participated in the design of one of the first Network on Chip, SPIN, and currently focuses its research activity on ASPIN, “Asynchronous SPIN”, A Network on Chip suited for GALS Architecture. He also runs the technical part of the SocLib? project.
LIRMM
The LIRMM (Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier) is a research institute, jointly supported by the University of Montpellier II and the CNRS (French National Center for Scientific Research). It is composed of three research departments (fundamental computer sciences and applications, robotics, microelectronics), and consists of around 330 persons. The Microelectronics Department of the LIRMM has a 24 permanent staff members and around 35 Ph.D. students. It is involved in the research areas of flexible architectures and system level architecture, physical design, circuit testing and MEMs. The department has permanent relationships with the national and international scientific communities, and main semiconductor companies.
The flexible parallel and reconfigurable architectures group staff participates to this proposal and has an almost decade-long experience in reconfigurable technologies design. This group is composed of 5 permanent researchers and 8 Ph.D. students; it holds focus on emerging dynamic and self-organizing reconfigurable fabrics for various application domains, like balanced reconfigware/software systems, Networks on Chip, automatic task mapping and loop unrolling on reconfigurable systems.
HS-Scale is a hardware/software framework developed at the LIRMM to study, define and experiment scalable solutions for next generation MP2SOC. The hardware architecture, H-Scale, is a homogeneous MP2-SOC based on RISC processors, distributed memories and a Globally Asynchronous / Locally Synchronous Network on Chip. S-Scale is the software support to program H-Scale. It is a multi-threaded sequential programming model with dedicated communication primitives handled at run-time by a simple Operating System. The hardware validations on FPGA and CMOS 90nm technology and the experimental case studies on several applications (FIR, DES and MJPEG) have demonstrated the scalability of this approach and draws interesting perspectives to enable task self-placement and duplication.
The LIRMM expects the following outcome from the research conducted in collaboration within the confine of the ADAM project:
- Based on the experience of the LIP6/LETI, we intend to evaluate the benefits of the currently developed dynamic mapping strategies on both reliability aspects (fault tolerance) and physical aspects (dynamic frequency / voltage scaling) on realistic application scenarios
- Evaluate the opportunity of distributed adaptive / recursive mapping strategies for massively parallel MP2SoC architectures. These strategies are based on statistical analysis of remapping actions that have been taken, and therefore help refining the future decisions to be made.
Gilles SASSATELLI holds a full-time researcher position at CNRS and is responsible of the flexible parallel and reconfigurable architectures group. He obtained his Ph.D. in 2002 in Microelectronics and has been working at the Darmstadt University of Technology, Germany as an assistant professor. He has been involved in many different funded national and European projects and is the founder of the ReCoSoC European workshop focusing on reconfigurable technologies in a SoC context. His main research activity aims at bringing parallel reconfigurable computing devices to a new level of performance through exploring phy- and bio-inspired features for achieving self-organization of spatial computation elements.
Lionel TORRES received his PhD degree in microelectronics from the University of Montpellier II in 199.Between 1996 and 1997 he has worked at the ATMEL industry as a design engineer. After that he became assistant professor at the Polytech’Montpellier. He is currently a professor at the Université Montpellier II and a researcher at the LIRMM lab. He has scientific interest in microelectronic architectures for digital signal processing and dynamic reconfigurable architectures. He has publications in the main international conferences in microelectronics design area. Lionel Torres also participate as program committee member in several international conferences and he is currently deputy director of the LIRMM Microelectronic department.
Pascal BENOIT received a Master Degree in Microelectronics and Automated Systems from the University of Montpellier, France, in 2001. He obtained his PhD degree in Computer Engineering from the University of Montpellier in 2004. In November 2004, he joined the department of Electrical Engineering at the University of Karlsruhe in Germany where he worked as scientific assistant. Since September 2005, Dr. BENOIT has moved to the University of Montpellier in France as Associate Professor and Associate researcher of the Flexible Architectures Group of the LIRMM microelectronic research department.
