| | 22 | |
| | 23 | ---- |
| | 24 | |
| | 25 | = LIP6 = |
| | 26 | |
| | 27 | [[Image(htdocs:logos/logo_lip6.png)]] |
| | 28 | |
| | 29 | Université Pierre et Marie Curie – Paris 6 (UPMC) is one of the largest universities teaching science and medicine in France, and indeed in Europe, with 4000 researchers and teaching academics/researchers, 180 laboratories, and some 30 000 students including 8000 in postgraduate studies. UPMC is based in the Latin Quarter in Paris. The LIP6 Laboratory is part of UPMC and is one of the most important centers of Computer Science in France (450 permanent researchers and Phd). The SoC & Embedded Systems Department of LIP6 has about 60 employees (25 permanent researchers) working on all the main areas of research in the domain of Massively Parallel Multiprocessor Systems on Chips including analogue components for multimedia/telecom applications. |
| | 30 | |
| | 31 | The reference hardware architecture at LIP6, SMARTIS (Shared Memory Architecture with Reconfiguration and Testability Integrated Services), is based on a two-level interconnect and relies on shared memory for IPs intercommunications. The first interconnect level, called global interconnect, is a two-dimensional mesh of subsystems. A subsystem contains a local interconnect (bus or crossbar) that connects up to 4 pipelined scalar 32-bit processors with integrated caches, up to 4 local memories (100Kbytes per susbsystem), and all the necessary peripherals. A key point in this architecture is the presence in a subsystem of an embedded test processor, which function is to fetch test instruction and data from memory (eventually outside the SoC) and execute them at SoC speed. This feature allows for online self-test and prevents the need from costly external test equipments. |
| | 32 | |
| | 33 | All the components of SMARTIS belong to the SoCLib library, a collection of interoperable simulation models for the design of MP2SoCs. SocLib is supported by an ANR platform project since December 2006. Interoperability is ensured by means of the VCI/OCP protocol used to interconnect initiators and targets. |
| | 34 | |
| | 35 | To answer the issues of permanent failures in a MP2SoC, LIP6 intends to take the opportunity of the ADAM project to work on two key issues: |
| | 36 | * Extensive use of the embedded test processor in each subsystem to trigger a thorough test of the MP2SoC on a periodic scheme or in reaction to a failed CRC test in the running application |
| | 37 | * Embed the remapping functionality onto the SoC. This implies the development of a static task placement algorithm, the modification of the routing parameters in the global routers and local interconnects, as well as an embedded application linker. With this approach, it is possible for the MP2SoC to self adapt the application to its downgraded architecture without any modification of the original firmware, considered as a collection and precompiled object files and link directives. |
| | 38 | |
| | 39 | ---- |
| | 40 | |
| | 41 | = LIRMM = |
| | 42 | |
| | 43 | [[Image(htdocs:logos/logo_lirmm.png)]] |
| | 44 | |
| | 45 | The LIRMM (Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier) is a research institute, jointly supported by the University of Montpellier II and the CNRS (French National Center for Scientific Research). It is composed of three research departments (fundamental computer sciences and applications, robotics, microelectronics), and consists of around 330 persons. |
| | 46 | The Microelectronics Department of the LIRMM has a 24 permanent staff members and around 35 Ph.D. students. It is involved in the research areas of flexible architectures and system level architecture, physical design, circuit testing and MEMs. The department has permanent relationships with the national and international scientific communities, and main semiconductor companies. |
| | 47 | |
| | 48 | The flexible parallel and reconfigurable architectures group staff participates to this proposal and has an almost decade-long experience in reconfigurable technologies design. This group is composed of 5 permanent researchers and 8 Ph.D. students; it holds focus on emerging dynamic and self-organizing reconfigurable fabrics for various application domains, like balanced reconfigware/software systems, Networks on Chip, automatic task mapping and loop unrolling on reconfigurable systems. |
| | 49 | |
| | 50 | HS-Scale is a hardware/software framework developed at the LIRMM to study, define and experiment scalable solutions for next generation MP2SOC. The hardware architecture, H-Scale, is a homogeneous MP2-SOC based on RISC processors, distributed memories and a Globally Asynchronous / Locally Synchronous Network on Chip. S-Scale is the software support to program H-Scale. It is a multi-threaded sequential programming model with dedicated communication primitives handled at run-time by a simple Operating System. |
| | 51 | The hardware validations on FPGA and CMOS 90nm technology and the experimental case studies on several applications (FIR, DES and MJPEG) have demonstrated the scalability of this approach and draws interesting perspectives to enable task self-placement and duplication. |
| | 52 | |
| | 53 | The LIRMM expects the following outcome from the research conducted in collaboration within the confine of the ADAM project: |
| | 54 | * Based on the experience of the LIP6/LETI, we intend to evaluate the benefits of the currently developed dynamic mapping strategies on both reliability aspects (fault tolerance) and physical aspects (dynamic frequency / voltage scaling) on realistic application scenarios |
| | 55 | * Evaluate the opportunity of distributed adaptive / recursive mapping strategies for massively parallel MP2SoC architectures. These strategies are based on statistical analysis of remapping actions that have been taken, and therefore help refining the future decisions to be made. |
| | 56 | |
