[1] | 1 | /* |
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| 2 | * hal_context.c - implementation of Thread Context API for TSAR-MIPS32 |
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| 3 | * |
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| 4 | * Author Alain Greiner (2016) |
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| 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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| 24 | #include <hal_types.h> |
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[317] | 25 | #include <hal_switch.h> |
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[1] | 26 | #include <memcpy.h> |
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| 27 | #include <thread.h> |
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| 28 | #include <string.h> |
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| 29 | #include <process.h> |
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[8] | 30 | #include <printk.h> |
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[1] | 31 | #include <vmm.h> |
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| 32 | #include <core.h> |
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| 33 | #include <cluster.h> |
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| 34 | #include <hal_context.h> |
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| 35 | |
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[151] | 36 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 37 | // Define various SR values for TSAR-MIPS32 |
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| 38 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 39 | |
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| 40 | #define SR_USR_MODE 0xFC11 |
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| 41 | #define SR_USR_MODE_FPU 0x2000FC11 |
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| 42 | #define SR_SYS_MODE 0xFC00 |
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| 43 | |
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| 44 | ///////////////////////////////////////////////////////////////////////////////////////// |
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[296] | 45 | // These structuree defines the cpu_context anf fpu_context for TSAR MIPS32. |
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[151] | 46 | // These registers are saved/restored at each context switch. |
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[296] | 47 | // WARNING : update the hal_***_context_save() and hal_***_context_restore() |
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| 48 | // functions when modifying this structure, and check the two |
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| 49 | // CONFIG_CPU_CTX_SIZE & CONFIGFPU_CTX_SIZE configuration parameterss. |
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[151] | 50 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 51 | |
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| 52 | typedef struct hal_cpu_context_s |
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| 53 | { |
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[296] | 54 | uint32_t c0_epc; // slot 0 |
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| 55 | uint32_t at_01; // slot 1 |
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| 56 | uint32_t v0_02; // slot 2 |
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| 57 | uint32_t v1_03; // slot 3 |
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| 58 | uint32_t a0_04; // slot 4 |
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| 59 | uint32_t a1_05; // slot 5 |
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| 60 | uint32_t a2_06; // slot 6 |
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| 61 | uint32_t a3_07; // slot 7 |
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| 62 | |
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| 63 | uint32_t t0_08; // slot 8 |
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| 64 | uint32_t t1_09; // slot 9 |
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| 65 | uint32_t t2_10; // slot 10 |
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| 66 | uint32_t t3_11; // slot 11 |
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| 67 | uint32_t t4_12; // slot 12 |
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| 68 | uint32_t t5_13; // slot 13 |
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| 69 | uint32_t t6_14; // slot 14 |
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| 70 | uint32_t t7_15; // slot 15 |
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| 71 | |
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| 72 | uint32_t s0_16; // slot 16 |
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| 73 | uint32_t s1_17; // slot 17 |
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| 74 | uint32_t s2_18; // slot 18 |
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| 75 | uint32_t s3_19; // slot 19 |
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| 76 | uint32_t s4_20; // slot 20 |
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| 77 | uint32_t s5_21; // slot 21 |
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| 78 | uint32_t s6_22; // slot 22 |
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| 79 | uint32_t s7_23; // slot 23 |
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| 80 | |
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| 81 | uint32_t t8_24; // slot 24 |
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| 82 | uint32_t t8_25; // slot 25 |
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| 83 | uint32_t hi_26; // slot 26 |
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| 84 | uint32_t lo_27; // slot 27 |
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| 85 | uint32_t gp_28; // slot 28 |
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| 86 | uint32_t sp_29; // slot 29 |
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| 87 | uint32_t fp_30; // slot 30 |
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| 88 | uint32_t ra_31; // slot 31 |
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| 89 | |
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| 90 | uint32_t c2_ptpr; // slot 32 |
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| 91 | uint32_t c2_mode; // slot 33 |
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| 92 | |
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| 93 | uint32_t c0_sr; // slot 34 |
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| 94 | uint32_t c0_th; // slot 35 |
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[151] | 95 | } |
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| 96 | hal_cpu_context_t; |
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| 97 | |
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| 98 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 99 | // This structure defines the fpu_context for TSAR MIPS32. |
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| 100 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 101 | |
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| 102 | typedef struct hal_fpu_context_s |
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| 103 | { |
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| 104 | uint32_t fpu_regs[32]; |
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| 105 | } |
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| 106 | hal_fpu_context_t; |
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| 107 | |
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[296] | 108 | |
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| 109 | |
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| 110 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 111 | // CPU context access functions |
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| 112 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 113 | |
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| 114 | |
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| 115 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 116 | // Seven registers are initialised by this function: |
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| 117 | // GPR : sp_29 / fp_30 / ra_31 |
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| 118 | // CP0 : c0_sr / c0_th |
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| 119 | // CP2 : c2_ptpr / c2_mode |
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| 120 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 121 | error_t hal_cpu_context_create( thread_t * thread ) |
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[1] | 122 | { |
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| 123 | kmem_req_t req; |
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| 124 | |
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[8] | 125 | context_dmsg("\n[INFO] %s : enters for thread %x in process %x\n", |
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| 126 | __FUNCTION__ , thread->trdid , thread->process->pid ); |
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| 127 | |
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[1] | 128 | // allocate memory for cpu_context |
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[8] | 129 | req.type = KMEM_CPU_CTX; |
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[1] | 130 | req.size = sizeof(hal_cpu_context_t); |
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| 131 | req.flags = AF_KERNEL | AF_ZERO; |
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| 132 | |
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| 133 | hal_cpu_context_t * context = (hal_cpu_context_t *)kmem_alloc( &req ); |
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| 134 | if( context == NULL ) return ENOMEM; |
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| 135 | |
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| 136 | // set cpu context pointer in thread |
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| 137 | thread->cpu_context = (void*)context; |
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| 138 | |
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| 139 | // stack pointer, status register and mmu_mode depends on thread type |
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| 140 | uint32_t sp_29; |
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| 141 | uint32_t c0_sr; |
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| 142 | uint32_t c2_mode; |
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| 143 | if( thread->type == THREAD_USER ) |
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| 144 | { |
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| 145 | sp_29 = ((uint32_t)thread->u_stack_base) + thread->u_stack_size; |
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| 146 | c0_sr = SR_USR_MODE; |
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| 147 | c2_mode = 0xF; |
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| 148 | } |
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| 149 | else |
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| 150 | { |
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| 151 | sp_29 = ((uint32_t)thread->k_stack_base) + thread->k_stack_size; |
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| 152 | c0_sr = SR_SYS_MODE; |
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| 153 | c2_mode = 0x3; |
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| 154 | } |
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| 155 | |
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| 156 | // align stack pointer on a double word boundary |
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| 157 | sp_29 = (sp_29 - 8) & (~ 0x7); |
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| 158 | |
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| 159 | // initialise context |
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| 160 | context->sp_29 = sp_29; |
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| 161 | context->fp_30 = sp_29; // TODO check this [AG] |
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| 162 | context->ra_31 = (uint32_t)thread->entry_func; |
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| 163 | context->c0_sr = c0_sr; |
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| 164 | context->c0_th = (uint32_t)thread; |
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| 165 | context->c2_ptpr = (uint32_t)((thread->process->vmm.gpt.ppn) >> 1); |
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| 166 | context->c2_mode = c2_mode; |
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| 167 | |
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[296] | 168 | context_dmsg("\n[INFO] %s : exit for thread %x in process %x / ra = %x\n", |
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| 169 | __FUNCTION__ , thread->trdid , thread->process->pid , context->ra_31 ); |
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[8] | 170 | |
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[1] | 171 | return 0; |
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| 172 | } // end hal_cpu_context_create() |
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| 173 | |
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[296] | 174 | ///////////////////////////////////////////////// |
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| 175 | void hal_cpu_context_display( thread_t * thread ) |
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| 176 | { |
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| 177 | hal_cpu_context_t * ctx = (hal_cpu_context_t *)thread->cpu_context; |
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| 178 | |
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[317] | 179 | printk("\n***** cpu_context for thread %x in cluster %x / ctx = %x\n" |
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[296] | 180 | " gp_28 = %X sp_29 = %X ra_31 = %X\n" |
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| 181 | " c0_sr = %X c0_epc = %X c0_th = %X\n" |
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| 182 | " c2_ptpr = %X c2_mode = %X\n", |
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| 183 | thread->trdid, local_cxy, ctx, |
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| 184 | ctx->gp_28 , ctx->sp_29 , ctx->ra_31, |
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| 185 | ctx->c0_sr , ctx->c0_epc , ctx->c0_th, |
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| 186 | ctx->c2_ptpr , ctx->c2_mode ); |
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| 187 | |
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[317] | 188 | } // end hal_context_display() |
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| 189 | |
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| 190 | /* |
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| 191 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 192 | // This static function makes the actual context switch. |
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| 193 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 194 | static void hal_do_switch( hal_cpu_context_t * ctx_old, |
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| 195 | hal_cpu_context_t * ctx_new ) |
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[296] | 196 | { |
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| 197 | asm volatile( |
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[317] | 198 | ".set noat \n" |
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| 199 | ".set noreorder \n" |
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| 200 | "move $26, %0 \n" |
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[296] | 201 | |
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[317] | 202 | "mfc0 $27, $14 \n" |
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| 203 | "sw $27, 0*4($26) \n" |
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[296] | 204 | |
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[317] | 205 | "sw $1, 1*4($26) \n" |
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| 206 | "sw $2, 2*4($26) \n" |
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| 207 | "sw $3, 3*4($26) \n" |
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| 208 | "sw $4, 4*4($26) \n" |
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| 209 | "sw $5, 5*4($26) \n" |
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| 210 | "sw $6, 6*4($26) \n" |
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| 211 | "sw $7, 7*4($26) \n" |
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[296] | 212 | |
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[317] | 213 | "sw $8, 8*4($26) \n" |
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| 214 | "sw $9, 9*4($26) \n" |
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| 215 | "sw $10, 10*4($26) \n" |
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| 216 | "sw $11, 11*4($26) \n" |
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| 217 | "sw $12, 12*4($26) \n" |
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| 218 | "sw $13, 13*4($26) \n" |
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| 219 | "sw $14, 14*4($26) \n" |
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| 220 | "sw $15, 15*4($26) \n" |
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[296] | 221 | |
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[317] | 222 | "sw $16, 16*4($26) \n" |
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| 223 | "sw $17, 17*4($26) \n" |
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| 224 | "sw $18, 18*4($26) \n" |
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| 225 | "sw $19, 19*4($26) \n" |
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| 226 | "sw $20, 20*4($26) \n" |
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| 227 | "sw $21, 21*4($26) \n" |
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| 228 | "sw $22, 22*4($26) \n" |
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| 229 | "sw $23, 23*4($26) \n" |
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[296] | 230 | |
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[317] | 231 | "sw $24, 24*4($26) \n" |
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| 232 | "sw $25, 25*4($26) \n" |
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[296] | 233 | |
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[317] | 234 | "mfhi $27 \n" |
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| 235 | "sw $27, 26*4($26) \n" |
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| 236 | "mflo $27 \n" |
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| 237 | "sw $27, 27*4($26) \n" |
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[296] | 238 | |
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[317] | 239 | "sw $28, 28*4($26) \n" |
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| 240 | "sw $29, 29*4($26) \n" |
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| 241 | "sw $30, 30*4($26) \n" |
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| 242 | "sw $31, 31*4($26) \n" |
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[296] | 243 | |
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[317] | 244 | "mfc2 $27, $0 \n" |
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| 245 | "sw $27, 32*4($26) \n" |
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| 246 | "mfc2 $27, $1 \n" |
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| 247 | "sw $27, 33*4($26) \n" |
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[296] | 248 | |
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[317] | 249 | "mfc0 $27, $12 \n" |
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| 250 | "sw $27, 34*4($26) \n" |
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| 251 | "mfc0 $27, $4, 2 \n" |
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| 252 | "sw $27, 35*4($26) \n" |
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[296] | 253 | |
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[317] | 254 | "sync \n" |
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[296] | 255 | |
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[317] | 256 | "move $26, %1 \n" |
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[296] | 257 | |
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[317] | 258 | "lw $27, 0*4($26) \n" |
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| 259 | "mtc0 $27, $14 \n" |
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[296] | 260 | |
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[317] | 261 | "lw $1, 1*4($26) \n" |
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| 262 | "lw $2, 2*4($26) \n" |
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| 263 | "lw $3, 3*4($26) \n" |
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| 264 | "lw $4, 4*4($26) \n" |
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| 265 | "lw $5, 5*4($26) \n" |
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| 266 | "lw $6, 6*4($26) \n" |
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| 267 | "lw $7, 7*4($26) \n" |
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[296] | 268 | |
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[317] | 269 | "lw $8, 8*4($26) \n" |
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| 270 | "lw $9, 9*4($26) \n" |
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| 271 | "lw $10, 10*4($26) \n" |
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| 272 | "lw $11, 11*4($26) \n" |
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| 273 | "lw $12, 12*4($26) \n" |
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| 274 | "lw $13, 13*4($26) \n" |
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| 275 | "lw $14, 14*4($26) \n" |
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| 276 | "lw $15, 15*4($26) \n" |
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[296] | 277 | |
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[317] | 278 | "lw $16, 16*4($26) \n" |
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| 279 | "lw $17, 17*4($26) \n" |
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| 280 | "lw $18, 18*4($26) \n" |
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| 281 | "lw $19, 19*4($26) \n" |
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| 282 | "lw $20, 20*4($26) \n" |
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| 283 | "lw $21, 21*4($26) \n" |
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| 284 | "lw $22, 22*4($26) \n" |
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| 285 | "lw $23, 23*4($26) \n" |
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[296] | 286 | |
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[317] | 287 | "lw $24, 24*4($26) \n" |
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| 288 | "lw $25, 25*4($26) \n" |
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[296] | 289 | |
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[317] | 290 | "lw $27, 26*4($26) \n" |
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| 291 | "mthi $27 \n" |
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| 292 | "lw $27, 27*4($26) \n" |
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| 293 | "mtlo $27 \n" |
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[296] | 294 | |
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[317] | 295 | "lw $28, 28*4($26) \n" |
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| 296 | "lw $29, 29*4($26) \n" |
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| 297 | "lw $30, 30*4($26) \n" |
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| 298 | "lw $31, 31*4($26) \n" |
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[296] | 299 | |
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[317] | 300 | "lw $27, 32*4($26) \n" |
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| 301 | "mtc2 $27, $0 \n" |
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| 302 | "lw $27, 33*4($26) \n" |
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| 303 | "mtc2 $27, $1 \n" |
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[296] | 304 | |
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[317] | 305 | "lw $27, 34*4($26) \n" |
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| 306 | "mtc0 $27, $12 \n" |
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| 307 | "lw $27, 35*4($26) \n" |
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| 308 | "mtc0 $27, $4, 2 \n" |
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[296] | 309 | |
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[317] | 310 | "jr $31 \n" |
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[296] | 311 | |
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[317] | 312 | ".set reorder \n" |
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| 313 | ".set at \n" |
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| 314 | : : "r"(ctx_old) , "r"(ctx_new) : "$26" , "$27" , "memory" ); |
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[296] | 315 | |
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[317] | 316 | } // hal_context_switch() |
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[296] | 317 | |
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[317] | 318 | */ |
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[296] | 319 | |
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[317] | 320 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 321 | // These registers are saved/restored to/from CPU context defined by <ctx> argument. |
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| 322 | // - GPR : all, but (zero, k0, k1), plus (hi, lo) |
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| 323 | // - CP0 : c0_th , c0_sr |
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| 324 | // - CP2 : c2_ptpr , C2_mode, C2_epc |
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| 325 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 326 | void hal_cpu_context_switch( thread_t * old, |
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| 327 | thread_t * new ) |
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[311] | 328 | { |
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[317] | 329 | hal_cpu_context_t * ctx_old = old->cpu_context; |
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| 330 | hal_cpu_context_t * ctx_new = new->cpu_context; |
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| 331 | |
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| 332 | #if CONFIG_CONTEXT_DEBUG |
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| 333 | hal_cpu_context_display( old ); |
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| 334 | hal_cpu_context_display( new ); |
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| 335 | #endif |
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| 336 | |
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| 337 | hal_do_switch( ctx_old , ctx_new ); |
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[311] | 338 | } |
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| 339 | |
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[1] | 340 | ///////////////////////////////////////////// |
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| 341 | error_t hal_cpu_context_copy( thread_t * dst, |
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| 342 | thread_t * src ) |
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| 343 | { |
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| 344 | kmem_req_t req; |
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| 345 | |
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| 346 | // allocate memory for dst cpu_context |
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[8] | 347 | req.type = KMEM_CPU_CTX; |
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[1] | 348 | req.size = sizeof(hal_cpu_context_t); |
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| 349 | req.flags = AF_KERNEL | AF_ZERO; |
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| 350 | |
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| 351 | hal_cpu_context_t * dst_context = (hal_cpu_context_t *)kmem_alloc( &req ); |
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| 352 | if( dst_context == NULL ) return ENOMEM; |
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| 353 | |
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| 354 | // set cpu context pointer in dst thread |
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| 355 | dst->cpu_context = dst_context; |
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| 356 | |
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| 357 | // get cpu context pointer from src thread |
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| 358 | hal_cpu_context_t * src_context = src->cpu_context; |
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| 359 | |
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| 360 | // copy CPU context from src to dst |
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| 361 | memcpy( dst_context , src_context , sizeof(hal_cpu_context_t) ); |
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| 362 | |
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| 363 | return 0; |
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[317] | 364 | |
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[1] | 365 | } // end hal_cpu_context_copy() |
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| 366 | |
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| 367 | ///////////////////////////////////////////////// |
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| 368 | void hal_cpu_context_destroy( thread_t * thread ) |
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| 369 | { |
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| 370 | kmem_req_t req; |
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| 371 | |
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[8] | 372 | req.type = KMEM_CPU_CTX; |
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[1] | 373 | req.ptr = thread->cpu_context; |
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| 374 | kmem_free( &req ); |
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| 375 | |
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| 376 | } // end hal_cpu_context_destroy() |
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| 377 | |
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[317] | 378 | |
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| 379 | |
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| 380 | |
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| 381 | |
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[1] | 382 | /////////////////////////////////////////////////// |
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| 383 | error_t hal_fpu_context_create( thread_t * thread ) |
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| 384 | { |
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| 385 | kmem_req_t req; |
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| 386 | |
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| 387 | // allocate memory for uzone |
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[8] | 388 | req.type = KMEM_FPU_CTX; |
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[1] | 389 | req.size = sizeof(hal_fpu_context_t); |
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| 390 | req.flags = AF_KERNEL | AF_ZERO; |
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| 391 | |
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| 392 | hal_fpu_context_t * context = (hal_fpu_context_t *)kmem_alloc( &req ); |
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| 393 | if( context == NULL ) return ENOMEM; |
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| 394 | |
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| 395 | // set fpu context pointer in thread |
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| 396 | thread->fpu_context = (void*)context; |
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| 397 | |
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| 398 | return 0; |
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| 399 | } // hal_fpu_context_create() |
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| 400 | |
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| 401 | ///////////////////////////////////////////// |
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| 402 | error_t hal_fpu_context_copy( thread_t * dst, |
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| 403 | thread_t * src ) |
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| 404 | { |
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| 405 | kmem_req_t req; |
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| 406 | |
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| 407 | // allocate memory for dst fpu_context |
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[8] | 408 | req.type = KMEM_FPU_CTX; |
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[1] | 409 | req.size = sizeof(hal_fpu_context_t); |
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| 410 | req.flags = AF_KERNEL | AF_ZERO; |
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| 411 | |
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| 412 | hal_fpu_context_t * dst_context = (hal_fpu_context_t *)kmem_alloc( &req ); |
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| 413 | if( dst_context == NULL ) return ENOMEM; |
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| 414 | |
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| 415 | // set fpu context pointer in dst thread |
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| 416 | dst->fpu_context = (void*)dst_context; |
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| 417 | |
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| 418 | // get fpu context pointer from src thread |
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| 419 | hal_fpu_context_t * src_context = src->fpu_context; |
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| 420 | |
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| 421 | // copy CPU context from src to dst |
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| 422 | memcpy( dst_context , src_context , sizeof(hal_fpu_context_t) ); |
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| 423 | |
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| 424 | return 0; |
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| 425 | } // end hal_fpu_context_copy() |
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| 426 | |
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| 427 | ///////////////////////////////////////////////// |
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| 428 | void hal_fpu_context_destroy( thread_t * thread ) |
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| 429 | { |
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| 430 | kmem_req_t req; |
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| 431 | |
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[8] | 432 | req.type = KMEM_FPU_CTX; |
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[1] | 433 | req.ptr = thread->fpu_context; |
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| 434 | kmem_free( &req ); |
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| 435 | |
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| 436 | } // end hal_fpu_context_destroy() |
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| 437 | |
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[296] | 438 | ///////////////////////////////////////////////////////////////////////////////////////// |
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| 439 | // These registers are initialised: |
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| 440 | // - GPR : sp_29 , fp_30 , a0 |
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| 441 | // - CP0 : c0_sr , c0_epc , c0_th |
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| 442 | // - CP2 : C2_ptpr , c2_mode |
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| 443 | // TODO Quand cette fonction est-elle appelée? [AG] |
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| 444 | ///////////////////////////////////////////////////////////////////////////////////////// |
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[1] | 445 | void hal_cpu_context_load( thread_t * thread ) |
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| 446 | { |
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| 447 | // get relevant values from thread context |
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| 448 | hal_cpu_context_t * ctx = (hal_cpu_context_t *)thread->cpu_context; |
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| 449 | uint32_t sp_29 = ctx->sp_29; |
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| 450 | uint32_t fp_30 = ctx->fp_30; |
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| 451 | uint32_t c0_th = ctx->c0_th; |
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| 452 | uint32_t c0_sr = ctx->c0_sr; |
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| 453 | uint32_t c2_ptpr = ctx->c2_ptpr; |
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| 454 | uint32_t c2_mode = ctx->c2_mode; |
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| 455 | |
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| 456 | // get pointer on entry function & argument from thread attributes |
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| 457 | uint32_t func = (uint32_t)thread->entry_func; |
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| 458 | uint32_t args = (uint32_t)thread->entry_args; |
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| 459 | |
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| 460 | // reset loadable field in thread descriptor |
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| 461 | thread->flags &= ~THREAD_FLAG_LOADABLE; |
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| 462 | |
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| 463 | // load registers |
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| 464 | asm volatile( |
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| 465 | ".set noreorder \n" |
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| 466 | "or $26, %0, $0 \n" /* $26 <= stack pointer */ |
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| 467 | "or $27, %2, $0 \n" /* $27 <= status register */ |
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| 468 | "addiu $26, $26, -4 \n" /* decrement stack pointer */ |
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| 469 | "or $4, %7, $0 \n" /* load a0 */ |
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| 470 | "sw $4, ($26) \n" /* set entry_args in stack */ |
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| 471 | "ori $27, $27, 0x2 \n" /* set EXL flag in status register */ |
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| 472 | "mtc0 $27, $12 \n" /* load c0_sr */ |
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| 473 | "mtc0 %3, $4, 2 \n" /* load c0_th */ |
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| 474 | "mtc2 %4, $0 \n" /* load c2 ptpr */ |
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| 475 | "mtc0 %6, $14 \n" /* load c0_epc */ |
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| 476 | "or $29, $16, $0 \n" /* load sp_29 */ |
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| 477 | "or $30, %1, $0 \n" /* load fp_30 */ |
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| 478 | "mtc2 %5, $1 \n" /* load c2_mode */ |
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| 479 | "nop \n" |
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| 480 | "eret \n" /* jump to user code */ |
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| 481 | "nop \n" |
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| 482 | ".set reorder \n" |
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| 483 | : |
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| 484 | : "r"(sp_29),"r"(fp_30),"r"(c0_sr),"r"(c0_th), |
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| 485 | "r"(c2_ptpr),"r"(c2_mode),"r"(func),"r"(args) |
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| 486 | : "$4","$26","$27","$29","$30" ); |
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| 487 | |
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| 488 | } // end hal_cpu_context_load() |
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| 489 | |
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| 490 | |
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| 491 | ////////////////////////////////////////////// |
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| 492 | void hal_fpu_context_save( thread_t * thread ) |
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| 493 | { |
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| 494 | uint32_t ctx = (uint32_t)thread->fpu_context; |
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| 495 | |
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| 496 | asm volatile( |
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| 497 | ".set noreorder \n" |
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| 498 | "swc1 $f0, 0*4(%0) \n" |
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| 499 | "swc1 $f1, 1*4(%0) \n" |
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| 500 | "swc1 $f2, 2*4(%0) \n" |
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| 501 | "swc1 $f3, 3*4(%0) \n" |
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| 502 | "swc1 $f4, 4*4(%0) \n" |
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| 503 | "swc1 $f5, 5*4(%0) \n" |
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| 504 | "swc1 $f6, 6*4(%0) \n" |
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| 505 | "swc1 $f7, 7*4(%0) \n" |
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| 506 | "swc1 $f8, 8*4(%0) \n" |
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| 507 | "swc1 $f9, 9*4(%0) \n" |
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| 508 | "swc1 $f10, 10*4(%0) \n" |
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| 509 | "swc1 $f11, 11*4(%0) \n" |
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| 510 | "swc1 $f12, 12*4(%0) \n" |
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| 511 | "swc1 $f13, 13*4(%0) \n" |
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| 512 | "swc1 $f14, 14*4(%0) \n" |
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| 513 | "swc1 $f15, 15*4(%0) \n" |
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| 514 | "swc1 $f16, 16*4(%0) \n" |
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| 515 | "swc1 $f17, 17*4(%0) \n" |
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| 516 | "swc1 $f18, 18*4(%0) \n" |
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| 517 | "swc1 $f19, 19*4(%0) \n" |
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| 518 | "swc1 $f20, 20*4(%0) \n" |
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| 519 | "swc1 $f21, 21*4(%0) \n" |
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| 520 | "swc1 $f22, 22*4(%0) \n" |
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| 521 | "swc1 $f23, 23*4(%0) \n" |
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| 522 | "swc1 $f24, 24*4(%0) \n" |
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| 523 | "swc1 $f25, 25*4(%0) \n" |
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| 524 | "swc1 $f26, 26*4(%0) \n" |
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| 525 | "swc1 $f27, 27*4(%0) \n" |
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| 526 | "swc1 $f28, 28*4(%0) \n" |
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| 527 | "swc1 $f29, 29*4(%0) \n" |
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| 528 | "swc1 $f30, 30*4(%0) \n" |
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| 529 | "swc1 $f31, 31*4(%0) \n" |
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| 530 | ".set reorder \n" |
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| 531 | : : "r"(ctx) ); |
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| 532 | |
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| 533 | } // end hal_cpu_context_save() |
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| 534 | |
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| 535 | ///////////////////////////////////////////////// |
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| 536 | void hal_fpu_context_restore( thread_t * thread ) |
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| 537 | { |
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| 538 | uint32_t ctx = (uint32_t)thread->fpu_context; |
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| 539 | |
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| 540 | asm volatile( |
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| 541 | ".set noreorder \n" |
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| 542 | "lwc1 $f0, 0*4(%0) \n" |
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| 543 | "lwc1 $f1, 1*4(%0) \n" |
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| 544 | "lwc1 $f2, 2*4(%0) \n" |
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| 545 | "lwc1 $f3, 3*4(%0) \n" |
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| 546 | "lwc1 $f4, 4*4(%0) \n" |
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| 547 | "lwc1 $f5, 5*4(%0) \n" |
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| 548 | "lwc1 $f6, 6*4(%0) \n" |
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| 549 | "lwc1 $f7, 7*4(%0) \n" |
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| 550 | "lwc1 $f8, 8*4(%0) \n" |
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| 551 | "lwc1 $f9, 9*4(%0) \n" |
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| 552 | "lwc1 $f10, 10*4(%0) \n" |
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| 553 | "lwc1 $f11, 11*4(%0) \n" |
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| 554 | "lwc1 $f12, 12*4(%0) \n" |
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| 555 | "lwc1 $f13, 13*4(%0) \n" |
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| 556 | "lwc1 $f14, 14*4(%0) \n" |
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| 557 | "lwc1 $f15, 15*4(%0) \n" |
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| 558 | "lwc1 $f16, 16*4(%0) \n" |
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| 559 | "lwc1 $f17, 17*4(%0) \n" |
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| 560 | "lwc1 $f18, 18*4(%0) \n" |
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| 561 | "lwc1 $f19, 19*4(%0) \n" |
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| 562 | "lwc1 $f20, 20*4(%0) \n" |
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| 563 | "lwc1 $f21, 21*4(%0) \n" |
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| 564 | "lwc1 $f22, 22*4(%0) \n" |
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| 565 | "lwc1 $f23, 23*4(%0) \n" |
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| 566 | "lwc1 $f24, 24*4(%0) \n" |
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| 567 | "lwc1 $f25, 25*4(%0) \n" |
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| 568 | "lwc1 $f26, 26*4(%0) \n" |
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| 569 | "lwc1 $f27, 27*4(%0) \n" |
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| 570 | "lwc1 $f28, 28*4(%0) \n" |
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| 571 | "lwc1 $f29, 29*4(%0) \n" |
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| 572 | "lwc1 $f30, 30*4(%0) \n" |
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| 573 | "lwc1 $f31, 31*4(%0) \n" |
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| 574 | ".set reorder \n" |
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| 575 | : : "r"(ctx) ); |
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| 576 | |
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| 577 | } // end hal_cpu_context_restore() |
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| 578 | |
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| 579 | ///////////////////////////////////// |
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| 580 | void hal_fpu_context_dup( xptr_t dst, |
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| 581 | xptr_t src ) |
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| 582 | { |
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| 583 | hal_remote_memcpy( dst , src , sizeof(hal_fpu_context_t) ); |
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| 584 | } |
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| 585 | |
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