[1] | 1 | /* |
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| 2 | * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 |
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| 3 | * |
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[445] | 4 | * Author Alain Greiner (2016,2017,2018) |
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[1] | 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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[457] | 24 | #include <hal_kernel_types.h> |
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[1] | 25 | #include <hal_gpt.h> |
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| 26 | #include <hal_special.h> |
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| 27 | #include <printk.h> |
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| 28 | #include <bits.h> |
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| 29 | #include <process.h> |
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| 30 | #include <kmem.h> |
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| 31 | #include <thread.h> |
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| 32 | #include <cluster.h> |
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| 33 | #include <ppm.h> |
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| 34 | #include <page.h> |
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| 35 | |
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| 36 | //////////////////////////////////////////////////////////////////////////////////////// |
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[401] | 37 | // This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification) |
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[1] | 38 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 39 | |
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[401] | 40 | #define TSAR_MMU_MAPPED 0x80000000 |
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| 41 | #define TSAR_MMU_SMALL 0x40000000 |
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[1] | 42 | #define TSAR_MMU_LOCAL 0x20000000 |
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| 43 | #define TSAR_MMU_REMOTE 0x10000000 |
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| 44 | #define TSAR_MMU_CACHABLE 0x08000000 |
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| 45 | #define TSAR_MMU_WRITABLE 0x04000000 |
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| 46 | #define TSAR_MMU_EXECUTABLE 0x02000000 |
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| 47 | #define TSAR_MMU_USER 0x01000000 |
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| 48 | #define TSAR_MMU_GLOBAL 0x00800000 |
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| 49 | #define TSAR_MMU_DIRTY 0x00400000 |
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| 50 | |
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[401] | 51 | #define TSAR_MMU_COW 0x00000001 // only for small pages |
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| 52 | #define TSAR_MMU_SWAP 0x00000004 // only for small pages |
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| 53 | #define TSAR_MMU_LOCKED 0x00000008 // only for small pages |
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[1] | 54 | |
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| 55 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 56 | // TSAR MMU related macros (from the TSAR MMU specification) |
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| 57 | // - IX1 on 11 bits |
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| 58 | // - IX2 on 9 bits |
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| 59 | // - PPN on 28 bits |
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| 60 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 61 | |
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| 62 | #define TSAR_MMU_IX1_WIDTH 11 |
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| 63 | #define TSAR_MMU_IX2_WIDTH 9 |
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| 64 | #define TSAR_MMU_PPN_WIDTH 28 |
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| 65 | |
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[401] | 66 | #define TSAR_MMU_PTE1_ATTR_MASK 0xFFC00000 |
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| 67 | #define TSAR_MMU_PTE1_PPN_MASK 0x0007FFFF |
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| 68 | |
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[1] | 69 | #define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF) |
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| 70 | #define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF) |
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| 71 | |
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[315] | 72 | #define TSAR_MMU_PTBA_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF) |
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| 73 | #define TSAR_MMU_PPN_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9) |
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[1] | 74 | #define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000) |
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| 75 | |
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| 76 | #define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF) |
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| 77 | #define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF) |
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| 78 | |
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[401] | 79 | |
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| 80 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 81 | // This static function translates the GPT attributes to the TSAR attributes |
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| 82 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 83 | static inline uint32_t gpt2tsar( uint32_t gpt_attr ) |
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| 84 | { |
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| 85 | uint32_t tsar_attr = 0; |
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| 86 | |
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| 87 | if( gpt_attr & GPT_MAPPED ) tsar_attr |= TSAR_MMU_MAPPED; |
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| 88 | if( gpt_attr & GPT_SMALL ) tsar_attr |= TSAR_MMU_SMALL; |
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| 89 | if( gpt_attr & GPT_WRITABLE ) tsar_attr |= TSAR_MMU_WRITABLE; |
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| 90 | if( gpt_attr & GPT_EXECUTABLE ) tsar_attr |= TSAR_MMU_EXECUTABLE; |
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| 91 | if( gpt_attr & GPT_CACHABLE ) tsar_attr |= TSAR_MMU_CACHABLE; |
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| 92 | if( gpt_attr & GPT_USER ) tsar_attr |= TSAR_MMU_USER; |
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| 93 | if( gpt_attr & GPT_DIRTY ) tsar_attr |= TSAR_MMU_DIRTY; |
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| 94 | if( gpt_attr & GPT_ACCESSED ) tsar_attr |= TSAR_MMU_LOCAL; |
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| 95 | if( gpt_attr & GPT_GLOBAL ) tsar_attr |= TSAR_MMU_GLOBAL; |
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| 96 | if( gpt_attr & GPT_COW ) tsar_attr |= TSAR_MMU_COW; |
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| 97 | if( gpt_attr & GPT_SWAP ) tsar_attr |= TSAR_MMU_SWAP; |
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| 98 | if( gpt_attr & GPT_LOCKED ) tsar_attr |= TSAR_MMU_LOCKED; |
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| 99 | |
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| 100 | return tsar_attr; |
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| 101 | } |
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| 102 | |
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| 103 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 104 | // This static function translates the TSAR attributes to the GPT attributes |
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| 105 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 106 | static inline uint32_t tsar2gpt( uint32_t tsar_attr ) |
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| 107 | { |
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| 108 | uint32_t gpt_attr = 0; |
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| 109 | |
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| 110 | if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr |= GPT_MAPPED; |
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| 111 | if( tsar_attr & TSAR_MMU_MAPPED ) gpt_attr |= GPT_READABLE; |
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| 112 | if( tsar_attr & TSAR_MMU_SMALL ) gpt_attr |= GPT_SMALL; |
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| 113 | if( tsar_attr & TSAR_MMU_WRITABLE ) gpt_attr |= GPT_WRITABLE; |
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| 114 | if( tsar_attr & TSAR_MMU_EXECUTABLE ) gpt_attr |= GPT_EXECUTABLE; |
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| 115 | if( tsar_attr & TSAR_MMU_CACHABLE ) gpt_attr |= GPT_CACHABLE; |
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| 116 | if( tsar_attr & TSAR_MMU_USER ) gpt_attr |= GPT_USER; |
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| 117 | if( tsar_attr & TSAR_MMU_DIRTY ) gpt_attr |= GPT_DIRTY; |
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| 118 | if( tsar_attr & TSAR_MMU_LOCAL ) gpt_attr |= GPT_ACCESSED; |
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| 119 | if( tsar_attr & TSAR_MMU_REMOTE ) gpt_attr |= GPT_ACCESSED; |
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| 120 | if( tsar_attr & TSAR_MMU_GLOBAL ) gpt_attr |= GPT_GLOBAL; |
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| 121 | if( tsar_attr & TSAR_MMU_COW ) gpt_attr |= GPT_COW; |
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| 122 | if( tsar_attr & TSAR_MMU_SWAP ) gpt_attr |= GPT_SWAP; |
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| 123 | if( tsar_attr & TSAR_MMU_LOCKED ) gpt_attr |= GPT_LOCKED; |
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| 124 | |
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| 125 | return gpt_attr; |
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| 126 | } |
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| 127 | |
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[1] | 128 | ///////////////////////////////////// |
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| 129 | error_t hal_gpt_create( gpt_t * gpt ) |
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| 130 | { |
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| 131 | page_t * page; |
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[315] | 132 | xptr_t page_xp; |
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[1] | 133 | |
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[587] | 134 | thread_t * this = CURRENT_THREAD; |
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| 135 | |
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[443] | 136 | #if DEBUG_HAL_GPT_CREATE |
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[587] | 137 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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[443] | 138 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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[611] | 139 | printk("\n[%s] : thread[%x,%x] enter / cycle %d\n", |
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[587] | 140 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[432] | 141 | #endif |
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[406] | 142 | |
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[1] | 143 | // check page size |
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[492] | 144 | assert( (CONFIG_PPM_PAGE_SIZE == 4096) , |
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[440] | 145 | "for TSAR, the page size must be 4 Kbytes\n" ); |
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[1] | 146 | |
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| 147 | // allocates 2 physical pages for PT1 |
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| 148 | kmem_req_t req; |
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| 149 | req.type = KMEM_PAGE; |
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| 150 | req.size = 1; // 2 small pages |
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| 151 | req.flags = AF_KERNEL | AF_ZERO; |
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| 152 | page = (page_t *)kmem_alloc( &req ); |
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| 153 | |
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[406] | 154 | if( page == NULL ) |
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[1] | 155 | { |
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[587] | 156 | printk("\n[PANIC] in %s : no memory for PT1 / process %x / cluster %x\n", |
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| 157 | __FUNCTION__, this->process->pid, local_cxy ); |
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[1] | 158 | return ENOMEM; |
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[406] | 159 | } |
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[1] | 160 | |
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| 161 | // initialize generic page table descriptor |
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[315] | 162 | page_xp = XPTR( local_cxy , page ); |
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| 163 | gpt->ptr = GET_PTR( ppm_page2base( page_xp ) ); |
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| 164 | gpt->ppn = ppm_page2ppn( page_xp ); |
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| 165 | |
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[443] | 166 | #if DEBUG_HAL_GPT_CREATE |
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[587] | 167 | cycle = (uint32_t)hal_get_cycles(); |
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[443] | 168 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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[611] | 169 | printk("\n[%s] : thread[%x,%x] exit / cycle %d\n", |
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[587] | 170 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[432] | 171 | #endif |
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[406] | 172 | |
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[1] | 173 | return 0; |
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[406] | 174 | |
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[1] | 175 | } // end hal_gpt_create() |
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| 176 | |
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| 177 | |
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| 178 | /////////////////////////////////// |
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| 179 | void hal_gpt_destroy( gpt_t * gpt ) |
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| 180 | { |
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| 181 | uint32_t ix1; |
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| 182 | uint32_t ix2; |
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| 183 | uint32_t * pt1; |
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| 184 | uint32_t pte1; |
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| 185 | ppn_t pt2_ppn; |
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| 186 | uint32_t * pt2; |
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| 187 | uint32_t attr; |
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| 188 | vpn_t vpn; |
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| 189 | kmem_req_t req; |
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| 190 | bool_t is_ref; |
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| 191 | |
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[443] | 192 | #if DEBUG_HAL_GPT_DESTROY |
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[587] | 193 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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| 194 | thread_t * this = CURRENT_THREAD; |
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[443] | 195 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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[611] | 196 | printk("\n[%s] : thread[%x,%x] enter / cycle %d\n", |
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[587] | 197 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[443] | 198 | #endif |
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| 199 | |
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[1] | 200 | // get pointer on calling process |
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| 201 | process_t * process = CURRENT_THREAD->process; |
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| 202 | |
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| 203 | // compute is_ref |
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[23] | 204 | is_ref = ( GET_CXY( process->ref_xp ) == local_cxy ); |
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[1] | 205 | |
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| 206 | // get pointer on PT1 |
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| 207 | pt1 = (uint32_t *)gpt->ptr; |
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| 208 | |
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| 209 | // scan the PT1 |
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| 210 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 211 | { |
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| 212 | pte1 = pt1[ix1]; |
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[401] | 213 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) // PTE1 valid |
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[1] | 214 | { |
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[401] | 215 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page |
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[1] | 216 | { |
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[391] | 217 | if( (pte1 & TSAR_MMU_USER) != 0 ) |
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[1] | 218 | { |
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| 219 | // warning message |
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| 220 | printk("\n[WARNING] in %s : found an USER BIG page / ix1 = %d\n", |
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[391] | 221 | __FUNCTION__ , ix1 ); |
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[1] | 222 | |
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| 223 | // release the big physical page if reference cluster |
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| 224 | if( is_ref ) |
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| 225 | { |
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| 226 | vpn = (vpn_t)(ix1 << TSAR_MMU_IX2_WIDTH); |
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| 227 | hal_gpt_reset_pte( gpt , vpn ); |
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| 228 | } |
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| 229 | } |
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| 230 | } |
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[391] | 231 | else // SMALL page |
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[1] | 232 | { |
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[315] | 233 | // get local pointer on PT2 |
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[1] | 234 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 235 | xptr_t base_xp = ppm_ppn2base( pt2_ppn ); |
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[587] | 236 | pt2 = GET_PTR( base_xp ); |
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[1] | 237 | |
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| 238 | // scan the PT2 to release all entries VALID and USER if reference cluster |
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| 239 | if( is_ref ) |
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| 240 | { |
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| 241 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 242 | { |
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| 243 | attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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[401] | 244 | if( ((attr & TSAR_MMU_MAPPED) != 0 ) && ((attr & TSAR_MMU_USER) != 0) ) |
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[1] | 245 | { |
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| 246 | // release the physical page |
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| 247 | vpn = (vpn_t)((ix1 << TSAR_MMU_IX2_WIDTH) | ix2); |
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| 248 | hal_gpt_reset_pte( gpt , vpn ); |
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| 249 | } |
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| 250 | } |
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| 251 | } |
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| 252 | |
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| 253 | // release the PT2 |
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| 254 | req.type = KMEM_PAGE; |
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[315] | 255 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt2 ) ) ); |
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[1] | 256 | kmem_free( &req ); |
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| 257 | } |
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| 258 | } |
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| 259 | } |
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| 260 | |
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| 261 | // release the PT1 |
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| 262 | req.type = KMEM_PAGE; |
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[315] | 263 | req.ptr = GET_PTR( ppm_base2page( XPTR(local_cxy , pt1 ) ) ); |
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[1] | 264 | kmem_free( &req ); |
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| 265 | |
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[443] | 266 | #if DEBUG_HAL_GPT_DESTROY |
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[587] | 267 | cycle = (uint32_t)hal_get_cycles(); |
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[443] | 268 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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[611] | 269 | printk("\n[%s] : thread[%x,%x] exit / cycle %d\n", |
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[587] | 270 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[443] | 271 | #endif |
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| 272 | |
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[1] | 273 | } // end hal_gpt_destroy() |
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| 274 | |
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[407] | 275 | /////////////////////////////////////////// |
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| 276 | void hal_gpt_display( process_t * process ) |
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[1] | 277 | { |
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[407] | 278 | gpt_t * gpt; |
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[1] | 279 | uint32_t ix1; |
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| 280 | uint32_t ix2; |
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| 281 | uint32_t * pt1; |
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| 282 | uint32_t pte1; |
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| 283 | ppn_t pt2_ppn; |
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| 284 | uint32_t * pt2; |
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| 285 | uint32_t pte2_attr; |
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| 286 | ppn_t pte2_ppn; |
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[406] | 287 | vpn_t vpn; |
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[1] | 288 | |
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[492] | 289 | assert( (process != NULL) , "NULL process pointer\n"); |
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[1] | 290 | |
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[407] | 291 | // get pointer on gpt |
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| 292 | gpt = &(process->vmm.gpt); |
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| 293 | |
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| 294 | // get pointer on PT1 |
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[1] | 295 | pt1 = (uint32_t *)gpt->ptr; |
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| 296 | |
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[406] | 297 | printk("\n***** Generic Page Table for process %x : &gpt = %x / &pt1 = %x\n\n", |
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[407] | 298 | process->pid , gpt , pt1 ); |
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[406] | 299 | |
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[1] | 300 | // scan the PT1 |
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| 301 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 302 | { |
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| 303 | pte1 = pt1[ix1]; |
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[401] | 304 | if( (pte1 & TSAR_MMU_MAPPED) != 0 ) |
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[1] | 305 | { |
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[401] | 306 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // BIG page |
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[1] | 307 | { |
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[406] | 308 | vpn = ix1 << 9; |
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| 309 | printk(" - BIG : vpn = %x / pt1[%d] = %X\n", vpn , ix1 , pte1 ); |
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[1] | 310 | } |
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| 311 | else // SMALL pages |
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| 312 | { |
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| 313 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
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[315] | 314 | xptr_t base_xp = ppm_ppn2base ( pt2_ppn ); |
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[587] | 315 | pt2 = GET_PTR( base_xp ); |
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[1] | 316 | |
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| 317 | // scan the PT2 |
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| 318 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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| 319 | { |
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| 320 | pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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| 321 | pte2_ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2 * ix2 + 1] ); |
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[406] | 322 | |
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[401] | 323 | if( (pte2_attr & TSAR_MMU_MAPPED) != 0 ) |
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[1] | 324 | { |
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[406] | 325 | vpn = (ix1 << 9) | ix2; |
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[408] | 326 | printk(" - SMALL : vpn %X / ppn %X / attr %X\n", |
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| 327 | vpn , pte2_ppn , tsar2gpt(pte2_attr) ); |
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[1] | 328 | } |
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| 329 | } |
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| 330 | } |
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| 331 | } |
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| 332 | } |
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[407] | 333 | } // end hal_gpt_display() |
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[1] | 334 | |
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| 335 | |
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[587] | 336 | ////////////////////////////////////////// |
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| 337 | error_t hal_gpt_set_pte( xptr_t gpt_xp, |
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[1] | 338 | vpn_t vpn, |
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[587] | 339 | uint32_t attr, // GPT attributes |
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[408] | 340 | ppn_t ppn ) |
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[1] | 341 | { |
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[587] | 342 | cxy_t gpt_cxy; // target GPT cluster |
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| 343 | gpt_t * gpt_ptr; // target GPT local pointer |
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| 344 | uint32_t * pt1_ptr; // local pointer on PT1 |
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| 345 | xptr_t pte1_xp; // extended pointer on PT1 entry |
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| 346 | uint32_t pte1; // PT1 entry value if PTE1 |
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[1] | 347 | |
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[401] | 348 | ppn_t pt2_ppn; // PPN of PT2 |
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[587] | 349 | uint32_t * pt2_ptr; // PT2 base address |
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[1] | 350 | |
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[401] | 351 | uint32_t small; // requested PTE is for a small page |
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[315] | 352 | |
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[401] | 353 | page_t * page; // pointer on new physical page descriptor |
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| 354 | xptr_t page_xp; // extended pointer on new page descriptor |
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[1] | 355 | |
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[401] | 356 | uint32_t ix1; // index in PT1 |
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| 357 | uint32_t ix2; // index in PT2 |
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[1] | 358 | |
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[401] | 359 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
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| 360 | |
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[587] | 361 | thread_t * this = CURRENT_THREAD; |
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| 362 | |
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| 363 | // get cluster and local pointer on GPT |
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| 364 | gpt_cxy = GET_CXY( gpt_xp ); |
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| 365 | gpt_ptr = GET_PTR( gpt_xp ); |
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| 366 | |
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| 367 | #if DEBUG_HAL_GPT_SET_PTE |
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| 368 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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| 369 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
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[611] | 370 | printk("\n[%s] : thread[%x,%x] enter / vpn %x / attr %x / ppn %x / cluster %x / cycle %d\n", |
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[587] | 371 | __FUNCTION__, this->process->pid, this->trdid, vpn, attr, ppn, gpt_cxy, cycle ); |
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[432] | 372 | #endif |
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| 373 | |
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[1] | 374 | // compute indexes in PT1 and PT2 |
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| 375 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 376 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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| 377 | |
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[587] | 378 | pt1_ptr = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
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| 379 | small = attr & GPT_SMALL; |
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[1] | 380 | |
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[432] | 381 | // compute tsar attributes from generic attributes |
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[401] | 382 | tsar_attr = gpt2tsar( attr ); |
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| 383 | |
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[587] | 384 | // build extended pointer on PTE1 = PT1[ix1] |
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| 385 | pte1_xp = XPTR( gpt_cxy , &pt1_ptr[ix1] ); |
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[406] | 386 | |
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[587] | 387 | // get current pte1 value |
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| 388 | pte1 = hal_remote_l32( pte1_xp ); |
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[1] | 389 | |
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[587] | 390 | if( small == 0 ) // map a big page in PT1 |
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[401] | 391 | { |
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[492] | 392 | assert( (pte1 == 0) , |
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[406] | 393 | "try to set a big page in a mapped PT1 entry / PT1[%d] = %x\n", ix1 , pte1 ); |
---|
[1] | 394 | |
---|
[587] | 395 | // set the PTE1 value in PT1 |
---|
| 396 | pte1 = (tsar_attr & TSAR_MMU_PTE1_ATTR_MASK) | ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK); |
---|
| 397 | hal_remote_s32( pte1_xp , pte1 ); |
---|
[124] | 398 | hal_fence(); |
---|
[587] | 399 | |
---|
| 400 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 401 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[611] | 402 | printk("\n[%s] : thread[%x,%x] map PTE1 / cxy %x / ix1 %x / pt1 %x / pte1 %x\n", |
---|
[587] | 403 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, pte1 ); |
---|
| 404 | #endif |
---|
| 405 | |
---|
[1] | 406 | return 0; |
---|
| 407 | } |
---|
[587] | 408 | else // map a small page in PT1 & PT2 |
---|
| 409 | { |
---|
| 410 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry unmapped => map it |
---|
| 411 | { |
---|
| 412 | // allocate one physical page for PT2 |
---|
| 413 | if( gpt_cxy == local_cxy ) |
---|
| 414 | { |
---|
| 415 | kmem_req_t req; |
---|
| 416 | req.type = KMEM_PAGE; |
---|
| 417 | req.size = 0; // 1 small page |
---|
| 418 | req.flags = AF_KERNEL | AF_ZERO; |
---|
| 419 | page = (page_t *)kmem_alloc( &req ); |
---|
| 420 | } |
---|
| 421 | else |
---|
| 422 | { |
---|
| 423 | rpc_pmem_get_pages_client( gpt_cxy , 0 , &page ); |
---|
| 424 | } |
---|
[1] | 425 | |
---|
[406] | 426 | if( page == NULL ) |
---|
| 427 | { |
---|
[587] | 428 | printk("\n[PANIC] in %s : no memory for GPT PT2 / process %x / cluster %x\n", |
---|
| 429 | __FUNCTION__, this->process->pid, gpt_cxy ); |
---|
[406] | 430 | return ENOMEM; |
---|
| 431 | } |
---|
[1] | 432 | |
---|
[406] | 433 | // get the PT2 PPN |
---|
[587] | 434 | page_xp = XPTR( gpt_cxy , page ); |
---|
[406] | 435 | pt2_ppn = ppm_page2ppn( page_xp ); |
---|
[315] | 436 | |
---|
[587] | 437 | // build PTD1 value |
---|
[406] | 438 | pte1 = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn; |
---|
[1] | 439 | |
---|
[587] | 440 | // set the PTD1 value in PT1 |
---|
| 441 | hal_remote_s32( pte1_xp , pte1 ); |
---|
| 442 | |
---|
| 443 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 444 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[611] | 445 | printk("\n[%s] : thread[%x,%x] map PTD1 / cxy %x / ix1 %d / pt1 %x / ptd1 %x\n", |
---|
[587] | 446 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, pte1 ); |
---|
| 447 | #endif |
---|
[406] | 448 | } |
---|
[587] | 449 | else // pt1 entry mapped => use it |
---|
[1] | 450 | { |
---|
| 451 | |
---|
[587] | 452 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 453 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[611] | 454 | printk("\n[%s] : thread[%x,%x] get PTD1 / cxy %x / ix1 %d / pt1 %x / ptd1 %x\n", |
---|
[587] | 455 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, pte1 ); |
---|
| 456 | #endif |
---|
| 457 | |
---|
[1] | 458 | } |
---|
| 459 | |
---|
[406] | 460 | // get PT2 base from pte1 |
---|
| 461 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 462 | pt2_ptr = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 463 | |
---|
[587] | 464 | // set PTE2 in PT2 (in this order) |
---|
| 465 | hal_remote_s32( XPTR( gpt_cxy , &pt2_ptr[2 * ix2 + 1] ) , ppn ); |
---|
| 466 | hal_fence(); |
---|
| 467 | hal_remote_s32( XPTR( gpt_cxy , &pt2_ptr[2 * ix2] ) , tsar_attr ); |
---|
| 468 | hal_fence(); |
---|
[1] | 469 | |
---|
[587] | 470 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 471 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[611] | 472 | printk("\n[%s] : thread[%x,%x] map PTE2 / cxy %x / ix2 %x / pt2 %x / attr %x / ppn %x\n", |
---|
[587] | 473 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix2, pt2_ptr, tsar_attr, ppn ); |
---|
[432] | 474 | #endif |
---|
| 475 | |
---|
[587] | 476 | return 0; |
---|
| 477 | } |
---|
[1] | 478 | } // end of hal_gpt_set_pte() |
---|
| 479 | |
---|
[587] | 480 | //////////////////////////////////////// |
---|
| 481 | void hal_gpt_get_pte( xptr_t gpt_xp, |
---|
[1] | 482 | vpn_t vpn, |
---|
| 483 | uint32_t * attr, |
---|
| 484 | ppn_t * ppn ) |
---|
| 485 | { |
---|
| 486 | uint32_t * pt1; |
---|
| 487 | uint32_t pte1; |
---|
| 488 | |
---|
| 489 | uint32_t * pt2; |
---|
| 490 | ppn_t pt2_ppn; |
---|
| 491 | |
---|
[587] | 492 | // get cluster and local pointer on GPT |
---|
| 493 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 494 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
| 495 | |
---|
| 496 | // compute indexes in PT1 and PT2 |
---|
[1] | 497 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 498 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 499 | |
---|
[587] | 500 | // get PT1 base |
---|
| 501 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
| 502 | |
---|
| 503 | // get pte1 |
---|
| 504 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[1] | 505 | |
---|
[587] | 506 | // check PTE1 mapped |
---|
[401] | 507 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present |
---|
[1] | 508 | { |
---|
| 509 | *attr = 0; |
---|
| 510 | *ppn = 0; |
---|
[587] | 511 | return; |
---|
[1] | 512 | } |
---|
| 513 | |
---|
[587] | 514 | // access GPT |
---|
[401] | 515 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 |
---|
[1] | 516 | { |
---|
[587] | 517 | // get PPN & ATTR from PT1 |
---|
[401] | 518 | *attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) ); |
---|
[1] | 519 | *ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1)); |
---|
| 520 | } |
---|
[587] | 521 | else // it's a PTD1 |
---|
[1] | 522 | { |
---|
| 523 | // compute PT2 base address |
---|
| 524 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 525 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 526 | |
---|
[587] | 527 | // get PPN & ATTR from PT2 |
---|
| 528 | *ppn = hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2+1] ) ) & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
| 529 | *attr = tsar2gpt( hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2] ) ) ); |
---|
[1] | 530 | } |
---|
| 531 | } // end hal_gpt_get_pte() |
---|
| 532 | |
---|
| 533 | //////////////////////////////////// |
---|
| 534 | void hal_gpt_reset_pte( gpt_t * gpt, |
---|
| 535 | vpn_t vpn ) |
---|
| 536 | { |
---|
| 537 | uint32_t * pt1; // PT1 base address |
---|
| 538 | uint32_t pte1; // PT1 entry value |
---|
| 539 | |
---|
| 540 | ppn_t pt2_ppn; // PPN of PT2 |
---|
| 541 | uint32_t * pt2; // PT2 base address |
---|
| 542 | |
---|
[391] | 543 | // get ix1 & ix2 indexes |
---|
[1] | 544 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 545 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 546 | |
---|
| 547 | // get PTE1 value |
---|
| 548 | pt1 = gpt->ptr; |
---|
| 549 | pte1 = pt1[ix1]; |
---|
| 550 | |
---|
[401] | 551 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // PT1 entry not present |
---|
[1] | 552 | { |
---|
| 553 | return; |
---|
| 554 | } |
---|
| 555 | |
---|
[401] | 556 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) // it's a PTE1 |
---|
[1] | 557 | { |
---|
| 558 | // unmap the big page |
---|
| 559 | pt1[ix1] = 0; |
---|
[124] | 560 | hal_fence(); |
---|
[1] | 561 | |
---|
| 562 | return; |
---|
| 563 | } |
---|
[391] | 564 | else // it's a PTD1 |
---|
[1] | 565 | { |
---|
| 566 | // compute PT2 base address |
---|
| 567 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 568 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 569 | |
---|
| 570 | // unmap the small page |
---|
[587] | 571 | pt2[2*ix2] = 0; |
---|
[391] | 572 | hal_fence(); |
---|
[1] | 573 | |
---|
| 574 | return; |
---|
| 575 | } |
---|
| 576 | } // end hal_gpt_reset_pte() |
---|
| 577 | |
---|
| 578 | ////////////////////////////////////// |
---|
| 579 | error_t hal_gpt_lock_pte( gpt_t * gpt, |
---|
| 580 | vpn_t vpn ) |
---|
| 581 | { |
---|
| 582 | uint32_t * pt1; // PT1 base address |
---|
| 583 | volatile uint32_t * pte1_ptr; // address of PT1 entry |
---|
| 584 | uint32_t pte1; // value of PT1 entry |
---|
| 585 | |
---|
| 586 | uint32_t * pt2; // PT2 base address |
---|
| 587 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
---|
| 588 | volatile uint32_t * pte2_ptr; // address of PT2 entry |
---|
| 589 | |
---|
| 590 | uint32_t attr; |
---|
| 591 | bool_t atomic; |
---|
| 592 | page_t * page; |
---|
[315] | 593 | xptr_t page_xp; |
---|
[1] | 594 | |
---|
| 595 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
| 596 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
| 597 | |
---|
| 598 | // get the PTE1 value |
---|
| 599 | pt1 = gpt->ptr; |
---|
| 600 | pte1_ptr = &pt1[ix1]; |
---|
| 601 | pte1 = *pte1_ptr; |
---|
| 602 | |
---|
| 603 | // If present, the page must be small |
---|
[401] | 604 | if( ((pte1 & TSAR_MMU_MAPPED) != 0) && ((pte1 & TSAR_MMU_SMALL) == 0) ) |
---|
[1] | 605 | { |
---|
| 606 | printk("\n[ERROR] in %s : try to lock a big page / PT1[%d] = %x\n", |
---|
| 607 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 608 | return EINVAL; |
---|
| 609 | } |
---|
| 610 | |
---|
[401] | 611 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) // missing PT1 entry |
---|
[1] | 612 | { |
---|
| 613 | // allocate one physical page for PT2 |
---|
| 614 | kmem_req_t req; |
---|
| 615 | req.type = KMEM_PAGE; |
---|
| 616 | req.size = 0; // 1 small page |
---|
| 617 | req.flags = AF_KERNEL | AF_ZERO; |
---|
| 618 | page = (page_t *)kmem_alloc( &req ); |
---|
[23] | 619 | |
---|
[1] | 620 | if( page == NULL ) |
---|
| 621 | { |
---|
| 622 | printk("\n[ERROR] in %s : try to set a small page but cannot allocate PT2\n", |
---|
| 623 | __FUNCTION__ ); |
---|
| 624 | return ENOMEM; |
---|
| 625 | } |
---|
[23] | 626 | |
---|
[315] | 627 | page_xp = XPTR( local_cxy , page ); |
---|
| 628 | pt2_ppn = ppm_page2ppn( page_xp ); |
---|
[587] | 629 | pt2 = GET_PTR( ppm_page2base( page_xp ) ); |
---|
[1] | 630 | |
---|
| 631 | // try to set the PT1 entry |
---|
| 632 | do |
---|
| 633 | { |
---|
| 634 | atomic = hal_atomic_cas( (void*)pte1_ptr , 0 , |
---|
[401] | 635 | TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn ); |
---|
[1] | 636 | } |
---|
| 637 | while( (atomic == false) && (*pte1_ptr == 0) ); |
---|
| 638 | |
---|
| 639 | if( atomic == false ) // missing PT2 has been allocate by another core |
---|
| 640 | { |
---|
| 641 | // release the allocated page |
---|
| 642 | ppm_free_pages( page ); |
---|
| 643 | |
---|
| 644 | // read again the PTE1 |
---|
| 645 | pte1 = *pte1_ptr; |
---|
| 646 | |
---|
| 647 | // get the PT2 base address |
---|
| 648 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
[587] | 649 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 650 | } |
---|
| 651 | } |
---|
| 652 | else |
---|
| 653 | { |
---|
| 654 | // This valid entry must be a PTD1 |
---|
[401] | 655 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) |
---|
[1] | 656 | { |
---|
| 657 | printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n", |
---|
| 658 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 659 | return EINVAL; |
---|
| 660 | } |
---|
| 661 | |
---|
| 662 | // compute PPN of PT2 base |
---|
| 663 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
| 664 | |
---|
| 665 | // compute pointer on PT2 base |
---|
[587] | 666 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 667 | } |
---|
| 668 | |
---|
| 669 | // from here we have the PT2 pointer |
---|
| 670 | |
---|
| 671 | // compute pointer on PTE2 |
---|
| 672 | pte2_ptr = &pt2[2 * ix2]; |
---|
| 673 | |
---|
| 674 | // try to atomically lock the PTE2 until success |
---|
| 675 | do |
---|
| 676 | { |
---|
[401] | 677 | // busy waiting until TSAR_MMU_LOCK == 0 |
---|
[1] | 678 | do |
---|
| 679 | { |
---|
| 680 | attr = *pte2_ptr; |
---|
| 681 | hal_rdbar(); |
---|
| 682 | } |
---|
[401] | 683 | while( (attr & TSAR_MMU_LOCKED) != 0 ); |
---|
[1] | 684 | |
---|
[401] | 685 | atomic = hal_atomic_cas( (void*)pte2_ptr, attr , (attr | TSAR_MMU_LOCKED) ); |
---|
[1] | 686 | } |
---|
| 687 | while( atomic == 0 ); |
---|
| 688 | |
---|
| 689 | return 0; |
---|
[401] | 690 | |
---|
[1] | 691 | } // end hal_gpt_lock_pte() |
---|
| 692 | |
---|
| 693 | //////////////////////////////////////// |
---|
| 694 | error_t hal_gpt_unlock_pte( gpt_t * gpt, |
---|
| 695 | vpn_t vpn ) |
---|
| 696 | { |
---|
| 697 | uint32_t * pt1; // PT1 base address |
---|
| 698 | uint32_t pte1; // value of PT1 entry |
---|
| 699 | |
---|
| 700 | uint32_t * pt2; // PT2 base address |
---|
| 701 | ppn_t pt2_ppn; // PPN of PT2 page if missing PT2 |
---|
| 702 | uint32_t * pte2_ptr; // address of PT2 entry |
---|
| 703 | |
---|
| 704 | uint32_t attr; // PTE2 attribute |
---|
| 705 | |
---|
| 706 | // compute indexes in P1 and PT2 |
---|
| 707 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); // index in PT1 |
---|
| 708 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); // index in PT2 |
---|
| 709 | |
---|
| 710 | // get pointer on PT1 base |
---|
| 711 | pt1 = (uint32_t*)gpt->ptr; |
---|
| 712 | |
---|
| 713 | // get PTE1 |
---|
| 714 | pte1 = pt1[ix1]; |
---|
| 715 | |
---|
| 716 | // check PTE1 present and small page |
---|
[401] | 717 | if( ((pte1 & TSAR_MMU_MAPPED) == 0) || ((pte1 & TSAR_MMU_SMALL) == 0) ) |
---|
[1] | 718 | { |
---|
| 719 | printk("\n[ERROR] in %s : try to unlock a big or undefined page / PT1[%d] = %x\n", |
---|
| 720 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 721 | return EINVAL; |
---|
| 722 | } |
---|
| 723 | |
---|
| 724 | // get pointer on PT2 base |
---|
| 725 | pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 ); |
---|
[587] | 726 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 727 | |
---|
| 728 | // get pointer on PTE2 |
---|
| 729 | pte2_ptr = &pt2[2 * ix2]; |
---|
| 730 | |
---|
| 731 | // get PTE2_ATTR |
---|
| 732 | attr = *pte2_ptr; |
---|
| 733 | |
---|
| 734 | // check PTE2 present and locked |
---|
[420] | 735 | if( ((attr & TSAR_MMU_MAPPED) == 0) || ((attr & TSAR_MMU_LOCKED) == 0) ) |
---|
[1] | 736 | { |
---|
[401] | 737 | printk("\n[ERROR] in %s : unlock an unlocked/unmapped page / PT1[%d] = %x\n", |
---|
[1] | 738 | __FUNCTION__ , ix1 , pte1 ); |
---|
| 739 | return EINVAL; |
---|
| 740 | } |
---|
| 741 | |
---|
| 742 | // reset GPT_LOCK |
---|
[401] | 743 | *pte2_ptr = attr & ~TSAR_MMU_LOCKED; |
---|
[1] | 744 | |
---|
| 745 | return 0; |
---|
[401] | 746 | |
---|
[1] | 747 | } // end hal_gpt_unlock_pte() |
---|
| 748 | |
---|
[408] | 749 | /////////////////////////////////////////// |
---|
| 750 | error_t hal_gpt_pte_copy( gpt_t * dst_gpt, |
---|
| 751 | xptr_t src_gpt_xp, |
---|
| 752 | vpn_t vpn, |
---|
| 753 | bool_t cow, |
---|
| 754 | ppn_t * ppn, |
---|
| 755 | bool_t * mapped ) |
---|
[23] | 756 | { |
---|
| 757 | uint32_t ix1; // index in PT1 |
---|
| 758 | uint32_t ix2; // index in PT2 |
---|
[1] | 759 | |
---|
[408] | 760 | cxy_t src_cxy; // SRC GPT cluster |
---|
| 761 | gpt_t * src_gpt; // SRC GPT local pointer |
---|
[1] | 762 | |
---|
[408] | 763 | uint32_t * src_pt1; // local pointer on SRC PT1 |
---|
| 764 | uint32_t * dst_pt1; // local pointer on DST PT1 |
---|
| 765 | uint32_t * src_pt2; // local pointer on SRC PT2 |
---|
| 766 | uint32_t * dst_pt2; // local pointer on DST PT2 |
---|
| 767 | |
---|
[587] | 768 | kmem_req_t req; // for PT2 allocation |
---|
[407] | 769 | |
---|
| 770 | uint32_t src_pte1; |
---|
| 771 | uint32_t dst_pte1; |
---|
| 772 | |
---|
[408] | 773 | uint32_t src_pte2_attr; |
---|
| 774 | uint32_t src_pte2_ppn; |
---|
[1] | 775 | |
---|
[23] | 776 | page_t * page; |
---|
[315] | 777 | xptr_t page_xp; |
---|
[1] | 778 | |
---|
[23] | 779 | ppn_t src_pt2_ppn; |
---|
| 780 | ppn_t dst_pt2_ppn; |
---|
[1] | 781 | |
---|
[587] | 782 | // get remote src_gpt cluster and local pointer |
---|
| 783 | src_cxy = GET_CXY( src_gpt_xp ); |
---|
| 784 | src_gpt = GET_PTR( src_gpt_xp ); |
---|
| 785 | |
---|
| 786 | #if DEBUG_HAL_GPT_COPY |
---|
| 787 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 788 | thread_t * this = CURRENT_THREAD; |
---|
| 789 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[611] | 790 | printk("\n[%s] : thread[%x,%x] enter / vpn %x / src_cxy %x / dst_cxy %x / cycle %d\n", |
---|
[587] | 791 | __FUNCTION__, this->process->pid, this->trdid, vpn, src_cxy, local_cxy, cycle ); |
---|
[432] | 792 | #endif |
---|
[407] | 793 | |
---|
[408] | 794 | // get remote src_gpt cluster and local pointer |
---|
| 795 | src_cxy = GET_CXY( src_gpt_xp ); |
---|
[587] | 796 | src_gpt = GET_PTR( src_gpt_xp ); |
---|
[407] | 797 | |
---|
[408] | 798 | // get remote src_pt1 and local dst_pt1 |
---|
| 799 | src_pt1 = (uint32_t *)hal_remote_lpt( XPTR( src_cxy , &src_gpt->ptr ) ); |
---|
[23] | 800 | dst_pt1 = (uint32_t *)dst_gpt->ptr; |
---|
[1] | 801 | |
---|
[408] | 802 | // check src_pt1 and dst_pt1 existence |
---|
[492] | 803 | assert( (src_pt1 != NULL) , "src_pt1 does not exist\n"); |
---|
| 804 | assert( (dst_pt1 != NULL) , "dst_pt1 does not exist\n"); |
---|
[407] | 805 | |
---|
[408] | 806 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 807 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[407] | 808 | |
---|
[408] | 809 | // get src_pte1 |
---|
[570] | 810 | src_pte1 = hal_remote_l32( XPTR( src_cxy , &src_pt1[ix1] ) ); |
---|
[407] | 811 | |
---|
[408] | 812 | // do nothing if src_pte1 not MAPPED or not SMALL |
---|
| 813 | if( (src_pte1 & TSAR_MMU_MAPPED) && (src_pte1 & TSAR_MMU_SMALL) ) |
---|
| 814 | { |
---|
| 815 | // get dst_pt1 entry |
---|
| 816 | dst_pte1 = dst_pt1[ix1]; |
---|
[407] | 817 | |
---|
[408] | 818 | // map dst_pte1 if required |
---|
| 819 | if( (dst_pte1 & TSAR_MMU_MAPPED) == 0 ) |
---|
| 820 | { |
---|
| 821 | // allocate one physical page for a new PT2 |
---|
| 822 | req.type = KMEM_PAGE; |
---|
| 823 | req.size = 0; // 1 small page |
---|
| 824 | req.flags = AF_KERNEL | AF_ZERO; |
---|
| 825 | page = (page_t *)kmem_alloc( &req ); |
---|
[407] | 826 | |
---|
[408] | 827 | if( page == NULL ) |
---|
| 828 | { |
---|
| 829 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
---|
| 830 | return -1; |
---|
| 831 | } |
---|
[407] | 832 | |
---|
[408] | 833 | // build extended pointer on page descriptor |
---|
| 834 | page_xp = XPTR( local_cxy , page ); |
---|
[407] | 835 | |
---|
[408] | 836 | // get PPN for this new PT2 |
---|
| 837 | dst_pt2_ppn = (ppn_t)ppm_page2ppn( page_xp ); |
---|
[407] | 838 | |
---|
[408] | 839 | // build the new dst_pte1 |
---|
| 840 | dst_pte1 = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | dst_pt2_ppn; |
---|
[407] | 841 | |
---|
[408] | 842 | // register it in DST_GPT |
---|
| 843 | dst_pt1[ix1] = dst_pte1; |
---|
| 844 | } |
---|
[407] | 845 | |
---|
[408] | 846 | // get pointer on src_pt2 |
---|
| 847 | src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( src_pte1 ); |
---|
[587] | 848 | src_pt2 = GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
---|
[407] | 849 | |
---|
[408] | 850 | // get pointer on dst_pt2 |
---|
| 851 | dst_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( dst_pte1 ); |
---|
[587] | 852 | dst_pt2 = GET_PTR( ppm_ppn2base( dst_pt2_ppn ) ); |
---|
[407] | 853 | |
---|
[408] | 854 | // get attr and ppn from SRC_PT2 |
---|
[570] | 855 | src_pte2_attr = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * ix2] ) ); |
---|
| 856 | src_pte2_ppn = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * ix2 + 1] ) ); |
---|
[407] | 857 | |
---|
[408] | 858 | // do nothing if src_pte2 not MAPPED |
---|
| 859 | if( (src_pte2_attr & TSAR_MMU_MAPPED) != 0 ) |
---|
| 860 | { |
---|
| 861 | // set PPN in DST PTE2 |
---|
| 862 | dst_pt2[2*ix2+1] = src_pte2_ppn; |
---|
| 863 | |
---|
| 864 | // set attributes in DST PTE2 |
---|
| 865 | if( cow && (src_pte2_attr & TSAR_MMU_WRITABLE) ) |
---|
[407] | 866 | { |
---|
[408] | 867 | dst_pt2[2*ix2] = (src_pte2_attr | TSAR_MMU_COW) & (~TSAR_MMU_WRITABLE); |
---|
| 868 | } |
---|
| 869 | else |
---|
| 870 | { |
---|
| 871 | dst_pt2[2*ix2] = src_pte2_attr; |
---|
| 872 | } |
---|
[407] | 873 | |
---|
[408] | 874 | // return "successfully copied" |
---|
| 875 | *mapped = true; |
---|
| 876 | *ppn = src_pte2_ppn; |
---|
| 877 | |
---|
[587] | 878 | #if DEBUG_HAL_GPT_COPY |
---|
[432] | 879 | cycle = (uint32_t)hal_get_cycles; |
---|
[587] | 880 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[611] | 881 | printk("\n[%s] : thread[%x,%x] exit / copy done for vpn %x / cycle %d\n", |
---|
[587] | 882 | __FUNCTION__, this->process->pid, this->trdid, vpn, cycle ); |
---|
[432] | 883 | #endif |
---|
[407] | 884 | |
---|
[408] | 885 | hal_fence(); |
---|
[407] | 886 | |
---|
[408] | 887 | return 0; |
---|
| 888 | } // end if PTE2 mapped |
---|
| 889 | } // end if PTE1 mapped |
---|
| 890 | |
---|
| 891 | // return "nothing done" |
---|
| 892 | *mapped = false; |
---|
| 893 | *ppn = 0; |
---|
[432] | 894 | |
---|
[587] | 895 | #if DEBUG_HAL_GPT_COPY |
---|
[432] | 896 | cycle = (uint32_t)hal_get_cycles; |
---|
[587] | 897 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[611] | 898 | printk("\n[%s] : thread[%x,%x] exit / nothing done for vpn %x / cycle %d\n", |
---|
[587] | 899 | __FUNCTION__, this->process->pid, this->trdid, vpn, cycle ); |
---|
[432] | 900 | #endif |
---|
[408] | 901 | |
---|
[407] | 902 | hal_fence(); |
---|
| 903 | |
---|
| 904 | return 0; |
---|
| 905 | |
---|
[408] | 906 | } // end hal_gpt_pte_copy() |
---|
[407] | 907 | |
---|
[408] | 908 | ////////////////////////////////////////// |
---|
| 909 | bool_t hal_gpt_pte_is_mapped( gpt_t * gpt, |
---|
| 910 | vpn_t vpn ) |
---|
| 911 | { |
---|
| 912 | uint32_t * pt1; |
---|
| 913 | uint32_t pte1; |
---|
| 914 | uint32_t pte2_attr; |
---|
| 915 | |
---|
| 916 | uint32_t * pt2; |
---|
| 917 | ppn_t pt2_ppn; |
---|
| 918 | |
---|
| 919 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 920 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 921 | |
---|
| 922 | // get PTE1 value |
---|
| 923 | pt1 = gpt->ptr; |
---|
| 924 | pte1 = pt1[ix1]; |
---|
| 925 | |
---|
| 926 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
| 927 | |
---|
| 928 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) return false; |
---|
| 929 | |
---|
| 930 | // compute PT2 base address |
---|
| 931 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 932 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[408] | 933 | |
---|
| 934 | // get pte2_attr |
---|
| 935 | pte2_attr = pt2[2*ix2]; |
---|
| 936 | |
---|
| 937 | if( (pte2_attr & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
| 938 | else return true; |
---|
| 939 | |
---|
| 940 | } // end hal_gpt_pte_is_mapped() |
---|
| 941 | |
---|
[407] | 942 | /////////////////////////////////////// |
---|
| 943 | bool_t hal_gpt_pte_is_cow( gpt_t * gpt, |
---|
| 944 | vpn_t vpn ) |
---|
| 945 | { |
---|
| 946 | uint32_t * pt1; |
---|
| 947 | uint32_t pte1; |
---|
[408] | 948 | uint32_t pte2_attr; |
---|
[407] | 949 | |
---|
| 950 | uint32_t * pt2; |
---|
| 951 | ppn_t pt2_ppn; |
---|
| 952 | |
---|
| 953 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 954 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 955 | |
---|
| 956 | // get PTE1 value |
---|
| 957 | pt1 = gpt->ptr; |
---|
| 958 | pte1 = pt1[ix1]; |
---|
| 959 | |
---|
[408] | 960 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
[407] | 961 | |
---|
[408] | 962 | if( (pte1 & TSAR_MMU_SMALL) == 0 ) return false; |
---|
[407] | 963 | |
---|
[408] | 964 | // compute PT2 base address |
---|
| 965 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 966 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[408] | 967 | |
---|
| 968 | // get pte2_attr |
---|
| 969 | pte2_attr = pt2[2*ix2]; |
---|
| 970 | |
---|
| 971 | if( (pte2_attr & TSAR_MMU_MAPPED) == 0 ) return false; |
---|
| 972 | |
---|
| 973 | if( (pte2_attr & TSAR_MMU_COW) == 0 ) return false; |
---|
| 974 | else return true; |
---|
| 975 | |
---|
[407] | 976 | } // end hal_gpt_pte_is_cow() |
---|
| 977 | |
---|
[408] | 978 | ///////////////////////////////////////// |
---|
[432] | 979 | void hal_gpt_set_cow( xptr_t gpt_xp, |
---|
| 980 | vpn_t vpn_base, |
---|
| 981 | vpn_t vpn_size ) |
---|
[408] | 982 | { |
---|
| 983 | cxy_t gpt_cxy; |
---|
| 984 | gpt_t * gpt_ptr; |
---|
[407] | 985 | |
---|
[408] | 986 | vpn_t vpn; |
---|
[407] | 987 | |
---|
[408] | 988 | uint32_t ix1; |
---|
| 989 | uint32_t ix2; |
---|
[407] | 990 | |
---|
[408] | 991 | uint32_t * pt1; |
---|
| 992 | uint32_t pte1; |
---|
[407] | 993 | |
---|
[408] | 994 | uint32_t * pt2; |
---|
| 995 | ppn_t pt2_ppn; |
---|
[432] | 996 | uint32_t attr; |
---|
[407] | 997 | |
---|
[408] | 998 | // get GPT cluster and local pointer |
---|
| 999 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
[587] | 1000 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
[407] | 1001 | |
---|
[408] | 1002 | // get local PT1 pointer |
---|
| 1003 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[407] | 1004 | |
---|
[408] | 1005 | // loop on pages |
---|
| 1006 | for( vpn = vpn_base ; vpn < (vpn_base + vpn_size) ; vpn++ ) |
---|
| 1007 | { |
---|
| 1008 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 1009 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[407] | 1010 | |
---|
[408] | 1011 | // get PTE1 value |
---|
[570] | 1012 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[407] | 1013 | |
---|
[408] | 1014 | // only MAPPED & SMALL PTEs are modified |
---|
| 1015 | if( (pte1 & TSAR_MMU_MAPPED) && (pte1 & TSAR_MMU_SMALL) ) |
---|
| 1016 | { |
---|
| 1017 | // compute PT2 base address |
---|
| 1018 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 1019 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[407] | 1020 | |
---|
[492] | 1021 | assert( (GET_CXY( ppm_ppn2base( pt2_ppn ) ) == gpt_cxy ), |
---|
[408] | 1022 | "PT2 and PT1 must be in the same cluster\n"); |
---|
| 1023 | |
---|
| 1024 | // get current PTE2 attributes |
---|
[570] | 1025 | attr = hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2] ) ); |
---|
[408] | 1026 | |
---|
| 1027 | // only MAPPED PTEs are modified |
---|
[432] | 1028 | if( attr & TSAR_MMU_MAPPED ) |
---|
[23] | 1029 | { |
---|
[432] | 1030 | attr = (attr | TSAR_MMU_COW) & (~TSAR_MMU_WRITABLE); |
---|
[570] | 1031 | hal_remote_s32( XPTR( gpt_cxy , &pt2[2*ix2] ) , attr ); |
---|
[432] | 1032 | } |
---|
| 1033 | } |
---|
[408] | 1034 | } // end loop on pages |
---|
[23] | 1035 | |
---|
[432] | 1036 | } // end hal_gpt_set_cow() |
---|
[315] | 1037 | |
---|
[408] | 1038 | ////////////////////////////////////////// |
---|
| 1039 | void hal_gpt_update_pte( xptr_t gpt_xp, |
---|
| 1040 | vpn_t vpn, |
---|
| 1041 | uint32_t attr, // generic GPT attributes |
---|
| 1042 | ppn_t ppn ) |
---|
| 1043 | { |
---|
| 1044 | uint32_t * pt1; // PT1 base addres |
---|
| 1045 | uint32_t pte1; // PT1 entry value |
---|
[23] | 1046 | |
---|
[408] | 1047 | ppn_t pt2_ppn; // PPN of PT2 |
---|
| 1048 | uint32_t * pt2; // PT2 base address |
---|
[23] | 1049 | |
---|
[408] | 1050 | uint32_t ix1; // index in PT1 |
---|
| 1051 | uint32_t ix2; // index in PT2 |
---|
[23] | 1052 | |
---|
[408] | 1053 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
---|
[23] | 1054 | |
---|
[408] | 1055 | // check attr argument MAPPED and SMALL |
---|
| 1056 | if( (attr & GPT_MAPPED) == 0 ) return; |
---|
| 1057 | if( (attr & GPT_SMALL ) == 0 ) return; |
---|
[23] | 1058 | |
---|
[408] | 1059 | // get cluster and local pointer on remote GPT |
---|
| 1060 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
[587] | 1061 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
[23] | 1062 | |
---|
[408] | 1063 | // compute indexes in PT1 and PT2 |
---|
| 1064 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 1065 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[23] | 1066 | |
---|
[408] | 1067 | // get PT1 base |
---|
| 1068 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[23] | 1069 | |
---|
[408] | 1070 | // compute tsar_attr from generic attributes |
---|
| 1071 | tsar_attr = gpt2tsar( attr ); |
---|
[23] | 1072 | |
---|
[408] | 1073 | // get PTE1 value |
---|
[570] | 1074 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[23] | 1075 | |
---|
[408] | 1076 | if( (pte1 & TSAR_MMU_MAPPED) == 0 ) return; |
---|
| 1077 | if( (pte1 & TSAR_MMU_SMALL ) == 0 ) return; |
---|
| 1078 | |
---|
| 1079 | // get PT2 base from PTE1 |
---|
| 1080 | pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 ); |
---|
[587] | 1081 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[408] | 1082 | |
---|
| 1083 | // set PTE2 in this order |
---|
[570] | 1084 | hal_remote_s32( XPTR( gpt_cxy, &pt2[2 * ix2 + 1] ) , ppn ); |
---|
[408] | 1085 | hal_fence(); |
---|
[570] | 1086 | hal_remote_s32( XPTR( gpt_cxy, &pt2[2 * ix2] ) , tsar_attr ); |
---|
[408] | 1087 | hal_fence(); |
---|
| 1088 | |
---|
| 1089 | } // end hal_gpt_update_pte() |
---|
| 1090 | |
---|