[1] | 1 | /* |
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| 2 | * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 |
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| 3 | * |
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[635] | 4 | * Author Alain Greiner (2016,2017,2018,2019) |
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[1] | 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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[457] | 24 | #include <hal_kernel_types.h> |
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[1] | 25 | #include <hal_gpt.h> |
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| 26 | #include <hal_special.h> |
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[640] | 27 | #include <hal_irqmask.h> |
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[1] | 28 | #include <printk.h> |
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| 29 | #include <bits.h> |
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| 30 | #include <process.h> |
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| 31 | #include <kmem.h> |
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| 32 | #include <thread.h> |
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| 33 | #include <cluster.h> |
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| 34 | #include <ppm.h> |
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| 35 | #include <page.h> |
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| 36 | |
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| 37 | //////////////////////////////////////////////////////////////////////////////////////// |
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[401] | 38 | // This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification) |
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[1] | 39 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 40 | |
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[629] | 41 | #define TSAR_PTE_MAPPED 0x80000000 |
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| 42 | #define TSAR_PTE_SMALL 0x40000000 |
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| 43 | #define TSAR_PTE_LOCAL 0x20000000 |
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| 44 | #define TSAR_PTE_REMOTE 0x10000000 |
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| 45 | #define TSAR_PTE_CACHABLE 0x08000000 |
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| 46 | #define TSAR_PTE_WRITABLE 0x04000000 |
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| 47 | #define TSAR_PTE_EXECUTABLE 0x02000000 |
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| 48 | #define TSAR_PTE_USER 0x01000000 |
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| 49 | #define TSAR_PTE_GLOBAL 0x00800000 |
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| 50 | #define TSAR_PTE_DIRTY 0x00400000 |
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[1] | 51 | |
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[629] | 52 | #define TSAR_PTE_COW 0x00000001 // only for small pages |
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| 53 | #define TSAR_PTE_SWAP 0x00000004 // only for small pages |
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| 54 | #define TSAR_PTE_LOCKED 0x00000008 // only for small pages |
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[1] | 55 | |
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| 56 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 57 | // TSAR MMU related macros (from the TSAR MMU specification) |
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| 58 | // - IX1 on 11 bits |
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| 59 | // - IX2 on 9 bits |
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| 60 | // - PPN on 28 bits |
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| 61 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 62 | |
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| 63 | #define TSAR_MMU_IX1_WIDTH 11 |
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| 64 | #define TSAR_MMU_IX2_WIDTH 9 |
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| 65 | #define TSAR_MMU_PPN_WIDTH 28 |
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| 66 | |
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[401] | 67 | #define TSAR_MMU_PTE1_ATTR_MASK 0xFFC00000 |
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| 68 | #define TSAR_MMU_PTE1_PPN_MASK 0x0007FFFF |
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| 69 | |
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[1] | 70 | #define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF) |
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| 71 | #define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF) |
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| 72 | |
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[635] | 73 | #define TSAR_MMU_PPN2_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF) |
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| 74 | #define TSAR_MMU_PPN1_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9) |
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[1] | 75 | #define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000) |
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| 76 | |
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| 77 | #define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF) |
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| 78 | #define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF) |
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| 79 | |
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[401] | 80 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 81 | // This static function translates the GPT attributes to the TSAR attributes |
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| 82 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 83 | static inline uint32_t gpt2tsar( uint32_t gpt_attr ) |
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| 84 | { |
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| 85 | uint32_t tsar_attr = 0; |
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| 86 | |
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[629] | 87 | if( gpt_attr & GPT_MAPPED ) tsar_attr |= TSAR_PTE_MAPPED; |
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| 88 | if( gpt_attr & GPT_SMALL ) tsar_attr |= TSAR_PTE_SMALL; |
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| 89 | if( gpt_attr & GPT_WRITABLE ) tsar_attr |= TSAR_PTE_WRITABLE; |
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| 90 | if( gpt_attr & GPT_EXECUTABLE ) tsar_attr |= TSAR_PTE_EXECUTABLE; |
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| 91 | if( gpt_attr & GPT_CACHABLE ) tsar_attr |= TSAR_PTE_CACHABLE; |
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| 92 | if( gpt_attr & GPT_USER ) tsar_attr |= TSAR_PTE_USER; |
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| 93 | if( gpt_attr & GPT_DIRTY ) tsar_attr |= TSAR_PTE_DIRTY; |
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| 94 | if( gpt_attr & GPT_ACCESSED ) tsar_attr |= TSAR_PTE_LOCAL; |
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| 95 | if( gpt_attr & GPT_GLOBAL ) tsar_attr |= TSAR_PTE_GLOBAL; |
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| 96 | if( gpt_attr & GPT_COW ) tsar_attr |= TSAR_PTE_COW; |
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| 97 | if( gpt_attr & GPT_SWAP ) tsar_attr |= TSAR_PTE_SWAP; |
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| 98 | if( gpt_attr & GPT_LOCKED ) tsar_attr |= TSAR_PTE_LOCKED; |
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[401] | 99 | |
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| 100 | return tsar_attr; |
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| 101 | } |
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| 102 | |
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| 103 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 104 | // This static function translates the TSAR attributes to the GPT attributes |
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| 105 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 106 | static inline uint32_t tsar2gpt( uint32_t tsar_attr ) |
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| 107 | { |
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| 108 | uint32_t gpt_attr = 0; |
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| 109 | |
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[629] | 110 | if( tsar_attr & TSAR_PTE_MAPPED ) gpt_attr |= GPT_MAPPED; |
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| 111 | if( tsar_attr & TSAR_PTE_MAPPED ) gpt_attr |= GPT_READABLE; |
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| 112 | if( tsar_attr & TSAR_PTE_SMALL ) gpt_attr |= GPT_SMALL; |
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| 113 | if( tsar_attr & TSAR_PTE_WRITABLE ) gpt_attr |= GPT_WRITABLE; |
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| 114 | if( tsar_attr & TSAR_PTE_EXECUTABLE ) gpt_attr |= GPT_EXECUTABLE; |
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| 115 | if( tsar_attr & TSAR_PTE_CACHABLE ) gpt_attr |= GPT_CACHABLE; |
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| 116 | if( tsar_attr & TSAR_PTE_USER ) gpt_attr |= GPT_USER; |
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| 117 | if( tsar_attr & TSAR_PTE_DIRTY ) gpt_attr |= GPT_DIRTY; |
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| 118 | if( tsar_attr & TSAR_PTE_LOCAL ) gpt_attr |= GPT_ACCESSED; |
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| 119 | if( tsar_attr & TSAR_PTE_REMOTE ) gpt_attr |= GPT_ACCESSED; |
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| 120 | if( tsar_attr & TSAR_PTE_GLOBAL ) gpt_attr |= GPT_GLOBAL; |
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| 121 | if( tsar_attr & TSAR_PTE_COW ) gpt_attr |= GPT_COW; |
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| 122 | if( tsar_attr & TSAR_PTE_SWAP ) gpt_attr |= GPT_SWAP; |
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| 123 | if( tsar_attr & TSAR_PTE_LOCKED ) gpt_attr |= GPT_LOCKED; |
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[401] | 124 | |
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| 125 | return gpt_attr; |
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| 126 | } |
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| 127 | |
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[632] | 128 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 129 | // The blocking hal_gpt_lock_pte() function implements a busy-waiting policy to get |
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| 130 | // exclusive access to a specific GPT entry. |
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| 131 | // - when non zero, the following variable defines the max number of iterations |
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| 132 | // in the busy waiting loop. |
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| 133 | // - when zero, the watchdog mechanism is deactivated. |
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| 134 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 135 | |
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[640] | 136 | #define GPT_LOCK_WATCHDOG 100000 |
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[632] | 137 | |
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[1] | 138 | ///////////////////////////////////// |
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| 139 | error_t hal_gpt_create( gpt_t * gpt ) |
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| 140 | { |
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[635] | 141 | void * base; |
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[1] | 142 | |
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[587] | 143 | thread_t * this = CURRENT_THREAD; |
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| 144 | |
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[443] | 145 | #if DEBUG_HAL_GPT_CREATE |
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[587] | 146 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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[443] | 147 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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[635] | 148 | printk("\n[%s] thread[%x,%x] enter / cycle %d\n", |
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[587] | 149 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[432] | 150 | #endif |
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[406] | 151 | |
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[623] | 152 | // check page size |
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[635] | 153 | assert( (CONFIG_PPM_PAGE_SIZE == 4096) , "the TSAR page size must be 4 Kbytes\n" ); |
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[1] | 154 | |
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| 155 | // allocates 2 physical pages for PT1 |
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| 156 | kmem_req_t req; |
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[635] | 157 | req.type = KMEM_PPM; |
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| 158 | req.order = 1; // 2 small pages |
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[1] | 159 | req.flags = AF_KERNEL | AF_ZERO; |
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[635] | 160 | base = kmem_alloc( &req ); |
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[1] | 161 | |
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[635] | 162 | if( base == NULL ) |
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[1] | 163 | { |
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[587] | 164 | printk("\n[PANIC] in %s : no memory for PT1 / process %x / cluster %x\n", |
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| 165 | __FUNCTION__, this->process->pid, local_cxy ); |
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[1] | 166 | return ENOMEM; |
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[406] | 167 | } |
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[1] | 168 | |
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[640] | 169 | // initialze the GPT descriptor |
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| 170 | gpt->ptr = base; |
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| 171 | gpt->pte1_wait_events = 0; |
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| 172 | gpt->pte1_wait_iters = 0; |
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| 173 | gpt->pte2_wait_events = 0; |
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| 174 | gpt->pte2_wait_iters = 0; |
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[315] | 175 | |
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[443] | 176 | #if DEBUG_HAL_GPT_CREATE |
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[587] | 177 | cycle = (uint32_t)hal_get_cycles(); |
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[443] | 178 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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[635] | 179 | printk("\n[%s] thread[%x,%x] exit / pt1_base %x / pt1_ppn %x / cycle %d\n", |
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[640] | 180 | __FUNCTION__, this->process->pid, this->trdid, |
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| 181 | base, ppm_base2ppn( XPTR( local_cxy , base ) ), cycle ); |
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[432] | 182 | #endif |
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[406] | 183 | |
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[1] | 184 | return 0; |
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[406] | 185 | |
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[1] | 186 | } // end hal_gpt_create() |
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| 187 | |
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| 188 | /////////////////////////////////// |
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| 189 | void hal_gpt_destroy( gpt_t * gpt ) |
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| 190 | { |
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| 191 | uint32_t ix1; |
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| 192 | uint32_t ix2; |
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| 193 | uint32_t * pt1; |
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| 194 | uint32_t pte1; |
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| 195 | ppn_t pt2_ppn; |
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| 196 | uint32_t * pt2; |
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| 197 | uint32_t attr; |
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| 198 | kmem_req_t req; |
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| 199 | |
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[640] | 200 | thread_t * this = CURRENT_THREAD; |
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| 201 | |
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[443] | 202 | #if DEBUG_HAL_GPT_DESTROY |
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[587] | 203 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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[443] | 204 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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[635] | 205 | printk("\n[%s] thread[%x,%x] enter / cycle %d\n", |
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[587] | 206 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[443] | 207 | #endif |
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| 208 | |
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[1] | 209 | // get pointer on PT1 |
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| 210 | pt1 = (uint32_t *)gpt->ptr; |
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| 211 | |
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| 212 | // scan the PT1 |
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| 213 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 214 | { |
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| 215 | pte1 = pt1[ix1]; |
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[629] | 216 | |
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| 217 | if( (pte1 & TSAR_PTE_MAPPED) != 0 ) // PTE1 mapped |
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[1] | 218 | { |
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[629] | 219 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // BIG page |
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[1] | 220 | { |
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[640] | 221 | printk("\n[WARNING] %s : valid PTE1 / thread[%x,%x] / ix1 %x\n", |
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| 222 | __FUNCTION__, this->process->pid, this->trdid, ix1 ); |
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[1] | 223 | } |
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[629] | 224 | else // PT2 exist |
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[1] | 225 | { |
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[315] | 226 | // get local pointer on PT2 |
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[635] | 227 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
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| 228 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 229 | |
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[629] | 230 | // scan the PT2 |
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| 231 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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[1] | 232 | { |
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[629] | 233 | attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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| 234 | |
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| 235 | if( (attr & TSAR_PTE_MAPPED) != 0 ) // PTE2 mapped |
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[1] | 236 | { |
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[640] | 237 | printk("\n[WARNING] %s : valid PTE2 / thread[%x,%x] / ix1 %x / ix2 %x\n", |
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| 238 | __FUNCTION__, this->process->pid, this->trdid, ix1, ix2 ); |
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[1] | 239 | } |
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| 240 | } |
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| 241 | |
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[629] | 242 | // release the page allocated for the PT2 |
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[635] | 243 | req.type = KMEM_PPM; |
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| 244 | req.ptr = pt2; |
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[1] | 245 | kmem_free( &req ); |
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| 246 | } |
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| 247 | } |
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| 248 | } |
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| 249 | |
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| 250 | // release the PT1 |
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[635] | 251 | req.type = KMEM_PPM; |
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| 252 | req.ptr = pt1; |
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[1] | 253 | kmem_free( &req ); |
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| 254 | |
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[443] | 255 | #if DEBUG_HAL_GPT_DESTROY |
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[587] | 256 | cycle = (uint32_t)hal_get_cycles(); |
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[443] | 257 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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[635] | 258 | printk("\n[%s] thread[%x,%x] exit / cycle %d\n", |
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[587] | 259 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[443] | 260 | #endif |
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| 261 | |
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[1] | 262 | } // end hal_gpt_destroy() |
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| 263 | |
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[632] | 264 | //////////////////////////////////////////// |
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| 265 | error_t hal_gpt_lock_pte( xptr_t gpt_xp, |
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| 266 | vpn_t vpn, |
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| 267 | uint32_t * attr, |
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| 268 | ppn_t * ppn ) |
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[1] | 269 | { |
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[635] | 270 | uint32_t * pt1; // local pointer on PT1 base |
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| 271 | xptr_t pte1_xp; // extended pointer on PT1[x1] entry |
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| 272 | uint32_t pte1; // value of PT1[x1] entry |
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[629] | 273 | |
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[635] | 274 | kmem_req_t req; // kmem request fro PT2 allocation |
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[629] | 275 | |
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[635] | 276 | uint32_t * pt2; // local pointer on PT2 base |
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[632] | 277 | ppn_t pt2_ppn; // PPN of page containing PT2 |
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| 278 | xptr_t pte2_xp; // extended pointer on PT2[ix2].attr |
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| 279 | uint32_t pte2_attr; // PT2[ix2].attr current value |
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| 280 | uint32_t pte2_ppn; // PT2[ix2].ppn current value |
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[640] | 281 | bool_t success; // used for both PTE1 and PTE2 mapping |
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| 282 | uint32_t count; // watchdog |
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| 283 | uint32_t sr_save; // for critical section |
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[632] | 284 | |
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| 285 | // get cluster and local pointer on GPT |
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| 286 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
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| 287 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
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| 288 | |
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| 289 | #if DEBUG_HAL_GPT_LOCK_PTE |
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| 290 | thread_t * this = CURRENT_THREAD; |
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| 291 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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[640] | 292 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
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| 293 | if( (vpn == 0x3600) && (gpt_cxy == 0x11) ) |
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[635] | 294 | printk("\n[%s] thread[%x,%x] enters / vpn %x in cluster %x / cycle %d\n", |
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[632] | 295 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, cycle ); |
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| 296 | #endif |
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| 297 | |
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| 298 | // get indexes in PTI & PT2 from vpn |
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[635] | 299 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 300 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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[632] | 301 | |
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| 302 | // get local pointer on PT1 |
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[635] | 303 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
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[632] | 304 | |
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[635] | 305 | // build extended pointer on PTE1 == PT1[ix1] |
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| 306 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
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[632] | 307 | |
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| 308 | // get current PT1 entry value |
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[635] | 309 | pte1 = hal_remote_l32( pte1_xp ); |
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[629] | 310 | |
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[640] | 311 | // If PTE1 is unmapped, the calling thread try to map this PTE1. |
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| 312 | // To prevent multiple concurrent PT2 allocations, only the thread that |
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| 313 | // successfully locked the PTE1 allocates a new PT2 and updates the PTE1. |
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| 314 | // All other threads simply wait until the missing PTE1 is mapped. |
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[632] | 315 | |
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[640] | 316 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) |
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[629] | 317 | { |
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[640] | 318 | if( (pte1 & TSAR_PTE_LOCKED) == 0 ) |
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| 319 | { |
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| 320 | // try to atomically lock the PTE1 |
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| 321 | success = hal_remote_atomic_cas( pte1_xp, |
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| 322 | pte1, |
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| 323 | TSAR_PTE_LOCKED ); |
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| 324 | } |
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| 325 | else |
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| 326 | { |
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| 327 | success = false; |
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| 328 | } |
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| 329 | |
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| 330 | if( success ) // winner thread allocates one 4 Kbytes page for PT2 |
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| 331 | { |
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| 332 | // enter critical section |
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| 333 | hal_disable_irq( &sr_save ); |
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| 334 | |
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[635] | 335 | req.type = KMEM_PPM; |
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| 336 | req.order = 0; |
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| 337 | req.flags = AF_ZERO | AF_KERNEL; |
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| 338 | pt2 = kmem_remote_alloc( gpt_cxy , &req ); |
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[629] | 339 | |
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[635] | 340 | if( pt2 == NULL ) |
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[629] | 341 | { |
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[635] | 342 | printk("\n[ERROR] in %s : cannot allocate memory for PT2 in cluster %d\n", |
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| 343 | __FUNCTION__, gpt_cxy ); |
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[632] | 344 | return -1; |
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[629] | 345 | } |
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| 346 | |
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| 347 | // get the PT2 PPN |
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[635] | 348 | pt2_ppn = ppm_base2ppn( XPTR( gpt_cxy , pt2 ) ); |
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[629] | 349 | |
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[635] | 350 | // build PTE1 |
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| 351 | pte1 = TSAR_PTE_MAPPED | TSAR_PTE_SMALL | pt2_ppn; |
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[629] | 352 | |
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[640] | 353 | // set the PTE1 value in PT1 / this unlocks the PTE1 |
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[635] | 354 | hal_remote_s32( pte1_xp , pte1 ); |
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[629] | 355 | hal_fence(); |
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| 356 | |
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[640] | 357 | // exit critical section |
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| 358 | hal_restore_irq( sr_save ); |
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| 359 | |
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| 360 | #if DEBUG_HAL_GPT_LOCK_PTE |
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| 361 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
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| 362 | if( (vpn == 0x3600) && (gpt_cxy == 0x11) ) |
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| 363 | printk("\n[%s] PTE1 unmapped : winner thread[%x,%x] allocates a PT2 for vpn %x in cluster %x\n", |
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[632] | 364 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy ); |
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[629] | 365 | #endif |
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[632] | 366 | |
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[640] | 367 | } |
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| 368 | else // other threads wait until PTE1 mapped by the winner |
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| 369 | { |
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[632] | 370 | |
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[640] | 371 | #if DEBUG_HAL_GPT_LOCK_PTE |
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| 372 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
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| 373 | if( (vpn == 0x3600) && (gpt_cxy == 0x11) ) |
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| 374 | printk("\n[%s] PTE1 unmapped : loser thread[%x,%x] wait PTE1 for vpn %x in cluster %x\n", |
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| 375 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy ); |
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| 376 | #endif |
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[629] | 377 | |
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[640] | 378 | count = 0; |
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| 379 | do |
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| 380 | { |
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| 381 | // get current pte1 value |
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| 382 | pte1 = hal_remote_l32( pte1_xp ); |
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| 383 | |
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| 384 | // check iterations number |
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| 385 | if( count > GPT_LOCK_WATCHDOG ) |
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| 386 | { |
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| 387 | thread_t * this = CURRENT_THREAD; |
---|
| 388 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 389 | printk("\n[PANIC] in %s for PTE1 after %d iterations\n" |
---|
| 390 | " thread[%x,%x] / vpn %x / cluster %x / pte1 %x / cycle %d\n", |
---|
| 391 | __FUNCTION__, count, this->process->pid, this->trdid, |
---|
| 392 | vpn, gpt_cxy, pte1, cycle ); |
---|
| 393 | |
---|
| 394 | xptr_t process_xp = cluster_get_process_from_pid_in_cxy( gpt_cxy, |
---|
| 395 | this->process->pid ); |
---|
| 396 | hal_vmm_display( process_xp , true ); |
---|
| 397 | |
---|
| 398 | hal_core_sleep(); |
---|
| 399 | } |
---|
| 400 | |
---|
| 401 | // increment watchdog |
---|
| 402 | count++; |
---|
| 403 | } |
---|
| 404 | while( (pte1 & TSAR_PTE_MAPPED) == 0 ); |
---|
| 405 | |
---|
| 406 | #if CONFIG_INSTRUMENTATION_GPT |
---|
| 407 | hal_remote_atomic_add( XPTR( gpt_cxy , &gpt_ptr->pte1_wait_events ) , 1 ); |
---|
| 408 | hal_remote_atomic_add( XPTR( gpt_cxy , &gpt_ptr->pte1_wait_iters ) , count ); |
---|
[629] | 409 | #endif |
---|
| 410 | |
---|
| 411 | |
---|
[640] | 412 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
| 413 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
| 414 | if( (vpn == 0x3600) && (gpt_cxy == 0x11) ) |
---|
| 415 | printk("\n[%s] PTE1 unmapped : loser thread[%x,%x] get PTE1 for vpn %x in cluster %x\n", |
---|
| 416 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy ); |
---|
| 417 | #endif |
---|
| 418 | } |
---|
| 419 | } // end if pte1 unmapped |
---|
[629] | 420 | |
---|
[640] | 421 | // This code is executed by all calling threads |
---|
| 422 | |
---|
| 423 | // check PTE1 : only small and mapped pages can be locked |
---|
| 424 | assert( (pte1 & (TSAR_PTE_SMALL | TSAR_PTE_MAPPED)) , "cannot lock a big or unmapped page\n"); |
---|
| 425 | |
---|
| 426 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
| 427 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
| 428 | if( (vpn == 0x3600) && (gpt_cxy == 0x11) ) |
---|
[635] | 429 | printk("\n[%s] thread[%x,%x] get pte1 %x for vpn %x in cluster %x\n", |
---|
| 430 | __FUNCTION__, this->process->pid, this->trdid, pte1, vpn, gpt_cxy ); |
---|
[632] | 431 | #endif |
---|
[629] | 432 | |
---|
[635] | 433 | // get pointer on PT2 base |
---|
| 434 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
| 435 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[629] | 436 | |
---|
[632] | 437 | // build extended pointers on PT2[ix2].attr |
---|
[635] | 438 | pte2_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
[629] | 439 | |
---|
[640] | 440 | // initialize external loop watchdog |
---|
| 441 | count = 0; |
---|
| 442 | |
---|
| 443 | // in this busy waiting loop, each thread try to atomically |
---|
| 444 | // lock the PTE2, after checking that the PTE2 is not locked |
---|
| 445 | |
---|
[632] | 446 | do |
---|
[629] | 447 | { |
---|
[640] | 448 | // get current value of pte2_attr |
---|
| 449 | pte2_attr = hal_remote_l32( pte2_xp ); |
---|
[629] | 450 | |
---|
[640] | 451 | // check loop watchdog |
---|
| 452 | if( count > GPT_LOCK_WATCHDOG ) |
---|
[633] | 453 | { |
---|
[640] | 454 | thread_t * this = CURRENT_THREAD; |
---|
| 455 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 456 | printk("\n[PANIC] in %s for PTE2 after %d iterations\n" |
---|
| 457 | " thread[%x,%x] / vpn %x / cluster %x / pte2_attr %x / cycle %d\n", |
---|
| 458 | __FUNCTION__, count, this->process->pid, this->trdid, |
---|
| 459 | vpn, gpt_cxy, pte2_attr, cycle ); |
---|
[632] | 460 | |
---|
[640] | 461 | xptr_t process_xp = cluster_get_process_from_pid_in_cxy( gpt_cxy, |
---|
| 462 | this->process->pid ); |
---|
| 463 | hal_vmm_display( process_xp , true ); |
---|
| 464 | |
---|
| 465 | hal_core_sleep(); |
---|
[633] | 466 | } |
---|
[629] | 467 | |
---|
[640] | 468 | // increment loop watchdog |
---|
| 469 | count++; |
---|
| 470 | |
---|
| 471 | if( (pte2_attr & TSAR_PTE_LOCKED) == 0 ) |
---|
| 472 | { |
---|
| 473 | // try to atomically set the TSAR_PTE_LOCKED attribute |
---|
| 474 | success = hal_remote_atomic_cas( pte2_xp, |
---|
| 475 | pte2_attr, |
---|
| 476 | (pte2_attr | TSAR_PTE_LOCKED) ); |
---|
| 477 | } |
---|
| 478 | else |
---|
| 479 | { |
---|
| 480 | success = false; |
---|
| 481 | } |
---|
[633] | 482 | } |
---|
[640] | 483 | while( success == false ); |
---|
[629] | 484 | |
---|
[640] | 485 | #if CONFIG_INSTRUMENTATION_GPT |
---|
| 486 | hal_remote_atomic_add( XPTR( gpt_cxy , &gpt_ptr->pte2_wait_events ) , 1 ); |
---|
| 487 | hal_remote_atomic_add( XPTR( gpt_cxy , &gpt_ptr->pte2_wait_iters ) , count ); |
---|
| 488 | #endif |
---|
| 489 | |
---|
[629] | 490 | // get PTE2.ppn |
---|
[632] | 491 | pte2_ppn = hal_remote_l32( pte2_xp + 4 ); |
---|
[629] | 492 | |
---|
| 493 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
[632] | 494 | cycle = (uint32_t)hal_get_cycles(); |
---|
[640] | 495 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
| 496 | if( (vpn == 0x3600) && (gpt_cxy == 0x11) ) |
---|
| 497 | printk("\n[%s] thread[%x,%x] success / vpn %x in cluster %x / attr %x / ppn %x / cycle %d\n", |
---|
[632] | 498 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, pte2_attr, pte2_ppn, cycle ); |
---|
[629] | 499 | #endif |
---|
| 500 | |
---|
| 501 | // return PPN and GPT attributes |
---|
[632] | 502 | *ppn = pte2_ppn & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
[629] | 503 | *attr = tsar2gpt( pte2_attr ); |
---|
[633] | 504 | return 0; |
---|
[629] | 505 | |
---|
| 506 | } // end hal_gpt_lock_pte() |
---|
| 507 | |
---|
| 508 | //////////////////////////////////////// |
---|
| 509 | void hal_gpt_unlock_pte( xptr_t gpt_xp, |
---|
| 510 | vpn_t vpn ) |
---|
| 511 | { |
---|
[635] | 512 | uint32_t * pt1; // local pointer on PT1 base |
---|
| 513 | xptr_t pte1_xp; // extended pointer on PT1[ix1] |
---|
| 514 | uint32_t pte1; // value of PT1[ix1] entry |
---|
[629] | 515 | |
---|
[635] | 516 | uint32_t * pt2; // PT2 base address |
---|
[629] | 517 | ppn_t pt2_ppn; // PPN of page containing PT2 |
---|
[632] | 518 | xptr_t pte2_xp; // extended pointer on PT2[ix2].attr |
---|
| 519 | uint32_t pte2_attr; // PTE2 attribute |
---|
[629] | 520 | |
---|
| 521 | // get cluster and local pointer on GPT |
---|
| 522 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 523 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
| 524 | |
---|
| 525 | // compute indexes in P1 and PT2 |
---|
[635] | 526 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 527 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[629] | 528 | |
---|
| 529 | // get local pointer on PT1 |
---|
[635] | 530 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[629] | 531 | |
---|
[635] | 532 | // build extended pointer on PTE1 == PT1[ix1] |
---|
| 533 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
---|
[629] | 534 | |
---|
[635] | 535 | // get current pte1 value |
---|
| 536 | pte1 = hal_remote_l32( pte1_xp ); |
---|
[629] | 537 | |
---|
[640] | 538 | assert( ((pte1 & TSAR_PTE_MAPPED) != 0), |
---|
| 539 | "PTE1 for vpn %x in cluster %x is unmapped / pte1 = %x\n", vpn, gpt_cxy, pte1 ); |
---|
[629] | 540 | |
---|
[640] | 541 | assert( ((pte1 & TSAR_PTE_SMALL ) != 0), |
---|
| 542 | "PTE1 for vpn %x in cluster %x is not small / pte1 = %x\n", vpn, gpt_cxy, pte1 ); |
---|
| 543 | |
---|
[635] | 544 | // get pointer on PT2 base |
---|
| 545 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
| 546 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[629] | 547 | |
---|
| 548 | // build extended pointers on PT2[ix2].attr |
---|
[635] | 549 | pte2_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
[629] | 550 | |
---|
| 551 | // get PT2[ix2].attr |
---|
[632] | 552 | pte2_attr = hal_remote_l32( pte2_xp ); |
---|
[629] | 553 | |
---|
[640] | 554 | assert( ((pte2_attr & TSAR_PTE_LOCKED) != 0), |
---|
| 555 | "PTE2 for vpn %x in cluster %x is unlocked / pte2_attr = %x\n", vpn, gpt_cxy, pte2_attr ); |
---|
[629] | 556 | |
---|
[632] | 557 | // reset TSAR_PTE_LOCKED attribute |
---|
| 558 | hal_remote_s32( pte2_xp , pte2_attr & ~TSAR_PTE_LOCKED ); |
---|
| 559 | |
---|
[629] | 560 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
[640] | 561 | thread_t * this = CURRENT_THREAD; |
---|
| 562 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 563 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
| 564 | if( (vpn == 0xc5fff) && (gpt_cxy == 0x1) ) |
---|
[635] | 565 | printk("\n[%s] thread[%x,%x] unlocks vpn %x in cluster %x / cycle %d\n", |
---|
[632] | 566 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, cycle ); |
---|
[629] | 567 | #endif |
---|
[632] | 568 | |
---|
[629] | 569 | } // end hal_gpt_unlock_pte() |
---|
| 570 | |
---|
[632] | 571 | |
---|
[629] | 572 | /////////////////////////////////////// |
---|
| 573 | void hal_gpt_set_pte( xptr_t gpt_xp, |
---|
| 574 | vpn_t vpn, |
---|
| 575 | uint32_t attr, |
---|
| 576 | ppn_t ppn ) |
---|
| 577 | { |
---|
[587] | 578 | cxy_t gpt_cxy; // target GPT cluster |
---|
| 579 | gpt_t * gpt_ptr; // target GPT local pointer |
---|
[629] | 580 | |
---|
[635] | 581 | uint32_t * pt1; // local pointer on PT1 base |
---|
[587] | 582 | xptr_t pte1_xp; // extended pointer on PT1 entry |
---|
| 583 | uint32_t pte1; // PT1 entry value if PTE1 |
---|
[1] | 584 | |
---|
[635] | 585 | uint32_t * pt2; // local pointer on PT2 base |
---|
[401] | 586 | ppn_t pt2_ppn; // PPN of PT2 |
---|
[629] | 587 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
| 588 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
| 589 | uint32_t pte2_attr; // current value of PT2[ix2].attr |
---|
[1] | 590 | |
---|
[401] | 591 | uint32_t ix1; // index in PT1 |
---|
| 592 | uint32_t ix2; // index in PT2 |
---|
[1] | 593 | |
---|
[401] | 594 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
---|
[629] | 595 | uint32_t small; // requested PTE is for a small page |
---|
[401] | 596 | |
---|
[587] | 597 | // get cluster and local pointer on GPT |
---|
| 598 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 599 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
| 600 | |
---|
[1] | 601 | // compute indexes in PT1 and PT2 |
---|
| 602 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 603 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 604 | |
---|
[635] | 605 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 606 | thread_t * this = CURRENT_THREAD; |
---|
| 607 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 608 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
| 609 | printk("\n[%s] thread[%x,%x] enter gpt (%x,%x) / vpn %x / attr %x / ppn %x\n", |
---|
| 610 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, &gpt_ptr->ptr, vpn, attr, ppn ); |
---|
| 611 | #endif |
---|
[1] | 612 | |
---|
[635] | 613 | small = attr & GPT_SMALL; |
---|
| 614 | |
---|
| 615 | // get local pointer on PT1 |
---|
| 616 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
| 617 | |
---|
[432] | 618 | // compute tsar attributes from generic attributes |
---|
[401] | 619 | tsar_attr = gpt2tsar( attr ); |
---|
| 620 | |
---|
[587] | 621 | // build extended pointer on PTE1 = PT1[ix1] |
---|
[635] | 622 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
---|
[406] | 623 | |
---|
[587] | 624 | // get current pte1 value |
---|
| 625 | pte1 = hal_remote_l32( pte1_xp ); |
---|
[1] | 626 | |
---|
[629] | 627 | if( small == 0 ) ///////////////// map a big page in PT1 |
---|
[401] | 628 | { |
---|
[623] | 629 | |
---|
| 630 | // check PT1 entry not mapped |
---|
[629] | 631 | assert( (pte1 == 0) , "try to set a big page in an already mapped PTE1\n" ); |
---|
[623] | 632 | |
---|
| 633 | // check VPN aligned |
---|
| 634 | assert( (ix2 == 0) , "illegal vpn for a big page\n" ); |
---|
| 635 | |
---|
| 636 | // check PPN aligned |
---|
| 637 | assert( ((ppn & 0x1FF) == 0) , "illegal ppn for a big page\n" ); |
---|
| 638 | |
---|
[587] | 639 | // set the PTE1 value in PT1 |
---|
| 640 | pte1 = (tsar_attr & TSAR_MMU_PTE1_ATTR_MASK) | ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK); |
---|
| 641 | hal_remote_s32( pte1_xp , pte1 ); |
---|
[124] | 642 | hal_fence(); |
---|
[587] | 643 | |
---|
| 644 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 645 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[635] | 646 | printk("\n[%s] thread[%x,%x] map PTE1 / cxy %x / ix1 %x / pt1 %x / pte1 %x\n", |
---|
| 647 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1, pte1 ); |
---|
[587] | 648 | #endif |
---|
| 649 | |
---|
[1] | 650 | } |
---|
[629] | 651 | else ///////////////// map a small page in PT2 |
---|
[587] | 652 | { |
---|
[1] | 653 | |
---|
[629] | 654 | // PTE1 must be mapped because PTE2 must be locked |
---|
[640] | 655 | assert( (pte1 & TSAR_PTE_MAPPED), |
---|
| 656 | "PTE1 for vpn %x in cluster %x must be mapped / pte1 = %x\n", vpn, gpt_cxy, pte1 ); |
---|
[1] | 657 | |
---|
[635] | 658 | // get PT2 base |
---|
| 659 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
| 660 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[315] | 661 | |
---|
[629] | 662 | // build extended pointers on PT2[ix2].attr and PT2[ix2].ppn |
---|
[635] | 663 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
| 664 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
---|
[1] | 665 | |
---|
[629] | 666 | // get current value of PTE2.attr |
---|
| 667 | pte2_attr = hal_remote_l32( pte2_attr_xp ); |
---|
[587] | 668 | |
---|
[629] | 669 | // PTE2 must be locked |
---|
[640] | 670 | assert( (pte2_attr & TSAR_PTE_LOCKED), |
---|
| 671 | "PTE2 for vpn %x in cluster %x must be locked / pte2_attr = %x\n", vpn, gpt_cxy, pte2_attr ); |
---|
[629] | 672 | |
---|
[587] | 673 | // set PTE2 in PT2 (in this order) |
---|
[629] | 674 | hal_remote_s32( pte2_ppn_xp , ppn ); |
---|
[587] | 675 | hal_fence(); |
---|
[629] | 676 | hal_remote_s32( pte2_attr_xp , tsar_attr ); |
---|
[587] | 677 | hal_fence(); |
---|
[1] | 678 | |
---|
[587] | 679 | #if DEBUG_HAL_GPT_SET_PTE |
---|
[629] | 680 | thread_t * this = CURRENT_THREAD; |
---|
| 681 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
[587] | 682 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[635] | 683 | printk("\n[%s] thread[%x,%x] map PTE2 / cxy %x / ix2 %x / pt2 %x / attr %x / ppn %x\n", |
---|
| 684 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix2, pt2, tsar_attr, ppn ); |
---|
[432] | 685 | #endif |
---|
| 686 | |
---|
[587] | 687 | } |
---|
[1] | 688 | } // end of hal_gpt_set_pte() |
---|
| 689 | |
---|
[629] | 690 | /////////////////////////////////////// |
---|
| 691 | void hal_gpt_reset_pte( xptr_t gpt_xp, |
---|
| 692 | vpn_t vpn ) |
---|
[1] | 693 | { |
---|
[629] | 694 | cxy_t gpt_cxy; // target GPT cluster |
---|
| 695 | gpt_t * gpt_ptr; // target GPT local pointer |
---|
[1] | 696 | |
---|
[629] | 697 | uint32_t ix1; // index in PT1 |
---|
| 698 | uint32_t ix2; // index in PT2 |
---|
[1] | 699 | |
---|
[635] | 700 | uint32_t * pt1; // PT1 base address |
---|
[629] | 701 | xptr_t pte1_xp; // extended pointer on PT1[ix1] |
---|
| 702 | uint32_t pte1; // PT1 entry value |
---|
[587] | 703 | |
---|
[635] | 704 | uint32_t * pt2; // PT2 base address |
---|
[629] | 705 | ppn_t pt2_ppn; // PPN of PT2 |
---|
| 706 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
| 707 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
[1] | 708 | |
---|
[629] | 709 | // get cluster and local pointer on GPT |
---|
| 710 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 711 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
[1] | 712 | |
---|
[629] | 713 | // get ix1 & ix2 indexes |
---|
| 714 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 715 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[1] | 716 | |
---|
[629] | 717 | // get local pointer on PT1 base |
---|
[635] | 718 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[1] | 719 | |
---|
[629] | 720 | // build extended pointer on PTE1 = PT1[ix1] |
---|
[635] | 721 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
---|
[1] | 722 | |
---|
[629] | 723 | // get current PTE1 value |
---|
| 724 | pte1 = hal_remote_l32( pte1_xp ); |
---|
[1] | 725 | |
---|
[629] | 726 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) // PTE1 unmapped => do nothing |
---|
[1] | 727 | { |
---|
| 728 | return; |
---|
| 729 | } |
---|
| 730 | |
---|
[629] | 731 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // it's a PTE1 => unmap it from PT1 |
---|
[1] | 732 | { |
---|
[629] | 733 | hal_remote_s32( pte1_xp , 0 ); |
---|
[124] | 734 | hal_fence(); |
---|
[1] | 735 | |
---|
[629] | 736 | #if DEBUG_HAL_GPT_RESET_PTE |
---|
| 737 | thread_t * this = CURRENT_THREAD; |
---|
| 738 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 739 | if( DEBUG_HAL_GPT_RESET_PTE < cycle ) |
---|
[635] | 740 | printk("\n[%s] thread[%x,%x] unmap PTE1 / cxy %x / vpn %x / ix1 %x\n", |
---|
[629] | 741 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, vpn, ix1 ); |
---|
| 742 | #endif |
---|
| 743 | |
---|
[1] | 744 | return; |
---|
| 745 | } |
---|
[629] | 746 | else // it's a PTE2 => unmap it from PT2 |
---|
[1] | 747 | { |
---|
[635] | 748 | // get PT2 base |
---|
| 749 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
| 750 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 751 | |
---|
[629] | 752 | // build extended pointer on PT2[ix2].attr and PT2[ix2].ppn |
---|
[635] | 753 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
| 754 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
---|
[629] | 755 | |
---|
| 756 | // unmap the PTE2 |
---|
| 757 | hal_remote_s32( pte2_attr_xp , 0 ); |
---|
[391] | 758 | hal_fence(); |
---|
[629] | 759 | hal_remote_s32( pte2_ppn_xp , 0 ); |
---|
| 760 | hal_fence(); |
---|
[1] | 761 | |
---|
[629] | 762 | #if DEBUG_HAL_GPT_RESET_PTE |
---|
| 763 | thread_t * this = CURRENT_THREAD; |
---|
| 764 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 765 | if( DEBUG_HAL_GPT_RESET_PTE < cycle ) |
---|
[635] | 766 | printk("\n[%s] thread[%x,%x] unmap PTE2 / cxy %x / vpn %x / ix2 %x\n", |
---|
[629] | 767 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, vpn, ix2 ); |
---|
| 768 | #endif |
---|
| 769 | |
---|
[1] | 770 | return; |
---|
| 771 | } |
---|
| 772 | } // end hal_gpt_reset_pte() |
---|
| 773 | |
---|
[629] | 774 | //////////////////////////////////////// |
---|
| 775 | void hal_gpt_get_pte( xptr_t gpt_xp, |
---|
| 776 | vpn_t vpn, |
---|
| 777 | uint32_t * attr, |
---|
| 778 | ppn_t * ppn ) |
---|
[624] | 779 | { |
---|
[629] | 780 | uint32_t * pt1; // local pointer on PT1 base |
---|
| 781 | uint32_t pte1; // PTE1 value |
---|
[624] | 782 | |
---|
[629] | 783 | uint32_t * pt2; // local pointer on PT2 base |
---|
| 784 | ppn_t pt2_ppn; // PPN of page containing the PT2 |
---|
| 785 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
| 786 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
| 787 | uint32_t pte2_attr; // current value of PT2[ix2].attr |
---|
| 788 | ppn_t pte2_ppn; // current value of PT2[ix2].ppn |
---|
[624] | 789 | |
---|
[629] | 790 | // get cluster and local pointer on GPT |
---|
| 791 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 792 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
[624] | 793 | |
---|
[629] | 794 | // compute indexes in PT1 and PT2 |
---|
| 795 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 796 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[624] | 797 | |
---|
[629] | 798 | // get PT1 base |
---|
| 799 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
| 800 | |
---|
| 801 | // get pte1 |
---|
| 802 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[624] | 803 | |
---|
[629] | 804 | // check PTE1 mapped |
---|
| 805 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) // PTE1 unmapped |
---|
[1] | 806 | { |
---|
[629] | 807 | *attr = 0; |
---|
| 808 | *ppn = 0; |
---|
| 809 | return; |
---|
[1] | 810 | } |
---|
| 811 | |
---|
[629] | 812 | // access GPT |
---|
| 813 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // it's a PTE1 |
---|
| 814 | { |
---|
[635] | 815 | // get PPN & ATTR |
---|
[629] | 816 | *attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) ); |
---|
[635] | 817 | *ppn = TSAR_MMU_PPN1_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1)); |
---|
[1] | 818 | } |
---|
[629] | 819 | else // it's a PTE2 |
---|
[1] | 820 | { |
---|
[629] | 821 | // compute PT2 base address |
---|
[635] | 822 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
[629] | 823 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 824 | |
---|
[629] | 825 | // build extended pointer on PT2[ix2].attr and PT2[ix2].ppn |
---|
| 826 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
| 827 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
---|
[1] | 828 | |
---|
[629] | 829 | // get current value of PTE2.attr & PTE2.ppn |
---|
| 830 | pte2_attr = hal_remote_l32( pte2_attr_xp ); |
---|
| 831 | pte2_ppn = hal_remote_l32( pte2_ppn_xp ); |
---|
[1] | 832 | |
---|
[629] | 833 | // return PPN & GPT attributes |
---|
| 834 | *ppn = pte2_ppn & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
| 835 | *attr = tsar2gpt( pte2_attr ); |
---|
[1] | 836 | } |
---|
[629] | 837 | } // end hal_gpt_get_pte() |
---|
[1] | 838 | |
---|
| 839 | |
---|
[408] | 840 | /////////////////////////////////////////// |
---|
| 841 | error_t hal_gpt_pte_copy( gpt_t * dst_gpt, |
---|
[625] | 842 | vpn_t dst_vpn, |
---|
[408] | 843 | xptr_t src_gpt_xp, |
---|
[625] | 844 | vpn_t src_vpn, |
---|
[408] | 845 | bool_t cow, |
---|
| 846 | ppn_t * ppn, |
---|
| 847 | bool_t * mapped ) |
---|
[23] | 848 | { |
---|
[625] | 849 | uint32_t src_ix1; // index in SRC PT1 |
---|
| 850 | uint32_t src_ix2; // index in SRC PT2 |
---|
[1] | 851 | |
---|
[625] | 852 | uint32_t dst_ix1; // index in DST PT1 |
---|
| 853 | uint32_t dst_ix2; // index in DST PT2 |
---|
| 854 | |
---|
[408] | 855 | cxy_t src_cxy; // SRC GPT cluster |
---|
| 856 | gpt_t * src_gpt; // SRC GPT local pointer |
---|
[1] | 857 | |
---|
[408] | 858 | uint32_t * src_pt1; // local pointer on SRC PT1 |
---|
| 859 | uint32_t * dst_pt1; // local pointer on DST PT1 |
---|
[635] | 860 | |
---|
[408] | 861 | uint32_t * src_pt2; // local pointer on SRC PT2 |
---|
| 862 | uint32_t * dst_pt2; // local pointer on DST PT2 |
---|
| 863 | |
---|
[587] | 864 | kmem_req_t req; // for PT2 allocation |
---|
[407] | 865 | |
---|
| 866 | uint32_t src_pte1; |
---|
| 867 | uint32_t dst_pte1; |
---|
| 868 | |
---|
[408] | 869 | uint32_t src_pte2_attr; |
---|
| 870 | uint32_t src_pte2_ppn; |
---|
[1] | 871 | |
---|
[23] | 872 | page_t * page; |
---|
[315] | 873 | xptr_t page_xp; |
---|
[1] | 874 | |
---|
[23] | 875 | ppn_t src_pt2_ppn; |
---|
| 876 | ppn_t dst_pt2_ppn; |
---|
[1] | 877 | |
---|
[587] | 878 | // get remote src_gpt cluster and local pointer |
---|
| 879 | src_cxy = GET_CXY( src_gpt_xp ); |
---|
| 880 | src_gpt = GET_PTR( src_gpt_xp ); |
---|
| 881 | |
---|
| 882 | #if DEBUG_HAL_GPT_COPY |
---|
| 883 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 884 | thread_t * this = CURRENT_THREAD; |
---|
| 885 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[635] | 886 | printk("\n[%s] thread[%x,%x] enter / src_cxy %x / dst_cxy %x / cycle %d\n", |
---|
[625] | 887 | __FUNCTION__, this->process->pid, this->trdid, src_cxy, local_cxy, cycle ); |
---|
[432] | 888 | #endif |
---|
[407] | 889 | |
---|
[408] | 890 | // get remote src_pt1 and local dst_pt1 |
---|
| 891 | src_pt1 = (uint32_t *)hal_remote_lpt( XPTR( src_cxy , &src_gpt->ptr ) ); |
---|
[23] | 892 | dst_pt1 = (uint32_t *)dst_gpt->ptr; |
---|
[1] | 893 | |
---|
[408] | 894 | // check src_pt1 and dst_pt1 existence |
---|
[492] | 895 | assert( (src_pt1 != NULL) , "src_pt1 does not exist\n"); |
---|
| 896 | assert( (dst_pt1 != NULL) , "dst_pt1 does not exist\n"); |
---|
[407] | 897 | |
---|
[625] | 898 | // compute SRC indexes |
---|
| 899 | src_ix1 = TSAR_MMU_IX1_FROM_VPN( src_vpn ); |
---|
| 900 | src_ix2 = TSAR_MMU_IX2_FROM_VPN( src_vpn ); |
---|
[407] | 901 | |
---|
[625] | 902 | // compute DST indexes |
---|
| 903 | dst_ix1 = TSAR_MMU_IX1_FROM_VPN( dst_vpn ); |
---|
| 904 | dst_ix2 = TSAR_MMU_IX2_FROM_VPN( dst_vpn ); |
---|
| 905 | |
---|
[408] | 906 | // get src_pte1 |
---|
[625] | 907 | src_pte1 = hal_remote_l32( XPTR( src_cxy , &src_pt1[src_ix1] ) ); |
---|
[407] | 908 | |
---|
[408] | 909 | // do nothing if src_pte1 not MAPPED or not SMALL |
---|
[629] | 910 | if( (src_pte1 & TSAR_PTE_MAPPED) && (src_pte1 & TSAR_PTE_SMALL) ) |
---|
[408] | 911 | { |
---|
| 912 | // get dst_pt1 entry |
---|
[625] | 913 | dst_pte1 = dst_pt1[dst_ix1]; |
---|
[407] | 914 | |
---|
[635] | 915 | // map dst_pte1 when this entry is not mapped |
---|
[629] | 916 | if( (dst_pte1 & TSAR_PTE_MAPPED) == 0 ) |
---|
[408] | 917 | { |
---|
| 918 | // allocate one physical page for a new PT2 |
---|
[635] | 919 | req.type = KMEM_PPM; |
---|
| 920 | req.order = 0; // 1 small page |
---|
[408] | 921 | req.flags = AF_KERNEL | AF_ZERO; |
---|
[635] | 922 | dst_pt2 = kmem_alloc( &req ); |
---|
[407] | 923 | |
---|
[635] | 924 | if( dst_pt2 == NULL ) |
---|
[408] | 925 | { |
---|
| 926 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
---|
| 927 | return -1; |
---|
| 928 | } |
---|
[407] | 929 | |
---|
[408] | 930 | // build extended pointer on page descriptor |
---|
| 931 | page_xp = XPTR( local_cxy , page ); |
---|
[407] | 932 | |
---|
[408] | 933 | // get PPN for this new PT2 |
---|
[635] | 934 | dst_pt2_ppn = ppm_base2ppn( XPTR( local_cxy , dst_pt2 ) ); |
---|
[407] | 935 | |
---|
[635] | 936 | // build new dst_pte1 |
---|
[629] | 937 | dst_pte1 = TSAR_PTE_MAPPED | TSAR_PTE_SMALL | dst_pt2_ppn; |
---|
[407] | 938 | |
---|
[408] | 939 | // register it in DST_GPT |
---|
[625] | 940 | dst_pt1[dst_ix1] = dst_pte1; |
---|
[408] | 941 | } |
---|
[407] | 942 | |
---|
[408] | 943 | // get pointer on src_pt2 |
---|
[635] | 944 | src_pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( src_pte1 ); |
---|
[587] | 945 | src_pt2 = GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
---|
[407] | 946 | |
---|
[408] | 947 | // get pointer on dst_pt2 |
---|
[635] | 948 | dst_pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( dst_pte1 ); |
---|
[587] | 949 | dst_pt2 = GET_PTR( ppm_ppn2base( dst_pt2_ppn ) ); |
---|
[407] | 950 | |
---|
[408] | 951 | // get attr and ppn from SRC_PT2 |
---|
[625] | 952 | src_pte2_attr = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2] ) ); |
---|
| 953 | src_pte2_ppn = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2 + 1] ) ); |
---|
[407] | 954 | |
---|
[408] | 955 | // do nothing if src_pte2 not MAPPED |
---|
[629] | 956 | if( (src_pte2_attr & TSAR_PTE_MAPPED) != 0 ) |
---|
[408] | 957 | { |
---|
| 958 | // set PPN in DST PTE2 |
---|
[625] | 959 | dst_pt2[2 * dst_ix2 + 1] = src_pte2_ppn; |
---|
[408] | 960 | |
---|
| 961 | // set attributes in DST PTE2 |
---|
[629] | 962 | if( cow && (src_pte2_attr & TSAR_PTE_WRITABLE) ) |
---|
[407] | 963 | { |
---|
[629] | 964 | dst_pt2[2 * dst_ix2] = (src_pte2_attr | TSAR_PTE_COW) & (~TSAR_PTE_WRITABLE); |
---|
[408] | 965 | } |
---|
| 966 | else |
---|
| 967 | { |
---|
[625] | 968 | dst_pt2[2 * dst_ix2] = src_pte2_attr; |
---|
[408] | 969 | } |
---|
[407] | 970 | |
---|
[408] | 971 | // return "successfully copied" |
---|
| 972 | *mapped = true; |
---|
| 973 | *ppn = src_pte2_ppn; |
---|
| 974 | |
---|
[587] | 975 | #if DEBUG_HAL_GPT_COPY |
---|
[432] | 976 | cycle = (uint32_t)hal_get_cycles; |
---|
[587] | 977 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[635] | 978 | printk("\n[%s] thread[%x,%x] exit / copy done for src_vpn %x / dst_vpn %x / cycle %d\n", |
---|
[625] | 979 | __FUNCTION__, this->process->pid, this->trdid, src_vpn, dst_vpn, cycle ); |
---|
[432] | 980 | #endif |
---|
[407] | 981 | |
---|
[408] | 982 | hal_fence(); |
---|
[407] | 983 | |
---|
[408] | 984 | return 0; |
---|
| 985 | } // end if PTE2 mapped |
---|
| 986 | } // end if PTE1 mapped |
---|
| 987 | |
---|
| 988 | // return "nothing done" |
---|
| 989 | *mapped = false; |
---|
| 990 | *ppn = 0; |
---|
[432] | 991 | |
---|
[587] | 992 | #if DEBUG_HAL_GPT_COPY |
---|
[432] | 993 | cycle = (uint32_t)hal_get_cycles; |
---|
[587] | 994 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[635] | 995 | printk("\n[%s] thread[%x,%x] exit / nothing done / cycle %d\n", |
---|
[625] | 996 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
---|
[432] | 997 | #endif |
---|
[408] | 998 | |
---|
[407] | 999 | hal_fence(); |
---|
| 1000 | |
---|
| 1001 | return 0; |
---|
| 1002 | |
---|
[408] | 1003 | } // end hal_gpt_pte_copy() |
---|
[407] | 1004 | |
---|
[408] | 1005 | ///////////////////////////////////////// |
---|
[432] | 1006 | void hal_gpt_set_cow( xptr_t gpt_xp, |
---|
| 1007 | vpn_t vpn_base, |
---|
| 1008 | vpn_t vpn_size ) |
---|
[408] | 1009 | { |
---|
| 1010 | cxy_t gpt_cxy; |
---|
| 1011 | gpt_t * gpt_ptr; |
---|
[407] | 1012 | |
---|
[635] | 1013 | uint32_t ix1; // current |
---|
| 1014 | uint32_t ix2; // current |
---|
[407] | 1015 | |
---|
[635] | 1016 | vpn_t vpn_min; |
---|
| 1017 | vpn_t vpn_max; // included |
---|
[407] | 1018 | |
---|
[635] | 1019 | uint32_t ix1_min; |
---|
| 1020 | uint32_t ix1_max; // included |
---|
| 1021 | |
---|
| 1022 | uint32_t ix2_min; |
---|
| 1023 | uint32_t ix2_max; // included |
---|
| 1024 | |
---|
[408] | 1025 | uint32_t * pt1; |
---|
| 1026 | uint32_t pte1; |
---|
[407] | 1027 | |
---|
[408] | 1028 | uint32_t * pt2; |
---|
| 1029 | ppn_t pt2_ppn; |
---|
[432] | 1030 | uint32_t attr; |
---|
[407] | 1031 | |
---|
[408] | 1032 | // get GPT cluster and local pointer |
---|
| 1033 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
[587] | 1034 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
[407] | 1035 | |
---|
[635] | 1036 | #if DEBUG_HAL_GPT_SET_COW |
---|
| 1037 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 1038 | thread_t * this = CURRENT_THREAD; |
---|
| 1039 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
| 1040 | printk("\n[%s] thread[%x,%x] enter / gpt[%x,%x] / vpn_base %x / vpn_size %x / cycle %d\n", |
---|
| 1041 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, gpt_ptr, vpn_base, vpn_size, cycle ); |
---|
| 1042 | #endif |
---|
| 1043 | |
---|
| 1044 | // get PT1 pointer |
---|
[408] | 1045 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[407] | 1046 | |
---|
[635] | 1047 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
| 1048 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
| 1049 | printk("\n[%s] thread[%x,%x] get pt1 = %x\n", |
---|
| 1050 | __FUNCTION__, this->process->pid, this->trdid, pt1 ); |
---|
| 1051 | #endif |
---|
| 1052 | |
---|
| 1053 | vpn_min = vpn_base; |
---|
| 1054 | vpn_max = vpn_base + vpn_size - 1; |
---|
| 1055 | |
---|
| 1056 | ix1_min = TSAR_MMU_IX1_FROM_VPN( vpn_base ); |
---|
| 1057 | ix1_max = TSAR_MMU_IX1_FROM_VPN( vpn_max ); |
---|
| 1058 | |
---|
| 1059 | for( ix1 = ix1_min ; ix1 <= ix1_max ; ix1++ ) |
---|
[408] | 1060 | { |
---|
[407] | 1061 | |
---|
[635] | 1062 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
| 1063 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
| 1064 | printk("\n[%s] thread[%x,%x] : &pt1[%x] = %x\n", |
---|
| 1065 | __FUNCTION__, this->process->pid, this->trdid, ix1, &pt1[ix1] ); |
---|
| 1066 | #endif |
---|
[408] | 1067 | // get PTE1 value |
---|
[570] | 1068 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[407] | 1069 | |
---|
[635] | 1070 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
| 1071 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
| 1072 | printk("\n[%s] thread[%x,%x] : pt1[%x] = %x\n", |
---|
| 1073 | __FUNCTION__, this->process->pid, this->trdid, ix1, pte1 ); |
---|
| 1074 | #endif |
---|
| 1075 | |
---|
[408] | 1076 | // only MAPPED & SMALL PTEs are modified |
---|
[629] | 1077 | if( (pte1 & TSAR_PTE_MAPPED) && (pte1 & TSAR_PTE_SMALL) ) |
---|
[408] | 1078 | { |
---|
[635] | 1079 | // get PT2 pointer |
---|
| 1080 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
[587] | 1081 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[407] | 1082 | |
---|
[635] | 1083 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
| 1084 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
| 1085 | printk("\n[%s] thread[%x,%x] : get pt2 = %x\n", |
---|
| 1086 | __FUNCTION__, this->process->pid, this->trdid, pt2 ); |
---|
| 1087 | #endif |
---|
| 1088 | ix2_min = (ix1 == ix1_min) ? TSAR_MMU_IX2_FROM_VPN(vpn_min) : 0; |
---|
| 1089 | ix2_max = (ix1 == ix1_max) ? TSAR_MMU_IX2_FROM_VPN(vpn_max) : 511; |
---|
| 1090 | |
---|
| 1091 | for( ix2 = ix2_min ; ix2 <= ix2_max ; ix2++ ) |
---|
[23] | 1092 | { |
---|
| 1093 | |
---|
[635] | 1094 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
| 1095 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
| 1096 | printk("\n[%s] thread[%x,%x] : &pte2[%x] = %x\n", |
---|
| 1097 | __FUNCTION__, this->process->pid, this->trdid, 2*ix2, &pt2[2*ix2] ); |
---|
| 1098 | #endif |
---|
| 1099 | // get current PTE2 attributes |
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| 1100 | attr = hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2] ) ); |
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| 1101 | |
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| 1102 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
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| 1103 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
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| 1104 | printk("\n[%s] thread[%x,%x] : pte2[%x] (attr) = %x\n", |
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| 1105 | __FUNCTION__, this->process->pid, this->trdid, 2*ix2, attr ); |
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| 1106 | #endif |
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| 1107 | // only MAPPED PTEs are modified |
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| 1108 | if( attr & TSAR_PTE_MAPPED ) |
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| 1109 | { |
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| 1110 | attr = (attr | TSAR_PTE_COW) & (~TSAR_PTE_WRITABLE); |
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| 1111 | hal_remote_s32( XPTR( gpt_cxy , &pt2[2*ix2] ) , attr ); |
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| 1112 | } |
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| 1113 | } // end loop on ix2 |
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| 1114 | } |
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| 1115 | } // end loop on ix1 |
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| 1116 | |
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| 1117 | #if DEBUG_HAL_GPT_SET_COW |
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| 1118 | cycle = (uint32_t)hal_get_cycles(); |
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| 1119 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
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| 1120 | printk("\n[%s] thread[%x,%x] exit / cycle %d\n", |
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| 1121 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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| 1122 | #endif |
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| 1123 | |
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[432] | 1124 | } // end hal_gpt_set_cow() |
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[315] | 1125 | |
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[408] | 1126 | ////////////////////////////////////////// |
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| 1127 | void hal_gpt_update_pte( xptr_t gpt_xp, |
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| 1128 | vpn_t vpn, |
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| 1129 | uint32_t attr, // generic GPT attributes |
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| 1130 | ppn_t ppn ) |
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| 1131 | { |
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| 1132 | uint32_t * pt1; // PT1 base addres |
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| 1133 | uint32_t pte1; // PT1 entry value |
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[23] | 1134 | |
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[408] | 1135 | ppn_t pt2_ppn; // PPN of PT2 |
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| 1136 | uint32_t * pt2; // PT2 base address |
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[635] | 1137 | xptr_t pte2_attr_xp; // exended pointer on pte2.attr |
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| 1138 | xptr_t pte2_ppn_xp; // exended pointer on pte2.ppn |
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[23] | 1139 | |
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[408] | 1140 | uint32_t ix1; // index in PT1 |
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| 1141 | uint32_t ix2; // index in PT2 |
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[23] | 1142 | |
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[632] | 1143 | // check MAPPED, SMALL, and not LOCKED in attr argument |
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| 1144 | assert( ((attr & GPT_MAPPED) != 0), "attribute MAPPED must be set in new attributes\n" ); |
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| 1145 | assert( ((attr & GPT_SMALL ) != 0), "attribute SMALL must be set in new attributes\n" ); |
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| 1146 | assert( ((attr & GPT_LOCKED) == 0), "attribute LOCKED must not be set in new attributes\n" ); |
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[23] | 1147 | |
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[408] | 1148 | // get cluster and local pointer on remote GPT |
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| 1149 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
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[587] | 1150 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
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[23] | 1151 | |
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[408] | 1152 | // compute indexes in PT1 and PT2 |
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| 1153 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 1154 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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[23] | 1155 | |
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[408] | 1156 | // get PT1 base |
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| 1157 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
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[23] | 1158 | |
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[408] | 1159 | // get PTE1 value |
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[570] | 1160 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
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[23] | 1161 | |
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[632] | 1162 | // check MAPPED and SMALL in target PTE1 |
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[635] | 1163 | assert( ((pte1 & TSAR_PTE_MAPPED) != 0), "attribute MAPPED must be set in target PTE1\n" ); |
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| 1164 | assert( ((pte1 & TSAR_PTE_SMALL ) != 0), "attribute SMALL must be set in target PTE1\n" ); |
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[408] | 1165 | |
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[635] | 1166 | // get PT2 base |
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| 1167 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
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[587] | 1168 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[408] | 1169 | |
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[635] | 1170 | // build extended pointers on PT2[ix2].attr and PT2[ix2].ppn |
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| 1171 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
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| 1172 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
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| 1173 | |
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[632] | 1174 | |
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| 1175 | // check MAPPED in target PTE2 |
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[635] | 1176 | assert( ((hal_remote_l32(pte2_attr_xp) & TSAR_PTE_MAPPED) != 0), |
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[632] | 1177 | "attribute MAPPED must be set in target PTE2\n" ); |
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| 1178 | |
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[408] | 1179 | // set PTE2 in this order |
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[635] | 1180 | hal_remote_s32( pte2_ppn_xp , ppn ); |
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[408] | 1181 | hal_fence(); |
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[635] | 1182 | hal_remote_s32( pte2_attr_xp , gpt2tsar( attr ) ); |
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[408] | 1183 | hal_fence(); |
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| 1184 | |
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| 1185 | } // end hal_gpt_update_pte() |
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| 1186 | |
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[629] | 1187 | |
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| 1188 | |
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| 1189 | |
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| 1190 | |
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