[1] | 1 | /* |
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| 2 | * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 |
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| 3 | * |
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[635] | 4 | * Author Alain Greiner (2016,2017,2018,2019) |
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[1] | 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH. |
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| 9 | * |
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| 10 | * ALMOS-MKH.is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH.is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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[457] | 24 | #include <hal_kernel_types.h> |
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[1] | 25 | #include <hal_gpt.h> |
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[647] | 26 | #include <hal_vmm.h> |
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[1] | 27 | #include <hal_special.h> |
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[640] | 28 | #include <hal_irqmask.h> |
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[1] | 29 | #include <printk.h> |
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| 30 | #include <bits.h> |
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| 31 | #include <process.h> |
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| 32 | #include <kmem.h> |
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| 33 | #include <thread.h> |
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| 34 | #include <cluster.h> |
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| 35 | #include <ppm.h> |
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| 36 | #include <page.h> |
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| 37 | |
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| 38 | //////////////////////////////////////////////////////////////////////////////////////// |
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[401] | 39 | // This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification) |
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[1] | 40 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 41 | |
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[629] | 42 | #define TSAR_PTE_MAPPED 0x80000000 |
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| 43 | #define TSAR_PTE_SMALL 0x40000000 |
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| 44 | #define TSAR_PTE_LOCAL 0x20000000 |
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| 45 | #define TSAR_PTE_REMOTE 0x10000000 |
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| 46 | #define TSAR_PTE_CACHABLE 0x08000000 |
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| 47 | #define TSAR_PTE_WRITABLE 0x04000000 |
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| 48 | #define TSAR_PTE_EXECUTABLE 0x02000000 |
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| 49 | #define TSAR_PTE_USER 0x01000000 |
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| 50 | #define TSAR_PTE_GLOBAL 0x00800000 |
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| 51 | #define TSAR_PTE_DIRTY 0x00400000 |
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[1] | 52 | |
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[629] | 53 | #define TSAR_PTE_COW 0x00000001 // only for small pages |
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| 54 | #define TSAR_PTE_SWAP 0x00000004 // only for small pages |
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| 55 | #define TSAR_PTE_LOCKED 0x00000008 // only for small pages |
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[1] | 56 | |
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| 57 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 58 | // TSAR MMU related macros (from the TSAR MMU specification) |
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| 59 | // - IX1 on 11 bits |
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| 60 | // - IX2 on 9 bits |
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| 61 | // - PPN on 28 bits |
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| 62 | //////////////////////////////////////////////////////////////////////////////////////// |
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| 63 | |
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| 64 | #define TSAR_MMU_IX1_WIDTH 11 |
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| 65 | #define TSAR_MMU_IX2_WIDTH 9 |
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| 66 | #define TSAR_MMU_PPN_WIDTH 28 |
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| 67 | |
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[401] | 68 | #define TSAR_MMU_PTE1_ATTR_MASK 0xFFC00000 |
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| 69 | #define TSAR_MMU_PTE1_PPN_MASK 0x0007FFFF |
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| 70 | |
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[1] | 71 | #define TSAR_MMU_IX1_FROM_VPN( vpn ) ((vpn >> 9) & 0x7FF) |
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| 72 | #define TSAR_MMU_IX2_FROM_VPN( vpn ) (vpn & 0x1FF) |
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| 73 | |
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[635] | 74 | #define TSAR_MMU_PPN2_FROM_PTE1( pte1 ) (pte1 & 0x0FFFFFFF) |
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| 75 | #define TSAR_MMU_PPN1_FROM_PTE1( pte1 ) ((pte1 & 0x0007FFFF)<<9) |
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[1] | 76 | #define TSAR_MMU_ATTR_FROM_PTE1( pte1 ) (pte1 & 0xFFC00000) |
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| 77 | |
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| 78 | #define TSAR_MMU_PPN_FROM_PTE2( pte2 ) (pte2 & 0x0FFFFFFF) |
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| 79 | #define TSAR_MMU_ATTR_FROM_PTE2( pte2 ) (pte2 & 0xFFC000FF) |
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| 80 | |
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[401] | 81 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 82 | // This static function translates the GPT attributes to the TSAR attributes |
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| 83 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 84 | static inline uint32_t gpt2tsar( uint32_t gpt_attr ) |
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| 85 | { |
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| 86 | uint32_t tsar_attr = 0; |
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| 87 | |
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[629] | 88 | if( gpt_attr & GPT_MAPPED ) tsar_attr |= TSAR_PTE_MAPPED; |
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| 89 | if( gpt_attr & GPT_SMALL ) tsar_attr |= TSAR_PTE_SMALL; |
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| 90 | if( gpt_attr & GPT_WRITABLE ) tsar_attr |= TSAR_PTE_WRITABLE; |
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| 91 | if( gpt_attr & GPT_EXECUTABLE ) tsar_attr |= TSAR_PTE_EXECUTABLE; |
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| 92 | if( gpt_attr & GPT_CACHABLE ) tsar_attr |= TSAR_PTE_CACHABLE; |
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| 93 | if( gpt_attr & GPT_USER ) tsar_attr |= TSAR_PTE_USER; |
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| 94 | if( gpt_attr & GPT_DIRTY ) tsar_attr |= TSAR_PTE_DIRTY; |
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| 95 | if( gpt_attr & GPT_ACCESSED ) tsar_attr |= TSAR_PTE_LOCAL; |
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| 96 | if( gpt_attr & GPT_GLOBAL ) tsar_attr |= TSAR_PTE_GLOBAL; |
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| 97 | if( gpt_attr & GPT_COW ) tsar_attr |= TSAR_PTE_COW; |
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| 98 | if( gpt_attr & GPT_SWAP ) tsar_attr |= TSAR_PTE_SWAP; |
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| 99 | if( gpt_attr & GPT_LOCKED ) tsar_attr |= TSAR_PTE_LOCKED; |
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[401] | 100 | |
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| 101 | return tsar_attr; |
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| 102 | } |
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| 103 | |
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| 104 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 105 | // This static function translates the TSAR attributes to the GPT attributes |
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| 106 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 107 | static inline uint32_t tsar2gpt( uint32_t tsar_attr ) |
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| 108 | { |
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| 109 | uint32_t gpt_attr = 0; |
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| 110 | |
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[629] | 111 | if( tsar_attr & TSAR_PTE_MAPPED ) gpt_attr |= GPT_MAPPED; |
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| 112 | if( tsar_attr & TSAR_PTE_MAPPED ) gpt_attr |= GPT_READABLE; |
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| 113 | if( tsar_attr & TSAR_PTE_SMALL ) gpt_attr |= GPT_SMALL; |
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| 114 | if( tsar_attr & TSAR_PTE_WRITABLE ) gpt_attr |= GPT_WRITABLE; |
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| 115 | if( tsar_attr & TSAR_PTE_EXECUTABLE ) gpt_attr |= GPT_EXECUTABLE; |
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| 116 | if( tsar_attr & TSAR_PTE_CACHABLE ) gpt_attr |= GPT_CACHABLE; |
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| 117 | if( tsar_attr & TSAR_PTE_USER ) gpt_attr |= GPT_USER; |
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| 118 | if( tsar_attr & TSAR_PTE_DIRTY ) gpt_attr |= GPT_DIRTY; |
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| 119 | if( tsar_attr & TSAR_PTE_LOCAL ) gpt_attr |= GPT_ACCESSED; |
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| 120 | if( tsar_attr & TSAR_PTE_REMOTE ) gpt_attr |= GPT_ACCESSED; |
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| 121 | if( tsar_attr & TSAR_PTE_GLOBAL ) gpt_attr |= GPT_GLOBAL; |
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| 122 | if( tsar_attr & TSAR_PTE_COW ) gpt_attr |= GPT_COW; |
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| 123 | if( tsar_attr & TSAR_PTE_SWAP ) gpt_attr |= GPT_SWAP; |
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| 124 | if( tsar_attr & TSAR_PTE_LOCKED ) gpt_attr |= GPT_LOCKED; |
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[401] | 125 | |
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| 126 | return gpt_attr; |
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| 127 | } |
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| 128 | |
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[632] | 129 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 130 | // The blocking hal_gpt_lock_pte() function implements a busy-waiting policy to get |
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| 131 | // exclusive access to a specific GPT entry. |
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| 132 | // - when non zero, the following variable defines the max number of iterations |
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| 133 | // in the busy waiting loop. |
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| 134 | // - when zero, the watchdog mechanism is deactivated. |
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| 135 | /////////////////////////////////////////////////////////////////////////////////////// |
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| 136 | |
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[640] | 137 | #define GPT_LOCK_WATCHDOG 100000 |
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[632] | 138 | |
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[1] | 139 | ///////////////////////////////////// |
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| 140 | error_t hal_gpt_create( gpt_t * gpt ) |
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| 141 | { |
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[635] | 142 | void * base; |
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[1] | 143 | |
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[587] | 144 | thread_t * this = CURRENT_THREAD; |
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| 145 | |
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[443] | 146 | #if DEBUG_HAL_GPT_CREATE |
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[587] | 147 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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[443] | 148 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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[635] | 149 | printk("\n[%s] thread[%x,%x] enter / cycle %d\n", |
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[587] | 150 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[432] | 151 | #endif |
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[406] | 152 | |
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[623] | 153 | // check page size |
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[635] | 154 | assert( (CONFIG_PPM_PAGE_SIZE == 4096) , "the TSAR page size must be 4 Kbytes\n" ); |
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[1] | 155 | |
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| 156 | // allocates 2 physical pages for PT1 |
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| 157 | kmem_req_t req; |
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[635] | 158 | req.type = KMEM_PPM; |
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| 159 | req.order = 1; // 2 small pages |
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[1] | 160 | req.flags = AF_KERNEL | AF_ZERO; |
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[635] | 161 | base = kmem_alloc( &req ); |
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[1] | 162 | |
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[635] | 163 | if( base == NULL ) |
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[1] | 164 | { |
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[587] | 165 | printk("\n[PANIC] in %s : no memory for PT1 / process %x / cluster %x\n", |
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| 166 | __FUNCTION__, this->process->pid, local_cxy ); |
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[1] | 167 | return ENOMEM; |
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[406] | 168 | } |
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[1] | 169 | |
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[640] | 170 | // initialze the GPT descriptor |
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| 171 | gpt->ptr = base; |
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| 172 | gpt->pte1_wait_events = 0; |
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| 173 | gpt->pte1_wait_iters = 0; |
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| 174 | gpt->pte2_wait_events = 0; |
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| 175 | gpt->pte2_wait_iters = 0; |
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[315] | 176 | |
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[443] | 177 | #if DEBUG_HAL_GPT_CREATE |
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[587] | 178 | cycle = (uint32_t)hal_get_cycles(); |
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[443] | 179 | if( DEBUG_HAL_GPT_CREATE < cycle ) |
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[635] | 180 | printk("\n[%s] thread[%x,%x] exit / pt1_base %x / pt1_ppn %x / cycle %d\n", |
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[640] | 181 | __FUNCTION__, this->process->pid, this->trdid, |
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| 182 | base, ppm_base2ppn( XPTR( local_cxy , base ) ), cycle ); |
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[432] | 183 | #endif |
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[406] | 184 | |
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[1] | 185 | return 0; |
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[406] | 186 | |
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[1] | 187 | } // end hal_gpt_create() |
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| 188 | |
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| 189 | /////////////////////////////////// |
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| 190 | void hal_gpt_destroy( gpt_t * gpt ) |
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| 191 | { |
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| 192 | uint32_t ix1; |
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| 193 | uint32_t ix2; |
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| 194 | uint32_t * pt1; |
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| 195 | uint32_t pte1; |
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| 196 | ppn_t pt2_ppn; |
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| 197 | uint32_t * pt2; |
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| 198 | uint32_t attr; |
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| 199 | kmem_req_t req; |
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| 200 | |
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[640] | 201 | thread_t * this = CURRENT_THREAD; |
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| 202 | |
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[443] | 203 | #if DEBUG_HAL_GPT_DESTROY |
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[587] | 204 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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[443] | 205 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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[635] | 206 | printk("\n[%s] thread[%x,%x] enter / cycle %d\n", |
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[587] | 207 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[443] | 208 | #endif |
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| 209 | |
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[1] | 210 | // get pointer on PT1 |
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| 211 | pt1 = (uint32_t *)gpt->ptr; |
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| 212 | |
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| 213 | // scan the PT1 |
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| 214 | for( ix1 = 0 ; ix1 < 2048 ; ix1++ ) |
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| 215 | { |
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| 216 | pte1 = pt1[ix1]; |
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[629] | 217 | |
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| 218 | if( (pte1 & TSAR_PTE_MAPPED) != 0 ) // PTE1 mapped |
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[1] | 219 | { |
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[629] | 220 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // BIG page |
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[1] | 221 | { |
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[640] | 222 | printk("\n[WARNING] %s : valid PTE1 / thread[%x,%x] / ix1 %x\n", |
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| 223 | __FUNCTION__, this->process->pid, this->trdid, ix1 ); |
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[1] | 224 | } |
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[629] | 225 | else // PT2 exist |
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[1] | 226 | { |
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[315] | 227 | // get local pointer on PT2 |
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[635] | 228 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
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| 229 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[1] | 230 | |
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[629] | 231 | // scan the PT2 |
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| 232 | for( ix2 = 0 ; ix2 < 512 ; ix2++ ) |
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[1] | 233 | { |
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[629] | 234 | attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] ); |
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| 235 | |
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| 236 | if( (attr & TSAR_PTE_MAPPED) != 0 ) // PTE2 mapped |
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[1] | 237 | { |
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[640] | 238 | printk("\n[WARNING] %s : valid PTE2 / thread[%x,%x] / ix1 %x / ix2 %x\n", |
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| 239 | __FUNCTION__, this->process->pid, this->trdid, ix1, ix2 ); |
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[1] | 240 | } |
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| 241 | } |
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| 242 | |
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[629] | 243 | // release the page allocated for the PT2 |
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[635] | 244 | req.type = KMEM_PPM; |
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| 245 | req.ptr = pt2; |
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[1] | 246 | kmem_free( &req ); |
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| 247 | } |
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| 248 | } |
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| 249 | } |
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| 250 | |
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| 251 | // release the PT1 |
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[635] | 252 | req.type = KMEM_PPM; |
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| 253 | req.ptr = pt1; |
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[1] | 254 | kmem_free( &req ); |
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| 255 | |
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[443] | 256 | #if DEBUG_HAL_GPT_DESTROY |
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[587] | 257 | cycle = (uint32_t)hal_get_cycles(); |
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[443] | 258 | if( DEBUG_HAL_GPT_DESTROY < cycle ) |
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[635] | 259 | printk("\n[%s] thread[%x,%x] exit / cycle %d\n", |
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[587] | 260 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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[443] | 261 | #endif |
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| 262 | |
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[1] | 263 | } // end hal_gpt_destroy() |
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| 264 | |
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[632] | 265 | //////////////////////////////////////////// |
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| 266 | error_t hal_gpt_lock_pte( xptr_t gpt_xp, |
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| 267 | vpn_t vpn, |
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| 268 | uint32_t * attr, |
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| 269 | ppn_t * ppn ) |
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[1] | 270 | { |
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[635] | 271 | uint32_t * pt1; // local pointer on PT1 base |
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| 272 | xptr_t pte1_xp; // extended pointer on PT1[x1] entry |
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| 273 | uint32_t pte1; // value of PT1[x1] entry |
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[629] | 274 | |
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[635] | 275 | kmem_req_t req; // kmem request fro PT2 allocation |
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[629] | 276 | |
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[635] | 277 | uint32_t * pt2; // local pointer on PT2 base |
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[632] | 278 | ppn_t pt2_ppn; // PPN of page containing PT2 |
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| 279 | xptr_t pte2_xp; // extended pointer on PT2[ix2].attr |
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| 280 | uint32_t pte2_attr; // PT2[ix2].attr current value |
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| 281 | uint32_t pte2_ppn; // PT2[ix2].ppn current value |
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[640] | 282 | bool_t success; // used for both PTE1 and PTE2 mapping |
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| 283 | uint32_t count; // watchdog |
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| 284 | uint32_t sr_save; // for critical section |
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[632] | 285 | |
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| 286 | // get cluster and local pointer on GPT |
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| 287 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
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| 288 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
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| 289 | |
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| 290 | #if DEBUG_HAL_GPT_LOCK_PTE |
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| 291 | thread_t * this = CURRENT_THREAD; |
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| 292 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
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[640] | 293 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
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[647] | 294 | if( (vpn == 0xc1fff) && (gpt_cxy == 0x1) ) |
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[635] | 295 | printk("\n[%s] thread[%x,%x] enters / vpn %x in cluster %x / cycle %d\n", |
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[632] | 296 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, cycle ); |
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| 297 | #endif |
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| 298 | |
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| 299 | // get indexes in PTI & PT2 from vpn |
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[635] | 300 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 301 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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[632] | 302 | |
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| 303 | // get local pointer on PT1 |
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[635] | 304 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
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[632] | 305 | |
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[635] | 306 | // build extended pointer on PTE1 == PT1[ix1] |
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| 307 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
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[632] | 308 | |
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| 309 | // get current PT1 entry value |
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[635] | 310 | pte1 = hal_remote_l32( pte1_xp ); |
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[629] | 311 | |
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[640] | 312 | // If PTE1 is unmapped, the calling thread try to map this PTE1. |
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| 313 | // To prevent multiple concurrent PT2 allocations, only the thread that |
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| 314 | // successfully locked the PTE1 allocates a new PT2 and updates the PTE1. |
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| 315 | // All other threads simply wait until the missing PTE1 is mapped. |
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[632] | 316 | |
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[640] | 317 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) |
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[629] | 318 | { |
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[640] | 319 | if( (pte1 & TSAR_PTE_LOCKED) == 0 ) |
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| 320 | { |
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| 321 | // try to atomically lock the PTE1 |
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| 322 | success = hal_remote_atomic_cas( pte1_xp, |
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| 323 | pte1, |
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| 324 | TSAR_PTE_LOCKED ); |
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| 325 | } |
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| 326 | else |
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| 327 | { |
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| 328 | success = false; |
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| 329 | } |
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| 330 | |
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| 331 | if( success ) // winner thread allocates one 4 Kbytes page for PT2 |
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| 332 | { |
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| 333 | // enter critical section |
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| 334 | hal_disable_irq( &sr_save ); |
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| 335 | |
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[635] | 336 | req.type = KMEM_PPM; |
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| 337 | req.order = 0; |
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| 338 | req.flags = AF_ZERO | AF_KERNEL; |
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| 339 | pt2 = kmem_remote_alloc( gpt_cxy , &req ); |
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[629] | 340 | |
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[635] | 341 | if( pt2 == NULL ) |
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[629] | 342 | { |
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[635] | 343 | printk("\n[ERROR] in %s : cannot allocate memory for PT2 in cluster %d\n", |
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| 344 | __FUNCTION__, gpt_cxy ); |
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[632] | 345 | return -1; |
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[629] | 346 | } |
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| 347 | |
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| 348 | // get the PT2 PPN |
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[635] | 349 | pt2_ppn = ppm_base2ppn( XPTR( gpt_cxy , pt2 ) ); |
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[629] | 350 | |
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[635] | 351 | // build PTE1 |
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| 352 | pte1 = TSAR_PTE_MAPPED | TSAR_PTE_SMALL | pt2_ppn; |
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[629] | 353 | |
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[640] | 354 | // set the PTE1 value in PT1 / this unlocks the PTE1 |
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[635] | 355 | hal_remote_s32( pte1_xp , pte1 ); |
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[629] | 356 | hal_fence(); |
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| 357 | |
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[640] | 358 | // exit critical section |
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| 359 | hal_restore_irq( sr_save ); |
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| 360 | |
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| 361 | #if DEBUG_HAL_GPT_LOCK_PTE |
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| 362 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
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[647] | 363 | if( (vpn == 0xc1fff) && (gpt_cxy == 0x1) ) |
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[640] | 364 | printk("\n[%s] PTE1 unmapped : winner thread[%x,%x] allocates a PT2 for vpn %x in cluster %x\n", |
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[632] | 365 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy ); |
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[629] | 366 | #endif |
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[632] | 367 | |
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[640] | 368 | } |
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| 369 | else // other threads wait until PTE1 mapped by the winner |
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| 370 | { |
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[632] | 371 | |
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[640] | 372 | #if DEBUG_HAL_GPT_LOCK_PTE |
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| 373 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
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[647] | 374 | if( (vpn == 0xc1fff) && (gpt_cxy == 0x1) ) |
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[640] | 375 | printk("\n[%s] PTE1 unmapped : loser thread[%x,%x] wait PTE1 for vpn %x in cluster %x\n", |
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| 376 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy ); |
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| 377 | #endif |
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[629] | 378 | |
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[640] | 379 | count = 0; |
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| 380 | do |
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| 381 | { |
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| 382 | // get current pte1 value |
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| 383 | pte1 = hal_remote_l32( pte1_xp ); |
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| 384 | |
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| 385 | // check iterations number |
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| 386 | if( count > GPT_LOCK_WATCHDOG ) |
---|
| 387 | { |
---|
| 388 | thread_t * this = CURRENT_THREAD; |
---|
| 389 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 390 | printk("\n[PANIC] in %s for PTE1 after %d iterations\n" |
---|
| 391 | " thread[%x,%x] / vpn %x / cluster %x / pte1 %x / cycle %d\n", |
---|
| 392 | __FUNCTION__, count, this->process->pid, this->trdid, |
---|
| 393 | vpn, gpt_cxy, pte1, cycle ); |
---|
| 394 | |
---|
| 395 | xptr_t process_xp = cluster_get_process_from_pid_in_cxy( gpt_cxy, |
---|
| 396 | this->process->pid ); |
---|
| 397 | hal_vmm_display( process_xp , true ); |
---|
| 398 | |
---|
| 399 | hal_core_sleep(); |
---|
| 400 | } |
---|
| 401 | |
---|
| 402 | // increment watchdog |
---|
| 403 | count++; |
---|
| 404 | } |
---|
| 405 | while( (pte1 & TSAR_PTE_MAPPED) == 0 ); |
---|
| 406 | |
---|
| 407 | #if CONFIG_INSTRUMENTATION_GPT |
---|
| 408 | hal_remote_atomic_add( XPTR( gpt_cxy , &gpt_ptr->pte1_wait_events ) , 1 ); |
---|
| 409 | hal_remote_atomic_add( XPTR( gpt_cxy , &gpt_ptr->pte1_wait_iters ) , count ); |
---|
[629] | 410 | #endif |
---|
| 411 | |
---|
| 412 | |
---|
[640] | 413 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
| 414 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
[647] | 415 | if( (vpn == 0xc1fff) && (gpt_cxy == 0x1) ) |
---|
[640] | 416 | printk("\n[%s] PTE1 unmapped : loser thread[%x,%x] get PTE1 for vpn %x in cluster %x\n", |
---|
| 417 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy ); |
---|
| 418 | #endif |
---|
| 419 | } |
---|
| 420 | } // end if pte1 unmapped |
---|
[629] | 421 | |
---|
[640] | 422 | // This code is executed by all calling threads |
---|
| 423 | |
---|
| 424 | // check PTE1 : only small and mapped pages can be locked |
---|
| 425 | assert( (pte1 & (TSAR_PTE_SMALL | TSAR_PTE_MAPPED)) , "cannot lock a big or unmapped page\n"); |
---|
| 426 | |
---|
| 427 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
| 428 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
[647] | 429 | if( (vpn == 0xc1fff) && (gpt_cxy == 0x1) ) |
---|
[635] | 430 | printk("\n[%s] thread[%x,%x] get pte1 %x for vpn %x in cluster %x\n", |
---|
| 431 | __FUNCTION__, this->process->pid, this->trdid, pte1, vpn, gpt_cxy ); |
---|
[632] | 432 | #endif |
---|
[629] | 433 | |
---|
[635] | 434 | // get pointer on PT2 base |
---|
| 435 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
| 436 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[629] | 437 | |
---|
[632] | 438 | // build extended pointers on PT2[ix2].attr |
---|
[635] | 439 | pte2_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
[629] | 440 | |
---|
[640] | 441 | // initialize external loop watchdog |
---|
| 442 | count = 0; |
---|
| 443 | |
---|
| 444 | // in this busy waiting loop, each thread try to atomically |
---|
| 445 | // lock the PTE2, after checking that the PTE2 is not locked |
---|
| 446 | |
---|
[632] | 447 | do |
---|
[629] | 448 | { |
---|
[640] | 449 | // get current value of pte2_attr |
---|
| 450 | pte2_attr = hal_remote_l32( pte2_xp ); |
---|
[629] | 451 | |
---|
[640] | 452 | // check loop watchdog |
---|
| 453 | if( count > GPT_LOCK_WATCHDOG ) |
---|
[633] | 454 | { |
---|
[640] | 455 | thread_t * this = CURRENT_THREAD; |
---|
| 456 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 457 | printk("\n[PANIC] in %s for PTE2 after %d iterations\n" |
---|
| 458 | " thread[%x,%x] / vpn %x / cluster %x / pte2_attr %x / cycle %d\n", |
---|
| 459 | __FUNCTION__, count, this->process->pid, this->trdid, |
---|
| 460 | vpn, gpt_cxy, pte2_attr, cycle ); |
---|
[632] | 461 | |
---|
[640] | 462 | xptr_t process_xp = cluster_get_process_from_pid_in_cxy( gpt_cxy, |
---|
| 463 | this->process->pid ); |
---|
| 464 | hal_vmm_display( process_xp , true ); |
---|
| 465 | |
---|
| 466 | hal_core_sleep(); |
---|
[633] | 467 | } |
---|
[629] | 468 | |
---|
[640] | 469 | // increment loop watchdog |
---|
| 470 | count++; |
---|
| 471 | |
---|
| 472 | if( (pte2_attr & TSAR_PTE_LOCKED) == 0 ) |
---|
| 473 | { |
---|
| 474 | // try to atomically set the TSAR_PTE_LOCKED attribute |
---|
| 475 | success = hal_remote_atomic_cas( pte2_xp, |
---|
| 476 | pte2_attr, |
---|
| 477 | (pte2_attr | TSAR_PTE_LOCKED) ); |
---|
| 478 | } |
---|
| 479 | else |
---|
| 480 | { |
---|
| 481 | success = false; |
---|
| 482 | } |
---|
[633] | 483 | } |
---|
[640] | 484 | while( success == false ); |
---|
[629] | 485 | |
---|
[640] | 486 | #if CONFIG_INSTRUMENTATION_GPT |
---|
| 487 | hal_remote_atomic_add( XPTR( gpt_cxy , &gpt_ptr->pte2_wait_events ) , 1 ); |
---|
| 488 | hal_remote_atomic_add( XPTR( gpt_cxy , &gpt_ptr->pte2_wait_iters ) , count ); |
---|
| 489 | #endif |
---|
| 490 | |
---|
[629] | 491 | // get PTE2.ppn |
---|
[632] | 492 | pte2_ppn = hal_remote_l32( pte2_xp + 4 ); |
---|
[629] | 493 | |
---|
| 494 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
[632] | 495 | cycle = (uint32_t)hal_get_cycles(); |
---|
[640] | 496 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
[647] | 497 | if( (vpn == 0xc1fff) && (gpt_cxy == 0x1) ) |
---|
[640] | 498 | printk("\n[%s] thread[%x,%x] success / vpn %x in cluster %x / attr %x / ppn %x / cycle %d\n", |
---|
[632] | 499 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, pte2_attr, pte2_ppn, cycle ); |
---|
[629] | 500 | #endif |
---|
| 501 | |
---|
| 502 | // return PPN and GPT attributes |
---|
[632] | 503 | *ppn = pte2_ppn & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
[629] | 504 | *attr = tsar2gpt( pte2_attr ); |
---|
[633] | 505 | return 0; |
---|
[629] | 506 | |
---|
| 507 | } // end hal_gpt_lock_pte() |
---|
| 508 | |
---|
| 509 | //////////////////////////////////////// |
---|
| 510 | void hal_gpt_unlock_pte( xptr_t gpt_xp, |
---|
| 511 | vpn_t vpn ) |
---|
| 512 | { |
---|
[635] | 513 | uint32_t * pt1; // local pointer on PT1 base |
---|
| 514 | xptr_t pte1_xp; // extended pointer on PT1[ix1] |
---|
| 515 | uint32_t pte1; // value of PT1[ix1] entry |
---|
[629] | 516 | |
---|
[635] | 517 | uint32_t * pt2; // PT2 base address |
---|
[629] | 518 | ppn_t pt2_ppn; // PPN of page containing PT2 |
---|
[632] | 519 | xptr_t pte2_xp; // extended pointer on PT2[ix2].attr |
---|
| 520 | uint32_t pte2_attr; // PTE2 attribute |
---|
[629] | 521 | |
---|
| 522 | // get cluster and local pointer on GPT |
---|
| 523 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 524 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
| 525 | |
---|
| 526 | // compute indexes in P1 and PT2 |
---|
[635] | 527 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 528 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[629] | 529 | |
---|
| 530 | // get local pointer on PT1 |
---|
[635] | 531 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[629] | 532 | |
---|
[635] | 533 | // build extended pointer on PTE1 == PT1[ix1] |
---|
| 534 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
---|
[629] | 535 | |
---|
[635] | 536 | // get current pte1 value |
---|
| 537 | pte1 = hal_remote_l32( pte1_xp ); |
---|
[629] | 538 | |
---|
[640] | 539 | assert( ((pte1 & TSAR_PTE_MAPPED) != 0), |
---|
| 540 | "PTE1 for vpn %x in cluster %x is unmapped / pte1 = %x\n", vpn, gpt_cxy, pte1 ); |
---|
[629] | 541 | |
---|
[640] | 542 | assert( ((pte1 & TSAR_PTE_SMALL ) != 0), |
---|
| 543 | "PTE1 for vpn %x in cluster %x is not small / pte1 = %x\n", vpn, gpt_cxy, pte1 ); |
---|
| 544 | |
---|
[635] | 545 | // get pointer on PT2 base |
---|
| 546 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
| 547 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[629] | 548 | |
---|
| 549 | // build extended pointers on PT2[ix2].attr |
---|
[635] | 550 | pte2_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
[629] | 551 | |
---|
| 552 | // get PT2[ix2].attr |
---|
[632] | 553 | pte2_attr = hal_remote_l32( pte2_xp ); |
---|
[629] | 554 | |
---|
[640] | 555 | assert( ((pte2_attr & TSAR_PTE_LOCKED) != 0), |
---|
| 556 | "PTE2 for vpn %x in cluster %x is unlocked / pte2_attr = %x\n", vpn, gpt_cxy, pte2_attr ); |
---|
[629] | 557 | |
---|
[632] | 558 | // reset TSAR_PTE_LOCKED attribute |
---|
| 559 | hal_remote_s32( pte2_xp , pte2_attr & ~TSAR_PTE_LOCKED ); |
---|
| 560 | |
---|
[629] | 561 | #if DEBUG_HAL_GPT_LOCK_PTE |
---|
[640] | 562 | thread_t * this = CURRENT_THREAD; |
---|
| 563 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 564 | // if( DEBUG_HAL_GPT_LOCK_PTE < cycle ) |
---|
| 565 | if( (vpn == 0xc5fff) && (gpt_cxy == 0x1) ) |
---|
[635] | 566 | printk("\n[%s] thread[%x,%x] unlocks vpn %x in cluster %x / cycle %d\n", |
---|
[632] | 567 | __FUNCTION__, this->process->pid, this->trdid, vpn, gpt_cxy, cycle ); |
---|
[629] | 568 | #endif |
---|
[632] | 569 | |
---|
[629] | 570 | } // end hal_gpt_unlock_pte() |
---|
| 571 | |
---|
[632] | 572 | |
---|
[629] | 573 | /////////////////////////////////////// |
---|
| 574 | void hal_gpt_set_pte( xptr_t gpt_xp, |
---|
| 575 | vpn_t vpn, |
---|
| 576 | uint32_t attr, |
---|
| 577 | ppn_t ppn ) |
---|
| 578 | { |
---|
[587] | 579 | cxy_t gpt_cxy; // target GPT cluster |
---|
| 580 | gpt_t * gpt_ptr; // target GPT local pointer |
---|
[629] | 581 | |
---|
[635] | 582 | uint32_t * pt1; // local pointer on PT1 base |
---|
[587] | 583 | xptr_t pte1_xp; // extended pointer on PT1 entry |
---|
| 584 | uint32_t pte1; // PT1 entry value if PTE1 |
---|
[1] | 585 | |
---|
[635] | 586 | uint32_t * pt2; // local pointer on PT2 base |
---|
[401] | 587 | ppn_t pt2_ppn; // PPN of PT2 |
---|
[629] | 588 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
| 589 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
| 590 | uint32_t pte2_attr; // current value of PT2[ix2].attr |
---|
[1] | 591 | |
---|
[401] | 592 | uint32_t ix1; // index in PT1 |
---|
| 593 | uint32_t ix2; // index in PT2 |
---|
[1] | 594 | |
---|
[401] | 595 | uint32_t tsar_attr; // PTE attributes for TSAR MMU |
---|
[629] | 596 | uint32_t small; // requested PTE is for a small page |
---|
[401] | 597 | |
---|
[587] | 598 | // get cluster and local pointer on GPT |
---|
| 599 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 600 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
| 601 | |
---|
[1] | 602 | // compute indexes in PT1 and PT2 |
---|
| 603 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 604 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
| 605 | |
---|
[635] | 606 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 607 | thread_t * this = CURRENT_THREAD; |
---|
| 608 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 609 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
| 610 | printk("\n[%s] thread[%x,%x] enter gpt (%x,%x) / vpn %x / attr %x / ppn %x\n", |
---|
| 611 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, &gpt_ptr->ptr, vpn, attr, ppn ); |
---|
| 612 | #endif |
---|
[1] | 613 | |
---|
[635] | 614 | small = attr & GPT_SMALL; |
---|
| 615 | |
---|
| 616 | // get local pointer on PT1 |
---|
| 617 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
| 618 | |
---|
[432] | 619 | // compute tsar attributes from generic attributes |
---|
[401] | 620 | tsar_attr = gpt2tsar( attr ); |
---|
| 621 | |
---|
[587] | 622 | // build extended pointer on PTE1 = PT1[ix1] |
---|
[635] | 623 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
---|
[406] | 624 | |
---|
[587] | 625 | // get current pte1 value |
---|
| 626 | pte1 = hal_remote_l32( pte1_xp ); |
---|
[1] | 627 | |
---|
[629] | 628 | if( small == 0 ) ///////////////// map a big page in PT1 |
---|
[401] | 629 | { |
---|
[623] | 630 | |
---|
| 631 | // check PT1 entry not mapped |
---|
[629] | 632 | assert( (pte1 == 0) , "try to set a big page in an already mapped PTE1\n" ); |
---|
[623] | 633 | |
---|
| 634 | // check VPN aligned |
---|
| 635 | assert( (ix2 == 0) , "illegal vpn for a big page\n" ); |
---|
| 636 | |
---|
| 637 | // check PPN aligned |
---|
| 638 | assert( ((ppn & 0x1FF) == 0) , "illegal ppn for a big page\n" ); |
---|
| 639 | |
---|
[587] | 640 | // set the PTE1 value in PT1 |
---|
| 641 | pte1 = (tsar_attr & TSAR_MMU_PTE1_ATTR_MASK) | ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK); |
---|
| 642 | hal_remote_s32( pte1_xp , pte1 ); |
---|
[124] | 643 | hal_fence(); |
---|
[587] | 644 | |
---|
| 645 | #if DEBUG_HAL_GPT_SET_PTE |
---|
| 646 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[635] | 647 | printk("\n[%s] thread[%x,%x] map PTE1 / cxy %x / ix1 %x / pt1 %x / pte1 %x\n", |
---|
| 648 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1, pte1 ); |
---|
[587] | 649 | #endif |
---|
| 650 | |
---|
[1] | 651 | } |
---|
[629] | 652 | else ///////////////// map a small page in PT2 |
---|
[587] | 653 | { |
---|
[1] | 654 | |
---|
[629] | 655 | // PTE1 must be mapped because PTE2 must be locked |
---|
[640] | 656 | assert( (pte1 & TSAR_PTE_MAPPED), |
---|
| 657 | "PTE1 for vpn %x in cluster %x must be mapped / pte1 = %x\n", vpn, gpt_cxy, pte1 ); |
---|
[1] | 658 | |
---|
[635] | 659 | // get PT2 base |
---|
| 660 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
| 661 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[315] | 662 | |
---|
[629] | 663 | // build extended pointers on PT2[ix2].attr and PT2[ix2].ppn |
---|
[635] | 664 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
| 665 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
---|
[1] | 666 | |
---|
[629] | 667 | // get current value of PTE2.attr |
---|
| 668 | pte2_attr = hal_remote_l32( pte2_attr_xp ); |
---|
[587] | 669 | |
---|
[629] | 670 | // PTE2 must be locked |
---|
[640] | 671 | assert( (pte2_attr & TSAR_PTE_LOCKED), |
---|
| 672 | "PTE2 for vpn %x in cluster %x must be locked / pte2_attr = %x\n", vpn, gpt_cxy, pte2_attr ); |
---|
[629] | 673 | |
---|
[587] | 674 | // set PTE2 in PT2 (in this order) |
---|
[629] | 675 | hal_remote_s32( pte2_ppn_xp , ppn ); |
---|
[587] | 676 | hal_fence(); |
---|
[629] | 677 | hal_remote_s32( pte2_attr_xp , tsar_attr ); |
---|
[587] | 678 | hal_fence(); |
---|
[1] | 679 | |
---|
[587] | 680 | #if DEBUG_HAL_GPT_SET_PTE |
---|
[629] | 681 | thread_t * this = CURRENT_THREAD; |
---|
| 682 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
[587] | 683 | if( DEBUG_HAL_GPT_SET_PTE < cycle ) |
---|
[635] | 684 | printk("\n[%s] thread[%x,%x] map PTE2 / cxy %x / ix2 %x / pt2 %x / attr %x / ppn %x\n", |
---|
| 685 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix2, pt2, tsar_attr, ppn ); |
---|
[432] | 686 | #endif |
---|
| 687 | |
---|
[587] | 688 | } |
---|
[1] | 689 | } // end of hal_gpt_set_pte() |
---|
| 690 | |
---|
[629] | 691 | /////////////////////////////////////// |
---|
| 692 | void hal_gpt_reset_pte( xptr_t gpt_xp, |
---|
| 693 | vpn_t vpn ) |
---|
[1] | 694 | { |
---|
[629] | 695 | cxy_t gpt_cxy; // target GPT cluster |
---|
| 696 | gpt_t * gpt_ptr; // target GPT local pointer |
---|
[1] | 697 | |
---|
[629] | 698 | uint32_t ix1; // index in PT1 |
---|
| 699 | uint32_t ix2; // index in PT2 |
---|
[1] | 700 | |
---|
[635] | 701 | uint32_t * pt1; // PT1 base address |
---|
[629] | 702 | xptr_t pte1_xp; // extended pointer on PT1[ix1] |
---|
| 703 | uint32_t pte1; // PT1 entry value |
---|
[587] | 704 | |
---|
[635] | 705 | uint32_t * pt2; // PT2 base address |
---|
[629] | 706 | ppn_t pt2_ppn; // PPN of PT2 |
---|
| 707 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
| 708 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
[1] | 709 | |
---|
[629] | 710 | // get cluster and local pointer on GPT |
---|
| 711 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 712 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
[1] | 713 | |
---|
[629] | 714 | // get ix1 & ix2 indexes |
---|
| 715 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 716 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[1] | 717 | |
---|
[629] | 718 | // get local pointer on PT1 base |
---|
[635] | 719 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[1] | 720 | |
---|
[629] | 721 | // build extended pointer on PTE1 = PT1[ix1] |
---|
[635] | 722 | pte1_xp = XPTR( gpt_cxy , &pt1[ix1] ); |
---|
[1] | 723 | |
---|
[629] | 724 | // get current PTE1 value |
---|
| 725 | pte1 = hal_remote_l32( pte1_xp ); |
---|
[1] | 726 | |
---|
[629] | 727 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) // PTE1 unmapped => do nothing |
---|
[1] | 728 | { |
---|
| 729 | return; |
---|
| 730 | } |
---|
| 731 | |
---|
[629] | 732 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // it's a PTE1 => unmap it from PT1 |
---|
[1] | 733 | { |
---|
[629] | 734 | hal_remote_s32( pte1_xp , 0 ); |
---|
[124] | 735 | hal_fence(); |
---|
[1] | 736 | |
---|
[629] | 737 | #if DEBUG_HAL_GPT_RESET_PTE |
---|
| 738 | thread_t * this = CURRENT_THREAD; |
---|
| 739 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 740 | if( DEBUG_HAL_GPT_RESET_PTE < cycle ) |
---|
[635] | 741 | printk("\n[%s] thread[%x,%x] unmap PTE1 / cxy %x / vpn %x / ix1 %x\n", |
---|
[629] | 742 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, vpn, ix1 ); |
---|
| 743 | #endif |
---|
| 744 | |
---|
[1] | 745 | return; |
---|
| 746 | } |
---|
[629] | 747 | else // it's a PTE2 => unmap it from PT2 |
---|
[1] | 748 | { |
---|
[635] | 749 | // get PT2 base |
---|
| 750 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
| 751 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 752 | |
---|
[629] | 753 | // build extended pointer on PT2[ix2].attr and PT2[ix2].ppn |
---|
[635] | 754 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
| 755 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
---|
[629] | 756 | |
---|
| 757 | // unmap the PTE2 |
---|
| 758 | hal_remote_s32( pte2_attr_xp , 0 ); |
---|
[391] | 759 | hal_fence(); |
---|
[629] | 760 | hal_remote_s32( pte2_ppn_xp , 0 ); |
---|
| 761 | hal_fence(); |
---|
[1] | 762 | |
---|
[629] | 763 | #if DEBUG_HAL_GPT_RESET_PTE |
---|
| 764 | thread_t * this = CURRENT_THREAD; |
---|
| 765 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 766 | if( DEBUG_HAL_GPT_RESET_PTE < cycle ) |
---|
[635] | 767 | printk("\n[%s] thread[%x,%x] unmap PTE2 / cxy %x / vpn %x / ix2 %x\n", |
---|
[629] | 768 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, vpn, ix2 ); |
---|
| 769 | #endif |
---|
| 770 | |
---|
[1] | 771 | return; |
---|
| 772 | } |
---|
| 773 | } // end hal_gpt_reset_pte() |
---|
| 774 | |
---|
[629] | 775 | //////////////////////////////////////// |
---|
| 776 | void hal_gpt_get_pte( xptr_t gpt_xp, |
---|
| 777 | vpn_t vpn, |
---|
| 778 | uint32_t * attr, |
---|
| 779 | ppn_t * ppn ) |
---|
[624] | 780 | { |
---|
[629] | 781 | uint32_t * pt1; // local pointer on PT1 base |
---|
| 782 | uint32_t pte1; // PTE1 value |
---|
[624] | 783 | |
---|
[629] | 784 | uint32_t * pt2; // local pointer on PT2 base |
---|
| 785 | ppn_t pt2_ppn; // PPN of page containing the PT2 |
---|
| 786 | xptr_t pte2_attr_xp; // extended pointer on PT2[ix2].attr |
---|
| 787 | xptr_t pte2_ppn_xp; // extended pointer on PT2[ix2].ppn |
---|
| 788 | uint32_t pte2_attr; // current value of PT2[ix2].attr |
---|
| 789 | ppn_t pte2_ppn; // current value of PT2[ix2].ppn |
---|
[624] | 790 | |
---|
[629] | 791 | // get cluster and local pointer on GPT |
---|
| 792 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
---|
| 793 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
---|
[624] | 794 | |
---|
[629] | 795 | // compute indexes in PT1 and PT2 |
---|
| 796 | uint32_t ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
---|
| 797 | uint32_t ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
---|
[624] | 798 | |
---|
[629] | 799 | // get PT1 base |
---|
| 800 | pt1 = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
| 801 | |
---|
| 802 | // get pte1 |
---|
| 803 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[624] | 804 | |
---|
[629] | 805 | // check PTE1 mapped |
---|
| 806 | if( (pte1 & TSAR_PTE_MAPPED) == 0 ) // PTE1 unmapped |
---|
[1] | 807 | { |
---|
[629] | 808 | *attr = 0; |
---|
| 809 | *ppn = 0; |
---|
| 810 | return; |
---|
[1] | 811 | } |
---|
| 812 | |
---|
[629] | 813 | // access GPT |
---|
| 814 | if( (pte1 & TSAR_PTE_SMALL) == 0 ) // it's a PTE1 |
---|
| 815 | { |
---|
[635] | 816 | // get PPN & ATTR |
---|
[629] | 817 | *attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) ); |
---|
[635] | 818 | *ppn = TSAR_MMU_PPN1_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1)); |
---|
[1] | 819 | } |
---|
[629] | 820 | else // it's a PTE2 |
---|
[1] | 821 | { |
---|
[629] | 822 | // compute PT2 base address |
---|
[635] | 823 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
[629] | 824 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[1] | 825 | |
---|
[629] | 826 | // build extended pointer on PT2[ix2].attr and PT2[ix2].ppn |
---|
| 827 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
---|
| 828 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
---|
[1] | 829 | |
---|
[629] | 830 | // get current value of PTE2.attr & PTE2.ppn |
---|
| 831 | pte2_attr = hal_remote_l32( pte2_attr_xp ); |
---|
| 832 | pte2_ppn = hal_remote_l32( pte2_ppn_xp ); |
---|
[1] | 833 | |
---|
[629] | 834 | // return PPN & GPT attributes |
---|
| 835 | *ppn = pte2_ppn & ((1<<TSAR_MMU_PPN_WIDTH)-1); |
---|
| 836 | *attr = tsar2gpt( pte2_attr ); |
---|
[1] | 837 | } |
---|
[629] | 838 | } // end hal_gpt_get_pte() |
---|
[1] | 839 | |
---|
| 840 | |
---|
[408] | 841 | /////////////////////////////////////////// |
---|
| 842 | error_t hal_gpt_pte_copy( gpt_t * dst_gpt, |
---|
[625] | 843 | vpn_t dst_vpn, |
---|
[408] | 844 | xptr_t src_gpt_xp, |
---|
[625] | 845 | vpn_t src_vpn, |
---|
[408] | 846 | bool_t cow, |
---|
| 847 | ppn_t * ppn, |
---|
| 848 | bool_t * mapped ) |
---|
[23] | 849 | { |
---|
[625] | 850 | uint32_t src_ix1; // index in SRC PT1 |
---|
| 851 | uint32_t src_ix2; // index in SRC PT2 |
---|
[1] | 852 | |
---|
[625] | 853 | uint32_t dst_ix1; // index in DST PT1 |
---|
| 854 | uint32_t dst_ix2; // index in DST PT2 |
---|
| 855 | |
---|
[408] | 856 | cxy_t src_cxy; // SRC GPT cluster |
---|
| 857 | gpt_t * src_gpt; // SRC GPT local pointer |
---|
[1] | 858 | |
---|
[408] | 859 | uint32_t * src_pt1; // local pointer on SRC PT1 |
---|
| 860 | uint32_t * dst_pt1; // local pointer on DST PT1 |
---|
[635] | 861 | |
---|
[408] | 862 | uint32_t * src_pt2; // local pointer on SRC PT2 |
---|
| 863 | uint32_t * dst_pt2; // local pointer on DST PT2 |
---|
| 864 | |
---|
[587] | 865 | kmem_req_t req; // for PT2 allocation |
---|
[407] | 866 | |
---|
| 867 | uint32_t src_pte1; |
---|
| 868 | uint32_t dst_pte1; |
---|
| 869 | |
---|
[408] | 870 | uint32_t src_pte2_attr; |
---|
| 871 | uint32_t src_pte2_ppn; |
---|
[1] | 872 | |
---|
[23] | 873 | page_t * page; |
---|
[315] | 874 | xptr_t page_xp; |
---|
[1] | 875 | |
---|
[23] | 876 | ppn_t src_pt2_ppn; |
---|
| 877 | ppn_t dst_pt2_ppn; |
---|
[1] | 878 | |
---|
[587] | 879 | // get remote src_gpt cluster and local pointer |
---|
| 880 | src_cxy = GET_CXY( src_gpt_xp ); |
---|
| 881 | src_gpt = GET_PTR( src_gpt_xp ); |
---|
| 882 | |
---|
| 883 | #if DEBUG_HAL_GPT_COPY |
---|
| 884 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 885 | thread_t * this = CURRENT_THREAD; |
---|
| 886 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[635] | 887 | printk("\n[%s] thread[%x,%x] enter / src_cxy %x / dst_cxy %x / cycle %d\n", |
---|
[625] | 888 | __FUNCTION__, this->process->pid, this->trdid, src_cxy, local_cxy, cycle ); |
---|
[432] | 889 | #endif |
---|
[407] | 890 | |
---|
[408] | 891 | // get remote src_pt1 and local dst_pt1 |
---|
| 892 | src_pt1 = (uint32_t *)hal_remote_lpt( XPTR( src_cxy , &src_gpt->ptr ) ); |
---|
[23] | 893 | dst_pt1 = (uint32_t *)dst_gpt->ptr; |
---|
[1] | 894 | |
---|
[408] | 895 | // check src_pt1 and dst_pt1 existence |
---|
[492] | 896 | assert( (src_pt1 != NULL) , "src_pt1 does not exist\n"); |
---|
| 897 | assert( (dst_pt1 != NULL) , "dst_pt1 does not exist\n"); |
---|
[407] | 898 | |
---|
[625] | 899 | // compute SRC indexes |
---|
| 900 | src_ix1 = TSAR_MMU_IX1_FROM_VPN( src_vpn ); |
---|
| 901 | src_ix2 = TSAR_MMU_IX2_FROM_VPN( src_vpn ); |
---|
[407] | 902 | |
---|
[625] | 903 | // compute DST indexes |
---|
| 904 | dst_ix1 = TSAR_MMU_IX1_FROM_VPN( dst_vpn ); |
---|
| 905 | dst_ix2 = TSAR_MMU_IX2_FROM_VPN( dst_vpn ); |
---|
| 906 | |
---|
[408] | 907 | // get src_pte1 |
---|
[625] | 908 | src_pte1 = hal_remote_l32( XPTR( src_cxy , &src_pt1[src_ix1] ) ); |
---|
[407] | 909 | |
---|
[408] | 910 | // do nothing if src_pte1 not MAPPED or not SMALL |
---|
[629] | 911 | if( (src_pte1 & TSAR_PTE_MAPPED) && (src_pte1 & TSAR_PTE_SMALL) ) |
---|
[408] | 912 | { |
---|
| 913 | // get dst_pt1 entry |
---|
[625] | 914 | dst_pte1 = dst_pt1[dst_ix1]; |
---|
[407] | 915 | |
---|
[635] | 916 | // map dst_pte1 when this entry is not mapped |
---|
[629] | 917 | if( (dst_pte1 & TSAR_PTE_MAPPED) == 0 ) |
---|
[408] | 918 | { |
---|
| 919 | // allocate one physical page for a new PT2 |
---|
[635] | 920 | req.type = KMEM_PPM; |
---|
| 921 | req.order = 0; // 1 small page |
---|
[408] | 922 | req.flags = AF_KERNEL | AF_ZERO; |
---|
[635] | 923 | dst_pt2 = kmem_alloc( &req ); |
---|
[407] | 924 | |
---|
[635] | 925 | if( dst_pt2 == NULL ) |
---|
[408] | 926 | { |
---|
| 927 | printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ ); |
---|
| 928 | return -1; |
---|
| 929 | } |
---|
[407] | 930 | |
---|
[408] | 931 | // build extended pointer on page descriptor |
---|
| 932 | page_xp = XPTR( local_cxy , page ); |
---|
[407] | 933 | |
---|
[408] | 934 | // get PPN for this new PT2 |
---|
[635] | 935 | dst_pt2_ppn = ppm_base2ppn( XPTR( local_cxy , dst_pt2 ) ); |
---|
[407] | 936 | |
---|
[635] | 937 | // build new dst_pte1 |
---|
[629] | 938 | dst_pte1 = TSAR_PTE_MAPPED | TSAR_PTE_SMALL | dst_pt2_ppn; |
---|
[407] | 939 | |
---|
[408] | 940 | // register it in DST_GPT |
---|
[625] | 941 | dst_pt1[dst_ix1] = dst_pte1; |
---|
[408] | 942 | } |
---|
[407] | 943 | |
---|
[408] | 944 | // get pointer on src_pt2 |
---|
[635] | 945 | src_pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( src_pte1 ); |
---|
[587] | 946 | src_pt2 = GET_PTR( ppm_ppn2base( src_pt2_ppn ) ); |
---|
[407] | 947 | |
---|
[408] | 948 | // get pointer on dst_pt2 |
---|
[635] | 949 | dst_pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( dst_pte1 ); |
---|
[587] | 950 | dst_pt2 = GET_PTR( ppm_ppn2base( dst_pt2_ppn ) ); |
---|
[407] | 951 | |
---|
[408] | 952 | // get attr and ppn from SRC_PT2 |
---|
[625] | 953 | src_pte2_attr = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2] ) ); |
---|
| 954 | src_pte2_ppn = hal_remote_l32( XPTR( src_cxy , &src_pt2[2 * src_ix2 + 1] ) ); |
---|
[407] | 955 | |
---|
[408] | 956 | // do nothing if src_pte2 not MAPPED |
---|
[629] | 957 | if( (src_pte2_attr & TSAR_PTE_MAPPED) != 0 ) |
---|
[408] | 958 | { |
---|
| 959 | // set PPN in DST PTE2 |
---|
[625] | 960 | dst_pt2[2 * dst_ix2 + 1] = src_pte2_ppn; |
---|
[408] | 961 | |
---|
| 962 | // set attributes in DST PTE2 |
---|
[629] | 963 | if( cow && (src_pte2_attr & TSAR_PTE_WRITABLE) ) |
---|
[407] | 964 | { |
---|
[629] | 965 | dst_pt2[2 * dst_ix2] = (src_pte2_attr | TSAR_PTE_COW) & (~TSAR_PTE_WRITABLE); |
---|
[408] | 966 | } |
---|
| 967 | else |
---|
| 968 | { |
---|
[625] | 969 | dst_pt2[2 * dst_ix2] = src_pte2_attr; |
---|
[408] | 970 | } |
---|
[407] | 971 | |
---|
[408] | 972 | // return "successfully copied" |
---|
| 973 | *mapped = true; |
---|
| 974 | *ppn = src_pte2_ppn; |
---|
| 975 | |
---|
[587] | 976 | #if DEBUG_HAL_GPT_COPY |
---|
[432] | 977 | cycle = (uint32_t)hal_get_cycles; |
---|
[587] | 978 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[635] | 979 | printk("\n[%s] thread[%x,%x] exit / copy done for src_vpn %x / dst_vpn %x / cycle %d\n", |
---|
[625] | 980 | __FUNCTION__, this->process->pid, this->trdid, src_vpn, dst_vpn, cycle ); |
---|
[432] | 981 | #endif |
---|
[407] | 982 | |
---|
[408] | 983 | hal_fence(); |
---|
[407] | 984 | |
---|
[408] | 985 | return 0; |
---|
| 986 | } // end if PTE2 mapped |
---|
| 987 | } // end if PTE1 mapped |
---|
| 988 | |
---|
| 989 | // return "nothing done" |
---|
| 990 | *mapped = false; |
---|
| 991 | *ppn = 0; |
---|
[432] | 992 | |
---|
[587] | 993 | #if DEBUG_HAL_GPT_COPY |
---|
[432] | 994 | cycle = (uint32_t)hal_get_cycles; |
---|
[587] | 995 | if( DEBUG_HAL_GPT_COPY < cycle ) |
---|
[635] | 996 | printk("\n[%s] thread[%x,%x] exit / nothing done / cycle %d\n", |
---|
[625] | 997 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
---|
[432] | 998 | #endif |
---|
[408] | 999 | |
---|
[407] | 1000 | hal_fence(); |
---|
| 1001 | |
---|
| 1002 | return 0; |
---|
| 1003 | |
---|
[408] | 1004 | } // end hal_gpt_pte_copy() |
---|
[407] | 1005 | |
---|
[408] | 1006 | ///////////////////////////////////////// |
---|
[432] | 1007 | void hal_gpt_set_cow( xptr_t gpt_xp, |
---|
| 1008 | vpn_t vpn_base, |
---|
| 1009 | vpn_t vpn_size ) |
---|
[408] | 1010 | { |
---|
| 1011 | cxy_t gpt_cxy; |
---|
| 1012 | gpt_t * gpt_ptr; |
---|
[407] | 1013 | |
---|
[635] | 1014 | uint32_t ix1; // current |
---|
| 1015 | uint32_t ix2; // current |
---|
[407] | 1016 | |
---|
[635] | 1017 | vpn_t vpn_min; |
---|
| 1018 | vpn_t vpn_max; // included |
---|
[407] | 1019 | |
---|
[635] | 1020 | uint32_t ix1_min; |
---|
| 1021 | uint32_t ix1_max; // included |
---|
| 1022 | |
---|
| 1023 | uint32_t ix2_min; |
---|
| 1024 | uint32_t ix2_max; // included |
---|
| 1025 | |
---|
[408] | 1026 | uint32_t * pt1; |
---|
| 1027 | uint32_t pte1; |
---|
[407] | 1028 | |
---|
[408] | 1029 | uint32_t * pt2; |
---|
| 1030 | ppn_t pt2_ppn; |
---|
[432] | 1031 | uint32_t attr; |
---|
[407] | 1032 | |
---|
[408] | 1033 | // get GPT cluster and local pointer |
---|
| 1034 | gpt_cxy = GET_CXY( gpt_xp ); |
---|
[587] | 1035 | gpt_ptr = GET_PTR( gpt_xp ); |
---|
[407] | 1036 | |
---|
[635] | 1037 | #if DEBUG_HAL_GPT_SET_COW |
---|
| 1038 | uint32_t cycle = (uint32_t)hal_get_cycles(); |
---|
| 1039 | thread_t * this = CURRENT_THREAD; |
---|
| 1040 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
| 1041 | printk("\n[%s] thread[%x,%x] enter / gpt[%x,%x] / vpn_base %x / vpn_size %x / cycle %d\n", |
---|
| 1042 | __FUNCTION__, this->process->pid, this->trdid, gpt_cxy, gpt_ptr, vpn_base, vpn_size, cycle ); |
---|
| 1043 | #endif |
---|
| 1044 | |
---|
| 1045 | // get PT1 pointer |
---|
[408] | 1046 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
---|
[407] | 1047 | |
---|
[635] | 1048 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
| 1049 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
| 1050 | printk("\n[%s] thread[%x,%x] get pt1 = %x\n", |
---|
| 1051 | __FUNCTION__, this->process->pid, this->trdid, pt1 ); |
---|
| 1052 | #endif |
---|
| 1053 | |
---|
| 1054 | vpn_min = vpn_base; |
---|
| 1055 | vpn_max = vpn_base + vpn_size - 1; |
---|
| 1056 | |
---|
| 1057 | ix1_min = TSAR_MMU_IX1_FROM_VPN( vpn_base ); |
---|
| 1058 | ix1_max = TSAR_MMU_IX1_FROM_VPN( vpn_max ); |
---|
| 1059 | |
---|
| 1060 | for( ix1 = ix1_min ; ix1 <= ix1_max ; ix1++ ) |
---|
[408] | 1061 | { |
---|
[407] | 1062 | |
---|
[635] | 1063 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
| 1064 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
| 1065 | printk("\n[%s] thread[%x,%x] : &pt1[%x] = %x\n", |
---|
| 1066 | __FUNCTION__, this->process->pid, this->trdid, ix1, &pt1[ix1] ); |
---|
| 1067 | #endif |
---|
[408] | 1068 | // get PTE1 value |
---|
[570] | 1069 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
---|
[407] | 1070 | |
---|
[635] | 1071 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
| 1072 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
| 1073 | printk("\n[%s] thread[%x,%x] : pt1[%x] = %x\n", |
---|
| 1074 | __FUNCTION__, this->process->pid, this->trdid, ix1, pte1 ); |
---|
| 1075 | #endif |
---|
| 1076 | |
---|
[408] | 1077 | // only MAPPED & SMALL PTEs are modified |
---|
[629] | 1078 | if( (pte1 & TSAR_PTE_MAPPED) && (pte1 & TSAR_PTE_SMALL) ) |
---|
[408] | 1079 | { |
---|
[635] | 1080 | // get PT2 pointer |
---|
| 1081 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
---|
[587] | 1082 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
---|
[407] | 1083 | |
---|
[635] | 1084 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
| 1085 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
---|
| 1086 | printk("\n[%s] thread[%x,%x] : get pt2 = %x\n", |
---|
| 1087 | __FUNCTION__, this->process->pid, this->trdid, pt2 ); |
---|
| 1088 | #endif |
---|
| 1089 | ix2_min = (ix1 == ix1_min) ? TSAR_MMU_IX2_FROM_VPN(vpn_min) : 0; |
---|
| 1090 | ix2_max = (ix1 == ix1_max) ? TSAR_MMU_IX2_FROM_VPN(vpn_max) : 511; |
---|
| 1091 | |
---|
| 1092 | for( ix2 = ix2_min ; ix2 <= ix2_max ; ix2++ ) |
---|
[23] | 1093 | { |
---|
| 1094 | |
---|
[635] | 1095 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
---|
| 1096 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
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| 1097 | printk("\n[%s] thread[%x,%x] : &pte2[%x] = %x\n", |
---|
| 1098 | __FUNCTION__, this->process->pid, this->trdid, 2*ix2, &pt2[2*ix2] ); |
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| 1099 | #endif |
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| 1100 | // get current PTE2 attributes |
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| 1101 | attr = hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2] ) ); |
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| 1102 | |
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| 1103 | #if (DEBUG_HAL_GPT_SET_COW & 1) |
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| 1104 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
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| 1105 | printk("\n[%s] thread[%x,%x] : pte2[%x] (attr) = %x\n", |
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| 1106 | __FUNCTION__, this->process->pid, this->trdid, 2*ix2, attr ); |
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| 1107 | #endif |
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| 1108 | // only MAPPED PTEs are modified |
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| 1109 | if( attr & TSAR_PTE_MAPPED ) |
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| 1110 | { |
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| 1111 | attr = (attr | TSAR_PTE_COW) & (~TSAR_PTE_WRITABLE); |
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| 1112 | hal_remote_s32( XPTR( gpt_cxy , &pt2[2*ix2] ) , attr ); |
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| 1113 | } |
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| 1114 | } // end loop on ix2 |
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| 1115 | } |
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| 1116 | } // end loop on ix1 |
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| 1117 | |
---|
| 1118 | #if DEBUG_HAL_GPT_SET_COW |
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| 1119 | cycle = (uint32_t)hal_get_cycles(); |
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| 1120 | if(DEBUG_HAL_GPT_SET_COW < cycle ) |
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| 1121 | printk("\n[%s] thread[%x,%x] exit / cycle %d\n", |
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| 1122 | __FUNCTION__, this->process->pid, this->trdid, cycle ); |
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| 1123 | #endif |
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| 1124 | |
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[432] | 1125 | } // end hal_gpt_set_cow() |
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[315] | 1126 | |
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[408] | 1127 | ////////////////////////////////////////// |
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| 1128 | void hal_gpt_update_pte( xptr_t gpt_xp, |
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| 1129 | vpn_t vpn, |
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| 1130 | uint32_t attr, // generic GPT attributes |
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| 1131 | ppn_t ppn ) |
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| 1132 | { |
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| 1133 | uint32_t * pt1; // PT1 base addres |
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| 1134 | uint32_t pte1; // PT1 entry value |
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[23] | 1135 | |
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[408] | 1136 | ppn_t pt2_ppn; // PPN of PT2 |
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| 1137 | uint32_t * pt2; // PT2 base address |
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[635] | 1138 | xptr_t pte2_attr_xp; // exended pointer on pte2.attr |
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| 1139 | xptr_t pte2_ppn_xp; // exended pointer on pte2.ppn |
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[23] | 1140 | |
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[408] | 1141 | uint32_t ix1; // index in PT1 |
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| 1142 | uint32_t ix2; // index in PT2 |
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[23] | 1143 | |
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[632] | 1144 | // check MAPPED, SMALL, and not LOCKED in attr argument |
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| 1145 | assert( ((attr & GPT_MAPPED) != 0), "attribute MAPPED must be set in new attributes\n" ); |
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| 1146 | assert( ((attr & GPT_SMALL ) != 0), "attribute SMALL must be set in new attributes\n" ); |
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| 1147 | assert( ((attr & GPT_LOCKED) == 0), "attribute LOCKED must not be set in new attributes\n" ); |
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[23] | 1148 | |
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[408] | 1149 | // get cluster and local pointer on remote GPT |
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| 1150 | cxy_t gpt_cxy = GET_CXY( gpt_xp ); |
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[587] | 1151 | gpt_t * gpt_ptr = GET_PTR( gpt_xp ); |
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[23] | 1152 | |
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[408] | 1153 | // compute indexes in PT1 and PT2 |
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| 1154 | ix1 = TSAR_MMU_IX1_FROM_VPN( vpn ); |
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| 1155 | ix2 = TSAR_MMU_IX2_FROM_VPN( vpn ); |
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[23] | 1156 | |
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[408] | 1157 | // get PT1 base |
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| 1158 | pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) ); |
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[23] | 1159 | |
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[408] | 1160 | // get PTE1 value |
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[570] | 1161 | pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) ); |
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[23] | 1162 | |
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[632] | 1163 | // check MAPPED and SMALL in target PTE1 |
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[635] | 1164 | assert( ((pte1 & TSAR_PTE_MAPPED) != 0), "attribute MAPPED must be set in target PTE1\n" ); |
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| 1165 | assert( ((pte1 & TSAR_PTE_SMALL ) != 0), "attribute SMALL must be set in target PTE1\n" ); |
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[408] | 1166 | |
---|
[635] | 1167 | // get PT2 base |
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| 1168 | pt2_ppn = TSAR_MMU_PPN2_FROM_PTE1( pte1 ); |
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[587] | 1169 | pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) ); |
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[408] | 1170 | |
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[635] | 1171 | // build extended pointers on PT2[ix2].attr and PT2[ix2].ppn |
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| 1172 | pte2_attr_xp = XPTR( gpt_cxy , &pt2[2 * ix2] ); |
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| 1173 | pte2_ppn_xp = XPTR( gpt_cxy , &pt2[2 * ix2 + 1] ); |
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| 1174 | |
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[632] | 1175 | |
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| 1176 | // check MAPPED in target PTE2 |
---|
[635] | 1177 | assert( ((hal_remote_l32(pte2_attr_xp) & TSAR_PTE_MAPPED) != 0), |
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[632] | 1178 | "attribute MAPPED must be set in target PTE2\n" ); |
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| 1179 | |
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[408] | 1180 | // set PTE2 in this order |
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[635] | 1181 | hal_remote_s32( pte2_ppn_xp , ppn ); |
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[408] | 1182 | hal_fence(); |
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[635] | 1183 | hal_remote_s32( pte2_attr_xp , gpt2tsar( attr ) ); |
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[408] | 1184 | hal_fence(); |
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| 1185 | |
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| 1186 | } // end hal_gpt_update_pte() |
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| 1187 | |
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[629] | 1188 | |
---|