[1] | 1 | /* |
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| 2 | * hal_special.c - implementation of Generic Special Register Access API for TSAR-MIPS32 |
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| 3 | * |
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[101] | 4 | * Author Alain Greiner (2016,2017) |
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[1] | 5 | * |
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| 6 | * Copyright (c) UPMC Sorbonne Universites |
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| 7 | * |
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| 8 | * This file is part of ALMOS-MKH.. |
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| 9 | * |
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| 10 | * ALMOS-MKH. is free software; you can redistribute it and/or modify it |
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| 11 | * under the terms of the GNU General Public License as published by |
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| 12 | * the Free Software Foundation; version 2.0 of the License. |
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| 13 | * |
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| 14 | * ALMOS-MKH. is distributed in the hope that it will be useful, but |
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| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 17 | * General Public License for more details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU General Public License |
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| 20 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
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| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 22 | */ |
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| 23 | |
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| 24 | |
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| 25 | #include <hal_types.h> |
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| 26 | #include <hal_special.h> |
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[101] | 27 | #include <core.h> |
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| 28 | #include <thread.h> |
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[1] | 29 | |
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| 30 | /**** Forward declarations ****/ |
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| 31 | |
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| 32 | struct thread_s; |
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| 33 | |
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[279] | 34 | ///////////////////////////////// |
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| 35 | void hal_set_ebase( reg_t base ) |
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| 36 | { |
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| 37 | asm volatile ("mtc0 %0, $15, 1" : : "r" (base)); |
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| 38 | } |
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[101] | 39 | |
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[121] | 40 | ////////////////////////// |
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| 41 | inline gid_t hal_get_gid() |
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[1] | 42 | { |
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| 43 | uint32_t proc_id; |
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| 44 | |
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| 45 | asm volatile ("mfc0 %0, $15, 1" : "=&r" (proc_id)); |
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| 46 | |
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[16] | 47 | return (proc_id & 0x3FF); // 4/4/2 format for TSAR |
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[1] | 48 | } |
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| 49 | |
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[296] | 50 | ///////////////////////////// |
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| 51 | inline reg_t hal_time_stamp() |
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[121] | 52 | { |
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[296] | 53 | reg_t count; |
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[121] | 54 | |
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[279] | 55 | asm volatile ("mfc0 %0, $9" : "=&r" (count)); |
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[121] | 56 | |
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| 57 | return count; |
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| 58 | } |
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| 59 | |
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[1] | 60 | ///////////////////////// |
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[279] | 61 | inline reg_t hal_get_sr() |
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| 62 | { |
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[296] | 63 | reg_t sr; |
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[279] | 64 | |
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| 65 | asm volatile ("mfc0 %0, $12" : "=&r" (sr)); |
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| 66 | |
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| 67 | return sr; |
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| 68 | } |
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| 69 | |
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| 70 | ///////////////////////// |
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[95] | 71 | uint64_t hal_get_cycles() |
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[1] | 72 | { |
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[95] | 73 | uint64_t cycles; // absolute time to be returned |
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| 74 | uint32_t last_count; // last registered cycles count |
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| 75 | uint32_t current_count; // current cycles count |
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| 76 | uint32_t elapsed; |
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| 77 | |
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| 78 | core_t * core = CURRENT_THREAD->core; |
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| 79 | |
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| 80 | // get last registered time stamp |
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| 81 | last_count = core->time_stamp; |
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| 82 | |
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| 83 | // get current time stamp from hardware register |
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[121] | 84 | current_count = hal_time_stamp(); |
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[95] | 85 | |
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| 86 | // compute number of elapsed cycles, taking into account 32 bits register wrap |
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| 87 | if(current_count < last_count) elapsed = (0xFFFFFFFF - last_count) + current_count; |
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| 88 | else elapsed = current_count - last_count; |
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| 89 | |
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| 90 | // compute absolute time |
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| 91 | cycles = core->cycles + elapsed; |
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| 92 | |
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| 93 | // update core time |
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| 94 | core->time_stamp = current_count; |
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| 95 | core->cycles = cycles; |
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| 96 | |
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[124] | 97 | hal_fence(); |
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[95] | 98 | |
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[1] | 99 | return cycles; |
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| 100 | } |
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| 101 | |
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[121] | 102 | ///////////////////////////////////////////////// |
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| 103 | inline struct thread_s * hal_get_current_thread() |
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[1] | 104 | { |
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| 105 | void * thread_ptr; |
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| 106 | |
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[279] | 107 | asm volatile ("mfc0 %0, $4, 2" : "=&r" (thread_ptr)); |
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[1] | 108 | |
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| 109 | return thread_ptr; |
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| 110 | } |
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| 111 | |
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| 112 | /////////////////////////////////////////////////////// |
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| 113 | void hal_set_current_thread( struct thread_s * thread ) |
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| 114 | { |
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[279] | 115 | asm volatile ("mtc0 %0, $4, 2" : : "r" (thread)); |
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[1] | 116 | } |
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| 117 | |
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| 118 | ///////////////////// |
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| 119 | void hal_fpu_enable() |
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| 120 | { |
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| 121 | asm volatile |
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| 122 | ( ".set noat \n" |
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| 123 | "lui $27, 0x2000 \n" |
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| 124 | "mfc0 $1, $12 \n" |
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| 125 | "or $27, $1, $27 \n" |
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| 126 | "mtc0 $27, $12 \n" |
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| 127 | ".set at \n" ); |
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| 128 | } |
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| 129 | |
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| 130 | ////////////////////// |
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| 131 | void hal_fpu_disable() |
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| 132 | { |
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| 133 | asm volatile |
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| 134 | ( ".set noat \n" |
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| 135 | "lui $27, 0xDFFF \n" |
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| 136 | "ori $27, $27, 0xFFFF \n" |
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| 137 | "mfc0 $1, $12 \n" |
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| 138 | "and $27, $1, $27 \n" |
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| 139 | "mtc0 $27, $12 \n" |
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| 140 | ".set at \n"); |
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| 141 | } |
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| 142 | |
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| 143 | //////////////////////// |
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| 144 | uint32_t hal_get_stack() |
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| 145 | { |
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| 146 | register uint32_t sp; |
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| 147 | |
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[279] | 148 | asm volatile ("or %0, $0, $29" : "=&r" (sp)); |
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[1] | 149 | |
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| 150 | return sp; |
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| 151 | } |
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| 152 | |
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| 153 | //////////////////////////////////////// |
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| 154 | uint32_t hal_set_stack( void * new_val ) |
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| 155 | { |
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| 156 | register uint32_t sp; |
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| 157 | |
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| 158 | asm volatile |
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| 159 | ( "or %0, $0, $29 \n" |
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| 160 | "or $29, $0, %1 \n" |
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| 161 | : "=&r" (sp) : "r" (new_val) ); |
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| 162 | |
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| 163 | return sp; |
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| 164 | } |
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| 165 | |
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| 166 | //////////////////////////// |
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| 167 | uint32_t hal_get_bad_vaddr() |
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| 168 | { |
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| 169 | register uint32_t bad_va; |
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| 170 | |
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| 171 | asm volatile |
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| 172 | ( "mfc0 %0, $8 \n" |
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| 173 | : "=&r" (bad_va) ); |
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| 174 | |
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| 175 | return bad_va; |
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| 176 | } |
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| 177 | |
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| 178 | //////////////////////////////////////////// |
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| 179 | uint32_t hal_uncached_read( uint32_t * ptr ) |
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| 180 | { |
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| 181 | register uint32_t val; |
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| 182 | |
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| 183 | asm volatile |
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| 184 | ( "ll %0, (%1) \n" |
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| 185 | : "=&r"(val) : "r" (ptr) ); |
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| 186 | |
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| 187 | return val; |
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| 188 | } |
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| 189 | |
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| 190 | ////////////////////////////////////////// |
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| 191 | void hal_invalid_dcache_line( void * ptr ) |
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| 192 | { |
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| 193 | asm volatile |
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| 194 | ( "cache %0, (%1) \n" |
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| 195 | "sync \n" |
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| 196 | : : "i" (0x11) , "r" (ptr) ); |
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| 197 | } |
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| 198 | |
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[124] | 199 | //////////////// |
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| 200 | void hal_fence() |
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[1] | 201 | { |
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| 202 | asm volatile |
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| 203 | ( "sync \n":: ); |
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| 204 | } |
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| 205 | |
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| 206 | //////////////// |
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| 207 | void hal_rdbar() |
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| 208 | { |
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| 209 | asm volatile( "" ::: "memory" ); |
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| 210 | } |
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| 211 | |
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| 212 | ///////////////////// |
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| 213 | void hal_core_sleep() |
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| 214 | { |
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| 215 | asm volatile |
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| 216 | ("wait \n"::); |
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| 217 | } |
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| 218 | |
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| 219 | ////////////////////////////////////// |
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| 220 | void hal_fixed_delay( uint32_t delay ) |
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| 221 | { |
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| 222 | asm volatile |
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| 223 | ( "1: \n" |
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| 224 | "or $27, %0, $0 \n" |
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| 225 | "addi $27, $27, -1 \n" |
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| 226 | "bne $27, $0, 1b \n" |
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| 227 | "nop \n" |
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| 228 | : : "r" (delay) : "$27" ); |
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| 229 | } |
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| 230 | |
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[16] | 231 | ////////////////////////////////////////////////// |
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| 232 | void hal_get_mmu_excp( intptr_t * mmu_ins_excp_code, |
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| 233 | intptr_t * mmu_ins_bad_vaddr, |
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| 234 | intptr_t * mmu_dat_excp_code, |
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| 235 | intptr_t * mmu_dat_bad_vaddr ) |
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| 236 | { |
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| 237 | asm volatile |
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| 238 | ( "mfc2 %0, $11 \n" |
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| 239 | "mfc2 %1, $13 \n" |
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| 240 | "mfc2 %2, $12 \n" |
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| 241 | "mfc2 %3, $14 \n" |
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| 242 | : "=&r"(mmu_ins_excp_code), |
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| 243 | "=&r"(mmu_ins_bad_vaddr), |
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| 244 | "=&r"(mmu_dat_excp_code), |
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| 245 | "=&r"(mmu_dat_bad_vaddr) ); |
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| 246 | } |
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