| 1 | /* |
|---|
| 2 | * soclib_dma.h - soclib Multi Channels DMA driver definition. |
|---|
| 3 | * |
|---|
| 4 | * Author Alain Greiner (2017) |
|---|
| 5 | * |
|---|
| 6 | * Copyright (c) UPMC Sorbonne Universites |
|---|
| 7 | * |
|---|
| 8 | * This file is part of ALMOS-MKH. |
|---|
| 9 | * |
|---|
| 10 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
|---|
| 11 | * under the terms of the GNU General Public License as published by |
|---|
| 12 | * the Free Software Foundation; version 2.0 of the License. |
|---|
| 13 | * |
|---|
| 14 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
|---|
| 15 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
|---|
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
|---|
| 17 | * General Public License for more details. |
|---|
| 18 | * |
|---|
| 19 | * You should have received a copy of the GNU General Public License |
|---|
| 20 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
|---|
| 21 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
|---|
| 22 | */ |
|---|
| 23 | |
|---|
| 24 | #ifndef _SOCLIB_DMA_H_ |
|---|
| 25 | #define _SOCLIB_DMA_H_ |
|---|
| 26 | |
|---|
| 27 | /******************************************************************************************** |
|---|
| 28 | * This driver supports the SocLib VciBlockDevice component, that is a simgle channel, |
|---|
| 29 | * block oriented, external storage controler, supporting only one I/O transaction, |
|---|
| 30 | * at a given time. |
|---|
| 31 | *******************************************************************************************/ |
|---|
| 32 | |
|---|
| 33 | /******************************************************************************************** |
|---|
| 34 | * SOCLIB_DMA registers offset |
|---|
| 35 | *******************************************************************************************/ |
|---|
| 36 | |
|---|
| 37 | enum SoclibDmaRegisters |
|---|
| 38 | { |
|---|
| 39 | DMA_SRC = 0, /*! source buffer 32 LSB address bits */ |
|---|
| 40 | DMA_DST = 1, /*! source buffer 32 LSB address bits */ |
|---|
| 41 | DMA_LEN_STS = 2, /*! number of bytes (on write) / transfer status (on read) */ |
|---|
| 42 | DMA_RESET = 3, /*! desactivate channel (can be usde to acknowledge IRQ) */ |
|---|
| 43 | DMA_IRQ_DISABLED = 4, /*! no IRQ generated if non zero */ |
|---|
| 44 | DMA_SRC_EXT = 5, /*! source buffer 32 MSB address bits */ |
|---|
| 45 | DMA_DST_EXT = 6, /*! source buffer 32 MSB address bits */ |
|---|
| 46 | |
|---|
| 47 | DMA_SPAN = 8, /*! number of registers per channel */ |
|---|
| 48 | }; |
|---|
| 49 | |
|---|
| 50 | /******************************************************************************************** |
|---|
| 51 | * SOCLIB_DMA status values |
|---|
| 52 | *******************************************************************************************/ |
|---|
| 53 | |
|---|
| 54 | #define DMA_SUCCESS 0 |
|---|
| 55 | #define DMA_IDLE 2 |
|---|
| 56 | #define DMA_ERROR_READ 1 |
|---|
| 57 | #define DMA_ERROR_WRITE 3 |
|---|
| 58 | #define DMA_BUSY 4 // or any value larger than 3 |
|---|
| 59 | |
|---|
| 60 | |
|---|
| 61 | /******************************************************************************************** |
|---|
| 62 | * This function access the SOCLIB_DMA hardware register to disable interrupts, |
|---|
| 63 | * because the most frequent operations are supposed to be synchronous accesses. |
|---|
| 64 | ******************************************************************************************** |
|---|
| 65 | * @ chdev : pointer on DMA chdev descriptor. |
|---|
| 66 | *******************************************************************************************/ |
|---|
| 67 | extern void soclib_dma_init( chdev_t * chdev ); |
|---|
| 68 | |
|---|
| 69 | /******************************************************************************************** |
|---|
| 70 | * This function can be called by the "server" thread associated to the DMA channel, for an |
|---|
| 71 | * asynchronous access, or can be directly called by the "client" thread for a synchronous |
|---|
| 72 | * access. In both cases, it get the command arguments from the calling thread descriptor, |
|---|
| 73 | * and access the DMA registers to launch the DMA transfer. |
|---|
| 74 | * Then, the waiting policy depends on the command type: |
|---|
| 75 | * - for asynchronous access, it enables the DMA interrupts, blocks on THREAD_BLOCKED_ISR, |
|---|
| 76 | * and deschedules. It will be re-activated by the soclib_dma_isr() function. |
|---|
| 77 | * - for a synchronous transfer, it polls the DMA status register until completion, |
|---|
| 78 | * and reports the transfer status in the command registered in the client thread. |
|---|
| 79 | ******************************************************************************************** |
|---|
| 80 | * @ thread_xp : extended pointer on the client thread. |
|---|
| 81 | *******************************************************************************************/ |
|---|
| 82 | extern void soclib_dma_cmd( xptr_t thread_xp ); |
|---|
| 83 | |
|---|
| 84 | /******************************************************************************************** |
|---|
| 85 | * This Interrupt Service Routine is executed when the IRQ signaling the completion of |
|---|
| 86 | * an asynchronous DMA command is received by a core. It acknowledge the IRQ by accessing |
|---|
| 87 | * the proper SOCLIB_DMA register, reports the transfer status in the command registered |
|---|
| 88 | * in the client thread descriptor, and unblock the server thread. |
|---|
| 89 | ******************************************************************************************** |
|---|
| 90 | * @ chdev : pointer on DMA chdev descriptor. |
|---|
| 91 | *******************************************************************************************/ |
|---|
| 92 | extern void soclib_dma_isr( chdev_t * chdev ); |
|---|
| 93 | |
|---|
| 94 | |
|---|
| 95 | #endif /* _SOCLIB_DMA_H_ */ |
|---|
