Changeset 657 for trunk/hal/tsar_mips32/drivers/soclib_dma.h
- Timestamp:
- Mar 18, 2020, 11:16:59 PM (5 years ago)
- File:
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- 1 edited
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trunk/hal/tsar_mips32/drivers/soclib_dma.h
r75 r657 39 39 DMA_SRC = 0, /*! source buffer 32 LSB address bits */ 40 40 DMA_DST = 1, /*! source buffer 32 LSB address bits */ 41 DMA_LEN 41 DMA_LEN_STS = 2, /*! number of bytes (on write) / transfer status (on read) */ 42 42 DMA_RESET = 3, /*! desactivate channel (can be usde to acknowledge IRQ) */ 43 43 DMA_IRQ_DISABLED = 4, /*! no IRQ generated if non zero */ … … 60 60 61 61 /******************************************************************************************** 62 * This function access the SOCLIB_DMA hardware register to enable interrupts. 62 * This function access the SOCLIB_DMA hardware register to disable interrupts, 63 * because the most frequent operations are supposed to be synchronous accesses. 63 64 ******************************************************************************************** 64 65 * @ chdev : pointer on DMA chdev descriptor. … … 67 68 68 69 /******************************************************************************************** 69 * This function is called by the server thread associated to the DMA device. 70 * It access the command embedded in the calling thread descriptor, (format defined in the 71 * dev_dma.h file) and access the SOCLIB_DMA hardware registers to start command execution. 72 * Then it blocks on the THREAD_BLOCKED_DEV_ISR and deschedules, because each DMA channel 73 * can only execute one command at a given time. 74 * It is re-activated by the ISR signaling the transfer completion. 70 * This function can be called by the "server" thread associated to the DMA channel, for an 71 * asynchronous access, or can be directly called by the "client" thread for a synchronous 72 * access. In both cases, it get the command arguments from the calling thread descriptor, 73 * and access the DMA registers to launch the DMA transfer. 74 * Then, the waiting policy depends on the command type: 75 * - for asynchronous access, it enables the DMA interrupts, blocks on THREAD_BLOCKED_ISR, 76 * and deschedules. It will be re-activated by the soclib_dma_isr() function. 77 * - for a synchronous transfer, it polls the DMA status register until completion, 78 * and reports the transfer status in the command registered in the client thread. 75 79 ******************************************************************************************** 76 80 * @ thread_xp : extended pointer on the client thread. … … 80 84 /******************************************************************************************** 81 85 * This Interrupt Service Routine is executed when the IRQ signaling the completion of 82 * a DMA command is received by a core. It acknowledge the IRQ by accessing the proper83 * SOCLIB_DMA register, unblock the client thread, and unblock the server thread that84 * can starts execution of a new command if the waiting queue is not emppty.86 * an asynchronous DMA command is received by a core. It acknowledge the IRQ by accessing 87 * the proper SOCLIB_DMA register, reports the transfer status in the command registered 88 * in the client thread descriptor, and unblock the server thread. 85 89 ******************************************************************************************** 86 90 * @ chdev : pointer on DMA chdev descriptor.
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