source: trunk/hal/tsar_mips32/drivers/soclib_mmc.h @ 633

Last change on this file since 633 was 626, checked in by alain, 6 years ago

This version has been tested on the sort multithreaded application
for TSAR_IOB architectures ranging from 1 to 8 clusters.
It fixes three bigs bugs:
1) the dev_ioc device API has been modified: the dev_ioc_sync_read()
and dev_ioc_sync_write() function use now extended pointers on the
kernel buffer to access a mapper stored in any cluster.
2) the hal_uspace API has been modified: the hal_copy_to_uspace()
and hal_copy_from_uspace() functions use now a (cxy,ptr) couple
to identify the target buffer (equivalent to an extended pointer.
3) an implementation bug has been fixed in the assembly code contained
in the hal_copy_to_uspace() and hal_copy_from_uspace() functions.
File size: 6.5 KB
RevLine 
[75]1/*
[626]2 * soclib_mmc.h - TSAR L2 cache driver definition.
[75]3 *
[626]4 * Author    Alain Greiner (2016,2017,2018,2019)
[75]5 *
6 * Copyright (c) UPMC Sorbonne Universites
7 *
8 * This file is part of ALMOS-MKH.
9 *
10 * ALMOS-MKH is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2.0 of the License.
13 *
14 * ALMOS-MKH is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with ALMOS-MKH; if not, write to the Free Software Foundation,
21 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24#ifndef _SOCLIB_MMC_H_
25#define _SOCLIB_MMC_H_
26
27#include <chdev.h>
28#include <dev_mmc.h>
[451]29#include <hal_kernel_types.h>
[75]30
31/********************************************************************************************
32 * This driver supports the SocLib VciMemCache component, that is the L2 cache used
33 * by the TSAR architure.
34 *******************************************************************************************/
35
36/********************************************************************************************
37 *       SOCLIB_MMC registers offset
38 *  - the register index is coded on 7 address bits : A[8:2]
39 *  - the functionnality is coded on 2 address bits : A[10:9]
40 *******************************************************************************************/
41
42enum SoclibMemCacheFunc
43{
44    SOCLIB_MMC_CC_FUNC    = 0,
45    SOCLIB_MMC_INSTR_FUNC = 1,
46    SOCLIB_MMC_ERROR_FUNC = 2,
47
48    SOCLIB_MMC_FUNC_SPAN  = 0x200
49};
50
51enum SoclibMemCacheCCRegs
52{
53    SOCLIB_MMC_ADDR_LO    = 0,
54    SOCLIB_MMC_ADDR_HI    = 1,
55    SOCLIB_MMC_BUF_LENGTH = 2,
56    SOCLIB_MMC_CMD_TYPE   = 3,
57};
58
59enum SoclibMemCacheConfigCmd
60{
61    SOCLIB_MMC_CC_NOP     = 0,
62    SOCLIB_MMC_CC_INVAL   = 1,
63    SOCLIB_MMC_CC_SYNC    = 2,
64};
65
66enum SoclibMemCacheInstrRegs
67{
68
69    // NUMBER OF LOCAL TRANSACTIONS ON DIRECT NETWORK
70
71    SOCLIB_MMC_LOCAL_READ_LO     = 0x00,
72    SOCLIB_MMC_LOCAL_READ_HI     = 0x01,
73    SOCLIB_MMC_LOCAL_WRITE_LO    = 0x02,
74    SOCLIB_MMC_LOCAL_WRITE_HI    = 0x03,
75    SOCLIB_MMC_LOCAL_LL_LO       = 0x04,
76    SOCLIB_MMC_LOCAL_LL_HI       = 0x05,
77    SOCLIB_MMC_LOCAL_SC_LO       = 0x06,
78    SOCLIB_MMC_LOCAL_SC_HI       = 0x07,
79    SOCLIB_MMC_LOCAL_CAS_LO      = 0x08,
80    SOCLIB_MMC_LOCAL_CAS_HI      = 0x09,
81
82    // NUMBER OF REMOTE TRANSACTIONS ON DIRECT NETWORK
83
84    SOCLIB_MMC_REMOTE_READ_LO    = 0x10,
85    SOCLIB_MMC_REMOTE_READ_HI    = 0x11,
86    SOCLIB_MMC_REMOTE_WRITE_LO   = 0x12,
87    SOCLIB_MMC_REMOTE_WRITE_HI   = 0x13,
88    SOCLIB_MMC_REMOTE_LL_LO      = 0x14,
89    SOCLIB_MMC_REMOTE_LL_HI      = 0x15,
90    SOCLIB_MMC_REMOTE_SC_LO      = 0x16,
91    SOCLIB_MMC_REMOTE_SC_HI      = 0x17,
92    SOCLIB_MMC_REMOTE_CAS_LO     = 0x18,
93    SOCLIB_MMC_REMOTE_CAS_HI     = 0x19,
94
95    // COST OF TRANSACTIONS ON DIRECT NETWORK
96
97    SOCLIB_MMC_COST_READ_LO      = 0x20,
98    SOCLIB_MMC_COST_READ_HI      = 0x21,
99    SOCLIB_MMC_COST_WRITE_LO     = 0x22,
100    SOCLIB_MMC_COST_WRITE_HI     = 0x23,
101    SOCLIB_MMC_COST_LL_LO        = 0x24,
102    SOCLIB_MMC_COST_LL_HI        = 0x25,
103    SOCLIB_MMC_COST_SC_LO        = 0x26,
104    SOCLIB_MMC_COST_SC_HI        = 0x27,
105    SOCLIB_MMC_COST_CAS_LO       = 0x28,
106    SOCLIB_MMC_COST_CAS_HI       = 0x29,
107
108    // NUMBER OF LOCAL TRANSACTIONS ON CC NETWORK
109
110    SOCLIB_MMC_LOCAL_MUPDATE_LO  = 0x40,
111    SOCLIB_MMC_LOCAL_MUPDATE_HI  = 0x41,
112    SOCLIB_MMC_LOCAL_MINVAL_LO   = 0x42,
113    SOCLIB_MMC_LOCAL_MINVAL_HI   = 0x43,
114    SOCLIB_MMC_LOCAL_CLEANUP_LO  = 0x44,
115    SOCLIB_MMC_LOCAL_CLEANUP_HI  = 0x45,
116
117    // NUMBER OF REMOTE TRANSACTIONS ON CC NETWORK
118
119    SOCLIB_MMC_REMOTE_MUPDATE_LO = 0x50,
120    SOCLIB_MMC_REMOTE_MUPDATE_HI = 0x51,
121    SOCLIB_MMC_REMOTE_MINVAL_LO  = 0x52,
122    SOCLIB_MMC_REMOTE_MINVAL_HI  = 0x53,
123    SOCLIB_MMC_REMOTE_CLEANUP_LO = 0x54,
124    SOCLIB_MMC_REMOTE_CLEANUP_HI = 0x55,
125
126    // COST OF TRANSACTIONS ON CC NETWORK
127
128    SOCLIB_MMC_COST_MUPDATE_LO   = 0x60,
129    SOCLIB_MMC_COST_MUPDATE_HI   = 0x61,
130    SOCLIB_MMC_COST_MINVAL_LO    = 0x62,
131    SOCLIB_MMC_COST_MINVAL_HI    = 0x63,
132    SOCLIB_MMC_COST_CLEANUP_LO   = 0x64,
133    SOCLIB_MMC_COST_CLEANUP_HI   = 0x65,
134
135    // TOTAL
136
137    SOCLIB_MMC_TOTAL_MUPDATE_LO  = 0x68,
138    SOCLIB_MMC_TOTAL_MUPDATE_HI  = 0x69,
139    SOCLIB_MMC_TOTAL_MINVAL_LO   = 0x6A,
140    SOCLIB_MMC_TOTAL_MINVAL_HI   = 0x6B,
141    SOCLIB_MMC_TOTAL_BINVAL_LO   = 0x6C,
142    SOCLIB_MMC_TOTAL_BINVAL_HI   = 0x6D,
143};
144
145enum SoclibMemCacheRerrorRegs
146{
147    SOCLIB_MMC_ERROR_ADDR_LO     = 0,
148    SOCLIB_MMC_ERROR_ADDR_HI     = 1,
149    SOCLIB_MMC_ERROR_SRCID       = 2, 
150    SOCLIB_MMC_ERROR_IRQ_RESET   = 3,
151    SOCLIB_MMC_ERROR_IRQ_ENABLE  = 4,
152};
153
154
155#define MMC_REG(func,index) ((func<<7)|index)
156
157
158/********************************************************************************************
159 * This function initializes the SOCLIB_MMC peripheral hardware registers related
160 * to error signaling. It enables the MMC peripheral IRQ.
161 ********************************************************************************************
162 * @ chdev      : local pointer on the MMC chdev descriptor.
163 *******************************************************************************************/
164extern void soclib_mmc_init( chdev_t * chdev );
165
166/********************************************************************************************
167 * This blocking function can be called by any thread running in any cluster.
168 * It executes the command registered in the calling thread descriptor.
169 * The MMC device spinlock must have been taken by the calling thead.
170 ********************************************************************************************
171 * @ thread_xp  : extended pointer on the client thread.
172 *******************************************************************************************/
173extern void soclib_mmc_cmd( xptr_t thread_xp );
174
175/********************************************************************************************
176 * This Interrupt Service Routine is executed when the MMC IRQ signals a faulty address.
177 * The ISR should access the vci_mem_cache component to get the faulty physical address
178 * and the associated SRCID, and acknowledges the IRQ.
179 ********************************************************************************************
180 * @ chdev     : local pointer on the MMC chdev descriptor.
181 *******************************************************************************************/
182extern void soclib_mmc_isr( chdev_t * chdev );
183
184
185#endif // SOCLIB_MMC_H_
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