[45] | 1 | /* |
---|
[82] | 2 | * hal_apic.c - Advanced Programmable Interrupt Controller |
---|
[45] | 3 | * |
---|
| 4 | * Copyright (c) 2017 Maxime Villard |
---|
| 5 | * |
---|
| 6 | * This file is part of ALMOS-MKH. |
---|
| 7 | * |
---|
| 8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
---|
| 9 | * under the terms of the GNU General Public License as published by |
---|
| 10 | * the Free Software Foundation; version 2.0 of the License. |
---|
| 11 | * |
---|
| 12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
---|
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
---|
| 15 | * General Public License for more details. |
---|
| 16 | * |
---|
| 17 | * You should have received a copy of the GNU General Public License |
---|
| 18 | * along with ALMOS-MKH.; if not, write to the Free Software Foundation, |
---|
| 19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
---|
| 20 | */ |
---|
| 21 | |
---|
| 22 | #include <hal_types.h> |
---|
[83] | 23 | #include <hal_boot.h> |
---|
[82] | 24 | #include <hal_register.h> |
---|
[45] | 25 | #include <hal_segmentation.h> |
---|
[82] | 26 | #include <hal_apic.h> |
---|
[45] | 27 | #include <hal_internal.h> |
---|
| 28 | |
---|
| 29 | #include <memcpy.h> |
---|
| 30 | #include <thread.h> |
---|
| 31 | #include <string.h> |
---|
| 32 | #include <process.h> |
---|
| 33 | #include <printk.h> |
---|
| 34 | #include <vmm.h> |
---|
| 35 | #include <core.h> |
---|
| 36 | #include <cluster.h> |
---|
| 37 | |
---|
[82] | 38 | /* -------------------------------------------------------------------------- */ |
---|
| 39 | |
---|
| 40 | #define PIC1_CMD 0x0020 |
---|
| 41 | #define PIC1_DATA 0x0021 |
---|
| 42 | #define PIC2_CMD 0x00a0 |
---|
| 43 | #define PIC2_DATA 0x00a1 |
---|
| 44 | |
---|
| 45 | static void hal_pic_init() |
---|
| 46 | { |
---|
| 47 | /* |
---|
| 48 | * Disable the PIC (8259A). We are going to use IOAPIC instead. |
---|
| 49 | */ |
---|
| 50 | out8(PIC1_DATA, 0xff); |
---|
| 51 | out8(PIC2_DATA, 0xff); |
---|
| 52 | } |
---|
| 53 | |
---|
| 54 | /* -------------------------------------------------------------------------- */ |
---|
| 55 | |
---|
[117] | 56 | uint64_t pit_ticks_base __in_kdata = 0; |
---|
| 57 | |
---|
| 58 | #define PIT_FREQUENCY 1193182 |
---|
| 59 | #define HZ 100 /* 1/HZ = 10ms */ |
---|
| 60 | |
---|
| 61 | #define PIT_TIMER0 0x40 |
---|
| 62 | |
---|
| 63 | #define PIT_CMD 0x43 |
---|
| 64 | # define CMD_BINARY 0x00 /* Use Binary counter values */ |
---|
| 65 | # define CMD_BCD 0x01 /* Use Binary Coded Decimal counter values */ |
---|
| 66 | # define CMD_MODE0 0x00 /* Interrupt on Terminal Count */ |
---|
| 67 | # define CMD_MODE1 0x02 /* Hardware Retriggerable One-Shot */ |
---|
| 68 | # define CMD_MODE2 0x04 /* Rate Generator */ |
---|
| 69 | # define CMD_MODE3 0x06 /* Square Wave */ |
---|
| 70 | # define CMD_MODE4 0x08 /* Software Trigerred Strobe */ |
---|
| 71 | # define CMD_MODE5 0x0a /* Hardware Trigerred Strobe */ |
---|
| 72 | # define CMD_LATCH 0x00 /* latch counter for reading */ |
---|
| 73 | # define CMD_LSB 0x10 /* LSB, 8 bits */ |
---|
| 74 | # define CMD_MSB 0x20 /* MSB, 8 bits */ |
---|
| 75 | # define CMD_16BIT 0x30 /* LSB and MSB, 16 bits */ |
---|
| 76 | # define CMD_COUNTER0 0x00 |
---|
| 77 | # define CMD_COUNTER1 0x40 |
---|
| 78 | # define CMD_COUNTER2 0x80 |
---|
| 79 | # define CMD_READBACK 0xc0 |
---|
| 80 | |
---|
| 81 | void hal_pit_init() |
---|
| 82 | { |
---|
| 83 | /* Initialize PIT clock 0 to the maximum counter value, 65535. */ |
---|
| 84 | out8(PIT_CMD, CMD_COUNTER0|CMD_MODE2|CMD_16BIT); |
---|
| 85 | out8(PIT_TIMER0, 0xFF); |
---|
| 86 | out8(PIT_TIMER0, 0xFF); |
---|
| 87 | } |
---|
| 88 | |
---|
| 89 | uint64_t |
---|
| 90 | hal_pit_timer_read() |
---|
| 91 | { |
---|
| 92 | static uint16_t last; |
---|
| 93 | |
---|
| 94 | uint8_t lo, hi; |
---|
| 95 | uint16_t ctr; |
---|
| 96 | uint64_t ticks; |
---|
| 97 | |
---|
| 98 | /* Read the current timer counter. */ |
---|
| 99 | out8(PIT_CMD, CMD_COUNTER0|CMD_LATCH); |
---|
| 100 | lo = in8(PIT_TIMER0); |
---|
| 101 | hi = in8(PIT_TIMER0); |
---|
| 102 | ctr = (hi << 8) | lo; |
---|
| 103 | |
---|
| 104 | /* If the counter has wrapped, assume we're into the next tick. */ |
---|
| 105 | if (ctr > last) |
---|
| 106 | pit_ticks_base += 0xFFFF; |
---|
| 107 | last = ctr; |
---|
| 108 | |
---|
| 109 | ticks = pit_ticks_base + (0xFFFF - ctr); |
---|
| 110 | |
---|
| 111 | return ticks; |
---|
| 112 | } |
---|
| 113 | |
---|
| 114 | /* -------------------------------------------------------------------------- */ |
---|
| 115 | |
---|
[135] | 116 | size_t ioapic_pins __in_kdata = 0; |
---|
[89] | 117 | paddr_t ioapic_pa __in_kdata = 0; |
---|
| 118 | vaddr_t ioapic_va __in_kdata = 0; |
---|
| 119 | |
---|
| 120 | #define IRQ_TIMER 0x00 |
---|
| 121 | #define IRQ_KEYBOARD 0x01 |
---|
| 122 | #define IRQ_COM2 0x03 |
---|
| 123 | #define IRQ_COM1 0x04 |
---|
| 124 | #define IRQ_FLOPPY 0x06 |
---|
| 125 | #define IRQ_ATA0 0x0e |
---|
| 126 | #define IRQ_ATA1 0x0f |
---|
| 127 | |
---|
| 128 | #define IOREGSEL 0x00 |
---|
| 129 | #define IOWIN 0x10 |
---|
| 130 | |
---|
| 131 | #define IOAPICID 0x00 |
---|
| 132 | #define IOAPICVER 0x01 |
---|
| 133 | #define IOAPICARB 0x02 |
---|
[137] | 134 | |
---|
[89] | 135 | #define IOREDTBL 0x10 |
---|
[137] | 136 | # define IOREDTBL_DEL_FIXED 0x000 |
---|
| 137 | # define IOREDTBL_DEL_LOPRI 0x100 |
---|
| 138 | # define IOREDTBL_DEL_SMI 0x200 |
---|
| 139 | # define IOREDTBL_DEL_NMI 0x400 |
---|
| 140 | # define IOREDTBL_DEL_INIT 0x500 |
---|
| 141 | # define IOREDTBL_DEL_EXTINT 0x700 |
---|
| 142 | # define IOREDTBL_DEM_PHYS 0x000 |
---|
| 143 | # define IOREDTBL_DEM_LOGIC 0x800 |
---|
| 144 | # define IOREDTBL_DES_SHIFT 56 |
---|
| 145 | # define IOREDTBL_MSK 0x10000 |
---|
[89] | 146 | |
---|
| 147 | void hal_ioapic_write(uint8_t reg, uint32_t val) |
---|
| 148 | { |
---|
| 149 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
---|
| 150 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)) = val; |
---|
| 151 | } |
---|
| 152 | |
---|
| 153 | uint32_t hal_ioapic_read(uint8_t reg) |
---|
| 154 | { |
---|
| 155 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
---|
| 156 | return *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)); |
---|
| 157 | } |
---|
| 158 | |
---|
[137] | 159 | void hal_ioapic_disable_entry(uint8_t index) |
---|
[89] | 160 | { |
---|
[137] | 161 | const uint64_t data = IOREDTBL_MSK; |
---|
| 162 | |
---|
[89] | 163 | hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF)); |
---|
| 164 | hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32)); |
---|
| 165 | } |
---|
| 166 | |
---|
[137] | 167 | void hal_ioapic_set_entry(uint8_t index, uint8_t vec, uint8_t dest) |
---|
| 168 | { |
---|
| 169 | const uint64_t data = ((uint64_t)dest << IOREDTBL_DES_SHIFT) | |
---|
| 170 | IOREDTBL_DEM_PHYS | IOREDTBL_DEL_FIXED | vec; |
---|
| 171 | |
---|
| 172 | hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF)); |
---|
| 173 | hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32)); |
---|
| 174 | } |
---|
| 175 | |
---|
[89] | 176 | static void hal_ioapic_init() |
---|
| 177 | { |
---|
| 178 | uint32_t ver; |
---|
[135] | 179 | size_t i; |
---|
[89] | 180 | |
---|
| 181 | ioapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
---|
| 182 | |
---|
| 183 | hal_gpt_enter(ioapic_va, ioapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
---|
| 184 | |
---|
| 185 | ver = hal_ioapic_read(IOAPICVER); |
---|
[135] | 186 | ioapic_pins = ((ver >> 16) & 0xFF) + 1; |
---|
[89] | 187 | |
---|
| 188 | /* Explicitly disable (mask) each vector */ |
---|
[135] | 189 | for (i = 0; i < ioapic_pins; i++) { |
---|
[137] | 190 | hal_ioapic_disable_entry(i); |
---|
[89] | 191 | } |
---|
| 192 | |
---|
[135] | 193 | x86_printf("IOAPICPINS: #%z\n", ioapic_pins); |
---|
| 194 | |
---|
[89] | 195 | /* Now, enable the keyboard */ |
---|
[137] | 196 | hal_ioapic_set_entry(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR, 0); |
---|
[89] | 197 | } |
---|
| 198 | |
---|
| 199 | /* -------------------------------------------------------------------------- */ |
---|
| 200 | |
---|
[45] | 201 | paddr_t lapic_pa __in_kdata = 0; |
---|
| 202 | vaddr_t lapic_va __in_kdata = 0; |
---|
| 203 | |
---|
[46] | 204 | void hal_lapic_write(uint32_t reg, uint32_t val) |
---|
[45] | 205 | { |
---|
[82] | 206 | *((volatile uint32_t *)((uint8_t *)lapic_va + reg)) = val; |
---|
[45] | 207 | } |
---|
| 208 | |
---|
[46] | 209 | uint32_t hal_lapic_read(uint32_t reg) |
---|
[45] | 210 | { |
---|
[82] | 211 | return *((volatile uint32_t *)((uint8_t *)lapic_va + reg)); |
---|
[45] | 212 | } |
---|
| 213 | |
---|
[46] | 214 | uint32_t hal_lapic_gid() |
---|
[45] | 215 | { |
---|
[46] | 216 | return hal_lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT; |
---|
| 217 | } |
---|
[45] | 218 | |
---|
[82] | 219 | /* |
---|
[117] | 220 | * Use the PIT, which has a standard clock frequency, to determine the CPU's |
---|
| 221 | * exact bus frequency. |
---|
| 222 | */ |
---|
| 223 | static void hal_lapic_calibrate() |
---|
| 224 | { |
---|
| 225 | uint64_t pittick, lapictick0, lapictick1; |
---|
| 226 | uint32_t lapicticks, lapicstart; |
---|
| 227 | |
---|
| 228 | /* Initialize the LAPIC timer to the maximum value */ |
---|
[145] | 229 | hal_lapic_write(LAPIC_ICR_TIMER, 0xFFFFFFFF); |
---|
[117] | 230 | |
---|
[135] | 231 | /* Initialize the PIT */ |
---|
| 232 | hal_pit_init(); |
---|
| 233 | |
---|
[117] | 234 | pittick = hal_pit_timer_read() + 1; |
---|
| 235 | while (hal_pit_timer_read() < pittick) { |
---|
| 236 | /* Wait until start of a PIT tick */ |
---|
| 237 | } |
---|
| 238 | |
---|
| 239 | /* Read base count from LAPIC */ |
---|
| 240 | lapictick0 = hal_lapic_read(LAPIC_CCR_TIMER); |
---|
| 241 | |
---|
| 242 | while (hal_pit_timer_read() < pittick + (PIT_FREQUENCY + HZ/2) / HZ) { |
---|
| 243 | /* Wait 1/HZ sec = 10ms */ |
---|
| 244 | } |
---|
| 245 | |
---|
| 246 | /* Read final count from LAPIC */ |
---|
| 247 | lapictick1 = hal_lapic_read(LAPIC_CCR_TIMER); |
---|
| 248 | |
---|
| 249 | /* Total number of LAPIC ticks per 1/HZ tick */ |
---|
| 250 | lapicticks = (lapictick1 - lapictick0); |
---|
| 251 | |
---|
| 252 | /* Finally, calibrate the timer, an interrupt each 1s. */ |
---|
| 253 | lapicstart = - (lapicticks * 100); |
---|
| 254 | hal_lapic_write(LAPIC_ICR_TIMER, lapicstart); |
---|
| 255 | } |
---|
| 256 | |
---|
| 257 | /* |
---|
[82] | 258 | * We have 8 interrupt sources: |
---|
| 259 | * - Spurious |
---|
| 260 | * - APIC Timer (TMR) |
---|
| 261 | * - Local Interrupt 0 (LINT0) |
---|
| 262 | * - Local Interrupt 1 (LINT1) |
---|
| 263 | * - Performance Monitor Counters (PMC) |
---|
| 264 | * - Thermal Sensors (THM) |
---|
| 265 | * - APIC internal error (ERR) |
---|
| 266 | * - Extended (Implementation dependent) |
---|
[135] | 267 | * Only the Spurious and APIC Timer interrupts are enabled. |
---|
[82] | 268 | */ |
---|
| 269 | static void hal_lapic_init() |
---|
[46] | 270 | { |
---|
[45] | 271 | lapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared |
---|
| 272 | |
---|
[82] | 273 | if ((rdmsr(MSR_APICBASE) & APICBASE_PHYSADDR) != lapic_pa) { |
---|
| 274 | x86_panic("APICBASE and ACPI don't match!\n"); |
---|
| 275 | } |
---|
| 276 | wrmsr(MSR_APICBASE, lapic_pa | APICBASE_EN); |
---|
| 277 | |
---|
[83] | 278 | hal_gpt_enter(lapic_va, lapic_pa, PG_V|PG_KW|PG_NX|PG_N); |
---|
[45] | 279 | |
---|
[46] | 280 | hal_lapic_write(LAPIC_TPR, 0); |
---|
[82] | 281 | hal_lapic_write(LAPIC_EOI, 0); |
---|
[138] | 282 | hal_lapic_write(LAPIC_SVR, LAPIC_SVR_ENABLE|VECTOR_APIC_SPURIOU); |
---|
[82] | 283 | |
---|
| 284 | /* Explicitly disable (mask) each vector */ |
---|
| 285 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_M); |
---|
| 286 | hal_lapic_write(LAPIC_LVT_LINT0, LAPIC_LINT_M); |
---|
| 287 | hal_lapic_write(LAPIC_LVT_LINT1, LAPIC_LINT_M); |
---|
| 288 | hal_lapic_write(LAPIC_LVT_PMC, LAPIC_PMC_M); |
---|
| 289 | hal_lapic_write(LAPIC_LVT_THM, LAPIC_THM_M); |
---|
| 290 | hal_lapic_write(LAPIC_LVT_ERR, LAPIC_ERR_M); |
---|
[86] | 291 | |
---|
| 292 | /* Now, enable the timer in repeated mode. */ |
---|
| 293 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TMR_M); |
---|
| 294 | hal_lapic_write(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1); |
---|
[117] | 295 | hal_lapic_calibrate(); |
---|
[86] | 296 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TIMER_VECTOR); |
---|
[45] | 297 | } |
---|
| 298 | |
---|
[82] | 299 | /* -------------------------------------------------------------------------- */ |
---|
| 300 | |
---|
| 301 | void hal_apic_init() |
---|
| 302 | { |
---|
| 303 | /* Disable the PIC */ |
---|
| 304 | hal_pic_init(); |
---|
| 305 | |
---|
| 306 | /* Enable the LAPIC */ |
---|
| 307 | hal_lapic_init(); |
---|
[89] | 308 | |
---|
| 309 | /* Enable the IOAPIC */ |
---|
| 310 | hal_ioapic_init(); |
---|
[82] | 311 | } |
---|
| 312 | |
---|