[45] | 1 | /* |
---|
[82] | 2 | * hal_apic.c - Advanced Programmable Interrupt Controller |
---|
[45] | 3 | * |
---|
| 4 | * Copyright (c) 2017 Maxime Villard |
---|
| 5 | * |
---|
| 6 | * This file is part of ALMOS-MKH. |
---|
| 7 | * |
---|
| 8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
---|
| 9 | * under the terms of the GNU General Public License as published by |
---|
| 10 | * the Free Software Foundation; version 2.0 of the License. |
---|
| 11 | * |
---|
| 12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
---|
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
---|
| 15 | * General Public License for more details. |
---|
| 16 | * |
---|
| 17 | * You should have received a copy of the GNU General Public License |
---|
[234] | 18 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
---|
[45] | 19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
---|
| 20 | */ |
---|
| 21 | |
---|
| 22 | #include <hal_types.h> |
---|
[83] | 23 | #include <hal_boot.h> |
---|
[82] | 24 | #include <hal_register.h> |
---|
[45] | 25 | #include <hal_segmentation.h> |
---|
[82] | 26 | #include <hal_apic.h> |
---|
[45] | 27 | #include <hal_internal.h> |
---|
| 28 | |
---|
| 29 | #include <memcpy.h> |
---|
| 30 | #include <thread.h> |
---|
| 31 | #include <string.h> |
---|
| 32 | #include <process.h> |
---|
| 33 | #include <printk.h> |
---|
| 34 | #include <vmm.h> |
---|
| 35 | #include <core.h> |
---|
| 36 | #include <cluster.h> |
---|
| 37 | |
---|
[82] | 38 | /* -------------------------------------------------------------------------- */ |
---|
| 39 | |
---|
| 40 | #define PIC1_CMD 0x0020 |
---|
| 41 | #define PIC1_DATA 0x0021 |
---|
| 42 | #define PIC2_CMD 0x00a0 |
---|
| 43 | #define PIC2_DATA 0x00a1 |
---|
| 44 | |
---|
| 45 | static void hal_pic_init() |
---|
| 46 | { |
---|
| 47 | /* |
---|
| 48 | * Disable the PIC (8259A). We are going to use IOAPIC instead. |
---|
| 49 | */ |
---|
| 50 | out8(PIC1_DATA, 0xff); |
---|
| 51 | out8(PIC2_DATA, 0xff); |
---|
| 52 | } |
---|
| 53 | |
---|
| 54 | /* -------------------------------------------------------------------------- */ |
---|
| 55 | |
---|
[117] | 56 | uint64_t pit_ticks_base __in_kdata = 0; |
---|
| 57 | |
---|
| 58 | #define PIT_FREQUENCY 1193182 |
---|
| 59 | #define HZ 100 /* 1/HZ = 10ms */ |
---|
| 60 | |
---|
| 61 | #define PIT_TIMER0 0x40 |
---|
| 62 | |
---|
| 63 | #define PIT_CMD 0x43 |
---|
| 64 | # define CMD_BINARY 0x00 /* Use Binary counter values */ |
---|
| 65 | # define CMD_BCD 0x01 /* Use Binary Coded Decimal counter values */ |
---|
| 66 | # define CMD_MODE0 0x00 /* Interrupt on Terminal Count */ |
---|
| 67 | # define CMD_MODE1 0x02 /* Hardware Retriggerable One-Shot */ |
---|
| 68 | # define CMD_MODE2 0x04 /* Rate Generator */ |
---|
| 69 | # define CMD_MODE3 0x06 /* Square Wave */ |
---|
| 70 | # define CMD_MODE4 0x08 /* Software Trigerred Strobe */ |
---|
| 71 | # define CMD_MODE5 0x0a /* Hardware Trigerred Strobe */ |
---|
| 72 | # define CMD_LATCH 0x00 /* latch counter for reading */ |
---|
| 73 | # define CMD_LSB 0x10 /* LSB, 8 bits */ |
---|
| 74 | # define CMD_MSB 0x20 /* MSB, 8 bits */ |
---|
| 75 | # define CMD_16BIT 0x30 /* LSB and MSB, 16 bits */ |
---|
| 76 | # define CMD_COUNTER0 0x00 |
---|
| 77 | # define CMD_COUNTER1 0x40 |
---|
| 78 | # define CMD_COUNTER2 0x80 |
---|
| 79 | # define CMD_READBACK 0xc0 |
---|
| 80 | |
---|
| 81 | void hal_pit_init() |
---|
| 82 | { |
---|
| 83 | /* Initialize PIT clock 0 to the maximum counter value, 65535. */ |
---|
| 84 | out8(PIT_CMD, CMD_COUNTER0|CMD_MODE2|CMD_16BIT); |
---|
| 85 | out8(PIT_TIMER0, 0xFF); |
---|
| 86 | out8(PIT_TIMER0, 0xFF); |
---|
| 87 | } |
---|
| 88 | |
---|
| 89 | uint64_t |
---|
| 90 | hal_pit_timer_read() |
---|
| 91 | { |
---|
| 92 | static uint16_t last; |
---|
| 93 | |
---|
| 94 | uint8_t lo, hi; |
---|
| 95 | uint16_t ctr; |
---|
| 96 | uint64_t ticks; |
---|
| 97 | |
---|
| 98 | /* Read the current timer counter. */ |
---|
| 99 | out8(PIT_CMD, CMD_COUNTER0|CMD_LATCH); |
---|
| 100 | lo = in8(PIT_TIMER0); |
---|
| 101 | hi = in8(PIT_TIMER0); |
---|
| 102 | ctr = (hi << 8) | lo; |
---|
| 103 | |
---|
| 104 | /* If the counter has wrapped, assume we're into the next tick. */ |
---|
| 105 | if (ctr > last) |
---|
| 106 | pit_ticks_base += 0xFFFF; |
---|
| 107 | last = ctr; |
---|
| 108 | |
---|
| 109 | ticks = pit_ticks_base + (0xFFFF - ctr); |
---|
| 110 | |
---|
| 111 | return ticks; |
---|
| 112 | } |
---|
| 113 | |
---|
| 114 | /* -------------------------------------------------------------------------- */ |
---|
| 115 | |
---|
[152] | 116 | #define BAUDRATE 19200 |
---|
| 117 | #define BAUDRATE_DIV (115200 / BAUDRATE) |
---|
| 118 | |
---|
| 119 | #define RS232_COM1_BASE 0x3F8 |
---|
| 120 | |
---|
| 121 | #define RS232_DATA 0x00 |
---|
| 122 | #define RS232_IER 0x01 |
---|
| 123 | # define IER_RD 0x01 |
---|
| 124 | # define IER_TBE 0x02 |
---|
| 125 | # define IER_ER_BRK 0x04 |
---|
| 126 | # define IER_RS232IN 0x08 |
---|
| 127 | #define RS232_DIVLO 0x00 /* when DLAB = 1 */ |
---|
| 128 | #define RS232_DIVHI 0x01 /* when DLAB = 1 */ |
---|
| 129 | #define RS232_IIR 0x02 |
---|
| 130 | #define RS232_LCR 0x03 |
---|
| 131 | # define LCR_DATA5 0x00 |
---|
| 132 | # define LCR_DATA6 0x01 |
---|
| 133 | # define LCR_DATA7 0x02 |
---|
| 134 | # define LCR_DATA8 0x03 |
---|
| 135 | # define LCR_TWOSTOP 0x04 |
---|
| 136 | # define LCR_PARITY 0x08 |
---|
| 137 | # define LCR_EVEN 0x10 |
---|
| 138 | # define LCR_STICK 0x20 |
---|
| 139 | # define LCR_DLAB 0x80 |
---|
| 140 | #define RS232_MCR 0x04 |
---|
| 141 | # define MCR_DTR 0x01 |
---|
| 142 | # define MCR_RTS 0x02 |
---|
| 143 | # define MCR_ELL 0x04 |
---|
| 144 | # define MCR_IR 0x40 |
---|
| 145 | #define RS232_LSR 0x05 |
---|
| 146 | # define LSR_DR 0x01 |
---|
| 147 | # define LSR_OVR 0x02 |
---|
| 148 | # define LSR_PE 0x04 |
---|
| 149 | # define LSR_FE 0x08 |
---|
| 150 | # define LSR_BRK 0x10 |
---|
| 151 | # define LSR_TBE 0x20 |
---|
| 152 | # define LSR_TE 0x40 |
---|
| 153 | #define RS232_MSR 0x06 |
---|
| 154 | # define MSR_DCTS 0x01 |
---|
| 155 | # define MSR_DDSR 0x02 |
---|
| 156 | # define MSR_DRI 0x04 |
---|
| 157 | # define MSR_DDCD 0x08 |
---|
| 158 | # define MSR_CTS 0x10 |
---|
| 159 | # define MSR_DSR 0x20 |
---|
| 160 | # define MSR_RI 0x40 |
---|
| 161 | # define MSR_DCD 0x80 |
---|
| 162 | |
---|
| 163 | #define RS232_SCRATCH 0x07 |
---|
| 164 | |
---|
| 165 | static bool_t hal_com_received() |
---|
| 166 | { |
---|
| 167 | return (in8(RS232_COM1_BASE + RS232_LSR) & LSR_DR) != 0; |
---|
| 168 | } |
---|
| 169 | |
---|
| 170 | static bool_t hal_com_transmit_empty() |
---|
| 171 | { |
---|
| 172 | return (in8(RS232_COM1_BASE + RS232_LSR) & LSR_TBE) != 0; |
---|
| 173 | } |
---|
| 174 | |
---|
| 175 | char hal_com_read() |
---|
| 176 | { |
---|
| 177 | while (!hal_com_received()); |
---|
| 178 | return in8(RS232_COM1_BASE + RS232_DATA); |
---|
| 179 | } |
---|
| 180 | |
---|
[154] | 181 | void hal_com_send(uint8_t chan, char c) |
---|
[152] | 182 | { |
---|
| 183 | uint8_t mcr = in8(RS232_COM1_BASE + RS232_MCR); |
---|
| 184 | out8(RS232_COM1_BASE + RS232_MCR, mcr | MCR_RTS); |
---|
| 185 | |
---|
| 186 | while (!hal_com_transmit_empty()); |
---|
[154] | 187 | out8(RS232_COM1_BASE + RS232_DATA, chan | 0x80); |
---|
[152] | 188 | out8(RS232_COM1_BASE + RS232_DATA, c); |
---|
| 189 | |
---|
| 190 | out8(RS232_COM1_BASE + RS232_MCR, mcr); |
---|
| 191 | } |
---|
| 192 | |
---|
[154] | 193 | /* |
---|
| 194 | * Called early to provide x86-specific messages. Interrupts disabled. |
---|
| 195 | */ |
---|
| 196 | void hal_com_init_early() |
---|
| 197 | { |
---|
| 198 | /* Disable all interrupts */ |
---|
| 199 | out8(RS232_COM1_BASE + RS232_IER, 0x00); |
---|
| 200 | |
---|
| 201 | /* Set baudrate */ |
---|
| 202 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DLAB); |
---|
| 203 | out8(RS232_COM1_BASE + RS232_DIVLO, BAUDRATE_DIV); |
---|
| 204 | out8(RS232_COM1_BASE + RS232_DIVHI, 0); |
---|
| 205 | |
---|
| 206 | /* 8bits, no parity, one stop bit */ |
---|
| 207 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DATA8); |
---|
| 208 | |
---|
| 209 | /* DTR set, and also DSR */ |
---|
| 210 | out8(RS232_COM1_BASE + RS232_MCR, MCR_DTR|MCR_IR); |
---|
| 211 | out8(RS232_COM1_BASE + RS232_MSR, MSR_DSR); |
---|
| 212 | } |
---|
| 213 | |
---|
[152] | 214 | static void hal_com_init() |
---|
| 215 | { |
---|
| 216 | /* Disable all interrupts */ |
---|
| 217 | out8(RS232_COM1_BASE + RS232_IER, 0x00); |
---|
| 218 | |
---|
| 219 | /* Set baudrate */ |
---|
| 220 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DLAB); |
---|
| 221 | out8(RS232_COM1_BASE + RS232_DIVLO, BAUDRATE_DIV); |
---|
| 222 | out8(RS232_COM1_BASE + RS232_DIVHI, 0); |
---|
| 223 | |
---|
| 224 | /* 8bits, no parity, one stop bit */ |
---|
| 225 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DATA8); |
---|
| 226 | |
---|
| 227 | /* Enable IRQs, DTR set, and also DSR */ |
---|
| 228 | out8(RS232_COM1_BASE + RS232_IER, IER_RD|IER_RS232IN); |
---|
| 229 | out8(RS232_COM1_BASE + RS232_MCR, MCR_DTR|MCR_IR); |
---|
| 230 | out8(RS232_COM1_BASE + RS232_MSR, MSR_DSR); |
---|
| 231 | } |
---|
| 232 | |
---|
| 233 | /* -------------------------------------------------------------------------- */ |
---|
| 234 | |
---|
[135] | 235 | size_t ioapic_pins __in_kdata = 0; |
---|
[89] | 236 | paddr_t ioapic_pa __in_kdata = 0; |
---|
| 237 | vaddr_t ioapic_va __in_kdata = 0; |
---|
| 238 | |
---|
| 239 | #define IOREGSEL 0x00 |
---|
| 240 | #define IOWIN 0x10 |
---|
| 241 | |
---|
| 242 | #define IOAPICID 0x00 |
---|
| 243 | #define IOAPICVER 0x01 |
---|
| 244 | #define IOAPICARB 0x02 |
---|
[137] | 245 | |
---|
[89] | 246 | #define IOREDTBL 0x10 |
---|
[137] | 247 | # define IOREDTBL_DEL_FIXED 0x000 |
---|
| 248 | # define IOREDTBL_DEL_LOPRI 0x100 |
---|
| 249 | # define IOREDTBL_DEL_SMI 0x200 |
---|
| 250 | # define IOREDTBL_DEL_NMI 0x400 |
---|
| 251 | # define IOREDTBL_DEL_INIT 0x500 |
---|
| 252 | # define IOREDTBL_DEL_EXTINT 0x700 |
---|
| 253 | # define IOREDTBL_DEM_PHYS 0x000 |
---|
| 254 | # define IOREDTBL_DEM_LOGIC 0x800 |
---|
| 255 | # define IOREDTBL_DES_SHIFT 56 |
---|
| 256 | # define IOREDTBL_MSK 0x10000 |
---|
[89] | 257 | |
---|
| 258 | void hal_ioapic_write(uint8_t reg, uint32_t val) |
---|
| 259 | { |
---|
| 260 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
---|
| 261 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)) = val; |
---|
| 262 | } |
---|
| 263 | |
---|
| 264 | uint32_t hal_ioapic_read(uint8_t reg) |
---|
| 265 | { |
---|
| 266 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
---|
| 267 | return *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)); |
---|
| 268 | } |
---|
| 269 | |
---|
[203] | 270 | void hal_ioapic_bind_irq(uint8_t irq, uint8_t vec, uint8_t dest) |
---|
[89] | 271 | { |
---|
[203] | 272 | const uint64_t data = ((uint64_t)dest << IOREDTBL_DES_SHIFT) | |
---|
| 273 | IOREDTBL_DEM_PHYS | IOREDTBL_DEL_FIXED | IOREDTBL_MSK | vec; |
---|
[137] | 274 | |
---|
[203] | 275 | hal_ioapic_write(IOREDTBL + irq * 2, (uint32_t)(data & 0xFFFFFFFF)); |
---|
| 276 | hal_ioapic_write(IOREDTBL + irq * 2 + 1, (uint32_t)(data >> 32)); |
---|
[89] | 277 | } |
---|
| 278 | |
---|
[203] | 279 | void hal_ioapic_enable_irq(uint8_t irq) |
---|
[137] | 280 | { |
---|
[203] | 281 | uint32_t data[2]; |
---|
[137] | 282 | |
---|
[203] | 283 | data[0] = hal_ioapic_read(IOREDTBL + irq * 2); |
---|
| 284 | data[1] = hal_ioapic_read(IOREDTBL + irq * 2 + 1); |
---|
| 285 | |
---|
| 286 | data[0] &= ~IOREDTBL_MSK; |
---|
| 287 | |
---|
| 288 | hal_ioapic_write(IOREDTBL + irq * 2, data[0]); |
---|
| 289 | hal_ioapic_write(IOREDTBL + irq * 2 + 1, data[1]); |
---|
[137] | 290 | } |
---|
| 291 | |
---|
[203] | 292 | void hal_ioapic_disable_irq(uint8_t irq) |
---|
| 293 | { |
---|
| 294 | uint32_t data[2]; |
---|
| 295 | |
---|
| 296 | data[0] = hal_ioapic_read(IOREDTBL + irq * 2); |
---|
| 297 | data[1] = hal_ioapic_read(IOREDTBL + irq * 2 + 1); |
---|
| 298 | |
---|
| 299 | data[0] |= IOREDTBL_MSK; |
---|
| 300 | |
---|
| 301 | hal_ioapic_write(IOREDTBL + irq * 2, data[0]); |
---|
| 302 | hal_ioapic_write(IOREDTBL + irq * 2 + 1, data[1]); |
---|
| 303 | } |
---|
| 304 | |
---|
[89] | 305 | static void hal_ioapic_init() |
---|
| 306 | { |
---|
| 307 | uint32_t ver; |
---|
[135] | 308 | size_t i; |
---|
[89] | 309 | |
---|
| 310 | ver = hal_ioapic_read(IOAPICVER); |
---|
[135] | 311 | ioapic_pins = ((ver >> 16) & 0xFF) + 1; |
---|
[89] | 312 | |
---|
| 313 | /* Explicitly disable (mask) each vector */ |
---|
[135] | 314 | for (i = 0; i < ioapic_pins; i++) { |
---|
[203] | 315 | hal_ioapic_disable_irq(i); |
---|
[89] | 316 | } |
---|
| 317 | |
---|
[135] | 318 | x86_printf("IOAPICPINS: #%z\n", ioapic_pins); |
---|
| 319 | |
---|
[152] | 320 | /* Now, enable the com1 port and the keyboard */ |
---|
[203] | 321 | hal_ioapic_bind_irq(IRQ_COM1, IOAPIC_COM1_VECTOR, 0); |
---|
| 322 | hal_ioapic_enable_irq(IRQ_COM1); |
---|
| 323 | hal_ioapic_bind_irq(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR, 0); |
---|
| 324 | hal_ioapic_enable_irq(IRQ_KEYBOARD); |
---|
[89] | 325 | } |
---|
| 326 | |
---|
| 327 | /* -------------------------------------------------------------------------- */ |
---|
| 328 | |
---|
[45] | 329 | paddr_t lapic_pa __in_kdata = 0; |
---|
| 330 | vaddr_t lapic_va __in_kdata = 0; |
---|
| 331 | |
---|
[46] | 332 | void hal_lapic_write(uint32_t reg, uint32_t val) |
---|
[45] | 333 | { |
---|
[82] | 334 | *((volatile uint32_t *)((uint8_t *)lapic_va + reg)) = val; |
---|
[45] | 335 | } |
---|
| 336 | |
---|
[46] | 337 | uint32_t hal_lapic_read(uint32_t reg) |
---|
[45] | 338 | { |
---|
[82] | 339 | return *((volatile uint32_t *)((uint8_t *)lapic_va + reg)); |
---|
[45] | 340 | } |
---|
| 341 | |
---|
[46] | 342 | uint32_t hal_lapic_gid() |
---|
[45] | 343 | { |
---|
[46] | 344 | return hal_lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT; |
---|
| 345 | } |
---|
[45] | 346 | |
---|
[82] | 347 | /* |
---|
[117] | 348 | * Use the PIT, which has a standard clock frequency, to determine the CPU's |
---|
| 349 | * exact bus frequency. |
---|
| 350 | */ |
---|
| 351 | static void hal_lapic_calibrate() |
---|
| 352 | { |
---|
| 353 | uint64_t pittick, lapictick0, lapictick1; |
---|
| 354 | uint32_t lapicticks, lapicstart; |
---|
| 355 | |
---|
| 356 | /* Initialize the LAPIC timer to the maximum value */ |
---|
[145] | 357 | hal_lapic_write(LAPIC_ICR_TIMER, 0xFFFFFFFF); |
---|
[117] | 358 | |
---|
[135] | 359 | /* Initialize the PIT */ |
---|
| 360 | hal_pit_init(); |
---|
| 361 | |
---|
[117] | 362 | pittick = hal_pit_timer_read() + 1; |
---|
| 363 | while (hal_pit_timer_read() < pittick) { |
---|
| 364 | /* Wait until start of a PIT tick */ |
---|
| 365 | } |
---|
| 366 | |
---|
| 367 | /* Read base count from LAPIC */ |
---|
| 368 | lapictick0 = hal_lapic_read(LAPIC_CCR_TIMER); |
---|
| 369 | |
---|
| 370 | while (hal_pit_timer_read() < pittick + (PIT_FREQUENCY + HZ/2) / HZ) { |
---|
| 371 | /* Wait 1/HZ sec = 10ms */ |
---|
| 372 | } |
---|
| 373 | |
---|
| 374 | /* Read final count from LAPIC */ |
---|
| 375 | lapictick1 = hal_lapic_read(LAPIC_CCR_TIMER); |
---|
| 376 | |
---|
| 377 | /* Total number of LAPIC ticks per 1/HZ tick */ |
---|
| 378 | lapicticks = (lapictick1 - lapictick0); |
---|
| 379 | |
---|
| 380 | /* Finally, calibrate the timer, an interrupt each 1s. */ |
---|
| 381 | lapicstart = - (lapicticks * 100); |
---|
| 382 | hal_lapic_write(LAPIC_ICR_TIMER, lapicstart); |
---|
| 383 | } |
---|
| 384 | |
---|
| 385 | /* |
---|
[82] | 386 | * We have 8 interrupt sources: |
---|
| 387 | * - Spurious |
---|
| 388 | * - APIC Timer (TMR) |
---|
| 389 | * - Local Interrupt 0 (LINT0) |
---|
| 390 | * - Local Interrupt 1 (LINT1) |
---|
| 391 | * - Performance Monitor Counters (PMC) |
---|
| 392 | * - Thermal Sensors (THM) |
---|
| 393 | * - APIC internal error (ERR) |
---|
| 394 | * - Extended (Implementation dependent) |
---|
[135] | 395 | * Only the Spurious and APIC Timer interrupts are enabled. |
---|
[82] | 396 | */ |
---|
| 397 | static void hal_lapic_init() |
---|
[46] | 398 | { |
---|
[82] | 399 | if ((rdmsr(MSR_APICBASE) & APICBASE_PHYSADDR) != lapic_pa) { |
---|
| 400 | x86_panic("APICBASE and ACPI don't match!\n"); |
---|
| 401 | } |
---|
| 402 | wrmsr(MSR_APICBASE, lapic_pa | APICBASE_EN); |
---|
| 403 | |
---|
[46] | 404 | hal_lapic_write(LAPIC_TPR, 0); |
---|
[82] | 405 | hal_lapic_write(LAPIC_EOI, 0); |
---|
[138] | 406 | hal_lapic_write(LAPIC_SVR, LAPIC_SVR_ENABLE|VECTOR_APIC_SPURIOU); |
---|
[82] | 407 | |
---|
| 408 | /* Explicitly disable (mask) each vector */ |
---|
| 409 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_M); |
---|
| 410 | hal_lapic_write(LAPIC_LVT_LINT0, LAPIC_LINT_M); |
---|
| 411 | hal_lapic_write(LAPIC_LVT_LINT1, LAPIC_LINT_M); |
---|
| 412 | hal_lapic_write(LAPIC_LVT_PMC, LAPIC_PMC_M); |
---|
| 413 | hal_lapic_write(LAPIC_LVT_THM, LAPIC_THM_M); |
---|
| 414 | hal_lapic_write(LAPIC_LVT_ERR, LAPIC_ERR_M); |
---|
[86] | 415 | |
---|
| 416 | /* Now, enable the timer in repeated mode. */ |
---|
| 417 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TMR_M); |
---|
| 418 | hal_lapic_write(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1); |
---|
[117] | 419 | hal_lapic_calibrate(); |
---|
[86] | 420 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TIMER_VECTOR); |
---|
[45] | 421 | } |
---|
| 422 | |
---|
[82] | 423 | /* -------------------------------------------------------------------------- */ |
---|
| 424 | |
---|
| 425 | void hal_apic_init() |
---|
| 426 | { |
---|
| 427 | /* Disable the PIC */ |
---|
| 428 | hal_pic_init(); |
---|
| 429 | |
---|
| 430 | /* Enable the LAPIC */ |
---|
| 431 | hal_lapic_init(); |
---|
[89] | 432 | |
---|
| 433 | /* Enable the IOAPIC */ |
---|
| 434 | hal_ioapic_init(); |
---|
[152] | 435 | |
---|
| 436 | /* Enable the Serial Port */ |
---|
| 437 | hal_com_init(); |
---|
[82] | 438 | } |
---|
| 439 | |
---|