[45] | 1 | /* |
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[82] | 2 | * hal_apic.c - Advanced Programmable Interrupt Controller |
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[45] | 3 | * |
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| 4 | * Copyright (c) 2017 Maxime Villard |
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| 5 | * |
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| 6 | * This file is part of ALMOS-MKH. |
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| 7 | * |
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| 8 | * ALMOS-MKH is free software; you can redistribute it and/or modify it |
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| 9 | * under the terms of the GNU General Public License as published by |
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| 10 | * the Free Software Foundation; version 2.0 of the License. |
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| 11 | * |
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| 12 | * ALMOS-MKH is distributed in the hope that it will be useful, but |
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| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 15 | * General Public License for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU General Public License |
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[234] | 18 | * along with ALMOS-MKH; if not, write to the Free Software Foundation, |
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[45] | 19 | * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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| 20 | */ |
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| 21 | |
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[457] | 22 | #include <hal_kernel_types.h> |
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[83] | 23 | #include <hal_boot.h> |
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[82] | 24 | #include <hal_register.h> |
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[45] | 25 | #include <hal_segmentation.h> |
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[82] | 26 | #include <hal_apic.h> |
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[45] | 27 | #include <hal_internal.h> |
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| 28 | |
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| 29 | #include <memcpy.h> |
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| 30 | #include <thread.h> |
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| 31 | #include <string.h> |
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| 32 | #include <process.h> |
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| 33 | #include <printk.h> |
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| 34 | #include <vmm.h> |
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| 35 | #include <core.h> |
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| 36 | #include <cluster.h> |
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| 37 | |
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[82] | 38 | /* -------------------------------------------------------------------------- */ |
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| 39 | |
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| 40 | #define PIC1_CMD 0x0020 |
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| 41 | #define PIC1_DATA 0x0021 |
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| 42 | #define PIC2_CMD 0x00a0 |
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| 43 | #define PIC2_DATA 0x00a1 |
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| 44 | |
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| 45 | static void hal_pic_init() |
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| 46 | { |
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| 47 | /* |
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| 48 | * Disable the PIC (8259A). We are going to use IOAPIC instead. |
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| 49 | */ |
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[327] | 50 | out8(PIC1_DATA, 0xFF); |
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| 51 | out8(PIC2_DATA, 0xFF); |
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[82] | 52 | } |
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| 53 | |
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| 54 | /* -------------------------------------------------------------------------- */ |
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| 55 | |
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[327] | 56 | static uint64_t pit_ticks_base __in_kdata = 0; |
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| 57 | static uint16_t pit_ticks_last __in_kdata = 0; |
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[117] | 58 | |
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| 59 | #define PIT_FREQUENCY 1193182 |
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| 60 | #define HZ 100 /* 1/HZ = 10ms */ |
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[235] | 61 | #define muHZ 1000000 /* 1/muHZ = 1 microsecond */ |
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[117] | 62 | |
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| 63 | #define PIT_TIMER0 0x40 |
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| 64 | |
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| 65 | #define PIT_CMD 0x43 |
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| 66 | # define CMD_BINARY 0x00 /* Use Binary counter values */ |
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| 67 | # define CMD_BCD 0x01 /* Use Binary Coded Decimal counter values */ |
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| 68 | # define CMD_MODE0 0x00 /* Interrupt on Terminal Count */ |
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| 69 | # define CMD_MODE1 0x02 /* Hardware Retriggerable One-Shot */ |
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| 70 | # define CMD_MODE2 0x04 /* Rate Generator */ |
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| 71 | # define CMD_MODE3 0x06 /* Square Wave */ |
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[327] | 72 | # define CMD_MODE4 0x08 /* Software Triggered Strobe */ |
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| 73 | # define CMD_MODE5 0x0a /* Hardware Triggered Strobe */ |
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[117] | 74 | # define CMD_LATCH 0x00 /* latch counter for reading */ |
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| 75 | # define CMD_LSB 0x10 /* LSB, 8 bits */ |
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| 76 | # define CMD_MSB 0x20 /* MSB, 8 bits */ |
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| 77 | # define CMD_16BIT 0x30 /* LSB and MSB, 16 bits */ |
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| 78 | # define CMD_COUNTER0 0x00 |
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| 79 | # define CMD_COUNTER1 0x40 |
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| 80 | # define CMD_COUNTER2 0x80 |
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| 81 | # define CMD_READBACK 0xc0 |
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| 82 | |
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[235] | 83 | void hal_pit_reset(uint16_t val) |
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[117] | 84 | { |
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[327] | 85 | uint8_t lo, hi; |
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| 86 | |
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[235] | 87 | pit_ticks_base = 0; |
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| 88 | |
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[327] | 89 | /* Set the initial counter value for clock 0. */ |
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[117] | 90 | out8(PIT_CMD, CMD_COUNTER0|CMD_MODE2|CMD_16BIT); |
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[235] | 91 | out8(PIT_TIMER0, (val >> 0) & 0xFF); |
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| 92 | out8(PIT_TIMER0, (val >> 8) & 0xFF); |
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[327] | 93 | |
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| 94 | /* |
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| 95 | * Read the current value, to initialize pit_ticks_last. Not extremely |
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| 96 | * accurate, but fine. |
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| 97 | */ |
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| 98 | out8(PIT_CMD, CMD_COUNTER0|CMD_LATCH); |
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| 99 | lo = in8(PIT_TIMER0); |
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| 100 | hi = in8(PIT_TIMER0); |
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| 101 | |
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| 102 | pit_ticks_last = (hi << 8) | lo; |
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[117] | 103 | } |
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| 104 | |
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| 105 | uint64_t |
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[482] | 106 | hal_pit_timer_read( void ) |
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[117] | 107 | { |
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| 108 | uint8_t lo, hi; |
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| 109 | uint16_t ctr; |
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| 110 | uint64_t ticks; |
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| 111 | |
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| 112 | /* Read the current timer counter. */ |
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| 113 | out8(PIT_CMD, CMD_COUNTER0|CMD_LATCH); |
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| 114 | lo = in8(PIT_TIMER0); |
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| 115 | hi = in8(PIT_TIMER0); |
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| 116 | ctr = (hi << 8) | lo; |
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| 117 | |
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[327] | 118 | /* If the counter has overflown, assume we're into the next tick. */ |
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| 119 | if (ctr > pit_ticks_last) |
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[117] | 120 | pit_ticks_base += 0xFFFF; |
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[327] | 121 | pit_ticks_last = ctr; |
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[117] | 122 | |
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| 123 | ticks = pit_ticks_base + (0xFFFF - ctr); |
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| 124 | |
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| 125 | return ticks; |
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| 126 | } |
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| 127 | |
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[235] | 128 | /* |
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| 129 | * Wait approximately n microseconds. |
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| 130 | */ |
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| 131 | void |
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| 132 | hal_pit_delay(uint64_t n) |
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| 133 | { |
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| 134 | uint64_t nticks; |
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| 135 | |
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| 136 | nticks = 0; |
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[327] | 137 | hal_pit_reset(0xFFFF); |
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[235] | 138 | |
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| 139 | while (n > 0) { |
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| 140 | while (hal_pit_timer_read() - nticks < (PIT_FREQUENCY + muHZ/2) / muHZ) { |
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| 141 | /* Wait 1/muHZ sec = 1 microsecond */ |
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| 142 | } |
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[327] | 143 | nticks++; // ??? |
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[235] | 144 | n--; |
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| 145 | } |
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| 146 | } |
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| 147 | |
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[117] | 148 | /* -------------------------------------------------------------------------- */ |
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| 149 | |
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[152] | 150 | #define BAUDRATE 19200 |
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| 151 | #define BAUDRATE_DIV (115200 / BAUDRATE) |
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| 152 | |
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| 153 | #define RS232_COM1_BASE 0x3F8 |
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| 154 | |
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| 155 | #define RS232_DATA 0x00 |
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| 156 | #define RS232_IER 0x01 |
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| 157 | # define IER_RD 0x01 |
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| 158 | # define IER_TBE 0x02 |
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| 159 | # define IER_ER_BRK 0x04 |
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| 160 | # define IER_RS232IN 0x08 |
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| 161 | #define RS232_DIVLO 0x00 /* when DLAB = 1 */ |
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| 162 | #define RS232_DIVHI 0x01 /* when DLAB = 1 */ |
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| 163 | #define RS232_IIR 0x02 |
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| 164 | #define RS232_LCR 0x03 |
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| 165 | # define LCR_DATA5 0x00 |
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| 166 | # define LCR_DATA6 0x01 |
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| 167 | # define LCR_DATA7 0x02 |
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| 168 | # define LCR_DATA8 0x03 |
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| 169 | # define LCR_TWOSTOP 0x04 |
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| 170 | # define LCR_PARITY 0x08 |
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| 171 | # define LCR_EVEN 0x10 |
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| 172 | # define LCR_STICK 0x20 |
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| 173 | # define LCR_DLAB 0x80 |
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| 174 | #define RS232_MCR 0x04 |
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| 175 | # define MCR_DTR 0x01 |
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| 176 | # define MCR_RTS 0x02 |
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| 177 | # define MCR_ELL 0x04 |
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| 178 | # define MCR_IR 0x40 |
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| 179 | #define RS232_LSR 0x05 |
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| 180 | # define LSR_DR 0x01 |
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| 181 | # define LSR_OVR 0x02 |
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| 182 | # define LSR_PE 0x04 |
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| 183 | # define LSR_FE 0x08 |
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| 184 | # define LSR_BRK 0x10 |
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| 185 | # define LSR_TBE 0x20 |
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| 186 | # define LSR_TE 0x40 |
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| 187 | #define RS232_MSR 0x06 |
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| 188 | # define MSR_DCTS 0x01 |
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| 189 | # define MSR_DDSR 0x02 |
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| 190 | # define MSR_DRI 0x04 |
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| 191 | # define MSR_DDCD 0x08 |
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| 192 | # define MSR_CTS 0x10 |
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| 193 | # define MSR_DSR 0x20 |
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| 194 | # define MSR_RI 0x40 |
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| 195 | # define MSR_DCD 0x80 |
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| 196 | |
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| 197 | #define RS232_SCRATCH 0x07 |
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| 198 | |
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[482] | 199 | static bool_t hal_com_received( void ) |
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[152] | 200 | { |
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| 201 | return (in8(RS232_COM1_BASE + RS232_LSR) & LSR_DR) != 0; |
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| 202 | } |
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| 203 | |
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[482] | 204 | static bool_t hal_com_transmit_empty( void ) |
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[152] | 205 | { |
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| 206 | return (in8(RS232_COM1_BASE + RS232_LSR) & LSR_TBE) != 0; |
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| 207 | } |
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| 208 | |
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[482] | 209 | char hal_com_read( void ) |
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[152] | 210 | { |
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| 211 | while (!hal_com_received()); |
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| 212 | return in8(RS232_COM1_BASE + RS232_DATA); |
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| 213 | } |
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| 214 | |
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[154] | 215 | void hal_com_send(uint8_t chan, char c) |
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[152] | 216 | { |
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| 217 | uint8_t mcr = in8(RS232_COM1_BASE + RS232_MCR); |
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| 218 | out8(RS232_COM1_BASE + RS232_MCR, mcr | MCR_RTS); |
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| 219 | |
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| 220 | while (!hal_com_transmit_empty()); |
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[154] | 221 | out8(RS232_COM1_BASE + RS232_DATA, chan | 0x80); |
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[152] | 222 | out8(RS232_COM1_BASE + RS232_DATA, c); |
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| 223 | |
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| 224 | out8(RS232_COM1_BASE + RS232_MCR, mcr); |
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| 225 | } |
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| 226 | |
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[154] | 227 | /* |
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| 228 | * Called early to provide x86-specific messages. Interrupts disabled. |
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| 229 | */ |
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[482] | 230 | void hal_com_init_early( void ) |
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[154] | 231 | { |
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| 232 | /* Disable all interrupts */ |
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| 233 | out8(RS232_COM1_BASE + RS232_IER, 0x00); |
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| 234 | |
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| 235 | /* Set baudrate */ |
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| 236 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DLAB); |
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| 237 | out8(RS232_COM1_BASE + RS232_DIVLO, BAUDRATE_DIV); |
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| 238 | out8(RS232_COM1_BASE + RS232_DIVHI, 0); |
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| 239 | |
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| 240 | /* 8bits, no parity, one stop bit */ |
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| 241 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DATA8); |
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| 242 | |
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| 243 | /* DTR set, and also DSR */ |
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| 244 | out8(RS232_COM1_BASE + RS232_MCR, MCR_DTR|MCR_IR); |
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| 245 | out8(RS232_COM1_BASE + RS232_MSR, MSR_DSR); |
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| 246 | } |
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| 247 | |
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[482] | 248 | static void hal_com_init( void ) |
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[152] | 249 | { |
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| 250 | /* Disable all interrupts */ |
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| 251 | out8(RS232_COM1_BASE + RS232_IER, 0x00); |
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| 252 | |
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| 253 | /* Set baudrate */ |
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| 254 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DLAB); |
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| 255 | out8(RS232_COM1_BASE + RS232_DIVLO, BAUDRATE_DIV); |
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| 256 | out8(RS232_COM1_BASE + RS232_DIVHI, 0); |
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| 257 | |
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| 258 | /* 8bits, no parity, one stop bit */ |
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| 259 | out8(RS232_COM1_BASE + RS232_LCR, LCR_DATA8); |
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| 260 | |
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| 261 | /* Enable IRQs, DTR set, and also DSR */ |
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| 262 | out8(RS232_COM1_BASE + RS232_IER, IER_RD|IER_RS232IN); |
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| 263 | out8(RS232_COM1_BASE + RS232_MCR, MCR_DTR|MCR_IR); |
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| 264 | out8(RS232_COM1_BASE + RS232_MSR, MSR_DSR); |
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| 265 | } |
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| 266 | |
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| 267 | /* -------------------------------------------------------------------------- */ |
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| 268 | |
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[135] | 269 | size_t ioapic_pins __in_kdata = 0; |
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[89] | 270 | paddr_t ioapic_pa __in_kdata = 0; |
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| 271 | vaddr_t ioapic_va __in_kdata = 0; |
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| 272 | |
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| 273 | #define IOREGSEL 0x00 |
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| 274 | #define IOWIN 0x10 |
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| 275 | |
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| 276 | #define IOAPICID 0x00 |
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| 277 | #define IOAPICVER 0x01 |
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| 278 | #define IOAPICARB 0x02 |
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[137] | 279 | |
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[89] | 280 | #define IOREDTBL 0x10 |
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[137] | 281 | # define IOREDTBL_DEL_FIXED 0x000 |
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| 282 | # define IOREDTBL_DEL_LOPRI 0x100 |
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| 283 | # define IOREDTBL_DEL_SMI 0x200 |
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| 284 | # define IOREDTBL_DEL_NMI 0x400 |
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| 285 | # define IOREDTBL_DEL_INIT 0x500 |
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| 286 | # define IOREDTBL_DEL_EXTINT 0x700 |
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| 287 | # define IOREDTBL_DEM_PHYS 0x000 |
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| 288 | # define IOREDTBL_DEM_LOGIC 0x800 |
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| 289 | # define IOREDTBL_DES_SHIFT 56 |
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| 290 | # define IOREDTBL_MSK 0x10000 |
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[89] | 291 | |
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| 292 | void hal_ioapic_write(uint8_t reg, uint32_t val) |
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| 293 | { |
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| 294 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
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| 295 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)) = val; |
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| 296 | } |
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| 297 | |
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| 298 | uint32_t hal_ioapic_read(uint8_t reg) |
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| 299 | { |
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| 300 | *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg; |
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| 301 | return *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)); |
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| 302 | } |
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| 303 | |
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[203] | 304 | void hal_ioapic_bind_irq(uint8_t irq, uint8_t vec, uint8_t dest) |
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[89] | 305 | { |
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[203] | 306 | const uint64_t data = ((uint64_t)dest << IOREDTBL_DES_SHIFT) | |
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| 307 | IOREDTBL_DEM_PHYS | IOREDTBL_DEL_FIXED | IOREDTBL_MSK | vec; |
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[137] | 308 | |
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[203] | 309 | hal_ioapic_write(IOREDTBL + irq * 2, (uint32_t)(data & 0xFFFFFFFF)); |
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| 310 | hal_ioapic_write(IOREDTBL + irq * 2 + 1, (uint32_t)(data >> 32)); |
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[89] | 311 | } |
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| 312 | |
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[203] | 313 | void hal_ioapic_enable_irq(uint8_t irq) |
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[137] | 314 | { |
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[203] | 315 | uint32_t data[2]; |
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[137] | 316 | |
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[203] | 317 | data[0] = hal_ioapic_read(IOREDTBL + irq * 2); |
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| 318 | data[1] = hal_ioapic_read(IOREDTBL + irq * 2 + 1); |
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| 319 | |
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| 320 | data[0] &= ~IOREDTBL_MSK; |
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| 321 | |
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| 322 | hal_ioapic_write(IOREDTBL + irq * 2, data[0]); |
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| 323 | hal_ioapic_write(IOREDTBL + irq * 2 + 1, data[1]); |
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[137] | 324 | } |
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| 325 | |
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[203] | 326 | void hal_ioapic_disable_irq(uint8_t irq) |
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| 327 | { |
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| 328 | uint32_t data[2]; |
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| 329 | |
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| 330 | data[0] = hal_ioapic_read(IOREDTBL + irq * 2); |
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| 331 | data[1] = hal_ioapic_read(IOREDTBL + irq * 2 + 1); |
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| 332 | |
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| 333 | data[0] |= IOREDTBL_MSK; |
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| 334 | |
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| 335 | hal_ioapic_write(IOREDTBL + irq * 2, data[0]); |
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| 336 | hal_ioapic_write(IOREDTBL + irq * 2 + 1, data[1]); |
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| 337 | } |
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| 338 | |
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[482] | 339 | static void hal_ioapic_init( void ) |
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[89] | 340 | { |
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| 341 | uint32_t ver; |
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[135] | 342 | size_t i; |
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[89] | 343 | |
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| 344 | ver = hal_ioapic_read(IOAPICVER); |
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[135] | 345 | ioapic_pins = ((ver >> 16) & 0xFF) + 1; |
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[89] | 346 | |
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| 347 | /* Explicitly disable (mask) each vector */ |
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[135] | 348 | for (i = 0; i < ioapic_pins; i++) { |
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[203] | 349 | hal_ioapic_disable_irq(i); |
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[89] | 350 | } |
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| 351 | |
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[135] | 352 | x86_printf("IOAPICPINS: #%z\n", ioapic_pins); |
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| 353 | |
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[152] | 354 | /* Now, enable the com1 port and the keyboard */ |
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[203] | 355 | hal_ioapic_bind_irq(IRQ_COM1, IOAPIC_COM1_VECTOR, 0); |
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| 356 | hal_ioapic_enable_irq(IRQ_COM1); |
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| 357 | hal_ioapic_bind_irq(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR, 0); |
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| 358 | hal_ioapic_enable_irq(IRQ_KEYBOARD); |
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[89] | 359 | } |
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| 360 | |
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| 361 | /* -------------------------------------------------------------------------- */ |
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| 362 | |
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[45] | 363 | paddr_t lapic_pa __in_kdata = 0; |
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| 364 | vaddr_t lapic_va __in_kdata = 0; |
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| 365 | |
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[46] | 366 | void hal_lapic_write(uint32_t reg, uint32_t val) |
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[45] | 367 | { |
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[82] | 368 | *((volatile uint32_t *)((uint8_t *)lapic_va + reg)) = val; |
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[45] | 369 | } |
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| 370 | |
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[46] | 371 | uint32_t hal_lapic_read(uint32_t reg) |
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[45] | 372 | { |
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[82] | 373 | return *((volatile uint32_t *)((uint8_t *)lapic_va + reg)); |
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[45] | 374 | } |
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| 375 | |
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[482] | 376 | uint32_t hal_lapic_gid( void ) |
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[45] | 377 | { |
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[46] | 378 | return hal_lapic_read(LAPIC_ID) >> LAPIC_ID_SHIFT; |
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| 379 | } |
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[45] | 380 | |
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[482] | 381 | static void hal_lapic_icr_wait( void ) |
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[235] | 382 | { |
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| 383 | while ((hal_lapic_read(LAPIC_ICRLO) & LAPIC_DLSTAT_BUSY) != 0) { |
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| 384 | pause(); |
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| 385 | } |
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| 386 | } |
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| 387 | |
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[82] | 388 | /* |
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[117] | 389 | * Use the PIT, which has a standard clock frequency, to determine the CPU's |
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| 390 | * exact bus frequency. |
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| 391 | */ |
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[482] | 392 | static void hal_lapic_calibrate( void ) |
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[117] | 393 | { |
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| 394 | uint64_t pittick, lapictick0, lapictick1; |
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| 395 | uint32_t lapicticks, lapicstart; |
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| 396 | |
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| 397 | /* Initialize the LAPIC timer to the maximum value */ |
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[145] | 398 | hal_lapic_write(LAPIC_ICR_TIMER, 0xFFFFFFFF); |
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[117] | 399 | |
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[235] | 400 | /* Reset the PIT */ |
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[327] | 401 | hal_pit_reset(0xFFFF); |
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[135] | 402 | |
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[117] | 403 | pittick = hal_pit_timer_read() + 1; |
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| 404 | while (hal_pit_timer_read() < pittick) { |
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| 405 | /* Wait until start of a PIT tick */ |
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| 406 | } |
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| 407 | |
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| 408 | /* Read base count from LAPIC */ |
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| 409 | lapictick0 = hal_lapic_read(LAPIC_CCR_TIMER); |
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| 410 | |
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| 411 | while (hal_pit_timer_read() < pittick + (PIT_FREQUENCY + HZ/2) / HZ) { |
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| 412 | /* Wait 1/HZ sec = 10ms */ |
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| 413 | } |
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| 414 | |
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| 415 | /* Read final count from LAPIC */ |
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| 416 | lapictick1 = hal_lapic_read(LAPIC_CCR_TIMER); |
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| 417 | |
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[327] | 418 | if (lapictick1 > lapictick0) |
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| 419 | x86_panic("LAPIC tick overflow!"); |
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| 420 | |
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[117] | 421 | /* Total number of LAPIC ticks per 1/HZ tick */ |
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[327] | 422 | lapicticks = (lapictick0 - lapictick1); |
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[117] | 423 | |
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[327] | 424 | /* |
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| 425 | * Finally, calibrate the timer, with an interrupt each 1s (10ms * 100). |
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| 426 | */ |
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| 427 | lapicstart = (lapicticks * 100); |
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[117] | 428 | hal_lapic_write(LAPIC_ICR_TIMER, lapicstart); |
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[327] | 429 | x86_printf("-> lapicticks: %z\n", (uint64_t)lapicticks); |
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[117] | 430 | } |
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| 431 | |
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| 432 | /* |
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[82] | 433 | * We have 8 interrupt sources: |
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| 434 | * - Spurious |
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| 435 | * - APIC Timer (TMR) |
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| 436 | * - Local Interrupt 0 (LINT0) |
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| 437 | * - Local Interrupt 1 (LINT1) |
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| 438 | * - Performance Monitor Counters (PMC) |
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| 439 | * - Thermal Sensors (THM) |
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| 440 | * - APIC internal error (ERR) |
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| 441 | * - Extended (Implementation dependent) |
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[135] | 442 | * Only the Spurious and APIC Timer interrupts are enabled. |
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[82] | 443 | */ |
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[482] | 444 | void cpu_lapic_init( void ) |
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[46] | 445 | { |
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[82] | 446 | if ((rdmsr(MSR_APICBASE) & APICBASE_PHYSADDR) != lapic_pa) { |
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| 447 | x86_panic("APICBASE and ACPI don't match!\n"); |
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| 448 | } |
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| 449 | wrmsr(MSR_APICBASE, lapic_pa | APICBASE_EN); |
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| 450 | |
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[46] | 451 | hal_lapic_write(LAPIC_TPR, 0); |
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[82] | 452 | hal_lapic_write(LAPIC_EOI, 0); |
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[138] | 453 | hal_lapic_write(LAPIC_SVR, LAPIC_SVR_ENABLE|VECTOR_APIC_SPURIOU); |
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[82] | 454 | |
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| 455 | /* Explicitly disable (mask) each vector */ |
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| 456 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_M); |
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| 457 | hal_lapic_write(LAPIC_LVT_LINT0, LAPIC_LINT_M); |
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| 458 | hal_lapic_write(LAPIC_LVT_LINT1, LAPIC_LINT_M); |
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| 459 | hal_lapic_write(LAPIC_LVT_PMC, LAPIC_PMC_M); |
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| 460 | hal_lapic_write(LAPIC_LVT_THM, LAPIC_THM_M); |
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| 461 | hal_lapic_write(LAPIC_LVT_ERR, LAPIC_ERR_M); |
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[86] | 462 | |
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| 463 | /* Now, enable the timer in repeated mode. */ |
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| 464 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TMR_M); |
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| 465 | hal_lapic_write(LAPIC_DCR_TIMER, LAPIC_DCRT_DIV1); |
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[117] | 466 | hal_lapic_calibrate(); |
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[86] | 467 | hal_lapic_write(LAPIC_LVT_TMR, LAPIC_TMR_TM|LAPIC_TIMER_VECTOR); |
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[45] | 468 | } |
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| 469 | |
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[82] | 470 | /* -------------------------------------------------------------------------- */ |
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| 471 | |
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[235] | 472 | static void |
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| 473 | hal_ipi_init(uint32_t gid) |
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| 474 | { |
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| 475 | /* clear the error status */ |
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| 476 | hal_lapic_write(LAPIC_ESR, 0); |
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| 477 | (void)hal_lapic_read(LAPIC_ESR); |
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| 478 | |
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| 479 | /* send the IPI */ |
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| 480 | hal_lapic_write(LAPIC_ICRHI, gid << LAPIC_ID_SHIFT); |
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| 481 | hal_lapic_write(LAPIC_ICRLO, LAPIC_DLMODE_INIT | LAPIC_LEVEL_ASSERT); |
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| 482 | hal_lapic_icr_wait(); |
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| 483 | |
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| 484 | /* wait 10ms */ |
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| 485 | hal_pit_delay(10000); |
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| 486 | |
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| 487 | hal_lapic_write(LAPIC_ICRLO, |
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| 488 | LAPIC_DLMODE_INIT | LAPIC_TRIGGER_LEVEL | LAPIC_LEVEL_DEASSERT); |
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| 489 | hal_lapic_icr_wait(); |
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| 490 | } |
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| 491 | |
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| 492 | static void |
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| 493 | hal_ipi_startup(uint32_t gid, paddr_t pa) |
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| 494 | { |
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| 495 | /* clear the error status */ |
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| 496 | hal_lapic_write(LAPIC_ESR, 0); |
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| 497 | (void)hal_lapic_read(LAPIC_ESR); |
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| 498 | |
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| 499 | /* send the IPI */ |
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| 500 | hal_lapic_icr_wait(); |
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| 501 | hal_lapic_write(LAPIC_ICRHI, gid << LAPIC_ID_SHIFT); |
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| 502 | hal_lapic_write(LAPIC_ICRLO, pa | LAPIC_DLMODE_STARTUP | |
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| 503 | LAPIC_LEVEL_ASSERT); |
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| 504 | hal_lapic_icr_wait(); |
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| 505 | } |
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| 506 | |
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| 507 | /* -------------------------------------------------------------------------- */ |
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| 508 | |
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| 509 | int |
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[236] | 510 | boot_cpuN(uint32_t gid, paddr_t pa) |
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[235] | 511 | { |
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| 512 | /* |
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| 513 | * Bootstrap code must be addressable in real mode and it must be |
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| 514 | * page-aligned. |
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| 515 | */ |
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| 516 | XASSERT(pa < 0x10000 && pa % PAGE_SIZE == 0); |
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| 517 | |
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| 518 | /* |
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| 519 | * Local cache flush, in case the BIOS has left the AP with its cache |
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| 520 | * disabled. It may not be able to cope with MP coherency. |
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| 521 | */ |
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| 522 | wbinvd(); |
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| 523 | |
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| 524 | hal_ipi_init(gid); |
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| 525 | hal_pit_delay(10000); |
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| 526 | |
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| 527 | hal_ipi_startup(gid, pa / PAGE_SIZE); |
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| 528 | hal_pit_delay(200); |
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| 529 | |
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| 530 | hal_ipi_startup(gid, pa / PAGE_SIZE); |
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| 531 | hal_pit_delay(200); |
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| 532 | |
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| 533 | return 0; |
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| 534 | } |
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| 535 | |
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| 536 | /* -------------------------------------------------------------------------- */ |
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| 537 | |
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[482] | 538 | void hal_apic_init( void ) |
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[82] | 539 | { |
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| 540 | /* Disable the PIC */ |
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| 541 | hal_pic_init(); |
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| 542 | |
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[89] | 543 | /* Enable the IOAPIC */ |
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| 544 | hal_ioapic_init(); |
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[152] | 545 | |
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| 546 | /* Enable the Serial Port */ |
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| 547 | hal_com_init(); |
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[82] | 548 | } |
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| 549 | |
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