Changeset 137 for trunk

Timestamp:

Jul 4, 2017, 10:17:44 AM (7 years ago)

Author:

max@…

Message:

improve the APIC implementation

Location:

trunk/hal/x86_64

Files:

• core/hal_apic.c (modified) (4 diffs)
• core/hal_apic.h (modified) (2 diffs)
• core/hal_drivers.c (modified) (2 diffs)
• core/hal_init.c (modified) (3 diffs)
• drivers/soclib_xcu.c (modified) (4 diffs)

trunk/hal/x86_64/core/hal_apic.c

@@ -132 +132 @@
 #define IOAPICVER       0x01
 #define IOAPICARB       0x02
+
 #define IOREDTBL        0x10
+#       define IOREDTBL_DEL_FIXED       0x000
+#       define IOREDTBL_DEL_LOPRI       0x100
+#       define IOREDTBL_DEL_SMI         0x200
+#       define IOREDTBL_DEL_NMI         0x400
+#       define IOREDTBL_DEL_INIT        0x500
+#       define IOREDTBL_DEL_EXTINT      0x700
+#       define IOREDTBL_DEM_PHYS        0x000
+#       define IOREDTBL_DEM_LOGIC       0x800
+#       define IOREDTBL_DES_SHIFT       56
+#       define IOREDTBL_MSK             0x10000
 
 void hal_ioapic_write(uint8_t reg, uint32_t val)
@@ -146 +157 @@
 }
 
-void hal_ioapic_set_entry(uint8_t index, uint64_t data)
-{
+void hal_ioapic_disable_entry(uint8_t index)
+{
+        const uint64_t data = IOREDTBL_MSK;
+
         hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF));
         hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32));
 }
 
+void hal_ioapic_set_entry(uint8_t index, uint8_t vec, uint8_t dest)
+{
+        const uint64_t data = ((uint64_t)dest << IOREDTBL_DES_SHIFT) |
+            IOREDTBL_DEM_PHYS | IOREDTBL_DEL_FIXED | vec;
+
+        hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF));
+        hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32));
+}
+
 static void hal_ioapic_init()
 {
@@ -166 +188 @@
         /* Explicitly disable (mask) each vector */
         for (i = 0; i < ioapic_pins; i++) {
-                hal_ioapic_set_entry(i, IOENTRY_DISABLE);
+                hal_ioapic_disable_entry(i);
         }
 
@@ -172 +194 @@
 
         /* Now, enable the keyboard */
-        hal_ioapic_set_entry(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR);
+        hal_ioapic_set_entry(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR, 0);
 }
 

trunk/hal/x86_64/core/hal_apic.h

@@ -21 +21 @@
 
 #ifndef x86_ASM
-void hal_ioapic_set_entry(uint8_t index, uint64_t data);
+void hal_ioapic_disable_entry(uint8_t index);
+void hal_ioapic_set_entry(uint8_t index, uint8_t vec, uint8_t dest);
 
 uint32_t hal_lapic_gid();
@@ -33 +34 @@
  */
 
-#define IOENTRY_DISABLE 0x10000
+
 
 

trunk/hal/x86_64/core/hal_drivers.c

@@ -43 +43 @@
     uint32_t irq_type, lid_t lid)
 {
-        soclib_xcu_disable_irq(icu, 1 << irq_index, irq_type, lid);
+        soclib_xcu_disable_irq(icu, irq_index, irq_type, lid);
 }
 
@@ -49 +49 @@
     uint32_t irq_type, lid_t lid)
 {
-        soclib_xcu_enable_irq(icu, 1 << irq_index, irq_type, lid);
+        soclib_xcu_enable_irq(icu, irq_index, irq_type, lid);
 }
 

trunk/hal/x86_64/core/hal_init.c

@@ -84 +84 @@
 static void init_bootinfo_icu(boot_device_t *dev)
 {
+        extern uint32_t hwi_baseidx;
+        extern uint32_t wti_baseidx;
+        extern uint32_t pti_baseidx;
+        extern size_t ioapic_pins;
+
         memset(dev, 0, sizeof(boot_device_t));
 
-        dev->base = NULL; /* XXX */
+        dev->base = 0;
         dev->type = (DEV_FUNC_ICU << 16) | IMPL_ICU_XCU;
         dev->channels = 1;
-        dev->param0 = 0;
-        dev->param1 = 0;
-        dev->param2 = 0;
+
+        /*
+         * Give 20% of the pins to HWI, 80% to WTI.
+         */
+        dev->param0 = (ioapic_pins * 20) / 100;  /* hwi_nr */
+        dev->param1 = ioapic_pins - dev->param0; /* wti_nr */
+
+        /*
+         * We always set 1 for pti_nr. On x86, timer interrupts are handled by
+         * LAPIC, which is per-cpu and not global. Therefore, we always have one
+         * timer for each CPU, and its IRQ number is faked to 0.
+         */
+        dev->param2 = 1; /* pti_nr */
+
         dev->param3 = 0;
+
+        /* Set the base idx for the XCU driver */
+        hwi_baseidx = 0;
+        wti_baseidx = dev->param0;
+        pti_baseidx = 0xFFFFFFFF;
 
 #ifdef NOTYET
@@ -132 +153 @@
         size_t i, rsvd_nr;
 
-        memset(rsvd, 0, sizeof(boot_rsvd_t));
+        memset(rsvd, 0, sizeof(boot_rsvd_t) * CONFIG_PPM_MAX_RSVD);
 
         i = 0, rsvd_nr = 0;
@@ -208 +229 @@
         init_bootinfo_core(&info->core[0]);
 
-        info->rsvd_nr = init_bootinfo_rsvd(&info->rsvd);
+        info->rsvd_nr = init_bootinfo_rsvd((boot_rsvd_t *)&info->rsvd);
 
         init_bootinfo_icu(&info->dev_icu);

trunk/hal/x86_64/drivers/soclib_xcu.c

@@ -32 +32 @@
 extern size_t ioapic_pins;
 
+uint64_t apic_fake_status __in_kdata = 0;
+
+/*
+ * These indexes are used to translate a type::idx to a pin on the IOAPIC.
+ */
+uint32_t hwi_baseidx __in_kdata = 0;
+uint32_t wti_baseidx __in_kdata = 0;
+uint32_t pti_baseidx __in_kdata = 0;
+
 void soclib_xcu_init(chdev_t *icu, lid_t lid)
 {
@@ -38 +47 @@
         /* disable all IRQs */
         for (i = 0; i < ioapic_pins; i++) {
-                hal_ioapic_set_entry(i, IOENTRY_DISABLE);
+                hal_ioapic_disable_entry(i);
         }
 
@@ -44 +53 @@
 }
 
-void soclib_xcu_disable_irq( chdev_t  * icu,
-                             uint32_t   mask,
-                             uint32_t   type,
-                             lid_t      lid )
+void soclib_xcu_enable_irq(chdev_t *icu, uint32_t idx, uint32_t type,
+    lid_t lid)
 {
+        uint32_t pin;
+
+        switch (type) {
+                case HWI_TYPE:
+                        pin = hwi_baseidx + idx;
+                case WTI_TYPE:
+                        pin = wti_baseidx + idx;
+                case PTI_TYPE:
+                        pin = pti_baseidx + idx;
+                default:
+                        x86_panic("enabling wrong irq");
+        }
+
         x86_panic((char *)__func__);
 }
 
-void soclib_xcu_enable_irq( chdev_t  * icu,
-                            uint32_t   mask,
-                            uint32_t   type,
-                            lid_t      lid )
+void soclib_xcu_disable_irq(chdev_t *icu, uint32_t idx, uint32_t type,
+    lid_t lid)
 {
         x86_panic((char *)__func__);
@@ -83 +101 @@
 }
 
-void soclib_xcu_get_status( chdev_t  * icu,
-                            lid_t      lid,
-                            uint32_t * hwi_status,
-                            uint32_t * wti_status,
-                            uint32_t * pti_status )
+
+
+
+
+void soclib_xcu_get_status(chdev_t *icu, lid_t lid, uint32_t *hwi_status,
+    uint32_t *wti_status, uint32_t *pti_status)
 {
+        if (lid != 0) {
+                x86_panic("xcu_get_status should have lid==0");
+        }
+
         x86_panic((char *)__func__);
 }
+
+
+
+
+
 
 void soclib_xcu_send_ipi( xptr_t  icu_xp,