Changeset 166

Timestamp:

Jul 10, 2017, 10:14:27 AM (7 years ago)

Author:

max@…

Message:

identify the cpu features

Location:

trunk/hal/x86_64/core

Files:

• hal_cpu.S (modified) (2 diffs)
• hal_init.c (modified) (6 diffs)
• hal_internal.h (modified) (2 diffs)
• hal_register.h (modified) (1 diff)

trunk/hal/x86_64/core/hal_cpu.S

@@ -23 +23 @@
 #include <hal_boot.h>
 #include <hal_segmentation.h>
+#include <hal_register.h>
 
 ASM_ENTRY(lgdt)
@@ -99 +100 @@
         ret
 
+ASM_ENTRY(rcr4)
+        movq    %cr4,%rax
+        ret
+
+ASM_ENTRY(lcr4)
+        movq    %rdi,%cr4
+        ret
+
+ASM_ENTRY(cpuid)
+        movq    %rbx,%r8
+        movq    %rdi,%rax
+        movq    %rsi,%rcx
+        movq    %rdx,%rsi
+        cpuid
+        movl    %eax,0(%rsi)
+        movl    %ebx,4(%rsi)
+        movl    %ecx,8(%rsi)
+        movl    %edx,12(%rsi)
+        movq    %r8,%rbx
+        ret
+
+/*
+ * To flush all TLB entries, we must re-set the CR4_PGE flag in %cr4.
+ */
+ASM_ENTRY(tlbflushg)
+        movq    %cr4,%rax
+        movq    %rax,%rdx
+        andq    $~CR4_PGE,%rdx
+        movq    %rdx,%cr4
+        movq    %rax,%cr4
+        ret
+
+ASM_ENTRY(tlbflush)
+        movq    %cr3,%rax
+        movq    %rax,%cr3
+        ret
+
 ASM_ENTRY(x86_stop) /* debug only */
         int     $0x0b

trunk/hal/x86_64/core/hal_init.c

@@ -27 +27 @@
 #include <hal_apic.h>
 #include <hal_internal.h>
+#include <hal_register.h>
+
 #include <hal_remote.h>
 #include <hal_irqmask.h>
@@ -46 +48 @@
 static void gdt_create();
 static void idt_create();
+void cpu_identify();
 void cpu_attach();
 
@@ -250 +253 @@
 }
 
+/* -------------------------------------------------------------------------- */
+
 void init_x86_64(paddr_t firstpa)
 {
@@ -262 +267 @@
         gdt_create();
         idt_create();
+
+        /* Identify the features of the cpu */
+        cpu_identify();
 
         /* Attach cpu0 */
@@ -477 +485 @@
 /* -------------------------------------------------------------------------- */
 
+uint64_t cpu_features[4] __in_kdata;
+
+void cpu_identify()
+{
+        /*
+         * desc[0] = eax
+         * desc[1] = ebx
+         * desc[2] = ecx
+         * desc[3] = edx
+         */
+        uint32_t desc[4];
+        char vendor[13];
+        size_t lvl;
+
+        /*
+         * Get information from the standard cpuid leafs
+         */
+        cpuid(0, 0, (uint32_t *)&desc);
+
+        lvl = (uint64_t)desc[0];
+        x86_printf("-> cpuid standard level: %z\n", lvl);
+
+        memcpy(vendor + 0, &desc[1], sizeof(uint32_t));
+        memcpy(vendor + 8, &desc[2], sizeof(uint32_t));
+        memcpy(vendor + 4, &desc[3], sizeof(uint32_t));
+        vendor[12] = '\0';
+        x86_printf("-> CPU vendor: '%s'\n", vendor);
+
+        if (lvl >= 1) {
+                cpuid(1, 0, (uint32_t *)&desc);
+                cpu_features[0] = desc[3];
+                cpu_features[1] = desc[2];
+        }
+
+        /*
+         * Get information from the extended cpuid leafs
+         */
+        cpuid(0x80000000, 0, desc);
+
+        lvl = (uint64_t)desc[0];
+        x86_printf("-> cpuid extended level: %Z\n", lvl);
+}
+
+/* -------------------------------------------------------------------------- */
+
 void cpu_attach(size_t lid)
 {
@@ -482 +535 @@
         cpu_load_idt();
         cpu_create_tss(lid);
-}
-
+
+        if (cpu_features[0] & CPUID_PSE) {
+                lcr4(rcr4() | CR4_PSE);
+                tlbflushg();
+        } else {
+                /*
+                 * amd64 supports PSE by default, if it's not here we have a
+                 * problem
+                 */
+                x86_panic("PSE not supported");
+        }
+}
+

trunk/hal/x86_64/core/hal_internal.h

@@ -16 +16 @@
  *
  * You should have received a copy of the GNU General Public License
- * along with ALMOS-MKH.; if not, write to the Free Software Foundation,
+ * along with ALMOS-MKH; if not, write to the Free Software Foundation,
  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
@@ -42 +42 @@
 void mfence();
 vaddr_t rcr2(void);
+uint64_t rcr4(void);
+void lcr4(uint64_t);
+void cpuid(uint32_t eax, uint32_t ecx, uint32_t *desc);
+void tlbflushg();
+void tlbflush();
 
 uint32_t atomic_cas_32(volatile uint32_t *ptr, uint32_t exp, uint32_t new);

trunk/hal/x86_64/core/hal_register.h

@@ -87 +87 @@
 #define         APICBASE_PHYSADDR       0xfffff000      /* physical address */
 
+/*
+ * CPUID
+ */
+/* Fn00000001 %edx features */
+#define CPUID_FPU       0x00000001      /* processor has an FPU? */
+#define CPUID_VME       0x00000002      /* has virtual mode (%cr4's VME/PVI) */
+#define CPUID_DE        0x00000004      /* has debugging extension */
+#define CPUID_PSE       0x00000008      /* has 4MB page size extension */
+#define CPUID_TSC       0x00000010      /* has time stamp counter */
+#define CPUID_MSR       0x00000020      /* has mode specific registers */
+#define CPUID_PAE       0x00000040      /* has phys address extension */
+#define CPUID_MCE       0x00000080      /* has machine check exception */
+#define CPUID_CX8       0x00000100      /* has CMPXCHG8B instruction */
+#define CPUID_APIC      0x00000200      /* has enabled APIC */
+#define CPUID_B10       0x00000400      /* reserved, MTRR */
+#define CPUID_SEP       0x00000800      /* has SYSENTER/SYSEXIT extension */
+#define CPUID_MTRR      0x00001000      /* has memory type range register */
+#define CPUID_PGE       0x00002000      /* has page global extension */
+#define CPUID_MCA       0x00004000      /* has machine check architecture */
+#define CPUID_CMOV      0x00008000      /* has CMOVcc instruction */
+#define CPUID_PAT       0x00010000      /* Page Attribute Table */
+#define CPUID_PSE36     0x00020000      /* 36-bit PSE */
+#define CPUID_PN        0x00040000      /* processor serial number */
+#define CPUID_CFLUSH    0x00080000      /* CLFLUSH insn supported */
+#define CPUID_B20       0x00100000      /* reserved */
+#define CPUID_DS        0x00200000      /* Debug Store */
+#define CPUID_ACPI      0x00400000      /* ACPI performance modulation regs */
+#define CPUID_MMX       0x00800000      /* MMX supported */
+#define CPUID_FXSR      0x01000000      /* fast FP/MMX save/restore */
+#define CPUID_SSE       0x02000000      /* streaming SIMD extensions */
+#define CPUID_SSE2      0x04000000      /* streaming SIMD extensions #2 */
+#define CPUID_SS        0x08000000      /* self-snoop */
+#define CPUID_HTT       0x10000000      /* Hyper-Threading Technology */
+#define CPUID_TM        0x20000000      /* thermal monitor (TCC) */
+#define CPUID_IA64      0x40000000      /* IA-64 architecture */
+#define CPUID_SBF       0x80000000      /* signal break on FERR */
+