Changeset 166 for trunk/hal/x86_64/core/hal_register.h

Timestamp:

Jul 10, 2017, 10:14:27 AM (7 years ago)

Author:

max@…

Message:

identify the cpu features

File:

• trunk/hal/x86_64/core/hal_register.h (modified) (1 diff)

trunk/hal/x86_64/core/hal_register.h

@@ -87 +87 @@
 #define         APICBASE_PHYSADDR       0xfffff000      /* physical address */
 
+/*
+ * CPUID
+ */
+/* Fn00000001 %edx features */
+#define CPUID_FPU       0x00000001      /* processor has an FPU? */
+#define CPUID_VME       0x00000002      /* has virtual mode (%cr4's VME/PVI) */
+#define CPUID_DE        0x00000004      /* has debugging extension */
+#define CPUID_PSE       0x00000008      /* has 4MB page size extension */
+#define CPUID_TSC       0x00000010      /* has time stamp counter */
+#define CPUID_MSR       0x00000020      /* has mode specific registers */
+#define CPUID_PAE       0x00000040      /* has phys address extension */
+#define CPUID_MCE       0x00000080      /* has machine check exception */
+#define CPUID_CX8       0x00000100      /* has CMPXCHG8B instruction */
+#define CPUID_APIC      0x00000200      /* has enabled APIC */
+#define CPUID_B10       0x00000400      /* reserved, MTRR */
+#define CPUID_SEP       0x00000800      /* has SYSENTER/SYSEXIT extension */
+#define CPUID_MTRR      0x00001000      /* has memory type range register */
+#define CPUID_PGE       0x00002000      /* has page global extension */
+#define CPUID_MCA       0x00004000      /* has machine check architecture */
+#define CPUID_CMOV      0x00008000      /* has CMOVcc instruction */
+#define CPUID_PAT       0x00010000      /* Page Attribute Table */
+#define CPUID_PSE36     0x00020000      /* 36-bit PSE */
+#define CPUID_PN        0x00040000      /* processor serial number */
+#define CPUID_CFLUSH    0x00080000      /* CLFLUSH insn supported */
+#define CPUID_B20       0x00100000      /* reserved */
+#define CPUID_DS        0x00200000      /* Debug Store */
+#define CPUID_ACPI      0x00400000      /* ACPI performance modulation regs */
+#define CPUID_MMX       0x00800000      /* MMX supported */
+#define CPUID_FXSR      0x01000000      /* fast FP/MMX save/restore */
+#define CPUID_SSE       0x02000000      /* streaming SIMD extensions */
+#define CPUID_SSE2      0x04000000      /* streaming SIMD extensions #2 */
+#define CPUID_SS        0x08000000      /* self-snoop */
+#define CPUID_HTT       0x10000000      /* Hyper-Threading Technology */
+#define CPUID_TM        0x20000000      /* thermal monitor (TCC) */
+#define CPUID_IA64      0x40000000      /* IA-64 architecture */
+#define CPUID_SBF       0x80000000      /* signal break on FERR */
+