Changeset 279 for trunk/hal/tsar_mips32/core/hal_kentry.S
- Timestamp:
- Jul 27, 2017, 12:23:29 AM (7 years ago)
- File:
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- 1 edited
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trunk/hal/tsar_mips32/core/hal_kentry.S (modified) (10 diffs)
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trunk/hal/tsar_mips32/core/hal_kentry.S
r121 r279 1 1 /* 2 * hal_kentry.S - exception/interrupt/syscall kernel entry point for MIPS322 * hal_kentry.S - Interrupt / Exception / Syscall kernel entry point for MIPS32 3 3 * 4 4 * AUthors Ghassan Almaless (2007,2008,2009,2010,2011,2012) … … 30 30 # or syscall for the TSAR_MIPS32 architecture. 31 31 # 32 # - If the core is in user mode: 33 # . we desactivate the MMU. 34 # . we save the context in the uzone of the calling thread descriptor. 35 # . we increment the cores_in_kernel variable. 36 # . we call the relevant exception/interrupt/syscall handler 32 # When we enter the kernel, we test the ststus register: 33 # - If the core is in user mode, we desactivate the MMU, and we save 34 # the core context in the uzone of the calling thread descriptor. 35 # - If the core is already in kernel mode (in case of interrupt), 36 # we save the context in the kernel stack. 37 # - In both cases, we increment the cores_in_kernel variable, 38 # and we call the relevant exception/interrupt/syscall handler 37 39 # 38 # - If the core is already in kernel mode: 39 # . we save the context in the kernel stack 40 # . we call the relevant exception/interrupt/syscall handler 41 # 42 # - In both cases, when the handler returns: 43 # . we restore the context 44 # . we reactivate the MMU ??? TODO 40 # When we exit the kernel after handler execution: 41 # - we restore the core context from the uzone 45 42 #--------------------------------------------------------------------------------- 46 43 47 .section .kentry,"ax",@progbits 48 .extern cpu_do_interrupt 49 .extern cpu_do_exception 50 .extern cpu_do_syscall 51 .extern cpu_kentry 52 .extern cpu_kexit 44 .section .kgiet, "ax", @progbits 45 46 .extern hal_do_interrupt 47 .extern hal_do_exception 48 .extern hal_do_syscall 49 .extern cluster_core_kernel_enter 50 .extern cluster_core_kernel_exit 51 53 52 .org 0x180 54 .ent ke ntry55 .global ke ntry56 .global kentry_load 53 .ent kernel_enter 54 .global kernel_enter 55 57 56 .set noat 58 57 .set noreorder … … 67 66 68 67 #--------------------------------------------------------------------------------- 69 # Kernel Entry point 68 # Kernel Entry point for Interrupt / Exception / Syscall 70 69 #--------------------------------------------------------------------------------- 71 70 72 ke ntry:71 kernel_enter: 73 72 mfc0 $26, $12 # read SR to test user/kernel mode 74 73 andi $26, $26, 0x10 # User Mode bitmask … … 101 100 #--------------------------------------------------------------------------------------- 102 101 # this code is executed when the core is in kernel mode: 103 # - we use an uzone allocated in kernel stack.102 # - we use an uzone dynamically allocated in kernel stack. 104 103 # - we set the MMU off, set the MMU data_paddr extension to local_cxy, 105 104 # and save the CP2_MODE and CP2_DEXT to uzone. … … 141 140 142 141 #-------------------------------------------------------------------------------------- 143 # this code is executed in both modes, with the two following assumptions: 144 # - $27 contains the pointer on uzone to save the cpu registers 142 # This code is executed in both modes, and saves the core context, 143 # with the two following assumptions: 144 # - $27 contains the pointer on uzone to save the core registers 145 145 # - $29 contains the kernel stack pointer 146 146 … … 186 186 sw $17, (UZ_CR*4)($27) # Save CR 187 187 188 srl $3, $18, 5 # put SR in kernel mode, IRQ disabled, clear exl 188 # put SR in kernel mode, IRQ disabled, clear exl 189 srl $3, $18, 5 189 190 sll $3, $3, 5 190 191 mtc0 $3, $12 # Set new SR 191 192 192 andi $1, $17, 0x3F # $1 <= XCODE (from CR)193 194 193 # signal that core enters kernel 195 jal cluster_core_kernel_enter 194 la $1, cluster_core_kernel_enter 195 jal $1 196 196 nop 197 197 198 198 #--------------------------------------------------------------------------------------- 199 # Depending on XCODE (in $1) , call the apropriate handler. The three called 200 # functions take the same two arguments: thread pointer and uzone pointer. 199 # This code call the relevant Interrupt / Exception / Syscall handler, 200 # depending on XCODE in CP0_CR, with the two following assumptions: 201 # - $27 contains the pointer on uzone containing to save the core registers 202 # - $29 contains the kernel stack pointer 203 # The three handlers take the same two arguments: thread pointer and uzone pointer. 204 # The uzone pointer is saved in $19 to be used by kernel_exit. 205 206 mfc0 $17, $13 # $1 <= CR 207 andi $1, $1, 0x3F # $1 <= XCODE 201 208 202 209 mfc0 $4, $4, 2 # $4 <= thread pointer (first arg) 203 210 or $5, $0, $27 # $5 <= uzone pointer (second arg) 204 or $19, $0, $27 # $19 <= &uzone (for ke ntry_exit)211 or $19, $0, $27 # $19 <= &uzone (for kernel_exit) 205 212 206 213 ori $8, $0, 0x20 # $8 <= cause syscall … … 215 222 addiu $29, $29, -8 # hal_do_exception has 2 args 216 223 addiu $29, $29, 8 217 j ke ntry_exit # jump to kentry_exit224 j kernel_exit # jump to kernel_exit 218 225 nop 219 226 … … 223 230 addiu $29, $29, -8 # hal_do_syscall has 2 args 224 231 addiu $29, $29, 8 225 j ke ntry_exit # jump to kentry_exit226 or $19, $0, $2232 j kernel_exit # jump to kernel_exit 233 nop 227 234 228 235 cause_int: … … 233 240 234 241 # ----------------------------------------------------------------------------------- 235 # Kentry exit 242 # Kernel exit 243 # The pointer on uzone is supposed to be stored in $19 236 244 # ----------------------------------------------------------------------------------- 237 ke ntry_exit:245 kernel_exit: 238 246 239 247 # signal that core exit kernel 240 jal cluster_core_kernel_exit 248 la $1, cluster_core_kernel_exit 249 jalr $1 250 nop 241 251 242 252 # restore context from uzone … … 286 296 lw $31, (UZ_RA*4)($27) 287 297 288 289 298 lw $26, (UZ_DEXT*4)($27) 290 299 mtc2 $26, $24 # restore CP2_DEXT from uzone 291 300 292 #TODO: optimize 293 lw $26, (UZ_MODE*4)($27) # get saved CP2_MODE from uzone 294 andi $26, $26, 0xc # keep only the TLBs controling bits 295 beq $26, $0, out_mmu_3 # both MSB are 0 (the first two LSB are always set) 296 andi $26, $26, 0x8 297 beq $26, $0, out_mmu_7 # first MSB is 0 (bit 2 is set) 298 299 # Possible value for MMU_MODE 300 # In kernel mode : 0x7/0x3 301 # In user mode : 0xF 302 303 # DP_EXT can either be local or remote 304 # Once these register set we can no longuer 305 # access global data 306 307 out_mmu_F: 308 ori $26, $0, 0xF 309 mtc2 $26, $1 # CP2_MODE <= 0xF 310 j out_kentry 311 nop 312 313 out_mmu_7: 314 ori $26, $0, 0x7 315 mtc2 $26, $1 # CP2_MODE <= 0x7 316 j out_kentry 317 nop 318 319 out_mmu_3: 320 ori $26, $0, 0x3 321 mtc2 $26, $1 # CP2_MODE <= 0x3 322 323 out_kentry: 301 lw $26, (UZ_MODE*4)($27) 302 mtc2 $26, $1 # restore CP2_MODE from uzone 303 324 304 nop 325 305 eret 326 306 327 .end ke ntry307 .end kernel_enter 328 308 .set reorder 329 309 .set at 330 310 331 .ent kentry_load332 kentry_load:333 # theses nops are required to load the eret instruction334 # while we are in virtual mode (processor pipeline) ?335 mtc2 $26, $1 # set MMU MODE336 nop337 nop338 eret339 .end kentry_load340 341 311 #------------------------------------------------------------------------------- 342 312
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