Changeset 296 for trunk/hal/tsar_mips32/core
- Timestamp:
- Jul 31, 2017, 1:59:52 PM (7 years ago)
- Location:
- trunk/hal/tsar_mips32/core
- Files:
-
- 6 edited
-
hal_context.c (modified) (4 diffs)
-
hal_exception.c (modified) (4 diffs)
-
hal_kentry.S (modified) (4 diffs)
-
hal_ppm.c (modified) (3 diffs)
-
hal_remote.c (modified) (10 diffs)
-
hal_special.c (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/hal/tsar_mips32/core/hal_context.c
r151 r296 43 43 44 44 ///////////////////////////////////////////////////////////////////////////////////////// 45 // Th is structure defines the cpu_context for TSAR MIPS32.45 // These structuree defines the cpu_context anf fpu_context for TSAR MIPS32. 46 46 // These registers are saved/restored at each context switch. 47 // WARNING : update the hal_cpu_context_save() and hal_cpu_context_restore() 48 // functions when modifying this structure. 47 // WARNING : update the hal_***_context_save() and hal_***_context_restore() 48 // functions when modifying this structure, and check the two 49 // CONFIG_CPU_CTX_SIZE & CONFIGFPU_CTX_SIZE configuration parameterss. 49 50 ///////////////////////////////////////////////////////////////////////////////////////// 50 51 51 52 typedef struct hal_cpu_context_s 52 53 { 53 uint32_t s0_16; // slot 0 54 uint32_t s1_17; // slot 1 55 uint32_t s2_18; // slot 2 56 uint32_t s3_19; // slot 3 57 uint32_t s4_20; // slot 4 58 uint32_t s5_21; // slot 5 59 uint32_t s6_22; // slot 6 60 uint32_t s7_23; // slot 7 61 uint32_t sp_29; // slot 8 62 uint32_t fp_30; // slot 9 63 uint32_t ra_31; // slot 10 64 uint32_t c0_sr; // slot 11 65 uint32_t c0_th; // slot 12 66 uint32_t c2_ptpr; // slot 13 67 uint32_t c2_mode; // slot 14 54 uint32_t c0_epc; // slot 0 55 uint32_t at_01; // slot 1 56 uint32_t v0_02; // slot 2 57 uint32_t v1_03; // slot 3 58 uint32_t a0_04; // slot 4 59 uint32_t a1_05; // slot 5 60 uint32_t a2_06; // slot 6 61 uint32_t a3_07; // slot 7 62 63 uint32_t t0_08; // slot 8 64 uint32_t t1_09; // slot 9 65 uint32_t t2_10; // slot 10 66 uint32_t t3_11; // slot 11 67 uint32_t t4_12; // slot 12 68 uint32_t t5_13; // slot 13 69 uint32_t t6_14; // slot 14 70 uint32_t t7_15; // slot 15 71 72 uint32_t s0_16; // slot 16 73 uint32_t s1_17; // slot 17 74 uint32_t s2_18; // slot 18 75 uint32_t s3_19; // slot 19 76 uint32_t s4_20; // slot 20 77 uint32_t s5_21; // slot 21 78 uint32_t s6_22; // slot 22 79 uint32_t s7_23; // slot 23 80 81 uint32_t t8_24; // slot 24 82 uint32_t t8_25; // slot 25 83 uint32_t hi_26; // slot 26 84 uint32_t lo_27; // slot 27 85 uint32_t gp_28; // slot 28 86 uint32_t sp_29; // slot 29 87 uint32_t fp_30; // slot 30 88 uint32_t ra_31; // slot 31 89 90 uint32_t c2_ptpr; // slot 32 91 uint32_t c2_mode; // slot 33 92 93 uint32_t c0_sr; // slot 34 94 uint32_t c0_th; // slot 35 68 95 } 69 96 hal_cpu_context_t; … … 79 106 hal_fpu_context_t; 80 107 81 ////////////////////////////////////////////////////////// 82 error_t hal_cpu_context_create( struct thread_s * thread ) 108 109 110 ///////////////////////////////////////////////////////////////////////////////////////// 111 // CPU context access functions 112 ///////////////////////////////////////////////////////////////////////////////////////// 113 114 115 ///////////////////////////////////////////////////////////////////////////////////////// 116 // Seven registers are initialised by this function: 117 // GPR : sp_29 / fp_30 / ra_31 118 // CP0 : c0_sr / c0_th 119 // CP2 : c2_ptpr / c2_mode 120 ///////////////////////////////////////////////////////////////////////////////////////// 121 error_t hal_cpu_context_create( thread_t * thread ) 83 122 { 84 123 kmem_req_t req; … … 127 166 context->c2_mode = c2_mode; 128 167 129 context_dmsg("\n[INFO] %s : exit for thread %x in process %x \n",130 __FUNCTION__ , thread->trdid , thread->process->pid );168 context_dmsg("\n[INFO] %s : exit for thread %x in process %x / ra = %x\n", 169 __FUNCTION__ , thread->trdid , thread->process->pid , context->ra_31 ); 131 170 132 171 return 0; 133 172 } // end hal_cpu_context_create() 173 174 ///////////////////////////////////////////////// 175 void hal_cpu_context_display( thread_t * thread ) 176 { 177 hal_cpu_context_t * ctx = (hal_cpu_context_t *)thread->cpu_context; 178 179 printk("\n*** cpu_context for thread %x in cluster %x / ctx = %x ***\n" 180 " gp_28 = %X sp_29 = %X ra_31 = %X\n" 181 " c0_sr = %X c0_epc = %X c0_th = %X\n" 182 " c2_ptpr = %X c2_mode = %X\n", 183 thread->trdid, local_cxy, ctx, 184 ctx->gp_28 , ctx->sp_29 , ctx->ra_31, 185 ctx->c0_sr , ctx->c0_epc , ctx->c0_th, 186 ctx->c2_ptpr , ctx->c2_mode ); 187 } 188 189 ///////////////////////////////////////////////////////////////////////////////////////// 190 // These registers are saved to CPU context defined by <ctx> argument. 191 // - GPR : all, but (zero, k0, k1), plus (hi, lo) 192 // - CP0 : c0_th , c0_sr 193 // - CP2 : c2_ptpr , C2_mode, C2_epc 194 ///////////////////////////////////////////////////////////////////////////////////////// 195 void hal_cpu_context_save( void * ctx ) 196 { 197 asm volatile( 198 ".set noat \n" 199 ".set noreorder \n" 200 "move $26, $4 \n" /* $26 <= &ctx */ 201 202 "mfc0 $27, $14 \n" 203 "sw $27, 0*4($26) \n" /* save c0_epc to slot 0 */ 204 205 "sw $1, 1*4($26) \n" 206 "sw $2, 2*4($26) \n" 207 "sw $3, 3*4($26) \n" 208 "sw $4, 4*4($26) \n" 209 "sw $5, 5*4($26) \n" 210 "sw $6, 6*4($26) \n" 211 "sw $7, 7*4($26) \n" 212 213 "sw $8, 8*4($26) \n" 214 "sw $9, 9*4($26) \n" 215 "sw $10, 10*4($26) \n" 216 "sw $11, 11*4($26) \n" 217 "sw $12, 12*4($26) \n" 218 "sw $13, 13*4($26) \n" 219 "sw $14, 14*4($26) \n" 220 "sw $15, 15*4($26) \n" 221 222 "sw $16, 16*4($26) \n" 223 "sw $17, 17*4($26) \n" 224 "sw $18, 18*4($26) \n" 225 "sw $19, 19*4($26) \n" 226 "sw $20, 20*4($26) \n" 227 "sw $21, 21*4($26) \n" 228 "sw $22, 22*4($26) \n" 229 "sw $23, 23*4($26) \n" 230 231 "sw $24, 24*4($26) \n" 232 "sw $25, 25*4($26) \n" 233 234 "mfhi $27 \n" 235 "sw $27, 26*4($26) \n" /* save hi to slot 26 */ 236 "mflo $27 \n" 237 "sw $27, 27*4($26) \n" /* save lo to slot 27 */ 238 239 "sw $28, 28*4($26) \n" 240 "sw $29, 29*4($26) \n" 241 "sw $30, 30*4($26) \n" 242 "sw $31, 31*4($26) \n" 243 244 "mfc2 $27, $0 \n" 245 "sw $27, 32*4($26) \n" /* save c2_ptpr to slot 32 */ 246 "mfc2 $27, $1 \n" 247 "sw $27, 33*4($26) \n" /* save c2_mode to slot 33 */ 248 249 "mfc0 $27, $12 \n" 250 "sw $27, 34*4($26) \n" /* save c0_sr to slot 34 */ 251 "mfc0 $27, $4, 2 \n" 252 "sw $27, 35*4($26) \n" /* save c0_th to slot 35 */ 253 254 "sync \n" 255 256 "move $4, $27 \n" 257 "jal hal_cpu_context_display \n" /* display context */ 258 "nop \n" 259 260 ".set reorder \n" 261 ".set at \n" 262 : : : "$26" , "$27" , "memory" ); 263 } 264 265 ///////////////////////////////////////////////////////////////////////////////////////// 266 // These registers are restored from cpu context defined by <ctx> argument: 267 // - GPR : all, but (zero, k0, k1), plus (hi, lo) 268 // - CP0 : c0_th , c0_sr 269 // - CP2 : c2_ptpr , C2_mode 270 ///////////////////////////////////////////////////////////////////////////////////////// 271 void hal_cpu_context_restore( void * ctx ) 272 { 273 asm volatile( 274 ".set noat \n" 275 ".set noreorder \n" 276 "move $26, $4 \n" /* $26 <= &ctx */ 277 278 "lw $4, 35*4($26) \n" 279 "jal hal_cpu_context_display \n" /* display context */ 280 "nop \n" 281 282 "lw $27, 0*4($26) \n" 283 "mtc0 $27, $14 \n" /* restore C0_epc from slot 0 */ 284 285 "lw $1, 1*4($26) \n" 286 "lw $2, 2*4($26) \n" 287 "lw $3, 3*4($26) \n" 288 "lw $4, 4*4($26) \n" 289 "lw $5, 5*4($26) \n" 290 "lw $6, 6*4($26) \n" 291 "lw $7, 7*4($26) \n" 292 293 "lw $8, 8*4($26) \n" 294 "lw $9, 9*4($26) \n" 295 "lw $10, 10*4($26) \n" 296 "lw $11, 11*4($26) \n" 297 "lw $12, 12*4($26) \n" 298 "lw $13, 13*4($26) \n" 299 "lw $14, 14*4($26) \n" 300 "lw $15, 15*4($26) \n" 301 302 "lw $16, 16*4($26) \n" 303 "lw $17, 17*4($26) \n" 304 "lw $18, 18*4($26) \n" 305 "lw $19, 19*4($26) \n" 306 "lw $20, 20*4($26) \n" 307 "lw $21, 21*4($26) \n" 308 "lw $22, 22*4($26) \n" 309 "lw $23, 23*4($26) \n" 310 311 "lw $24, 24*4($26) \n" 312 "lw $25, 25*4($26) \n" 313 314 "lw $27, 26*4($26) \n" 315 "mthi $27 \n" /* restore hi from slot 26 */ 316 "lw $27, 27*4($26) \n" 317 "mtlo $27 \n" /* restote lo from slot 27 */ 318 319 "lw $28, 28*4($26) \n" 320 "lw $29, 29*4($26) \n" 321 "lw $30, 30*4($26) \n" 322 "lw $31, 31*4($26) \n" 323 324 "lw $27, 32*4($26) \n" 325 "mtc2 $27, $0 \n" /* restore c2_ptpr from slot 32 */ 326 "lw $27, 33*4($26) \n" 327 "mtc2 $27, $1 \n" /* restore c2_mode from slot 33 */ 328 329 "lw $27, 34*4($26) \n" 330 "mtc0 $27, $12 \n" /* restore c0_sr from slot 34 */ 331 "lw $27, 35*4($26) \n" 332 "mtc0 $27, $4, 2 \n" /* restore co_th from slot 35 */ 333 334 ".set reorder \n" 335 ".set at \n" 336 : : : "$26" , "$27" ); 337 } 134 338 135 339 ///////////////////////////////////////////// … … 226 430 } // end hal_fpu_context_destroy() 227 431 228 ////////////////////////////////////////////// 229 void hal_cpu_context_save( thread_t * thread ) 230 { 231 uint32_t ctx = (uint32_t)thread->cpu_context; 232 233 asm volatile( 234 ".set noreorder \n" 235 "sw $16, 0*4(%0) \n" /* save s0 to slot 0 */ 236 "sw $17, 1*4(%0) \n" /* save s1 to slot 1 */ 237 "sw $18, 2*4(%0) \n" /* save s2 to slot 2 */ 238 "sw $19, 3*4(%0) \n" /* save s3 to slot 3 */ 239 "sw $20, 4*4(%0) \n" /* save s4 to slot 4 */ 240 "sw $21, 5*4(%0) \n" /* save s5 to slot 5 */ 241 "sw $22, 6*4(%0) \n" /* save s6 to slot 6 */ 242 "sw $23, 7*4(%0) \n" /* save s7 to slot 7 */ 243 "sw $29, 8*4(%0) \n" /* save sp to slot 8 */ 244 "sw $30, 9*4(%0) \n" /* save fp to slot 9 */ 245 "sw $31, 10*4(%0) \n" /* save ra to slot 10 */ 246 "mfc0 $26, $4, 2 \n" /* get c0_th from CP0 */ 247 "sw $26, 12*4(%0) \n" /* save c0_th to slot 12 */ 248 "mfc2 $26, $0 \n" /* get c2_ptpr from CP2 */ 249 "sw $26, 13*4(%0) \n" /* save c2_ptpr to slot 13 */ 250 "mfc2 $26, $1 \n" /* get c2_mod from CP2 */ 251 "sw $26, 14*4(%0) \n" /* save c2_mode to slot 14 */ 252 "sync \n" 253 ".set reorder \n" 254 : : "r"( ctx ) : "$26" , "memory" ); 255 } 256 257 ///////////////////////////////////////////////// 258 void hal_cpu_context_restore( thread_t * thread ) 259 { 260 uint32_t ctx = (uint32_t)thread->cpu_context; 261 262 asm volatile( 263 ".set noreorder \n" 264 "nop \n" 265 "lw $16, 0*4(%0) \n" /* restore s0_16 */ 266 "lw $17, 1*4(%0) \n" /* restore s1_17 */ 267 "lw $18, 2*4(%0) \n" /* restore s2_18 */ 268 "lw $19, 3*4(%0) \n" /* restore s3_19 */ 269 "lw $20, 4*4(%0) \n" /* restore s4_20 */ 270 "lw $21, 5*4(%0) \n" /* restore s5_21 */ 271 "lw $22, 6*4(%0) \n" /* restore s6_22 */ 272 "lw $23, 7*4(%0) \n" /* restore s7_23 */ 273 "lw $29, 8*4(%0) \n" /* restore sp_29 */ 274 "lw $30, 9*4(%0) \n" /* restore fp_30 */ 275 "lw $31, 10*4(%0) \n" /* restore ra_31 */ 276 "lw $26, 12*4(%0) \n" /* get c0_th from slot 12 */ 277 "mtc0 $26, $4, 2 \n" /* restore c0_th */ 278 "lw $26, 13*4(%0) \n" /* get c2_ptpr from slot 13 */ 279 "mtc2 $26, $0 \n" /* restore c2_ptpr */ 280 "lw $26, 14*4(%0) \n" /* get c2_mode from slot 14 */ 281 "mtc2 $26, $1 \n" /* restore c2_mode */ 282 ".set reorder \n" 283 : : "r"(ctx) 284 : "$16","$17","$18","$19","$20","$21","$22","$23","$26","$29","$30","$31" ); 285 } 286 287 ////////////////////////////////////////////// 432 ///////////////////////////////////////////////////////////////////////////////////////// 433 // These registers are initialised: 434 // - GPR : sp_29 , fp_30 , a0 435 // - CP0 : c0_sr , c0_epc , c0_th 436 // - CP2 : C2_ptpr , c2_mode 437 // TODO Quand cette fonction est-elle appelée? [AG] 438 ///////////////////////////////////////////////////////////////////////////////////////// 288 439 void hal_cpu_context_load( thread_t * thread ) 289 440 { -
trunk/hal/tsar_mips32/core/hal_exception.c
r101 r296 49 49 typedef enum 50 50 { 51 XCODE_ADEL = 4, // Illegal address for data load52 XCODE_ADES = 5, // Illegal address for data store53 XCODE_IBE = 6, // Instruction MMU exception (can be NON-FATAL)54 XCODE_DBE = 7, // Data MMU exception (can be NON-FATAL)55 XCODE_RI = 10,// Reserved instruction exception56 XCODE_CPU = 11,// Coprocessor unusable exception (can be NON-FATAl)57 XCODE_OVR = 12// Arithmetic Overflow exception51 XCODE_ADEL = 0x4, // Illegal address for data load 52 XCODE_ADES = 0x5, // Illegal address for data store 53 XCODE_IBE = 0x6, // Instruction MMU exception (can be NON-FATAL) 54 XCODE_DBE = 0x7, // Data MMU exception (can be NON-FATAL) 55 XCODE_RI = 0xA, // Reserved instruction exception 56 XCODE_CPU = 0xB, // Coprocessor unusable exception (can be NON-FATAl) 57 XCODE_OVR = 0xC, // Arithmetic Overflow exception 58 58 } 59 59 xcode_values_t; … … 105 105 case XCODE_RI: // user fatal error 106 106 { 107 printk("\n[ERROR] in thread %x / arithmetic overflow\n",107 printk("\n[ERROR] in thread %x / Illegal Codop\n", 108 108 this->trdid ); 109 109 error = EXCP_USER_ERROR; … … 123 123 default: 124 124 { 125 printk("\n[PANIC] in %s for thread %x / illegal XCODE value \n",126 __FUNCTION__ , this->trdid );125 printk("\n[PANIC] in %s for thread %x / illegal XCODE value = %x\n", 126 __FUNCTION__ , this->trdid , excCode ); 127 127 error = EXCP_USER_ERROR; 128 128 } … … 149 149 remote_spinlock_lock( XPTR( LOCAL_CLUSTER->io_cxy , &exception_lock ) ); 150 150 151 // dump core registers values 151 if( this->type == THREAD_USER ) 152 printk("\n================= USER ERROR =======================================\n"); 153 else 154 printk("\n================= KERNEL PANIC =====================================\n"); 152 155 153 printk("\n====================================================================\n"); 154 printk(" thread %x / process %x / core %x / cycle %d\n", 155 this->trdid , this->process->pid , this->core->gid , hal_get_cycles() ); 156 printk(" thread type = %s / trdid = %x / pid %x / core[%x,%d]\n" 157 " local locks = %d / remote locks = %d / blocked_vector = %X\n\n", 158 thread_type_str(this->type), this->trdid, this->process->pid, local_cxy, 159 this->core->lid, this->local_locks, this->remote_locks, this->blocked ); 156 160 157 printk(" - Processor State:\n"); 158 159 printk(" CR: %x\tEPC: %x\tSR: %x\tSP: %x\n", 161 printk("CR %X EPC %X SR %X SP %X\n", 160 162 regs_tbl[UZ_CR], regs_tbl[UZ_EPC], regs_tbl[UZ_SR], regs_tbl[UZ_SP]); 161 163 162 printk(" at_1 %x\tv0_2 %x\t\tv1_3 %x\ta0_4 %x\ta1_5 %x\n",164 printk("at_1 %X v0_2 %X v1_3 %X a0_4 %X a1_5 %X\n", 163 165 regs_tbl[UZ_AT], regs_tbl[UZ_V0], regs_tbl[UZ_V1], regs_tbl[UZ_A0], regs_tbl[UZ_A1]); 164 166 165 printk(" a2_6 %x\t\ta3_7 %x\tt0_8 %x\tt1_9 %x\tt2_10 %x\n",167 printk("a2_6 %X a3_7 %X t0_8 %X t1_9 %X t2_10 %X\n", 166 168 regs_tbl[UZ_A2],regs_tbl[UZ_A3],regs_tbl[UZ_T0],regs_tbl[UZ_T1],regs_tbl[UZ_T2]); 167 169 168 printk(" t3_11 %x\tt4_12 %x\t\tt5_13 %x\tt6_14 %x\tt7_15 %x\n",170 printk("t3_11 %X t4_12 %X t5_13 %X t6_14 %X t7_15 %X\n", 169 171 regs_tbl[UZ_T3],regs_tbl[UZ_T4],regs_tbl[UZ_T5],regs_tbl[UZ_T6],regs_tbl[UZ_T7]); 170 172 171 printk(" t8_24 %x\t\tt9_25 %x\tgp_28 %x\tc0_hi %x\tc0_lo %x\n",173 printk("t8_24 %X t9_25 %X gp_28 %X c0_hi %X c0_lo %X\n", 172 174 regs_tbl[UZ_T8],regs_tbl[UZ_T9],regs_tbl[UZ_GP],regs_tbl[UZ_HI],regs_tbl[UZ_LO]); 173 175 174 printk(" s0_16 %x\ts1_17 %x\ts2_18 %x\ts3_19 %x\ts4_20 %x\n",176 printk("s0_16 %X s1_17 %X s2_18 %X s3_19 %X s4_20 %X\n", 175 177 regs_tbl[UZ_S0],regs_tbl[UZ_S1],regs_tbl[UZ_S2],regs_tbl[UZ_S3],regs_tbl[UZ_S4]); 176 178 177 printk(" s5_21 %x\ts6_22 %x\t\ts7_23 %x\ts8_30 %x\tra_31 %x\n\n",179 printk("s5_21 %X s6_22 %X s7_23 %X s8_30 %X ra_31 %X\n", 178 180 regs_tbl[UZ_S5],regs_tbl[UZ_S6],regs_tbl[UZ_S7],regs_tbl[UZ_S8],regs_tbl[UZ_RA]); 179 180 printk(" - Thread State: %x\n"181 " type = %s / local_locks = %d / remote_locks = %d / blocked = %x\n",182 thread_type_str( this->type ), this->local_locks, this->remote_locks,183 this->blocked );184 181 185 182 // release the exception_lock -
trunk/hal/tsar_mips32/core/hal_kentry.S
r279 r296 30 30 # or syscall for the TSAR_MIPS32 architecture. 31 31 # 32 # When we enter the kernel, we test the st stus register:32 # When we enter the kernel, we test the status register: 33 33 # - If the core is in user mode, we desactivate the MMU, and we save 34 34 # the core context in the uzone of the calling thread descriptor. … … 42 42 #--------------------------------------------------------------------------------- 43 43 44 .section .k giet, "ax", @progbits44 .section .kentry, "ax", @progbits 45 45 46 46 .extern hal_do_interrupt … … 204 204 # The uzone pointer is saved in $19 to be used by kernel_exit. 205 205 206 mfc0 $17, $13 # $1 <= CR207 andi $1 , $1, 0x3F # $1<= XCODE206 mfc0 $17, $13 # $17 <= CR 207 andi $17, $17, 0x3F # $17 <= XCODE 208 208 209 209 mfc0 $4, $4, 2 # $4 <= thread pointer (first arg) … … 212 212 213 213 ori $8, $0, 0x20 # $8 <= cause syscall 214 beq $8, $1 , cause_sys215 nop 216 beq $1 , $0, cause_int214 beq $8, $17, cause_sys # go to syscall handler 215 nop 216 beq $17, $0, cause_int # go to interrupt handler 217 217 nop 218 218 -
trunk/hal/tsar_mips32/core/hal_ppm.c
r279 r296 35 35 36 36 ////////////////////////////////////////////////////////////////////////////////////////// 37 // This file contains the TSAR specific code for cores registers, 38 // and for physical memory allocators initialisation in a given cluster. 39 37 40 // For The TSAR architecture, the kernel pointers are identity mapped: 38 41 // - the 32 bits PTR value is identical to the 32 bits LPA value, 39 42 // - the 64 bits XPTR value is identical to the 64 bits PADDR value. 40 // The pages_tbl[] is mapped in first free page after kernel code. 43 // This hal_ppm_init() function initializes the pages_tbl[] array used by the generic 44 // kmem memory allocator in the local cluster. This array starts in first free page 45 // after kernel code, as defined by the 'offset' field in boot_info. 46 // 47 // For the TSAR architecture the MIP32 EBASE register defining the kernel entry point 48 // fot Interrupts, Exceptions and Syscalls, has to be redefined. 41 49 ////////////////////////////////////////////////////////////////////////////////////////// 42 50 … … 49 57 uint32_t pages_nr = info->pages_nr; 50 58 uint32_t pages_tbl_offset = info->pages_offset; 51 uint32_t rsvd_nr = info->rsvd_nr;52 59 53 60 // get pointer on local Physical Page Manager … … 113 120 // check consistency 114 121 return ppm_assert_order( ppm ); 115 }116 122 123 } // end hal_ppm_init() 124 125 //////////////////////////////////////// 126 void hal_core_init( boot_info_t * info ) 127 { 128 // get relevant info from boot_info structure 129 reg_t kentry_base = info->kentry_base; 130 131 // set CP0_EBASE register 132 hal_set_ebase( kentry_base ); 133 134 } // end hal_core_init() -
trunk/hal/tsar_mips32/core/hal_remote.c
r279 r296 30 30 uint8_t data ) 31 31 { 32 uint32_t save_sr; 33 uint32_t ptr = (uint32_t)GET_PTR( xp ); 34 uint32_t cxy = (uint32_t)GET_CXY( xp ); 35 36 /* TODO improve all hal remote functions to include SR handling in assembly code */ 37 /* as it is done below for hal_remote_sb */ 32 uint32_t ptr = (uint32_t)GET_PTR( xp ); 33 uint32_t cxy = (uint32_t)GET_CXY( xp ); 38 34 39 35 asm volatile( … … 44 40 "mtc0 $13, $12 \n" /* IRQ disabled */ 45 41 46 47 42 "mfc2 $15, $24 \n" /* $15 <= PADDR_EXT */ 48 43 "mtc2 %2, $24 \n" /* PADDR_EXT <= cxy */ … … 61 56 uint32_t data ) 62 57 { 63 uint32_t save_sr; 64 uint32_t ptr = (uint32_t)GET_PTR( xp ); 65 uint32_t cxy = (uint32_t)GET_CXY( xp ); 66 67 hal_disable_irq( &save_sr ); 68 69 asm volatile( "mfc2 $15, $24 \n" /* $15 <= PADDR_EXT */ 70 ".set noreorder \n" 71 "mtc2 %2, $24 \n" /* PADDR_EXT <= cxy */ 72 "sw %0, 0(%1) \n" /* *paddr <= value */ 73 "mtc2 $15, $24 \n" /* PADDR_EXT <= $15 */ 58 uint32_t ptr = (uint32_t)GET_PTR( xp ); 59 uint32_t cxy = (uint32_t)GET_CXY( xp ); 60 61 asm volatile( 62 ".set noreorder \n" 63 "mfc0 $14, $12 \n" /* $14 <= CP0_SR */ 64 "srl $13, $14, 1 \n" 65 "sll $13, $13, 1 \n" /* $13 <= SR masked */ 66 "mtc0 $13, $12 \n" /* IRQ disabled */ 67 68 "mfc2 $15, $24 \n" /* $15 <= PADDR_EXT */ 69 "mtc2 %2, $24 \n" /* PADDR_EXT <= cxy */ 70 "sw %0, 0(%1) \n" /* *paddr <= value */ 71 "mtc2 $15, $24 \n" /* PADDR_EXT <= $15 */ 72 73 "mtc0 $14, $12 \n" /* SR restored */ 74 74 75 "sync \n" 75 76 ".set reorder \n" 76 : : "r" (data), "r" (ptr), "r" (cxy) : "$15" ); 77 78 hal_restore_irq( save_sr ); 79 77 : : "r" (data), "r" (ptr), "r" (cxy) : "$13", "$14", "$15" ); 80 78 } 81 79 … … 84 82 uint64_t data ) 85 83 { 86 uint32_t save_sr;87 84 uint32_t ptr = (uint32_t)GET_PTR( xp ); 88 85 uint32_t cxy = (uint32_t)GET_CXY( xp ); … … 91 88 uint32_t data_msb = (uint32_t)(data>>32); 92 89 93 hal_disable_irq( &save_sr ); 94 95 asm volatile( 96 ".set noreorder \n" 97 "mfc2 $15, $24 \n" /* $15 <= PADDR_EXT */ 98 "mtc2 %3, $24 \n" /* PADDR_EXT <= cxy */ 99 "sw %0, 0(%2) \n" /* *paddr <= lsb */ 100 "sw %1, 4(%2) \n" /* *(paddr+4) <= msb */ 101 "mtc2 $15, $24 \n" /* PADDR_EXT <= $15 */ 90 asm volatile( 91 ".set noreorder \n" 92 "mfc0 $14, $12 \n" /* $14 <= CP0_SR */ 93 "srl $13, $14, 1 \n" 94 "sll $13, $13, 1 \n" /* $13 <= SR masked */ 95 "mtc0 $13, $12 \n" /* IRQ disabled */ 96 97 "mfc2 $15, $24 \n" /* $15 <= PADDR_EXT */ 98 "mtc2 %3, $24 \n" /* PADDR_EXT <= cxy */ 99 "sw %0, 0(%2) \n" /* *paddr <= lsb */ 100 "sw %1, 4(%2) \n" /* *(paddr+4) <= msb */ 101 "mtc2 $15, $24 \n" /* PADDR_EXT <= $15 */ 102 103 "mtc0 $14, $12 \n" /* SR restored */ 104 102 105 "sync \n" 103 106 ".set reorder \n" 104 : : "r" (data_lsb), "r" (data_msb), "r" (ptr), "r" (cxy) : "$15" ); 105 106 hal_restore_irq( save_sr ); 107 107 : : "r" (data_lsb), "r" (data_msb), "r" (ptr), "r" (cxy) : "$13", "$14", "$15" ); 108 108 } 109 109 … … 118 118 uint8_t hal_remote_lb( xptr_t xp ) 119 119 { 120 uint32_t save_sr;121 120 char data; 122 121 uint32_t ptr = (uint32_t)GET_PTR( xp ); 123 122 uint32_t cxy = (uint32_t)GET_CXY( xp ); 124 123 125 hal_disable_irq( &save_sr ); 126 127 asm volatile( 128 ".set noreorder \n" 124 asm volatile( 125 ".set noreorder \n" 126 "mfc0 $14, $12 \n" /* $14 <= CP0_SR */ 127 "srl $13, $14, 1 \n" 128 "sll $13, $13, 1 \n" /* $13 <= SR masked */ 129 "mtc0 $13, $12 \n" /* IRQ disabled */ 130 129 131 "mfc2 $15, $24 \n" /* $15 <= PADDR_EXT */ 130 132 "mtc2 %2, $24 \n" /* PADDR_EXT <= cxy */ 131 133 "lb %0, 0(%1) \n" /* data <= *paddr */ 132 134 "mtc2 $15, $24 \n" /* PADDR_EXT <= $15 */ 133 ".set reorder \n" 134 : "=r" (data) : "r" (ptr), "r" (cxy) : "$15" );135 136 hal_restore_irq( save_sr);135 136 "mtc0 $14, $12 \n" /* SR restored */ 137 ".set reorder \n" 138 : "=r" (data) : "r" (ptr), "r" (cxy) : "$13", "$14", "$15" ); 137 139 138 140 return ( data ); … … 142 144 uint32_t hal_remote_lw( xptr_t xp ) 143 145 { 144 uint32_t save_sr;145 146 uint32_t data; 146 147 uint32_t ptr = (uint32_t)GET_PTR( xp ); 147 148 uint32_t cxy = (uint32_t)GET_CXY( xp ); 148 149 149 hal_disable_irq( &save_sr ); 150 151 asm volatile( 152 ".set noreorder \n" 150 asm volatile( 151 ".set noreorder \n" 152 "mfc0 $14, $12 \n" /* $14 <= CP0_SR */ 153 "srl $13, $14, 1 \n" 154 "sll $13, $13, 1 \n" /* $13 <= SR masked */ 155 "mtc0 $13, $12 \n" /* IRQ disabled */ 156 153 157 "mfc2 $15, $24 \n" /* $15 <= PADDR_EXT */ 154 158 "mtc2 %2, $24 \n" /* PADDR_EXT <= cxy */ 155 159 "lw %0, 0(%1) \n" /* data <= *paddr */ 156 160 "mtc2 $15, $24 \n" /* PADDR_EXT <= $15 */ 157 ".set reorder \n" 158 : "=r" (data) : "r" (ptr), "r" (cxy) : "$15" );159 160 hal_restore_irq( save_sr);161 162 "mtc0 $14, $12 \n" /* SR restored */ 163 ".set reorder \n" 164 : "=r" (data) : "r" (ptr), "r" (cxy) : "$13", "$14", "$15" ); 161 165 162 166 return ( data ); … … 166 170 uint64_t hal_remote_lwd( xptr_t xp ) 167 171 { 168 uint32_t save_sr;169 172 uint32_t data_lsb; 170 173 uint32_t data_msb; … … 172 175 uint32_t cxy = (uint32_t)GET_CXY( xp ); 173 176 174 hal_disable_irq( &save_sr ); 175 176 asm volatile( 177 ".set noreorder \n" 177 asm volatile( 178 ".set noreorder \n" 179 "mfc0 $14, $12 \n" /* $14 <= CP0_SR */ 180 "srl $13, $14, 1 \n" 181 "sll $13, $13, 1 \n" /* $13 <= SR masked */ 182 "mtc0 $13, $12 \n" /* IRQ disabled */ 183 178 184 "mfc2 $15, $24 \n" /* $15 <= PADDR_EXT */ 179 185 "mtc2 %3, $24 \n" /* PADDR_EXT <= cxy */ … … 181 187 "lw %1, 4(%2) \n" /* data_msb <= *paddr+4 */ 182 188 "mtc2 $15, $24 \n" /* PADDR_EXT <= $15 */ 183 ".set reorder \n" 184 : "=r" (data_lsb), "=r"(data_msb) : "r" (ptr), "r" (cxy) : "$15" );185 186 hal_restore_irq( save_sr);189 190 "mtc0 $14, $12 \n" /* SR restored */ 191 ".set reorder \n" 192 : "=r" (data_lsb), "=r"(data_msb) : "r" (ptr), "r" (cxy) : "$13", "$14", "$15" ); 187 193 188 194 return ( (((uint64_t)data_msb)<<32) + (((uint64_t)data_lsb)) ); -
trunk/hal/tsar_mips32/core/hal_special.c
r279 r296 48 48 } 49 49 50 ///////////////////////////// ///51 inline cycle_t hal_time_stamp()52 { 53 cycle_t count;50 ///////////////////////////// 51 inline reg_t hal_time_stamp() 52 { 53 reg_t count; 54 54 55 55 asm volatile ("mfc0 %0, $9" : "=&r" (count)); … … 61 61 inline reg_t hal_get_sr() 62 62 { 63 reg ister uint32_t sr;63 reg_t sr; 64 64 65 65 asm volatile ("mfc0 %0, $12" : "=&r" (sr));
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