Changeset 32 for trunk/hal/x86_64/hal_boot.S
- Timestamp:
- Jun 21, 2017, 11:34:09 AM (7 years ago)
- File:
-
- 1 edited
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trunk/hal/x86_64/hal_boot.S
r29 r32 24 24 #define x86_ASM 25 25 #include <hal_boot.h> 26 #include <hal_multiboot.h> 26 27 #include <hal_register.h> 27 28 #include <hal_segmentation.h> … … 181 182 /* Warm boot */ 182 183 movw $0x1234,0x472 184 cld 183 185 184 186 /* Make sure it is a multiboot-compliant bootloader. */ 185 // cmpl $MULTIBOOT_INFO_MAGIC,%eax 186 // jne boot_panic 187 cmpl $MULTIBOOT_INFO_MAGIC,%eax 188 je 1f 189 ret /* what to do? */ 190 1: 187 191 188 192 movl $RELOC(tmpstk),%esp … … 192 196 popfl 193 197 198 /* 199 * Copy the various multiboot structures 200 */ 201 movl %ebx,%esi /* src */ 202 movl $RELOC(mb_info),%edi /* dst */ 203 movl $MULTIBOOT_INFO_SIZE,%ecx /* len */ 204 rep 205 movsb /* copy esi -> edi */ 206 207 testl $MULTIBOOT_INFO_HAS_LOADER_NAME,MB_MI_FLAGS(%ebx) 208 jz 1f 209 movl MB_MI_LOADER_NAME(%ebx),%esi /* src */ 210 movl $RELOC(mb_loader_name),%edi /* dst */ 211 copy_loop: 212 cmpb $0,(%esi) 213 je copy_end 214 movsb /* copy esi -> edi */ 215 jmp copy_loop 216 copy_end: 217 movsb /* copy esi -> edi */ 218 1: 219 220 testl $MULTIBOOT_INFO_HAS_MMAP,MB_MI_FLAGS(%ebx) 221 jz 1f 222 movl MB_MI_MMAP_ADDR(%ebx),%esi /* src */ 223 movl $RELOC(mb_mmap),%edi /* dst */ 224 movl MB_MI_MMAP_LENGTH(%ebx),%ecx /* len */ 225 226 rep 227 movsb /* copy esi -> edi */ 228 1: 229 194 230 /* 195 231 * There are four levels of pages in amd64: PML4 -> PDP -> PD -> PT. They will … … 197 233 * 198 234 * Virtual address space of the kernel: 199 * +---------------+------------+-----------------------------------+--- 200 * | TEXT + RODATA | DATA + BSS | L4 -> PROC0 STK -> L3 -> L2 -> L1 | 201 * +---------------+------------+-----------------------------------+--- 202 * (1) 203 * 204 * ---+-------------+ 205 * | ISA I/O MEM | 206 * ---+-------------+ 207 * (2) 235 * +---------------+------+-----------------------------------+-------------+ 236 * | TEXT + RODATA | DATA | L4 -> PROC0 STK -> L3 -> L2 -> L1 | ISA I/O MEM | 237 * +---------------+------+-----------------------------------+-------------+ 238 * (1) (2) 208 239 * 209 240 * PROC0 STK is obviously not linked as a page level. It just happens to be … … 215 246 * 216 247 * Important note: the kernel segments are properly 4k-aligned 217 * (see kern .ldscript), so there's no need to enforce alignment.248 * (see kernel_x86.ld), so there's no need to enforce alignment. 218 249 */ 219 250 … … 430 461 killkpt 431 462 432 /* Relocate atdevbase. */463 /* Save the virtual address of ISA I/O MEM. */ 433 464 movq $(TABLESIZE+KERNBASE),%rdx 434 465 addq %rsi,%rdx
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